1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
79 // X86 is weird. It always uses i8 for shift amounts and setcc results.
80 setBooleanContents(ZeroOrOneBooleanContent);
81 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
82 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
84 // For 64-bit, since we have so many registers, use the ILP scheduler.
85 // For 32-bit, use the register pressure specific scheduling.
86 // For Atom, always use ILP scheduling.
87 if (Subtarget->isAtom())
88 setSchedulingPreference(Sched::ILP);
89 else if (Subtarget->is64Bit())
90 setSchedulingPreference(Sched::ILP);
92 setSchedulingPreference(Sched::RegPressure);
93 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
94 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
96 // Bypass expensive divides on Atom when compiling with O2.
97 if (TM.getOptLevel() >= CodeGenOpt::Default) {
98 if (Subtarget->hasSlowDivide32())
99 addBypassSlowDiv(32, 8);
100 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
101 addBypassSlowDiv(64, 16);
104 if (Subtarget->isTargetKnownWindowsMSVC()) {
105 // Setup Windows compiler runtime calls.
106 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
107 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
108 setLibcallName(RTLIB::SREM_I64, "_allrem");
109 setLibcallName(RTLIB::UREM_I64, "_aullrem");
110 setLibcallName(RTLIB::MUL_I64, "_allmul");
111 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
112 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
118 if (Subtarget->isTargetDarwin()) {
119 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
120 setUseUnderscoreSetJmp(false);
121 setUseUnderscoreLongJmp(false);
122 } else if (Subtarget->isTargetWindowsGNU()) {
123 // MS runtime is weird: it exports _setjmp, but longjmp!
124 setUseUnderscoreSetJmp(true);
125 setUseUnderscoreLongJmp(false);
127 setUseUnderscoreSetJmp(true);
128 setUseUnderscoreLongJmp(true);
131 // Set up the register classes.
132 addRegisterClass(MVT::i8, &X86::GR8RegClass);
133 addRegisterClass(MVT::i16, &X86::GR16RegClass);
134 addRegisterClass(MVT::i32, &X86::GR32RegClass);
135 if (Subtarget->is64Bit())
136 addRegisterClass(MVT::i64, &X86::GR64RegClass);
138 for (MVT VT : MVT::integer_valuetypes())
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
141 // We don't accept any truncstore of integer registers.
142 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
143 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
145 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
146 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
147 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
149 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
151 // SETOEQ and SETUNE require checking two conditions.
152 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
153 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
155 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
159 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
161 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
162 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
165 if (Subtarget->is64Bit()) {
166 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
167 // f32/f64 are legal, f80 is custom.
168 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
172 } else if (!Subtarget->useSoftFloat()) {
173 // We have an algorithm for SSE2->double, and we turn this into a
174 // 64-bit FILD followed by conditional FADD for other targets.
175 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
176 // We have an algorithm for SSE2, and we turn this into a 64-bit
177 // FILD or VCVTUSI2SS/SD for other targets.
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
181 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
183 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
186 if (!Subtarget->useSoftFloat()) {
187 // SSE has no i16 to fp conversion, only i32
188 if (X86ScalarSSEf32) {
189 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
190 // f32 and f64 cases are Legal, f80 case is not
191 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
193 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
201 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
202 // are Legal, f80 is custom lowered.
203 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
204 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
206 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
208 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
209 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
211 if (X86ScalarSSEf32) {
212 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
213 // f32 and f64 cases are Legal, f80 case is not
214 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
216 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
220 // Handle FP_TO_UINT by promoting the destination to a larger signed
222 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
226 if (Subtarget->is64Bit()) {
227 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
228 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
229 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
235 } else if (!Subtarget->useSoftFloat()) {
236 // Since AVX is a superset of SSE3, only check for SSE here.
237 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
238 // Expand FP_TO_UINT into a select.
239 // FIXME: We would like to use a Custom expander here eventually to do
240 // the optimal thing for SSE vs. the default expansion in the legalizer.
241 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
243 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
244 // With SSE3 we can use fisttpll to convert to a signed i64; without
245 // SSE, we're stuck with a fistpll.
246 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
248 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
251 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
252 if (!X86ScalarSSEf64) {
253 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
254 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
255 if (Subtarget->is64Bit()) {
256 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
257 // Without SSE, i64->f64 goes through memory.
258 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
262 // Scalar integer divide and remainder are lowered to use operations that
263 // produce two results, to match the available instructions. This exposes
264 // the two-result form to trivial CSE, which is able to combine x/y and x%y
265 // into a single instruction.
267 // Scalar integer multiply-high is also lowered to use two-result
268 // operations, to match the available instructions. However, plain multiply
269 // (low) operations are left as Legal, as there are single-result
270 // instructions for this in x86. Using the two-result multiply instructions
271 // when both high and low results are needed must be arranged by dagcombine.
272 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
273 setOperationAction(ISD::MULHS, VT, Expand);
274 setOperationAction(ISD::MULHU, VT, Expand);
275 setOperationAction(ISD::SDIV, VT, Expand);
276 setOperationAction(ISD::UDIV, VT, Expand);
277 setOperationAction(ISD::SREM, VT, Expand);
278 setOperationAction(ISD::UREM, VT, Expand);
280 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
281 setOperationAction(ISD::ADDC, VT, Custom);
282 setOperationAction(ISD::ADDE, VT, Custom);
283 setOperationAction(ISD::SUBC, VT, Custom);
284 setOperationAction(ISD::SUBE, VT, Custom);
287 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
288 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
289 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
290 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
291 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
292 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
293 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
296 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
297 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
303 if (Subtarget->is64Bit())
304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
308 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
310 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
311 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
312 // is. We should promote the value to 64-bits to solve this.
313 // This is what the CRT headers do - `fmodf` is an inline header
314 // function casting to f64 and calling `fmod`.
315 setOperationAction(ISD::FREM , MVT::f32 , Promote);
317 setOperationAction(ISD::FREM , MVT::f32 , Expand);
320 setOperationAction(ISD::FREM , MVT::f64 , Expand);
321 setOperationAction(ISD::FREM , MVT::f80 , Expand);
322 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
324 // Promote the i8 variants and force them on up to i32 which has a shorter
326 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
327 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
330 if (Subtarget->hasBMI()) {
331 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
333 if (Subtarget->is64Bit())
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
336 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
337 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
338 if (Subtarget->is64Bit())
339 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
342 if (Subtarget->hasLZCNT()) {
343 // When promoting the i8 variants, force them to i32 for a shorter
345 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
346 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
351 if (Subtarget->is64Bit())
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
354 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
355 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
356 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
360 if (Subtarget->is64Bit()) {
361 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
362 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
366 // Special handling for half-precision floating point conversions.
367 // If we don't have F16C support, then lower half float conversions
368 // into library calls.
369 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
370 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
371 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
374 // There's never any support for operations beyond MVT::f32.
375 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
376 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
381 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
384 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
387 if (Subtarget->hasPOPCNT()) {
388 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
390 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
391 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
392 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
397 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
399 if (!Subtarget->hasMOVBE())
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
422 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
423 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
424 // support continuation, user-level threading, and etc.. As a result, no
425 // other SjLj exception interfaces are implemented and please don't build
426 // your own exception handling based on them.
427 // LLVM/Clang supports zero-cost DWARF exception handling.
428 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
429 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
432 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
433 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
434 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
435 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
436 if (Subtarget->is64Bit())
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
438 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
439 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
440 if (Subtarget->is64Bit()) {
441 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
442 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
443 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
444 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
445 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
447 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
448 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
453 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
454 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
457 if (Subtarget->hasSSE1())
458 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
460 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
462 // Expand certain atomics
463 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
464 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
465 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
466 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
469 if (Subtarget->hasCmpxchg16b()) {
470 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
473 // FIXME - use subtarget debug flags
474 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
475 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
476 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
479 if (Subtarget->isTarget64BitLP64()) {
480 setExceptionPointerRegister(X86::RAX);
481 setExceptionSelectorRegister(X86::RDX);
483 setExceptionPointerRegister(X86::EAX);
484 setExceptionSelectorRegister(X86::EDX);
486 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
487 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
489 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
490 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
492 setOperationAction(ISD::TRAP, MVT::Other, Legal);
493 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
495 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
496 setOperationAction(ISD::VASTART , MVT::Other, Custom);
497 setOperationAction(ISD::VAEND , MVT::Other, Expand);
498 if (Subtarget->is64Bit()) {
499 setOperationAction(ISD::VAARG , MVT::Other, Custom);
500 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
502 // TargetInfo::CharPtrBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Expand);
504 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
516 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!Subtarget->useSoftFloat()) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!Subtarget->useSoftFloat()) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
750 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
751 // split/scalarized right now.
752 if (VT.getVectorElementType() == MVT::f16)
753 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
757 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
758 // with -msoft-float, disable use of MMX as well.
759 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
760 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
761 // No operations on x86mmx supported, everything uses intrinsics.
764 // MMX-sized vectors (other than x86mmx) are expected to be expanded
765 // into smaller operations.
766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
767 setOperationAction(ISD::MULHS, MMXTy, Expand);
768 setOperationAction(ISD::AND, MMXTy, Expand);
769 setOperationAction(ISD::OR, MMXTy, Expand);
770 setOperationAction(ISD::XOR, MMXTy, Expand);
771 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
772 setOperationAction(ISD::SELECT, MMXTy, Expand);
773 setOperationAction(ISD::BITCAST, MMXTy, Expand);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
777 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
778 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
780 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
781 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
782 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
789 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
790 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
796 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
797 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
799 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
800 // registers cannot be used even for integer operations.
801 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
802 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
804 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
806 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
807 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
809 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
810 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
811 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
813 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
814 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
815 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
816 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
818 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
819 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
820 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
821 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
822 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
823 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
824 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
825 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
827 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
828 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
830 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
832 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
833 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
835 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
836 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
837 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
838 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
841 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
851 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
852 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
853 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
854 // ISD::CTTZ v2i64 - scalarization is faster.
855 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
858 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
860 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
861 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
900 setOperationAction(ISD::AND, VT, Promote);
901 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
902 setOperationAction(ISD::OR, VT, Promote);
903 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
904 setOperationAction(ISD::XOR, VT, Promote);
905 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
906 setOperationAction(ISD::LOAD, VT, Promote);
907 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
908 setOperationAction(ISD::SELECT, VT, Promote);
909 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
912 // Custom lower v2i64 and v2f64 selects.
913 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
914 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
915 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
916 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
918 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
919 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
923 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
924 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
925 // As there is no 64-bit GPR available, we need build a special custom
926 // sequence to convert from v2i32 to v2f32.
927 if (!Subtarget->is64Bit())
928 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
930 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
931 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
933 for (MVT VT : MVT::fp_vector_valuetypes())
934 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
937 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
938 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
941 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
942 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
943 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
944 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
945 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
946 setOperationAction(ISD::FRINT, RoundedTy, Legal);
947 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
950 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
951 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
952 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
953 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
959 // FIXME: Do we need to handle scalar-to-vector here?
960 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
962 // We directly match byte blends in the backend as they match the VSELECT
964 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
966 // SSE41 brings specific instructions for doing vector sign extend even in
967 // cases where we don't have SRA.
968 for (MVT VT : MVT::integer_vector_valuetypes()) {
969 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
970 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
974 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
983 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
989 // i8 and i16 vectors are custom because the source register and source
990 // source memory operand types are not the same width. f32 vectors are
991 // custom since the immediate controlling the insert encodes additional
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
998 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // FIXME: these should be Legal, but that's only for the case where
1004 // the index is constant. For now custom expand to deal with that.
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1011 if (Subtarget->hasSSE2()) {
1012 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1013 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1016 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1017 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1019 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1022 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1023 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1025 // In the customized shift lowering, the legal cases in AVX2 will be
1027 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1028 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1031 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1033 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1034 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1037 if (Subtarget->hasXOP()) {
1038 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1040 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1041 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1042 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1048 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1049 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1050 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1051 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1052 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1053 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1056 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1058 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1060 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1063 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1071 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1073 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1084 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1086 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1087 // even though v8i16 is a legal type.
1088 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1089 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1090 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1092 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1093 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1094 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1096 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1097 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1099 for (MVT VT : MVT::fp_vector_valuetypes())
1100 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1102 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1108 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1109 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1111 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1117 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1120 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1122 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1123 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1124 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1125 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1126 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1127 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1128 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1129 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1130 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1131 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1133 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1134 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1135 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1136 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1138 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1147 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1148 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1151 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1152 setOperationAction(ISD::FMA, MVT::f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::f64, Legal);
1156 if (Subtarget->hasInt256()) {
1157 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1158 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1159 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1160 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1163 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1164 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1165 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1167 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1168 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1169 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1170 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1173 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1174 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1177 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1179 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1180 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1181 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1182 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1184 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1185 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1186 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1187 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1188 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1190 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1191 // when we have a 256bit-wide blend with immediate.
1192 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1194 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1195 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1196 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1197 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1198 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1202 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1203 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1204 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1205 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1209 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1210 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1211 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1212 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1214 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1215 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1216 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1219 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1220 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1221 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1226 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1227 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1228 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1229 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1233 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1234 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1235 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1238 // In the customized shift lowering, the legal cases in AVX2 will be
1240 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1247 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1249 // Custom lower several nodes for 256-bit types.
1250 for (MVT VT : MVT::vector_valuetypes()) {
1251 if (VT.getScalarSizeInBits() >= 32) {
1252 setOperationAction(ISD::MLOAD, VT, Legal);
1253 setOperationAction(ISD::MSTORE, VT, Legal);
1255 // Extract subvector is special because the value type
1256 // (result) is 128-bit but the source is 256-bit wide.
1257 if (VT.is128BitVector()) {
1258 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1260 // Do not attempt to custom lower other non-256-bit vectors
1261 if (!VT.is256BitVector())
1264 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1265 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1266 setOperationAction(ISD::VSELECT, VT, Custom);
1267 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1268 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1269 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1270 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1271 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1274 if (Subtarget->hasInt256())
1275 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1277 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1278 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1279 setOperationAction(ISD::AND, VT, Promote);
1280 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1281 setOperationAction(ISD::OR, VT, Promote);
1282 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1283 setOperationAction(ISD::XOR, VT, Promote);
1284 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1285 setOperationAction(ISD::LOAD, VT, Promote);
1286 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1287 setOperationAction(ISD::SELECT, VT, Promote);
1288 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1292 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1293 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1294 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1295 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1296 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1298 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1299 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1300 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1302 for (MVT VT : MVT::fp_vector_valuetypes())
1303 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1306 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1307 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1308 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1318 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1319 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1320 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1321 setOperationAction(ISD::XOR, MVT::i1, Legal);
1322 setOperationAction(ISD::OR, MVT::i1, Legal);
1323 setOperationAction(ISD::AND, MVT::i1, Legal);
1324 setOperationAction(ISD::SUB, MVT::i1, Custom);
1325 setOperationAction(ISD::ADD, MVT::i1, Custom);
1326 setOperationAction(ISD::MUL, MVT::i1, Custom);
1327 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1328 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1329 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1330 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1331 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1333 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1340 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1342 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1344 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1346 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1350 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1351 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1354 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1359 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1360 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1361 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1363 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1364 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1366 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1367 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1368 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1369 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1370 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1371 if (Subtarget->hasVLX()){
1372 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1373 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1374 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1375 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1376 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1379 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1380 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1381 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1382 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1384 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1385 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1386 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1387 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1388 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1389 if (Subtarget->hasDQI()) {
1390 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1393 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1394 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1395 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1396 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1397 if (Subtarget->hasVLX()) {
1398 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1399 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1400 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1419 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1420 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1421 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1422 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1423 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1424 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1425 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1428 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1430 if (Subtarget->hasDQI()) {
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1434 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1436 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1437 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1438 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1451 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1452 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1454 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1470 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1471 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1472 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1508 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1509 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1510 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1516 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1519 if (Subtarget->hasVLX()) {
1520 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1521 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1535 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1536 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1537 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1543 } // Subtarget->hasCDI()
1545 if (Subtarget->hasDQI()) {
1546 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1547 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1548 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1550 // Custom lower several nodes.
1551 for (MVT VT : MVT::vector_valuetypes()) {
1552 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1554 setOperationAction(ISD::AND, VT, Legal);
1555 setOperationAction(ISD::OR, VT, Legal);
1556 setOperationAction(ISD::XOR, VT, Legal);
1558 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1559 setOperationAction(ISD::MGATHER, VT, Custom);
1560 setOperationAction(ISD::MSCATTER, VT, Custom);
1562 // Extract subvector is special because the value type
1563 // (result) is 256/128-bit but the source is 512-bit wide.
1564 if (VT.is128BitVector() || VT.is256BitVector()) {
1565 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1567 if (VT.getVectorElementType() == MVT::i1)
1568 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1570 // Do not attempt to custom lower other non-512-bit vectors
1571 if (!VT.is512BitVector())
1574 if (EltSize >= 32) {
1575 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1576 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1577 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1578 setOperationAction(ISD::VSELECT, VT, Legal);
1579 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1580 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1581 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1582 setOperationAction(ISD::MLOAD, VT, Legal);
1583 setOperationAction(ISD::MSTORE, VT, Legal);
1586 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1587 setOperationAction(ISD::SELECT, VT, Promote);
1588 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1592 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1593 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1594 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1596 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1597 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1599 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1602 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1603 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1606 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1607 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1608 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1609 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1610 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1611 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1612 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1613 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1614 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1615 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1616 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1617 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1618 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1619 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1620 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1621 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1622 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1623 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1624 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1625 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1630 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1631 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1632 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1633 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1634 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1635 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1636 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1637 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1638 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1643 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1644 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1645 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1646 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1651 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1652 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1653 if (Subtarget->hasVLX())
1654 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1656 if (Subtarget->hasCDI()) {
1657 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1658 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1659 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1660 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1663 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1664 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1665 setOperationAction(ISD::VSELECT, VT, Legal);
1669 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1670 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1671 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1673 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1674 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1675 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1676 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1677 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1678 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1679 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1680 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1681 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1686 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1687 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1688 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1689 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1690 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1691 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1692 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1693 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1695 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1699 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1705 // We want to custom lower some of our intrinsics.
1706 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1707 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1708 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1709 if (!Subtarget->is64Bit())
1710 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1712 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1713 // handle type legalization for these operations here.
1715 // FIXME: We really should do custom legalization for addition and
1716 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1717 // than generic legalization for 64-bit multiplication-with-overflow, though.
1718 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1719 if (VT == MVT::i64 && !Subtarget->is64Bit())
1721 // Add/Sub/Mul with overflow operations are custom lowered.
1722 setOperationAction(ISD::SADDO, VT, Custom);
1723 setOperationAction(ISD::UADDO, VT, Custom);
1724 setOperationAction(ISD::SSUBO, VT, Custom);
1725 setOperationAction(ISD::USUBO, VT, Custom);
1726 setOperationAction(ISD::SMULO, VT, Custom);
1727 setOperationAction(ISD::UMULO, VT, Custom);
1730 if (!Subtarget->is64Bit()) {
1731 // These libcalls are not available in 32-bit.
1732 setLibcallName(RTLIB::SHL_I128, nullptr);
1733 setLibcallName(RTLIB::SRL_I128, nullptr);
1734 setLibcallName(RTLIB::SRA_I128, nullptr);
1737 // Combine sin / cos into one node or libcall if possible.
1738 if (Subtarget->hasSinCos()) {
1739 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1740 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1741 if (Subtarget->isTargetDarwin()) {
1742 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1743 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1744 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1745 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1749 if (Subtarget->isTargetWin64()) {
1750 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1751 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1752 setOperationAction(ISD::SREM, MVT::i128, Custom);
1753 setOperationAction(ISD::UREM, MVT::i128, Custom);
1754 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1758 // We have target-specific dag combine patterns for the following nodes:
1759 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1760 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1761 setTargetDAGCombine(ISD::BITCAST);
1762 setTargetDAGCombine(ISD::VSELECT);
1763 setTargetDAGCombine(ISD::SELECT);
1764 setTargetDAGCombine(ISD::SHL);
1765 setTargetDAGCombine(ISD::SRA);
1766 setTargetDAGCombine(ISD::SRL);
1767 setTargetDAGCombine(ISD::OR);
1768 setTargetDAGCombine(ISD::AND);
1769 setTargetDAGCombine(ISD::ADD);
1770 setTargetDAGCombine(ISD::FADD);
1771 setTargetDAGCombine(ISD::FSUB);
1772 setTargetDAGCombine(ISD::FMA);
1773 setTargetDAGCombine(ISD::SUB);
1774 setTargetDAGCombine(ISD::LOAD);
1775 setTargetDAGCombine(ISD::MLOAD);
1776 setTargetDAGCombine(ISD::STORE);
1777 setTargetDAGCombine(ISD::MSTORE);
1778 setTargetDAGCombine(ISD::ZERO_EXTEND);
1779 setTargetDAGCombine(ISD::ANY_EXTEND);
1780 setTargetDAGCombine(ISD::SIGN_EXTEND);
1781 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1782 setTargetDAGCombine(ISD::SINT_TO_FP);
1783 setTargetDAGCombine(ISD::UINT_TO_FP);
1784 setTargetDAGCombine(ISD::SETCC);
1785 setTargetDAGCombine(ISD::BUILD_VECTOR);
1786 setTargetDAGCombine(ISD::MUL);
1787 setTargetDAGCombine(ISD::XOR);
1789 computeRegisterProperties(Subtarget->getRegisterInfo());
1791 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1792 MaxStoresPerMemsetOptSize = 8;
1793 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1794 MaxStoresPerMemcpyOptSize = 4;
1795 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1796 MaxStoresPerMemmoveOptSize = 4;
1797 setPrefLoopAlignment(4); // 2^4 bytes.
1799 // A predictable cmov does not hurt on an in-order CPU.
1800 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1801 PredictableSelectIsExpensive = !Subtarget->isAtom();
1802 EnableExtLdPromotion = true;
1803 setPrefFunctionAlignment(4); // 2^4 bytes.
1805 verifyIntrinsicTables();
1808 // This has so far only been implemented for 64-bit MachO.
1809 bool X86TargetLowering::useLoadStackGuardNode() const {
1810 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1813 TargetLoweringBase::LegalizeTypeAction
1814 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1815 if (ExperimentalVectorWideningLegalization &&
1816 VT.getVectorNumElements() != 1 &&
1817 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1818 return TypeWidenVector;
1820 return TargetLoweringBase::getPreferredVectorAction(VT);
1823 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1826 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1828 if (VT.isSimple()) {
1829 MVT VVT = VT.getSimpleVT();
1830 const unsigned NumElts = VVT.getVectorNumElements();
1831 const MVT EltVT = VVT.getVectorElementType();
1832 if (VVT.is512BitVector()) {
1833 if (Subtarget->hasAVX512())
1834 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1835 EltVT == MVT::f32 || EltVT == MVT::f64)
1837 case 8: return MVT::v8i1;
1838 case 16: return MVT::v16i1;
1840 if (Subtarget->hasBWI())
1841 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1843 case 32: return MVT::v32i1;
1844 case 64: return MVT::v64i1;
1848 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1849 if (Subtarget->hasVLX())
1850 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851 EltVT == MVT::f32 || EltVT == MVT::f64)
1853 case 2: return MVT::v2i1;
1854 case 4: return MVT::v4i1;
1855 case 8: return MVT::v8i1;
1857 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1858 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1860 case 8: return MVT::v8i1;
1861 case 16: return MVT::v16i1;
1862 case 32: return MVT::v32i1;
1867 return VT.changeVectorElementTypeToInteger();
1870 /// Helper for getByValTypeAlignment to determine
1871 /// the desired ByVal argument alignment.
1872 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1875 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1876 if (VTy->getBitWidth() == 128)
1878 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1879 unsigned EltAlign = 0;
1880 getMaxByValAlign(ATy->getElementType(), EltAlign);
1881 if (EltAlign > MaxAlign)
1882 MaxAlign = EltAlign;
1883 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1884 for (auto *EltTy : STy->elements()) {
1885 unsigned EltAlign = 0;
1886 getMaxByValAlign(EltTy, EltAlign);
1887 if (EltAlign > MaxAlign)
1888 MaxAlign = EltAlign;
1895 /// Return the desired alignment for ByVal aggregate
1896 /// function arguments in the caller parameter area. For X86, aggregates
1897 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1898 /// are at 4-byte boundaries.
1899 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1900 const DataLayout &DL) const {
1901 if (Subtarget->is64Bit()) {
1902 // Max of 8 and alignment of type.
1903 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1910 if (Subtarget->hasSSE1())
1911 getMaxByValAlign(Ty, Align);
1915 /// Returns the target specific optimal type for load
1916 /// and store operations as a result of memset, memcpy, and memmove
1917 /// lowering. If DstAlign is zero that means it's safe to destination
1918 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1919 /// means there isn't a need to check it against alignment requirement,
1920 /// probably because the source does not need to be loaded. If 'IsMemset' is
1921 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1922 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1923 /// source is constant so it does not need to be loaded.
1924 /// It returns EVT::Other if the type should be determined using generic
1925 /// target-independent logic.
1927 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1928 unsigned DstAlign, unsigned SrcAlign,
1929 bool IsMemset, bool ZeroMemset,
1931 MachineFunction &MF) const {
1932 const Function *F = MF.getFunction();
1933 if ((!IsMemset || ZeroMemset) &&
1934 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1936 (!Subtarget->isUnalignedMem16Slow() ||
1937 ((DstAlign == 0 || DstAlign >= 16) &&
1938 (SrcAlign == 0 || SrcAlign >= 16)))) {
1940 // FIXME: Check if unaligned 32-byte accesses are slow.
1941 if (Subtarget->hasInt256())
1943 if (Subtarget->hasFp256())
1946 if (Subtarget->hasSSE2())
1948 if (Subtarget->hasSSE1())
1950 } else if (!MemcpyStrSrc && Size >= 8 &&
1951 !Subtarget->is64Bit() &&
1952 Subtarget->hasSSE2()) {
1953 // Do not use f64 to lower memcpy if source is string constant. It's
1954 // better to use i32 to avoid the loads.
1958 // This is a compromise. If we reach here, unaligned accesses may be slow on
1959 // this target. However, creating smaller, aligned accesses could be even
1960 // slower and would certainly be a lot more code.
1961 if (Subtarget->is64Bit() && Size >= 8)
1966 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1968 return X86ScalarSSEf32;
1969 else if (VT == MVT::f64)
1970 return X86ScalarSSEf64;
1975 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1980 switch (VT.getSizeInBits()) {
1982 // 8-byte and under are always assumed to be fast.
1986 *Fast = !Subtarget->isUnalignedMem16Slow();
1989 *Fast = !Subtarget->isUnalignedMem32Slow();
1991 // TODO: What about AVX-512 (512-bit) accesses?
1994 // Misaligned accesses of any size are always allowed.
1998 /// Return the entry encoding for a jump table in the
1999 /// current function. The returned value is a member of the
2000 /// MachineJumpTableInfo::JTEntryKind enum.
2001 unsigned X86TargetLowering::getJumpTableEncoding() const {
2002 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2004 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2005 Subtarget->isPICStyleGOT())
2006 return MachineJumpTableInfo::EK_Custom32;
2008 // Otherwise, use the normal jump table encoding heuristics.
2009 return TargetLowering::getJumpTableEncoding();
2012 bool X86TargetLowering::useSoftFloat() const {
2013 return Subtarget->useSoftFloat();
2017 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2018 const MachineBasicBlock *MBB,
2019 unsigned uid,MCContext &Ctx) const{
2020 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2021 Subtarget->isPICStyleGOT());
2022 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2024 return MCSymbolRefExpr::create(MBB->getSymbol(),
2025 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2028 /// Returns relocation base for the given PIC jumptable.
2029 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2030 SelectionDAG &DAG) const {
2031 if (!Subtarget->is64Bit())
2032 // This doesn't have SDLoc associated with it, but is not really the
2033 // same as a Register.
2034 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2035 getPointerTy(DAG.getDataLayout()));
2039 /// This returns the relocation base for the given PIC jumptable,
2040 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2041 const MCExpr *X86TargetLowering::
2042 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2043 MCContext &Ctx) const {
2044 // X86-64 uses RIP relative addressing based on the jump table label.
2045 if (Subtarget->isPICStyleRIPRel())
2046 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2048 // Otherwise, the reference is relative to the PIC base.
2049 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2052 std::pair<const TargetRegisterClass *, uint8_t>
2053 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2055 const TargetRegisterClass *RRC = nullptr;
2057 switch (VT.SimpleTy) {
2059 return TargetLowering::findRepresentativeClass(TRI, VT);
2060 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2061 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2064 RRC = &X86::VR64RegClass;
2066 case MVT::f32: case MVT::f64:
2067 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2068 case MVT::v4f32: case MVT::v2f64:
2069 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2071 RRC = &X86::VR128RegClass;
2074 return std::make_pair(RRC, Cost);
2077 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2078 unsigned &Offset) const {
2079 if (!Subtarget->isTargetLinux())
2082 if (Subtarget->is64Bit()) {
2083 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2085 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2097 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2098 if (!Subtarget->isTargetAndroid())
2099 return TargetLowering::getSafeStackPointerLocation(IRB);
2101 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2102 // definition of TLS_SLOT_SAFESTACK in
2103 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2104 unsigned AddressSpace, Offset;
2105 if (Subtarget->is64Bit()) {
2106 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2108 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2118 return ConstantExpr::getIntToPtr(
2119 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2120 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2123 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2124 unsigned DestAS) const {
2125 assert(SrcAS != DestAS && "Expected different address spaces!");
2127 return SrcAS < 256 && DestAS < 256;
2130 //===----------------------------------------------------------------------===//
2131 // Return Value Calling Convention Implementation
2132 //===----------------------------------------------------------------------===//
2134 #include "X86GenCallingConv.inc"
2136 bool X86TargetLowering::CanLowerReturn(
2137 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2138 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2139 SmallVector<CCValAssign, 16> RVLocs;
2140 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2141 return CCInfo.CheckReturn(Outs, RetCC_X86);
2144 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2145 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2150 X86TargetLowering::LowerReturn(SDValue Chain,
2151 CallingConv::ID CallConv, bool isVarArg,
2152 const SmallVectorImpl<ISD::OutputArg> &Outs,
2153 const SmallVectorImpl<SDValue> &OutVals,
2154 SDLoc dl, SelectionDAG &DAG) const {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2160 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2163 SmallVector<SDValue, 6> RetOps;
2164 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2165 // Operand #1 = Bytes To Pop
2166 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2169 // Copy the result values into the output registers.
2170 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2171 CCValAssign &VA = RVLocs[i];
2172 assert(VA.isRegLoc() && "Can only return in registers!");
2173 SDValue ValToCopy = OutVals[i];
2174 EVT ValVT = ValToCopy.getValueType();
2176 // Promote values to the appropriate types.
2177 if (VA.getLocInfo() == CCValAssign::SExt)
2178 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2179 else if (VA.getLocInfo() == CCValAssign::ZExt)
2180 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2181 else if (VA.getLocInfo() == CCValAssign::AExt) {
2182 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2183 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::BCvt)
2188 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2190 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2191 "Unexpected FP-extend for return value.");
2193 // If this is x86-64, and we disabled SSE, we can't return FP values,
2194 // or SSE or MMX vectors.
2195 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2196 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2197 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2198 report_fatal_error("SSE register return with SSE disabled");
2200 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2201 // llvm-gcc has never done it right and no one has noticed, so this
2202 // should be OK for now.
2203 if (ValVT == MVT::f64 &&
2204 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2205 report_fatal_error("SSE2 register return with SSE2 disabled");
2207 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2208 // the RET instruction and handled by the FP Stackifier.
2209 if (VA.getLocReg() == X86::FP0 ||
2210 VA.getLocReg() == X86::FP1) {
2211 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2212 // change the value to the FP stack register class.
2213 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2214 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2215 RetOps.push_back(ValToCopy);
2216 // Don't emit a copytoreg.
2220 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2221 // which is returned in RAX / RDX.
2222 if (Subtarget->is64Bit()) {
2223 if (ValVT == MVT::x86mmx) {
2224 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2225 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2228 // If we don't have SSE2 available, convert to v4f32 so the generated
2229 // register is legal.
2230 if (!Subtarget->hasSSE2())
2231 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2236 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2237 Flag = Chain.getValue(1);
2238 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2241 // All x86 ABIs require that for returning structs by value we copy
2242 // the sret argument into %rax/%eax (depending on ABI) for the return.
2243 // We saved the argument into a virtual register in the entry block,
2244 // so now we copy the value out and into %rax/%eax.
2246 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2247 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2248 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2249 // either case FuncInfo->setSRetReturnReg() will have been called.
2250 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2251 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2252 getPointerTy(MF.getDataLayout()));
2255 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2256 X86::RAX : X86::EAX;
2257 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2258 Flag = Chain.getValue(1);
2260 // RAX/EAX now acts like a return value.
2262 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2265 RetOps[0] = Chain; // Update chain.
2267 // Add the flag if we have it.
2269 RetOps.push_back(Flag);
2271 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2274 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2275 if (N->getNumValues() != 1)
2277 if (!N->hasNUsesOfValue(1, 0))
2280 SDValue TCChain = Chain;
2281 SDNode *Copy = *N->use_begin();
2282 if (Copy->getOpcode() == ISD::CopyToReg) {
2283 // If the copy has a glue operand, we conservatively assume it isn't safe to
2284 // perform a tail call.
2285 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2287 TCChain = Copy->getOperand(0);
2288 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2291 bool HasRet = false;
2292 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2294 if (UI->getOpcode() != X86ISD::RET_FLAG)
2296 // If we are returning more than one value, we can definitely
2297 // not make a tail call see PR19530
2298 if (UI->getNumOperands() > 4)
2300 if (UI->getNumOperands() == 4 &&
2301 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2314 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2315 ISD::NodeType ExtendKind) const {
2317 // TODO: Is this also valid on 32-bit?
2318 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2319 ReturnMVT = MVT::i8;
2321 ReturnMVT = MVT::i32;
2323 EVT MinVT = getRegisterType(Context, ReturnMVT);
2324 return VT.bitsLT(MinVT) ? MinVT : VT;
2327 /// Lower the result values of a call into the
2328 /// appropriate copies out of appropriate physical registers.
2331 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2332 CallingConv::ID CallConv, bool isVarArg,
2333 const SmallVectorImpl<ISD::InputArg> &Ins,
2334 SDLoc dl, SelectionDAG &DAG,
2335 SmallVectorImpl<SDValue> &InVals) const {
2337 // Assign locations to each value returned by this call.
2338 SmallVector<CCValAssign, 16> RVLocs;
2339 bool Is64Bit = Subtarget->is64Bit();
2340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2342 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2344 // Copy all of the result registers out of their specified physreg.
2345 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2346 CCValAssign &VA = RVLocs[i];
2347 EVT CopyVT = VA.getLocVT();
2349 // If this is x86-64, and we disabled SSE, we can't return FP values
2350 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2351 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2352 report_fatal_error("SSE register return with SSE disabled");
2355 // If we prefer to use the value in xmm registers, copy it out as f80 and
2356 // use a truncate to move it from fp stack reg to xmm reg.
2357 bool RoundAfterCopy = false;
2358 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2359 isScalarFPTypeInSSEReg(VA.getValVT())) {
2361 RoundAfterCopy = (CopyVT != VA.getLocVT());
2364 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2365 CopyVT, InFlag).getValue(1);
2366 SDValue Val = Chain.getValue(0);
2369 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2370 // This truncation won't change the value.
2371 DAG.getIntPtrConstant(1, dl));
2373 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2374 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2376 InFlag = Chain.getValue(2);
2377 InVals.push_back(Val);
2383 //===----------------------------------------------------------------------===//
2384 // C & StdCall & Fast Calling Convention implementation
2385 //===----------------------------------------------------------------------===//
2386 // StdCall calling convention seems to be standard for many Windows' API
2387 // routines and around. It differs from C calling convention just a little:
2388 // callee should clean up the stack, not caller. Symbols should be also
2389 // decorated in some fancy way :) It doesn't support any vector arguments.
2390 // For info on fast calling convention see Fast Calling Convention (tail call)
2391 // implementation LowerX86_32FastCCCallTo.
2393 /// CallIsStructReturn - Determines whether a call uses struct return
2395 enum StructReturnType {
2400 static StructReturnType
2401 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2403 return NotStructReturn;
2405 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2406 if (!Flags.isSRet())
2407 return NotStructReturn;
2408 if (Flags.isInReg())
2409 return RegStructReturn;
2410 return StackStructReturn;
2413 /// Determines whether a function uses struct return semantics.
2414 static StructReturnType
2415 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2417 return NotStructReturn;
2419 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2420 if (!Flags.isSRet())
2421 return NotStructReturn;
2422 if (Flags.isInReg())
2423 return RegStructReturn;
2424 return StackStructReturn;
2427 /// Make a copy of an aggregate at address specified by "Src" to address
2428 /// "Dst" with size and alignment information specified by the specific
2429 /// parameter attribute. The copy will be passed as a byval function parameter.
2431 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2432 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2434 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2436 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2437 /*isVolatile*/false, /*AlwaysInline=*/true,
2438 /*isTailCall*/false,
2439 MachinePointerInfo(), MachinePointerInfo());
2442 /// Return true if the calling convention is one that we can guarantee TCO for.
2443 static bool canGuaranteeTCO(CallingConv::ID CC) {
2444 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2445 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2448 /// Return true if we might ever do TCO for calls with this calling convention.
2449 static bool mayTailCallThisCC(CallingConv::ID CC) {
2451 // C calling conventions:
2452 case CallingConv::C:
2453 case CallingConv::X86_64_Win64:
2454 case CallingConv::X86_64_SysV:
2455 // Callee pop conventions:
2456 case CallingConv::X86_ThisCall:
2457 case CallingConv::X86_StdCall:
2458 case CallingConv::X86_VectorCall:
2459 case CallingConv::X86_FastCall:
2462 return canGuaranteeTCO(CC);
2466 /// Return true if the function is being made into a tailcall target by
2467 /// changing its ABI.
2468 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2469 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2472 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2474 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2475 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2479 CallingConv::ID CalleeCC = CS.getCallingConv();
2480 if (!mayTailCallThisCC(CalleeCC))
2487 X86TargetLowering::LowerMemArgument(SDValue Chain,
2488 CallingConv::ID CallConv,
2489 const SmallVectorImpl<ISD::InputArg> &Ins,
2490 SDLoc dl, SelectionDAG &DAG,
2491 const CCValAssign &VA,
2492 MachineFrameInfo *MFI,
2494 // Create the nodes corresponding to a load from this parameter slot.
2495 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2496 bool AlwaysUseMutable = shouldGuaranteeTCO(
2497 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2498 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2501 // If value is passed by pointer we have address passed instead of the value
2503 bool ExtendedInMem = VA.isExtInLoc() &&
2504 VA.getValVT().getScalarType() == MVT::i1;
2506 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2507 ValVT = VA.getLocVT();
2509 ValVT = VA.getValVT();
2511 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2512 // changed with more analysis.
2513 // In case of tail call optimization mark all arguments mutable. Since they
2514 // could be overwritten by lowering of arguments in case of a tail call.
2515 if (Flags.isByVal()) {
2516 unsigned Bytes = Flags.getByValSize();
2517 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2518 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2519 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2521 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2522 VA.getLocMemOffset(), isImmutable);
2523 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2524 SDValue Val = DAG.getLoad(
2525 ValVT, dl, Chain, FIN,
2526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2528 return ExtendedInMem ?
2529 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2533 // FIXME: Get this from tablegen.
2534 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2535 const X86Subtarget *Subtarget) {
2536 assert(Subtarget->is64Bit());
2538 if (Subtarget->isCallingConvWin64(CallConv)) {
2539 static const MCPhysReg GPR64ArgRegsWin64[] = {
2540 X86::RCX, X86::RDX, X86::R8, X86::R9
2542 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2545 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2546 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2548 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2551 // FIXME: Get this from tablegen.
2552 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2553 CallingConv::ID CallConv,
2554 const X86Subtarget *Subtarget) {
2555 assert(Subtarget->is64Bit());
2556 if (Subtarget->isCallingConvWin64(CallConv)) {
2557 // The XMM registers which might contain var arg parameters are shadowed
2558 // in their paired GPR. So we only need to save the GPR to their home
2560 // TODO: __vectorcall will change this.
2564 const Function *Fn = MF.getFunction();
2565 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2566 bool isSoftFloat = Subtarget->useSoftFloat();
2567 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2568 "SSE register cannot be used when SSE is disabled!");
2569 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2570 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2574 static const MCPhysReg XMMArgRegs64Bit[] = {
2575 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2576 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2578 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2581 SDValue X86TargetLowering::LowerFormalArguments(
2582 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2583 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2584 SmallVectorImpl<SDValue> &InVals) const {
2585 MachineFunction &MF = DAG.getMachineFunction();
2586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2587 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2589 const Function* Fn = MF.getFunction();
2590 if (Fn->hasExternalLinkage() &&
2591 Subtarget->isTargetCygMing() &&
2592 Fn->getName() == "main")
2593 FuncInfo->setForceFramePointer(true);
2595 MachineFrameInfo *MFI = MF.getFrameInfo();
2596 bool Is64Bit = Subtarget->is64Bit();
2597 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2599 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2600 "Var args not supported with calling convention fastcc, ghc or hipe");
2602 // Assign locations to all of the incoming arguments.
2603 SmallVector<CCValAssign, 16> ArgLocs;
2604 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2606 // Allocate shadow area for Win64
2608 CCInfo.AllocateStack(32, 8);
2610 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2612 unsigned LastVal = ~0U;
2614 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2615 CCValAssign &VA = ArgLocs[i];
2616 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2618 assert(VA.getValNo() != LastVal &&
2619 "Don't support value assigned to multiple locs yet");
2621 LastVal = VA.getValNo();
2623 if (VA.isRegLoc()) {
2624 EVT RegVT = VA.getLocVT();
2625 const TargetRegisterClass *RC;
2626 if (RegVT == MVT::i32)
2627 RC = &X86::GR32RegClass;
2628 else if (Is64Bit && RegVT == MVT::i64)
2629 RC = &X86::GR64RegClass;
2630 else if (RegVT == MVT::f32)
2631 RC = &X86::FR32RegClass;
2632 else if (RegVT == MVT::f64)
2633 RC = &X86::FR64RegClass;
2634 else if (RegVT.is512BitVector())
2635 RC = &X86::VR512RegClass;
2636 else if (RegVT.is256BitVector())
2637 RC = &X86::VR256RegClass;
2638 else if (RegVT.is128BitVector())
2639 RC = &X86::VR128RegClass;
2640 else if (RegVT == MVT::x86mmx)
2641 RC = &X86::VR64RegClass;
2642 else if (RegVT == MVT::i1)
2643 RC = &X86::VK1RegClass;
2644 else if (RegVT == MVT::v8i1)
2645 RC = &X86::VK8RegClass;
2646 else if (RegVT == MVT::v16i1)
2647 RC = &X86::VK16RegClass;
2648 else if (RegVT == MVT::v32i1)
2649 RC = &X86::VK32RegClass;
2650 else if (RegVT == MVT::v64i1)
2651 RC = &X86::VK64RegClass;
2653 llvm_unreachable("Unknown argument type!");
2655 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2656 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2658 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2659 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2661 if (VA.getLocInfo() == CCValAssign::SExt)
2662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2663 DAG.getValueType(VA.getValVT()));
2664 else if (VA.getLocInfo() == CCValAssign::ZExt)
2665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2666 DAG.getValueType(VA.getValVT()));
2667 else if (VA.getLocInfo() == CCValAssign::BCvt)
2668 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2670 if (VA.isExtInLoc()) {
2671 // Handle MMX values passed in XMM regs.
2672 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2673 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2675 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2678 assert(VA.isMemLoc());
2679 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2682 // If value is passed via pointer - do a load.
2683 if (VA.getLocInfo() == CCValAssign::Indirect)
2684 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2685 MachinePointerInfo(), false, false, false, 0);
2687 InVals.push_back(ArgValue);
2690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2691 // All x86 ABIs require that for returning structs by value we copy the
2692 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2693 // the argument into a virtual register so that we can access it from the
2695 if (Ins[i].Flags.isSRet()) {
2696 unsigned Reg = FuncInfo->getSRetReturnReg();
2698 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2699 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2700 FuncInfo->setSRetReturnReg(Reg);
2702 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2703 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2708 unsigned StackSize = CCInfo.getNextStackOffset();
2709 // Align stack specially for tail calls.
2710 if (shouldGuaranteeTCO(CallConv,
2711 MF.getTarget().Options.GuaranteedTailCallOpt))
2712 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2714 // If the function takes variable number of arguments, make a frame index for
2715 // the start of the first vararg value... for expansion of llvm.va_start. We
2716 // can skip this if there are no va_start calls.
2717 if (MFI->hasVAStart() &&
2718 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2719 CallConv != CallingConv::X86_ThisCall))) {
2720 FuncInfo->setVarArgsFrameIndex(
2721 MFI->CreateFixedObject(1, StackSize, true));
2724 MachineModuleInfo &MMI = MF.getMMI();
2726 // Figure out if XMM registers are in use.
2727 assert(!(Subtarget->useSoftFloat() &&
2728 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2729 "SSE register cannot be used when SSE is disabled!");
2731 // 64-bit calling conventions support varargs and register parameters, so we
2732 // have to do extra work to spill them in the prologue.
2733 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2734 // Find the first unallocated argument registers.
2735 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2736 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2737 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2738 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2739 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2740 "SSE register cannot be used when SSE is disabled!");
2742 // Gather all the live in physical registers.
2743 SmallVector<SDValue, 6> LiveGPRs;
2744 SmallVector<SDValue, 8> LiveXMMRegs;
2746 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2747 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2749 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2751 if (!ArgXMMs.empty()) {
2752 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2753 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2754 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2755 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2756 LiveXMMRegs.push_back(
2757 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2762 // Get to the caller-allocated home save location. Add 8 to account
2763 // for the return address.
2764 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2765 FuncInfo->setRegSaveFrameIndex(
2766 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2767 // Fixup to set vararg frame on shadow area (4 x i64).
2769 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2771 // For X86-64, if there are vararg parameters that are passed via
2772 // registers, then we must store them to their spots on the stack so
2773 // they may be loaded by deferencing the result of va_next.
2774 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2775 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2776 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2777 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2780 // Store the integer parameter registers.
2781 SmallVector<SDValue, 8> MemOps;
2782 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2783 getPointerTy(DAG.getDataLayout()));
2784 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2785 for (SDValue Val : LiveGPRs) {
2786 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2787 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2789 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2790 MachinePointerInfo::getFixedStack(
2791 DAG.getMachineFunction(),
2792 FuncInfo->getRegSaveFrameIndex(), Offset),
2794 MemOps.push_back(Store);
2798 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2799 // Now store the XMM (fp + vector) parameter registers.
2800 SmallVector<SDValue, 12> SaveXMMOps;
2801 SaveXMMOps.push_back(Chain);
2802 SaveXMMOps.push_back(ALVal);
2803 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2804 FuncInfo->getRegSaveFrameIndex(), dl));
2805 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2806 FuncInfo->getVarArgsFPOffset(), dl));
2807 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2809 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2810 MVT::Other, SaveXMMOps));
2813 if (!MemOps.empty())
2814 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2817 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2818 // Find the largest legal vector type.
2819 MVT VecVT = MVT::Other;
2820 // FIXME: Only some x86_32 calling conventions support AVX512.
2821 if (Subtarget->hasAVX512() &&
2822 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2823 CallConv == CallingConv::Intel_OCL_BI)))
2824 VecVT = MVT::v16f32;
2825 else if (Subtarget->hasAVX())
2827 else if (Subtarget->hasSSE2())
2830 // We forward some GPRs and some vector types.
2831 SmallVector<MVT, 2> RegParmTypes;
2832 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2833 RegParmTypes.push_back(IntVT);
2834 if (VecVT != MVT::Other)
2835 RegParmTypes.push_back(VecVT);
2837 // Compute the set of forwarded registers. The rest are scratch.
2838 SmallVectorImpl<ForwardedRegister> &Forwards =
2839 FuncInfo->getForwardedMustTailRegParms();
2840 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2842 // Conservatively forward AL on x86_64, since it might be used for varargs.
2843 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2844 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2845 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2848 // Copy all forwards from physical to virtual registers.
2849 for (ForwardedRegister &F : Forwards) {
2850 // FIXME: Can we use a less constrained schedule?
2851 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2852 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2853 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2857 // Some CCs need callee pop.
2858 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2859 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2860 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2862 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2863 // If this is an sret function, the return should pop the hidden pointer.
2864 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2865 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2866 argsAreStructReturn(Ins) == StackStructReturn)
2867 FuncInfo->setBytesToPopOnReturn(4);
2871 // RegSaveFrameIndex is X86-64 only.
2872 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2873 if (CallConv == CallingConv::X86_FastCall ||
2874 CallConv == CallingConv::X86_ThisCall)
2875 // fastcc functions can't have varargs.
2876 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2879 FuncInfo->setArgumentStackSize(StackSize);
2881 if (MMI.hasWinEHFuncInfo(Fn)) {
2883 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2884 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2885 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2886 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2887 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2888 MachinePointerInfo::getFixedStack(
2889 DAG.getMachineFunction(), UnwindHelpFI),
2890 /*isVolatile=*/true,
2891 /*isNonTemporal=*/false, /*Alignment=*/0);
2899 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2900 SDValue StackPtr, SDValue Arg,
2901 SDLoc dl, SelectionDAG &DAG,
2902 const CCValAssign &VA,
2903 ISD::ArgFlagsTy Flags) const {
2904 unsigned LocMemOffset = VA.getLocMemOffset();
2905 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2906 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2908 if (Flags.isByVal())
2909 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2911 return DAG.getStore(
2912 Chain, dl, Arg, PtrOff,
2913 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2917 /// Emit a load of return address if tail call
2918 /// optimization is performed and it is required.
2920 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2921 SDValue &OutRetAddr, SDValue Chain,
2922 bool IsTailCall, bool Is64Bit,
2923 int FPDiff, SDLoc dl) const {
2924 // Adjust the Return address stack slot.
2925 EVT VT = getPointerTy(DAG.getDataLayout());
2926 OutRetAddr = getReturnAddressFrameIndex(DAG);
2928 // Load the "old" Return address.
2929 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2930 false, false, false, 0);
2931 return SDValue(OutRetAddr.getNode(), 1);
2934 /// Emit a store of the return address if tail call
2935 /// optimization is performed and it is required (FPDiff!=0).
2936 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2937 SDValue Chain, SDValue RetAddrFrIdx,
2938 EVT PtrVT, unsigned SlotSize,
2939 int FPDiff, SDLoc dl) {
2940 // Store the return address to the appropriate stack slot.
2941 if (!FPDiff) return Chain;
2942 // Calculate the new stack slot for the return address.
2943 int NewReturnAddrFI =
2944 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2946 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2947 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2948 MachinePointerInfo::getFixedStack(
2949 DAG.getMachineFunction(), NewReturnAddrFI),
2954 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2955 /// operation of specified width.
2956 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2958 unsigned NumElems = VT.getVectorNumElements();
2959 SmallVector<int, 8> Mask;
2960 Mask.push_back(NumElems);
2961 for (unsigned i = 1; i != NumElems; ++i)
2963 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2967 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2968 SmallVectorImpl<SDValue> &InVals) const {
2969 SelectionDAG &DAG = CLI.DAG;
2971 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2972 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2973 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2974 SDValue Chain = CLI.Chain;
2975 SDValue Callee = CLI.Callee;
2976 CallingConv::ID CallConv = CLI.CallConv;
2977 bool &isTailCall = CLI.IsTailCall;
2978 bool isVarArg = CLI.IsVarArg;
2980 MachineFunction &MF = DAG.getMachineFunction();
2981 bool Is64Bit = Subtarget->is64Bit();
2982 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2983 StructReturnType SR = callIsStructReturn(Outs);
2984 bool IsSibcall = false;
2985 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2986 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2988 if (Attr.getValueAsString() == "true")
2991 if (Subtarget->isPICStyleGOT() &&
2992 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2993 // If we are using a GOT, disable tail calls to external symbols with
2994 // default visibility. Tail calling such a symbol requires using a GOT
2995 // relocation, which forces early binding of the symbol. This breaks code
2996 // that require lazy function symbol resolution. Using musttail or
2997 // GuaranteedTailCallOpt will override this.
2998 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2999 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3000 G->getGlobal()->hasDefaultVisibility()))
3004 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3006 // Force this to be a tail call. The verifier rules are enough to ensure
3007 // that we can lower this successfully without moving the return address
3010 } else if (isTailCall) {
3011 // Check if it's really possible to do a tail call.
3012 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3013 isVarArg, SR != NotStructReturn,
3014 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3015 Outs, OutVals, Ins, DAG);
3017 // Sibcalls are automatically detected tailcalls which do not require
3019 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3026 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3027 "Var args not supported with calling convention fastcc, ghc or hipe");
3029 // Analyze operands of the call, assigning locations to each operand.
3030 SmallVector<CCValAssign, 16> ArgLocs;
3031 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3033 // Allocate shadow area for Win64
3035 CCInfo.AllocateStack(32, 8);
3037 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3039 // Get a count of how many bytes are to be pushed on the stack.
3040 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3042 // This is a sibcall. The memory operands are available in caller's
3043 // own caller's stack.
3045 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3046 canGuaranteeTCO(CallConv))
3047 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3050 if (isTailCall && !IsSibcall && !IsMustTail) {
3051 // Lower arguments at fp - stackoffset + fpdiff.
3052 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3054 FPDiff = NumBytesCallerPushed - NumBytes;
3056 // Set the delta of movement of the returnaddr stackslot.
3057 // But only set if delta is greater than previous delta.
3058 if (FPDiff < X86Info->getTCReturnAddrDelta())
3059 X86Info->setTCReturnAddrDelta(FPDiff);
3062 unsigned NumBytesToPush = NumBytes;
3063 unsigned NumBytesToPop = NumBytes;
3065 // If we have an inalloca argument, all stack space has already been allocated
3066 // for us and be right at the top of the stack. We don't support multiple
3067 // arguments passed in memory when using inalloca.
3068 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3070 if (!ArgLocs.back().isMemLoc())
3071 report_fatal_error("cannot use inalloca attribute on a register "
3073 if (ArgLocs.back().getLocMemOffset() != 0)
3074 report_fatal_error("any parameter with the inalloca attribute must be "
3075 "the only memory argument");
3079 Chain = DAG.getCALLSEQ_START(
3080 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3082 SDValue RetAddrFrIdx;
3083 // Load return address for tail calls.
3084 if (isTailCall && FPDiff)
3085 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3086 Is64Bit, FPDiff, dl);
3088 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3089 SmallVector<SDValue, 8> MemOpChains;
3092 // Walk the register/memloc assignments, inserting copies/loads. In the case
3093 // of tail call optimization arguments are handle later.
3094 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3095 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3096 // Skip inalloca arguments, they have already been written.
3097 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3098 if (Flags.isInAlloca())
3101 CCValAssign &VA = ArgLocs[i];
3102 EVT RegVT = VA.getLocVT();
3103 SDValue Arg = OutVals[i];
3104 bool isByVal = Flags.isByVal();
3106 // Promote the value if needed.
3107 switch (VA.getLocInfo()) {
3108 default: llvm_unreachable("Unknown loc info!");
3109 case CCValAssign::Full: break;
3110 case CCValAssign::SExt:
3111 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3113 case CCValAssign::ZExt:
3114 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3116 case CCValAssign::AExt:
3117 if (Arg.getValueType().isVector() &&
3118 Arg.getValueType().getVectorElementType() == MVT::i1)
3119 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3120 else if (RegVT.is128BitVector()) {
3121 // Special case: passing MMX values in XMM registers.
3122 Arg = DAG.getBitcast(MVT::i64, Arg);
3123 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3124 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3126 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3128 case CCValAssign::BCvt:
3129 Arg = DAG.getBitcast(RegVT, Arg);
3131 case CCValAssign::Indirect: {
3132 // Store the argument.
3133 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3134 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3135 Chain = DAG.getStore(
3136 Chain, dl, Arg, SpillSlot,
3137 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3144 if (VA.isRegLoc()) {
3145 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3146 if (isVarArg && IsWin64) {
3147 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3148 // shadow reg if callee is a varargs function.
3149 unsigned ShadowReg = 0;
3150 switch (VA.getLocReg()) {
3151 case X86::XMM0: ShadowReg = X86::RCX; break;
3152 case X86::XMM1: ShadowReg = X86::RDX; break;
3153 case X86::XMM2: ShadowReg = X86::R8; break;
3154 case X86::XMM3: ShadowReg = X86::R9; break;
3157 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3159 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3160 assert(VA.isMemLoc());
3161 if (!StackPtr.getNode())
3162 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3163 getPointerTy(DAG.getDataLayout()));
3164 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3165 dl, DAG, VA, Flags));
3169 if (!MemOpChains.empty())
3170 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3172 if (Subtarget->isPICStyleGOT()) {
3173 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3176 RegsToPass.push_back(std::make_pair(
3177 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3178 getPointerTy(DAG.getDataLayout()))));
3180 // If we are tail calling and generating PIC/GOT style code load the
3181 // address of the callee into ECX. The value in ecx is used as target of
3182 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3183 // for tail calls on PIC/GOT architectures. Normally we would just put the
3184 // address of GOT into ebx and then call target@PLT. But for tail calls
3185 // ebx would be restored (since ebx is callee saved) before jumping to the
3188 // Note: The actual moving to ECX is done further down.
3189 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3190 if (G && !G->getGlobal()->hasLocalLinkage() &&
3191 G->getGlobal()->hasDefaultVisibility())
3192 Callee = LowerGlobalAddress(Callee, DAG);
3193 else if (isa<ExternalSymbolSDNode>(Callee))
3194 Callee = LowerExternalSymbol(Callee, DAG);
3198 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3199 // From AMD64 ABI document:
3200 // For calls that may call functions that use varargs or stdargs
3201 // (prototype-less calls or calls to functions containing ellipsis (...) in
3202 // the declaration) %al is used as hidden argument to specify the number
3203 // of SSE registers used. The contents of %al do not need to match exactly
3204 // the number of registers, but must be an ubound on the number of SSE
3205 // registers used and is in the range 0 - 8 inclusive.
3207 // Count the number of XMM registers allocated.
3208 static const MCPhysReg XMMArgRegs[] = {
3209 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3210 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3212 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3213 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3214 && "SSE registers cannot be used when SSE is disabled");
3216 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3217 DAG.getConstant(NumXMMRegs, dl,
3221 if (isVarArg && IsMustTail) {
3222 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3223 for (const auto &F : Forwards) {
3224 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3225 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3229 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3230 // don't need this because the eligibility check rejects calls that require
3231 // shuffling arguments passed in memory.
3232 if (!IsSibcall && isTailCall) {
3233 // Force all the incoming stack arguments to be loaded from the stack
3234 // before any new outgoing arguments are stored to the stack, because the
3235 // outgoing stack slots may alias the incoming argument stack slots, and
3236 // the alias isn't otherwise explicit. This is slightly more conservative
3237 // than necessary, because it means that each store effectively depends
3238 // on every argument instead of just those arguments it would clobber.
3239 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3241 SmallVector<SDValue, 8> MemOpChains2;
3244 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3245 CCValAssign &VA = ArgLocs[i];
3248 assert(VA.isMemLoc());
3249 SDValue Arg = OutVals[i];
3250 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3251 // Skip inalloca arguments. They don't require any work.
3252 if (Flags.isInAlloca())
3254 // Create frame index.
3255 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3256 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3257 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3258 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3260 if (Flags.isByVal()) {
3261 // Copy relative to framepointer.
3262 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3263 if (!StackPtr.getNode())
3264 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3265 getPointerTy(DAG.getDataLayout()));
3266 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3269 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3273 // Store relative to framepointer.
3274 MemOpChains2.push_back(DAG.getStore(
3275 ArgChain, dl, Arg, FIN,
3276 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3281 if (!MemOpChains2.empty())
3282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3284 // Store the return address to the appropriate stack slot.
3285 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3286 getPointerTy(DAG.getDataLayout()),
3287 RegInfo->getSlotSize(), FPDiff, dl);
3290 // Build a sequence of copy-to-reg nodes chained together with token chain
3291 // and flag operands which copy the outgoing args into registers.
3293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3294 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3295 RegsToPass[i].second, InFlag);
3296 InFlag = Chain.getValue(1);
3299 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3300 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3301 // In the 64-bit large code model, we have to make all calls
3302 // through a register, since the call instruction's 32-bit
3303 // pc-relative offset may not be large enough to hold the whole
3305 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3306 // If the callee is a GlobalAddress node (quite common, every direct call
3307 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3309 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3311 // We should use extra load for direct calls to dllimported functions in
3313 const GlobalValue *GV = G->getGlobal();
3314 if (!GV->hasDLLImportStorageClass()) {
3315 unsigned char OpFlags = 0;
3316 bool ExtraLoad = false;
3317 unsigned WrapperKind = ISD::DELETED_NODE;
3319 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3320 // external symbols most go through the PLT in PIC mode. If the symbol
3321 // has hidden or protected visibility, or if it is static or local, then
3322 // we don't need to use the PLT - we can directly call it.
3323 if (Subtarget->isTargetELF() &&
3324 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3325 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3326 OpFlags = X86II::MO_PLT;
3327 } else if (Subtarget->isPICStyleStubAny() &&
3328 !GV->isStrongDefinitionForLinker() &&
3329 (!Subtarget->getTargetTriple().isMacOSX() ||
3330 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3331 // PC-relative references to external symbols should go through $stub,
3332 // unless we're building with the leopard linker or later, which
3333 // automatically synthesizes these stubs.
3334 OpFlags = X86II::MO_DARWIN_STUB;
3335 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3336 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3337 // If the function is marked as non-lazy, generate an indirect call
3338 // which loads from the GOT directly. This avoids runtime overhead
3339 // at the cost of eager binding (and one extra byte of encoding).
3340 OpFlags = X86II::MO_GOTPCREL;
3341 WrapperKind = X86ISD::WrapperRIP;
3345 Callee = DAG.getTargetGlobalAddress(
3346 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3348 // Add a wrapper if needed.
3349 if (WrapperKind != ISD::DELETED_NODE)
3350 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3351 getPointerTy(DAG.getDataLayout()), Callee);
3352 // Add extra indirection if needed.
3354 Callee = DAG.getLoad(
3355 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3356 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3359 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3360 unsigned char OpFlags = 0;
3362 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3363 // external symbols should go through the PLT.
3364 if (Subtarget->isTargetELF() &&
3365 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3366 OpFlags = X86II::MO_PLT;
3367 } else if (Subtarget->isPICStyleStubAny() &&
3368 (!Subtarget->getTargetTriple().isMacOSX() ||
3369 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3370 // PC-relative references to external symbols should go through $stub,
3371 // unless we're building with the leopard linker or later, which
3372 // automatically synthesizes these stubs.
3373 OpFlags = X86II::MO_DARWIN_STUB;
3376 Callee = DAG.getTargetExternalSymbol(
3377 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3378 } else if (Subtarget->isTarget64BitILP32() &&
3379 Callee->getValueType(0) == MVT::i32) {
3380 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3381 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3384 // Returns a chain & a flag for retval copy to use.
3385 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3386 SmallVector<SDValue, 8> Ops;
3388 if (!IsSibcall && isTailCall) {
3389 Chain = DAG.getCALLSEQ_END(Chain,
3390 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3391 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3392 InFlag = Chain.getValue(1);
3395 Ops.push_back(Chain);
3396 Ops.push_back(Callee);
3399 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3401 // Add argument registers to the end of the list so that they are known live
3403 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3404 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3405 RegsToPass[i].second.getValueType()));
3407 // Add a register mask operand representing the call-preserved registers.
3408 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3409 assert(Mask && "Missing call preserved mask for calling convention");
3411 // If this is an invoke in a 32-bit function using a funclet-based
3412 // personality, assume the function clobbers all registers. If an exception
3413 // is thrown, the runtime will not restore CSRs.
3414 // FIXME: Model this more precisely so that we can register allocate across
3415 // the normal edge and spill and fill across the exceptional edge.
3416 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3417 const Function *CallerFn = MF.getFunction();
3418 EHPersonality Pers =
3419 CallerFn->hasPersonalityFn()
3420 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3421 : EHPersonality::Unknown;
3422 if (isFuncletEHPersonality(Pers))
3423 Mask = RegInfo->getNoPreservedMask();
3426 Ops.push_back(DAG.getRegisterMask(Mask));
3428 if (InFlag.getNode())
3429 Ops.push_back(InFlag);
3433 //// If this is the first return lowered for this function, add the regs
3434 //// to the liveout set for the function.
3435 // This isn't right, although it's probably harmless on x86; liveouts
3436 // should be computed from returns not tail calls. Consider a void
3437 // function making a tail call to a function returning int.
3438 MF.getFrameInfo()->setHasTailCall();
3439 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3442 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3443 InFlag = Chain.getValue(1);
3445 // Create the CALLSEQ_END node.
3446 unsigned NumBytesForCalleeToPop;
3447 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3448 DAG.getTarget().Options.GuaranteedTailCallOpt))
3449 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3450 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3451 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3452 SR == StackStructReturn)
3453 // If this is a call to a struct-return function, the callee
3454 // pops the hidden struct pointer, so we have to push it back.
3455 // This is common for Darwin/X86, Linux & Mingw32 targets.
3456 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3457 NumBytesForCalleeToPop = 4;
3459 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3461 // Returns a flag for retval copy to use.
3463 Chain = DAG.getCALLSEQ_END(Chain,
3464 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3465 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3468 InFlag = Chain.getValue(1);
3471 // Handle result values, copying them out of physregs into vregs that we
3473 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3474 Ins, dl, DAG, InVals);
3477 //===----------------------------------------------------------------------===//
3478 // Fast Calling Convention (tail call) implementation
3479 //===----------------------------------------------------------------------===//
3481 // Like std call, callee cleans arguments, convention except that ECX is
3482 // reserved for storing the tail called function address. Only 2 registers are
3483 // free for argument passing (inreg). Tail call optimization is performed
3485 // * tailcallopt is enabled
3486 // * caller/callee are fastcc
3487 // On X86_64 architecture with GOT-style position independent code only local
3488 // (within module) calls are supported at the moment.
3489 // To keep the stack aligned according to platform abi the function
3490 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3491 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3492 // If a tail called function callee has more arguments than the caller the
3493 // caller needs to make sure that there is room to move the RETADDR to. This is
3494 // achieved by reserving an area the size of the argument delta right after the
3495 // original RETADDR, but before the saved framepointer or the spilled registers
3496 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3508 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3511 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3512 SelectionDAG& DAG) const {
3513 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3514 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3515 unsigned StackAlignment = TFI.getStackAlignment();
3516 uint64_t AlignMask = StackAlignment - 1;
3517 int64_t Offset = StackSize;
3518 unsigned SlotSize = RegInfo->getSlotSize();
3519 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3520 // Number smaller than 12 so just add the difference.
3521 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3523 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3524 Offset = ((~AlignMask) & Offset) + StackAlignment +
3525 (StackAlignment-SlotSize);
3530 /// Return true if the given stack call argument is already available in the
3531 /// same position (relatively) of the caller's incoming argument stack.
3533 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3534 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3535 const X86InstrInfo *TII) {
3536 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3538 if (Arg.getOpcode() == ISD::CopyFromReg) {
3539 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3540 if (!TargetRegisterInfo::isVirtualRegister(VR))
3542 MachineInstr *Def = MRI->getVRegDef(VR);
3545 if (!Flags.isByVal()) {
3546 if (!TII->isLoadFromStackSlot(Def, FI))
3549 unsigned Opcode = Def->getOpcode();
3550 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3551 Opcode == X86::LEA64_32r) &&
3552 Def->getOperand(1).isFI()) {
3553 FI = Def->getOperand(1).getIndex();
3554 Bytes = Flags.getByValSize();
3558 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3559 if (Flags.isByVal())
3560 // ByVal argument is passed in as a pointer but it's now being
3561 // dereferenced. e.g.
3562 // define @foo(%struct.X* %A) {
3563 // tail call @bar(%struct.X* byval %A)
3566 SDValue Ptr = Ld->getBasePtr();
3567 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3570 FI = FINode->getIndex();
3571 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3572 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3573 FI = FINode->getIndex();
3574 Bytes = Flags.getByValSize();
3578 assert(FI != INT_MAX);
3579 if (!MFI->isFixedObjectIndex(FI))
3581 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3584 /// Check whether the call is eligible for tail call optimization. Targets
3585 /// that want to do tail call optimization should implement this function.
3586 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3587 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3588 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3589 const SmallVectorImpl<ISD::OutputArg> &Outs,
3590 const SmallVectorImpl<SDValue> &OutVals,
3591 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3592 if (!mayTailCallThisCC(CalleeCC))
3595 // If -tailcallopt is specified, make fastcc functions tail-callable.
3596 MachineFunction &MF = DAG.getMachineFunction();
3597 const Function *CallerF = MF.getFunction();
3599 // If the function return type is x86_fp80 and the callee return type is not,
3600 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3601 // perform a tailcall optimization here.
3602 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3605 CallingConv::ID CallerCC = CallerF->getCallingConv();
3606 bool CCMatch = CallerCC == CalleeCC;
3607 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3608 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3610 // Win64 functions have extra shadow space for argument homing. Don't do the
3611 // sibcall if the caller and callee have mismatched expectations for this
3613 if (IsCalleeWin64 != IsCallerWin64)
3616 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3617 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3622 // Look for obvious safe cases to perform tail call optimization that do not
3623 // require ABI changes. This is what gcc calls sibcall.
3625 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3626 // emit a special epilogue.
3627 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3628 if (RegInfo->needsStackRealignment(MF))
3631 // Also avoid sibcall optimization if either caller or callee uses struct
3632 // return semantics.
3633 if (isCalleeStructRet || isCallerStructRet)
3636 // Do not sibcall optimize vararg calls unless all arguments are passed via
3638 if (isVarArg && !Outs.empty()) {
3639 // Optimizing for varargs on Win64 is unlikely to be safe without
3640 // additional testing.
3641 if (IsCalleeWin64 || IsCallerWin64)
3644 SmallVector<CCValAssign, 16> ArgLocs;
3645 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3648 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3649 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3650 if (!ArgLocs[i].isRegLoc())
3654 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3655 // stack. Therefore, if it's not used by the call it is not safe to optimize
3656 // this into a sibcall.
3657 bool Unused = false;
3658 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3665 SmallVector<CCValAssign, 16> RVLocs;
3666 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3668 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3669 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3670 CCValAssign &VA = RVLocs[i];
3671 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3676 // If the calling conventions do not match, then we'd better make sure the
3677 // results are returned in the same way as what the caller expects.
3679 SmallVector<CCValAssign, 16> RVLocs1;
3680 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3682 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3684 SmallVector<CCValAssign, 16> RVLocs2;
3685 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3687 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3689 if (RVLocs1.size() != RVLocs2.size())
3691 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3692 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3694 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3696 if (RVLocs1[i].isRegLoc()) {
3697 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3700 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3706 unsigned StackArgsSize = 0;
3708 // If the callee takes no arguments then go on to check the results of the
3710 if (!Outs.empty()) {
3711 // Check if stack adjustment is needed. For now, do not do this if any
3712 // argument is passed on the stack.
3713 SmallVector<CCValAssign, 16> ArgLocs;
3714 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3717 // Allocate shadow area for Win64
3719 CCInfo.AllocateStack(32, 8);
3721 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3722 StackArgsSize = CCInfo.getNextStackOffset();
3724 if (CCInfo.getNextStackOffset()) {
3725 // Check if the arguments are already laid out in the right way as
3726 // the caller's fixed stack objects.
3727 MachineFrameInfo *MFI = MF.getFrameInfo();
3728 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3729 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3730 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3731 CCValAssign &VA = ArgLocs[i];
3732 SDValue Arg = OutVals[i];
3733 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3734 if (VA.getLocInfo() == CCValAssign::Indirect)
3736 if (!VA.isRegLoc()) {
3737 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3744 // If the tailcall address may be in a register, then make sure it's
3745 // possible to register allocate for it. In 32-bit, the call address can
3746 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3747 // callee-saved registers are restored. These happen to be the same
3748 // registers used to pass 'inreg' arguments so watch out for those.
3749 if (!Subtarget->is64Bit() &&
3750 ((!isa<GlobalAddressSDNode>(Callee) &&
3751 !isa<ExternalSymbolSDNode>(Callee)) ||
3752 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3753 unsigned NumInRegs = 0;
3754 // In PIC we need an extra register to formulate the address computation
3756 unsigned MaxInRegs =
3757 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3759 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3760 CCValAssign &VA = ArgLocs[i];
3763 unsigned Reg = VA.getLocReg();
3766 case X86::EAX: case X86::EDX: case X86::ECX:
3767 if (++NumInRegs == MaxInRegs)
3775 bool CalleeWillPop =
3776 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3777 MF.getTarget().Options.GuaranteedTailCallOpt);
3779 if (unsigned BytesToPop =
3780 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3781 // If we have bytes to pop, the callee must pop them.
3782 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3783 if (!CalleePopMatches)
3785 } else if (CalleeWillPop && StackArgsSize > 0) {
3786 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3794 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3795 const TargetLibraryInfo *libInfo) const {
3796 return X86::createFastISel(funcInfo, libInfo);
3799 //===----------------------------------------------------------------------===//
3800 // Other Lowering Hooks
3801 //===----------------------------------------------------------------------===//
3803 static bool MayFoldLoad(SDValue Op) {
3804 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3807 static bool MayFoldIntoStore(SDValue Op) {
3808 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3811 static bool isTargetShuffle(unsigned Opcode) {
3813 default: return false;
3814 case X86ISD::BLENDI:
3815 case X86ISD::PSHUFB:
3816 case X86ISD::PSHUFD:
3817 case X86ISD::PSHUFHW:
3818 case X86ISD::PSHUFLW:
3820 case X86ISD::PALIGNR:
3821 case X86ISD::MOVLHPS:
3822 case X86ISD::MOVLHPD:
3823 case X86ISD::MOVHLPS:
3824 case X86ISD::MOVLPS:
3825 case X86ISD::MOVLPD:
3826 case X86ISD::MOVSHDUP:
3827 case X86ISD::MOVSLDUP:
3828 case X86ISD::MOVDDUP:
3831 case X86ISD::UNPCKL:
3832 case X86ISD::UNPCKH:
3833 case X86ISD::VPERMILPI:
3834 case X86ISD::VPERM2X128:
3835 case X86ISD::VPERMI:
3836 case X86ISD::VPERMV:
3837 case X86ISD::VPERMV3:
3842 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3843 SDValue V1, unsigned TargetMask,
3844 SelectionDAG &DAG) {
3846 default: llvm_unreachable("Unknown x86 shuffle node");
3847 case X86ISD::PSHUFD:
3848 case X86ISD::PSHUFHW:
3849 case X86ISD::PSHUFLW:
3850 case X86ISD::VPERMILPI:
3851 case X86ISD::VPERMI:
3852 return DAG.getNode(Opc, dl, VT, V1,
3853 DAG.getConstant(TargetMask, dl, MVT::i8));
3857 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3858 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3860 default: llvm_unreachable("Unknown x86 shuffle node");
3861 case X86ISD::MOVLHPS:
3862 case X86ISD::MOVLHPD:
3863 case X86ISD::MOVHLPS:
3864 case X86ISD::MOVLPS:
3865 case X86ISD::MOVLPD:
3868 case X86ISD::UNPCKL:
3869 case X86ISD::UNPCKH:
3870 return DAG.getNode(Opc, dl, VT, V1, V2);
3874 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3875 MachineFunction &MF = DAG.getMachineFunction();
3876 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3877 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3878 int ReturnAddrIndex = FuncInfo->getRAIndex();
3880 if (ReturnAddrIndex == 0) {
3881 // Set up a frame object for the return address.
3882 unsigned SlotSize = RegInfo->getSlotSize();
3883 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3886 FuncInfo->setRAIndex(ReturnAddrIndex);
3889 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3892 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3893 bool hasSymbolicDisplacement) {
3894 // Offset should fit into 32 bit immediate field.
3895 if (!isInt<32>(Offset))
3898 // If we don't have a symbolic displacement - we don't have any extra
3900 if (!hasSymbolicDisplacement)
3903 // FIXME: Some tweaks might be needed for medium code model.
3904 if (M != CodeModel::Small && M != CodeModel::Kernel)
3907 // For small code model we assume that latest object is 16MB before end of 31
3908 // bits boundary. We may also accept pretty large negative constants knowing
3909 // that all objects are in the positive half of address space.
3910 if (M == CodeModel::Small && Offset < 16*1024*1024)
3913 // For kernel code model we know that all object resist in the negative half
3914 // of 32bits address space. We may not accept negative offsets, since they may
3915 // be just off and we may accept pretty large positive ones.
3916 if (M == CodeModel::Kernel && Offset >= 0)
3922 /// Determines whether the callee is required to pop its own arguments.
3923 /// Callee pop is necessary to support tail calls.
3924 bool X86::isCalleePop(CallingConv::ID CallingConv,
3925 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3926 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3927 // can guarantee TCO.
3928 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3931 switch (CallingConv) {
3934 case CallingConv::X86_StdCall:
3935 case CallingConv::X86_FastCall:
3936 case CallingConv::X86_ThisCall:
3937 case CallingConv::X86_VectorCall:
3942 /// \brief Return true if the condition is an unsigned comparison operation.
3943 static bool isX86CCUnsigned(unsigned X86CC) {
3945 default: llvm_unreachable("Invalid integer condition!");
3946 case X86::COND_E: return true;
3947 case X86::COND_G: return false;
3948 case X86::COND_GE: return false;
3949 case X86::COND_L: return false;
3950 case X86::COND_LE: return false;
3951 case X86::COND_NE: return true;
3952 case X86::COND_B: return true;
3953 case X86::COND_A: return true;
3954 case X86::COND_BE: return true;
3955 case X86::COND_AE: return true;
3959 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3960 /// condition code, returning the condition code and the LHS/RHS of the
3961 /// comparison to make.
3962 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3963 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3965 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3966 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3967 // X > -1 -> X == 0, jump !sign.
3968 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3969 return X86::COND_NS;
3971 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3972 // X < 0 -> X == 0, jump on sign.
3975 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3977 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3978 return X86::COND_LE;
3982 switch (SetCCOpcode) {
3983 default: llvm_unreachable("Invalid integer condition!");
3984 case ISD::SETEQ: return X86::COND_E;
3985 case ISD::SETGT: return X86::COND_G;
3986 case ISD::SETGE: return X86::COND_GE;
3987 case ISD::SETLT: return X86::COND_L;
3988 case ISD::SETLE: return X86::COND_LE;
3989 case ISD::SETNE: return X86::COND_NE;
3990 case ISD::SETULT: return X86::COND_B;
3991 case ISD::SETUGT: return X86::COND_A;
3992 case ISD::SETULE: return X86::COND_BE;
3993 case ISD::SETUGE: return X86::COND_AE;
3997 // First determine if it is required or is profitable to flip the operands.
3999 // If LHS is a foldable load, but RHS is not, flip the condition.
4000 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4001 !ISD::isNON_EXTLoad(RHS.getNode())) {
4002 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4003 std::swap(LHS, RHS);
4006 switch (SetCCOpcode) {
4012 std::swap(LHS, RHS);
4016 // On a floating point condition, the flags are set as follows:
4018 // 0 | 0 | 0 | X > Y
4019 // 0 | 0 | 1 | X < Y
4020 // 1 | 0 | 0 | X == Y
4021 // 1 | 1 | 1 | unordered
4022 switch (SetCCOpcode) {
4023 default: llvm_unreachable("Condcode should be pre-legalized away");
4025 case ISD::SETEQ: return X86::COND_E;
4026 case ISD::SETOLT: // flipped
4028 case ISD::SETGT: return X86::COND_A;
4029 case ISD::SETOLE: // flipped
4031 case ISD::SETGE: return X86::COND_AE;
4032 case ISD::SETUGT: // flipped
4034 case ISD::SETLT: return X86::COND_B;
4035 case ISD::SETUGE: // flipped
4037 case ISD::SETLE: return X86::COND_BE;
4039 case ISD::SETNE: return X86::COND_NE;
4040 case ISD::SETUO: return X86::COND_P;
4041 case ISD::SETO: return X86::COND_NP;
4043 case ISD::SETUNE: return X86::COND_INVALID;
4047 /// Is there a floating point cmov for the specific X86 condition code?
4048 /// Current x86 isa includes the following FP cmov instructions:
4049 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4050 static bool hasFPCMov(unsigned X86CC) {
4066 /// Returns true if the target can instruction select the
4067 /// specified FP immediate natively. If false, the legalizer will
4068 /// materialize the FP immediate as a load from a constant pool.
4069 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4070 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4071 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4077 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4078 ISD::LoadExtType ExtTy,
4080 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4081 // relocation target a movq or addq instruction: don't let the load shrink.
4082 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4083 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4084 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4085 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4089 /// \brief Returns true if it is beneficial to convert a load of a constant
4090 /// to just the constant itself.
4091 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4093 assert(Ty->isIntegerTy());
4095 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4096 if (BitSize == 0 || BitSize > 64)
4101 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4102 unsigned Index) const {
4103 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4106 return (Index == 0 || Index == ResVT.getVectorNumElements());
4109 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4110 // Speculate cttz only if we can directly use TZCNT.
4111 return Subtarget->hasBMI();
4114 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4115 // Speculate ctlz only if we can directly use LZCNT.
4116 return Subtarget->hasLZCNT();
4119 /// Return true if every element in Mask, beginning
4120 /// from position Pos and ending in Pos+Size is undef.
4121 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4122 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4128 /// Return true if Val is undef or if its value falls within the
4129 /// specified range (L, H].
4130 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4131 return (Val < 0) || (Val >= Low && Val < Hi);
4134 /// Val is either less than zero (undef) or equal to the specified value.
4135 static bool isUndefOrEqual(int Val, int CmpVal) {
4136 return (Val < 0 || Val == CmpVal);
4139 /// Return true if every element in Mask, beginning
4140 /// from position Pos and ending in Pos+Size, falls within the specified
4141 /// sequential range (Low, Low+Size]. or is undef.
4142 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4143 unsigned Pos, unsigned Size, int Low) {
4144 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4145 if (!isUndefOrEqual(Mask[i], Low))
4150 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4151 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4152 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4153 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4154 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4157 // The index should be aligned on a vecWidth-bit boundary.
4159 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4161 MVT VT = N->getSimpleValueType(0);
4162 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4163 bool Result = (Index * ElSize) % vecWidth == 0;
4168 /// Return true if the specified INSERT_SUBVECTOR
4169 /// operand specifies a subvector insert that is suitable for input to
4170 /// insertion of 128 or 256-bit subvectors
4171 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4172 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4173 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4175 // The index should be aligned on a vecWidth-bit boundary.
4177 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4179 MVT VT = N->getSimpleValueType(0);
4180 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4181 bool Result = (Index * ElSize) % vecWidth == 0;
4186 bool X86::isVINSERT128Index(SDNode *N) {
4187 return isVINSERTIndex(N, 128);
4190 bool X86::isVINSERT256Index(SDNode *N) {
4191 return isVINSERTIndex(N, 256);
4194 bool X86::isVEXTRACT128Index(SDNode *N) {
4195 return isVEXTRACTIndex(N, 128);
4198 bool X86::isVEXTRACT256Index(SDNode *N) {
4199 return isVEXTRACTIndex(N, 256);
4202 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4203 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4204 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4205 "Illegal extract subvector for VEXTRACT");
4208 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4210 MVT VecVT = N->getOperand(0).getSimpleValueType();
4211 MVT ElVT = VecVT.getVectorElementType();
4213 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4214 return Index / NumElemsPerChunk;
4217 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4218 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4219 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4220 "Illegal insert subvector for VINSERT");
4223 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4225 MVT VecVT = N->getSimpleValueType(0);
4226 MVT ElVT = VecVT.getVectorElementType();
4228 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4229 return Index / NumElemsPerChunk;
4232 /// Return the appropriate immediate to extract the specified
4233 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4234 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4235 return getExtractVEXTRACTImmediate(N, 128);
4238 /// Return the appropriate immediate to extract the specified
4239 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4240 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4241 return getExtractVEXTRACTImmediate(N, 256);
4244 /// Return the appropriate immediate to insert at the specified
4245 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4246 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4247 return getInsertVINSERTImmediate(N, 128);
4250 /// Return the appropriate immediate to insert at the specified
4251 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4252 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4253 return getInsertVINSERTImmediate(N, 256);
4256 /// Returns true if V is a constant integer zero.
4257 static bool isZero(SDValue V) {
4258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4259 return C && C->isNullValue();
4262 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4263 bool X86::isZeroNode(SDValue Elt) {
4266 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4267 return CFP->getValueAPF().isPosZero();
4271 // Build a vector of constants
4272 // Use an UNDEF node if MaskElt == -1.
4273 // Spilt 64-bit constants in the 32-bit mode.
4274 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4276 SDLoc dl, bool IsMask = false) {
4278 SmallVector<SDValue, 32> Ops;
4281 MVT ConstVecVT = VT;
4282 unsigned NumElts = VT.getVectorNumElements();
4283 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4284 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4285 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4289 MVT EltVT = ConstVecVT.getVectorElementType();
4290 for (unsigned i = 0; i < NumElts; ++i) {
4291 bool IsUndef = Values[i] < 0 && IsMask;
4292 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4293 DAG.getConstant(Values[i], dl, EltVT);
4294 Ops.push_back(OpNode);
4296 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4297 DAG.getConstant(0, dl, EltVT));
4299 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4301 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4305 /// Returns a vector of specified type with all zero elements.
4306 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4307 SelectionDAG &DAG, SDLoc dl) {
4308 assert(VT.isVector() && "Expected a vector type");
4310 // Always build SSE zero vectors as <4 x i32> bitcasted
4311 // to their dest type. This ensures they get CSE'd.
4313 if (VT.is128BitVector()) { // SSE
4314 if (Subtarget->hasSSE2()) { // SSE2
4315 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4316 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4318 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4319 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4321 } else if (VT.is256BitVector()) { // AVX
4322 if (Subtarget->hasInt256()) { // AVX2
4323 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4324 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4325 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4327 // 256-bit logic and arithmetic instructions in AVX are all
4328 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4329 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4330 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4331 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4333 } else if (VT.is512BitVector()) { // AVX-512
4334 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4335 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4336 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4337 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4338 } else if (VT.getVectorElementType() == MVT::i1) {
4340 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4341 && "Unexpected vector type");
4342 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4343 && "Unexpected vector type");
4344 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4345 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4346 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4348 llvm_unreachable("Unexpected vector type");
4350 return DAG.getBitcast(VT, Vec);
4353 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4354 SelectionDAG &DAG, SDLoc dl,
4355 unsigned vectorWidth) {
4356 assert((vectorWidth == 128 || vectorWidth == 256) &&
4357 "Unsupported vector width");
4358 EVT VT = Vec.getValueType();
4359 EVT ElVT = VT.getVectorElementType();
4360 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4361 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4362 VT.getVectorNumElements()/Factor);
4364 // Extract from UNDEF is UNDEF.
4365 if (Vec.getOpcode() == ISD::UNDEF)
4366 return DAG.getUNDEF(ResultVT);
4368 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4369 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4370 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4372 // This is the index of the first element of the vectorWidth-bit chunk
4373 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4374 IdxVal &= ~(ElemsPerChunk - 1);
4376 // If the input is a buildvector just emit a smaller one.
4377 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4378 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4379 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4381 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4382 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4385 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4386 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4387 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4388 /// instructions or a simple subregister reference. Idx is an index in the
4389 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4390 /// lowering EXTRACT_VECTOR_ELT operations easier.
4391 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4392 SelectionDAG &DAG, SDLoc dl) {
4393 assert((Vec.getValueType().is256BitVector() ||
4394 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4395 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4398 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4399 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4400 SelectionDAG &DAG, SDLoc dl) {
4401 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4402 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4405 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4406 unsigned IdxVal, SelectionDAG &DAG,
4407 SDLoc dl, unsigned vectorWidth) {
4408 assert((vectorWidth == 128 || vectorWidth == 256) &&
4409 "Unsupported vector width");
4410 // Inserting UNDEF is Result
4411 if (Vec.getOpcode() == ISD::UNDEF)
4413 EVT VT = Vec.getValueType();
4414 EVT ElVT = VT.getVectorElementType();
4415 EVT ResultVT = Result.getValueType();
4417 // Insert the relevant vectorWidth bits.
4418 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4419 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4421 // This is the index of the first element of the vectorWidth-bit chunk
4422 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4423 IdxVal &= ~(ElemsPerChunk - 1);
4425 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4426 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4429 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4430 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4431 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4432 /// simple superregister reference. Idx is an index in the 128 bits
4433 /// we want. It need not be aligned to a 128-bit boundary. That makes
4434 /// lowering INSERT_VECTOR_ELT operations easier.
4435 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4436 SelectionDAG &DAG, SDLoc dl) {
4437 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4439 // For insertion into the zero index (low half) of a 256-bit vector, it is
4440 // more efficient to generate a blend with immediate instead of an insert*128.
4441 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4442 // extend the subvector to the size of the result vector. Make sure that
4443 // we are not recursing on that node by checking for undef here.
4444 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4445 Result.getOpcode() != ISD::UNDEF) {
4446 EVT ResultVT = Result.getValueType();
4447 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4448 SDValue Undef = DAG.getUNDEF(ResultVT);
4449 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4452 // The blend instruction, and therefore its mask, depend on the data type.
4453 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4454 if (ScalarType.isFloatingPoint()) {
4455 // Choose either vblendps (float) or vblendpd (double).
4456 unsigned ScalarSize = ScalarType.getSizeInBits();
4457 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4458 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4459 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4460 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4463 const X86Subtarget &Subtarget =
4464 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4466 // AVX2 is needed for 256-bit integer blend support.
4467 // Integers must be cast to 32-bit because there is only vpblendd;
4468 // vpblendw can't be used for this because it has a handicapped mask.
4470 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4471 // is still more efficient than using the wrong domain vinsertf128 that
4472 // will be created by InsertSubVector().
4473 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4475 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4476 Vec256 = DAG.getBitcast(CastVT, Vec256);
4477 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4478 return DAG.getBitcast(ResultVT, Vec256);
4481 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4484 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4485 SelectionDAG &DAG, SDLoc dl) {
4486 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4487 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4490 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4491 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4492 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4493 /// large BUILD_VECTORS.
4494 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4495 unsigned NumElems, SelectionDAG &DAG,
4497 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4498 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4501 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4502 unsigned NumElems, SelectionDAG &DAG,
4504 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4505 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4508 /// Returns a vector of specified type with all bits set.
4509 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4510 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4511 /// Then bitcast to their original type, ensuring they get CSE'd.
4512 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4513 SelectionDAG &DAG, SDLoc dl) {
4514 assert(VT.isVector() && "Expected a vector type");
4516 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4518 if (VT.is512BitVector()) {
4519 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4520 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4521 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4522 } else if (VT.is256BitVector()) {
4523 if (Subtarget->hasInt256()) { // AVX2
4524 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4525 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4527 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4528 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4530 } else if (VT.is128BitVector()) {
4531 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4533 llvm_unreachable("Unexpected vector type");
4535 return DAG.getBitcast(VT, Vec);
4538 /// Returns a vector_shuffle node for an unpackl operation.
4539 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4541 unsigned NumElems = VT.getVectorNumElements();
4542 SmallVector<int, 8> Mask;
4543 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4545 Mask.push_back(i + NumElems);
4547 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4550 /// Returns a vector_shuffle node for an unpackh operation.
4551 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4553 unsigned NumElems = VT.getVectorNumElements();
4554 SmallVector<int, 8> Mask;
4555 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4556 Mask.push_back(i + Half);
4557 Mask.push_back(i + NumElems + Half);
4559 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4562 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4563 /// This produces a shuffle where the low element of V2 is swizzled into the
4564 /// zero/undef vector, landing at element Idx.
4565 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4566 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4568 const X86Subtarget *Subtarget,
4569 SelectionDAG &DAG) {
4570 MVT VT = V2.getSimpleValueType();
4572 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4573 unsigned NumElems = VT.getVectorNumElements();
4574 SmallVector<int, 16> MaskVec;
4575 for (unsigned i = 0; i != NumElems; ++i)
4576 // If this is the insertion idx, put the low elt of V2 here.
4577 MaskVec.push_back(i == Idx ? NumElems : i);
4578 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4581 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4582 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4583 /// uses one source. Note that this will set IsUnary for shuffles which use a
4584 /// single input multiple times, and in those cases it will
4585 /// adjust the mask to only have indices within that single input.
4586 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4587 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4588 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4589 unsigned NumElems = VT.getVectorNumElements();
4593 bool IsFakeUnary = false;
4594 switch(N->getOpcode()) {
4595 case X86ISD::BLENDI:
4596 ImmN = N->getOperand(N->getNumOperands()-1);
4597 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4602 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4604 case X86ISD::UNPCKH:
4605 DecodeUNPCKHMask(VT, Mask);
4606 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4608 case X86ISD::UNPCKL:
4609 DecodeUNPCKLMask(VT, Mask);
4610 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4612 case X86ISD::MOVHLPS:
4613 DecodeMOVHLPSMask(NumElems, Mask);
4614 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4616 case X86ISD::MOVLHPS:
4617 DecodeMOVLHPSMask(NumElems, Mask);
4618 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4620 case X86ISD::PALIGNR:
4621 ImmN = N->getOperand(N->getNumOperands()-1);
4622 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4624 case X86ISD::PSHUFD:
4625 case X86ISD::VPERMILPI:
4626 ImmN = N->getOperand(N->getNumOperands()-1);
4627 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4630 case X86ISD::PSHUFHW:
4631 ImmN = N->getOperand(N->getNumOperands()-1);
4632 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4635 case X86ISD::PSHUFLW:
4636 ImmN = N->getOperand(N->getNumOperands()-1);
4637 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4640 case X86ISD::PSHUFB: {
4642 SDValue MaskNode = N->getOperand(1);
4643 while (MaskNode->getOpcode() == ISD::BITCAST)
4644 MaskNode = MaskNode->getOperand(0);
4646 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4647 // If we have a build-vector, then things are easy.
4648 MVT VT = MaskNode.getSimpleValueType();
4649 assert(VT.isVector() &&
4650 "Can't produce a non-vector with a build_vector!");
4651 if (!VT.isInteger())
4654 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4656 SmallVector<uint64_t, 32> RawMask;
4657 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4658 SDValue Op = MaskNode->getOperand(i);
4659 if (Op->getOpcode() == ISD::UNDEF) {
4660 RawMask.push_back((uint64_t)SM_SentinelUndef);
4663 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4666 APInt MaskElement = CN->getAPIntValue();
4668 // We now have to decode the element which could be any integer size and
4669 // extract each byte of it.
4670 for (int j = 0; j < NumBytesPerElement; ++j) {
4671 // Note that this is x86 and so always little endian: the low byte is
4672 // the first byte of the mask.
4673 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4674 MaskElement = MaskElement.lshr(8);
4677 DecodePSHUFBMask(RawMask, Mask);
4681 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4685 SDValue Ptr = MaskLoad->getBasePtr();
4686 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4687 Ptr->getOpcode() == X86ISD::WrapperRIP)
4688 Ptr = Ptr->getOperand(0);
4690 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4691 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4694 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4695 DecodePSHUFBMask(C, Mask);
4703 case X86ISD::VPERMI:
4704 ImmN = N->getOperand(N->getNumOperands()-1);
4705 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4710 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4712 case X86ISD::VPERM2X128:
4713 ImmN = N->getOperand(N->getNumOperands()-1);
4714 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4715 if (Mask.empty()) return false;
4716 // Mask only contains negative index if an element is zero.
4717 if (std::any_of(Mask.begin(), Mask.end(),
4718 [](int M){ return M == SM_SentinelZero; }))
4721 case X86ISD::MOVSLDUP:
4722 DecodeMOVSLDUPMask(VT, Mask);
4725 case X86ISD::MOVSHDUP:
4726 DecodeMOVSHDUPMask(VT, Mask);
4729 case X86ISD::MOVDDUP:
4730 DecodeMOVDDUPMask(VT, Mask);
4733 case X86ISD::MOVLHPD:
4734 case X86ISD::MOVLPD:
4735 case X86ISD::MOVLPS:
4736 // Not yet implemented
4738 case X86ISD::VPERMV: {
4740 SDValue MaskNode = N->getOperand(0);
4741 while (MaskNode->getOpcode() == ISD::BITCAST)
4742 MaskNode = MaskNode->getOperand(0);
4744 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4745 SmallVector<uint64_t, 32> RawMask;
4746 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4747 // If we have a build-vector, then things are easy.
4748 assert(MaskNode.getSimpleValueType().isInteger() &&
4749 MaskNode.getSimpleValueType().getVectorNumElements() ==
4750 VT.getVectorNumElements());
4752 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4753 SDValue Op = MaskNode->getOperand(i);
4754 if (Op->getOpcode() == ISD::UNDEF)
4755 RawMask.push_back((uint64_t)SM_SentinelUndef);
4756 else if (isa<ConstantSDNode>(Op)) {
4757 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4758 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4762 DecodeVPERMVMask(RawMask, Mask);
4765 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4766 unsigned NumEltsInMask = MaskNode->getNumOperands();
4767 MaskNode = MaskNode->getOperand(0);
4768 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4770 APInt MaskEltValue = CN->getAPIntValue();
4771 for (unsigned i = 0; i < NumEltsInMask; ++i)
4772 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4773 DecodeVPERMVMask(RawMask, Mask);
4776 // It may be a scalar load
4779 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4783 SDValue Ptr = MaskLoad->getBasePtr();
4784 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4785 Ptr->getOpcode() == X86ISD::WrapperRIP)
4786 Ptr = Ptr->getOperand(0);
4788 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4789 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4792 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4794 DecodeVPERMVMask(C, VT, Mask);
4801 case X86ISD::VPERMV3: {
4803 SDValue MaskNode = N->getOperand(1);
4804 while (MaskNode->getOpcode() == ISD::BITCAST)
4805 MaskNode = MaskNode->getOperand(1);
4807 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4808 // If we have a build-vector, then things are easy.
4809 assert(MaskNode.getSimpleValueType().isInteger() &&
4810 MaskNode.getSimpleValueType().getVectorNumElements() ==
4811 VT.getVectorNumElements());
4813 SmallVector<uint64_t, 32> RawMask;
4814 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4816 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4817 SDValue Op = MaskNode->getOperand(i);
4818 if (Op->getOpcode() == ISD::UNDEF)
4819 RawMask.push_back((uint64_t)SM_SentinelUndef);
4821 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4824 APInt MaskElement = CN->getAPIntValue();
4825 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4828 DecodeVPERMV3Mask(RawMask, Mask);
4832 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4836 SDValue Ptr = MaskLoad->getBasePtr();
4837 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4838 Ptr->getOpcode() == X86ISD::WrapperRIP)
4839 Ptr = Ptr->getOperand(0);
4841 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4842 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4845 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4847 DecodeVPERMV3Mask(C, VT, Mask);
4854 default: llvm_unreachable("unknown target shuffle node");
4857 // If we have a fake unary shuffle, the shuffle mask is spread across two
4858 // inputs that are actually the same node. Re-map the mask to always point
4859 // into the first input.
4862 if (M >= (int)Mask.size())
4868 /// Returns the scalar element that will make up the ith
4869 /// element of the result of the vector shuffle.
4870 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4873 return SDValue(); // Limit search depth.
4875 SDValue V = SDValue(N, 0);
4876 EVT VT = V.getValueType();
4877 unsigned Opcode = V.getOpcode();
4879 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4880 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4881 int Elt = SV->getMaskElt(Index);
4884 return DAG.getUNDEF(VT.getVectorElementType());
4886 unsigned NumElems = VT.getVectorNumElements();
4887 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4888 : SV->getOperand(1);
4889 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4892 // Recurse into target specific vector shuffles to find scalars.
4893 if (isTargetShuffle(Opcode)) {
4894 MVT ShufVT = V.getSimpleValueType();
4895 unsigned NumElems = ShufVT.getVectorNumElements();
4896 SmallVector<int, 16> ShuffleMask;
4899 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4902 int Elt = ShuffleMask[Index];
4904 return DAG.getUNDEF(ShufVT.getVectorElementType());
4906 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4908 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4912 // Actual nodes that may contain scalar elements
4913 if (Opcode == ISD::BITCAST) {
4914 V = V.getOperand(0);
4915 EVT SrcVT = V.getValueType();
4916 unsigned NumElems = VT.getVectorNumElements();
4918 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4922 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4923 return (Index == 0) ? V.getOperand(0)
4924 : DAG.getUNDEF(VT.getVectorElementType());
4926 if (V.getOpcode() == ISD::BUILD_VECTOR)
4927 return V.getOperand(Index);
4932 /// Custom lower build_vector of v16i8.
4933 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4934 unsigned NumNonZero, unsigned NumZero,
4936 const X86Subtarget* Subtarget,
4937 const TargetLowering &TLI) {
4945 // SSE4.1 - use PINSRB to insert each byte directly.
4946 if (Subtarget->hasSSE41()) {
4947 for (unsigned i = 0; i < 16; ++i) {
4948 bool isNonZero = (NonZeros & (1 << i)) != 0;
4952 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4954 V = DAG.getUNDEF(MVT::v16i8);
4957 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4958 MVT::v16i8, V, Op.getOperand(i),
4959 DAG.getIntPtrConstant(i, dl));
4966 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4967 for (unsigned i = 0; i < 16; ++i) {
4968 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4969 if (ThisIsNonZero && First) {
4971 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4973 V = DAG.getUNDEF(MVT::v8i16);
4978 SDValue ThisElt, LastElt;
4979 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4980 if (LastIsNonZero) {
4981 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4982 MVT::i16, Op.getOperand(i-1));
4984 if (ThisIsNonZero) {
4985 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4986 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4987 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4989 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4993 if (ThisElt.getNode())
4994 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4995 DAG.getIntPtrConstant(i/2, dl));
4999 return DAG.getBitcast(MVT::v16i8, V);
5002 /// Custom lower build_vector of v8i16.
5003 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5004 unsigned NumNonZero, unsigned NumZero,
5006 const X86Subtarget* Subtarget,
5007 const TargetLowering &TLI) {
5014 for (unsigned i = 0; i < 8; ++i) {
5015 bool isNonZero = (NonZeros & (1 << i)) != 0;
5019 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5021 V = DAG.getUNDEF(MVT::v8i16);
5024 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5025 MVT::v8i16, V, Op.getOperand(i),
5026 DAG.getIntPtrConstant(i, dl));
5033 /// Custom lower build_vector of v4i32 or v4f32.
5034 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5035 const X86Subtarget *Subtarget,
5036 const TargetLowering &TLI) {
5037 // Find all zeroable elements.
5038 std::bitset<4> Zeroable;
5039 for (int i=0; i < 4; ++i) {
5040 SDValue Elt = Op->getOperand(i);
5041 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5043 assert(Zeroable.size() - Zeroable.count() > 1 &&
5044 "We expect at least two non-zero elements!");
5046 // We only know how to deal with build_vector nodes where elements are either
5047 // zeroable or extract_vector_elt with constant index.
5048 SDValue FirstNonZero;
5049 unsigned FirstNonZeroIdx;
5050 for (unsigned i=0; i < 4; ++i) {
5053 SDValue Elt = Op->getOperand(i);
5054 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5055 !isa<ConstantSDNode>(Elt.getOperand(1)))
5057 // Make sure that this node is extracting from a 128-bit vector.
5058 MVT VT = Elt.getOperand(0).getSimpleValueType();
5059 if (!VT.is128BitVector())
5061 if (!FirstNonZero.getNode()) {
5063 FirstNonZeroIdx = i;
5067 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5068 SDValue V1 = FirstNonZero.getOperand(0);
5069 MVT VT = V1.getSimpleValueType();
5071 // See if this build_vector can be lowered as a blend with zero.
5073 unsigned EltMaskIdx, EltIdx;
5075 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5076 if (Zeroable[EltIdx]) {
5077 // The zero vector will be on the right hand side.
5078 Mask[EltIdx] = EltIdx+4;
5082 Elt = Op->getOperand(EltIdx);
5083 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5084 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5085 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5087 Mask[EltIdx] = EltIdx;
5091 // Let the shuffle legalizer deal with blend operations.
5092 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5093 if (V1.getSimpleValueType() != VT)
5094 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5095 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5098 // See if we can lower this build_vector to a INSERTPS.
5099 if (!Subtarget->hasSSE41())
5102 SDValue V2 = Elt.getOperand(0);
5103 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5106 bool CanFold = true;
5107 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5111 SDValue Current = Op->getOperand(i);
5112 SDValue SrcVector = Current->getOperand(0);
5115 CanFold = SrcVector == V1 &&
5116 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5122 assert(V1.getNode() && "Expected at least two non-zero elements!");
5123 if (V1.getSimpleValueType() != MVT::v4f32)
5124 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5125 if (V2.getSimpleValueType() != MVT::v4f32)
5126 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5128 // Ok, we can emit an INSERTPS instruction.
5129 unsigned ZMask = Zeroable.to_ulong();
5131 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5132 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5134 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5135 DAG.getIntPtrConstant(InsertPSMask, DL));
5136 return DAG.getBitcast(VT, Result);
5139 /// Return a vector logical shift node.
5140 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5141 unsigned NumBits, SelectionDAG &DAG,
5142 const TargetLowering &TLI, SDLoc dl) {
5143 assert(VT.is128BitVector() && "Unknown type for VShift");
5144 MVT ShVT = MVT::v2i64;
5145 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5146 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5147 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5148 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5149 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5150 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5154 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5156 // Check if the scalar load can be widened into a vector load. And if
5157 // the address is "base + cst" see if the cst can be "absorbed" into
5158 // the shuffle mask.
5159 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5160 SDValue Ptr = LD->getBasePtr();
5161 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5163 EVT PVT = LD->getValueType(0);
5164 if (PVT != MVT::i32 && PVT != MVT::f32)
5169 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5170 FI = FINode->getIndex();
5172 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5173 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5174 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5175 Offset = Ptr.getConstantOperandVal(1);
5176 Ptr = Ptr.getOperand(0);
5181 // FIXME: 256-bit vector instructions don't require a strict alignment,
5182 // improve this code to support it better.
5183 unsigned RequiredAlign = VT.getSizeInBits()/8;
5184 SDValue Chain = LD->getChain();
5185 // Make sure the stack object alignment is at least 16 or 32.
5186 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5187 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5188 if (MFI->isFixedObjectIndex(FI)) {
5189 // Can't change the alignment. FIXME: It's possible to compute
5190 // the exact stack offset and reference FI + adjust offset instead.
5191 // If someone *really* cares about this. That's the way to implement it.
5194 MFI->setObjectAlignment(FI, RequiredAlign);
5198 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5199 // Ptr + (Offset & ~15).
5202 if ((Offset % RequiredAlign) & 3)
5204 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5207 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5208 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5211 int EltNo = (Offset - StartOffset) >> 2;
5212 unsigned NumElems = VT.getVectorNumElements();
5214 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5215 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5216 LD->getPointerInfo().getWithOffset(StartOffset),
5217 false, false, false, 0);
5219 SmallVector<int, 8> Mask(NumElems, EltNo);
5221 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5227 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5228 /// elements can be replaced by a single large load which has the same value as
5229 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5231 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5233 /// FIXME: we'd also like to handle the case where the last elements are zero
5234 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5235 /// There's even a handy isZeroNode for that purpose.
5236 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5237 SDLoc &DL, SelectionDAG &DAG,
5238 bool isAfterLegalize) {
5239 unsigned NumElems = Elts.size();
5241 LoadSDNode *LDBase = nullptr;
5242 unsigned LastLoadedElt = -1U;
5244 // For each element in the initializer, see if we've found a load or an undef.
5245 // If we don't find an initial load element, or later load elements are
5246 // non-consecutive, bail out.
5247 for (unsigned i = 0; i < NumElems; ++i) {
5248 SDValue Elt = Elts[i];
5249 // Look through a bitcast.
5250 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5251 Elt = Elt.getOperand(0);
5252 if (!Elt.getNode() ||
5253 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5256 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5258 LDBase = cast<LoadSDNode>(Elt.getNode());
5262 if (Elt.getOpcode() == ISD::UNDEF)
5265 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5266 EVT LdVT = Elt.getValueType();
5267 // Each loaded element must be the correct fractional portion of the
5268 // requested vector load.
5269 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5271 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5276 // If we have found an entire vector of loads and undefs, then return a large
5277 // load of the entire vector width starting at the base pointer. If we found
5278 // consecutive loads for the low half, generate a vzext_load node.
5279 if (LastLoadedElt == NumElems - 1) {
5280 assert(LDBase && "Did not find base load for merging consecutive loads");
5281 EVT EltVT = LDBase->getValueType(0);
5282 // Ensure that the input vector size for the merged loads matches the
5283 // cumulative size of the input elements.
5284 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5287 if (isAfterLegalize &&
5288 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5291 SDValue NewLd = SDValue();
5293 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5294 LDBase->getPointerInfo(), LDBase->isVolatile(),
5295 LDBase->isNonTemporal(), LDBase->isInvariant(),
5296 LDBase->getAlignment());
5298 if (LDBase->hasAnyUseOfValue(1)) {
5299 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5301 SDValue(NewLd.getNode(), 1));
5302 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5303 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5304 SDValue(NewLd.getNode(), 1));
5310 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5311 //of a v4i32 / v4f32. It's probably worth generalizing.
5312 EVT EltVT = VT.getVectorElementType();
5313 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5314 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5315 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5316 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5318 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5319 LDBase->getPointerInfo(),
5320 LDBase->getAlignment(),
5321 false/*isVolatile*/, true/*ReadMem*/,
5324 // Make sure the newly-created LOAD is in the same position as LDBase in
5325 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5326 // update uses of LDBase's output chain to use the TokenFactor.
5327 if (LDBase->hasAnyUseOfValue(1)) {
5328 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5329 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5330 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5331 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5332 SDValue(ResNode.getNode(), 1));
5335 return DAG.getBitcast(VT, ResNode);
5340 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5341 /// to generate a splat value for the following cases:
5342 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5343 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5344 /// a scalar load, or a constant.
5345 /// The VBROADCAST node is returned when a pattern is found,
5346 /// or SDValue() otherwise.
5347 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5348 SelectionDAG &DAG) {
5349 // VBROADCAST requires AVX.
5350 // TODO: Splats could be generated for non-AVX CPUs using SSE
5351 // instructions, but there's less potential gain for only 128-bit vectors.
5352 if (!Subtarget->hasAVX())
5355 MVT VT = Op.getSimpleValueType();
5358 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5359 "Unsupported vector type for broadcast.");
5364 switch (Op.getOpcode()) {
5366 // Unknown pattern found.
5369 case ISD::BUILD_VECTOR: {
5370 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5371 BitVector UndefElements;
5372 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5374 // We need a splat of a single value to use broadcast, and it doesn't
5375 // make any sense if the value is only in one element of the vector.
5376 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5380 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5381 Ld.getOpcode() == ISD::ConstantFP);
5383 // Make sure that all of the users of a non-constant load are from the
5384 // BUILD_VECTOR node.
5385 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5390 case ISD::VECTOR_SHUFFLE: {
5391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5393 // Shuffles must have a splat mask where the first element is
5395 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5398 SDValue Sc = Op.getOperand(0);
5399 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5400 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5402 if (!Subtarget->hasInt256())
5405 // Use the register form of the broadcast instruction available on AVX2.
5406 if (VT.getSizeInBits() >= 256)
5407 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5408 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5411 Ld = Sc.getOperand(0);
5412 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5413 Ld.getOpcode() == ISD::ConstantFP);
5415 // The scalar_to_vector node and the suspected
5416 // load node must have exactly one user.
5417 // Constants may have multiple users.
5419 // AVX-512 has register version of the broadcast
5420 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5421 Ld.getValueType().getSizeInBits() >= 32;
5422 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5429 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5430 bool IsGE256 = (VT.getSizeInBits() >= 256);
5432 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5433 // instruction to save 8 or more bytes of constant pool data.
5434 // TODO: If multiple splats are generated to load the same constant,
5435 // it may be detrimental to overall size. There needs to be a way to detect
5436 // that condition to know if this is truly a size win.
5437 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5439 // Handle broadcasting a single constant scalar from the constant pool
5441 // On Sandybridge (no AVX2), it is still better to load a constant vector
5442 // from the constant pool and not to broadcast it from a scalar.
5443 // But override that restriction when optimizing for size.
5444 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5445 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5446 EVT CVT = Ld.getValueType();
5447 assert(!CVT.isVector() && "Must not broadcast a vector type");
5449 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5450 // For size optimization, also splat v2f64 and v2i64, and for size opt
5451 // with AVX2, also splat i8 and i16.
5452 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5453 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5454 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5455 const Constant *C = nullptr;
5456 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5457 C = CI->getConstantIntValue();
5458 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5459 C = CF->getConstantFPValue();
5461 assert(C && "Invalid constant type");
5463 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5465 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5466 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5468 CVT, dl, DAG.getEntryNode(), CP,
5469 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5470 false, false, Alignment);
5472 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5476 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5478 // Handle AVX2 in-register broadcasts.
5479 if (!IsLoad && Subtarget->hasInt256() &&
5480 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5481 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5483 // The scalar source must be a normal load.
5487 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5488 (Subtarget->hasVLX() && ScalarSize == 64))
5489 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5491 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5492 // double since there is no vbroadcastsd xmm
5493 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5494 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5495 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5498 // Unsupported broadcast.
5502 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5503 /// underlying vector and index.
5505 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5507 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5509 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5510 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5513 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5515 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5517 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5518 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5521 // In this case the vector is the extract_subvector expression and the index
5522 // is 2, as specified by the shuffle.
5523 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5524 SDValue ShuffleVec = SVOp->getOperand(0);
5525 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5526 assert(ShuffleVecVT.getVectorElementType() ==
5527 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5529 int ShuffleIdx = SVOp->getMaskElt(Idx);
5530 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5531 ExtractedFromVec = ShuffleVec;
5537 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5538 MVT VT = Op.getSimpleValueType();
5540 // Skip if insert_vec_elt is not supported.
5541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5542 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5546 unsigned NumElems = Op.getNumOperands();
5550 SmallVector<unsigned, 4> InsertIndices;
5551 SmallVector<int, 8> Mask(NumElems, -1);
5553 for (unsigned i = 0; i != NumElems; ++i) {
5554 unsigned Opc = Op.getOperand(i).getOpcode();
5556 if (Opc == ISD::UNDEF)
5559 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5560 // Quit if more than 1 elements need inserting.
5561 if (InsertIndices.size() > 1)
5564 InsertIndices.push_back(i);
5568 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5569 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5570 // Quit if non-constant index.
5571 if (!isa<ConstantSDNode>(ExtIdx))
5573 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5575 // Quit if extracted from vector of different type.
5576 if (ExtractedFromVec.getValueType() != VT)
5579 if (!VecIn1.getNode())
5580 VecIn1 = ExtractedFromVec;
5581 else if (VecIn1 != ExtractedFromVec) {
5582 if (!VecIn2.getNode())
5583 VecIn2 = ExtractedFromVec;
5584 else if (VecIn2 != ExtractedFromVec)
5585 // Quit if more than 2 vectors to shuffle
5589 if (ExtractedFromVec == VecIn1)
5591 else if (ExtractedFromVec == VecIn2)
5592 Mask[i] = Idx + NumElems;
5595 if (!VecIn1.getNode())
5598 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5599 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5600 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5601 unsigned Idx = InsertIndices[i];
5602 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5603 DAG.getIntPtrConstant(Idx, DL));
5609 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5610 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5611 Op.getScalarValueSizeInBits() == 1 &&
5612 "Can not convert non-constant vector");
5613 uint64_t Immediate = 0;
5614 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5615 SDValue In = Op.getOperand(idx);
5616 if (In.getOpcode() != ISD::UNDEF)
5617 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5621 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5622 return DAG.getConstant(Immediate, dl, VT);
5624 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5626 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5628 MVT VT = Op.getSimpleValueType();
5629 assert((VT.getVectorElementType() == MVT::i1) &&
5630 "Unexpected type in LowerBUILD_VECTORvXi1!");
5633 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5634 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5635 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5636 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5639 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5640 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5641 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5642 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5645 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5646 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5647 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5648 return DAG.getBitcast(VT, Imm);
5649 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5650 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5651 DAG.getIntPtrConstant(0, dl));
5654 // Vector has one or more non-const elements
5655 uint64_t Immediate = 0;
5656 SmallVector<unsigned, 16> NonConstIdx;
5657 bool IsSplat = true;
5658 bool HasConstElts = false;
5660 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5661 SDValue In = Op.getOperand(idx);
5662 if (In.getOpcode() == ISD::UNDEF)
5664 if (!isa<ConstantSDNode>(In))
5665 NonConstIdx.push_back(idx);
5667 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5668 HasConstElts = true;
5672 else if (In != Op.getOperand(SplatIdx))
5676 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5678 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5679 DAG.getConstant(1, dl, VT),
5680 DAG.getConstant(0, dl, VT));
5682 // insert elements one by one
5686 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5687 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5689 else if (HasConstElts)
5690 Imm = DAG.getConstant(0, dl, VT);
5692 Imm = DAG.getUNDEF(VT);
5693 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5694 DstVec = DAG.getBitcast(VT, Imm);
5696 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5697 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5698 DAG.getIntPtrConstant(0, dl));
5701 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5702 unsigned InsertIdx = NonConstIdx[i];
5703 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5704 Op.getOperand(InsertIdx),
5705 DAG.getIntPtrConstant(InsertIdx, dl));
5710 /// \brief Return true if \p N implements a horizontal binop and return the
5711 /// operands for the horizontal binop into V0 and V1.
5713 /// This is a helper function of LowerToHorizontalOp().
5714 /// This function checks that the build_vector \p N in input implements a
5715 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5716 /// operation to match.
5717 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5718 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5719 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5722 /// This function only analyzes elements of \p N whose indices are
5723 /// in range [BaseIdx, LastIdx).
5724 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5726 unsigned BaseIdx, unsigned LastIdx,
5727 SDValue &V0, SDValue &V1) {
5728 EVT VT = N->getValueType(0);
5730 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5731 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5732 "Invalid Vector in input!");
5734 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5735 bool CanFold = true;
5736 unsigned ExpectedVExtractIdx = BaseIdx;
5737 unsigned NumElts = LastIdx - BaseIdx;
5738 V0 = DAG.getUNDEF(VT);
5739 V1 = DAG.getUNDEF(VT);
5741 // Check if N implements a horizontal binop.
5742 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5743 SDValue Op = N->getOperand(i + BaseIdx);
5746 if (Op->getOpcode() == ISD::UNDEF) {
5747 // Update the expected vector extract index.
5748 if (i * 2 == NumElts)
5749 ExpectedVExtractIdx = BaseIdx;
5750 ExpectedVExtractIdx += 2;
5754 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5759 SDValue Op0 = Op.getOperand(0);
5760 SDValue Op1 = Op.getOperand(1);
5762 // Try to match the following pattern:
5763 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5764 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5765 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5766 Op0.getOperand(0) == Op1.getOperand(0) &&
5767 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5768 isa<ConstantSDNode>(Op1.getOperand(1)));
5772 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5773 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5775 if (i * 2 < NumElts) {
5776 if (V0.getOpcode() == ISD::UNDEF) {
5777 V0 = Op0.getOperand(0);
5778 if (V0.getValueType() != VT)
5782 if (V1.getOpcode() == ISD::UNDEF) {
5783 V1 = Op0.getOperand(0);
5784 if (V1.getValueType() != VT)
5787 if (i * 2 == NumElts)
5788 ExpectedVExtractIdx = BaseIdx;
5791 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5792 if (I0 == ExpectedVExtractIdx)
5793 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5794 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5795 // Try to match the following dag sequence:
5796 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5797 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5801 ExpectedVExtractIdx += 2;
5807 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5808 /// a concat_vector.
5810 /// This is a helper function of LowerToHorizontalOp().
5811 /// This function expects two 256-bit vectors called V0 and V1.
5812 /// At first, each vector is split into two separate 128-bit vectors.
5813 /// Then, the resulting 128-bit vectors are used to implement two
5814 /// horizontal binary operations.
5816 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5818 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5819 /// the two new horizontal binop.
5820 /// When Mode is set, the first horizontal binop dag node would take as input
5821 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5822 /// horizontal binop dag node would take as input the lower 128-bit of V1
5823 /// and the upper 128-bit of V1.
5825 /// HADD V0_LO, V0_HI
5826 /// HADD V1_LO, V1_HI
5828 /// Otherwise, the first horizontal binop dag node takes as input the lower
5829 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5830 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5832 /// HADD V0_LO, V1_LO
5833 /// HADD V0_HI, V1_HI
5835 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5836 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5837 /// the upper 128-bits of the result.
5838 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5839 SDLoc DL, SelectionDAG &DAG,
5840 unsigned X86Opcode, bool Mode,
5841 bool isUndefLO, bool isUndefHI) {
5842 EVT VT = V0.getValueType();
5843 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5844 "Invalid nodes in input!");
5846 unsigned NumElts = VT.getVectorNumElements();
5847 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5848 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5849 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5850 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5851 EVT NewVT = V0_LO.getValueType();
5853 SDValue LO = DAG.getUNDEF(NewVT);
5854 SDValue HI = DAG.getUNDEF(NewVT);
5857 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5858 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5859 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5860 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5861 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5863 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5864 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5865 V1_LO->getOpcode() != ISD::UNDEF))
5866 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5868 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5869 V1_HI->getOpcode() != ISD::UNDEF))
5870 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5873 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5876 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5878 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5879 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5880 MVT VT = BV->getSimpleValueType(0);
5881 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5882 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5886 unsigned NumElts = VT.getVectorNumElements();
5887 SDValue InVec0 = DAG.getUNDEF(VT);
5888 SDValue InVec1 = DAG.getUNDEF(VT);
5890 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5891 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5893 // Odd-numbered elements in the input build vector are obtained from
5894 // adding two integer/float elements.
5895 // Even-numbered elements in the input build vector are obtained from
5896 // subtracting two integer/float elements.
5897 unsigned ExpectedOpcode = ISD::FSUB;
5898 unsigned NextExpectedOpcode = ISD::FADD;
5899 bool AddFound = false;
5900 bool SubFound = false;
5902 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5903 SDValue Op = BV->getOperand(i);
5905 // Skip 'undef' values.
5906 unsigned Opcode = Op.getOpcode();
5907 if (Opcode == ISD::UNDEF) {
5908 std::swap(ExpectedOpcode, NextExpectedOpcode);
5912 // Early exit if we found an unexpected opcode.
5913 if (Opcode != ExpectedOpcode)
5916 SDValue Op0 = Op.getOperand(0);
5917 SDValue Op1 = Op.getOperand(1);
5919 // Try to match the following pattern:
5920 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5921 // Early exit if we cannot match that sequence.
5922 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5923 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5924 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5925 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5926 Op0.getOperand(1) != Op1.getOperand(1))
5929 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5933 // We found a valid add/sub node. Update the information accordingly.
5939 // Update InVec0 and InVec1.
5940 if (InVec0.getOpcode() == ISD::UNDEF) {
5941 InVec0 = Op0.getOperand(0);
5942 if (InVec0.getSimpleValueType() != VT)
5945 if (InVec1.getOpcode() == ISD::UNDEF) {
5946 InVec1 = Op1.getOperand(0);
5947 if (InVec1.getSimpleValueType() != VT)
5951 // Make sure that operands in input to each add/sub node always
5952 // come from a same pair of vectors.
5953 if (InVec0 != Op0.getOperand(0)) {
5954 if (ExpectedOpcode == ISD::FSUB)
5957 // FADD is commutable. Try to commute the operands
5958 // and then test again.
5959 std::swap(Op0, Op1);
5960 if (InVec0 != Op0.getOperand(0))
5964 if (InVec1 != Op1.getOperand(0))
5967 // Update the pair of expected opcodes.
5968 std::swap(ExpectedOpcode, NextExpectedOpcode);
5971 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5972 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5973 InVec1.getOpcode() != ISD::UNDEF)
5974 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5979 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5980 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5981 const X86Subtarget *Subtarget,
5982 SelectionDAG &DAG) {
5983 MVT VT = BV->getSimpleValueType(0);
5984 unsigned NumElts = VT.getVectorNumElements();
5985 unsigned NumUndefsLO = 0;
5986 unsigned NumUndefsHI = 0;
5987 unsigned Half = NumElts/2;
5989 // Count the number of UNDEF operands in the build_vector in input.
5990 for (unsigned i = 0, e = Half; i != e; ++i)
5991 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5994 for (unsigned i = Half, e = NumElts; i != e; ++i)
5995 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5998 // Early exit if this is either a build_vector of all UNDEFs or all the
5999 // operands but one are UNDEF.
6000 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6004 SDValue InVec0, InVec1;
6005 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6006 // Try to match an SSE3 float HADD/HSUB.
6007 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6008 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6010 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6011 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6012 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6013 // Try to match an SSSE3 integer HADD/HSUB.
6014 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6015 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6017 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6018 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6021 if (!Subtarget->hasAVX())
6024 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6025 // Try to match an AVX horizontal add/sub of packed single/double
6026 // precision floating point values from 256-bit vectors.
6027 SDValue InVec2, InVec3;
6028 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6029 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6030 ((InVec0.getOpcode() == ISD::UNDEF ||
6031 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6032 ((InVec1.getOpcode() == ISD::UNDEF ||
6033 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6034 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6036 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6037 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6038 ((InVec0.getOpcode() == ISD::UNDEF ||
6039 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6040 ((InVec1.getOpcode() == ISD::UNDEF ||
6041 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6042 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6043 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6044 // Try to match an AVX2 horizontal add/sub of signed integers.
6045 SDValue InVec2, InVec3;
6047 bool CanFold = true;
6049 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6050 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6051 ((InVec0.getOpcode() == ISD::UNDEF ||
6052 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6053 ((InVec1.getOpcode() == ISD::UNDEF ||
6054 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6055 X86Opcode = X86ISD::HADD;
6056 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6057 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6058 ((InVec0.getOpcode() == ISD::UNDEF ||
6059 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6060 ((InVec1.getOpcode() == ISD::UNDEF ||
6061 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6062 X86Opcode = X86ISD::HSUB;
6067 // Fold this build_vector into a single horizontal add/sub.
6068 // Do this only if the target has AVX2.
6069 if (Subtarget->hasAVX2())
6070 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6072 // Do not try to expand this build_vector into a pair of horizontal
6073 // add/sub if we can emit a pair of scalar add/sub.
6074 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6077 // Convert this build_vector into a pair of horizontal binop followed by
6079 bool isUndefLO = NumUndefsLO == Half;
6080 bool isUndefHI = NumUndefsHI == Half;
6081 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6082 isUndefLO, isUndefHI);
6086 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6087 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6089 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6090 X86Opcode = X86ISD::HADD;
6091 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6092 X86Opcode = X86ISD::HSUB;
6093 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6094 X86Opcode = X86ISD::FHADD;
6095 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6096 X86Opcode = X86ISD::FHSUB;
6100 // Don't try to expand this build_vector into a pair of horizontal add/sub
6101 // if we can simply emit a pair of scalar add/sub.
6102 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6105 // Convert this build_vector into two horizontal add/sub followed by
6107 bool isUndefLO = NumUndefsLO == Half;
6108 bool isUndefHI = NumUndefsHI == Half;
6109 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6110 isUndefLO, isUndefHI);
6117 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6120 MVT VT = Op.getSimpleValueType();
6121 MVT ExtVT = VT.getVectorElementType();
6122 unsigned NumElems = Op.getNumOperands();
6124 // Generate vectors for predicate vectors.
6125 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6126 return LowerBUILD_VECTORvXi1(Op, DAG);
6128 // Vectors containing all zeros can be matched by pxor and xorps later
6129 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6130 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6131 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6132 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6135 return getZeroVector(VT, Subtarget, DAG, dl);
6138 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6139 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6140 // vpcmpeqd on 256-bit vectors.
6141 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6142 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6145 if (!VT.is512BitVector())
6146 return getOnesVector(VT, Subtarget, DAG, dl);
6149 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6150 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6152 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6153 return HorizontalOp;
6154 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6157 unsigned EVTBits = ExtVT.getSizeInBits();
6159 unsigned NumZero = 0;
6160 unsigned NumNonZero = 0;
6161 unsigned NonZeros = 0;
6162 bool IsAllConstants = true;
6163 SmallSet<SDValue, 8> Values;
6164 for (unsigned i = 0; i < NumElems; ++i) {
6165 SDValue Elt = Op.getOperand(i);
6166 if (Elt.getOpcode() == ISD::UNDEF)
6169 if (Elt.getOpcode() != ISD::Constant &&
6170 Elt.getOpcode() != ISD::ConstantFP)
6171 IsAllConstants = false;
6172 if (X86::isZeroNode(Elt))
6175 NonZeros |= (1 << i);
6180 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6181 if (NumNonZero == 0)
6182 return DAG.getUNDEF(VT);
6184 // Special case for single non-zero, non-undef, element.
6185 if (NumNonZero == 1) {
6186 unsigned Idx = countTrailingZeros(NonZeros);
6187 SDValue Item = Op.getOperand(Idx);
6189 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6190 // the value are obviously zero, truncate the value to i32 and do the
6191 // insertion that way. Only do this if the value is non-constant or if the
6192 // value is a constant being inserted into element 0. It is cheaper to do
6193 // a constant pool load than it is to do a movd + shuffle.
6194 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6195 (!IsAllConstants || Idx == 0)) {
6196 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6198 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6199 MVT VecVT = MVT::v4i32;
6201 // Truncate the value (which may itself be a constant) to i32, and
6202 // convert it to a vector with movd (S2V+shuffle to zero extend).
6203 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6204 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6205 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6206 Item, Idx * 2, true, Subtarget, DAG));
6210 // If we have a constant or non-constant insertion into the low element of
6211 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6212 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6213 // depending on what the source datatype is.
6216 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6218 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6219 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6220 if (VT.is512BitVector()) {
6221 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6222 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6223 Item, DAG.getIntPtrConstant(0, dl));
6225 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6226 "Expected an SSE value type!");
6227 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6228 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6229 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6232 // We can't directly insert an i8 or i16 into a vector, so zero extend
6234 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6235 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6236 if (VT.is256BitVector()) {
6237 if (Subtarget->hasAVX()) {
6238 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6239 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6241 // Without AVX, we need to extend to a 128-bit vector and then
6242 // insert into the 256-bit vector.
6243 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6244 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6245 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6248 assert(VT.is128BitVector() && "Expected an SSE value type!");
6249 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6250 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6252 return DAG.getBitcast(VT, Item);
6256 // Is it a vector logical left shift?
6257 if (NumElems == 2 && Idx == 1 &&
6258 X86::isZeroNode(Op.getOperand(0)) &&
6259 !X86::isZeroNode(Op.getOperand(1))) {
6260 unsigned NumBits = VT.getSizeInBits();
6261 return getVShift(true, VT,
6262 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6263 VT, Op.getOperand(1)),
6264 NumBits/2, DAG, *this, dl);
6267 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6270 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6271 // is a non-constant being inserted into an element other than the low one,
6272 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6273 // movd/movss) to move this into the low element, then shuffle it into
6275 if (EVTBits == 32) {
6276 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6277 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6281 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6282 if (Values.size() == 1) {
6283 if (EVTBits == 32) {
6284 // Instead of a shuffle like this:
6285 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6286 // Check if it's possible to issue this instead.
6287 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6288 unsigned Idx = countTrailingZeros(NonZeros);
6289 SDValue Item = Op.getOperand(Idx);
6290 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6291 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6296 // A vector full of immediates; various special cases are already
6297 // handled, so this is best done with a single constant-pool load.
6301 // For AVX-length vectors, see if we can use a vector load to get all of the
6302 // elements, otherwise build the individual 128-bit pieces and use
6303 // shuffles to put them in place.
6304 if (VT.is256BitVector() || VT.is512BitVector()) {
6305 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6307 // Check for a build vector of consecutive loads.
6308 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6311 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6313 // Build both the lower and upper subvector.
6314 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6315 makeArrayRef(&V[0], NumElems/2));
6316 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6317 makeArrayRef(&V[NumElems / 2], NumElems/2));
6319 // Recreate the wider vector with the lower and upper part.
6320 if (VT.is256BitVector())
6321 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6322 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6325 // Let legalizer expand 2-wide build_vectors.
6326 if (EVTBits == 64) {
6327 if (NumNonZero == 1) {
6328 // One half is zero or undef.
6329 unsigned Idx = countTrailingZeros(NonZeros);
6330 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6331 Op.getOperand(Idx));
6332 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6337 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6338 if (EVTBits == 8 && NumElems == 16)
6339 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6343 if (EVTBits == 16 && NumElems == 8)
6344 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6348 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6349 if (EVTBits == 32 && NumElems == 4)
6350 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6353 // If element VT is == 32 bits, turn it into a number of shuffles.
6354 SmallVector<SDValue, 8> V(NumElems);
6355 if (NumElems == 4 && NumZero > 0) {
6356 for (unsigned i = 0; i < 4; ++i) {
6357 bool isZero = !(NonZeros & (1 << i));
6359 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6361 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6364 for (unsigned i = 0; i < 2; ++i) {
6365 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6368 V[i] = V[i*2]; // Must be a zero vector.
6371 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6374 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6377 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6382 bool Reverse1 = (NonZeros & 0x3) == 2;
6383 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6387 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6388 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6390 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6393 if (Values.size() > 1 && VT.is128BitVector()) {
6394 // Check for a build vector of consecutive loads.
6395 for (unsigned i = 0; i < NumElems; ++i)
6396 V[i] = Op.getOperand(i);
6398 // Check for elements which are consecutive loads.
6399 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6402 // Check for a build vector from mostly shuffle plus few inserting.
6403 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6406 // For SSE 4.1, use insertps to put the high elements into the low element.
6407 if (Subtarget->hasSSE41()) {
6409 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6410 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6412 Result = DAG.getUNDEF(VT);
6414 for (unsigned i = 1; i < NumElems; ++i) {
6415 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6416 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6417 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6422 // Otherwise, expand into a number of unpckl*, start by extending each of
6423 // our (non-undef) elements to the full vector width with the element in the
6424 // bottom slot of the vector (which generates no code for SSE).
6425 for (unsigned i = 0; i < NumElems; ++i) {
6426 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6427 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6429 V[i] = DAG.getUNDEF(VT);
6432 // Next, we iteratively mix elements, e.g. for v4f32:
6433 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6434 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6435 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6436 unsigned EltStride = NumElems >> 1;
6437 while (EltStride != 0) {
6438 for (unsigned i = 0; i < EltStride; ++i) {
6439 // If V[i+EltStride] is undef and this is the first round of mixing,
6440 // then it is safe to just drop this shuffle: V[i] is already in the
6441 // right place, the one element (since it's the first round) being
6442 // inserted as undef can be dropped. This isn't safe for successive
6443 // rounds because they will permute elements within both vectors.
6444 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6445 EltStride == NumElems/2)
6448 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6457 // 256-bit AVX can use the vinsertf128 instruction
6458 // to create 256-bit vectors from two other 128-bit ones.
6459 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6461 MVT ResVT = Op.getSimpleValueType();
6463 assert((ResVT.is256BitVector() ||
6464 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6466 SDValue V1 = Op.getOperand(0);
6467 SDValue V2 = Op.getOperand(1);
6468 unsigned NumElems = ResVT.getVectorNumElements();
6469 if (ResVT.is256BitVector())
6470 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6472 if (Op.getNumOperands() == 4) {
6473 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6474 ResVT.getVectorNumElements()/2);
6475 SDValue V3 = Op.getOperand(2);
6476 SDValue V4 = Op.getOperand(3);
6477 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6478 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6480 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6483 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6484 const X86Subtarget *Subtarget,
6485 SelectionDAG & DAG) {
6487 MVT ResVT = Op.getSimpleValueType();
6488 unsigned NumOfOperands = Op.getNumOperands();
6490 assert(isPowerOf2_32(NumOfOperands) &&
6491 "Unexpected number of operands in CONCAT_VECTORS");
6493 if (NumOfOperands > 2) {
6494 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6495 ResVT.getVectorNumElements()/2);
6496 SmallVector<SDValue, 2> Ops;
6497 for (unsigned i = 0; i < NumOfOperands/2; i++)
6498 Ops.push_back(Op.getOperand(i));
6499 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6501 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6502 Ops.push_back(Op.getOperand(i));
6503 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6504 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6507 SDValue V1 = Op.getOperand(0);
6508 SDValue V2 = Op.getOperand(1);
6509 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6510 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6512 if (IsZeroV1 && IsZeroV2)
6513 return getZeroVector(ResVT, Subtarget, DAG, dl);
6515 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6516 SDValue Undef = DAG.getUNDEF(ResVT);
6517 unsigned NumElems = ResVT.getVectorNumElements();
6518 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6520 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6521 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6525 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6526 // Zero the upper bits of V1
6527 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6528 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6531 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6534 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6535 const X86Subtarget *Subtarget,
6536 SelectionDAG &DAG) {
6537 MVT VT = Op.getSimpleValueType();
6538 if (VT.getVectorElementType() == MVT::i1)
6539 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6541 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6542 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6543 Op.getNumOperands() == 4)));
6545 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6546 // from two other 128-bit ones.
6548 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6549 return LowerAVXCONCAT_VECTORS(Op, DAG);
6552 //===----------------------------------------------------------------------===//
6553 // Vector shuffle lowering
6555 // This is an experimental code path for lowering vector shuffles on x86. It is
6556 // designed to handle arbitrary vector shuffles and blends, gracefully
6557 // degrading performance as necessary. It works hard to recognize idiomatic
6558 // shuffles and lower them to optimal instruction patterns without leaving
6559 // a framework that allows reasonably efficient handling of all vector shuffle
6561 //===----------------------------------------------------------------------===//
6563 /// \brief Tiny helper function to identify a no-op mask.
6565 /// This is a somewhat boring predicate function. It checks whether the mask
6566 /// array input, which is assumed to be a single-input shuffle mask of the kind
6567 /// used by the X86 shuffle instructions (not a fully general
6568 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6569 /// in-place shuffle are 'no-op's.
6570 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6571 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6572 if (Mask[i] != -1 && Mask[i] != i)
6577 /// \brief Helper function to classify a mask as a single-input mask.
6579 /// This isn't a generic single-input test because in the vector shuffle
6580 /// lowering we canonicalize single inputs to be the first input operand. This
6581 /// means we can more quickly test for a single input by only checking whether
6582 /// an input from the second operand exists. We also assume that the size of
6583 /// mask corresponds to the size of the input vectors which isn't true in the
6584 /// fully general case.
6585 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6587 if (M >= (int)Mask.size())
6592 /// \brief Test whether there are elements crossing 128-bit lanes in this
6595 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6596 /// and we routinely test for these.
6597 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6598 int LaneSize = 128 / VT.getScalarSizeInBits();
6599 int Size = Mask.size();
6600 for (int i = 0; i < Size; ++i)
6601 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6606 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6608 /// This checks a shuffle mask to see if it is performing the same
6609 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6610 /// that it is also not lane-crossing. It may however involve a blend from the
6611 /// same lane of a second vector.
6613 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6614 /// non-trivial to compute in the face of undef lanes. The representation is
6615 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6616 /// entries from both V1 and V2 inputs to the wider mask.
6618 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6619 SmallVectorImpl<int> &RepeatedMask) {
6620 int LaneSize = 128 / VT.getScalarSizeInBits();
6621 RepeatedMask.resize(LaneSize, -1);
6622 int Size = Mask.size();
6623 for (int i = 0; i < Size; ++i) {
6626 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6627 // This entry crosses lanes, so there is no way to model this shuffle.
6630 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6631 if (RepeatedMask[i % LaneSize] == -1)
6632 // This is the first non-undef entry in this slot of a 128-bit lane.
6633 RepeatedMask[i % LaneSize] =
6634 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6635 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6636 // Found a mismatch with the repeated mask.
6642 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6645 /// This is a fast way to test a shuffle mask against a fixed pattern:
6647 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6649 /// It returns true if the mask is exactly as wide as the argument list, and
6650 /// each element of the mask is either -1 (signifying undef) or the value given
6651 /// in the argument.
6652 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6653 ArrayRef<int> ExpectedMask) {
6654 if (Mask.size() != ExpectedMask.size())
6657 int Size = Mask.size();
6659 // If the values are build vectors, we can look through them to find
6660 // equivalent inputs that make the shuffles equivalent.
6661 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6662 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6664 for (int i = 0; i < Size; ++i)
6665 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6666 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6667 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6668 if (!MaskBV || !ExpectedBV ||
6669 MaskBV->getOperand(Mask[i] % Size) !=
6670 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6677 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6679 /// This helper function produces an 8-bit shuffle immediate corresponding to
6680 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6681 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6684 /// NB: We rely heavily on "undef" masks preserving the input lane.
6685 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6686 SelectionDAG &DAG) {
6687 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6688 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6689 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6690 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6691 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6694 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6695 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6696 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6697 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6698 return DAG.getConstant(Imm, DL, MVT::i8);
6701 /// \brief Compute whether each element of a shuffle is zeroable.
6703 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6704 /// Either it is an undef element in the shuffle mask, the element of the input
6705 /// referenced is undef, or the element of the input referenced is known to be
6706 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6707 /// as many lanes with this technique as possible to simplify the remaining
6709 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6710 SDValue V1, SDValue V2) {
6711 SmallBitVector Zeroable(Mask.size(), false);
6713 while (V1.getOpcode() == ISD::BITCAST)
6714 V1 = V1->getOperand(0);
6715 while (V2.getOpcode() == ISD::BITCAST)
6716 V2 = V2->getOperand(0);
6718 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6719 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6721 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6723 // Handle the easy cases.
6724 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6729 // If this is an index into a build_vector node (which has the same number
6730 // of elements), dig out the input value and use it.
6731 SDValue V = M < Size ? V1 : V2;
6732 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6735 SDValue Input = V.getOperand(M % Size);
6736 // The UNDEF opcode check really should be dead code here, but not quite
6737 // worth asserting on (it isn't invalid, just unexpected).
6738 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6745 // X86 has dedicated unpack instructions that can handle specific blend
6746 // operations: UNPCKH and UNPCKL.
6747 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6748 SDValue V1, SDValue V2,
6749 SelectionDAG &DAG) {
6750 int NumElts = VT.getVectorNumElements();
6751 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6752 SmallVector<int, 8> Unpckl;
6753 SmallVector<int, 8> Unpckh;
6755 for (int i = 0; i < NumElts; ++i) {
6756 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6757 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6758 int HiPos = LoPos + NumEltsInLane / 2;
6759 Unpckl.push_back(LoPos);
6760 Unpckh.push_back(HiPos);
6763 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6764 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6765 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6766 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6768 // Commute and try again.
6769 ShuffleVectorSDNode::commuteMask(Unpckl);
6770 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6771 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6773 ShuffleVectorSDNode::commuteMask(Unpckh);
6774 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6775 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6780 /// \brief Try to emit a bitmask instruction for a shuffle.
6782 /// This handles cases where we can model a blend exactly as a bitmask due to
6783 /// one of the inputs being zeroable.
6784 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6785 SDValue V2, ArrayRef<int> Mask,
6786 SelectionDAG &DAG) {
6787 MVT EltVT = VT.getVectorElementType();
6788 int NumEltBits = EltVT.getSizeInBits();
6789 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6790 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6791 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6793 if (EltVT.isFloatingPoint()) {
6794 Zero = DAG.getBitcast(EltVT, Zero);
6795 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6797 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6798 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6800 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6803 if (Mask[i] % Size != i)
6804 return SDValue(); // Not a blend.
6806 V = Mask[i] < Size ? V1 : V2;
6807 else if (V != (Mask[i] < Size ? V1 : V2))
6808 return SDValue(); // Can only let one input through the mask.
6810 VMaskOps[i] = AllOnes;
6813 return SDValue(); // No non-zeroable elements!
6815 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6816 V = DAG.getNode(VT.isFloatingPoint()
6817 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6822 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6824 /// This is used as a fallback approach when first class blend instructions are
6825 /// unavailable. Currently it is only suitable for integer vectors, but could
6826 /// be generalized for floating point vectors if desirable.
6827 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6828 SDValue V2, ArrayRef<int> Mask,
6829 SelectionDAG &DAG) {
6830 assert(VT.isInteger() && "Only supports integer vector types!");
6831 MVT EltVT = VT.getVectorElementType();
6832 int NumEltBits = EltVT.getSizeInBits();
6833 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6834 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6836 SmallVector<SDValue, 16> MaskOps;
6837 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6838 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6839 return SDValue(); // Shuffled input!
6840 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6843 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6844 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6845 // We have to cast V2 around.
6846 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6847 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6848 DAG.getBitcast(MaskVT, V1Mask),
6849 DAG.getBitcast(MaskVT, V2)));
6850 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6853 /// \brief Try to emit a blend instruction for a shuffle.
6855 /// This doesn't do any checks for the availability of instructions for blending
6856 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6857 /// be matched in the backend with the type given. What it does check for is
6858 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6859 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6860 SDValue V2, ArrayRef<int> Original,
6861 const X86Subtarget *Subtarget,
6862 SelectionDAG &DAG) {
6863 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6864 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6865 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6866 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6867 bool ForceV1Zero = false, ForceV2Zero = false;
6869 // Attempt to generate the binary blend mask. If an input is zero then
6870 // we can use any lane.
6871 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6872 unsigned BlendMask = 0;
6873 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6879 if (M == i + Size) {
6880 BlendMask |= 1u << i;
6891 BlendMask |= 1u << i;
6896 return SDValue(); // Shuffled input!
6899 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
6901 V1 = getZeroVector(VT, Subtarget, DAG, DL);
6903 V2 = getZeroVector(VT, Subtarget, DAG, DL);
6905 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
6906 unsigned ScaledMask = 0;
6907 for (int i = 0; i != Size; ++i)
6908 if (BlendMask & (1u << i))
6909 for (int j = 0; j != Scale; ++j)
6910 ScaledMask |= 1u << (i * Scale + j);
6914 switch (VT.SimpleTy) {
6919 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6920 DAG.getConstant(BlendMask, DL, MVT::i8));
6924 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6928 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6929 // that instruction.
6930 if (Subtarget->hasAVX2()) {
6931 // Scale the blend by the number of 32-bit dwords per element.
6932 int Scale = VT.getScalarSizeInBits() / 32;
6933 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6934 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6935 V1 = DAG.getBitcast(BlendVT, V1);
6936 V2 = DAG.getBitcast(BlendVT, V2);
6937 return DAG.getBitcast(
6938 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6939 DAG.getConstant(BlendMask, DL, MVT::i8)));
6943 // For integer shuffles we need to expand the mask and cast the inputs to
6944 // v8i16s prior to blending.
6945 int Scale = 8 / VT.getVectorNumElements();
6946 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6947 V1 = DAG.getBitcast(MVT::v8i16, V1);
6948 V2 = DAG.getBitcast(MVT::v8i16, V2);
6949 return DAG.getBitcast(VT,
6950 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6951 DAG.getConstant(BlendMask, DL, MVT::i8)));
6955 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6956 SmallVector<int, 8> RepeatedMask;
6957 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6958 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6959 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6961 for (int i = 0; i < 8; ++i)
6962 if (RepeatedMask[i] >= 16)
6963 BlendMask |= 1u << i;
6964 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6965 DAG.getConstant(BlendMask, DL, MVT::i8));
6971 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
6972 "256-bit byte-blends require AVX2 support!");
6974 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6975 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6978 // Scale the blend by the number of bytes per element.
6979 int Scale = VT.getScalarSizeInBits() / 8;
6981 // This form of blend is always done on bytes. Compute the byte vector
6983 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6985 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6986 // mix of LLVM's code generator and the x86 backend. We tell the code
6987 // generator that boolean values in the elements of an x86 vector register
6988 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6989 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6990 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6991 // of the element (the remaining are ignored) and 0 in that high bit would
6992 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6993 // the LLVM model for boolean values in vector elements gets the relevant
6994 // bit set, it is set backwards and over constrained relative to x86's
6996 SmallVector<SDValue, 32> VSELECTMask;
6997 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6998 for (int j = 0; j < Scale; ++j)
6999 VSELECTMask.push_back(
7000 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7001 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7004 V1 = DAG.getBitcast(BlendVT, V1);
7005 V2 = DAG.getBitcast(BlendVT, V2);
7006 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7007 DAG.getNode(ISD::BUILD_VECTOR, DL,
7008 BlendVT, VSELECTMask),
7013 llvm_unreachable("Not a supported integer vector type!");
7017 /// \brief Try to lower as a blend of elements from two inputs followed by
7018 /// a single-input permutation.
7020 /// This matches the pattern where we can blend elements from two inputs and
7021 /// then reduce the shuffle to a single-input permutation.
7022 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7025 SelectionDAG &DAG) {
7026 // We build up the blend mask while checking whether a blend is a viable way
7027 // to reduce the shuffle.
7028 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7029 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7031 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7035 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7037 if (BlendMask[Mask[i] % Size] == -1)
7038 BlendMask[Mask[i] % Size] = Mask[i];
7039 else if (BlendMask[Mask[i] % Size] != Mask[i])
7040 return SDValue(); // Can't blend in the needed input!
7042 PermuteMask[i] = Mask[i] % Size;
7045 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7046 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7049 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7050 /// blends and permutes.
7052 /// This matches the extremely common pattern for handling combined
7053 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7054 /// operations. It will try to pick the best arrangement of shuffles and
7056 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7060 SelectionDAG &DAG) {
7061 // Shuffle the input elements into the desired positions in V1 and V2 and
7062 // blend them together.
7063 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7064 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7065 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7066 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7067 if (Mask[i] >= 0 && Mask[i] < Size) {
7068 V1Mask[i] = Mask[i];
7070 } else if (Mask[i] >= Size) {
7071 V2Mask[i] = Mask[i] - Size;
7072 BlendMask[i] = i + Size;
7075 // Try to lower with the simpler initial blend strategy unless one of the
7076 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7077 // shuffle may be able to fold with a load or other benefit. However, when
7078 // we'll have to do 2x as many shuffles in order to achieve this, blending
7079 // first is a better strategy.
7080 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7081 if (SDValue BlendPerm =
7082 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7085 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7086 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7087 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7090 /// \brief Try to lower a vector shuffle as a byte rotation.
7092 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7093 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7094 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7095 /// try to generically lower a vector shuffle through such an pattern. It
7096 /// does not check for the profitability of lowering either as PALIGNR or
7097 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7098 /// This matches shuffle vectors that look like:
7100 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7102 /// Essentially it concatenates V1 and V2, shifts right by some number of
7103 /// elements, and takes the low elements as the result. Note that while this is
7104 /// specified as a *right shift* because x86 is little-endian, it is a *left
7105 /// rotate* of the vector lanes.
7106 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7109 const X86Subtarget *Subtarget,
7110 SelectionDAG &DAG) {
7111 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7113 int NumElts = Mask.size();
7114 int NumLanes = VT.getSizeInBits() / 128;
7115 int NumLaneElts = NumElts / NumLanes;
7117 // We need to detect various ways of spelling a rotation:
7118 // [11, 12, 13, 14, 15, 0, 1, 2]
7119 // [-1, 12, 13, 14, -1, -1, 1, -1]
7120 // [-1, -1, -1, -1, -1, -1, 1, 2]
7121 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7122 // [-1, 4, 5, 6, -1, -1, 9, -1]
7123 // [-1, 4, 5, 6, -1, -1, -1, -1]
7126 for (int l = 0; l < NumElts; l += NumLaneElts) {
7127 for (int i = 0; i < NumLaneElts; ++i) {
7128 if (Mask[l + i] == -1)
7130 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7132 // Get the mod-Size index and lane correct it.
7133 int LaneIdx = (Mask[l + i] % NumElts) - l;
7134 // Make sure it was in this lane.
7135 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7138 // Determine where a rotated vector would have started.
7139 int StartIdx = i - LaneIdx;
7141 // The identity rotation isn't interesting, stop.
7144 // If we found the tail of a vector the rotation must be the missing
7145 // front. If we found the head of a vector, it must be how much of the
7147 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7150 Rotation = CandidateRotation;
7151 else if (Rotation != CandidateRotation)
7152 // The rotations don't match, so we can't match this mask.
7155 // Compute which value this mask is pointing at.
7156 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7158 // Compute which of the two target values this index should be assigned
7159 // to. This reflects whether the high elements are remaining or the low
7160 // elements are remaining.
7161 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7163 // Either set up this value if we've not encountered it before, or check
7164 // that it remains consistent.
7167 else if (TargetV != MaskV)
7168 // This may be a rotation, but it pulls from the inputs in some
7169 // unsupported interleaving.
7174 // Check that we successfully analyzed the mask, and normalize the results.
7175 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7176 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7182 // The actual rotate instruction rotates bytes, so we need to scale the
7183 // rotation based on how many bytes are in the vector lane.
7184 int Scale = 16 / NumLaneElts;
7186 // SSSE3 targets can use the palignr instruction.
7187 if (Subtarget->hasSSSE3()) {
7188 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7189 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7190 Lo = DAG.getBitcast(AlignVT, Lo);
7191 Hi = DAG.getBitcast(AlignVT, Hi);
7193 return DAG.getBitcast(
7194 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7195 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7198 assert(VT.is128BitVector() &&
7199 "Rotate-based lowering only supports 128-bit lowering!");
7200 assert(Mask.size() <= 16 &&
7201 "Can shuffle at most 16 bytes in a 128-bit vector!");
7203 // Default SSE2 implementation
7204 int LoByteShift = 16 - Rotation * Scale;
7205 int HiByteShift = Rotation * Scale;
7207 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7208 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7209 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7211 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7212 DAG.getConstant(LoByteShift, DL, MVT::i8));
7213 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7214 DAG.getConstant(HiByteShift, DL, MVT::i8));
7215 return DAG.getBitcast(VT,
7216 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7219 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7221 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7222 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7223 /// matches elements from one of the input vectors shuffled to the left or
7224 /// right with zeroable elements 'shifted in'. It handles both the strictly
7225 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7228 /// PSHL : (little-endian) left bit shift.
7229 /// [ zz, 0, zz, 2 ]
7230 /// [ -1, 4, zz, -1 ]
7231 /// PSRL : (little-endian) right bit shift.
7233 /// [ -1, -1, 7, zz]
7234 /// PSLLDQ : (little-endian) left byte shift
7235 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7236 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7237 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7238 /// PSRLDQ : (little-endian) right byte shift
7239 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7240 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7241 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7242 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7243 SDValue V2, ArrayRef<int> Mask,
7244 SelectionDAG &DAG) {
7245 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7247 int Size = Mask.size();
7248 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7250 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7251 for (int i = 0; i < Size; i += Scale)
7252 for (int j = 0; j < Shift; ++j)
7253 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7259 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7260 for (int i = 0; i != Size; i += Scale) {
7261 unsigned Pos = Left ? i + Shift : i;
7262 unsigned Low = Left ? i : i + Shift;
7263 unsigned Len = Scale - Shift;
7264 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7265 Low + (V == V1 ? 0 : Size)))
7269 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7270 bool ByteShift = ShiftEltBits > 64;
7271 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7272 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7273 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7275 // Normalize the scale for byte shifts to still produce an i64 element
7277 Scale = ByteShift ? Scale / 2 : Scale;
7279 // We need to round trip through the appropriate type for the shift.
7280 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7281 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7282 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7283 "Illegal integer vector type");
7284 V = DAG.getBitcast(ShiftVT, V);
7286 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7287 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7288 return DAG.getBitcast(VT, V);
7291 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7292 // keep doubling the size of the integer elements up to that. We can
7293 // then shift the elements of the integer vector by whole multiples of
7294 // their width within the elements of the larger integer vector. Test each
7295 // multiple to see if we can find a match with the moved element indices
7296 // and that the shifted in elements are all zeroable.
7297 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7298 for (int Shift = 1; Shift != Scale; ++Shift)
7299 for (bool Left : {true, false})
7300 if (CheckZeros(Shift, Scale, Left))
7301 for (SDValue V : {V1, V2})
7302 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7309 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7310 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7311 SDValue V2, ArrayRef<int> Mask,
7312 SelectionDAG &DAG) {
7313 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7314 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7316 int Size = Mask.size();
7317 int HalfSize = Size / 2;
7318 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7320 // Upper half must be undefined.
7321 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7324 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7325 // Remainder of lower half result is zero and upper half is all undef.
7326 auto LowerAsEXTRQ = [&]() {
7327 // Determine the extraction length from the part of the
7328 // lower half that isn't zeroable.
7330 for (; Len > 0; --Len)
7331 if (!Zeroable[Len - 1])
7333 assert(Len > 0 && "Zeroable shuffle mask");
7335 // Attempt to match first Len sequential elements from the lower half.
7338 for (int i = 0; i != Len; ++i) {
7342 SDValue &V = (M < Size ? V1 : V2);
7345 // All mask elements must be in the lower half.
7349 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7360 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7361 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7362 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7363 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7364 DAG.getConstant(BitLen, DL, MVT::i8),
7365 DAG.getConstant(BitIdx, DL, MVT::i8));
7368 if (SDValue ExtrQ = LowerAsEXTRQ())
7371 // INSERTQ: Extract lowest Len elements from lower half of second source and
7372 // insert over first source, starting at Idx.
7373 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7374 auto LowerAsInsertQ = [&]() {
7375 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7378 // Attempt to match first source from mask before insertion point.
7379 if (isUndefInRange(Mask, 0, Idx)) {
7381 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7383 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7389 // Extend the extraction length looking to match both the insertion of
7390 // the second source and the remaining elements of the first.
7391 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7396 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7398 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7404 // Match the remaining elements of the lower half.
7405 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7407 } else if ((!Base || (Base == V1)) &&
7408 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7410 } else if ((!Base || (Base == V2)) &&
7411 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7418 // We may not have a base (first source) - this can safely be undefined.
7420 Base = DAG.getUNDEF(VT);
7422 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7423 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7424 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7425 DAG.getConstant(BitLen, DL, MVT::i8),
7426 DAG.getConstant(BitIdx, DL, MVT::i8));
7433 if (SDValue InsertQ = LowerAsInsertQ())
7439 /// \brief Lower a vector shuffle as a zero or any extension.
7441 /// Given a specific number of elements, element bit width, and extension
7442 /// stride, produce either a zero or any extension based on the available
7443 /// features of the subtarget. The extended elements are consecutive and
7444 /// begin and can start from an offseted element index in the input; to
7445 /// avoid excess shuffling the offset must either being in the bottom lane
7446 /// or at the start of a higher lane. All extended elements must be from
7448 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7449 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7450 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7451 assert(Scale > 1 && "Need a scale to extend.");
7452 int EltBits = VT.getScalarSizeInBits();
7453 int NumElements = VT.getVectorNumElements();
7454 int NumEltsPerLane = 128 / EltBits;
7455 int OffsetLane = Offset / NumEltsPerLane;
7456 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7457 "Only 8, 16, and 32 bit elements can be extended.");
7458 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7459 assert(0 <= Offset && "Extension offset must be positive.");
7460 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7461 "Extension offset must be in the first lane or start an upper lane.");
7463 // Check that an index is in same lane as the base offset.
7464 auto SafeOffset = [&](int Idx) {
7465 return OffsetLane == (Idx / NumEltsPerLane);
7468 // Shift along an input so that the offset base moves to the first element.
7469 auto ShuffleOffset = [&](SDValue V) {
7473 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7474 for (int i = 0; i * Scale < NumElements; ++i) {
7475 int SrcIdx = i + Offset;
7476 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7478 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7481 // Found a valid zext mask! Try various lowering strategies based on the
7482 // input type and available ISA extensions.
7483 if (Subtarget->hasSSE41()) {
7484 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7485 // PUNPCK will catch this in a later shuffle match.
7486 if (Offset && Scale == 2 && VT.is128BitVector())
7488 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7489 NumElements / Scale);
7490 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7491 return DAG.getBitcast(VT, InputV);
7494 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7496 // For any extends we can cheat for larger element sizes and use shuffle
7497 // instructions that can fold with a load and/or copy.
7498 if (AnyExt && EltBits == 32) {
7499 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7501 return DAG.getBitcast(
7502 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7503 DAG.getBitcast(MVT::v4i32, InputV),
7504 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7506 if (AnyExt && EltBits == 16 && Scale > 2) {
7507 int PSHUFDMask[4] = {Offset / 2, -1,
7508 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7509 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7510 DAG.getBitcast(MVT::v4i32, InputV),
7511 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7512 int PSHUFWMask[4] = {1, -1, -1, -1};
7513 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7514 return DAG.getBitcast(
7515 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7516 DAG.getBitcast(MVT::v8i16, InputV),
7517 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7520 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7522 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7523 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7524 assert(VT.is128BitVector() && "Unexpected vector width!");
7526 int LoIdx = Offset * EltBits;
7527 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7528 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7529 DAG.getConstant(EltBits, DL, MVT::i8),
7530 DAG.getConstant(LoIdx, DL, MVT::i8)));
7532 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7533 !SafeOffset(Offset + 1))
7534 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7536 int HiIdx = (Offset + 1) * EltBits;
7537 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7538 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7539 DAG.getConstant(EltBits, DL, MVT::i8),
7540 DAG.getConstant(HiIdx, DL, MVT::i8)));
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7545 // If this would require more than 2 unpack instructions to expand, use
7546 // pshufb when available. We can only use more than 2 unpack instructions
7547 // when zero extending i8 elements which also makes it easier to use pshufb.
7548 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7549 assert(NumElements == 16 && "Unexpected byte vector width!");
7550 SDValue PSHUFBMask[16];
7551 for (int i = 0; i < 16; ++i) {
7552 int Idx = Offset + (i / Scale);
7553 PSHUFBMask[i] = DAG.getConstant(
7554 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7556 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7557 return DAG.getBitcast(VT,
7558 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7559 DAG.getNode(ISD::BUILD_VECTOR, DL,
7560 MVT::v16i8, PSHUFBMask)));
7563 // If we are extending from an offset, ensure we start on a boundary that
7564 // we can unpack from.
7565 int AlignToUnpack = Offset % (NumElements / Scale);
7566 if (AlignToUnpack) {
7567 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7568 for (int i = AlignToUnpack; i < NumElements; ++i)
7569 ShMask[i - AlignToUnpack] = i;
7570 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7571 Offset -= AlignToUnpack;
7574 // Otherwise emit a sequence of unpacks.
7576 unsigned UnpackLoHi = X86ISD::UNPCKL;
7577 if (Offset >= (NumElements / 2)) {
7578 UnpackLoHi = X86ISD::UNPCKH;
7579 Offset -= (NumElements / 2);
7582 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7583 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7584 : getZeroVector(InputVT, Subtarget, DAG, DL);
7585 InputV = DAG.getBitcast(InputVT, InputV);
7586 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7590 } while (Scale > 1);
7591 return DAG.getBitcast(VT, InputV);
7594 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7596 /// This routine will try to do everything in its power to cleverly lower
7597 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7598 /// check for the profitability of this lowering, it tries to aggressively
7599 /// match this pattern. It will use all of the micro-architectural details it
7600 /// can to emit an efficient lowering. It handles both blends with all-zero
7601 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7602 /// masking out later).
7604 /// The reason we have dedicated lowering for zext-style shuffles is that they
7605 /// are both incredibly common and often quite performance sensitive.
7606 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7607 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7608 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7609 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7611 int Bits = VT.getSizeInBits();
7612 int NumLanes = Bits / 128;
7613 int NumElements = VT.getVectorNumElements();
7614 int NumEltsPerLane = NumElements / NumLanes;
7615 assert(VT.getScalarSizeInBits() <= 32 &&
7616 "Exceeds 32-bit integer zero extension limit");
7617 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7619 // Define a helper function to check a particular ext-scale and lower to it if
7621 auto Lower = [&](int Scale) -> SDValue {
7626 for (int i = 0; i < NumElements; ++i) {
7629 continue; // Valid anywhere but doesn't tell us anything.
7630 if (i % Scale != 0) {
7631 // Each of the extended elements need to be zeroable.
7635 // We no longer are in the anyext case.
7640 // Each of the base elements needs to be consecutive indices into the
7641 // same input vector.
7642 SDValue V = M < NumElements ? V1 : V2;
7643 M = M % NumElements;
7646 Offset = M - (i / Scale);
7647 } else if (InputV != V)
7648 return SDValue(); // Flip-flopping inputs.
7650 // Offset must start in the lowest 128-bit lane or at the start of an
7652 // FIXME: Is it ever worth allowing a negative base offset?
7653 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7654 (Offset % NumEltsPerLane) == 0))
7657 // If we are offsetting, all referenced entries must come from the same
7659 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7662 if ((M % NumElements) != (Offset + (i / Scale)))
7663 return SDValue(); // Non-consecutive strided elements.
7667 // If we fail to find an input, we have a zero-shuffle which should always
7668 // have already been handled.
7669 // FIXME: Maybe handle this here in case during blending we end up with one?
7673 // If we are offsetting, don't extend if we only match a single input, we
7674 // can always do better by using a basic PSHUF or PUNPCK.
7675 if (Offset != 0 && Matches < 2)
7678 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7679 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7682 // The widest scale possible for extending is to a 64-bit integer.
7683 assert(Bits % 64 == 0 &&
7684 "The number of bits in a vector must be divisible by 64 on x86!");
7685 int NumExtElements = Bits / 64;
7687 // Each iteration, try extending the elements half as much, but into twice as
7689 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7690 assert(NumElements % NumExtElements == 0 &&
7691 "The input vector size must be divisible by the extended size.");
7692 if (SDValue V = Lower(NumElements / NumExtElements))
7696 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7700 // Returns one of the source operands if the shuffle can be reduced to a
7701 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7702 auto CanZExtLowHalf = [&]() {
7703 for (int i = NumElements / 2; i != NumElements; ++i)
7706 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7708 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7713 if (SDValue V = CanZExtLowHalf()) {
7714 V = DAG.getBitcast(MVT::v2i64, V);
7715 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7716 return DAG.getBitcast(VT, V);
7719 // No viable ext lowering found.
7723 /// \brief Try to get a scalar value for a specific element of a vector.
7725 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7726 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7727 SelectionDAG &DAG) {
7728 MVT VT = V.getSimpleValueType();
7729 MVT EltVT = VT.getVectorElementType();
7730 while (V.getOpcode() == ISD::BITCAST)
7731 V = V.getOperand(0);
7732 // If the bitcasts shift the element size, we can't extract an equivalent
7734 MVT NewVT = V.getSimpleValueType();
7735 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7738 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7739 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7740 // Ensure the scalar operand is the same size as the destination.
7741 // FIXME: Add support for scalar truncation where possible.
7742 SDValue S = V.getOperand(Idx);
7743 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7744 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7750 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7752 /// This is particularly important because the set of instructions varies
7753 /// significantly based on whether the operand is a load or not.
7754 static bool isShuffleFoldableLoad(SDValue V) {
7755 while (V.getOpcode() == ISD::BITCAST)
7756 V = V.getOperand(0);
7758 return ISD::isNON_EXTLoad(V.getNode());
7761 /// \brief Try to lower insertion of a single element into a zero vector.
7763 /// This is a common pattern that we have especially efficient patterns to lower
7764 /// across all subtarget feature sets.
7765 static SDValue lowerVectorShuffleAsElementInsertion(
7766 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7767 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7768 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7770 MVT EltVT = VT.getVectorElementType();
7772 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7773 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7775 bool IsV1Zeroable = true;
7776 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7777 if (i != V2Index && !Zeroable[i]) {
7778 IsV1Zeroable = false;
7782 // Check for a single input from a SCALAR_TO_VECTOR node.
7783 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7784 // all the smarts here sunk into that routine. However, the current
7785 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7786 // vector shuffle lowering is dead.
7787 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7789 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7790 // We need to zext the scalar if it is smaller than an i32.
7791 V2S = DAG.getBitcast(EltVT, V2S);
7792 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7793 // Using zext to expand a narrow element won't work for non-zero
7798 // Zero-extend directly to i32.
7800 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7802 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7803 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7804 EltVT == MVT::i16) {
7805 // Either not inserting from the low element of the input or the input
7806 // element size is too small to use VZEXT_MOVL to clear the high bits.
7810 if (!IsV1Zeroable) {
7811 // If V1 can't be treated as a zero vector we have fewer options to lower
7812 // this. We can't support integer vectors or non-zero targets cheaply, and
7813 // the V1 elements can't be permuted in any way.
7814 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7815 if (!VT.isFloatingPoint() || V2Index != 0)
7817 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7818 V1Mask[V2Index] = -1;
7819 if (!isNoopShuffleMask(V1Mask))
7821 // This is essentially a special case blend operation, but if we have
7822 // general purpose blend operations, they are always faster. Bail and let
7823 // the rest of the lowering handle these as blends.
7824 if (Subtarget->hasSSE41())
7827 // Otherwise, use MOVSD or MOVSS.
7828 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7829 "Only two types of floating point element types to handle!");
7830 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7834 // This lowering only works for the low element with floating point vectors.
7835 if (VT.isFloatingPoint() && V2Index != 0)
7838 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7840 V2 = DAG.getBitcast(VT, V2);
7843 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7844 // the desired position. Otherwise it is more efficient to do a vector
7845 // shift left. We know that we can do a vector shift left because all
7846 // the inputs are zero.
7847 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7848 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7849 V2Shuffle[V2Index] = 0;
7850 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7852 V2 = DAG.getBitcast(MVT::v2i64, V2);
7854 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7855 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7856 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7857 DAG.getDataLayout(), VT)));
7858 V2 = DAG.getBitcast(VT, V2);
7864 /// \brief Try to lower broadcast of a single - truncated - integer element,
7865 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7867 /// This assumes we have AVX2.
7868 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7870 const X86Subtarget *Subtarget,
7871 SelectionDAG &DAG) {
7872 assert(Subtarget->hasAVX2() &&
7873 "We can only lower integer broadcasts with AVX2!");
7875 EVT EltVT = VT.getVectorElementType();
7876 EVT V0VT = V0.getValueType();
7878 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7879 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7881 EVT V0EltVT = V0VT.getVectorElementType();
7882 if (!V0EltVT.isInteger())
7885 const unsigned EltSize = EltVT.getSizeInBits();
7886 const unsigned V0EltSize = V0EltVT.getSizeInBits();
7888 // This is only a truncation if the original element type is larger.
7889 if (V0EltSize <= EltSize)
7892 assert(((V0EltSize % EltSize) == 0) &&
7893 "Scalar type sizes must all be powers of 2 on x86!");
7895 const unsigned V0Opc = V0.getOpcode();
7896 const unsigned Scale = V0EltSize / EltSize;
7897 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
7899 // If we're extracting non-least-significant bits, this isn't a truncation.
7900 if (BroadcastIdx % Scale)
7903 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
7904 V0Opc != ISD::BUILD_VECTOR)
7907 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
7908 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
7909 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
7912 /// \brief Try to lower broadcast of a single element.
7914 /// For convenience, this code also bundles all of the subtarget feature set
7915 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7916 /// a convenient way to factor it out.
7917 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7919 const X86Subtarget *Subtarget,
7920 SelectionDAG &DAG) {
7921 if (!Subtarget->hasAVX())
7923 if (VT.isInteger() && !Subtarget->hasAVX2())
7926 // Check that the mask is a broadcast.
7927 int BroadcastIdx = -1;
7929 if (M >= 0 && BroadcastIdx == -1)
7931 else if (M >= 0 && M != BroadcastIdx)
7934 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7935 "a sorted mask where the broadcast "
7938 // Go up the chain of (vector) values to find a scalar load that we can
7939 // combine with the broadcast.
7941 switch (V.getOpcode()) {
7942 case ISD::CONCAT_VECTORS: {
7943 int OperandSize = Mask.size() / V.getNumOperands();
7944 V = V.getOperand(BroadcastIdx / OperandSize);
7945 BroadcastIdx %= OperandSize;
7949 case ISD::INSERT_SUBVECTOR: {
7950 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7951 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7955 int BeginIdx = (int)ConstantIdx->getZExtValue();
7957 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
7958 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7959 BroadcastIdx -= BeginIdx;
7970 // Check if this is a broadcast of a scalar. We special case lowering
7971 // for scalars so that we can more effectively fold with loads.
7972 // First, look through bitcast: if the original value has a larger element
7973 // type than the shuffle, the broadcast element is in essence truncated.
7974 // Make that explicit to ease folding.
7975 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
7976 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
7977 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
7978 return TruncBroadcast;
7980 // Also check the simpler case, where we can directly reuse the scalar.
7981 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7982 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7983 V = V.getOperand(BroadcastIdx);
7985 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7986 // Only AVX2 has register broadcasts.
7987 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7989 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7990 // We can't broadcast from a vector register without AVX2, and we can only
7991 // broadcast from the zero-element of a vector register.
7995 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7998 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7999 // INSERTPS when the V1 elements are already in the correct locations
8000 // because otherwise we can just always use two SHUFPS instructions which
8001 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8002 // perform INSERTPS if a single V1 element is out of place and all V2
8003 // elements are zeroable.
8004 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8006 SelectionDAG &DAG) {
8007 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8008 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8009 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8010 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8012 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8015 int V1DstIndex = -1;
8016 int V2DstIndex = -1;
8017 bool V1UsedInPlace = false;
8019 for (int i = 0; i < 4; ++i) {
8020 // Synthesize a zero mask from the zeroable elements (includes undefs).
8026 // Flag if we use any V1 inputs in place.
8028 V1UsedInPlace = true;
8032 // We can only insert a single non-zeroable element.
8033 if (V1DstIndex != -1 || V2DstIndex != -1)
8037 // V1 input out of place for insertion.
8040 // V2 input for insertion.
8045 // Don't bother if we have no (non-zeroable) element for insertion.
8046 if (V1DstIndex == -1 && V2DstIndex == -1)
8049 // Determine element insertion src/dst indices. The src index is from the
8050 // start of the inserted vector, not the start of the concatenated vector.
8051 unsigned V2SrcIndex = 0;
8052 if (V1DstIndex != -1) {
8053 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8054 // and don't use the original V2 at all.
8055 V2SrcIndex = Mask[V1DstIndex];
8056 V2DstIndex = V1DstIndex;
8059 V2SrcIndex = Mask[V2DstIndex] - 4;
8062 // If no V1 inputs are used in place, then the result is created only from
8063 // the zero mask and the V2 insertion - so remove V1 dependency.
8065 V1 = DAG.getUNDEF(MVT::v4f32);
8067 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8068 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8070 // Insert the V2 element into the desired position.
8072 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8073 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8076 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8077 /// UNPCK instruction.
8079 /// This specifically targets cases where we end up with alternating between
8080 /// the two inputs, and so can permute them into something that feeds a single
8081 /// UNPCK instruction. Note that this routine only targets integer vectors
8082 /// because for floating point vectors we have a generalized SHUFPS lowering
8083 /// strategy that handles everything that doesn't *exactly* match an unpack,
8084 /// making this clever lowering unnecessary.
8085 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8086 SDValue V1, SDValue V2,
8088 SelectionDAG &DAG) {
8089 assert(!VT.isFloatingPoint() &&
8090 "This routine only supports integer vectors.");
8091 assert(!isSingleInputShuffleMask(Mask) &&
8092 "This routine should only be used when blending two inputs.");
8093 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8095 int Size = Mask.size();
8097 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8098 return M >= 0 && M % Size < Size / 2;
8100 int NumHiInputs = std::count_if(
8101 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8103 bool UnpackLo = NumLoInputs >= NumHiInputs;
8105 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8106 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8107 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8109 for (int i = 0; i < Size; ++i) {
8113 // Each element of the unpack contains Scale elements from this mask.
8114 int UnpackIdx = i / Scale;
8116 // We only handle the case where V1 feeds the first slots of the unpack.
8117 // We rely on canonicalization to ensure this is the case.
8118 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8121 // Setup the mask for this input. The indexing is tricky as we have to
8122 // handle the unpack stride.
8123 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8124 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8128 // If we will have to shuffle both inputs to use the unpack, check whether
8129 // we can just unpack first and shuffle the result. If so, skip this unpack.
8130 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8131 !isNoopShuffleMask(V2Mask))
8134 // Shuffle the inputs into place.
8135 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8136 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8138 // Cast the inputs to the type we will use to unpack them.
8139 V1 = DAG.getBitcast(UnpackVT, V1);
8140 V2 = DAG.getBitcast(UnpackVT, V2);
8142 // Unpack the inputs and cast the result back to the desired type.
8143 return DAG.getBitcast(
8144 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8148 // We try each unpack from the largest to the smallest to try and find one
8149 // that fits this mask.
8150 int OrigNumElements = VT.getVectorNumElements();
8151 int OrigScalarSize = VT.getScalarSizeInBits();
8152 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8153 int Scale = ScalarSize / OrigScalarSize;
8154 int NumElements = OrigNumElements / Scale;
8155 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8156 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8160 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8162 if (NumLoInputs == 0 || NumHiInputs == 0) {
8163 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8164 "We have to have *some* inputs!");
8165 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8167 // FIXME: We could consider the total complexity of the permute of each
8168 // possible unpacking. Or at the least we should consider how many
8169 // half-crossings are created.
8170 // FIXME: We could consider commuting the unpacks.
8172 SmallVector<int, 32> PermMask;
8173 PermMask.assign(Size, -1);
8174 for (int i = 0; i < Size; ++i) {
8178 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8181 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8183 return DAG.getVectorShuffle(
8184 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8186 DAG.getUNDEF(VT), PermMask);
8192 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8194 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8195 /// support for floating point shuffles but not integer shuffles. These
8196 /// instructions will incur a domain crossing penalty on some chips though so
8197 /// it is better to avoid lowering through this for integer vectors where
8199 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8200 const X86Subtarget *Subtarget,
8201 SelectionDAG &DAG) {
8203 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8204 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8205 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8207 ArrayRef<int> Mask = SVOp->getMask();
8208 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8210 if (isSingleInputShuffleMask(Mask)) {
8211 // Use low duplicate instructions for masks that match their pattern.
8212 if (Subtarget->hasSSE3())
8213 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8214 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8216 // Straight shuffle of a single input vector. Simulate this by using the
8217 // single input as both of the "inputs" to this instruction..
8218 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8220 if (Subtarget->hasAVX()) {
8221 // If we have AVX, we can use VPERMILPS which will allow folding a load
8222 // into the shuffle.
8223 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8224 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8227 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8228 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8230 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8231 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8233 // If we have a single input, insert that into V1 if we can do so cheaply.
8234 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8235 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8236 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8238 // Try inverting the insertion since for v2 masks it is easy to do and we
8239 // can't reliably sort the mask one way or the other.
8240 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8241 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8242 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8243 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8247 // Try to use one of the special instruction patterns to handle two common
8248 // blend patterns if a zero-blend above didn't work.
8249 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8250 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8251 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8252 // We can either use a special instruction to load over the low double or
8253 // to move just the low double.
8255 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8257 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8259 if (Subtarget->hasSSE41())
8260 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8264 // Use dedicated unpack instructions for masks that match their pattern.
8266 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8269 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8270 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8271 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8274 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8276 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8277 /// the integer unit to minimize domain crossing penalties. However, for blends
8278 /// it falls back to the floating point shuffle operation with appropriate bit
8280 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8281 const X86Subtarget *Subtarget,
8282 SelectionDAG &DAG) {
8284 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8285 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8286 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8287 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8288 ArrayRef<int> Mask = SVOp->getMask();
8289 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8291 if (isSingleInputShuffleMask(Mask)) {
8292 // Check for being able to broadcast a single element.
8293 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8294 Mask, Subtarget, DAG))
8297 // Straight shuffle of a single input vector. For everything from SSE2
8298 // onward this has a single fast instruction with no scary immediates.
8299 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8300 V1 = DAG.getBitcast(MVT::v4i32, V1);
8301 int WidenedMask[4] = {
8302 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8303 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8304 return DAG.getBitcast(
8306 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8307 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8309 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8310 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8311 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8312 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8314 // If we have a blend of two PACKUS operations an the blend aligns with the
8315 // low and half halves, we can just merge the PACKUS operations. This is
8316 // particularly important as it lets us merge shuffles that this routine itself
8318 auto GetPackNode = [](SDValue V) {
8319 while (V.getOpcode() == ISD::BITCAST)
8320 V = V.getOperand(0);
8322 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8324 if (SDValue V1Pack = GetPackNode(V1))
8325 if (SDValue V2Pack = GetPackNode(V2))
8326 return DAG.getBitcast(MVT::v2i64,
8327 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8328 Mask[0] == 0 ? V1Pack.getOperand(0)
8329 : V1Pack.getOperand(1),
8330 Mask[1] == 2 ? V2Pack.getOperand(0)
8331 : V2Pack.getOperand(1)));
8333 // Try to use shift instructions.
8335 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8338 // When loading a scalar and then shuffling it into a vector we can often do
8339 // the insertion cheaply.
8340 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8341 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8343 // Try inverting the insertion since for v2 masks it is easy to do and we
8344 // can't reliably sort the mask one way or the other.
8345 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8346 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8347 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8350 // We have different paths for blend lowering, but they all must use the
8351 // *exact* same predicate.
8352 bool IsBlendSupported = Subtarget->hasSSE41();
8353 if (IsBlendSupported)
8354 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8358 // Use dedicated unpack instructions for masks that match their pattern.
8360 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8363 // Try to use byte rotation instructions.
8364 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8365 if (Subtarget->hasSSSE3())
8366 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8367 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8370 // If we have direct support for blends, we should lower by decomposing into
8371 // a permute. That will be faster than the domain cross.
8372 if (IsBlendSupported)
8373 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8376 // We implement this with SHUFPD which is pretty lame because it will likely
8377 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8378 // However, all the alternatives are still more cycles and newer chips don't
8379 // have this problem. It would be really nice if x86 had better shuffles here.
8380 V1 = DAG.getBitcast(MVT::v2f64, V1);
8381 V2 = DAG.getBitcast(MVT::v2f64, V2);
8382 return DAG.getBitcast(MVT::v2i64,
8383 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8386 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8388 /// This is used to disable more specialized lowerings when the shufps lowering
8389 /// will happen to be efficient.
8390 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8391 // This routine only handles 128-bit shufps.
8392 assert(Mask.size() == 4 && "Unsupported mask size!");
8394 // To lower with a single SHUFPS we need to have the low half and high half
8395 // each requiring a single input.
8396 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8398 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8404 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8406 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8407 /// It makes no assumptions about whether this is the *best* lowering, it simply
8409 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8410 ArrayRef<int> Mask, SDValue V1,
8411 SDValue V2, SelectionDAG &DAG) {
8412 SDValue LowV = V1, HighV = V2;
8413 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8416 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8418 if (NumV2Elements == 1) {
8420 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8423 // Compute the index adjacent to V2Index and in the same half by toggling
8425 int V2AdjIndex = V2Index ^ 1;
8427 if (Mask[V2AdjIndex] == -1) {
8428 // Handles all the cases where we have a single V2 element and an undef.
8429 // This will only ever happen in the high lanes because we commute the
8430 // vector otherwise.
8432 std::swap(LowV, HighV);
8433 NewMask[V2Index] -= 4;
8435 // Handle the case where the V2 element ends up adjacent to a V1 element.
8436 // To make this work, blend them together as the first step.
8437 int V1Index = V2AdjIndex;
8438 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8439 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8440 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8442 // Now proceed to reconstruct the final blend as we have the necessary
8443 // high or low half formed.
8450 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8451 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8453 } else if (NumV2Elements == 2) {
8454 if (Mask[0] < 4 && Mask[1] < 4) {
8455 // Handle the easy case where we have V1 in the low lanes and V2 in the
8459 } else if (Mask[2] < 4 && Mask[3] < 4) {
8460 // We also handle the reversed case because this utility may get called
8461 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8462 // arrange things in the right direction.
8468 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8469 // trying to place elements directly, just blend them and set up the final
8470 // shuffle to place them.
8472 // The first two blend mask elements are for V1, the second two are for
8474 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8475 Mask[2] < 4 ? Mask[2] : Mask[3],
8476 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8477 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8478 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8479 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8481 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8484 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8485 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8486 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8487 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8490 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8491 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8494 /// \brief Lower 4-lane 32-bit floating point shuffles.
8496 /// Uses instructions exclusively from the floating point unit to minimize
8497 /// domain crossing penalties, as these are sufficient to implement all v4f32
8499 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8500 const X86Subtarget *Subtarget,
8501 SelectionDAG &DAG) {
8503 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8504 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8505 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8506 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8507 ArrayRef<int> Mask = SVOp->getMask();
8508 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8511 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8513 if (NumV2Elements == 0) {
8514 // Check for being able to broadcast a single element.
8515 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8516 Mask, Subtarget, DAG))
8519 // Use even/odd duplicate instructions for masks that match their pattern.
8520 if (Subtarget->hasSSE3()) {
8521 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8522 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8523 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8524 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8527 if (Subtarget->hasAVX()) {
8528 // If we have AVX, we can use VPERMILPS which will allow folding a load
8529 // into the shuffle.
8530 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8531 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8534 // Otherwise, use a straight shuffle of a single input vector. We pass the
8535 // input vector to both operands to simulate this with a SHUFPS.
8536 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8537 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8540 // There are special ways we can lower some single-element blends. However, we
8541 // have custom ways we can lower more complex single-element blends below that
8542 // we defer to if both this and BLENDPS fail to match, so restrict this to
8543 // when the V2 input is targeting element 0 of the mask -- that is the fast
8545 if (NumV2Elements == 1 && Mask[0] >= 4)
8546 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8547 Mask, Subtarget, DAG))
8550 if (Subtarget->hasSSE41()) {
8551 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8555 // Use INSERTPS if we can complete the shuffle efficiently.
8556 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8559 if (!isSingleSHUFPSMask(Mask))
8560 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8561 DL, MVT::v4f32, V1, V2, Mask, DAG))
8565 // Use dedicated unpack instructions for masks that match their pattern.
8567 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8570 // Otherwise fall back to a SHUFPS lowering strategy.
8571 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8574 /// \brief Lower 4-lane i32 vector shuffles.
8576 /// We try to handle these with integer-domain shuffles where we can, but for
8577 /// blends we use the floating point domain blend instructions.
8578 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8579 const X86Subtarget *Subtarget,
8580 SelectionDAG &DAG) {
8582 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8583 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8584 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8586 ArrayRef<int> Mask = SVOp->getMask();
8587 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8589 // Whenever we can lower this as a zext, that instruction is strictly faster
8590 // than any alternative. It also allows us to fold memory operands into the
8591 // shuffle in many cases.
8592 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8593 Mask, Subtarget, DAG))
8597 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8599 if (NumV2Elements == 0) {
8600 // Check for being able to broadcast a single element.
8601 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8602 Mask, Subtarget, DAG))
8605 // Straight shuffle of a single input vector. For everything from SSE2
8606 // onward this has a single fast instruction with no scary immediates.
8607 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8608 // but we aren't actually going to use the UNPCK instruction because doing
8609 // so prevents folding a load into this instruction or making a copy.
8610 const int UnpackLoMask[] = {0, 0, 1, 1};
8611 const int UnpackHiMask[] = {2, 2, 3, 3};
8612 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8613 Mask = UnpackLoMask;
8614 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8615 Mask = UnpackHiMask;
8617 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8618 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8621 // Try to use shift instructions.
8623 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8626 // There are special ways we can lower some single-element blends.
8627 if (NumV2Elements == 1)
8628 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8629 Mask, Subtarget, DAG))
8632 // We have different paths for blend lowering, but they all must use the
8633 // *exact* same predicate.
8634 bool IsBlendSupported = Subtarget->hasSSE41();
8635 if (IsBlendSupported)
8636 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8640 if (SDValue Masked =
8641 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8644 // Use dedicated unpack instructions for masks that match their pattern.
8646 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8649 // Try to use byte rotation instructions.
8650 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8651 if (Subtarget->hasSSSE3())
8652 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8653 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8656 // If we have direct support for blends, we should lower by decomposing into
8657 // a permute. That will be faster than the domain cross.
8658 if (IsBlendSupported)
8659 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8662 // Try to lower by permuting the inputs into an unpack instruction.
8663 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8667 // We implement this with SHUFPS because it can blend from two vectors.
8668 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8669 // up the inputs, bypassing domain shift penalties that we would encur if we
8670 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8672 return DAG.getBitcast(
8674 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8675 DAG.getBitcast(MVT::v4f32, V2), Mask));
8678 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8679 /// shuffle lowering, and the most complex part.
8681 /// The lowering strategy is to try to form pairs of input lanes which are
8682 /// targeted at the same half of the final vector, and then use a dword shuffle
8683 /// to place them onto the right half, and finally unpack the paired lanes into
8684 /// their final position.
8686 /// The exact breakdown of how to form these dword pairs and align them on the
8687 /// correct sides is really tricky. See the comments within the function for
8688 /// more of the details.
8690 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8691 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8692 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8693 /// vector, form the analogous 128-bit 8-element Mask.
8694 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8695 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8696 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8697 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8698 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8700 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8701 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8702 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8704 SmallVector<int, 4> LoInputs;
8705 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8706 [](int M) { return M >= 0; });
8707 std::sort(LoInputs.begin(), LoInputs.end());
8708 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8709 SmallVector<int, 4> HiInputs;
8710 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8711 [](int M) { return M >= 0; });
8712 std::sort(HiInputs.begin(), HiInputs.end());
8713 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8715 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8716 int NumHToL = LoInputs.size() - NumLToL;
8718 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8719 int NumHToH = HiInputs.size() - NumLToH;
8720 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8721 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8722 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8723 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8725 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8726 // such inputs we can swap two of the dwords across the half mark and end up
8727 // with <=2 inputs to each half in each half. Once there, we can fall through
8728 // to the generic code below. For example:
8730 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8731 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8733 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8734 // and an existing 2-into-2 on the other half. In this case we may have to
8735 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8736 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8737 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8738 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8739 // half than the one we target for fixing) will be fixed when we re-enter this
8740 // path. We will also combine away any sequence of PSHUFD instructions that
8741 // result into a single instruction. Here is an example of the tricky case:
8743 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8744 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8746 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8748 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8749 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8751 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8752 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8754 // The result is fine to be handled by the generic logic.
8755 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8756 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8757 int AOffset, int BOffset) {
8758 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8759 "Must call this with A having 3 or 1 inputs from the A half.");
8760 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8761 "Must call this with B having 1 or 3 inputs from the B half.");
8762 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8763 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8765 bool ThreeAInputs = AToAInputs.size() == 3;
8767 // Compute the index of dword with only one word among the three inputs in
8768 // a half by taking the sum of the half with three inputs and subtracting
8769 // the sum of the actual three inputs. The difference is the remaining
8772 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8773 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8774 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8775 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8776 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8777 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8778 int TripleNonInputIdx =
8779 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8780 TripleDWord = TripleNonInputIdx / 2;
8782 // We use xor with one to compute the adjacent DWord to whichever one the
8784 OneInputDWord = (OneInput / 2) ^ 1;
8786 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8787 // and BToA inputs. If there is also such a problem with the BToB and AToB
8788 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8789 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8790 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8791 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8792 // Compute how many inputs will be flipped by swapping these DWords. We
8794 // to balance this to ensure we don't form a 3-1 shuffle in the other
8796 int NumFlippedAToBInputs =
8797 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8798 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8799 int NumFlippedBToBInputs =
8800 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8801 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8802 if ((NumFlippedAToBInputs == 1 &&
8803 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8804 (NumFlippedBToBInputs == 1 &&
8805 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8806 // We choose whether to fix the A half or B half based on whether that
8807 // half has zero flipped inputs. At zero, we may not be able to fix it
8808 // with that half. We also bias towards fixing the B half because that
8809 // will more commonly be the high half, and we have to bias one way.
8810 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8811 ArrayRef<int> Inputs) {
8812 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8813 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8814 PinnedIdx ^ 1) != Inputs.end();
8815 // Determine whether the free index is in the flipped dword or the
8816 // unflipped dword based on where the pinned index is. We use this bit
8817 // in an xor to conditionally select the adjacent dword.
8818 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8819 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8820 FixFreeIdx) != Inputs.end();
8821 if (IsFixIdxInput == IsFixFreeIdxInput)
8823 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8824 FixFreeIdx) != Inputs.end();
8825 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8826 "We need to be changing the number of flipped inputs!");
8827 int PSHUFHalfMask[] = {0, 1, 2, 3};
8828 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8829 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8831 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8834 if (M != -1 && M == FixIdx)
8836 else if (M != -1 && M == FixFreeIdx)
8839 if (NumFlippedBToBInputs != 0) {
8841 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8842 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8844 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8845 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8846 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8851 int PSHUFDMask[] = {0, 1, 2, 3};
8852 PSHUFDMask[ADWord] = BDWord;
8853 PSHUFDMask[BDWord] = ADWord;
8856 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8857 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8859 // Adjust the mask to match the new locations of A and B.
8861 if (M != -1 && M/2 == ADWord)
8862 M = 2 * BDWord + M % 2;
8863 else if (M != -1 && M/2 == BDWord)
8864 M = 2 * ADWord + M % 2;
8866 // Recurse back into this routine to re-compute state now that this isn't
8867 // a 3 and 1 problem.
8868 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8871 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8872 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8873 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8874 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8876 // At this point there are at most two inputs to the low and high halves from
8877 // each half. That means the inputs can always be grouped into dwords and
8878 // those dwords can then be moved to the correct half with a dword shuffle.
8879 // We use at most one low and one high word shuffle to collect these paired
8880 // inputs into dwords, and finally a dword shuffle to place them.
8881 int PSHUFLMask[4] = {-1, -1, -1, -1};
8882 int PSHUFHMask[4] = {-1, -1, -1, -1};
8883 int PSHUFDMask[4] = {-1, -1, -1, -1};
8885 // First fix the masks for all the inputs that are staying in their
8886 // original halves. This will then dictate the targets of the cross-half
8888 auto fixInPlaceInputs =
8889 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8890 MutableArrayRef<int> SourceHalfMask,
8891 MutableArrayRef<int> HalfMask, int HalfOffset) {
8892 if (InPlaceInputs.empty())
8894 if (InPlaceInputs.size() == 1) {
8895 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8896 InPlaceInputs[0] - HalfOffset;
8897 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8900 if (IncomingInputs.empty()) {
8901 // Just fix all of the in place inputs.
8902 for (int Input : InPlaceInputs) {
8903 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8904 PSHUFDMask[Input / 2] = Input / 2;
8909 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8910 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8911 InPlaceInputs[0] - HalfOffset;
8912 // Put the second input next to the first so that they are packed into
8913 // a dword. We find the adjacent index by toggling the low bit.
8914 int AdjIndex = InPlaceInputs[0] ^ 1;
8915 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8916 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8917 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8919 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8920 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8922 // Now gather the cross-half inputs and place them into a free dword of
8923 // their target half.
8924 // FIXME: This operation could almost certainly be simplified dramatically to
8925 // look more like the 3-1 fixing operation.
8926 auto moveInputsToRightHalf = [&PSHUFDMask](
8927 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8928 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8929 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8931 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8932 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8934 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8936 int LowWord = Word & ~1;
8937 int HighWord = Word | 1;
8938 return isWordClobbered(SourceHalfMask, LowWord) ||
8939 isWordClobbered(SourceHalfMask, HighWord);
8942 if (IncomingInputs.empty())
8945 if (ExistingInputs.empty()) {
8946 // Map any dwords with inputs from them into the right half.
8947 for (int Input : IncomingInputs) {
8948 // If the source half mask maps over the inputs, turn those into
8949 // swaps and use the swapped lane.
8950 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8951 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8952 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8953 Input - SourceOffset;
8954 // We have to swap the uses in our half mask in one sweep.
8955 for (int &M : HalfMask)
8956 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8958 else if (M == Input)
8959 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8961 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8962 Input - SourceOffset &&
8963 "Previous placement doesn't match!");
8965 // Note that this correctly re-maps both when we do a swap and when
8966 // we observe the other side of the swap above. We rely on that to
8967 // avoid swapping the members of the input list directly.
8968 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8971 // Map the input's dword into the correct half.
8972 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8973 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8975 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8977 "Previous placement doesn't match!");
8980 // And just directly shift any other-half mask elements to be same-half
8981 // as we will have mirrored the dword containing the element into the
8982 // same position within that half.
8983 for (int &M : HalfMask)
8984 if (M >= SourceOffset && M < SourceOffset + 4) {
8985 M = M - SourceOffset + DestOffset;
8986 assert(M >= 0 && "This should never wrap below zero!");
8991 // Ensure we have the input in a viable dword of its current half. This
8992 // is particularly tricky because the original position may be clobbered
8993 // by inputs being moved and *staying* in that half.
8994 if (IncomingInputs.size() == 1) {
8995 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8996 int InputFixed = std::find(std::begin(SourceHalfMask),
8997 std::end(SourceHalfMask), -1) -
8998 std::begin(SourceHalfMask) + SourceOffset;
8999 SourceHalfMask[InputFixed - SourceOffset] =
9000 IncomingInputs[0] - SourceOffset;
9001 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9003 IncomingInputs[0] = InputFixed;
9005 } else if (IncomingInputs.size() == 2) {
9006 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9007 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9008 // We have two non-adjacent or clobbered inputs we need to extract from
9009 // the source half. To do this, we need to map them into some adjacent
9010 // dword slot in the source mask.
9011 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9012 IncomingInputs[1] - SourceOffset};
9014 // If there is a free slot in the source half mask adjacent to one of
9015 // the inputs, place the other input in it. We use (Index XOR 1) to
9016 // compute an adjacent index.
9017 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9018 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9019 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9020 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9021 InputsFixed[1] = InputsFixed[0] ^ 1;
9022 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9023 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9024 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9025 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9026 InputsFixed[0] = InputsFixed[1] ^ 1;
9027 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9028 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9029 // The two inputs are in the same DWord but it is clobbered and the
9030 // adjacent DWord isn't used at all. Move both inputs to the free
9032 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9033 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9034 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9035 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9037 // The only way we hit this point is if there is no clobbering
9038 // (because there are no off-half inputs to this half) and there is no
9039 // free slot adjacent to one of the inputs. In this case, we have to
9040 // swap an input with a non-input.
9041 for (int i = 0; i < 4; ++i)
9042 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9043 "We can't handle any clobbers here!");
9044 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9045 "Cannot have adjacent inputs here!");
9047 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9048 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9050 // We also have to update the final source mask in this case because
9051 // it may need to undo the above swap.
9052 for (int &M : FinalSourceHalfMask)
9053 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9054 M = InputsFixed[1] + SourceOffset;
9055 else if (M == InputsFixed[1] + SourceOffset)
9056 M = (InputsFixed[0] ^ 1) + SourceOffset;
9058 InputsFixed[1] = InputsFixed[0] ^ 1;
9061 // Point everything at the fixed inputs.
9062 for (int &M : HalfMask)
9063 if (M == IncomingInputs[0])
9064 M = InputsFixed[0] + SourceOffset;
9065 else if (M == IncomingInputs[1])
9066 M = InputsFixed[1] + SourceOffset;
9068 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9069 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9072 llvm_unreachable("Unhandled input size!");
9075 // Now hoist the DWord down to the right half.
9076 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9077 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9078 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9079 for (int &M : HalfMask)
9080 for (int Input : IncomingInputs)
9082 M = FreeDWord * 2 + Input % 2;
9084 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9085 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9086 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9087 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9089 // Now enact all the shuffles we've computed to move the inputs into their
9091 if (!isNoopShuffleMask(PSHUFLMask))
9092 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9093 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9094 if (!isNoopShuffleMask(PSHUFHMask))
9095 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9096 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9097 if (!isNoopShuffleMask(PSHUFDMask))
9100 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9101 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9103 // At this point, each half should contain all its inputs, and we can then
9104 // just shuffle them into their final position.
9105 assert(std::count_if(LoMask.begin(), LoMask.end(),
9106 [](int M) { return M >= 4; }) == 0 &&
9107 "Failed to lift all the high half inputs to the low mask!");
9108 assert(std::count_if(HiMask.begin(), HiMask.end(),
9109 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9110 "Failed to lift all the low half inputs to the high mask!");
9112 // Do a half shuffle for the low mask.
9113 if (!isNoopShuffleMask(LoMask))
9114 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9115 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9117 // Do a half shuffle with the high mask after shifting its values down.
9118 for (int &M : HiMask)
9121 if (!isNoopShuffleMask(HiMask))
9122 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9123 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9128 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9129 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9130 SDValue V2, ArrayRef<int> Mask,
9131 SelectionDAG &DAG, bool &V1InUse,
9133 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9139 int Size = Mask.size();
9140 int Scale = 16 / Size;
9141 for (int i = 0; i < 16; ++i) {
9142 if (Mask[i / Scale] == -1) {
9143 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9145 const int ZeroMask = 0x80;
9146 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9148 int V2Idx = Mask[i / Scale] < Size
9150 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9151 if (Zeroable[i / Scale])
9152 V1Idx = V2Idx = ZeroMask;
9153 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9154 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9155 V1InUse |= (ZeroMask != V1Idx);
9156 V2InUse |= (ZeroMask != V2Idx);
9161 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9162 DAG.getBitcast(MVT::v16i8, V1),
9163 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9165 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9166 DAG.getBitcast(MVT::v16i8, V2),
9167 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9169 // If we need shuffled inputs from both, blend the two.
9171 if (V1InUse && V2InUse)
9172 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9174 V = V1InUse ? V1 : V2;
9176 // Cast the result back to the correct type.
9177 return DAG.getBitcast(VT, V);
9180 /// \brief Generic lowering of 8-lane i16 shuffles.
9182 /// This handles both single-input shuffles and combined shuffle/blends with
9183 /// two inputs. The single input shuffles are immediately delegated to
9184 /// a dedicated lowering routine.
9186 /// The blends are lowered in one of three fundamental ways. If there are few
9187 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9188 /// of the input is significantly cheaper when lowered as an interleaving of
9189 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9190 /// halves of the inputs separately (making them have relatively few inputs)
9191 /// and then concatenate them.
9192 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9193 const X86Subtarget *Subtarget,
9194 SelectionDAG &DAG) {
9196 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9197 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9198 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9200 ArrayRef<int> OrigMask = SVOp->getMask();
9201 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9202 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9203 MutableArrayRef<int> Mask(MaskStorage);
9205 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9207 // Whenever we can lower this as a zext, that instruction is strictly faster
9208 // than any alternative.
9209 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9210 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9213 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9215 auto isV2 = [](int M) { return M >= 8; };
9217 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9219 if (NumV2Inputs == 0) {
9220 // Check for being able to broadcast a single element.
9221 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9222 Mask, Subtarget, DAG))
9225 // Try to use shift instructions.
9227 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9230 // Use dedicated unpack instructions for masks that match their pattern.
9232 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9235 // Try to use byte rotation instructions.
9236 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9237 Mask, Subtarget, DAG))
9240 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9244 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9245 "All single-input shuffles should be canonicalized to be V1-input "
9248 // Try to use shift instructions.
9250 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9253 // See if we can use SSE4A Extraction / Insertion.
9254 if (Subtarget->hasSSE4A())
9255 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9258 // There are special ways we can lower some single-element blends.
9259 if (NumV2Inputs == 1)
9260 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9261 Mask, Subtarget, DAG))
9264 // We have different paths for blend lowering, but they all must use the
9265 // *exact* same predicate.
9266 bool IsBlendSupported = Subtarget->hasSSE41();
9267 if (IsBlendSupported)
9268 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9272 if (SDValue Masked =
9273 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9276 // Use dedicated unpack instructions for masks that match their pattern.
9278 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9281 // Try to use byte rotation instructions.
9282 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9283 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9286 if (SDValue BitBlend =
9287 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9290 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9294 // If we can't directly blend but can use PSHUFB, that will be better as it
9295 // can both shuffle and set up the inefficient blend.
9296 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9297 bool V1InUse, V2InUse;
9298 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9302 // We can always bit-blend if we have to so the fallback strategy is to
9303 // decompose into single-input permutes and blends.
9304 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9308 /// \brief Check whether a compaction lowering can be done by dropping even
9309 /// elements and compute how many times even elements must be dropped.
9311 /// This handles shuffles which take every Nth element where N is a power of
9312 /// two. Example shuffle masks:
9314 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9315 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9316 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9317 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9318 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9319 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9321 /// Any of these lanes can of course be undef.
9323 /// This routine only supports N <= 3.
9324 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9327 /// \returns N above, or the number of times even elements must be dropped if
9328 /// there is such a number. Otherwise returns zero.
9329 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9330 // Figure out whether we're looping over two inputs or just one.
9331 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9333 // The modulus for the shuffle vector entries is based on whether this is
9334 // a single input or not.
9335 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9336 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9337 "We should only be called with masks with a power-of-2 size!");
9339 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9341 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9342 // and 2^3 simultaneously. This is because we may have ambiguity with
9343 // partially undef inputs.
9344 bool ViableForN[3] = {true, true, true};
9346 for (int i = 0, e = Mask.size(); i < e; ++i) {
9347 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9352 bool IsAnyViable = false;
9353 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9354 if (ViableForN[j]) {
9357 // The shuffle mask must be equal to (i * 2^N) % M.
9358 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9361 ViableForN[j] = false;
9363 // Early exit if we exhaust the possible powers of two.
9368 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9372 // Return 0 as there is no viable power of two.
9376 /// \brief Generic lowering of v16i8 shuffles.
9378 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9379 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9380 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9381 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9383 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9384 const X86Subtarget *Subtarget,
9385 SelectionDAG &DAG) {
9387 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9388 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9389 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9391 ArrayRef<int> Mask = SVOp->getMask();
9392 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9394 // Try to use shift instructions.
9396 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9399 // Try to use byte rotation instructions.
9400 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9401 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9404 // Try to use a zext lowering.
9405 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9406 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9409 // See if we can use SSE4A Extraction / Insertion.
9410 if (Subtarget->hasSSE4A())
9411 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9415 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9417 // For single-input shuffles, there are some nicer lowering tricks we can use.
9418 if (NumV2Elements == 0) {
9419 // Check for being able to broadcast a single element.
9420 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9421 Mask, Subtarget, DAG))
9424 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9425 // Notably, this handles splat and partial-splat shuffles more efficiently.
9426 // However, it only makes sense if the pre-duplication shuffle simplifies
9427 // things significantly. Currently, this means we need to be able to
9428 // express the pre-duplication shuffle as an i16 shuffle.
9430 // FIXME: We should check for other patterns which can be widened into an
9431 // i16 shuffle as well.
9432 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9433 for (int i = 0; i < 16; i += 2)
9434 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9439 auto tryToWidenViaDuplication = [&]() -> SDValue {
9440 if (!canWidenViaDuplication(Mask))
9442 SmallVector<int, 4> LoInputs;
9443 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9444 [](int M) { return M >= 0 && M < 8; });
9445 std::sort(LoInputs.begin(), LoInputs.end());
9446 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9448 SmallVector<int, 4> HiInputs;
9449 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9450 [](int M) { return M >= 8; });
9451 std::sort(HiInputs.begin(), HiInputs.end());
9452 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9455 bool TargetLo = LoInputs.size() >= HiInputs.size();
9456 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9457 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9459 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9460 SmallDenseMap<int, int, 8> LaneMap;
9461 for (int I : InPlaceInputs) {
9462 PreDupI16Shuffle[I/2] = I/2;
9465 int j = TargetLo ? 0 : 4, je = j + 4;
9466 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9467 // Check if j is already a shuffle of this input. This happens when
9468 // there are two adjacent bytes after we move the low one.
9469 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9470 // If we haven't yet mapped the input, search for a slot into which
9472 while (j < je && PreDupI16Shuffle[j] != -1)
9476 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9479 // Map this input with the i16 shuffle.
9480 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9483 // Update the lane map based on the mapping we ended up with.
9484 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9486 V1 = DAG.getBitcast(
9488 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9489 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9491 // Unpack the bytes to form the i16s that will be shuffled into place.
9492 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9493 MVT::v16i8, V1, V1);
9495 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9496 for (int i = 0; i < 16; ++i)
9497 if (Mask[i] != -1) {
9498 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9499 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9500 if (PostDupI16Shuffle[i / 2] == -1)
9501 PostDupI16Shuffle[i / 2] = MappedMask;
9503 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9504 "Conflicting entrties in the original shuffle!");
9506 return DAG.getBitcast(
9508 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9509 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9511 if (SDValue V = tryToWidenViaDuplication())
9515 if (SDValue Masked =
9516 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9519 // Use dedicated unpack instructions for masks that match their pattern.
9521 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9524 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9525 // with PSHUFB. It is important to do this before we attempt to generate any
9526 // blends but after all of the single-input lowerings. If the single input
9527 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9528 // want to preserve that and we can DAG combine any longer sequences into
9529 // a PSHUFB in the end. But once we start blending from multiple inputs,
9530 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9531 // and there are *very* few patterns that would actually be faster than the
9532 // PSHUFB approach because of its ability to zero lanes.
9534 // FIXME: The only exceptions to the above are blends which are exact
9535 // interleavings with direct instructions supporting them. We currently don't
9536 // handle those well here.
9537 if (Subtarget->hasSSSE3()) {
9538 bool V1InUse = false;
9539 bool V2InUse = false;
9541 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9542 DAG, V1InUse, V2InUse);
9544 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9545 // do so. This avoids using them to handle blends-with-zero which is
9546 // important as a single pshufb is significantly faster for that.
9547 if (V1InUse && V2InUse) {
9548 if (Subtarget->hasSSE41())
9549 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9550 Mask, Subtarget, DAG))
9553 // We can use an unpack to do the blending rather than an or in some
9554 // cases. Even though the or may be (very minorly) more efficient, we
9555 // preference this lowering because there are common cases where part of
9556 // the complexity of the shuffles goes away when we do the final blend as
9558 // FIXME: It might be worth trying to detect if the unpack-feeding
9559 // shuffles will both be pshufb, in which case we shouldn't bother with
9561 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9562 DL, MVT::v16i8, V1, V2, Mask, DAG))
9569 // There are special ways we can lower some single-element blends.
9570 if (NumV2Elements == 1)
9571 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9572 Mask, Subtarget, DAG))
9575 if (SDValue BitBlend =
9576 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9579 // Check whether a compaction lowering can be done. This handles shuffles
9580 // which take every Nth element for some even N. See the helper function for
9583 // We special case these as they can be particularly efficiently handled with
9584 // the PACKUSB instruction on x86 and they show up in common patterns of
9585 // rearranging bytes to truncate wide elements.
9586 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9587 // NumEvenDrops is the power of two stride of the elements. Another way of
9588 // thinking about it is that we need to drop the even elements this many
9589 // times to get the original input.
9590 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9592 // First we need to zero all the dropped bytes.
9593 assert(NumEvenDrops <= 3 &&
9594 "No support for dropping even elements more than 3 times.");
9595 // We use the mask type to pick which bytes are preserved based on how many
9596 // elements are dropped.
9597 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9598 SDValue ByteClearMask = DAG.getBitcast(
9599 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9600 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9602 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9604 // Now pack things back together.
9605 V1 = DAG.getBitcast(MVT::v8i16, V1);
9606 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9607 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9608 for (int i = 1; i < NumEvenDrops; ++i) {
9609 Result = DAG.getBitcast(MVT::v8i16, Result);
9610 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9616 // Handle multi-input cases by blending single-input shuffles.
9617 if (NumV2Elements > 0)
9618 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9621 // The fallback path for single-input shuffles widens this into two v8i16
9622 // vectors with unpacks, shuffles those, and then pulls them back together
9626 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9627 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9628 for (int i = 0; i < 16; ++i)
9630 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9632 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9634 SDValue VLoHalf, VHiHalf;
9635 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9636 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9638 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9639 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9640 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9641 [](int M) { return M >= 0 && M % 2 == 1; })) {
9642 // Use a mask to drop the high bytes.
9643 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9644 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9645 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9647 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9648 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9650 // Squash the masks to point directly into VLoHalf.
9651 for (int &M : LoBlendMask)
9654 for (int &M : HiBlendMask)
9658 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9659 // VHiHalf so that we can blend them as i16s.
9660 VLoHalf = DAG.getBitcast(
9661 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9662 VHiHalf = DAG.getBitcast(
9663 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9666 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9667 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9669 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9672 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9674 /// This routine breaks down the specific type of 128-bit shuffle and
9675 /// dispatches to the lowering routines accordingly.
9676 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9677 MVT VT, const X86Subtarget *Subtarget,
9678 SelectionDAG &DAG) {
9679 switch (VT.SimpleTy) {
9681 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9683 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9685 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9687 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9689 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9691 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9694 llvm_unreachable("Unimplemented!");
9698 /// \brief Helper function to test whether a shuffle mask could be
9699 /// simplified by widening the elements being shuffled.
9701 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9702 /// leaves it in an unspecified state.
9704 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9705 /// shuffle masks. The latter have the special property of a '-2' representing
9706 /// a zero-ed lane of a vector.
9707 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9708 SmallVectorImpl<int> &WidenedMask) {
9709 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9710 // If both elements are undef, its trivial.
9711 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9712 WidenedMask.push_back(SM_SentinelUndef);
9716 // Check for an undef mask and a mask value properly aligned to fit with
9717 // a pair of values. If we find such a case, use the non-undef mask's value.
9718 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9719 WidenedMask.push_back(Mask[i + 1] / 2);
9722 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9723 WidenedMask.push_back(Mask[i] / 2);
9727 // When zeroing, we need to spread the zeroing across both lanes to widen.
9728 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9729 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9730 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9731 WidenedMask.push_back(SM_SentinelZero);
9737 // Finally check if the two mask values are adjacent and aligned with
9739 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9740 WidenedMask.push_back(Mask[i] / 2);
9744 // Otherwise we can't safely widen the elements used in this shuffle.
9747 assert(WidenedMask.size() == Mask.size() / 2 &&
9748 "Incorrect size of mask after widening the elements!");
9753 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9755 /// This routine just extracts two subvectors, shuffles them independently, and
9756 /// then concatenates them back together. This should work effectively with all
9757 /// AVX vector shuffle types.
9758 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9759 SDValue V2, ArrayRef<int> Mask,
9760 SelectionDAG &DAG) {
9761 assert(VT.getSizeInBits() >= 256 &&
9762 "Only for 256-bit or wider vector shuffles!");
9763 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9764 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9766 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9767 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9769 int NumElements = VT.getVectorNumElements();
9770 int SplitNumElements = NumElements / 2;
9771 MVT ScalarVT = VT.getVectorElementType();
9772 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9774 // Rather than splitting build-vectors, just build two narrower build
9775 // vectors. This helps shuffling with splats and zeros.
9776 auto SplitVector = [&](SDValue V) {
9777 while (V.getOpcode() == ISD::BITCAST)
9778 V = V->getOperand(0);
9780 MVT OrigVT = V.getSimpleValueType();
9781 int OrigNumElements = OrigVT.getVectorNumElements();
9782 int OrigSplitNumElements = OrigNumElements / 2;
9783 MVT OrigScalarVT = OrigVT.getVectorElementType();
9784 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9788 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9790 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9791 DAG.getIntPtrConstant(0, DL));
9792 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9793 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9796 SmallVector<SDValue, 16> LoOps, HiOps;
9797 for (int i = 0; i < OrigSplitNumElements; ++i) {
9798 LoOps.push_back(BV->getOperand(i));
9799 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9801 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9802 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9804 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9805 DAG.getBitcast(SplitVT, HiV));
9808 SDValue LoV1, HiV1, LoV2, HiV2;
9809 std::tie(LoV1, HiV1) = SplitVector(V1);
9810 std::tie(LoV2, HiV2) = SplitVector(V2);
9812 // Now create two 4-way blends of these half-width vectors.
9813 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9814 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9815 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9816 for (int i = 0; i < SplitNumElements; ++i) {
9817 int M = HalfMask[i];
9818 if (M >= NumElements) {
9819 if (M >= NumElements + SplitNumElements)
9823 V2BlendMask.push_back(M - NumElements);
9824 V1BlendMask.push_back(-1);
9825 BlendMask.push_back(SplitNumElements + i);
9826 } else if (M >= 0) {
9827 if (M >= SplitNumElements)
9831 V2BlendMask.push_back(-1);
9832 V1BlendMask.push_back(M);
9833 BlendMask.push_back(i);
9835 V2BlendMask.push_back(-1);
9836 V1BlendMask.push_back(-1);
9837 BlendMask.push_back(-1);
9841 // Because the lowering happens after all combining takes place, we need to
9842 // manually combine these blend masks as much as possible so that we create
9843 // a minimal number of high-level vector shuffle nodes.
9845 // First try just blending the halves of V1 or V2.
9846 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9847 return DAG.getUNDEF(SplitVT);
9848 if (!UseLoV2 && !UseHiV2)
9849 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9850 if (!UseLoV1 && !UseHiV1)
9851 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9853 SDValue V1Blend, V2Blend;
9854 if (UseLoV1 && UseHiV1) {
9856 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9858 // We only use half of V1 so map the usage down into the final blend mask.
9859 V1Blend = UseLoV1 ? LoV1 : HiV1;
9860 for (int i = 0; i < SplitNumElements; ++i)
9861 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9862 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9864 if (UseLoV2 && UseHiV2) {
9866 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9868 // We only use half of V2 so map the usage down into the final blend mask.
9869 V2Blend = UseLoV2 ? LoV2 : HiV2;
9870 for (int i = 0; i < SplitNumElements; ++i)
9871 if (BlendMask[i] >= SplitNumElements)
9872 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9874 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9876 SDValue Lo = HalfBlend(LoMask);
9877 SDValue Hi = HalfBlend(HiMask);
9878 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9881 /// \brief Either split a vector in halves or decompose the shuffles and the
9884 /// This is provided as a good fallback for many lowerings of non-single-input
9885 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9886 /// between splitting the shuffle into 128-bit components and stitching those
9887 /// back together vs. extracting the single-input shuffles and blending those
9889 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9890 SDValue V2, ArrayRef<int> Mask,
9891 SelectionDAG &DAG) {
9892 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9893 "lower single-input shuffles as it "
9894 "could then recurse on itself.");
9895 int Size = Mask.size();
9897 // If this can be modeled as a broadcast of two elements followed by a blend,
9898 // prefer that lowering. This is especially important because broadcasts can
9899 // often fold with memory operands.
9900 auto DoBothBroadcast = [&] {
9901 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9904 if (V2BroadcastIdx == -1)
9905 V2BroadcastIdx = M - Size;
9906 else if (M - Size != V2BroadcastIdx)
9908 } else if (M >= 0) {
9909 if (V1BroadcastIdx == -1)
9911 else if (M != V1BroadcastIdx)
9916 if (DoBothBroadcast())
9917 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9920 // If the inputs all stem from a single 128-bit lane of each input, then we
9921 // split them rather than blending because the split will decompose to
9922 // unusually few instructions.
9923 int LaneCount = VT.getSizeInBits() / 128;
9924 int LaneSize = Size / LaneCount;
9925 SmallBitVector LaneInputs[2];
9926 LaneInputs[0].resize(LaneCount, false);
9927 LaneInputs[1].resize(LaneCount, false);
9928 for (int i = 0; i < Size; ++i)
9930 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9931 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9932 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9934 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9935 // that the decomposed single-input shuffles don't end up here.
9936 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9939 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9940 /// a permutation and blend of those lanes.
9942 /// This essentially blends the out-of-lane inputs to each lane into the lane
9943 /// from a permuted copy of the vector. This lowering strategy results in four
9944 /// instructions in the worst case for a single-input cross lane shuffle which
9945 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9946 /// of. Special cases for each particular shuffle pattern should be handled
9947 /// prior to trying this lowering.
9948 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9949 SDValue V1, SDValue V2,
9951 SelectionDAG &DAG) {
9952 // FIXME: This should probably be generalized for 512-bit vectors as well.
9953 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
9954 int LaneSize = Mask.size() / 2;
9956 // If there are only inputs from one 128-bit lane, splitting will in fact be
9957 // less expensive. The flags track whether the given lane contains an element
9958 // that crosses to another lane.
9959 bool LaneCrossing[2] = {false, false};
9960 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9961 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9962 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9963 if (!LaneCrossing[0] || !LaneCrossing[1])
9964 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9966 if (isSingleInputShuffleMask(Mask)) {
9967 SmallVector<int, 32> FlippedBlendMask;
9968 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9969 FlippedBlendMask.push_back(
9970 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9972 : Mask[i] % LaneSize +
9973 (i / LaneSize) * LaneSize + Size));
9975 // Flip the vector, and blend the results which should now be in-lane. The
9976 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9977 // 5 for the high source. The value 3 selects the high half of source 2 and
9978 // the value 2 selects the low half of source 2. We only use source 2 to
9979 // allow folding it into a memory operand.
9980 unsigned PERMMask = 3 | 2 << 4;
9981 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9982 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9983 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9986 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9987 // will be handled by the above logic and a blend of the results, much like
9988 // other patterns in AVX.
9989 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9992 /// \brief Handle lowering 2-lane 128-bit shuffles.
9993 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9994 SDValue V2, ArrayRef<int> Mask,
9995 const X86Subtarget *Subtarget,
9996 SelectionDAG &DAG) {
9997 // TODO: If minimizing size and one of the inputs is a zero vector and the
9998 // the zero vector has only one use, we could use a VPERM2X128 to save the
9999 // instruction bytes needed to explicitly generate the zero vector.
10001 // Blends are faster and handle all the non-lane-crossing cases.
10002 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10006 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10007 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10009 // If either input operand is a zero vector, use VPERM2X128 because its mask
10010 // allows us to replace the zero input with an implicit zero.
10011 if (!IsV1Zero && !IsV2Zero) {
10012 // Check for patterns which can be matched with a single insert of a 128-bit
10014 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10015 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10016 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10017 VT.getVectorNumElements() / 2);
10018 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10019 DAG.getIntPtrConstant(0, DL));
10020 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10021 OnlyUsesV1 ? V1 : V2,
10022 DAG.getIntPtrConstant(0, DL));
10023 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10027 // Otherwise form a 128-bit permutation. After accounting for undefs,
10028 // convert the 64-bit shuffle mask selection values into 128-bit
10029 // selection bits by dividing the indexes by 2 and shifting into positions
10030 // defined by a vperm2*128 instruction's immediate control byte.
10032 // The immediate permute control byte looks like this:
10033 // [1:0] - select 128 bits from sources for low half of destination
10035 // [3] - zero low half of destination
10036 // [5:4] - select 128 bits from sources for high half of destination
10038 // [7] - zero high half of destination
10040 int MaskLO = Mask[0];
10041 if (MaskLO == SM_SentinelUndef)
10042 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10044 int MaskHI = Mask[2];
10045 if (MaskHI == SM_SentinelUndef)
10046 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10048 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10050 // If either input is a zero vector, replace it with an undef input.
10051 // Shuffle mask values < 4 are selecting elements of V1.
10052 // Shuffle mask values >= 4 are selecting elements of V2.
10053 // Adjust each half of the permute mask by clearing the half that was
10054 // selecting the zero vector and setting the zero mask bit.
10056 V1 = DAG.getUNDEF(VT);
10058 PermMask = (PermMask & 0xf0) | 0x08;
10060 PermMask = (PermMask & 0x0f) | 0x80;
10063 V2 = DAG.getUNDEF(VT);
10065 PermMask = (PermMask & 0xf0) | 0x08;
10067 PermMask = (PermMask & 0x0f) | 0x80;
10070 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10071 DAG.getConstant(PermMask, DL, MVT::i8));
10074 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10075 /// shuffling each lane.
10077 /// This will only succeed when the result of fixing the 128-bit lanes results
10078 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10079 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10080 /// the lane crosses early and then use simpler shuffles within each lane.
10082 /// FIXME: It might be worthwhile at some point to support this without
10083 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10084 /// in x86 only floating point has interesting non-repeating shuffles, and even
10085 /// those are still *marginally* more expensive.
10086 static SDValue lowerVectorShuffleByMerging128BitLanes(
10087 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10088 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10089 assert(!isSingleInputShuffleMask(Mask) &&
10090 "This is only useful with multiple inputs.");
10092 int Size = Mask.size();
10093 int LaneSize = 128 / VT.getScalarSizeInBits();
10094 int NumLanes = Size / LaneSize;
10095 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10097 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10098 // check whether the in-128-bit lane shuffles share a repeating pattern.
10099 SmallVector<int, 4> Lanes;
10100 Lanes.resize(NumLanes, -1);
10101 SmallVector<int, 4> InLaneMask;
10102 InLaneMask.resize(LaneSize, -1);
10103 for (int i = 0; i < Size; ++i) {
10107 int j = i / LaneSize;
10109 if (Lanes[j] < 0) {
10110 // First entry we've seen for this lane.
10111 Lanes[j] = Mask[i] / LaneSize;
10112 } else if (Lanes[j] != Mask[i] / LaneSize) {
10113 // This doesn't match the lane selected previously!
10117 // Check that within each lane we have a consistent shuffle mask.
10118 int k = i % LaneSize;
10119 if (InLaneMask[k] < 0) {
10120 InLaneMask[k] = Mask[i] % LaneSize;
10121 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10122 // This doesn't fit a repeating in-lane mask.
10127 // First shuffle the lanes into place.
10128 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10129 VT.getSizeInBits() / 64);
10130 SmallVector<int, 8> LaneMask;
10131 LaneMask.resize(NumLanes * 2, -1);
10132 for (int i = 0; i < NumLanes; ++i)
10133 if (Lanes[i] >= 0) {
10134 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10135 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10138 V1 = DAG.getBitcast(LaneVT, V1);
10139 V2 = DAG.getBitcast(LaneVT, V2);
10140 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10142 // Cast it back to the type we actually want.
10143 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10145 // Now do a simple shuffle that isn't lane crossing.
10146 SmallVector<int, 8> NewMask;
10147 NewMask.resize(Size, -1);
10148 for (int i = 0; i < Size; ++i)
10150 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10151 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10152 "Must not introduce lane crosses at this point!");
10154 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10157 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10160 /// This returns true if the elements from a particular input are already in the
10161 /// slot required by the given mask and require no permutation.
10162 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10163 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10164 int Size = Mask.size();
10165 for (int i = 0; i < Size; ++i)
10166 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10172 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10173 ArrayRef<int> Mask, SDValue V1,
10174 SDValue V2, SelectionDAG &DAG) {
10176 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10177 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10178 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10179 int NumElts = VT.getVectorNumElements();
10180 bool ShufpdMask = true;
10181 bool CommutableMask = true;
10182 unsigned Immediate = 0;
10183 for (int i = 0; i < NumElts; ++i) {
10186 int Val = (i & 6) + NumElts * (i & 1);
10187 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10188 if (Mask[i] < Val || Mask[i] > Val + 1)
10189 ShufpdMask = false;
10190 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10191 CommutableMask = false;
10192 Immediate |= (Mask[i] % 2) << i;
10195 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10196 DAG.getConstant(Immediate, DL, MVT::i8));
10197 if (CommutableMask)
10198 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10199 DAG.getConstant(Immediate, DL, MVT::i8));
10203 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10205 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10206 /// isn't available.
10207 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10208 const X86Subtarget *Subtarget,
10209 SelectionDAG &DAG) {
10211 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10212 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10214 ArrayRef<int> Mask = SVOp->getMask();
10215 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10217 SmallVector<int, 4> WidenedMask;
10218 if (canWidenShuffleElements(Mask, WidenedMask))
10219 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10222 if (isSingleInputShuffleMask(Mask)) {
10223 // Check for being able to broadcast a single element.
10224 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10225 Mask, Subtarget, DAG))
10228 // Use low duplicate instructions for masks that match their pattern.
10229 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10230 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10232 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10233 // Non-half-crossing single input shuffles can be lowerid with an
10234 // interleaved permutation.
10235 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10236 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10237 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10238 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10241 // With AVX2 we have direct support for this permutation.
10242 if (Subtarget->hasAVX2())
10243 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10244 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10246 // Otherwise, fall back.
10247 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10251 // Use dedicated unpack instructions for masks that match their pattern.
10253 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10256 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10260 // Check if the blend happens to exactly fit that of SHUFPD.
10262 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10265 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10266 // shuffle. However, if we have AVX2 and either inputs are already in place,
10267 // we will be able to shuffle even across lanes the other input in a single
10268 // instruction so skip this pattern.
10269 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10270 isShuffleMaskInputInPlace(1, Mask))))
10271 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10272 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10275 // If we have AVX2 then we always want to lower with a blend because an v4 we
10276 // can fully permute the elements.
10277 if (Subtarget->hasAVX2())
10278 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10281 // Otherwise fall back on generic lowering.
10282 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10285 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10287 /// This routine is only called when we have AVX2 and thus a reasonable
10288 /// instruction set for v4i64 shuffling..
10289 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10290 const X86Subtarget *Subtarget,
10291 SelectionDAG &DAG) {
10293 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10294 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10296 ArrayRef<int> Mask = SVOp->getMask();
10297 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10298 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10300 SmallVector<int, 4> WidenedMask;
10301 if (canWidenShuffleElements(Mask, WidenedMask))
10302 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10305 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10309 // Check for being able to broadcast a single element.
10310 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10311 Mask, Subtarget, DAG))
10314 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10315 // use lower latency instructions that will operate on both 128-bit lanes.
10316 SmallVector<int, 2> RepeatedMask;
10317 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10318 if (isSingleInputShuffleMask(Mask)) {
10319 int PSHUFDMask[] = {-1, -1, -1, -1};
10320 for (int i = 0; i < 2; ++i)
10321 if (RepeatedMask[i] >= 0) {
10322 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10323 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10325 return DAG.getBitcast(
10327 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10328 DAG.getBitcast(MVT::v8i32, V1),
10329 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10333 // AVX2 provides a direct instruction for permuting a single input across
10335 if (isSingleInputShuffleMask(Mask))
10336 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10337 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10339 // Try to use shift instructions.
10340 if (SDValue Shift =
10341 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10344 // Use dedicated unpack instructions for masks that match their pattern.
10346 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10349 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10350 // shuffle. However, if we have AVX2 and either inputs are already in place,
10351 // we will be able to shuffle even across lanes the other input in a single
10352 // instruction so skip this pattern.
10353 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10354 isShuffleMaskInputInPlace(1, Mask))))
10355 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10356 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10359 // Otherwise fall back on generic blend lowering.
10360 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10364 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10366 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10367 /// isn't available.
10368 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10369 const X86Subtarget *Subtarget,
10370 SelectionDAG &DAG) {
10372 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10373 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10375 ArrayRef<int> Mask = SVOp->getMask();
10376 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10378 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10382 // Check for being able to broadcast a single element.
10383 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10384 Mask, Subtarget, DAG))
10387 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10388 // options to efficiently lower the shuffle.
10389 SmallVector<int, 4> RepeatedMask;
10390 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10391 assert(RepeatedMask.size() == 4 &&
10392 "Repeated masks must be half the mask width!");
10394 // Use even/odd duplicate instructions for masks that match their pattern.
10395 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10396 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10397 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10398 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10400 if (isSingleInputShuffleMask(Mask))
10401 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10402 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10404 // Use dedicated unpack instructions for masks that match their pattern.
10406 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10409 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10410 // have already handled any direct blends. We also need to squash the
10411 // repeated mask into a simulated v4f32 mask.
10412 for (int i = 0; i < 4; ++i)
10413 if (RepeatedMask[i] >= 8)
10414 RepeatedMask[i] -= 4;
10415 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10418 // If we have a single input shuffle with different shuffle patterns in the
10419 // two 128-bit lanes use the variable mask to VPERMILPS.
10420 if (isSingleInputShuffleMask(Mask)) {
10421 SDValue VPermMask[8];
10422 for (int i = 0; i < 8; ++i)
10423 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10424 : DAG.getConstant(Mask[i], DL, MVT::i32);
10425 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10426 return DAG.getNode(
10427 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10428 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10430 if (Subtarget->hasAVX2())
10431 return DAG.getNode(
10432 X86ISD::VPERMV, DL, MVT::v8f32,
10433 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10434 MVT::v8i32, VPermMask)),
10437 // Otherwise, fall back.
10438 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10442 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10444 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10445 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10448 // If we have AVX2 then we always want to lower with a blend because at v8 we
10449 // can fully permute the elements.
10450 if (Subtarget->hasAVX2())
10451 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10454 // Otherwise fall back on generic lowering.
10455 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10458 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10460 /// This routine is only called when we have AVX2 and thus a reasonable
10461 /// instruction set for v8i32 shuffling..
10462 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10463 const X86Subtarget *Subtarget,
10464 SelectionDAG &DAG) {
10466 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10467 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10468 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10469 ArrayRef<int> Mask = SVOp->getMask();
10470 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10471 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10473 // Whenever we can lower this as a zext, that instruction is strictly faster
10474 // than any alternative. It also allows us to fold memory operands into the
10475 // shuffle in many cases.
10476 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10477 Mask, Subtarget, DAG))
10480 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10484 // Check for being able to broadcast a single element.
10485 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10486 Mask, Subtarget, DAG))
10489 // If the shuffle mask is repeated in each 128-bit lane we can use more
10490 // efficient instructions that mirror the shuffles across the two 128-bit
10492 SmallVector<int, 4> RepeatedMask;
10493 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10494 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10495 if (isSingleInputShuffleMask(Mask))
10496 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10497 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10499 // Use dedicated unpack instructions for masks that match their pattern.
10501 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10505 // Try to use shift instructions.
10506 if (SDValue Shift =
10507 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10510 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10511 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10514 // If the shuffle patterns aren't repeated but it is a single input, directly
10515 // generate a cross-lane VPERMD instruction.
10516 if (isSingleInputShuffleMask(Mask)) {
10517 SDValue VPermMask[8];
10518 for (int i = 0; i < 8; ++i)
10519 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10520 : DAG.getConstant(Mask[i], DL, MVT::i32);
10521 return DAG.getNode(
10522 X86ISD::VPERMV, DL, MVT::v8i32,
10523 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10526 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10528 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10529 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10532 // Otherwise fall back on generic blend lowering.
10533 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10537 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10539 /// This routine is only called when we have AVX2 and thus a reasonable
10540 /// instruction set for v16i16 shuffling..
10541 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10542 const X86Subtarget *Subtarget,
10543 SelectionDAG &DAG) {
10545 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10546 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10548 ArrayRef<int> Mask = SVOp->getMask();
10549 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10550 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10552 // Whenever we can lower this as a zext, that instruction is strictly faster
10553 // than any alternative. It also allows us to fold memory operands into the
10554 // shuffle in many cases.
10555 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10556 Mask, Subtarget, DAG))
10559 // Check for being able to broadcast a single element.
10560 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10561 Mask, Subtarget, DAG))
10564 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10568 // Use dedicated unpack instructions for masks that match their pattern.
10570 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10573 // Try to use shift instructions.
10574 if (SDValue Shift =
10575 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10578 // Try to use byte rotation instructions.
10579 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10580 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10583 if (isSingleInputShuffleMask(Mask)) {
10584 // There are no generalized cross-lane shuffle operations available on i16
10586 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10587 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10590 SmallVector<int, 8> RepeatedMask;
10591 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10592 // As this is a single-input shuffle, the repeated mask should be
10593 // a strictly valid v8i16 mask that we can pass through to the v8i16
10594 // lowering to handle even the v16 case.
10595 return lowerV8I16GeneralSingleInputVectorShuffle(
10596 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10599 SDValue PSHUFBMask[32];
10600 for (int i = 0; i < 16; ++i) {
10601 if (Mask[i] == -1) {
10602 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10606 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10607 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10608 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10609 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10611 return DAG.getBitcast(MVT::v16i16,
10612 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10613 DAG.getBitcast(MVT::v32i8, V1),
10614 DAG.getNode(ISD::BUILD_VECTOR, DL,
10615 MVT::v32i8, PSHUFBMask)));
10618 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10620 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10621 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10624 // Otherwise fall back on generic lowering.
10625 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10628 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10630 /// This routine is only called when we have AVX2 and thus a reasonable
10631 /// instruction set for v32i8 shuffling..
10632 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10633 const X86Subtarget *Subtarget,
10634 SelectionDAG &DAG) {
10636 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10637 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10638 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10639 ArrayRef<int> Mask = SVOp->getMask();
10640 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10641 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10643 // Whenever we can lower this as a zext, that instruction is strictly faster
10644 // than any alternative. It also allows us to fold memory operands into the
10645 // shuffle in many cases.
10646 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10647 Mask, Subtarget, DAG))
10650 // Check for being able to broadcast a single element.
10651 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10652 Mask, Subtarget, DAG))
10655 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10659 // Use dedicated unpack instructions for masks that match their pattern.
10661 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10664 // Try to use shift instructions.
10665 if (SDValue Shift =
10666 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10669 // Try to use byte rotation instructions.
10670 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10671 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10674 if (isSingleInputShuffleMask(Mask)) {
10675 // There are no generalized cross-lane shuffle operations available on i8
10677 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10678 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10681 SDValue PSHUFBMask[32];
10682 for (int i = 0; i < 32; ++i)
10685 ? DAG.getUNDEF(MVT::i8)
10686 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10689 return DAG.getNode(
10690 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10691 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10694 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10696 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10697 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10700 // Otherwise fall back on generic lowering.
10701 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10704 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10706 /// This routine either breaks down the specific type of a 256-bit x86 vector
10707 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10708 /// together based on the available instructions.
10709 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10710 MVT VT, const X86Subtarget *Subtarget,
10711 SelectionDAG &DAG) {
10713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10714 ArrayRef<int> Mask = SVOp->getMask();
10716 // If we have a single input to the zero element, insert that into V1 if we
10717 // can do so cheaply.
10718 int NumElts = VT.getVectorNumElements();
10719 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10720 return M >= NumElts;
10723 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10724 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10725 DL, VT, V1, V2, Mask, Subtarget, DAG))
10728 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10729 // can check for those subtargets here and avoid much of the subtarget
10730 // querying in the per-vector-type lowering routines. With AVX1 we have
10731 // essentially *zero* ability to manipulate a 256-bit vector with integer
10732 // types. Since we'll use floating point types there eventually, just
10733 // immediately cast everything to a float and operate entirely in that domain.
10734 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10735 int ElementBits = VT.getScalarSizeInBits();
10736 if (ElementBits < 32)
10737 // No floating point type available, decompose into 128-bit vectors.
10738 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10740 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10741 VT.getVectorNumElements());
10742 V1 = DAG.getBitcast(FpVT, V1);
10743 V2 = DAG.getBitcast(FpVT, V2);
10744 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10747 switch (VT.SimpleTy) {
10749 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10751 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10753 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10757 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10759 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10762 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10766 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10767 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10768 ArrayRef<int> Mask,
10769 SDValue V1, SDValue V2,
10770 SelectionDAG &DAG) {
10771 assert(VT.getScalarSizeInBits() == 64 &&
10772 "Unexpected element type size for 128bit shuffle.");
10774 // To handle 256 bit vector requires VLX and most probably
10775 // function lowerV2X128VectorShuffle() is better solution.
10776 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10778 SmallVector<int, 4> WidenedMask;
10779 if (!canWidenShuffleElements(Mask, WidenedMask))
10782 // Form a 128-bit permutation.
10783 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10784 // bits defined by a vshuf64x2 instruction's immediate control byte.
10785 unsigned PermMask = 0, Imm = 0;
10786 unsigned ControlBitsNum = WidenedMask.size() / 2;
10788 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10789 if (WidenedMask[i] == SM_SentinelZero)
10792 // Use first element in place of undef mask.
10793 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10794 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10797 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10798 DAG.getConstant(PermMask, DL, MVT::i8));
10801 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10802 ArrayRef<int> Mask, SDValue V1,
10803 SDValue V2, SelectionDAG &DAG) {
10805 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10807 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10808 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10810 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10811 if (isSingleInputShuffleMask(Mask))
10812 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10814 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10817 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10818 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10819 const X86Subtarget *Subtarget,
10820 SelectionDAG &DAG) {
10822 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10823 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10825 ArrayRef<int> Mask = SVOp->getMask();
10826 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10828 if (SDValue Shuf128 =
10829 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10832 if (SDValue Unpck =
10833 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10836 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10839 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10840 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10841 const X86Subtarget *Subtarget,
10842 SelectionDAG &DAG) {
10844 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10845 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10846 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10847 ArrayRef<int> Mask = SVOp->getMask();
10848 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10850 if (SDValue Unpck =
10851 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10854 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10857 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10858 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10859 const X86Subtarget *Subtarget,
10860 SelectionDAG &DAG) {
10862 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10863 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10864 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10865 ArrayRef<int> Mask = SVOp->getMask();
10866 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10868 if (SDValue Shuf128 =
10869 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10872 if (SDValue Unpck =
10873 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10876 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10879 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10880 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10881 const X86Subtarget *Subtarget,
10882 SelectionDAG &DAG) {
10884 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10885 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10887 ArrayRef<int> Mask = SVOp->getMask();
10888 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10890 if (SDValue Unpck =
10891 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10894 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10897 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10898 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10899 const X86Subtarget *Subtarget,
10900 SelectionDAG &DAG) {
10902 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10903 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10904 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10905 ArrayRef<int> Mask = SVOp->getMask();
10906 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10907 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10909 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10912 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10913 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10914 const X86Subtarget *Subtarget,
10915 SelectionDAG &DAG) {
10917 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10918 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10919 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10920 ArrayRef<int> Mask = SVOp->getMask();
10921 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10922 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10924 // FIXME: Implement direct support for this type!
10925 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10928 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10930 /// This routine either breaks down the specific type of a 512-bit x86 vector
10931 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10932 /// together based on the available instructions.
10933 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10934 MVT VT, const X86Subtarget *Subtarget,
10935 SelectionDAG &DAG) {
10937 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10938 ArrayRef<int> Mask = SVOp->getMask();
10939 assert(Subtarget->hasAVX512() &&
10940 "Cannot lower 512-bit vectors w/ basic ISA!");
10942 // Check for being able to broadcast a single element.
10943 if (SDValue Broadcast =
10944 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10947 // Dispatch to each element type for lowering. If we don't have supprot for
10948 // specific element type shuffles at 512 bits, immediately split them and
10949 // lower them. Each lowering routine of a given type is allowed to assume that
10950 // the requisite ISA extensions for that element type are available.
10951 switch (VT.SimpleTy) {
10953 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10955 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10957 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10959 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10961 if (Subtarget->hasBWI())
10962 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10965 if (Subtarget->hasBWI())
10966 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10970 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10973 // Otherwise fall back on splitting.
10974 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10977 // Lower vXi1 vector shuffles.
10978 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10979 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10980 // vector, shuffle and then truncate it back.
10981 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10982 MVT VT, const X86Subtarget *Subtarget,
10983 SelectionDAG &DAG) {
10985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10986 ArrayRef<int> Mask = SVOp->getMask();
10987 assert(Subtarget->hasAVX512() &&
10988 "Cannot lower 512-bit vectors w/o basic ISA!");
10990 switch (VT.SimpleTy) {
10992 llvm_unreachable("Expected a vector of i1 elements");
10994 ExtVT = MVT::v2i64;
10997 ExtVT = MVT::v4i32;
11000 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11003 ExtVT = MVT::v16i32;
11006 ExtVT = MVT::v32i16;
11009 ExtVT = MVT::v64i8;
11013 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11014 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11015 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11016 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11018 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11021 V2 = DAG.getUNDEF(ExtVT);
11022 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11023 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11024 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11025 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11027 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11028 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11029 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11031 /// \brief Top-level lowering for x86 vector shuffles.
11033 /// This handles decomposition, canonicalization, and lowering of all x86
11034 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11035 /// above in helper routines. The canonicalization attempts to widen shuffles
11036 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11037 /// s.t. only one of the two inputs needs to be tested, etc.
11038 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11039 SelectionDAG &DAG) {
11040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11041 ArrayRef<int> Mask = SVOp->getMask();
11042 SDValue V1 = Op.getOperand(0);
11043 SDValue V2 = Op.getOperand(1);
11044 MVT VT = Op.getSimpleValueType();
11045 int NumElements = VT.getVectorNumElements();
11047 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11049 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11050 "Can't lower MMX shuffles");
11052 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11053 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11054 if (V1IsUndef && V2IsUndef)
11055 return DAG.getUNDEF(VT);
11057 // When we create a shuffle node we put the UNDEF node to second operand,
11058 // but in some cases the first operand may be transformed to UNDEF.
11059 // In this case we should just commute the node.
11061 return DAG.getCommutedVectorShuffle(*SVOp);
11063 // Check for non-undef masks pointing at an undef vector and make the masks
11064 // undef as well. This makes it easier to match the shuffle based solely on
11068 if (M >= NumElements) {
11069 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11070 for (int &M : NewMask)
11071 if (M >= NumElements)
11073 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11076 // We actually see shuffles that are entirely re-arrangements of a set of
11077 // zero inputs. This mostly happens while decomposing complex shuffles into
11078 // simple ones. Directly lower these as a buildvector of zeros.
11079 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11080 if (Zeroable.all())
11081 return getZeroVector(VT, Subtarget, DAG, dl);
11083 // Try to collapse shuffles into using a vector type with fewer elements but
11084 // wider element types. We cap this to not form integers or floating point
11085 // elements wider than 64 bits, but it might be interesting to form i128
11086 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11087 SmallVector<int, 16> WidenedMask;
11088 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11089 canWidenShuffleElements(Mask, WidenedMask)) {
11090 MVT NewEltVT = VT.isFloatingPoint()
11091 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11092 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11093 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11094 // Make sure that the new vector type is legal. For example, v2f64 isn't
11096 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11097 V1 = DAG.getBitcast(NewVT, V1);
11098 V2 = DAG.getBitcast(NewVT, V2);
11099 return DAG.getBitcast(
11100 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11104 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11105 for (int M : SVOp->getMask())
11107 ++NumUndefElements;
11108 else if (M < NumElements)
11113 // Commute the shuffle as needed such that more elements come from V1 than
11114 // V2. This allows us to match the shuffle pattern strictly on how many
11115 // elements come from V1 without handling the symmetric cases.
11116 if (NumV2Elements > NumV1Elements)
11117 return DAG.getCommutedVectorShuffle(*SVOp);
11119 // When the number of V1 and V2 elements are the same, try to minimize the
11120 // number of uses of V2 in the low half of the vector. When that is tied,
11121 // ensure that the sum of indices for V1 is equal to or lower than the sum
11122 // indices for V2. When those are equal, try to ensure that the number of odd
11123 // indices for V1 is lower than the number of odd indices for V2.
11124 if (NumV1Elements == NumV2Elements) {
11125 int LowV1Elements = 0, LowV2Elements = 0;
11126 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11127 if (M >= NumElements)
11131 if (LowV2Elements > LowV1Elements) {
11132 return DAG.getCommutedVectorShuffle(*SVOp);
11133 } else if (LowV2Elements == LowV1Elements) {
11134 int SumV1Indices = 0, SumV2Indices = 0;
11135 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11136 if (SVOp->getMask()[i] >= NumElements)
11138 else if (SVOp->getMask()[i] >= 0)
11140 if (SumV2Indices < SumV1Indices) {
11141 return DAG.getCommutedVectorShuffle(*SVOp);
11142 } else if (SumV2Indices == SumV1Indices) {
11143 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11144 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11145 if (SVOp->getMask()[i] >= NumElements)
11146 NumV2OddIndices += i % 2;
11147 else if (SVOp->getMask()[i] >= 0)
11148 NumV1OddIndices += i % 2;
11149 if (NumV2OddIndices < NumV1OddIndices)
11150 return DAG.getCommutedVectorShuffle(*SVOp);
11155 // For each vector width, delegate to a specialized lowering routine.
11156 if (VT.is128BitVector())
11157 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11159 if (VT.is256BitVector())
11160 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11162 if (VT.is512BitVector())
11163 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11166 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11167 llvm_unreachable("Unimplemented!");
11170 // This function assumes its argument is a BUILD_VECTOR of constants or
11171 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11173 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11174 unsigned &MaskValue) {
11176 unsigned NumElems = BuildVector->getNumOperands();
11178 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11179 // We don't handle the >2 lanes case right now.
11180 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11184 unsigned NumElemsInLane = NumElems / NumLanes;
11186 // Blend for v16i16 should be symmetric for the both lanes.
11187 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11188 SDValue EltCond = BuildVector->getOperand(i);
11189 SDValue SndLaneEltCond =
11190 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11192 int Lane1Cond = -1, Lane2Cond = -1;
11193 if (isa<ConstantSDNode>(EltCond))
11194 Lane1Cond = !isZero(EltCond);
11195 if (isa<ConstantSDNode>(SndLaneEltCond))
11196 Lane2Cond = !isZero(SndLaneEltCond);
11198 unsigned LaneMask = 0;
11199 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11200 // Lane1Cond != 0, means we want the first argument.
11201 // Lane1Cond == 0, means we want the second argument.
11202 // The encoding of this argument is 0 for the first argument, 1
11203 // for the second. Therefore, invert the condition.
11204 LaneMask = !Lane1Cond << i;
11205 else if (Lane1Cond < 0)
11206 LaneMask = !Lane2Cond << i;
11210 MaskValue |= LaneMask;
11212 MaskValue |= LaneMask << NumElemsInLane;
11217 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11218 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11219 const X86Subtarget *Subtarget,
11220 SelectionDAG &DAG) {
11221 SDValue Cond = Op.getOperand(0);
11222 SDValue LHS = Op.getOperand(1);
11223 SDValue RHS = Op.getOperand(2);
11225 MVT VT = Op.getSimpleValueType();
11227 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11229 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11231 // Only non-legal VSELECTs reach this lowering, convert those into generic
11232 // shuffles and re-use the shuffle lowering path for blends.
11233 SmallVector<int, 32> Mask;
11234 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11235 SDValue CondElt = CondBV->getOperand(i);
11237 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11239 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11242 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11243 // A vselect where all conditions and data are constants can be optimized into
11244 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11245 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11246 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11247 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11250 // Try to lower this to a blend-style vector shuffle. This can handle all
11251 // constant condition cases.
11252 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11255 // Variable blends are only legal from SSE4.1 onward.
11256 if (!Subtarget->hasSSE41())
11259 // Only some types will be legal on some subtargets. If we can emit a legal
11260 // VSELECT-matching blend, return Op, and but if we need to expand, return
11262 switch (Op.getSimpleValueType().SimpleTy) {
11264 // Most of the vector types have blends past SSE4.1.
11268 // The byte blends for AVX vectors were introduced only in AVX2.
11269 if (Subtarget->hasAVX2())
11276 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11277 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11280 // FIXME: We should custom lower this by fixing the condition and using i8
11286 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11287 MVT VT = Op.getSimpleValueType();
11290 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11293 if (VT.getSizeInBits() == 8) {
11294 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11295 Op.getOperand(0), Op.getOperand(1));
11296 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11297 DAG.getValueType(VT));
11298 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11301 if (VT.getSizeInBits() == 16) {
11302 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11303 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11305 return DAG.getNode(
11306 ISD::TRUNCATE, dl, MVT::i16,
11307 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11308 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11309 Op.getOperand(1)));
11310 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11311 Op.getOperand(0), Op.getOperand(1));
11312 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11313 DAG.getValueType(VT));
11314 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11317 if (VT == MVT::f32) {
11318 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11319 // the result back to FR32 register. It's only worth matching if the
11320 // result has a single use which is a store or a bitcast to i32. And in
11321 // the case of a store, it's not worth it if the index is a constant 0,
11322 // because a MOVSSmr can be used instead, which is smaller and faster.
11323 if (!Op.hasOneUse())
11325 SDNode *User = *Op.getNode()->use_begin();
11326 if ((User->getOpcode() != ISD::STORE ||
11327 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11328 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11329 (User->getOpcode() != ISD::BITCAST ||
11330 User->getValueType(0) != MVT::i32))
11332 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11333 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11335 return DAG.getBitcast(MVT::f32, Extract);
11338 if (VT == MVT::i32 || VT == MVT::i64) {
11339 // ExtractPS/pextrq works with constant index.
11340 if (isa<ConstantSDNode>(Op.getOperand(1)))
11346 /// Extract one bit from mask vector, like v16i1 or v8i1.
11347 /// AVX-512 feature.
11349 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11350 SDValue Vec = Op.getOperand(0);
11352 MVT VecVT = Vec.getSimpleValueType();
11353 SDValue Idx = Op.getOperand(1);
11354 MVT EltVT = Op.getSimpleValueType();
11356 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11357 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11358 "Unexpected vector type in ExtractBitFromMaskVector");
11360 // variable index can't be handled in mask registers,
11361 // extend vector to VR512
11362 if (!isa<ConstantSDNode>(Idx)) {
11363 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11364 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11365 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11366 ExtVT.getVectorElementType(), Ext, Idx);
11367 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11370 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11371 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11372 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11373 rc = getRegClassFor(MVT::v16i1);
11374 unsigned MaxSift = rc->getSize()*8 - 1;
11375 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11376 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11377 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11378 DAG.getConstant(MaxSift, dl, MVT::i8));
11379 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11380 DAG.getIntPtrConstant(0, dl));
11384 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11385 SelectionDAG &DAG) const {
11387 SDValue Vec = Op.getOperand(0);
11388 MVT VecVT = Vec.getSimpleValueType();
11389 SDValue Idx = Op.getOperand(1);
11391 if (Op.getSimpleValueType() == MVT::i1)
11392 return ExtractBitFromMaskVector(Op, DAG);
11394 if (!isa<ConstantSDNode>(Idx)) {
11395 if (VecVT.is512BitVector() ||
11396 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11397 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11400 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11401 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11402 MaskEltVT.getSizeInBits());
11404 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11405 auto PtrVT = getPointerTy(DAG.getDataLayout());
11406 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11407 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11408 DAG.getConstant(0, dl, PtrVT));
11409 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11410 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11411 DAG.getConstant(0, dl, PtrVT));
11416 // If this is a 256-bit vector result, first extract the 128-bit vector and
11417 // then extract the element from the 128-bit vector.
11418 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11420 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11421 // Get the 128-bit vector.
11422 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11423 MVT EltVT = VecVT.getVectorElementType();
11425 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11426 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11428 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11429 // this can be done with a mask.
11430 IdxVal &= ElemsPerChunk - 1;
11431 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11432 DAG.getConstant(IdxVal, dl, MVT::i32));
11435 assert(VecVT.is128BitVector() && "Unexpected vector length");
11437 if (Subtarget->hasSSE41())
11438 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11441 MVT VT = Op.getSimpleValueType();
11442 // TODO: handle v16i8.
11443 if (VT.getSizeInBits() == 16) {
11444 SDValue Vec = Op.getOperand(0);
11445 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11447 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11448 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11449 DAG.getBitcast(MVT::v4i32, Vec),
11450 Op.getOperand(1)));
11451 // Transform it so it match pextrw which produces a 32-bit result.
11452 MVT EltVT = MVT::i32;
11453 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11454 Op.getOperand(0), Op.getOperand(1));
11455 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11456 DAG.getValueType(VT));
11457 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11460 if (VT.getSizeInBits() == 32) {
11461 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11465 // SHUFPS the element to the lowest double word, then movss.
11466 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11467 MVT VVT = Op.getOperand(0).getSimpleValueType();
11468 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11469 DAG.getUNDEF(VVT), Mask);
11470 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11471 DAG.getIntPtrConstant(0, dl));
11474 if (VT.getSizeInBits() == 64) {
11475 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11476 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11477 // to match extract_elt for f64.
11478 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11482 // UNPCKHPD the element to the lowest double word, then movsd.
11483 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11484 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11485 int Mask[2] = { 1, -1 };
11486 MVT VVT = Op.getOperand(0).getSimpleValueType();
11487 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11488 DAG.getUNDEF(VVT), Mask);
11489 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11490 DAG.getIntPtrConstant(0, dl));
11496 /// Insert one bit to mask vector, like v16i1 or v8i1.
11497 /// AVX-512 feature.
11499 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11501 SDValue Vec = Op.getOperand(0);
11502 SDValue Elt = Op.getOperand(1);
11503 SDValue Idx = Op.getOperand(2);
11504 MVT VecVT = Vec.getSimpleValueType();
11506 if (!isa<ConstantSDNode>(Idx)) {
11507 // Non constant index. Extend source and destination,
11508 // insert element and then truncate the result.
11509 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11510 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11511 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11512 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11513 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11514 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11517 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11518 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11520 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11521 DAG.getConstant(IdxVal, dl, MVT::i8));
11522 if (Vec.getOpcode() == ISD::UNDEF)
11524 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11527 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11528 SelectionDAG &DAG) const {
11529 MVT VT = Op.getSimpleValueType();
11530 MVT EltVT = VT.getVectorElementType();
11532 if (EltVT == MVT::i1)
11533 return InsertBitToMaskVector(Op, DAG);
11536 SDValue N0 = Op.getOperand(0);
11537 SDValue N1 = Op.getOperand(1);
11538 SDValue N2 = Op.getOperand(2);
11539 if (!isa<ConstantSDNode>(N2))
11541 auto *N2C = cast<ConstantSDNode>(N2);
11542 unsigned IdxVal = N2C->getZExtValue();
11544 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11545 // into that, and then insert the subvector back into the result.
11546 if (VT.is256BitVector() || VT.is512BitVector()) {
11547 // With a 256-bit vector, we can insert into the zero element efficiently
11548 // using a blend if we have AVX or AVX2 and the right data type.
11549 if (VT.is256BitVector() && IdxVal == 0) {
11550 // TODO: It is worthwhile to cast integer to floating point and back
11551 // and incur a domain crossing penalty if that's what we'll end up
11552 // doing anyway after extracting to a 128-bit vector.
11553 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11554 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11555 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11556 N2 = DAG.getIntPtrConstant(1, dl);
11557 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11561 // Get the desired 128-bit vector chunk.
11562 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11564 // Insert the element into the desired chunk.
11565 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11566 assert(isPowerOf2_32(NumEltsIn128));
11567 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11568 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11570 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11571 DAG.getConstant(IdxIn128, dl, MVT::i32));
11573 // Insert the changed part back into the bigger vector
11574 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11576 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11578 if (Subtarget->hasSSE41()) {
11579 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11581 if (VT == MVT::v8i16) {
11582 Opc = X86ISD::PINSRW;
11584 assert(VT == MVT::v16i8);
11585 Opc = X86ISD::PINSRB;
11588 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11590 if (N1.getValueType() != MVT::i32)
11591 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11592 if (N2.getValueType() != MVT::i32)
11593 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11594 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11597 if (EltVT == MVT::f32) {
11598 // Bits [7:6] of the constant are the source select. This will always be
11599 // zero here. The DAG Combiner may combine an extract_elt index into
11600 // these bits. For example (insert (extract, 3), 2) could be matched by
11601 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11602 // Bits [5:4] of the constant are the destination select. This is the
11603 // value of the incoming immediate.
11604 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11605 // combine either bitwise AND or insert of float 0.0 to set these bits.
11607 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11608 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11609 // If this is an insertion of 32-bits into the low 32-bits of
11610 // a vector, we prefer to generate a blend with immediate rather
11611 // than an insertps. Blends are simpler operations in hardware and so
11612 // will always have equal or better performance than insertps.
11613 // But if optimizing for size and there's a load folding opportunity,
11614 // generate insertps because blendps does not have a 32-bit memory
11616 N2 = DAG.getIntPtrConstant(1, dl);
11617 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11618 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11620 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11621 // Create this as a scalar to vector..
11622 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11623 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11626 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11627 // PINSR* works with constant index.
11632 if (EltVT == MVT::i8)
11635 if (EltVT.getSizeInBits() == 16) {
11636 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11637 // as its second argument.
11638 if (N1.getValueType() != MVT::i32)
11639 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11640 if (N2.getValueType() != MVT::i32)
11641 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11642 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11647 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11649 MVT OpVT = Op.getSimpleValueType();
11651 // If this is a 256-bit vector result, first insert into a 128-bit
11652 // vector and then insert into the 256-bit vector.
11653 if (!OpVT.is128BitVector()) {
11654 // Insert into a 128-bit vector.
11655 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11656 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11657 OpVT.getVectorNumElements() / SizeFactor);
11659 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11661 // Insert the 128-bit vector.
11662 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11665 if (OpVT == MVT::v1i64 &&
11666 Op.getOperand(0).getValueType() == MVT::i64)
11667 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11669 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11670 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11671 return DAG.getBitcast(
11672 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11675 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11676 // a simple subregister reference or explicit instructions to grab
11677 // upper bits of a vector.
11678 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11679 SelectionDAG &DAG) {
11681 SDValue In = Op.getOperand(0);
11682 SDValue Idx = Op.getOperand(1);
11683 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11684 MVT ResVT = Op.getSimpleValueType();
11685 MVT InVT = In.getSimpleValueType();
11687 if (Subtarget->hasFp256()) {
11688 if (ResVT.is128BitVector() &&
11689 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11690 isa<ConstantSDNode>(Idx)) {
11691 return Extract128BitVector(In, IdxVal, DAG, dl);
11693 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11694 isa<ConstantSDNode>(Idx)) {
11695 return Extract256BitVector(In, IdxVal, DAG, dl);
11701 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11702 // simple superregister reference or explicit instructions to insert
11703 // the upper bits of a vector.
11704 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11705 SelectionDAG &DAG) {
11706 if (!Subtarget->hasAVX())
11710 SDValue Vec = Op.getOperand(0);
11711 SDValue SubVec = Op.getOperand(1);
11712 SDValue Idx = Op.getOperand(2);
11714 if (!isa<ConstantSDNode>(Idx))
11717 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11718 MVT OpVT = Op.getSimpleValueType();
11719 MVT SubVecVT = SubVec.getSimpleValueType();
11721 // Fold two 16-byte subvector loads into one 32-byte load:
11722 // (insert_subvector (insert_subvector undef, (load addr), 0),
11723 // (load addr + 16), Elts/2)
11725 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11726 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11727 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11728 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11729 if (Idx2 && Idx2->getZExtValue() == 0) {
11730 SDValue SubVec2 = Vec.getOperand(1);
11731 // If needed, look through a bitcast to get to the load.
11732 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11733 SubVec2 = SubVec2.getOperand(0);
11735 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11737 unsigned Alignment = FirstLd->getAlignment();
11738 unsigned AS = FirstLd->getAddressSpace();
11739 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11740 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11741 OpVT, AS, Alignment, &Fast) && Fast) {
11742 SDValue Ops[] = { SubVec2, SubVec };
11743 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11750 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11751 SubVecVT.is128BitVector())
11752 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11754 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11755 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11757 if (OpVT.getVectorElementType() == MVT::i1) {
11758 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11760 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11761 SDValue Undef = DAG.getUNDEF(OpVT);
11762 unsigned NumElems = OpVT.getVectorNumElements();
11763 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11765 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11766 // Zero upper bits of the Vec
11767 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11768 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11770 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11772 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11773 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11776 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11778 // Zero upper bits of the Vec2
11779 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11780 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11781 // Zero lower bits of the Vec
11782 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11783 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11784 // Merge them together
11785 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11791 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11792 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11793 // one of the above mentioned nodes. It has to be wrapped because otherwise
11794 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11795 // be used to form addressing mode. These wrapped nodes will be selected
11798 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11799 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11801 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11802 // global base reg.
11803 unsigned char OpFlag = 0;
11804 unsigned WrapperKind = X86ISD::Wrapper;
11805 CodeModel::Model M = DAG.getTarget().getCodeModel();
11807 if (Subtarget->isPICStyleRIPRel() &&
11808 (M == CodeModel::Small || M == CodeModel::Kernel))
11809 WrapperKind = X86ISD::WrapperRIP;
11810 else if (Subtarget->isPICStyleGOT())
11811 OpFlag = X86II::MO_GOTOFF;
11812 else if (Subtarget->isPICStyleStubPIC())
11813 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11815 auto PtrVT = getPointerTy(DAG.getDataLayout());
11816 SDValue Result = DAG.getTargetConstantPool(
11817 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11819 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11820 // With PIC, the address is actually $g + Offset.
11823 DAG.getNode(ISD::ADD, DL, PtrVT,
11824 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11830 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11831 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11833 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11834 // global base reg.
11835 unsigned char OpFlag = 0;
11836 unsigned WrapperKind = X86ISD::Wrapper;
11837 CodeModel::Model M = DAG.getTarget().getCodeModel();
11839 if (Subtarget->isPICStyleRIPRel() &&
11840 (M == CodeModel::Small || M == CodeModel::Kernel))
11841 WrapperKind = X86ISD::WrapperRIP;
11842 else if (Subtarget->isPICStyleGOT())
11843 OpFlag = X86II::MO_GOTOFF;
11844 else if (Subtarget->isPICStyleStubPIC())
11845 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11847 auto PtrVT = getPointerTy(DAG.getDataLayout());
11848 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11850 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11852 // With PIC, the address is actually $g + Offset.
11855 DAG.getNode(ISD::ADD, DL, PtrVT,
11856 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11862 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11863 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11865 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11866 // global base reg.
11867 unsigned char OpFlag = 0;
11868 unsigned WrapperKind = X86ISD::Wrapper;
11869 CodeModel::Model M = DAG.getTarget().getCodeModel();
11871 if (Subtarget->isPICStyleRIPRel() &&
11872 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11873 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11874 OpFlag = X86II::MO_GOTPCREL;
11875 WrapperKind = X86ISD::WrapperRIP;
11876 } else if (Subtarget->isPICStyleGOT()) {
11877 OpFlag = X86II::MO_GOT;
11878 } else if (Subtarget->isPICStyleStubPIC()) {
11879 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11880 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11881 OpFlag = X86II::MO_DARWIN_NONLAZY;
11884 auto PtrVT = getPointerTy(DAG.getDataLayout());
11885 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11888 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11890 // With PIC, the address is actually $g + Offset.
11891 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11892 !Subtarget->is64Bit()) {
11894 DAG.getNode(ISD::ADD, DL, PtrVT,
11895 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11898 // For symbols that require a load from a stub to get the address, emit the
11900 if (isGlobalStubReference(OpFlag))
11901 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11902 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11903 false, false, false, 0);
11909 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11910 // Create the TargetBlockAddressAddress node.
11911 unsigned char OpFlags =
11912 Subtarget->ClassifyBlockAddressReference();
11913 CodeModel::Model M = DAG.getTarget().getCodeModel();
11914 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11915 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11917 auto PtrVT = getPointerTy(DAG.getDataLayout());
11918 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11920 if (Subtarget->isPICStyleRIPRel() &&
11921 (M == CodeModel::Small || M == CodeModel::Kernel))
11922 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11924 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11926 // With PIC, the address is actually $g + Offset.
11927 if (isGlobalRelativeToPICBase(OpFlags)) {
11928 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11929 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11936 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11937 int64_t Offset, SelectionDAG &DAG) const {
11938 // Create the TargetGlobalAddress node, folding in the constant
11939 // offset if it is legal.
11940 unsigned char OpFlags =
11941 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11942 CodeModel::Model M = DAG.getTarget().getCodeModel();
11943 auto PtrVT = getPointerTy(DAG.getDataLayout());
11945 if (OpFlags == X86II::MO_NO_FLAG &&
11946 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11947 // A direct static reference to a global.
11948 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11951 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11954 if (Subtarget->isPICStyleRIPRel() &&
11955 (M == CodeModel::Small || M == CodeModel::Kernel))
11956 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11958 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11960 // With PIC, the address is actually $g + Offset.
11961 if (isGlobalRelativeToPICBase(OpFlags)) {
11962 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11963 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11966 // For globals that require a load from a stub to get the address, emit the
11968 if (isGlobalStubReference(OpFlags))
11969 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11970 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11971 false, false, false, 0);
11973 // If there was a non-zero offset that we didn't fold, create an explicit
11974 // addition for it.
11976 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11977 DAG.getConstant(Offset, dl, PtrVT));
11983 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11984 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11985 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11986 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11990 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11991 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11992 unsigned char OperandFlags, bool LocalDynamic = false) {
11993 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11994 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11996 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11997 GA->getValueType(0),
12001 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12005 SDValue Ops[] = { Chain, TGA, *InFlag };
12006 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12008 SDValue Ops[] = { Chain, TGA };
12009 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12012 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12013 MFI->setAdjustsStack(true);
12014 MFI->setHasCalls(true);
12016 SDValue Flag = Chain.getValue(1);
12017 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12020 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12022 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12025 SDLoc dl(GA); // ? function entry point might be better
12026 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12027 DAG.getNode(X86ISD::GlobalBaseReg,
12028 SDLoc(), PtrVT), InFlag);
12029 InFlag = Chain.getValue(1);
12031 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12034 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12036 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12038 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12039 X86::RAX, X86II::MO_TLSGD);
12042 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12048 // Get the start address of the TLS block for this module.
12049 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12050 .getInfo<X86MachineFunctionInfo>();
12051 MFI->incNumLocalDynamicTLSAccesses();
12055 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12056 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12059 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12060 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12061 InFlag = Chain.getValue(1);
12062 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12063 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12066 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12070 unsigned char OperandFlags = X86II::MO_DTPOFF;
12071 unsigned WrapperKind = X86ISD::Wrapper;
12072 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12073 GA->getValueType(0),
12074 GA->getOffset(), OperandFlags);
12075 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12077 // Add x@dtpoff with the base.
12078 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12081 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12082 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12083 const EVT PtrVT, TLSModel::Model model,
12084 bool is64Bit, bool isPIC) {
12087 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12088 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12089 is64Bit ? 257 : 256));
12091 SDValue ThreadPointer =
12092 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12093 MachinePointerInfo(Ptr), false, false, false, 0);
12095 unsigned char OperandFlags = 0;
12096 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12098 unsigned WrapperKind = X86ISD::Wrapper;
12099 if (model == TLSModel::LocalExec) {
12100 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12101 } else if (model == TLSModel::InitialExec) {
12103 OperandFlags = X86II::MO_GOTTPOFF;
12104 WrapperKind = X86ISD::WrapperRIP;
12106 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12109 llvm_unreachable("Unexpected model");
12112 // emit "addl x@ntpoff,%eax" (local exec)
12113 // or "addl x@indntpoff,%eax" (initial exec)
12114 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12116 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12117 GA->getOffset(), OperandFlags);
12118 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12120 if (model == TLSModel::InitialExec) {
12121 if (isPIC && !is64Bit) {
12122 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12123 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12127 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12128 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12129 false, false, false, 0);
12132 // The address of the thread local variable is the add of the thread
12133 // pointer with the offset of the variable.
12134 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12138 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12140 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12141 const GlobalValue *GV = GA->getGlobal();
12142 auto PtrVT = getPointerTy(DAG.getDataLayout());
12144 if (Subtarget->isTargetELF()) {
12145 if (DAG.getTarget().Options.EmulatedTLS)
12146 return LowerToTLSEmulatedModel(GA, DAG);
12147 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12149 case TLSModel::GeneralDynamic:
12150 if (Subtarget->is64Bit())
12151 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12152 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12153 case TLSModel::LocalDynamic:
12154 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12155 Subtarget->is64Bit());
12156 case TLSModel::InitialExec:
12157 case TLSModel::LocalExec:
12158 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12159 DAG.getTarget().getRelocationModel() ==
12162 llvm_unreachable("Unknown TLS model.");
12165 if (Subtarget->isTargetDarwin()) {
12166 // Darwin only has one model of TLS. Lower to that.
12167 unsigned char OpFlag = 0;
12168 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12169 X86ISD::WrapperRIP : X86ISD::Wrapper;
12171 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12172 // global base reg.
12173 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12174 !Subtarget->is64Bit();
12176 OpFlag = X86II::MO_TLVP_PIC_BASE;
12178 OpFlag = X86II::MO_TLVP;
12180 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12181 GA->getValueType(0),
12182 GA->getOffset(), OpFlag);
12183 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12185 // With PIC32, the address is actually $g + Offset.
12187 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12188 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12191 // Lowering the machine isd will make sure everything is in the right
12193 SDValue Chain = DAG.getEntryNode();
12194 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12195 SDValue Args[] = { Chain, Offset };
12196 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12198 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12199 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12200 MFI->setAdjustsStack(true);
12202 // And our return value (tls address) is in the standard call return value
12204 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12205 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12208 if (Subtarget->isTargetKnownWindowsMSVC() ||
12209 Subtarget->isTargetWindowsGNU()) {
12210 // Just use the implicit TLS architecture
12211 // Need to generate someting similar to:
12212 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12214 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12215 // mov rcx, qword [rdx+rcx*8]
12216 // mov eax, .tls$:tlsvar
12217 // [rax+rcx] contains the address
12218 // Windows 64bit: gs:0x58
12219 // Windows 32bit: fs:__tls_array
12222 SDValue Chain = DAG.getEntryNode();
12224 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12225 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12226 // use its literal value of 0x2C.
12227 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12228 ? Type::getInt8PtrTy(*DAG.getContext(),
12230 : Type::getInt32PtrTy(*DAG.getContext(),
12233 SDValue TlsArray = Subtarget->is64Bit()
12234 ? DAG.getIntPtrConstant(0x58, dl)
12235 : (Subtarget->isTargetWindowsGNU()
12236 ? DAG.getIntPtrConstant(0x2C, dl)
12237 : DAG.getExternalSymbol("_tls_array", PtrVT));
12239 SDValue ThreadPointer =
12240 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12244 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12245 res = ThreadPointer;
12247 // Load the _tls_index variable
12248 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12249 if (Subtarget->is64Bit())
12250 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12251 MachinePointerInfo(), MVT::i32, false, false,
12254 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12257 auto &DL = DAG.getDataLayout();
12259 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12260 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12262 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12265 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12268 // Get the offset of start of .tls section
12269 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12270 GA->getValueType(0),
12271 GA->getOffset(), X86II::MO_SECREL);
12272 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12274 // The address of the thread local variable is the add of the thread
12275 // pointer with the offset of the variable.
12276 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12279 llvm_unreachable("TLS not implemented for this target.");
12282 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12283 /// and take a 2 x i32 value to shift plus a shift amount.
12284 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12285 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12286 MVT VT = Op.getSimpleValueType();
12287 unsigned VTBits = VT.getSizeInBits();
12289 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12290 SDValue ShOpLo = Op.getOperand(0);
12291 SDValue ShOpHi = Op.getOperand(1);
12292 SDValue ShAmt = Op.getOperand(2);
12293 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12294 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12296 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12297 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12298 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12299 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12300 : DAG.getConstant(0, dl, VT);
12302 SDValue Tmp2, Tmp3;
12303 if (Op.getOpcode() == ISD::SHL_PARTS) {
12304 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12305 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12307 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12308 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12311 // If the shift amount is larger or equal than the width of a part we can't
12312 // rely on the results of shld/shrd. Insert a test and select the appropriate
12313 // values for large shift amounts.
12314 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12315 DAG.getConstant(VTBits, dl, MVT::i8));
12316 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12317 AndNode, DAG.getConstant(0, dl, MVT::i8));
12320 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12321 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12322 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12324 if (Op.getOpcode() == ISD::SHL_PARTS) {
12325 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12326 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12328 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12329 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12332 SDValue Ops[2] = { Lo, Hi };
12333 return DAG.getMergeValues(Ops, dl);
12336 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12337 SelectionDAG &DAG) const {
12338 SDValue Src = Op.getOperand(0);
12339 MVT SrcVT = Src.getSimpleValueType();
12340 MVT VT = Op.getSimpleValueType();
12343 if (SrcVT.isVector()) {
12344 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12345 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12346 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12347 DAG.getUNDEF(SrcVT)));
12349 if (SrcVT.getVectorElementType() == MVT::i1) {
12350 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12351 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12352 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12357 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12358 "Unknown SINT_TO_FP to lower!");
12360 // These are really Legal; return the operand so the caller accepts it as
12362 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12364 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12365 Subtarget->is64Bit()) {
12369 unsigned Size = SrcVT.getSizeInBits()/8;
12370 MachineFunction &MF = DAG.getMachineFunction();
12371 auto PtrVT = getPointerTy(MF.getDataLayout());
12372 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12373 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12374 SDValue Chain = DAG.getStore(
12375 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12376 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12378 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12381 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12383 SelectionDAG &DAG) const {
12387 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12389 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12391 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12393 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12395 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12396 MachineMemOperand *MMO;
12398 int SSFI = FI->getIndex();
12399 MMO = DAG.getMachineFunction().getMachineMemOperand(
12400 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12401 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12403 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12404 StackSlot = StackSlot.getOperand(1);
12406 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12407 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12409 Tys, Ops, SrcVT, MMO);
12412 Chain = Result.getValue(1);
12413 SDValue InFlag = Result.getValue(2);
12415 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12416 // shouldn't be necessary except that RFP cannot be live across
12417 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12418 MachineFunction &MF = DAG.getMachineFunction();
12419 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12420 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12421 auto PtrVT = getPointerTy(MF.getDataLayout());
12422 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12423 Tys = DAG.getVTList(MVT::Other);
12425 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12427 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12428 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12429 MachineMemOperand::MOStore, SSFISize, SSFISize);
12431 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12432 Ops, Op.getValueType(), MMO);
12433 Result = DAG.getLoad(
12434 Op.getValueType(), DL, Chain, StackSlot,
12435 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12436 false, false, false, 0);
12442 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12443 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12444 SelectionDAG &DAG) const {
12445 // This algorithm is not obvious. Here it is what we're trying to output:
12448 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12449 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12451 haddpd %xmm0, %xmm0
12453 pshufd $0x4e, %xmm0, %xmm1
12459 LLVMContext *Context = DAG.getContext();
12461 // Build some magic constants.
12462 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12463 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12464 auto PtrVT = getPointerTy(DAG.getDataLayout());
12465 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12467 SmallVector<Constant*,2> CV1;
12469 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12470 APInt(64, 0x4330000000000000ULL))));
12472 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12473 APInt(64, 0x4530000000000000ULL))));
12474 Constant *C1 = ConstantVector::get(CV1);
12475 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12477 // Load the 64-bit value into an XMM register.
12478 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12481 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12482 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12483 false, false, false, 16);
12485 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12488 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12489 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12490 false, false, false, 16);
12491 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12492 // TODO: Are there any fast-math-flags to propagate here?
12493 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12496 if (Subtarget->hasSSE3()) {
12497 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12498 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12500 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12501 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12503 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12504 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12507 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12508 DAG.getIntPtrConstant(0, dl));
12511 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12512 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12513 SelectionDAG &DAG) const {
12515 // FP constant to bias correct the final result.
12516 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12519 // Load the 32-bit value into an XMM register.
12520 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12523 // Zero out the upper parts of the register.
12524 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12526 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12527 DAG.getBitcast(MVT::v2f64, Load),
12528 DAG.getIntPtrConstant(0, dl));
12530 // Or the load with the bias.
12531 SDValue Or = DAG.getNode(
12532 ISD::OR, dl, MVT::v2i64,
12533 DAG.getBitcast(MVT::v2i64,
12534 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12535 DAG.getBitcast(MVT::v2i64,
12536 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12538 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12539 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12541 // Subtract the bias.
12542 // TODO: Are there any fast-math-flags to propagate here?
12543 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12545 // Handle final rounding.
12546 MVT DestVT = Op.getSimpleValueType();
12548 if (DestVT.bitsLT(MVT::f64))
12549 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12550 DAG.getIntPtrConstant(0, dl));
12551 if (DestVT.bitsGT(MVT::f64))
12552 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12554 // Handle final rounding.
12558 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12559 const X86Subtarget &Subtarget) {
12560 // The algorithm is the following:
12561 // #ifdef __SSE4_1__
12562 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12563 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12564 // (uint4) 0x53000000, 0xaa);
12566 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12567 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12569 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12570 // return (float4) lo + fhi;
12572 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12573 // reassociate the two FADDs, and if we do that, the algorithm fails
12574 // spectacularly (PR24512).
12575 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12576 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12577 // there's also the MachineCombiner reassociations happening on Machine IR.
12578 if (DAG.getTarget().Options.UnsafeFPMath)
12582 SDValue V = Op->getOperand(0);
12583 MVT VecIntVT = V.getSimpleValueType();
12584 bool Is128 = VecIntVT == MVT::v4i32;
12585 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12586 // If we convert to something else than the supported type, e.g., to v4f64,
12588 if (VecFloatVT != Op->getSimpleValueType(0))
12591 unsigned NumElts = VecIntVT.getVectorNumElements();
12592 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12593 "Unsupported custom type");
12594 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12596 // In the #idef/#else code, we have in common:
12597 // - The vector of constants:
12603 // Create the splat vector for 0x4b000000.
12604 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12605 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12606 CstLow, CstLow, CstLow, CstLow};
12607 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12608 makeArrayRef(&CstLowArray[0], NumElts));
12609 // Create the splat vector for 0x53000000.
12610 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12611 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12612 CstHigh, CstHigh, CstHigh, CstHigh};
12613 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12614 makeArrayRef(&CstHighArray[0], NumElts));
12616 // Create the right shift.
12617 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12618 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12619 CstShift, CstShift, CstShift, CstShift};
12620 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12621 makeArrayRef(&CstShiftArray[0], NumElts));
12622 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12625 if (Subtarget.hasSSE41()) {
12626 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12627 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12628 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12629 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12630 // Low will be bitcasted right away, so do not bother bitcasting back to its
12632 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12633 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12634 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12635 // (uint4) 0x53000000, 0xaa);
12636 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12637 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12638 // High will be bitcasted right away, so do not bother bitcasting back to
12639 // its original type.
12640 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12641 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12643 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12644 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12645 CstMask, CstMask, CstMask);
12646 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12647 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12648 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12650 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12651 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12654 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12655 SDValue CstFAdd = DAG.getConstantFP(
12656 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12657 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12658 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12659 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12660 makeArrayRef(&CstFAddArray[0], NumElts));
12662 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12663 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12664 // TODO: Are there any fast-math-flags to propagate here?
12666 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12667 // return (float4) lo + fhi;
12668 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12669 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12672 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12673 SelectionDAG &DAG) const {
12674 SDValue N0 = Op.getOperand(0);
12675 MVT SVT = N0.getSimpleValueType();
12678 switch (SVT.SimpleTy) {
12680 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12685 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12686 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12687 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12691 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12694 assert(Subtarget->hasAVX512());
12695 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12696 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12700 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12701 SelectionDAG &DAG) const {
12702 SDValue N0 = Op.getOperand(0);
12704 auto PtrVT = getPointerTy(DAG.getDataLayout());
12706 if (Op.getSimpleValueType().isVector())
12707 return lowerUINT_TO_FP_vec(Op, DAG);
12709 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12710 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12711 // the optimization here.
12712 if (DAG.SignBitIsZero(N0))
12713 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12715 MVT SrcVT = N0.getSimpleValueType();
12716 MVT DstVT = Op.getSimpleValueType();
12718 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12719 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12720 // Conversions from unsigned i32 to f32/f64 are legal,
12721 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12725 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12726 return LowerUINT_TO_FP_i64(Op, DAG);
12727 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12728 return LowerUINT_TO_FP_i32(Op, DAG);
12729 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12732 // Make a 64-bit buffer, and use it to build an FILD.
12733 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12734 if (SrcVT == MVT::i32) {
12735 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12736 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12737 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12738 StackSlot, MachinePointerInfo(),
12740 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12741 OffsetSlot, MachinePointerInfo(),
12743 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12747 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12748 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12749 StackSlot, MachinePointerInfo(),
12751 // For i64 source, we need to add the appropriate power of 2 if the input
12752 // was negative. This is the same as the optimization in
12753 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12754 // we must be careful to do the computation in x87 extended precision, not
12755 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12756 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12757 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12758 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12759 MachineMemOperand::MOLoad, 8, 8);
12761 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12762 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12763 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12766 APInt FF(32, 0x5F800000ULL);
12768 // Check whether the sign bit is set.
12769 SDValue SignSet = DAG.getSetCC(
12770 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12771 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12773 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12774 SDValue FudgePtr = DAG.getConstantPool(
12775 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12777 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12778 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12779 SDValue Four = DAG.getIntPtrConstant(4, dl);
12780 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12782 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12784 // Load the value out, extending it from f32 to f80.
12785 // FIXME: Avoid the extend by constructing the right constant pool?
12786 SDValue Fudge = DAG.getExtLoad(
12787 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12788 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12789 false, false, false, 4);
12790 // Extend everything to 80 bits to force it to be done on x87.
12791 // TODO: Are there any fast-math-flags to propagate here?
12792 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12793 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12794 DAG.getIntPtrConstant(0, dl));
12797 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12798 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12799 // just return an <SDValue(), SDValue()> pair.
12800 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12801 // to i16, i32 or i64, and we lower it to a legal sequence.
12802 // If lowered to the final integer result we return a <result, SDValue()> pair.
12803 // Otherwise we lower it to a sequence ending with a FIST, return a
12804 // <FIST, StackSlot> pair, and the caller is responsible for loading
12805 // the final integer result from StackSlot.
12806 std::pair<SDValue,SDValue>
12807 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12808 bool IsSigned, bool IsReplace) const {
12811 EVT DstTy = Op.getValueType();
12812 EVT TheVT = Op.getOperand(0).getValueType();
12813 auto PtrVT = getPointerTy(DAG.getDataLayout());
12815 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12816 // f16 must be promoted before using the lowering in this routine.
12817 // fp128 does not use this lowering.
12818 return std::make_pair(SDValue(), SDValue());
12821 // If using FIST to compute an unsigned i64, we'll need some fixup
12822 // to handle values above the maximum signed i64. A FIST is always
12823 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12824 bool UnsignedFixup = !IsSigned &&
12825 DstTy == MVT::i64 &&
12826 (!Subtarget->is64Bit() ||
12827 !isScalarFPTypeInSSEReg(TheVT));
12829 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12830 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12831 // The low 32 bits of the fist result will have the correct uint32 result.
12832 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12836 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12837 DstTy.getSimpleVT() >= MVT::i16 &&
12838 "Unknown FP_TO_INT to lower!");
12840 // These are really Legal.
12841 if (DstTy == MVT::i32 &&
12842 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12843 return std::make_pair(SDValue(), SDValue());
12844 if (Subtarget->is64Bit() &&
12845 DstTy == MVT::i64 &&
12846 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12847 return std::make_pair(SDValue(), SDValue());
12849 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12851 MachineFunction &MF = DAG.getMachineFunction();
12852 unsigned MemSize = DstTy.getSizeInBits()/8;
12853 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12854 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12857 switch (DstTy.getSimpleVT().SimpleTy) {
12858 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12859 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12860 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12861 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12864 SDValue Chain = DAG.getEntryNode();
12865 SDValue Value = Op.getOperand(0);
12866 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12868 if (UnsignedFixup) {
12870 // Conversion to unsigned i64 is implemented with a select,
12871 // depending on whether the source value fits in the range
12872 // of a signed i64. Let Thresh be the FP equivalent of
12873 // 0x8000000000000000ULL.
12875 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12876 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12877 // Fist-to-mem64 FistSrc
12878 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12879 // to XOR'ing the high 32 bits with Adjust.
12881 // Being a power of 2, Thresh is exactly representable in all FP formats.
12882 // For X87 we'd like to use the smallest FP type for this constant, but
12883 // for DAG type consistency we have to match the FP operand type.
12885 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12886 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12887 bool LosesInfo = false;
12888 if (TheVT == MVT::f64)
12889 // The rounding mode is irrelevant as the conversion should be exact.
12890 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12892 else if (TheVT == MVT::f80)
12893 Status = Thresh.convert(APFloat::x87DoubleExtended,
12894 APFloat::rmNearestTiesToEven, &LosesInfo);
12896 assert(Status == APFloat::opOK && !LosesInfo &&
12897 "FP conversion should have been exact");
12899 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12901 SDValue Cmp = DAG.getSetCC(DL,
12902 getSetCCResultType(DAG.getDataLayout(),
12903 *DAG.getContext(), TheVT),
12904 Value, ThreshVal, ISD::SETLT);
12905 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12906 DAG.getConstant(0, DL, MVT::i32),
12907 DAG.getConstant(0x80000000, DL, MVT::i32));
12908 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12909 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12910 *DAG.getContext(), TheVT),
12911 Value, ThreshVal, ISD::SETLT);
12912 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12915 // FIXME This causes a redundant load/store if the SSE-class value is already
12916 // in memory, such as if it is on the callstack.
12917 if (isScalarFPTypeInSSEReg(TheVT)) {
12918 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12919 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12920 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12922 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12924 Chain, StackSlot, DAG.getValueType(TheVT)
12927 MachineMemOperand *MMO =
12928 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12929 MachineMemOperand::MOLoad, MemSize, MemSize);
12930 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12931 Chain = Value.getValue(1);
12932 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12933 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12936 MachineMemOperand *MMO =
12937 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12938 MachineMemOperand::MOStore, MemSize, MemSize);
12940 if (UnsignedFixup) {
12942 // Insert the FIST, load its result as two i32's,
12943 // and XOR the high i32 with Adjust.
12945 SDValue FistOps[] = { Chain, Value, StackSlot };
12946 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12947 FistOps, DstTy, MMO);
12949 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12950 MachinePointerInfo(),
12951 false, false, false, 0);
12952 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12953 DAG.getConstant(4, DL, PtrVT));
12955 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12956 MachinePointerInfo(),
12957 false, false, false, 0);
12958 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12960 if (Subtarget->is64Bit()) {
12961 // Join High32 and Low32 into a 64-bit result.
12962 // (High32 << 32) | Low32
12963 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12964 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12965 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12966 DAG.getConstant(32, DL, MVT::i8));
12967 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12968 return std::make_pair(Result, SDValue());
12971 SDValue ResultOps[] = { Low32, High32 };
12973 SDValue pair = IsReplace
12974 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12975 : DAG.getMergeValues(ResultOps, DL);
12976 return std::make_pair(pair, SDValue());
12978 // Build the FP_TO_INT*_IN_MEM
12979 SDValue Ops[] = { Chain, Value, StackSlot };
12980 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12982 return std::make_pair(FIST, StackSlot);
12986 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12987 const X86Subtarget *Subtarget) {
12988 MVT VT = Op->getSimpleValueType(0);
12989 SDValue In = Op->getOperand(0);
12990 MVT InVT = In.getSimpleValueType();
12993 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12994 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12996 // Optimize vectors in AVX mode:
12999 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13000 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13001 // Concat upper and lower parts.
13004 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13005 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13006 // Concat upper and lower parts.
13009 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13010 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13011 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13014 if (Subtarget->hasInt256())
13015 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13017 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13018 SDValue Undef = DAG.getUNDEF(InVT);
13019 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13020 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13021 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13023 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13024 VT.getVectorNumElements()/2);
13026 OpLo = DAG.getBitcast(HVT, OpLo);
13027 OpHi = DAG.getBitcast(HVT, OpHi);
13029 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13032 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13033 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13034 MVT VT = Op->getSimpleValueType(0);
13035 SDValue In = Op->getOperand(0);
13036 MVT InVT = In.getSimpleValueType();
13038 unsigned int NumElts = VT.getVectorNumElements();
13039 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13042 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13043 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13045 assert(InVT.getVectorElementType() == MVT::i1);
13046 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13048 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13050 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13052 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13053 if (VT.is512BitVector())
13055 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13058 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13059 SelectionDAG &DAG) {
13060 if (Subtarget->hasFp256())
13061 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13067 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13068 SelectionDAG &DAG) {
13070 MVT VT = Op.getSimpleValueType();
13071 SDValue In = Op.getOperand(0);
13072 MVT SVT = In.getSimpleValueType();
13074 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13075 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13077 if (Subtarget->hasFp256())
13078 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13081 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13082 VT.getVectorNumElements() != SVT.getVectorNumElements());
13086 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13088 MVT VT = Op.getSimpleValueType();
13089 SDValue In = Op.getOperand(0);
13090 MVT InVT = In.getSimpleValueType();
13092 if (VT == MVT::i1) {
13093 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13094 "Invalid scalar TRUNCATE operation");
13095 if (InVT.getSizeInBits() >= 32)
13097 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13098 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13100 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13101 "Invalid TRUNCATE operation");
13103 // move vector to mask - truncate solution for SKX
13104 if (VT.getVectorElementType() == MVT::i1) {
13105 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13106 Subtarget->hasBWI())
13107 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13108 if ((InVT.is256BitVector() || InVT.is128BitVector())
13109 && InVT.getScalarSizeInBits() <= 16 &&
13110 Subtarget->hasBWI() && Subtarget->hasVLX())
13111 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13112 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13113 Subtarget->hasDQI())
13114 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13115 if ((InVT.is256BitVector() || InVT.is128BitVector())
13116 && InVT.getScalarSizeInBits() >= 32 &&
13117 Subtarget->hasDQI() && Subtarget->hasVLX())
13118 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13121 if (VT.getVectorElementType() == MVT::i1) {
13122 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13123 unsigned NumElts = InVT.getVectorNumElements();
13124 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13125 if (InVT.getSizeInBits() < 512) {
13126 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13127 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13132 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13133 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13134 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13137 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13138 if (Subtarget->hasAVX512()) {
13139 // word to byte only under BWI
13140 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13141 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13142 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13143 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13145 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13146 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13147 if (Subtarget->hasInt256()) {
13148 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13149 In = DAG.getBitcast(MVT::v8i32, In);
13150 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13152 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13153 DAG.getIntPtrConstant(0, DL));
13156 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13157 DAG.getIntPtrConstant(0, DL));
13158 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13159 DAG.getIntPtrConstant(2, DL));
13160 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13161 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13162 static const int ShufMask[] = {0, 2, 4, 6};
13163 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13166 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13167 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13168 if (Subtarget->hasInt256()) {
13169 In = DAG.getBitcast(MVT::v32i8, In);
13171 SmallVector<SDValue,32> pshufbMask;
13172 for (unsigned i = 0; i < 2; ++i) {
13173 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13174 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13175 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13176 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13177 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13178 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13179 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13180 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13181 for (unsigned j = 0; j < 8; ++j)
13182 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13184 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13185 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13186 In = DAG.getBitcast(MVT::v4i64, In);
13188 static const int ShufMask[] = {0, 2, -1, -1};
13189 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13191 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13192 DAG.getIntPtrConstant(0, DL));
13193 return DAG.getBitcast(VT, In);
13196 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13197 DAG.getIntPtrConstant(0, DL));
13199 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13200 DAG.getIntPtrConstant(4, DL));
13202 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13203 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13205 // The PSHUFB mask:
13206 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13207 -1, -1, -1, -1, -1, -1, -1, -1};
13209 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13210 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13211 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13213 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13214 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13216 // The MOVLHPS Mask:
13217 static const int ShufMask2[] = {0, 1, 4, 5};
13218 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13219 return DAG.getBitcast(MVT::v8i16, res);
13222 // Handle truncation of V256 to V128 using shuffles.
13223 if (!VT.is128BitVector() || !InVT.is256BitVector())
13226 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13228 unsigned NumElems = VT.getVectorNumElements();
13229 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13231 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13232 // Prepare truncation shuffle mask
13233 for (unsigned i = 0; i != NumElems; ++i)
13234 MaskVec[i] = i * 2;
13235 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13236 DAG.getUNDEF(NVT), &MaskVec[0]);
13237 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13238 DAG.getIntPtrConstant(0, DL));
13241 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13242 SelectionDAG &DAG) const {
13243 assert(!Op.getSimpleValueType().isVector());
13245 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13246 /*IsSigned=*/ true, /*IsReplace=*/ false);
13247 SDValue FIST = Vals.first, StackSlot = Vals.second;
13248 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13249 if (!FIST.getNode())
13252 if (StackSlot.getNode())
13253 // Load the result.
13254 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13255 FIST, StackSlot, MachinePointerInfo(),
13256 false, false, false, 0);
13258 // The node is the result.
13262 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13263 SelectionDAG &DAG) const {
13264 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13265 /*IsSigned=*/ false, /*IsReplace=*/ false);
13266 SDValue FIST = Vals.first, StackSlot = Vals.second;
13267 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13268 if (!FIST.getNode())
13271 if (StackSlot.getNode())
13272 // Load the result.
13273 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13274 FIST, StackSlot, MachinePointerInfo(),
13275 false, false, false, 0);
13277 // The node is the result.
13281 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13283 MVT VT = Op.getSimpleValueType();
13284 SDValue In = Op.getOperand(0);
13285 MVT SVT = In.getSimpleValueType();
13287 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13289 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13290 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13291 In, DAG.getUNDEF(SVT)));
13294 /// The only differences between FABS and FNEG are the mask and the logic op.
13295 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13296 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13297 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13298 "Wrong opcode for lowering FABS or FNEG.");
13300 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13302 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13303 // into an FNABS. We'll lower the FABS after that if it is still in use.
13305 for (SDNode *User : Op->uses())
13306 if (User->getOpcode() == ISD::FNEG)
13310 MVT VT = Op.getSimpleValueType();
13312 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13313 // decide if we should generate a 16-byte constant mask when we only need 4 or
13314 // 8 bytes for the scalar case.
13320 if (VT.isVector()) {
13322 EltVT = VT.getVectorElementType();
13323 NumElts = VT.getVectorNumElements();
13325 // There are no scalar bitwise logical SSE/AVX instructions, so we
13326 // generate a 16-byte vector constant and logic op even for the scalar case.
13327 // Using a 16-byte mask allows folding the load of the mask with
13328 // the logic op, so it can save (~4 bytes) on code size.
13329 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13331 NumElts = (VT == MVT::f64) ? 2 : 4;
13334 unsigned EltBits = EltVT.getSizeInBits();
13335 LLVMContext *Context = DAG.getContext();
13336 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13338 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13339 Constant *C = ConstantInt::get(*Context, MaskElt);
13340 C = ConstantVector::getSplat(NumElts, C);
13341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13342 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13343 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13345 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13346 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13347 false, false, false, Alignment);
13349 SDValue Op0 = Op.getOperand(0);
13350 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13352 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13353 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13356 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13358 // For the scalar case extend to a 128-bit vector, perform the logic op,
13359 // and extract the scalar result back out.
13360 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13361 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13362 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13363 DAG.getIntPtrConstant(0, dl));
13366 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13367 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13368 LLVMContext *Context = DAG.getContext();
13369 SDValue Op0 = Op.getOperand(0);
13370 SDValue Op1 = Op.getOperand(1);
13372 MVT VT = Op.getSimpleValueType();
13373 MVT SrcVT = Op1.getSimpleValueType();
13375 // If second operand is smaller, extend it first.
13376 if (SrcVT.bitsLT(VT)) {
13377 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13380 // And if it is bigger, shrink it first.
13381 if (SrcVT.bitsGT(VT)) {
13382 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13386 // At this point the operands and the result should have the same
13387 // type, and that won't be f80 since that is not custom lowered.
13389 const fltSemantics &Sem =
13390 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13391 const unsigned SizeInBits = VT.getSizeInBits();
13393 SmallVector<Constant *, 4> CV(
13394 VT == MVT::f64 ? 2 : 4,
13395 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13397 // First, clear all bits but the sign bit from the second operand (sign).
13398 CV[0] = ConstantFP::get(*Context,
13399 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13400 Constant *C = ConstantVector::get(CV);
13401 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13402 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13404 // Perform all logic operations as 16-byte vectors because there are no
13405 // scalar FP logic instructions in SSE. This allows load folding of the
13406 // constants into the logic instructions.
13407 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13409 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13410 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13411 false, false, false, 16);
13412 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13413 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13415 // Next, clear the sign bit from the first operand (magnitude).
13416 // If it's a constant, we can clear it here.
13417 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13418 APFloat APF = Op0CN->getValueAPF();
13419 // If the magnitude is a positive zero, the sign bit alone is enough.
13420 if (APF.isPosZero())
13421 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13422 DAG.getIntPtrConstant(0, dl));
13424 CV[0] = ConstantFP::get(*Context, APF);
13426 CV[0] = ConstantFP::get(
13428 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13430 C = ConstantVector::get(CV);
13431 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13433 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13434 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13435 false, false, false, 16);
13436 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13437 if (!isa<ConstantFPSDNode>(Op0)) {
13438 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13439 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13441 // OR the magnitude value with the sign bit.
13442 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13443 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13444 DAG.getIntPtrConstant(0, dl));
13447 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13448 SDValue N0 = Op.getOperand(0);
13450 MVT VT = Op.getSimpleValueType();
13452 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13453 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13454 DAG.getConstant(1, dl, VT));
13455 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13458 // Check whether an OR'd tree is PTEST-able.
13459 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13460 SelectionDAG &DAG) {
13461 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13463 if (!Subtarget->hasSSE41())
13466 if (!Op->hasOneUse())
13469 SDNode *N = Op.getNode();
13472 SmallVector<SDValue, 8> Opnds;
13473 DenseMap<SDValue, unsigned> VecInMap;
13474 SmallVector<SDValue, 8> VecIns;
13475 EVT VT = MVT::Other;
13477 // Recognize a special case where a vector is casted into wide integer to
13479 Opnds.push_back(N->getOperand(0));
13480 Opnds.push_back(N->getOperand(1));
13482 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13483 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13484 // BFS traverse all OR'd operands.
13485 if (I->getOpcode() == ISD::OR) {
13486 Opnds.push_back(I->getOperand(0));
13487 Opnds.push_back(I->getOperand(1));
13488 // Re-evaluate the number of nodes to be traversed.
13489 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13493 // Quit if a non-EXTRACT_VECTOR_ELT
13494 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13497 // Quit if without a constant index.
13498 SDValue Idx = I->getOperand(1);
13499 if (!isa<ConstantSDNode>(Idx))
13502 SDValue ExtractedFromVec = I->getOperand(0);
13503 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13504 if (M == VecInMap.end()) {
13505 VT = ExtractedFromVec.getValueType();
13506 // Quit if not 128/256-bit vector.
13507 if (!VT.is128BitVector() && !VT.is256BitVector())
13509 // Quit if not the same type.
13510 if (VecInMap.begin() != VecInMap.end() &&
13511 VT != VecInMap.begin()->first.getValueType())
13513 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13514 VecIns.push_back(ExtractedFromVec);
13516 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13519 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13520 "Not extracted from 128-/256-bit vector.");
13522 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13524 for (DenseMap<SDValue, unsigned>::const_iterator
13525 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13526 // Quit if not all elements are used.
13527 if (I->second != FullMask)
13531 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13533 // Cast all vectors into TestVT for PTEST.
13534 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13535 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13537 // If more than one full vectors are evaluated, OR them first before PTEST.
13538 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13539 // Each iteration will OR 2 nodes and append the result until there is only
13540 // 1 node left, i.e. the final OR'd value of all vectors.
13541 SDValue LHS = VecIns[Slot];
13542 SDValue RHS = VecIns[Slot + 1];
13543 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13546 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13547 VecIns.back(), VecIns.back());
13550 /// \brief return true if \c Op has a use that doesn't just read flags.
13551 static bool hasNonFlagsUse(SDValue Op) {
13552 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13554 SDNode *User = *UI;
13555 unsigned UOpNo = UI.getOperandNo();
13556 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13557 // Look pass truncate.
13558 UOpNo = User->use_begin().getOperandNo();
13559 User = *User->use_begin();
13562 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13563 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13569 /// Emit nodes that will be selected as "test Op0,Op0", or something
13571 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13572 SelectionDAG &DAG) const {
13573 if (Op.getValueType() == MVT::i1) {
13574 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13575 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13576 DAG.getConstant(0, dl, MVT::i8));
13578 // CF and OF aren't always set the way we want. Determine which
13579 // of these we need.
13580 bool NeedCF = false;
13581 bool NeedOF = false;
13584 case X86::COND_A: case X86::COND_AE:
13585 case X86::COND_B: case X86::COND_BE:
13588 case X86::COND_G: case X86::COND_GE:
13589 case X86::COND_L: case X86::COND_LE:
13590 case X86::COND_O: case X86::COND_NO: {
13591 // Check if we really need to set the
13592 // Overflow flag. If NoSignedWrap is present
13593 // that is not actually needed.
13594 switch (Op->getOpcode()) {
13599 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13600 if (BinNode->Flags.hasNoSignedWrap())
13610 // See if we can use the EFLAGS value from the operand instead of
13611 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13612 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13613 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13614 // Emit a CMP with 0, which is the TEST pattern.
13615 //if (Op.getValueType() == MVT::i1)
13616 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13617 // DAG.getConstant(0, MVT::i1));
13618 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13619 DAG.getConstant(0, dl, Op.getValueType()));
13621 unsigned Opcode = 0;
13622 unsigned NumOperands = 0;
13624 // Truncate operations may prevent the merge of the SETCC instruction
13625 // and the arithmetic instruction before it. Attempt to truncate the operands
13626 // of the arithmetic instruction and use a reduced bit-width instruction.
13627 bool NeedTruncation = false;
13628 SDValue ArithOp = Op;
13629 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13630 SDValue Arith = Op->getOperand(0);
13631 // Both the trunc and the arithmetic op need to have one user each.
13632 if (Arith->hasOneUse())
13633 switch (Arith.getOpcode()) {
13640 NeedTruncation = true;
13646 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13647 // which may be the result of a CAST. We use the variable 'Op', which is the
13648 // non-casted variable when we check for possible users.
13649 switch (ArithOp.getOpcode()) {
13651 // Due to an isel shortcoming, be conservative if this add is likely to be
13652 // selected as part of a load-modify-store instruction. When the root node
13653 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13654 // uses of other nodes in the match, such as the ADD in this case. This
13655 // leads to the ADD being left around and reselected, with the result being
13656 // two adds in the output. Alas, even if none our users are stores, that
13657 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13658 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13659 // climbing the DAG back to the root, and it doesn't seem to be worth the
13661 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13662 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13663 if (UI->getOpcode() != ISD::CopyToReg &&
13664 UI->getOpcode() != ISD::SETCC &&
13665 UI->getOpcode() != ISD::STORE)
13668 if (ConstantSDNode *C =
13669 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13670 // An add of one will be selected as an INC.
13671 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13672 Opcode = X86ISD::INC;
13677 // An add of negative one (subtract of one) will be selected as a DEC.
13678 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13679 Opcode = X86ISD::DEC;
13685 // Otherwise use a regular EFLAGS-setting add.
13686 Opcode = X86ISD::ADD;
13691 // If we have a constant logical shift that's only used in a comparison
13692 // against zero turn it into an equivalent AND. This allows turning it into
13693 // a TEST instruction later.
13694 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13695 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13696 EVT VT = Op.getValueType();
13697 unsigned BitWidth = VT.getSizeInBits();
13698 unsigned ShAmt = Op->getConstantOperandVal(1);
13699 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13701 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13702 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13703 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13704 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13706 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13707 DAG.getConstant(Mask, dl, VT));
13708 DAG.ReplaceAllUsesWith(Op, New);
13714 // If the primary and result isn't used, don't bother using X86ISD::AND,
13715 // because a TEST instruction will be better.
13716 if (!hasNonFlagsUse(Op))
13722 // Due to the ISEL shortcoming noted above, be conservative if this op is
13723 // likely to be selected as part of a load-modify-store instruction.
13724 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13725 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13726 if (UI->getOpcode() == ISD::STORE)
13729 // Otherwise use a regular EFLAGS-setting instruction.
13730 switch (ArithOp.getOpcode()) {
13731 default: llvm_unreachable("unexpected operator!");
13732 case ISD::SUB: Opcode = X86ISD::SUB; break;
13733 case ISD::XOR: Opcode = X86ISD::XOR; break;
13734 case ISD::AND: Opcode = X86ISD::AND; break;
13736 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13737 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13738 if (EFLAGS.getNode())
13741 Opcode = X86ISD::OR;
13755 return SDValue(Op.getNode(), 1);
13761 // If we found that truncation is beneficial, perform the truncation and
13763 if (NeedTruncation) {
13764 EVT VT = Op.getValueType();
13765 SDValue WideVal = Op->getOperand(0);
13766 EVT WideVT = WideVal.getValueType();
13767 unsigned ConvertedOp = 0;
13768 // Use a target machine opcode to prevent further DAGCombine
13769 // optimizations that may separate the arithmetic operations
13770 // from the setcc node.
13771 switch (WideVal.getOpcode()) {
13773 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13774 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13775 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13776 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13777 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13782 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13783 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13784 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13785 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13791 // Emit a CMP with 0, which is the TEST pattern.
13792 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13793 DAG.getConstant(0, dl, Op.getValueType()));
13795 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13796 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13798 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13799 DAG.ReplaceAllUsesWith(Op, New);
13800 return SDValue(New.getNode(), 1);
13803 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13805 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13806 SDLoc dl, SelectionDAG &DAG) const {
13807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13808 if (C->getAPIntValue() == 0)
13809 return EmitTest(Op0, X86CC, dl, DAG);
13811 assert(Op0.getValueType() != MVT::i1 &&
13812 "Unexpected comparison operation for MVT::i1 operands");
13815 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13816 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13817 // Do the comparison at i32 if it's smaller, besides the Atom case.
13818 // This avoids subregister aliasing issues. Keep the smaller reference
13819 // if we're optimizing for size, however, as that'll allow better folding
13820 // of memory operations.
13821 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13822 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13823 !Subtarget->isAtom()) {
13824 unsigned ExtendOp =
13825 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13826 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13827 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13829 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13830 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13831 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13833 return SDValue(Sub.getNode(), 1);
13835 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13838 /// Convert a comparison if required by the subtarget.
13839 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13840 SelectionDAG &DAG) const {
13841 // If the subtarget does not support the FUCOMI instruction, floating-point
13842 // comparisons have to be converted.
13843 if (Subtarget->hasCMov() ||
13844 Cmp.getOpcode() != X86ISD::CMP ||
13845 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13846 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13849 // The instruction selector will select an FUCOM instruction instead of
13850 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13851 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13852 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13854 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13855 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13856 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13857 DAG.getConstant(8, dl, MVT::i8));
13858 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13859 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13862 /// The minimum architected relative accuracy is 2^-12. We need one
13863 /// Newton-Raphson step to have a good float result (24 bits of precision).
13864 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13865 DAGCombinerInfo &DCI,
13866 unsigned &RefinementSteps,
13867 bool &UseOneConstNR) const {
13868 EVT VT = Op.getValueType();
13869 const char *RecipOp;
13871 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13872 // TODO: Add support for AVX512 (v16f32).
13873 // It is likely not profitable to do this for f64 because a double-precision
13874 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13875 // instructions: convert to single, rsqrtss, convert back to double, refine
13876 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13877 // along with FMA, this could be a throughput win.
13878 if (VT == MVT::f32 && Subtarget->hasSSE1())
13880 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13881 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13882 RecipOp = "vec-sqrtf";
13886 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13887 if (!Recips.isEnabled(RecipOp))
13890 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13891 UseOneConstNR = false;
13892 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13895 /// The minimum architected relative accuracy is 2^-12. We need one
13896 /// Newton-Raphson step to have a good float result (24 bits of precision).
13897 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13898 DAGCombinerInfo &DCI,
13899 unsigned &RefinementSteps) const {
13900 EVT VT = Op.getValueType();
13901 const char *RecipOp;
13903 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13904 // TODO: Add support for AVX512 (v16f32).
13905 // It is likely not profitable to do this for f64 because a double-precision
13906 // reciprocal estimate with refinement on x86 prior to FMA requires
13907 // 15 instructions: convert to single, rcpss, convert back to double, refine
13908 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13909 // along with FMA, this could be a throughput win.
13910 if (VT == MVT::f32 && Subtarget->hasSSE1())
13912 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13913 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13914 RecipOp = "vec-divf";
13918 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13919 if (!Recips.isEnabled(RecipOp))
13922 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13923 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13926 /// If we have at least two divisions that use the same divisor, convert to
13927 /// multplication by a reciprocal. This may need to be adjusted for a given
13928 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13929 /// This is because we still need one division to calculate the reciprocal and
13930 /// then we need two multiplies by that reciprocal as replacements for the
13931 /// original divisions.
13932 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13936 static bool isAllOnes(SDValue V) {
13937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13938 return C && C->isAllOnesValue();
13941 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13942 /// if it's possible.
13943 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13944 SDLoc dl, SelectionDAG &DAG) const {
13945 SDValue Op0 = And.getOperand(0);
13946 SDValue Op1 = And.getOperand(1);
13947 if (Op0.getOpcode() == ISD::TRUNCATE)
13948 Op0 = Op0.getOperand(0);
13949 if (Op1.getOpcode() == ISD::TRUNCATE)
13950 Op1 = Op1.getOperand(0);
13953 if (Op1.getOpcode() == ISD::SHL)
13954 std::swap(Op0, Op1);
13955 if (Op0.getOpcode() == ISD::SHL) {
13956 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13957 if (And00C->getZExtValue() == 1) {
13958 // If we looked past a truncate, check that it's only truncating away
13960 unsigned BitWidth = Op0.getValueSizeInBits();
13961 unsigned AndBitWidth = And.getValueSizeInBits();
13962 if (BitWidth > AndBitWidth) {
13964 DAG.computeKnownBits(Op0, Zeros, Ones);
13965 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13969 RHS = Op0.getOperand(1);
13971 } else if (Op1.getOpcode() == ISD::Constant) {
13972 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13973 uint64_t AndRHSVal = AndRHS->getZExtValue();
13974 SDValue AndLHS = Op0;
13976 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13977 LHS = AndLHS.getOperand(0);
13978 RHS = AndLHS.getOperand(1);
13981 // Use BT if the immediate can't be encoded in a TEST instruction.
13982 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13984 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13988 if (LHS.getNode()) {
13989 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13990 // instruction. Since the shift amount is in-range-or-undefined, we know
13991 // that doing a bittest on the i32 value is ok. We extend to i32 because
13992 // the encoding for the i16 version is larger than the i32 version.
13993 // Also promote i16 to i32 for performance / code size reason.
13994 if (LHS.getValueType() == MVT::i8 ||
13995 LHS.getValueType() == MVT::i16)
13996 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13998 // If the operand types disagree, extend the shift amount to match. Since
13999 // BT ignores high bits (like shifts) we can use anyextend.
14000 if (LHS.getValueType() != RHS.getValueType())
14001 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14003 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14004 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14005 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14006 DAG.getConstant(Cond, dl, MVT::i8), BT);
14012 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14014 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14019 // SSE Condition code mapping:
14028 switch (SetCCOpcode) {
14029 default: llvm_unreachable("Unexpected SETCC condition");
14031 case ISD::SETEQ: SSECC = 0; break;
14033 case ISD::SETGT: Swap = true; // Fallthrough
14035 case ISD::SETOLT: SSECC = 1; break;
14037 case ISD::SETGE: Swap = true; // Fallthrough
14039 case ISD::SETOLE: SSECC = 2; break;
14040 case ISD::SETUO: SSECC = 3; break;
14042 case ISD::SETNE: SSECC = 4; break;
14043 case ISD::SETULE: Swap = true; // Fallthrough
14044 case ISD::SETUGE: SSECC = 5; break;
14045 case ISD::SETULT: Swap = true; // Fallthrough
14046 case ISD::SETUGT: SSECC = 6; break;
14047 case ISD::SETO: SSECC = 7; break;
14049 case ISD::SETONE: SSECC = 8; break;
14052 std::swap(Op0, Op1);
14057 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14058 // ones, and then concatenate the result back.
14059 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14060 MVT VT = Op.getSimpleValueType();
14062 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14063 "Unsupported value type for operation");
14065 unsigned NumElems = VT.getVectorNumElements();
14067 SDValue CC = Op.getOperand(2);
14069 // Extract the LHS vectors
14070 SDValue LHS = Op.getOperand(0);
14071 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14072 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14074 // Extract the RHS vectors
14075 SDValue RHS = Op.getOperand(1);
14076 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14077 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14079 // Issue the operation on the smaller types and concatenate the result back
14080 MVT EltVT = VT.getVectorElementType();
14081 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14082 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14083 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14084 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14087 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14088 SDValue Op0 = Op.getOperand(0);
14089 SDValue Op1 = Op.getOperand(1);
14090 SDValue CC = Op.getOperand(2);
14091 MVT VT = Op.getSimpleValueType();
14094 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14095 "Unexpected type for boolean compare operation");
14096 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14097 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14098 DAG.getConstant(-1, dl, VT));
14099 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14100 DAG.getConstant(-1, dl, VT));
14101 switch (SetCCOpcode) {
14102 default: llvm_unreachable("Unexpected SETCC condition");
14104 // (x == y) -> ~(x ^ y)
14105 return DAG.getNode(ISD::XOR, dl, VT,
14106 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14107 DAG.getConstant(-1, dl, VT));
14109 // (x != y) -> (x ^ y)
14110 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14113 // (x > y) -> (x & ~y)
14114 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14117 // (x < y) -> (~x & y)
14118 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14121 // (x <= y) -> (~x | y)
14122 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14125 // (x >=y) -> (x | ~y)
14126 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14130 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14131 const X86Subtarget *Subtarget) {
14132 SDValue Op0 = Op.getOperand(0);
14133 SDValue Op1 = Op.getOperand(1);
14134 SDValue CC = Op.getOperand(2);
14135 MVT VT = Op.getSimpleValueType();
14138 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14139 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14140 "Cannot set masked compare for this operation");
14142 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14144 bool Unsigned = false;
14147 switch (SetCCOpcode) {
14148 default: llvm_unreachable("Unexpected SETCC condition");
14149 case ISD::SETNE: SSECC = 4; break;
14150 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14151 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14152 case ISD::SETLT: Swap = true; //fall-through
14153 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14154 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14155 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14156 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14157 case ISD::SETULE: Unsigned = true; //fall-through
14158 case ISD::SETLE: SSECC = 2; break;
14162 std::swap(Op0, Op1);
14164 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14165 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14166 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14167 DAG.getConstant(SSECC, dl, MVT::i8));
14170 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14171 /// operand \p Op1. If non-trivial (for example because it's not constant)
14172 /// return an empty value.
14173 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14175 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14179 MVT VT = Op1.getSimpleValueType();
14180 MVT EVT = VT.getVectorElementType();
14181 unsigned n = VT.getVectorNumElements();
14182 SmallVector<SDValue, 8> ULTOp1;
14184 for (unsigned i = 0; i < n; ++i) {
14185 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14186 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14189 // Avoid underflow.
14190 APInt Val = Elt->getAPIntValue();
14194 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14197 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14200 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14201 SelectionDAG &DAG) {
14202 SDValue Op0 = Op.getOperand(0);
14203 SDValue Op1 = Op.getOperand(1);
14204 SDValue CC = Op.getOperand(2);
14205 MVT VT = Op.getSimpleValueType();
14206 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14207 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14212 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14213 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14216 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14217 unsigned Opc = X86ISD::CMPP;
14218 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14219 assert(VT.getVectorNumElements() <= 16);
14220 Opc = X86ISD::CMPM;
14222 // In the two special cases we can't handle, emit two comparisons.
14225 unsigned CombineOpc;
14226 if (SetCCOpcode == ISD::SETUEQ) {
14227 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14229 assert(SetCCOpcode == ISD::SETONE);
14230 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14233 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14234 DAG.getConstant(CC0, dl, MVT::i8));
14235 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14236 DAG.getConstant(CC1, dl, MVT::i8));
14237 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14239 // Handle all other FP comparisons here.
14240 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14241 DAG.getConstant(SSECC, dl, MVT::i8));
14244 MVT VTOp0 = Op0.getSimpleValueType();
14245 assert(VTOp0 == Op1.getSimpleValueType() &&
14246 "Expected operands with same type!");
14247 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14248 "Invalid number of packed elements for source and destination!");
14250 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14251 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14252 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14253 // legalizer firstly checks if the first operand in input to the setcc has
14254 // a legal type. If so, then it promotes the return type to that same type.
14255 // Otherwise, the return type is promoted to the 'next legal type' which,
14256 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14258 // We reach this code only if the following two conditions are met:
14259 // 1. Both return type and operand type have been promoted to wider types
14260 // by the type legalizer.
14261 // 2. The original operand type has been promoted to a 256-bit vector.
14263 // Note that condition 2. only applies for AVX targets.
14264 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14265 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14268 // The non-AVX512 code below works under the assumption that source and
14269 // destination types are the same.
14270 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14271 "Value types for source and destination must be the same!");
14273 // Break 256-bit integer vector compare into smaller ones.
14274 if (VT.is256BitVector() && !Subtarget->hasInt256())
14275 return Lower256IntVSETCC(Op, DAG);
14277 MVT OpVT = Op1.getSimpleValueType();
14278 if (OpVT.getVectorElementType() == MVT::i1)
14279 return LowerBoolVSETCC_AVX512(Op, DAG);
14281 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14282 if (Subtarget->hasAVX512()) {
14283 if (Op1.getSimpleValueType().is512BitVector() ||
14284 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14285 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14286 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14288 // In AVX-512 architecture setcc returns mask with i1 elements,
14289 // But there is no compare instruction for i8 and i16 elements in KNL.
14290 // We are not talking about 512-bit operands in this case, these
14291 // types are illegal.
14293 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14294 OpVT.getVectorElementType().getSizeInBits() >= 8))
14295 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14296 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14299 // Lower using XOP integer comparisons.
14300 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14301 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14302 // Translate compare code to XOP PCOM compare mode.
14303 unsigned CmpMode = 0;
14304 switch (SetCCOpcode) {
14305 default: llvm_unreachable("Unexpected SETCC condition");
14307 case ISD::SETLT: CmpMode = 0x00; break;
14309 case ISD::SETLE: CmpMode = 0x01; break;
14311 case ISD::SETGT: CmpMode = 0x02; break;
14313 case ISD::SETGE: CmpMode = 0x03; break;
14314 case ISD::SETEQ: CmpMode = 0x04; break;
14315 case ISD::SETNE: CmpMode = 0x05; break;
14318 // Are we comparing unsigned or signed integers?
14319 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14320 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14322 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14323 DAG.getConstant(CmpMode, dl, MVT::i8));
14326 // We are handling one of the integer comparisons here. Since SSE only has
14327 // GT and EQ comparisons for integer, swapping operands and multiple
14328 // operations may be required for some comparisons.
14330 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14331 bool Subus = false;
14333 switch (SetCCOpcode) {
14334 default: llvm_unreachable("Unexpected SETCC condition");
14335 case ISD::SETNE: Invert = true;
14336 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14337 case ISD::SETLT: Swap = true;
14338 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14339 case ISD::SETGE: Swap = true;
14340 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14341 Invert = true; break;
14342 case ISD::SETULT: Swap = true;
14343 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14344 FlipSigns = true; break;
14345 case ISD::SETUGE: Swap = true;
14346 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14347 FlipSigns = true; Invert = true; break;
14350 // Special case: Use min/max operations for SETULE/SETUGE
14351 MVT VET = VT.getVectorElementType();
14353 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14354 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14357 switch (SetCCOpcode) {
14359 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14360 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14363 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14366 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14367 if (!MinMax && hasSubus) {
14368 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14370 // t = psubus Op0, Op1
14371 // pcmpeq t, <0..0>
14372 switch (SetCCOpcode) {
14374 case ISD::SETULT: {
14375 // If the comparison is against a constant we can turn this into a
14376 // setule. With psubus, setule does not require a swap. This is
14377 // beneficial because the constant in the register is no longer
14378 // destructed as the destination so it can be hoisted out of a loop.
14379 // Only do this pre-AVX since vpcmp* is no longer destructive.
14380 if (Subtarget->hasAVX())
14382 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14383 if (ULEOp1.getNode()) {
14385 Subus = true; Invert = false; Swap = false;
14389 // Psubus is better than flip-sign because it requires no inversion.
14390 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14391 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14395 Opc = X86ISD::SUBUS;
14401 std::swap(Op0, Op1);
14403 // Check that the operation in question is available (most are plain SSE2,
14404 // but PCMPGTQ and PCMPEQQ have different requirements).
14405 if (VT == MVT::v2i64) {
14406 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14407 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14409 // First cast everything to the right type.
14410 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14411 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14413 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14414 // bits of the inputs before performing those operations. The lower
14415 // compare is always unsigned.
14418 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14420 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14421 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14422 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14423 Sign, Zero, Sign, Zero);
14425 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14426 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14428 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14429 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14430 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14432 // Create masks for only the low parts/high parts of the 64 bit integers.
14433 static const int MaskHi[] = { 1, 1, 3, 3 };
14434 static const int MaskLo[] = { 0, 0, 2, 2 };
14435 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14436 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14437 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14439 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14440 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14443 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14445 return DAG.getBitcast(VT, Result);
14448 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14449 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14450 // pcmpeqd + pshufd + pand.
14451 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14453 // First cast everything to the right type.
14454 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14455 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14458 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14460 // Make sure the lower and upper halves are both all-ones.
14461 static const int Mask[] = { 1, 0, 3, 2 };
14462 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14463 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14466 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14468 return DAG.getBitcast(VT, Result);
14472 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14473 // bits of the inputs before performing those operations.
14475 MVT EltVT = VT.getVectorElementType();
14476 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14478 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14479 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14482 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14484 // If the logical-not of the result is required, perform that now.
14486 Result = DAG.getNOT(dl, Result, VT);
14489 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14492 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14493 getZeroVector(VT, Subtarget, DAG, dl));
14498 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14500 MVT VT = Op.getSimpleValueType();
14502 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14504 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14505 && "SetCC type must be 8-bit or 1-bit integer");
14506 SDValue Op0 = Op.getOperand(0);
14507 SDValue Op1 = Op.getOperand(1);
14509 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14511 // Optimize to BT if possible.
14512 // Lower (X & (1 << N)) == 0 to BT(X, N).
14513 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14514 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14515 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14516 Op1.getOpcode() == ISD::Constant &&
14517 cast<ConstantSDNode>(Op1)->isNullValue() &&
14518 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14519 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14520 if (NewSetCC.getNode()) {
14522 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14527 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14529 if (Op1.getOpcode() == ISD::Constant &&
14530 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14531 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14532 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14534 // If the input is a setcc, then reuse the input setcc or use a new one with
14535 // the inverted condition.
14536 if (Op0.getOpcode() == X86ISD::SETCC) {
14537 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14538 bool Invert = (CC == ISD::SETNE) ^
14539 cast<ConstantSDNode>(Op1)->isNullValue();
14543 CCode = X86::GetOppositeBranchCondition(CCode);
14544 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14545 DAG.getConstant(CCode, dl, MVT::i8),
14546 Op0.getOperand(1));
14548 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14552 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14553 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14554 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14556 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14557 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14560 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14561 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14562 if (X86CC == X86::COND_INVALID)
14565 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14566 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14567 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14568 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14570 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14574 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14575 static bool isX86LogicalCmp(SDValue Op) {
14576 unsigned Opc = Op.getNode()->getOpcode();
14577 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14578 Opc == X86ISD::SAHF)
14580 if (Op.getResNo() == 1 &&
14581 (Opc == X86ISD::ADD ||
14582 Opc == X86ISD::SUB ||
14583 Opc == X86ISD::ADC ||
14584 Opc == X86ISD::SBB ||
14585 Opc == X86ISD::SMUL ||
14586 Opc == X86ISD::UMUL ||
14587 Opc == X86ISD::INC ||
14588 Opc == X86ISD::DEC ||
14589 Opc == X86ISD::OR ||
14590 Opc == X86ISD::XOR ||
14591 Opc == X86ISD::AND))
14594 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14600 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14601 if (V.getOpcode() != ISD::TRUNCATE)
14604 SDValue VOp0 = V.getOperand(0);
14605 unsigned InBits = VOp0.getValueSizeInBits();
14606 unsigned Bits = V.getValueSizeInBits();
14607 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14610 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14611 bool addTest = true;
14612 SDValue Cond = Op.getOperand(0);
14613 SDValue Op1 = Op.getOperand(1);
14614 SDValue Op2 = Op.getOperand(2);
14616 MVT VT = Op1.getSimpleValueType();
14619 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14620 // are available or VBLENDV if AVX is available.
14621 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14622 if (Cond.getOpcode() == ISD::SETCC &&
14623 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14624 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14625 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14626 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14627 int SSECC = translateX86FSETCC(
14628 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14631 if (Subtarget->hasAVX512()) {
14632 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14633 DAG.getConstant(SSECC, DL, MVT::i8));
14634 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14637 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14638 DAG.getConstant(SSECC, DL, MVT::i8));
14640 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14641 // of 3 logic instructions for size savings and potentially speed.
14642 // Unfortunately, there is no scalar form of VBLENDV.
14644 // If either operand is a constant, don't try this. We can expect to
14645 // optimize away at least one of the logic instructions later in that
14646 // case, so that sequence would be faster than a variable blend.
14648 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14649 // uses XMM0 as the selection register. That may need just as many
14650 // instructions as the AND/ANDN/OR sequence due to register moves, so
14653 if (Subtarget->hasAVX() &&
14654 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14656 // Convert to vectors, do a VSELECT, and convert back to scalar.
14657 // All of the conversions should be optimized away.
14659 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14660 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14661 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14662 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14664 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14665 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14667 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14669 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14670 VSel, DAG.getIntPtrConstant(0, DL));
14672 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14673 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14674 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14678 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14680 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14681 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14682 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14683 Op1Scalar = Op1.getOperand(0);
14685 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14686 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14687 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14688 Op2Scalar = Op2.getOperand(0);
14689 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14690 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14691 Op1Scalar.getValueType(),
14692 Cond, Op1Scalar, Op2Scalar);
14693 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14694 return DAG.getBitcast(VT, newSelect);
14695 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14696 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14697 DAG.getIntPtrConstant(0, DL));
14701 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14702 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14703 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14704 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14705 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14706 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14707 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14709 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14712 if (Cond.getOpcode() == ISD::SETCC) {
14713 SDValue NewCond = LowerSETCC(Cond, DAG);
14714 if (NewCond.getNode())
14718 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14719 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14720 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14721 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14722 if (Cond.getOpcode() == X86ISD::SETCC &&
14723 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14724 isZero(Cond.getOperand(1).getOperand(1))) {
14725 SDValue Cmp = Cond.getOperand(1);
14727 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14729 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14730 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14731 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14733 SDValue CmpOp0 = Cmp.getOperand(0);
14734 // Apply further optimizations for special cases
14735 // (select (x != 0), -1, 0) -> neg & sbb
14736 // (select (x == 0), 0, -1) -> neg & sbb
14737 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14738 if (YC->isNullValue() &&
14739 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14740 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14741 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14742 DAG.getConstant(0, DL,
14743 CmpOp0.getValueType()),
14745 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14746 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14747 SDValue(Neg.getNode(), 1));
14751 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14752 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14753 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14755 SDValue Res = // Res = 0 or -1.
14756 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14757 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14759 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14760 Res = DAG.getNOT(DL, Res, Res.getValueType());
14762 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14763 if (!N2C || !N2C->isNullValue())
14764 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14769 // Look past (and (setcc_carry (cmp ...)), 1).
14770 if (Cond.getOpcode() == ISD::AND &&
14771 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14772 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14773 if (C && C->getAPIntValue() == 1)
14774 Cond = Cond.getOperand(0);
14777 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14778 // setting operand in place of the X86ISD::SETCC.
14779 unsigned CondOpcode = Cond.getOpcode();
14780 if (CondOpcode == X86ISD::SETCC ||
14781 CondOpcode == X86ISD::SETCC_CARRY) {
14782 CC = Cond.getOperand(0);
14784 SDValue Cmp = Cond.getOperand(1);
14785 unsigned Opc = Cmp.getOpcode();
14786 MVT VT = Op.getSimpleValueType();
14788 bool IllegalFPCMov = false;
14789 if (VT.isFloatingPoint() && !VT.isVector() &&
14790 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14791 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14793 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14794 Opc == X86ISD::BT) { // FIXME
14798 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14799 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14800 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14801 Cond.getOperand(0).getValueType() != MVT::i8)) {
14802 SDValue LHS = Cond.getOperand(0);
14803 SDValue RHS = Cond.getOperand(1);
14804 unsigned X86Opcode;
14807 switch (CondOpcode) {
14808 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14809 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14810 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14811 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14812 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14813 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14814 default: llvm_unreachable("unexpected overflowing operator");
14816 if (CondOpcode == ISD::UMULO)
14817 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14820 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14822 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14824 if (CondOpcode == ISD::UMULO)
14825 Cond = X86Op.getValue(2);
14827 Cond = X86Op.getValue(1);
14829 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14834 // Look past the truncate if the high bits are known zero.
14835 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14836 Cond = Cond.getOperand(0);
14838 // We know the result of AND is compared against zero. Try to match
14840 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14841 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14842 if (NewSetCC.getNode()) {
14843 CC = NewSetCC.getOperand(0);
14844 Cond = NewSetCC.getOperand(1);
14851 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14852 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14855 // a < b ? -1 : 0 -> RES = ~setcc_carry
14856 // a < b ? 0 : -1 -> RES = setcc_carry
14857 // a >= b ? -1 : 0 -> RES = setcc_carry
14858 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14859 if (Cond.getOpcode() == X86ISD::SUB) {
14860 Cond = ConvertCmpIfNecessary(Cond, DAG);
14861 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14863 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14864 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14865 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14866 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14868 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14869 return DAG.getNOT(DL, Res, Res.getValueType());
14874 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14875 // widen the cmov and push the truncate through. This avoids introducing a new
14876 // branch during isel and doesn't add any extensions.
14877 if (Op.getValueType() == MVT::i8 &&
14878 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14879 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14880 if (T1.getValueType() == T2.getValueType() &&
14881 // Blacklist CopyFromReg to avoid partial register stalls.
14882 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14883 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14884 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14885 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14889 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14890 // condition is true.
14891 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14892 SDValue Ops[] = { Op2, Op1, CC, Cond };
14893 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14896 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14897 const X86Subtarget *Subtarget,
14898 SelectionDAG &DAG) {
14899 MVT VT = Op->getSimpleValueType(0);
14900 SDValue In = Op->getOperand(0);
14901 MVT InVT = In.getSimpleValueType();
14902 MVT VTElt = VT.getVectorElementType();
14903 MVT InVTElt = InVT.getVectorElementType();
14907 if ((InVTElt == MVT::i1) &&
14908 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14909 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14911 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14912 VTElt.getSizeInBits() <= 16)) ||
14914 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14915 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14917 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14918 VTElt.getSizeInBits() >= 32))))
14919 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14921 unsigned int NumElts = VT.getVectorNumElements();
14923 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14926 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14927 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14928 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14929 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14932 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14933 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14935 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14938 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14940 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14941 if (VT.is512BitVector())
14943 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14946 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14947 const X86Subtarget *Subtarget,
14948 SelectionDAG &DAG) {
14949 SDValue In = Op->getOperand(0);
14950 MVT VT = Op->getSimpleValueType(0);
14951 MVT InVT = In.getSimpleValueType();
14952 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14954 MVT InSVT = InVT.getVectorElementType();
14955 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
14957 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14959 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14964 // SSE41 targets can use the pmovsx* instructions directly.
14965 if (Subtarget->hasSSE41())
14966 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14968 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14972 // As SRAI is only available on i16/i32 types, we expand only up to i32
14973 // and handle i64 separately.
14974 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
14975 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14976 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14977 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14978 Curr = DAG.getBitcast(CurrVT, Curr);
14981 SDValue SignExt = Curr;
14982 if (CurrVT != InVT) {
14983 unsigned SignExtShift =
14984 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
14985 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14986 DAG.getConstant(SignExtShift, dl, MVT::i8));
14992 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14993 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14994 DAG.getConstant(31, dl, MVT::i8));
14995 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14996 return DAG.getBitcast(VT, Ext);
15002 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15003 SelectionDAG &DAG) {
15004 MVT VT = Op->getSimpleValueType(0);
15005 SDValue In = Op->getOperand(0);
15006 MVT InVT = In.getSimpleValueType();
15009 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15010 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15012 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15013 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15014 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15017 if (Subtarget->hasInt256())
15018 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15020 // Optimize vectors in AVX mode
15021 // Sign extend v8i16 to v8i32 and
15024 // Divide input vector into two parts
15025 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15026 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15027 // concat the vectors to original VT
15029 unsigned NumElems = InVT.getVectorNumElements();
15030 SDValue Undef = DAG.getUNDEF(InVT);
15032 SmallVector<int,8> ShufMask1(NumElems, -1);
15033 for (unsigned i = 0; i != NumElems/2; ++i)
15036 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15038 SmallVector<int,8> ShufMask2(NumElems, -1);
15039 for (unsigned i = 0; i != NumElems/2; ++i)
15040 ShufMask2[i] = i + NumElems/2;
15042 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15044 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15045 VT.getVectorNumElements()/2);
15047 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15048 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15050 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15053 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15054 // may emit an illegal shuffle but the expansion is still better than scalar
15055 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15056 // we'll emit a shuffle and a arithmetic shift.
15057 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15058 // TODO: It is possible to support ZExt by zeroing the undef values during
15059 // the shuffle phase or after the shuffle.
15060 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15061 SelectionDAG &DAG) {
15062 MVT RegVT = Op.getSimpleValueType();
15063 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15064 assert(RegVT.isInteger() &&
15065 "We only custom lower integer vector sext loads.");
15067 // Nothing useful we can do without SSE2 shuffles.
15068 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15070 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15072 EVT MemVT = Ld->getMemoryVT();
15073 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15074 unsigned RegSz = RegVT.getSizeInBits();
15076 ISD::LoadExtType Ext = Ld->getExtensionType();
15078 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15079 && "Only anyext and sext are currently implemented.");
15080 assert(MemVT != RegVT && "Cannot extend to the same type");
15081 assert(MemVT.isVector() && "Must load a vector from memory");
15083 unsigned NumElems = RegVT.getVectorNumElements();
15084 unsigned MemSz = MemVT.getSizeInBits();
15085 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15087 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15088 // The only way in which we have a legal 256-bit vector result but not the
15089 // integer 256-bit operations needed to directly lower a sextload is if we
15090 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15091 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15092 // correctly legalized. We do this late to allow the canonical form of
15093 // sextload to persist throughout the rest of the DAG combiner -- it wants
15094 // to fold together any extensions it can, and so will fuse a sign_extend
15095 // of an sextload into a sextload targeting a wider value.
15097 if (MemSz == 128) {
15098 // Just switch this to a normal load.
15099 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15100 "it must be a legal 128-bit vector "
15102 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15103 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15104 Ld->isInvariant(), Ld->getAlignment());
15106 assert(MemSz < 128 &&
15107 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15108 // Do an sext load to a 128-bit vector type. We want to use the same
15109 // number of elements, but elements half as wide. This will end up being
15110 // recursively lowered by this routine, but will succeed as we definitely
15111 // have all the necessary features if we're using AVX1.
15113 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15114 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15116 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15117 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15118 Ld->isNonTemporal(), Ld->isInvariant(),
15119 Ld->getAlignment());
15122 // Replace chain users with the new chain.
15123 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15124 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15126 // Finally, do a normal sign-extend to the desired register.
15127 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15130 // All sizes must be a power of two.
15131 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15132 "Non-power-of-two elements are not custom lowered!");
15134 // Attempt to load the original value using scalar loads.
15135 // Find the largest scalar type that divides the total loaded size.
15136 MVT SclrLoadTy = MVT::i8;
15137 for (MVT Tp : MVT::integer_valuetypes()) {
15138 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15143 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15144 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15146 SclrLoadTy = MVT::f64;
15148 // Calculate the number of scalar loads that we need to perform
15149 // in order to load our vector from memory.
15150 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15152 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15153 "Can only lower sext loads with a single scalar load!");
15155 unsigned loadRegZize = RegSz;
15156 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15159 // Represent our vector as a sequence of elements which are the
15160 // largest scalar that we can load.
15161 EVT LoadUnitVecVT = EVT::getVectorVT(
15162 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15164 // Represent the data using the same element type that is stored in
15165 // memory. In practice, we ''widen'' MemVT.
15167 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15168 loadRegZize / MemVT.getScalarSizeInBits());
15170 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15171 "Invalid vector type");
15173 // We can't shuffle using an illegal type.
15174 assert(TLI.isTypeLegal(WideVecVT) &&
15175 "We only lower types that form legal widened vector types");
15177 SmallVector<SDValue, 8> Chains;
15178 SDValue Ptr = Ld->getBasePtr();
15179 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15180 TLI.getPointerTy(DAG.getDataLayout()));
15181 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15183 for (unsigned i = 0; i < NumLoads; ++i) {
15184 // Perform a single load.
15185 SDValue ScalarLoad =
15186 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15187 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15188 Ld->getAlignment());
15189 Chains.push_back(ScalarLoad.getValue(1));
15190 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15191 // another round of DAGCombining.
15193 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15195 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15196 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15198 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15201 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15203 // Bitcast the loaded value to a vector of the original element type, in
15204 // the size of the target vector type.
15205 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15206 unsigned SizeRatio = RegSz / MemSz;
15208 if (Ext == ISD::SEXTLOAD) {
15209 // If we have SSE4.1, we can directly emit a VSEXT node.
15210 if (Subtarget->hasSSE41()) {
15211 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15212 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15216 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15218 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15219 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15221 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15222 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15226 // Redistribute the loaded elements into the different locations.
15227 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15228 for (unsigned i = 0; i != NumElems; ++i)
15229 ShuffleVec[i * SizeRatio] = i;
15231 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15232 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15234 // Bitcast to the requested type.
15235 Shuff = DAG.getBitcast(RegVT, Shuff);
15236 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15240 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15241 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15242 // from the AND / OR.
15243 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15244 Opc = Op.getOpcode();
15245 if (Opc != ISD::OR && Opc != ISD::AND)
15247 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15248 Op.getOperand(0).hasOneUse() &&
15249 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15250 Op.getOperand(1).hasOneUse());
15253 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15254 // 1 and that the SETCC node has a single use.
15255 static bool isXor1OfSetCC(SDValue Op) {
15256 if (Op.getOpcode() != ISD::XOR)
15258 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15259 if (N1C && N1C->getAPIntValue() == 1) {
15260 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15261 Op.getOperand(0).hasOneUse();
15266 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15267 bool addTest = true;
15268 SDValue Chain = Op.getOperand(0);
15269 SDValue Cond = Op.getOperand(1);
15270 SDValue Dest = Op.getOperand(2);
15273 bool Inverted = false;
15275 if (Cond.getOpcode() == ISD::SETCC) {
15276 // Check for setcc([su]{add,sub,mul}o == 0).
15277 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15278 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15279 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15280 Cond.getOperand(0).getResNo() == 1 &&
15281 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15282 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15283 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15284 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15285 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15286 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15288 Cond = Cond.getOperand(0);
15290 SDValue NewCond = LowerSETCC(Cond, DAG);
15291 if (NewCond.getNode())
15296 // FIXME: LowerXALUO doesn't handle these!!
15297 else if (Cond.getOpcode() == X86ISD::ADD ||
15298 Cond.getOpcode() == X86ISD::SUB ||
15299 Cond.getOpcode() == X86ISD::SMUL ||
15300 Cond.getOpcode() == X86ISD::UMUL)
15301 Cond = LowerXALUO(Cond, DAG);
15304 // Look pass (and (setcc_carry (cmp ...)), 1).
15305 if (Cond.getOpcode() == ISD::AND &&
15306 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15307 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15308 if (C && C->getAPIntValue() == 1)
15309 Cond = Cond.getOperand(0);
15312 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15313 // setting operand in place of the X86ISD::SETCC.
15314 unsigned CondOpcode = Cond.getOpcode();
15315 if (CondOpcode == X86ISD::SETCC ||
15316 CondOpcode == X86ISD::SETCC_CARRY) {
15317 CC = Cond.getOperand(0);
15319 SDValue Cmp = Cond.getOperand(1);
15320 unsigned Opc = Cmp.getOpcode();
15321 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15322 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15326 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15330 // These can only come from an arithmetic instruction with overflow,
15331 // e.g. SADDO, UADDO.
15332 Cond = Cond.getNode()->getOperand(1);
15338 CondOpcode = Cond.getOpcode();
15339 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15340 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15341 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15342 Cond.getOperand(0).getValueType() != MVT::i8)) {
15343 SDValue LHS = Cond.getOperand(0);
15344 SDValue RHS = Cond.getOperand(1);
15345 unsigned X86Opcode;
15348 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15349 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15351 switch (CondOpcode) {
15352 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15356 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15359 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15360 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15364 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15367 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15368 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15369 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15370 default: llvm_unreachable("unexpected overflowing operator");
15373 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15374 if (CondOpcode == ISD::UMULO)
15375 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15378 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15380 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15382 if (CondOpcode == ISD::UMULO)
15383 Cond = X86Op.getValue(2);
15385 Cond = X86Op.getValue(1);
15387 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15391 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15392 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15393 if (CondOpc == ISD::OR) {
15394 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15395 // two branches instead of an explicit OR instruction with a
15397 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15398 isX86LogicalCmp(Cmp)) {
15399 CC = Cond.getOperand(0).getOperand(0);
15400 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15401 Chain, Dest, CC, Cmp);
15402 CC = Cond.getOperand(1).getOperand(0);
15406 } else { // ISD::AND
15407 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15408 // two branches instead of an explicit AND instruction with a
15409 // separate test. However, we only do this if this block doesn't
15410 // have a fall-through edge, because this requires an explicit
15411 // jmp when the condition is false.
15412 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15413 isX86LogicalCmp(Cmp) &&
15414 Op.getNode()->hasOneUse()) {
15415 X86::CondCode CCode =
15416 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15417 CCode = X86::GetOppositeBranchCondition(CCode);
15418 CC = DAG.getConstant(CCode, dl, MVT::i8);
15419 SDNode *User = *Op.getNode()->use_begin();
15420 // Look for an unconditional branch following this conditional branch.
15421 // We need this because we need to reverse the successors in order
15422 // to implement FCMP_OEQ.
15423 if (User->getOpcode() == ISD::BR) {
15424 SDValue FalseBB = User->getOperand(1);
15426 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15427 assert(NewBR == User);
15431 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15432 Chain, Dest, CC, Cmp);
15433 X86::CondCode CCode =
15434 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15435 CCode = X86::GetOppositeBranchCondition(CCode);
15436 CC = DAG.getConstant(CCode, dl, MVT::i8);
15442 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15443 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15444 // It should be transformed during dag combiner except when the condition
15445 // is set by a arithmetics with overflow node.
15446 X86::CondCode CCode =
15447 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15448 CCode = X86::GetOppositeBranchCondition(CCode);
15449 CC = DAG.getConstant(CCode, dl, MVT::i8);
15450 Cond = Cond.getOperand(0).getOperand(1);
15452 } else if (Cond.getOpcode() == ISD::SETCC &&
15453 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15454 // For FCMP_OEQ, we can emit
15455 // two branches instead of an explicit AND instruction with a
15456 // separate test. However, we only do this if this block doesn't
15457 // have a fall-through edge, because this requires an explicit
15458 // jmp when the condition is false.
15459 if (Op.getNode()->hasOneUse()) {
15460 SDNode *User = *Op.getNode()->use_begin();
15461 // Look for an unconditional branch following this conditional branch.
15462 // We need this because we need to reverse the successors in order
15463 // to implement FCMP_OEQ.
15464 if (User->getOpcode() == ISD::BR) {
15465 SDValue FalseBB = User->getOperand(1);
15467 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15468 assert(NewBR == User);
15472 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15473 Cond.getOperand(0), Cond.getOperand(1));
15474 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15475 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15476 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15477 Chain, Dest, CC, Cmp);
15478 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15483 } else if (Cond.getOpcode() == ISD::SETCC &&
15484 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15485 // For FCMP_UNE, we can emit
15486 // two branches instead of an explicit AND instruction with a
15487 // separate test. However, we only do this if this block doesn't
15488 // have a fall-through edge, because this requires an explicit
15489 // jmp when the condition is false.
15490 if (Op.getNode()->hasOneUse()) {
15491 SDNode *User = *Op.getNode()->use_begin();
15492 // Look for an unconditional branch following this conditional branch.
15493 // We need this because we need to reverse the successors in order
15494 // to implement FCMP_UNE.
15495 if (User->getOpcode() == ISD::BR) {
15496 SDValue FalseBB = User->getOperand(1);
15498 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15499 assert(NewBR == User);
15502 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15503 Cond.getOperand(0), Cond.getOperand(1));
15504 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15505 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15506 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15507 Chain, Dest, CC, Cmp);
15508 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15518 // Look pass the truncate if the high bits are known zero.
15519 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15520 Cond = Cond.getOperand(0);
15522 // We know the result of AND is compared against zero. Try to match
15524 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15525 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15526 if (NewSetCC.getNode()) {
15527 CC = NewSetCC.getOperand(0);
15528 Cond = NewSetCC.getOperand(1);
15535 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15536 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15537 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15539 Cond = ConvertCmpIfNecessary(Cond, DAG);
15540 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15541 Chain, Dest, CC, Cond);
15544 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15545 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15546 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15547 // that the guard pages used by the OS virtual memory manager are allocated in
15548 // correct sequence.
15550 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15551 SelectionDAG &DAG) const {
15552 MachineFunction &MF = DAG.getMachineFunction();
15553 bool SplitStack = MF.shouldSplitStack();
15554 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15560 SDNode* Node = Op.getNode();
15562 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15563 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15564 " not tell us which reg is the stack pointer!");
15565 EVT VT = Node->getValueType(0);
15566 SDValue Tmp1 = SDValue(Node, 0);
15567 SDValue Tmp2 = SDValue(Node, 1);
15568 SDValue Tmp3 = Node->getOperand(2);
15569 SDValue Chain = Tmp1.getOperand(0);
15571 // Chain the dynamic stack allocation so that it doesn't modify the stack
15572 // pointer when other instructions are using the stack.
15573 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15576 SDValue Size = Tmp2.getOperand(1);
15577 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15578 Chain = SP.getValue(1);
15579 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15580 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15581 unsigned StackAlign = TFI.getStackAlignment();
15582 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15583 if (Align > StackAlign)
15584 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15585 DAG.getConstant(-(uint64_t)Align, dl, VT));
15586 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15588 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15589 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15592 SDValue Ops[2] = { Tmp1, Tmp2 };
15593 return DAG.getMergeValues(Ops, dl);
15597 SDValue Chain = Op.getOperand(0);
15598 SDValue Size = Op.getOperand(1);
15599 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15600 EVT VT = Op.getNode()->getValueType(0);
15602 bool Is64Bit = Subtarget->is64Bit();
15603 MVT SPTy = getPointerTy(DAG.getDataLayout());
15606 MachineRegisterInfo &MRI = MF.getRegInfo();
15609 // The 64 bit implementation of segmented stacks needs to clobber both r10
15610 // r11. This makes it impossible to use it along with nested parameters.
15611 const Function *F = MF.getFunction();
15613 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15615 if (I->hasNestAttr())
15616 report_fatal_error("Cannot use segmented stacks with functions that "
15617 "have nested arguments.");
15620 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15621 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15622 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15623 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15624 DAG.getRegister(Vreg, SPTy));
15625 SDValue Ops1[2] = { Value, Chain };
15626 return DAG.getMergeValues(Ops1, dl);
15629 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15631 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15632 Flag = Chain.getValue(1);
15633 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15635 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15637 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15638 unsigned SPReg = RegInfo->getStackRegister();
15639 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15640 Chain = SP.getValue(1);
15643 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15644 DAG.getConstant(-(uint64_t)Align, dl, VT));
15645 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15648 SDValue Ops1[2] = { SP, Chain };
15649 return DAG.getMergeValues(Ops1, dl);
15653 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15654 MachineFunction &MF = DAG.getMachineFunction();
15655 auto PtrVT = getPointerTy(MF.getDataLayout());
15656 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15658 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15661 if (!Subtarget->is64Bit() ||
15662 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15663 // vastart just stores the address of the VarArgsFrameIndex slot into the
15664 // memory location argument.
15665 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15666 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15667 MachinePointerInfo(SV), false, false, 0);
15671 // gp_offset (0 - 6 * 8)
15672 // fp_offset (48 - 48 + 8 * 16)
15673 // overflow_arg_area (point to parameters coming in memory).
15675 SmallVector<SDValue, 8> MemOps;
15676 SDValue FIN = Op.getOperand(1);
15678 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15679 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15681 FIN, MachinePointerInfo(SV), false, false, 0);
15682 MemOps.push_back(Store);
15685 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15686 Store = DAG.getStore(Op.getOperand(0), DL,
15687 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15689 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15690 MemOps.push_back(Store);
15692 // Store ptr to overflow_arg_area
15693 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15694 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15695 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15696 MachinePointerInfo(SV, 8),
15698 MemOps.push_back(Store);
15700 // Store ptr to reg_save_area.
15701 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15702 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15703 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15704 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15705 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15706 MemOps.push_back(Store);
15707 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15710 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15711 assert(Subtarget->is64Bit() &&
15712 "LowerVAARG only handles 64-bit va_arg!");
15713 assert(Op.getNode()->getNumOperands() == 4);
15715 MachineFunction &MF = DAG.getMachineFunction();
15716 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15717 // The Win64 ABI uses char* instead of a structure.
15718 return DAG.expandVAArg(Op.getNode());
15720 SDValue Chain = Op.getOperand(0);
15721 SDValue SrcPtr = Op.getOperand(1);
15722 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15723 unsigned Align = Op.getConstantOperandVal(3);
15726 EVT ArgVT = Op.getNode()->getValueType(0);
15727 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15728 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15731 // Decide which area this value should be read from.
15732 // TODO: Implement the AMD64 ABI in its entirety. This simple
15733 // selection mechanism works only for the basic types.
15734 if (ArgVT == MVT::f80) {
15735 llvm_unreachable("va_arg for f80 not yet implemented");
15736 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15737 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15738 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15739 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15741 llvm_unreachable("Unhandled argument type in LowerVAARG");
15744 if (ArgMode == 2) {
15745 // Sanity Check: Make sure using fp_offset makes sense.
15746 assert(!Subtarget->useSoftFloat() &&
15747 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15748 Subtarget->hasSSE1());
15751 // Insert VAARG_64 node into the DAG
15752 // VAARG_64 returns two values: Variable Argument Address, Chain
15753 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15754 DAG.getConstant(ArgMode, dl, MVT::i8),
15755 DAG.getConstant(Align, dl, MVT::i32)};
15756 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15757 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15758 VTs, InstOps, MVT::i64,
15759 MachinePointerInfo(SV),
15761 /*Volatile=*/false,
15763 /*WriteMem=*/true);
15764 Chain = VAARG.getValue(1);
15766 // Load the next argument and return it
15767 return DAG.getLoad(ArgVT, dl,
15770 MachinePointerInfo(),
15771 false, false, false, 0);
15774 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15775 SelectionDAG &DAG) {
15776 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15777 // where a va_list is still an i8*.
15778 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15779 if (Subtarget->isCallingConvWin64(
15780 DAG.getMachineFunction().getFunction()->getCallingConv()))
15781 // Probably a Win64 va_copy.
15782 return DAG.expandVACopy(Op.getNode());
15784 SDValue Chain = Op.getOperand(0);
15785 SDValue DstPtr = Op.getOperand(1);
15786 SDValue SrcPtr = Op.getOperand(2);
15787 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15788 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15791 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15792 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15794 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15797 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15798 // amount is a constant. Takes immediate version of shift as input.
15799 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15800 SDValue SrcOp, uint64_t ShiftAmt,
15801 SelectionDAG &DAG) {
15802 MVT ElementType = VT.getVectorElementType();
15804 // Fold this packed shift into its first operand if ShiftAmt is 0.
15808 // Check for ShiftAmt >= element width
15809 if (ShiftAmt >= ElementType.getSizeInBits()) {
15810 if (Opc == X86ISD::VSRAI)
15811 ShiftAmt = ElementType.getSizeInBits() - 1;
15813 return DAG.getConstant(0, dl, VT);
15816 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15817 && "Unknown target vector shift-by-constant node");
15819 // Fold this packed vector shift into a build vector if SrcOp is a
15820 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15821 if (VT == SrcOp.getSimpleValueType() &&
15822 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15823 SmallVector<SDValue, 8> Elts;
15824 unsigned NumElts = SrcOp->getNumOperands();
15825 ConstantSDNode *ND;
15828 default: llvm_unreachable(nullptr);
15829 case X86ISD::VSHLI:
15830 for (unsigned i=0; i!=NumElts; ++i) {
15831 SDValue CurrentOp = SrcOp->getOperand(i);
15832 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15833 Elts.push_back(CurrentOp);
15836 ND = cast<ConstantSDNode>(CurrentOp);
15837 const APInt &C = ND->getAPIntValue();
15838 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15841 case X86ISD::VSRLI:
15842 for (unsigned i=0; i!=NumElts; ++i) {
15843 SDValue CurrentOp = SrcOp->getOperand(i);
15844 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15845 Elts.push_back(CurrentOp);
15848 ND = cast<ConstantSDNode>(CurrentOp);
15849 const APInt &C = ND->getAPIntValue();
15850 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15853 case X86ISD::VSRAI:
15854 for (unsigned i=0; i!=NumElts; ++i) {
15855 SDValue CurrentOp = SrcOp->getOperand(i);
15856 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15857 Elts.push_back(CurrentOp);
15860 ND = cast<ConstantSDNode>(CurrentOp);
15861 const APInt &C = ND->getAPIntValue();
15862 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15867 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15870 return DAG.getNode(Opc, dl, VT, SrcOp,
15871 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15874 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15875 // may or may not be a constant. Takes immediate version of shift as input.
15876 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15877 SDValue SrcOp, SDValue ShAmt,
15878 SelectionDAG &DAG) {
15879 MVT SVT = ShAmt.getSimpleValueType();
15880 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15882 // Catch shift-by-constant.
15883 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15884 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15885 CShAmt->getZExtValue(), DAG);
15887 // Change opcode to non-immediate version
15889 default: llvm_unreachable("Unknown target vector shift node");
15890 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15891 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15892 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15895 const X86Subtarget &Subtarget =
15896 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15897 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15898 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15899 // Let the shuffle legalizer expand this shift amount node.
15900 SDValue Op0 = ShAmt.getOperand(0);
15901 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15902 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15904 // Need to build a vector containing shift amount.
15905 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15906 SmallVector<SDValue, 4> ShOps;
15907 ShOps.push_back(ShAmt);
15908 if (SVT == MVT::i32) {
15909 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15910 ShOps.push_back(DAG.getUNDEF(SVT));
15912 ShOps.push_back(DAG.getUNDEF(SVT));
15914 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15915 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15918 // The return type has to be a 128-bit type with the same element
15919 // type as the input type.
15920 MVT EltVT = VT.getVectorElementType();
15921 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15923 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15924 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15927 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15928 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15929 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15930 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15931 SDValue PreservedSrc,
15932 const X86Subtarget *Subtarget,
15933 SelectionDAG &DAG) {
15934 MVT VT = Op.getSimpleValueType();
15935 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
15937 unsigned OpcodeSelect = ISD::VSELECT;
15940 if (isAllOnes(Mask))
15943 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
15944 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
15945 VMask = DAG.getBitcast(MaskVT,
15946 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15948 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
15949 Mask.getSimpleValueType().getSizeInBits());
15950 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15951 // are extracted by EXTRACT_SUBVECTOR.
15952 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15953 DAG.getBitcast(BitcastVT, Mask),
15954 DAG.getIntPtrConstant(0, dl));
15957 switch (Op.getOpcode()) {
15959 case X86ISD::PCMPEQM:
15960 case X86ISD::PCMPGTM:
15962 case X86ISD::CMPMU:
15963 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15964 case X86ISD::VFPCLASS:
15965 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15966 case X86ISD::VTRUNC:
15967 case X86ISD::VTRUNCS:
15968 case X86ISD::VTRUNCUS:
15969 // We can't use ISD::VSELECT here because it is not always "Legal"
15970 // for the destination type. For example vpmovqb require only AVX512
15971 // and vselect that can operate on byte element type require BWI
15972 OpcodeSelect = X86ISD::SELECT;
15975 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15976 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15977 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15980 /// \brief Creates an SDNode for a predicated scalar operation.
15981 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15982 /// The mask is coming as MVT::i8 and it should be truncated
15983 /// to MVT::i1 while lowering masking intrinsics.
15984 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15985 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15986 /// for a scalar instruction.
15987 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15988 SDValue PreservedSrc,
15989 const X86Subtarget *Subtarget,
15990 SelectionDAG &DAG) {
15991 if (isAllOnes(Mask))
15994 MVT VT = Op.getSimpleValueType();
15996 // The mask should be of type MVT::i1
15997 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15999 if (Op.getOpcode() == X86ISD::FSETCC)
16000 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16001 if (Op.getOpcode() == X86ISD::VFPCLASS)
16002 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16004 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16005 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16006 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16009 static int getSEHRegistrationNodeSize(const Function *Fn) {
16010 if (!Fn->hasPersonalityFn())
16011 report_fatal_error(
16012 "querying registration node size for function without personality");
16013 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16014 // WinEHStatePass for the full struct definition.
16015 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16016 case EHPersonality::MSVC_X86SEH: return 24;
16017 case EHPersonality::MSVC_CXX: return 16;
16020 report_fatal_error("can only recover FP for MSVC EH personality functions");
16023 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16024 /// function or when returning to a parent frame after catching an exception, we
16025 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16026 /// Here's the math:
16027 /// RegNodeBase = EntryEBP - RegNodeSize
16028 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16029 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16030 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16031 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16032 SDValue EntryEBP) {
16033 MachineFunction &MF = DAG.getMachineFunction();
16036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16037 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16039 // It's possible that the parent function no longer has a personality function
16040 // if the exceptional code was optimized away, in which case we just return
16041 // the incoming EBP.
16042 if (!Fn->hasPersonalityFn())
16045 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16047 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16049 MCSymbol *OffsetSym =
16050 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16051 GlobalValue::getRealLinkageName(Fn->getName()));
16052 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16053 SDValue RegNodeFrameOffset =
16054 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16056 // RegNodeBase = EntryEBP - RegNodeSize
16057 // ParentFP = RegNodeBase - RegNodeFrameOffset
16058 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16059 DAG.getConstant(RegNodeSize, dl, PtrVT));
16060 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16063 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16064 SelectionDAG &DAG) {
16066 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16067 MVT VT = Op.getSimpleValueType();
16068 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16070 switch(IntrData->Type) {
16071 case INTR_TYPE_1OP:
16072 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16073 case INTR_TYPE_2OP:
16074 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16076 case INTR_TYPE_2OP_IMM8:
16077 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16078 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16079 case INTR_TYPE_3OP:
16080 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16081 Op.getOperand(2), Op.getOperand(3));
16082 case INTR_TYPE_4OP:
16083 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16084 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16085 case INTR_TYPE_1OP_MASK_RM: {
16086 SDValue Src = Op.getOperand(1);
16087 SDValue PassThru = Op.getOperand(2);
16088 SDValue Mask = Op.getOperand(3);
16089 SDValue RoundingMode;
16090 // We allways add rounding mode to the Node.
16091 // If the rounding mode is not specified, we add the
16092 // "current direction" mode.
16093 if (Op.getNumOperands() == 4)
16095 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16097 RoundingMode = Op.getOperand(4);
16098 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16099 if (IntrWithRoundingModeOpcode != 0)
16100 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16101 X86::STATIC_ROUNDING::CUR_DIRECTION)
16102 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16103 dl, Op.getValueType(), Src, RoundingMode),
16104 Mask, PassThru, Subtarget, DAG);
16105 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16107 Mask, PassThru, Subtarget, DAG);
16109 case INTR_TYPE_1OP_MASK: {
16110 SDValue Src = Op.getOperand(1);
16111 SDValue PassThru = Op.getOperand(2);
16112 SDValue Mask = Op.getOperand(3);
16113 // We add rounding mode to the Node when
16114 // - RM Opcode is specified and
16115 // - RM is not "current direction".
16116 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16117 if (IntrWithRoundingModeOpcode != 0) {
16118 SDValue Rnd = Op.getOperand(4);
16119 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16120 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16121 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16122 dl, Op.getValueType(),
16124 Mask, PassThru, Subtarget, DAG);
16127 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16128 Mask, PassThru, Subtarget, DAG);
16130 case INTR_TYPE_SCALAR_MASK: {
16131 SDValue Src1 = Op.getOperand(1);
16132 SDValue Src2 = Op.getOperand(2);
16133 SDValue passThru = Op.getOperand(3);
16134 SDValue Mask = Op.getOperand(4);
16135 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16136 Mask, passThru, Subtarget, DAG);
16138 case INTR_TYPE_SCALAR_MASK_RM: {
16139 SDValue Src1 = Op.getOperand(1);
16140 SDValue Src2 = Op.getOperand(2);
16141 SDValue Src0 = Op.getOperand(3);
16142 SDValue Mask = Op.getOperand(4);
16143 // There are 2 kinds of intrinsics in this group:
16144 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16145 // (2) With rounding mode and sae - 7 operands.
16146 if (Op.getNumOperands() == 6) {
16147 SDValue Sae = Op.getOperand(5);
16148 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16149 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16151 Mask, Src0, Subtarget, DAG);
16153 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16154 SDValue RoundingMode = Op.getOperand(5);
16155 SDValue Sae = Op.getOperand(6);
16156 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16157 RoundingMode, Sae),
16158 Mask, Src0, Subtarget, DAG);
16160 case INTR_TYPE_2OP_MASK:
16161 case INTR_TYPE_2OP_IMM8_MASK: {
16162 SDValue Src1 = Op.getOperand(1);
16163 SDValue Src2 = Op.getOperand(2);
16164 SDValue PassThru = Op.getOperand(3);
16165 SDValue Mask = Op.getOperand(4);
16167 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16168 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16170 // We specify 2 possible opcodes for intrinsics with rounding modes.
16171 // First, we check if the intrinsic may have non-default rounding mode,
16172 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16173 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16174 if (IntrWithRoundingModeOpcode != 0) {
16175 SDValue Rnd = Op.getOperand(5);
16176 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16177 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16178 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16179 dl, Op.getValueType(),
16181 Mask, PassThru, Subtarget, DAG);
16184 // TODO: Intrinsics should have fast-math-flags to propagate.
16185 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16186 Mask, PassThru, Subtarget, DAG);
16188 case INTR_TYPE_2OP_MASK_RM: {
16189 SDValue Src1 = Op.getOperand(1);
16190 SDValue Src2 = Op.getOperand(2);
16191 SDValue PassThru = Op.getOperand(3);
16192 SDValue Mask = Op.getOperand(4);
16193 // We specify 2 possible modes for intrinsics, with/without rounding
16195 // First, we check if the intrinsic have rounding mode (6 operands),
16196 // if not, we set rounding mode to "current".
16198 if (Op.getNumOperands() == 6)
16199 Rnd = Op.getOperand(5);
16201 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16202 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16204 Mask, PassThru, Subtarget, DAG);
16206 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16207 SDValue Src1 = Op.getOperand(1);
16208 SDValue Src2 = Op.getOperand(2);
16209 SDValue Src3 = Op.getOperand(3);
16210 SDValue PassThru = Op.getOperand(4);
16211 SDValue Mask = Op.getOperand(5);
16212 SDValue Sae = Op.getOperand(6);
16214 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16216 Mask, PassThru, Subtarget, DAG);
16218 case INTR_TYPE_3OP_MASK_RM: {
16219 SDValue Src1 = Op.getOperand(1);
16220 SDValue Src2 = Op.getOperand(2);
16221 SDValue Imm = Op.getOperand(3);
16222 SDValue PassThru = Op.getOperand(4);
16223 SDValue Mask = Op.getOperand(5);
16224 // We specify 2 possible modes for intrinsics, with/without rounding
16226 // First, we check if the intrinsic have rounding mode (7 operands),
16227 // if not, we set rounding mode to "current".
16229 if (Op.getNumOperands() == 7)
16230 Rnd = Op.getOperand(6);
16232 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16233 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16234 Src1, Src2, Imm, Rnd),
16235 Mask, PassThru, Subtarget, DAG);
16237 case INTR_TYPE_3OP_IMM8_MASK:
16238 case INTR_TYPE_3OP_MASK:
16239 case INSERT_SUBVEC: {
16240 SDValue Src1 = Op.getOperand(1);
16241 SDValue Src2 = Op.getOperand(2);
16242 SDValue Src3 = Op.getOperand(3);
16243 SDValue PassThru = Op.getOperand(4);
16244 SDValue Mask = Op.getOperand(5);
16246 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16247 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16248 else if (IntrData->Type == INSERT_SUBVEC) {
16249 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16250 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16251 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16252 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16253 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16256 // We specify 2 possible opcodes for intrinsics with rounding modes.
16257 // First, we check if the intrinsic may have non-default rounding mode,
16258 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16259 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16260 if (IntrWithRoundingModeOpcode != 0) {
16261 SDValue Rnd = Op.getOperand(6);
16262 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16263 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16264 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16265 dl, Op.getValueType(),
16266 Src1, Src2, Src3, Rnd),
16267 Mask, PassThru, Subtarget, DAG);
16270 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16272 Mask, PassThru, Subtarget, DAG);
16274 case VPERM_3OP_MASKZ:
16275 case VPERM_3OP_MASK:
16278 case FMA_OP_MASK: {
16279 SDValue Src1 = Op.getOperand(1);
16280 SDValue Src2 = Op.getOperand(2);
16281 SDValue Src3 = Op.getOperand(3);
16282 SDValue Mask = Op.getOperand(4);
16283 MVT VT = Op.getSimpleValueType();
16284 SDValue PassThru = SDValue();
16286 // set PassThru element
16287 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16288 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16289 else if (IntrData->Type == FMA_OP_MASK3)
16294 // We specify 2 possible opcodes for intrinsics with rounding modes.
16295 // First, we check if the intrinsic may have non-default rounding mode,
16296 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16297 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16298 if (IntrWithRoundingModeOpcode != 0) {
16299 SDValue Rnd = Op.getOperand(5);
16300 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16301 X86::STATIC_ROUNDING::CUR_DIRECTION)
16302 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16303 dl, Op.getValueType(),
16304 Src1, Src2, Src3, Rnd),
16305 Mask, PassThru, Subtarget, DAG);
16307 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16308 dl, Op.getValueType(),
16310 Mask, PassThru, Subtarget, DAG);
16312 case TERLOG_OP_MASK:
16313 case TERLOG_OP_MASKZ: {
16314 SDValue Src1 = Op.getOperand(1);
16315 SDValue Src2 = Op.getOperand(2);
16316 SDValue Src3 = Op.getOperand(3);
16317 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16318 SDValue Mask = Op.getOperand(5);
16319 MVT VT = Op.getSimpleValueType();
16320 SDValue PassThru = Src1;
16321 // Set PassThru element.
16322 if (IntrData->Type == TERLOG_OP_MASKZ)
16323 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16325 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16326 Src1, Src2, Src3, Src4),
16327 Mask, PassThru, Subtarget, DAG);
16330 // FPclass intrinsics with mask
16331 SDValue Src1 = Op.getOperand(1);
16332 MVT VT = Src1.getSimpleValueType();
16333 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16334 SDValue Imm = Op.getOperand(2);
16335 SDValue Mask = Op.getOperand(3);
16336 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16337 Mask.getSimpleValueType().getSizeInBits());
16338 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16339 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16340 DAG.getTargetConstant(0, dl, MaskVT),
16342 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16343 DAG.getUNDEF(BitcastVT), FPclassMask,
16344 DAG.getIntPtrConstant(0, dl));
16345 return DAG.getBitcast(Op.getValueType(), Res);
16348 SDValue Src1 = Op.getOperand(1);
16349 SDValue Imm = Op.getOperand(2);
16350 SDValue Mask = Op.getOperand(3);
16351 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16352 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16353 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16354 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16357 case CMP_MASK_CC: {
16358 // Comparison intrinsics with masks.
16359 // Example of transformation:
16360 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16361 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16363 // (v8i1 (insert_subvector undef,
16364 // (v2i1 (and (PCMPEQM %a, %b),
16365 // (extract_subvector
16366 // (v8i1 (bitcast %mask)), 0))), 0))))
16367 MVT VT = Op.getOperand(1).getSimpleValueType();
16368 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16369 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16370 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16371 Mask.getSimpleValueType().getSizeInBits());
16373 if (IntrData->Type == CMP_MASK_CC) {
16374 SDValue CC = Op.getOperand(3);
16375 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16376 // We specify 2 possible opcodes for intrinsics with rounding modes.
16377 // First, we check if the intrinsic may have non-default rounding mode,
16378 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16379 if (IntrData->Opc1 != 0) {
16380 SDValue Rnd = Op.getOperand(5);
16381 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16382 X86::STATIC_ROUNDING::CUR_DIRECTION)
16383 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16384 Op.getOperand(2), CC, Rnd);
16386 //default rounding mode
16388 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16389 Op.getOperand(2), CC);
16392 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16393 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16396 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16397 DAG.getTargetConstant(0, dl,
16400 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16401 DAG.getUNDEF(BitcastVT), CmpMask,
16402 DAG.getIntPtrConstant(0, dl));
16403 return DAG.getBitcast(Op.getValueType(), Res);
16405 case CMP_MASK_SCALAR_CC: {
16406 SDValue Src1 = Op.getOperand(1);
16407 SDValue Src2 = Op.getOperand(2);
16408 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16409 SDValue Mask = Op.getOperand(4);
16412 if (IntrData->Opc1 != 0) {
16413 SDValue Rnd = Op.getOperand(5);
16414 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16415 X86::STATIC_ROUNDING::CUR_DIRECTION)
16416 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16418 //default rounding mode
16420 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16422 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16423 DAG.getTargetConstant(0, dl,
16427 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16428 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16429 DAG.getValueType(MVT::i1));
16431 case COMI: { // Comparison intrinsics
16432 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16433 SDValue LHS = Op.getOperand(1);
16434 SDValue RHS = Op.getOperand(2);
16435 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16436 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16437 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16438 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16439 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16440 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16443 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16444 Op.getOperand(1), Op.getOperand(2), DAG);
16446 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16447 Op.getSimpleValueType(),
16449 Op.getOperand(2), DAG),
16450 Op.getOperand(4), Op.getOperand(3), Subtarget,
16452 case COMPRESS_EXPAND_IN_REG: {
16453 SDValue Mask = Op.getOperand(3);
16454 SDValue DataToCompress = Op.getOperand(1);
16455 SDValue PassThru = Op.getOperand(2);
16456 if (isAllOnes(Mask)) // return data as is
16457 return Op.getOperand(1);
16459 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16461 Mask, PassThru, Subtarget, DAG);
16464 SDValue Mask = Op.getOperand(3);
16465 MVT VT = Op.getSimpleValueType();
16466 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16467 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16468 Mask.getSimpleValueType().getSizeInBits());
16470 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16471 DAG.getBitcast(BitcastVT, Mask),
16472 DAG.getIntPtrConstant(0, dl));
16473 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16482 default: return SDValue(); // Don't custom lower most intrinsics.
16484 case Intrinsic::x86_avx2_permd:
16485 case Intrinsic::x86_avx2_permps:
16486 // Operands intentionally swapped. Mask is last operand to intrinsic,
16487 // but second operand for node/instruction.
16488 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16489 Op.getOperand(2), Op.getOperand(1));
16491 // ptest and testp intrinsics. The intrinsic these come from are designed to
16492 // return an integer value, not just an instruction so lower it to the ptest
16493 // or testp pattern and a setcc for the result.
16494 case Intrinsic::x86_sse41_ptestz:
16495 case Intrinsic::x86_sse41_ptestc:
16496 case Intrinsic::x86_sse41_ptestnzc:
16497 case Intrinsic::x86_avx_ptestz_256:
16498 case Intrinsic::x86_avx_ptestc_256:
16499 case Intrinsic::x86_avx_ptestnzc_256:
16500 case Intrinsic::x86_avx_vtestz_ps:
16501 case Intrinsic::x86_avx_vtestc_ps:
16502 case Intrinsic::x86_avx_vtestnzc_ps:
16503 case Intrinsic::x86_avx_vtestz_pd:
16504 case Intrinsic::x86_avx_vtestc_pd:
16505 case Intrinsic::x86_avx_vtestnzc_pd:
16506 case Intrinsic::x86_avx_vtestz_ps_256:
16507 case Intrinsic::x86_avx_vtestc_ps_256:
16508 case Intrinsic::x86_avx_vtestnzc_ps_256:
16509 case Intrinsic::x86_avx_vtestz_pd_256:
16510 case Intrinsic::x86_avx_vtestc_pd_256:
16511 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16512 bool IsTestPacked = false;
16515 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16516 case Intrinsic::x86_avx_vtestz_ps:
16517 case Intrinsic::x86_avx_vtestz_pd:
16518 case Intrinsic::x86_avx_vtestz_ps_256:
16519 case Intrinsic::x86_avx_vtestz_pd_256:
16520 IsTestPacked = true; // Fallthrough
16521 case Intrinsic::x86_sse41_ptestz:
16522 case Intrinsic::x86_avx_ptestz_256:
16524 X86CC = X86::COND_E;
16526 case Intrinsic::x86_avx_vtestc_ps:
16527 case Intrinsic::x86_avx_vtestc_pd:
16528 case Intrinsic::x86_avx_vtestc_ps_256:
16529 case Intrinsic::x86_avx_vtestc_pd_256:
16530 IsTestPacked = true; // Fallthrough
16531 case Intrinsic::x86_sse41_ptestc:
16532 case Intrinsic::x86_avx_ptestc_256:
16534 X86CC = X86::COND_B;
16536 case Intrinsic::x86_avx_vtestnzc_ps:
16537 case Intrinsic::x86_avx_vtestnzc_pd:
16538 case Intrinsic::x86_avx_vtestnzc_ps_256:
16539 case Intrinsic::x86_avx_vtestnzc_pd_256:
16540 IsTestPacked = true; // Fallthrough
16541 case Intrinsic::x86_sse41_ptestnzc:
16542 case Intrinsic::x86_avx_ptestnzc_256:
16544 X86CC = X86::COND_A;
16548 SDValue LHS = Op.getOperand(1);
16549 SDValue RHS = Op.getOperand(2);
16550 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16551 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16552 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16553 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16554 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16556 case Intrinsic::x86_avx512_kortestz_w:
16557 case Intrinsic::x86_avx512_kortestc_w: {
16558 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16559 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16560 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16561 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16562 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16563 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16564 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16567 case Intrinsic::x86_sse42_pcmpistria128:
16568 case Intrinsic::x86_sse42_pcmpestria128:
16569 case Intrinsic::x86_sse42_pcmpistric128:
16570 case Intrinsic::x86_sse42_pcmpestric128:
16571 case Intrinsic::x86_sse42_pcmpistrio128:
16572 case Intrinsic::x86_sse42_pcmpestrio128:
16573 case Intrinsic::x86_sse42_pcmpistris128:
16574 case Intrinsic::x86_sse42_pcmpestris128:
16575 case Intrinsic::x86_sse42_pcmpistriz128:
16576 case Intrinsic::x86_sse42_pcmpestriz128: {
16580 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16581 case Intrinsic::x86_sse42_pcmpistria128:
16582 Opcode = X86ISD::PCMPISTRI;
16583 X86CC = X86::COND_A;
16585 case Intrinsic::x86_sse42_pcmpestria128:
16586 Opcode = X86ISD::PCMPESTRI;
16587 X86CC = X86::COND_A;
16589 case Intrinsic::x86_sse42_pcmpistric128:
16590 Opcode = X86ISD::PCMPISTRI;
16591 X86CC = X86::COND_B;
16593 case Intrinsic::x86_sse42_pcmpestric128:
16594 Opcode = X86ISD::PCMPESTRI;
16595 X86CC = X86::COND_B;
16597 case Intrinsic::x86_sse42_pcmpistrio128:
16598 Opcode = X86ISD::PCMPISTRI;
16599 X86CC = X86::COND_O;
16601 case Intrinsic::x86_sse42_pcmpestrio128:
16602 Opcode = X86ISD::PCMPESTRI;
16603 X86CC = X86::COND_O;
16605 case Intrinsic::x86_sse42_pcmpistris128:
16606 Opcode = X86ISD::PCMPISTRI;
16607 X86CC = X86::COND_S;
16609 case Intrinsic::x86_sse42_pcmpestris128:
16610 Opcode = X86ISD::PCMPESTRI;
16611 X86CC = X86::COND_S;
16613 case Intrinsic::x86_sse42_pcmpistriz128:
16614 Opcode = X86ISD::PCMPISTRI;
16615 X86CC = X86::COND_E;
16617 case Intrinsic::x86_sse42_pcmpestriz128:
16618 Opcode = X86ISD::PCMPESTRI;
16619 X86CC = X86::COND_E;
16622 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16623 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16624 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16625 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16626 DAG.getConstant(X86CC, dl, MVT::i8),
16627 SDValue(PCMP.getNode(), 1));
16628 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16631 case Intrinsic::x86_sse42_pcmpistri128:
16632 case Intrinsic::x86_sse42_pcmpestri128: {
16634 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16635 Opcode = X86ISD::PCMPISTRI;
16637 Opcode = X86ISD::PCMPESTRI;
16639 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16640 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16641 return DAG.getNode(Opcode, dl, VTs, NewOps);
16644 case Intrinsic::x86_seh_lsda: {
16645 // Compute the symbol for the LSDA. We know it'll get emitted later.
16646 MachineFunction &MF = DAG.getMachineFunction();
16647 SDValue Op1 = Op.getOperand(1);
16648 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16649 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16650 GlobalValue::getRealLinkageName(Fn->getName()));
16652 // Generate a simple absolute symbol reference. This intrinsic is only
16653 // supported on 32-bit Windows, which isn't PIC.
16654 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16655 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16658 case Intrinsic::x86_seh_recoverfp: {
16659 SDValue FnOp = Op.getOperand(1);
16660 SDValue IncomingFPOp = Op.getOperand(2);
16661 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16662 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16664 report_fatal_error(
16665 "llvm.x86.seh.recoverfp must take a function as the first argument");
16666 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16669 case Intrinsic::localaddress: {
16670 // Returns one of the stack, base, or frame pointer registers, depending on
16671 // which is used to reference local variables.
16672 MachineFunction &MF = DAG.getMachineFunction();
16673 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16675 if (RegInfo->hasBasePointer(MF))
16676 Reg = RegInfo->getBaseRegister();
16677 else // This function handles the SP or FP case.
16678 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16679 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16684 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16685 SDValue Src, SDValue Mask, SDValue Base,
16686 SDValue Index, SDValue ScaleOp, SDValue Chain,
16687 const X86Subtarget * Subtarget) {
16689 auto *C = cast<ConstantSDNode>(ScaleOp);
16690 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16691 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16692 Index.getSimpleValueType().getVectorNumElements());
16694 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16696 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16698 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16699 Mask.getSimpleValueType().getSizeInBits());
16701 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16702 // are extracted by EXTRACT_SUBVECTOR.
16703 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16704 DAG.getBitcast(BitcastVT, Mask),
16705 DAG.getIntPtrConstant(0, dl));
16707 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16708 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16709 SDValue Segment = DAG.getRegister(0, MVT::i32);
16710 if (Src.getOpcode() == ISD::UNDEF)
16711 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16712 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16713 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16714 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16715 return DAG.getMergeValues(RetOps, dl);
16718 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16719 SDValue Src, SDValue Mask, SDValue Base,
16720 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16722 auto *C = cast<ConstantSDNode>(ScaleOp);
16723 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16724 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16725 SDValue Segment = DAG.getRegister(0, MVT::i32);
16726 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16727 Index.getSimpleValueType().getVectorNumElements());
16729 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16731 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16733 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16734 Mask.getSimpleValueType().getSizeInBits());
16736 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16737 // are extracted by EXTRACT_SUBVECTOR.
16738 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16739 DAG.getBitcast(BitcastVT, Mask),
16740 DAG.getIntPtrConstant(0, dl));
16742 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16743 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16744 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16745 return SDValue(Res, 1);
16748 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16749 SDValue Mask, SDValue Base, SDValue Index,
16750 SDValue ScaleOp, SDValue Chain) {
16752 auto *C = cast<ConstantSDNode>(ScaleOp);
16753 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16754 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16755 SDValue Segment = DAG.getRegister(0, MVT::i32);
16757 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16759 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16761 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16763 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16764 //SDVTList VTs = DAG.getVTList(MVT::Other);
16765 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16766 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16767 return SDValue(Res, 0);
16770 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16771 // read performance monitor counters (x86_rdpmc).
16772 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16773 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16774 SmallVectorImpl<SDValue> &Results) {
16775 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16776 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16779 // The ECX register is used to select the index of the performance counter
16781 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16783 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16785 // Reads the content of a 64-bit performance counter and returns it in the
16786 // registers EDX:EAX.
16787 if (Subtarget->is64Bit()) {
16788 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16789 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16792 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16793 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16796 Chain = HI.getValue(1);
16798 if (Subtarget->is64Bit()) {
16799 // The EAX register is loaded with the low-order 32 bits. The EDX register
16800 // is loaded with the supported high-order bits of the counter.
16801 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16802 DAG.getConstant(32, DL, MVT::i8));
16803 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16804 Results.push_back(Chain);
16808 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16809 SDValue Ops[] = { LO, HI };
16810 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16811 Results.push_back(Pair);
16812 Results.push_back(Chain);
16815 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16816 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16817 // also used to custom lower READCYCLECOUNTER nodes.
16818 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16819 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16820 SmallVectorImpl<SDValue> &Results) {
16821 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16822 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16825 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16826 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16827 // and the EAX register is loaded with the low-order 32 bits.
16828 if (Subtarget->is64Bit()) {
16829 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16830 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16833 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16834 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16837 SDValue Chain = HI.getValue(1);
16839 if (Opcode == X86ISD::RDTSCP_DAG) {
16840 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16842 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16843 // the ECX register. Add 'ecx' explicitly to the chain.
16844 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16846 // Explicitly store the content of ECX at the location passed in input
16847 // to the 'rdtscp' intrinsic.
16848 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16849 MachinePointerInfo(), false, false, 0);
16852 if (Subtarget->is64Bit()) {
16853 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16854 // the EAX register is loaded with the low-order 32 bits.
16855 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16856 DAG.getConstant(32, DL, MVT::i8));
16857 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16858 Results.push_back(Chain);
16862 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16863 SDValue Ops[] = { LO, HI };
16864 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16865 Results.push_back(Pair);
16866 Results.push_back(Chain);
16869 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16870 SelectionDAG &DAG) {
16871 SmallVector<SDValue, 2> Results;
16873 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16875 return DAG.getMergeValues(Results, DL);
16878 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16879 SelectionDAG &DAG) {
16880 MachineFunction &MF = DAG.getMachineFunction();
16881 const Function *Fn = MF.getFunction();
16883 SDValue Chain = Op.getOperand(0);
16885 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16886 "using llvm.x86.seh.restoreframe requires a frame pointer");
16888 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16889 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16891 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16892 unsigned FrameReg =
16893 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16894 unsigned SPReg = RegInfo->getStackRegister();
16895 unsigned SlotSize = RegInfo->getSlotSize();
16897 // Get incoming EBP.
16898 SDValue IncomingEBP =
16899 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16901 // SP is saved in the first field of every registration node, so load
16902 // [EBP-RegNodeSize] into SP.
16903 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16904 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16905 DAG.getConstant(-RegNodeSize, dl, VT));
16907 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16908 false, VT.getScalarSizeInBits() / 8);
16909 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16911 if (!RegInfo->needsStackRealignment(MF)) {
16912 // Adjust EBP to point back to the original frame position.
16913 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16914 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16916 assert(RegInfo->hasBasePointer(MF) &&
16917 "functions with Win32 EH must use frame or base pointer register");
16919 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16920 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16921 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16923 // Reload the spilled EBP value, now that the stack and base pointers are
16925 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16926 X86FI->setHasSEHFramePtrSave(true);
16927 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16928 X86FI->setSEHFramePtrSaveIndex(FI);
16929 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16930 MachinePointerInfo(), false, false, false,
16931 VT.getScalarSizeInBits() / 8);
16932 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16938 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16939 /// return truncate Store/MaskedStore Node
16940 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16944 SDValue Mask = Op.getOperand(4);
16945 SDValue DataToTruncate = Op.getOperand(3);
16946 SDValue Addr = Op.getOperand(2);
16947 SDValue Chain = Op.getOperand(0);
16949 MVT VT = DataToTruncate.getSimpleValueType();
16950 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
16952 if (isAllOnes(Mask)) // return just a truncate store
16953 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16954 MachinePointerInfo(), SVT, false, false,
16955 SVT.getScalarSizeInBits()/8);
16957 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16958 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16959 Mask.getSimpleValueType().getSizeInBits());
16960 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16961 // are extracted by EXTRACT_SUBVECTOR.
16962 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16963 DAG.getBitcast(BitcastVT, Mask),
16964 DAG.getIntPtrConstant(0, dl));
16966 MachineMemOperand *MMO = DAG.getMachineFunction().
16967 getMachineMemOperand(MachinePointerInfo(),
16968 MachineMemOperand::MOStore, SVT.getStoreSize(),
16969 SVT.getScalarSizeInBits()/8);
16971 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16972 VMask, SVT, MMO, true);
16975 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16976 SelectionDAG &DAG) {
16977 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16979 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16981 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16982 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16987 switch(IntrData->Type) {
16988 default: llvm_unreachable("Unknown Intrinsic Type");
16991 // Emit the node with the right value type.
16992 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16993 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16995 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16996 // Otherwise return the value from Rand, which is always 0, casted to i32.
16997 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16998 DAG.getConstant(1, dl, Op->getValueType(1)),
16999 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17000 SDValue(Result.getNode(), 1) };
17001 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17002 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17005 // Return { result, isValid, chain }.
17006 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17007 SDValue(Result.getNode(), 2));
17010 //gather(v1, mask, index, base, scale);
17011 SDValue Chain = Op.getOperand(0);
17012 SDValue Src = Op.getOperand(2);
17013 SDValue Base = Op.getOperand(3);
17014 SDValue Index = Op.getOperand(4);
17015 SDValue Mask = Op.getOperand(5);
17016 SDValue Scale = Op.getOperand(6);
17017 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17021 //scatter(base, mask, index, v1, scale);
17022 SDValue Chain = Op.getOperand(0);
17023 SDValue Base = Op.getOperand(2);
17024 SDValue Mask = Op.getOperand(3);
17025 SDValue Index = Op.getOperand(4);
17026 SDValue Src = Op.getOperand(5);
17027 SDValue Scale = Op.getOperand(6);
17028 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17032 SDValue Hint = Op.getOperand(6);
17033 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17034 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17035 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17036 SDValue Chain = Op.getOperand(0);
17037 SDValue Mask = Op.getOperand(2);
17038 SDValue Index = Op.getOperand(3);
17039 SDValue Base = Op.getOperand(4);
17040 SDValue Scale = Op.getOperand(5);
17041 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17043 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17045 SmallVector<SDValue, 2> Results;
17046 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17048 return DAG.getMergeValues(Results, dl);
17050 // Read Performance Monitoring Counters.
17052 SmallVector<SDValue, 2> Results;
17053 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17054 return DAG.getMergeValues(Results, dl);
17056 // XTEST intrinsics.
17058 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17059 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17060 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17061 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17063 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17064 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17065 Ret, SDValue(InTrans.getNode(), 1));
17069 SmallVector<SDValue, 2> Results;
17070 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17071 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17072 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17073 DAG.getConstant(-1, dl, MVT::i8));
17074 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17075 Op.getOperand(4), GenCF.getValue(1));
17076 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17077 Op.getOperand(5), MachinePointerInfo(),
17079 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17080 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17082 Results.push_back(SetCC);
17083 Results.push_back(Store);
17084 return DAG.getMergeValues(Results, dl);
17086 case COMPRESS_TO_MEM: {
17088 SDValue Mask = Op.getOperand(4);
17089 SDValue DataToCompress = Op.getOperand(3);
17090 SDValue Addr = Op.getOperand(2);
17091 SDValue Chain = Op.getOperand(0);
17093 MVT VT = DataToCompress.getSimpleValueType();
17094 if (isAllOnes(Mask)) // return just a store
17095 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17096 MachinePointerInfo(), false, false,
17097 VT.getScalarSizeInBits()/8);
17099 SDValue Compressed =
17100 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17101 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17102 return DAG.getStore(Chain, dl, Compressed, Addr,
17103 MachinePointerInfo(), false, false,
17104 VT.getScalarSizeInBits()/8);
17106 case TRUNCATE_TO_MEM_VI8:
17107 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17108 case TRUNCATE_TO_MEM_VI16:
17109 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17110 case TRUNCATE_TO_MEM_VI32:
17111 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17112 case EXPAND_FROM_MEM: {
17114 SDValue Mask = Op.getOperand(4);
17115 SDValue PassThru = Op.getOperand(3);
17116 SDValue Addr = Op.getOperand(2);
17117 SDValue Chain = Op.getOperand(0);
17118 MVT VT = Op.getSimpleValueType();
17120 if (isAllOnes(Mask)) // return just a load
17121 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17122 false, VT.getScalarSizeInBits()/8);
17124 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17125 false, false, false,
17126 VT.getScalarSizeInBits()/8);
17128 SDValue Results[] = {
17129 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17130 Mask, PassThru, Subtarget, DAG), Chain};
17131 return DAG.getMergeValues(Results, dl);
17136 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17137 SelectionDAG &DAG) const {
17138 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17139 MFI->setReturnAddressIsTaken(true);
17141 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17144 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17146 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17149 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17150 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17151 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17152 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17153 DAG.getNode(ISD::ADD, dl, PtrVT,
17154 FrameAddr, Offset),
17155 MachinePointerInfo(), false, false, false, 0);
17158 // Just load the return address.
17159 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17160 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17161 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17164 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17165 MachineFunction &MF = DAG.getMachineFunction();
17166 MachineFrameInfo *MFI = MF.getFrameInfo();
17167 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17168 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17169 EVT VT = Op.getValueType();
17171 MFI->setFrameAddressIsTaken(true);
17173 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17174 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17175 // is not possible to crawl up the stack without looking at the unwind codes
17177 int FrameAddrIndex = FuncInfo->getFAIndex();
17178 if (!FrameAddrIndex) {
17179 // Set up a frame object for the return address.
17180 unsigned SlotSize = RegInfo->getSlotSize();
17181 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17182 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17183 FuncInfo->setFAIndex(FrameAddrIndex);
17185 return DAG.getFrameIndex(FrameAddrIndex, VT);
17188 unsigned FrameReg =
17189 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17190 SDLoc dl(Op); // FIXME probably not meaningful
17191 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17192 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17193 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17194 "Invalid Frame Register!");
17195 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17197 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17198 MachinePointerInfo(),
17199 false, false, false, 0);
17203 // FIXME? Maybe this could be a TableGen attribute on some registers and
17204 // this table could be generated automatically from RegInfo.
17205 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17206 SelectionDAG &DAG) const {
17207 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17208 const MachineFunction &MF = DAG.getMachineFunction();
17210 unsigned Reg = StringSwitch<unsigned>(RegName)
17211 .Case("esp", X86::ESP)
17212 .Case("rsp", X86::RSP)
17213 .Case("ebp", X86::EBP)
17214 .Case("rbp", X86::RBP)
17217 if (Reg == X86::EBP || Reg == X86::RBP) {
17218 if (!TFI.hasFP(MF))
17219 report_fatal_error("register " + StringRef(RegName) +
17220 " is allocatable: function has no frame pointer");
17223 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17224 unsigned FrameReg =
17225 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17226 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17227 "Invalid Frame Register!");
17235 report_fatal_error("Invalid register name global variable");
17238 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17239 SelectionDAG &DAG) const {
17240 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17241 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17244 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17245 SDValue Chain = Op.getOperand(0);
17246 SDValue Offset = Op.getOperand(1);
17247 SDValue Handler = Op.getOperand(2);
17250 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17251 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17252 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17253 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17254 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17255 "Invalid Frame Register!");
17256 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17257 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17259 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17260 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17262 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17263 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17265 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17267 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17268 DAG.getRegister(StoreAddrReg, PtrVT));
17271 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17272 SelectionDAG &DAG) const {
17274 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17275 DAG.getVTList(MVT::i32, MVT::Other),
17276 Op.getOperand(0), Op.getOperand(1));
17279 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17280 SelectionDAG &DAG) const {
17282 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17283 Op.getOperand(0), Op.getOperand(1));
17286 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17287 return Op.getOperand(0);
17290 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17291 SelectionDAG &DAG) const {
17292 SDValue Root = Op.getOperand(0);
17293 SDValue Trmp = Op.getOperand(1); // trampoline
17294 SDValue FPtr = Op.getOperand(2); // nested function
17295 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17298 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17299 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17301 if (Subtarget->is64Bit()) {
17302 SDValue OutChains[6];
17304 // Large code-model.
17305 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17306 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17308 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17309 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17311 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17313 // Load the pointer to the nested function into R11.
17314 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17315 SDValue Addr = Trmp;
17316 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17317 Addr, MachinePointerInfo(TrmpAddr),
17320 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17321 DAG.getConstant(2, dl, MVT::i64));
17322 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17323 MachinePointerInfo(TrmpAddr, 2),
17326 // Load the 'nest' parameter value into R10.
17327 // R10 is specified in X86CallingConv.td
17328 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17329 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17330 DAG.getConstant(10, dl, MVT::i64));
17331 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17332 Addr, MachinePointerInfo(TrmpAddr, 10),
17335 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17336 DAG.getConstant(12, dl, MVT::i64));
17337 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17338 MachinePointerInfo(TrmpAddr, 12),
17341 // Jump to the nested function.
17342 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17343 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17344 DAG.getConstant(20, dl, MVT::i64));
17345 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17346 Addr, MachinePointerInfo(TrmpAddr, 20),
17349 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17350 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17351 DAG.getConstant(22, dl, MVT::i64));
17352 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17353 Addr, MachinePointerInfo(TrmpAddr, 22),
17356 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17358 const Function *Func =
17359 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17360 CallingConv::ID CC = Func->getCallingConv();
17365 llvm_unreachable("Unsupported calling convention");
17366 case CallingConv::C:
17367 case CallingConv::X86_StdCall: {
17368 // Pass 'nest' parameter in ECX.
17369 // Must be kept in sync with X86CallingConv.td
17370 NestReg = X86::ECX;
17372 // Check that ECX wasn't needed by an 'inreg' parameter.
17373 FunctionType *FTy = Func->getFunctionType();
17374 const AttributeSet &Attrs = Func->getAttributes();
17376 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17377 unsigned InRegCount = 0;
17380 for (FunctionType::param_iterator I = FTy->param_begin(),
17381 E = FTy->param_end(); I != E; ++I, ++Idx)
17382 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17383 auto &DL = DAG.getDataLayout();
17384 // FIXME: should only count parameters that are lowered to integers.
17385 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17388 if (InRegCount > 2) {
17389 report_fatal_error("Nest register in use - reduce number of inreg"
17395 case CallingConv::X86_FastCall:
17396 case CallingConv::X86_ThisCall:
17397 case CallingConv::Fast:
17398 // Pass 'nest' parameter in EAX.
17399 // Must be kept in sync with X86CallingConv.td
17400 NestReg = X86::EAX;
17404 SDValue OutChains[4];
17405 SDValue Addr, Disp;
17407 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17408 DAG.getConstant(10, dl, MVT::i32));
17409 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17411 // This is storing the opcode for MOV32ri.
17412 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17413 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17414 OutChains[0] = DAG.getStore(Root, dl,
17415 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17416 Trmp, MachinePointerInfo(TrmpAddr),
17419 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17420 DAG.getConstant(1, dl, MVT::i32));
17421 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17422 MachinePointerInfo(TrmpAddr, 1),
17425 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17426 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17427 DAG.getConstant(5, dl, MVT::i32));
17428 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17429 Addr, MachinePointerInfo(TrmpAddr, 5),
17432 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17433 DAG.getConstant(6, dl, MVT::i32));
17434 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17435 MachinePointerInfo(TrmpAddr, 6),
17438 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17442 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17443 SelectionDAG &DAG) const {
17445 The rounding mode is in bits 11:10 of FPSR, and has the following
17447 00 Round to nearest
17452 FLT_ROUNDS, on the other hand, expects the following:
17459 To perform the conversion, we do:
17460 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17463 MachineFunction &MF = DAG.getMachineFunction();
17464 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17465 unsigned StackAlignment = TFI.getStackAlignment();
17466 MVT VT = Op.getSimpleValueType();
17469 // Save FP Control Word to stack slot
17470 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17471 SDValue StackSlot =
17472 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17474 MachineMemOperand *MMO =
17475 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17476 MachineMemOperand::MOStore, 2, 2);
17478 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17479 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17480 DAG.getVTList(MVT::Other),
17481 Ops, MVT::i16, MMO);
17483 // Load FP Control Word from stack slot
17484 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17485 MachinePointerInfo(), false, false, false, 0);
17487 // Transform as necessary
17489 DAG.getNode(ISD::SRL, DL, MVT::i16,
17490 DAG.getNode(ISD::AND, DL, MVT::i16,
17491 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17492 DAG.getConstant(11, DL, MVT::i8));
17494 DAG.getNode(ISD::SRL, DL, MVT::i16,
17495 DAG.getNode(ISD::AND, DL, MVT::i16,
17496 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17497 DAG.getConstant(9, DL, MVT::i8));
17500 DAG.getNode(ISD::AND, DL, MVT::i16,
17501 DAG.getNode(ISD::ADD, DL, MVT::i16,
17502 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17503 DAG.getConstant(1, DL, MVT::i16)),
17504 DAG.getConstant(3, DL, MVT::i16));
17506 return DAG.getNode((VT.getSizeInBits() < 16 ?
17507 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17510 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17512 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17513 // to 512-bit vector.
17514 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17515 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17516 // split the vector, perform operation on it's Lo a Hi part and
17517 // concatenate the results.
17518 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17520 MVT VT = Op.getSimpleValueType();
17521 MVT EltVT = VT.getVectorElementType();
17522 unsigned NumElems = VT.getVectorNumElements();
17524 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17525 // Extend to 512 bit vector.
17526 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17527 "Unsupported value type for operation");
17529 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17530 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17531 DAG.getUNDEF(NewVT),
17533 DAG.getIntPtrConstant(0, dl));
17534 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17536 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17537 DAG.getIntPtrConstant(0, dl));
17540 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17541 "Unsupported element type");
17543 if (16 < NumElems) {
17544 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17546 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17547 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17549 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17550 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17552 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17555 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17557 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17558 "Unsupported value type for operation");
17560 // Use native supported vector instruction vplzcntd.
17561 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17562 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17563 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17564 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17566 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17569 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17570 SelectionDAG &DAG) {
17571 MVT VT = Op.getSimpleValueType();
17573 unsigned NumBits = VT.getSizeInBits();
17576 if (VT.isVector() && Subtarget->hasAVX512())
17577 return LowerVectorCTLZ_AVX512(Op, DAG);
17579 Op = Op.getOperand(0);
17580 if (VT == MVT::i8) {
17581 // Zero extend to i32 since there is not an i8 bsr.
17583 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17586 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17587 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17588 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17590 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17593 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17594 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17597 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17599 // Finally xor with NumBits-1.
17600 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17601 DAG.getConstant(NumBits - 1, dl, OpVT));
17604 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17608 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17609 SelectionDAG &DAG) {
17610 MVT VT = Op.getSimpleValueType();
17612 unsigned NumBits = VT.getSizeInBits();
17615 if (VT.isVector() && Subtarget->hasAVX512())
17616 return LowerVectorCTLZ_AVX512(Op, DAG);
17618 Op = Op.getOperand(0);
17619 if (VT == MVT::i8) {
17620 // Zero extend to i32 since there is not an i8 bsr.
17622 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17625 // Issue a bsr (scan bits in reverse).
17626 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17627 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17629 // And xor with NumBits-1.
17630 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17631 DAG.getConstant(NumBits - 1, dl, OpVT));
17634 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17638 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17639 MVT VT = Op.getSimpleValueType();
17640 unsigned NumBits = VT.getScalarSizeInBits();
17643 if (VT.isVector()) {
17644 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17646 SDValue N0 = Op.getOperand(0);
17647 SDValue Zero = DAG.getConstant(0, dl, VT);
17649 // lsb(x) = (x & -x)
17650 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17651 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17653 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17654 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17655 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17656 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17657 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17658 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17661 // cttz(x) = ctpop(lsb - 1)
17662 SDValue One = DAG.getConstant(1, dl, VT);
17663 return DAG.getNode(ISD::CTPOP, dl, VT,
17664 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17667 assert(Op.getOpcode() == ISD::CTTZ &&
17668 "Only scalar CTTZ requires custom lowering");
17670 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17671 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17672 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17674 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17677 DAG.getConstant(NumBits, dl, VT),
17678 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17681 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17684 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17685 // ones, and then concatenate the result back.
17686 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17687 MVT VT = Op.getSimpleValueType();
17689 assert(VT.is256BitVector() && VT.isInteger() &&
17690 "Unsupported value type for operation");
17692 unsigned NumElems = VT.getVectorNumElements();
17695 // Extract the LHS vectors
17696 SDValue LHS = Op.getOperand(0);
17697 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17698 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17700 // Extract the RHS vectors
17701 SDValue RHS = Op.getOperand(1);
17702 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17703 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17705 MVT EltVT = VT.getVectorElementType();
17706 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17708 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17709 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17710 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17713 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17714 if (Op.getValueType() == MVT::i1)
17715 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17716 Op.getOperand(0), Op.getOperand(1));
17717 assert(Op.getSimpleValueType().is256BitVector() &&
17718 Op.getSimpleValueType().isInteger() &&
17719 "Only handle AVX 256-bit vector integer operation");
17720 return Lower256IntArith(Op, DAG);
17723 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17724 if (Op.getValueType() == MVT::i1)
17725 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17726 Op.getOperand(0), Op.getOperand(1));
17727 assert(Op.getSimpleValueType().is256BitVector() &&
17728 Op.getSimpleValueType().isInteger() &&
17729 "Only handle AVX 256-bit vector integer operation");
17730 return Lower256IntArith(Op, DAG);
17733 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17734 assert(Op.getSimpleValueType().is256BitVector() &&
17735 Op.getSimpleValueType().isInteger() &&
17736 "Only handle AVX 256-bit vector integer operation");
17737 return Lower256IntArith(Op, DAG);
17740 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17741 SelectionDAG &DAG) {
17743 MVT VT = Op.getSimpleValueType();
17746 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17748 // Decompose 256-bit ops into smaller 128-bit ops.
17749 if (VT.is256BitVector() && !Subtarget->hasInt256())
17750 return Lower256IntArith(Op, DAG);
17752 SDValue A = Op.getOperand(0);
17753 SDValue B = Op.getOperand(1);
17755 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17756 // pairs, multiply and truncate.
17757 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17758 if (Subtarget->hasInt256()) {
17759 if (VT == MVT::v32i8) {
17760 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17761 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17762 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17763 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17764 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17765 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17766 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17767 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17768 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17769 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17772 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17773 return DAG.getNode(
17774 ISD::TRUNCATE, dl, VT,
17775 DAG.getNode(ISD::MUL, dl, ExVT,
17776 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17777 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17780 assert(VT == MVT::v16i8 &&
17781 "Pre-AVX2 support only supports v16i8 multiplication");
17782 MVT ExVT = MVT::v8i16;
17784 // Extract the lo parts and sign extend to i16
17786 if (Subtarget->hasSSE41()) {
17787 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17788 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17790 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17791 -1, 4, -1, 5, -1, 6, -1, 7};
17792 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17793 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17794 ALo = DAG.getBitcast(ExVT, ALo);
17795 BLo = DAG.getBitcast(ExVT, BLo);
17796 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17797 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17800 // Extract the hi parts and sign extend to i16
17802 if (Subtarget->hasSSE41()) {
17803 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17804 -1, -1, -1, -1, -1, -1, -1, -1};
17805 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17806 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17807 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17808 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17810 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17811 -1, 12, -1, 13, -1, 14, -1, 15};
17812 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17813 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17814 AHi = DAG.getBitcast(ExVT, AHi);
17815 BHi = DAG.getBitcast(ExVT, BHi);
17816 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17817 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17820 // Multiply, mask the lower 8bits of the lo/hi results and pack
17821 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17822 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17823 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17824 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17825 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17828 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17829 if (VT == MVT::v4i32) {
17830 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17831 "Should not custom lower when pmuldq is available!");
17833 // Extract the odd parts.
17834 static const int UnpackMask[] = { 1, -1, 3, -1 };
17835 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17836 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17838 // Multiply the even parts.
17839 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17840 // Now multiply odd parts.
17841 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17843 Evens = DAG.getBitcast(VT, Evens);
17844 Odds = DAG.getBitcast(VT, Odds);
17846 // Merge the two vectors back together with a shuffle. This expands into 2
17848 static const int ShufMask[] = { 0, 4, 2, 6 };
17849 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17852 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17853 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17855 // Ahi = psrlqi(a, 32);
17856 // Bhi = psrlqi(b, 32);
17858 // AloBlo = pmuludq(a, b);
17859 // AloBhi = pmuludq(a, Bhi);
17860 // AhiBlo = pmuludq(Ahi, b);
17862 // AloBhi = psllqi(AloBhi, 32);
17863 // AhiBlo = psllqi(AhiBlo, 32);
17864 // return AloBlo + AloBhi + AhiBlo;
17866 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17867 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17869 SDValue AhiBlo = Ahi;
17870 SDValue AloBhi = Bhi;
17871 // Bit cast to 32-bit vectors for MULUDQ
17872 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17873 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17874 A = DAG.getBitcast(MulVT, A);
17875 B = DAG.getBitcast(MulVT, B);
17876 Ahi = DAG.getBitcast(MulVT, Ahi);
17877 Bhi = DAG.getBitcast(MulVT, Bhi);
17879 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17880 // After shifting right const values the result may be all-zero.
17881 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17882 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17883 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17885 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17886 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17887 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17890 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17891 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17894 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17895 assert(Subtarget->isTargetWin64() && "Unexpected target");
17896 EVT VT = Op.getValueType();
17897 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17898 "Unexpected return type for lowering");
17902 switch (Op->getOpcode()) {
17903 default: llvm_unreachable("Unexpected request for libcall!");
17904 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17905 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17906 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17907 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17908 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17909 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17913 SDValue InChain = DAG.getEntryNode();
17915 TargetLowering::ArgListTy Args;
17916 TargetLowering::ArgListEntry Entry;
17917 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17918 EVT ArgVT = Op->getOperand(i).getValueType();
17919 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17920 "Unexpected argument type for lowering");
17921 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17922 Entry.Node = StackPtr;
17923 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17925 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17926 Entry.Ty = PointerType::get(ArgTy,0);
17927 Entry.isSExt = false;
17928 Entry.isZExt = false;
17929 Args.push_back(Entry);
17932 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17933 getPointerTy(DAG.getDataLayout()));
17935 TargetLowering::CallLoweringInfo CLI(DAG);
17936 CLI.setDebugLoc(dl).setChain(InChain)
17937 .setCallee(getLibcallCallingConv(LC),
17938 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17939 Callee, std::move(Args), 0)
17940 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17942 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17943 return DAG.getBitcast(VT, CallInfo.first);
17946 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17947 SelectionDAG &DAG) {
17948 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17949 MVT VT = Op0.getSimpleValueType();
17952 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17953 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17955 // PMULxD operations multiply each even value (starting at 0) of LHS with
17956 // the related value of RHS and produce a widen result.
17957 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17958 // => <2 x i64> <ae|cg>
17960 // In other word, to have all the results, we need to perform two PMULxD:
17961 // 1. one with the even values.
17962 // 2. one with the odd values.
17963 // To achieve #2, with need to place the odd values at an even position.
17965 // Place the odd value at an even position (basically, shift all values 1
17966 // step to the left):
17967 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17968 // <a|b|c|d> => <b|undef|d|undef>
17969 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17970 // <e|f|g|h> => <f|undef|h|undef>
17971 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17973 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17975 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17976 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17978 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17979 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17980 // => <2 x i64> <ae|cg>
17981 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17982 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17983 // => <2 x i64> <bf|dh>
17984 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17986 // Shuffle it back into the right order.
17987 SDValue Highs, Lows;
17988 if (VT == MVT::v8i32) {
17989 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17990 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17991 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17992 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17994 const int HighMask[] = {1, 5, 3, 7};
17995 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17996 const int LowMask[] = {0, 4, 2, 6};
17997 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18000 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18001 // unsigned multiply.
18002 if (IsSigned && !Subtarget->hasSSE41()) {
18003 SDValue ShAmt = DAG.getConstant(
18005 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18006 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18007 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18008 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18009 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18011 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18012 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18015 // The first result of MUL_LOHI is actually the low value, followed by the
18017 SDValue Ops[] = {Lows, Highs};
18018 return DAG.getMergeValues(Ops, dl);
18021 // Return true if the required (according to Opcode) shift-imm form is natively
18022 // supported by the Subtarget
18023 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18025 if (VT.getScalarSizeInBits() < 16)
18028 if (VT.is512BitVector() &&
18029 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18032 bool LShift = VT.is128BitVector() ||
18033 (VT.is256BitVector() && Subtarget->hasInt256());
18035 bool AShift = LShift && (Subtarget->hasVLX() ||
18036 (VT != MVT::v2i64 && VT != MVT::v4i64));
18037 return (Opcode == ISD::SRA) ? AShift : LShift;
18040 // The shift amount is a variable, but it is the same for all vector lanes.
18041 // These instructions are defined together with shift-immediate.
18043 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18045 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18048 // Return true if the required (according to Opcode) variable-shift form is
18049 // natively supported by the Subtarget
18050 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18053 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18056 // vXi16 supported only on AVX-512, BWI
18057 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18060 if (VT.is512BitVector() || Subtarget->hasVLX())
18063 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18064 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18065 return (Opcode == ISD::SRA) ? AShift : LShift;
18068 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18069 const X86Subtarget *Subtarget) {
18070 MVT VT = Op.getSimpleValueType();
18072 SDValue R = Op.getOperand(0);
18073 SDValue Amt = Op.getOperand(1);
18075 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18076 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18078 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18079 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18080 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18081 SDValue Ex = DAG.getBitcast(ExVT, R);
18083 if (ShiftAmt >= 32) {
18084 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18086 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18087 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18088 ShiftAmt - 32, DAG);
18089 if (VT == MVT::v2i64)
18090 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18091 if (VT == MVT::v4i64)
18092 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18093 {9, 1, 11, 3, 13, 5, 15, 7});
18095 // SRA upper i32, SHL whole i64 and select lower i32.
18096 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18099 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18100 Lower = DAG.getBitcast(ExVT, Lower);
18101 if (VT == MVT::v2i64)
18102 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18103 if (VT == MVT::v4i64)
18104 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18105 {8, 1, 10, 3, 12, 5, 14, 7});
18107 return DAG.getBitcast(VT, Ex);
18110 // Optimize shl/srl/sra with constant shift amount.
18111 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18112 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18113 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18115 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18116 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18118 // i64 SRA needs to be performed as partial shifts.
18119 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18120 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18121 return ArithmeticShiftRight64(ShiftAmt);
18123 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18124 unsigned NumElts = VT.getVectorNumElements();
18125 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18127 // Simple i8 add case
18128 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18129 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18131 // ashr(R, 7) === cmp_slt(R, 0)
18132 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18133 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18134 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18137 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18138 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18141 if (Op.getOpcode() == ISD::SHL) {
18142 // Make a large shift.
18143 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18145 SHL = DAG.getBitcast(VT, SHL);
18146 // Zero out the rightmost bits.
18147 SmallVector<SDValue, 32> V(
18148 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18149 return DAG.getNode(ISD::AND, dl, VT, SHL,
18150 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18152 if (Op.getOpcode() == ISD::SRL) {
18153 // Make a large shift.
18154 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18156 SRL = DAG.getBitcast(VT, SRL);
18157 // Zero out the leftmost bits.
18158 SmallVector<SDValue, 32> V(
18159 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18160 return DAG.getNode(ISD::AND, dl, VT, SRL,
18161 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18163 if (Op.getOpcode() == ISD::SRA) {
18164 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18165 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18166 SmallVector<SDValue, 32> V(NumElts,
18167 DAG.getConstant(128 >> ShiftAmt, dl,
18169 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18170 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18171 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18174 llvm_unreachable("Unknown shift opcode.");
18179 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18180 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18181 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18183 // Peek through any splat that was introduced for i64 shift vectorization.
18184 int SplatIndex = -1;
18185 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18186 if (SVN->isSplat()) {
18187 SplatIndex = SVN->getSplatIndex();
18188 Amt = Amt.getOperand(0);
18189 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18190 "Splat shuffle referencing second operand");
18193 if (Amt.getOpcode() != ISD::BITCAST ||
18194 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18197 Amt = Amt.getOperand(0);
18198 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18199 VT.getVectorNumElements();
18200 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18201 uint64_t ShiftAmt = 0;
18202 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18203 for (unsigned i = 0; i != Ratio; ++i) {
18204 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18208 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18211 // Check remaining shift amounts (if not a splat).
18212 if (SplatIndex < 0) {
18213 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18214 uint64_t ShAmt = 0;
18215 for (unsigned j = 0; j != Ratio; ++j) {
18216 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18220 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18222 if (ShAmt != ShiftAmt)
18227 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18228 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18230 if (Op.getOpcode() == ISD::SRA)
18231 return ArithmeticShiftRight64(ShiftAmt);
18237 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18238 const X86Subtarget* Subtarget) {
18239 MVT VT = Op.getSimpleValueType();
18241 SDValue R = Op.getOperand(0);
18242 SDValue Amt = Op.getOperand(1);
18244 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18245 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18247 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18248 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18250 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18252 MVT EltVT = VT.getVectorElementType();
18254 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18255 // Check if this build_vector node is doing a splat.
18256 // If so, then set BaseShAmt equal to the splat value.
18257 BaseShAmt = BV->getSplatValue();
18258 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18259 BaseShAmt = SDValue();
18261 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18262 Amt = Amt.getOperand(0);
18264 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18265 if (SVN && SVN->isSplat()) {
18266 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18267 SDValue InVec = Amt.getOperand(0);
18268 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18269 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18270 "Unexpected shuffle index found!");
18271 BaseShAmt = InVec.getOperand(SplatIdx);
18272 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18273 if (ConstantSDNode *C =
18274 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18275 if (C->getZExtValue() == SplatIdx)
18276 BaseShAmt = InVec.getOperand(1);
18281 // Avoid introducing an extract element from a shuffle.
18282 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18283 DAG.getIntPtrConstant(SplatIdx, dl));
18287 if (BaseShAmt.getNode()) {
18288 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18289 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18290 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18291 else if (EltVT.bitsLT(MVT::i32))
18292 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18294 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18298 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18299 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18300 Amt.getOpcode() == ISD::BITCAST &&
18301 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18302 Amt = Amt.getOperand(0);
18303 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18304 VT.getVectorNumElements();
18305 std::vector<SDValue> Vals(Ratio);
18306 for (unsigned i = 0; i != Ratio; ++i)
18307 Vals[i] = Amt.getOperand(i);
18308 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18309 for (unsigned j = 0; j != Ratio; ++j)
18310 if (Vals[j] != Amt.getOperand(i + j))
18314 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18315 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18320 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18321 SelectionDAG &DAG) {
18322 MVT VT = Op.getSimpleValueType();
18324 SDValue R = Op.getOperand(0);
18325 SDValue Amt = Op.getOperand(1);
18327 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18328 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18330 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18333 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18336 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18339 // XOP has 128-bit variable logical/arithmetic shifts.
18340 // +ve/-ve Amt = shift left/right.
18341 if (Subtarget->hasXOP() &&
18342 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18343 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18344 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18345 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18346 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18348 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18349 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18350 if (Op.getOpcode() == ISD::SRA)
18351 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18354 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18355 // shifts per-lane and then shuffle the partial results back together.
18356 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18357 // Splat the shift amounts so the scalar shifts above will catch it.
18358 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18359 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18360 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18361 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18362 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18365 // i64 vector arithmetic shift can be emulated with the transform:
18366 // M = lshr(SIGN_BIT, Amt)
18367 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18368 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18369 Op.getOpcode() == ISD::SRA) {
18370 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18371 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18372 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18373 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18374 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18378 // If possible, lower this packed shift into a vector multiply instead of
18379 // expanding it into a sequence of scalar shifts.
18380 // Do this only if the vector shift count is a constant build_vector.
18381 if (Op.getOpcode() == ISD::SHL &&
18382 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18383 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18384 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18385 SmallVector<SDValue, 8> Elts;
18386 MVT SVT = VT.getVectorElementType();
18387 unsigned SVTBits = SVT.getSizeInBits();
18388 APInt One(SVTBits, 1);
18389 unsigned NumElems = VT.getVectorNumElements();
18391 for (unsigned i=0; i !=NumElems; ++i) {
18392 SDValue Op = Amt->getOperand(i);
18393 if (Op->getOpcode() == ISD::UNDEF) {
18394 Elts.push_back(Op);
18398 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18399 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18400 uint64_t ShAmt = C.getZExtValue();
18401 if (ShAmt >= SVTBits) {
18402 Elts.push_back(DAG.getUNDEF(SVT));
18405 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18407 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18408 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18411 // Lower SHL with variable shift amount.
18412 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18413 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18415 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18416 DAG.getConstant(0x3f800000U, dl, VT));
18417 Op = DAG.getBitcast(MVT::v4f32, Op);
18418 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18419 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18422 // If possible, lower this shift as a sequence of two shifts by
18423 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18425 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18427 // Could be rewritten as:
18428 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18430 // The advantage is that the two shifts from the example would be
18431 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18432 // the vector shift into four scalar shifts plus four pairs of vector
18434 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18435 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18436 unsigned TargetOpcode = X86ISD::MOVSS;
18437 bool CanBeSimplified;
18438 // The splat value for the first packed shift (the 'X' from the example).
18439 SDValue Amt1 = Amt->getOperand(0);
18440 // The splat value for the second packed shift (the 'Y' from the example).
18441 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18442 Amt->getOperand(2);
18444 // See if it is possible to replace this node with a sequence of
18445 // two shifts followed by a MOVSS/MOVSD
18446 if (VT == MVT::v4i32) {
18447 // Check if it is legal to use a MOVSS.
18448 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18449 Amt2 == Amt->getOperand(3);
18450 if (!CanBeSimplified) {
18451 // Otherwise, check if we can still simplify this node using a MOVSD.
18452 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18453 Amt->getOperand(2) == Amt->getOperand(3);
18454 TargetOpcode = X86ISD::MOVSD;
18455 Amt2 = Amt->getOperand(2);
18458 // Do similar checks for the case where the machine value type
18460 CanBeSimplified = Amt1 == Amt->getOperand(1);
18461 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18462 CanBeSimplified = Amt2 == Amt->getOperand(i);
18464 if (!CanBeSimplified) {
18465 TargetOpcode = X86ISD::MOVSD;
18466 CanBeSimplified = true;
18467 Amt2 = Amt->getOperand(4);
18468 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18469 CanBeSimplified = Amt1 == Amt->getOperand(i);
18470 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18471 CanBeSimplified = Amt2 == Amt->getOperand(j);
18475 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18476 isa<ConstantSDNode>(Amt2)) {
18477 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18478 MVT CastVT = MVT::v4i32;
18480 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18481 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18483 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18484 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18485 if (TargetOpcode == X86ISD::MOVSD)
18486 CastVT = MVT::v2i64;
18487 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18488 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18489 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18491 return DAG.getBitcast(VT, Result);
18495 // v4i32 Non Uniform Shifts.
18496 // If the shift amount is constant we can shift each lane using the SSE2
18497 // immediate shifts, else we need to zero-extend each lane to the lower i64
18498 // and shift using the SSE2 variable shifts.
18499 // The separate results can then be blended together.
18500 if (VT == MVT::v4i32) {
18501 unsigned Opc = Op.getOpcode();
18502 SDValue Amt0, Amt1, Amt2, Amt3;
18503 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18504 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18505 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18506 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18507 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18509 // ISD::SHL is handled above but we include it here for completeness.
18512 llvm_unreachable("Unknown target vector shift node");
18514 Opc = X86ISD::VSHL;
18517 Opc = X86ISD::VSRL;
18520 Opc = X86ISD::VSRA;
18523 // The SSE2 shifts use the lower i64 as the same shift amount for
18524 // all lanes and the upper i64 is ignored. These shuffle masks
18525 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18526 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18527 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18528 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18529 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18530 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18533 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18534 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18535 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18536 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18537 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18538 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18539 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18542 if (VT == MVT::v16i8 ||
18543 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18544 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18545 unsigned ShiftOpcode = Op->getOpcode();
18547 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18548 // On SSE41 targets we make use of the fact that VSELECT lowers
18549 // to PBLENDVB which selects bytes based just on the sign bit.
18550 if (Subtarget->hasSSE41()) {
18551 V0 = DAG.getBitcast(VT, V0);
18552 V1 = DAG.getBitcast(VT, V1);
18553 Sel = DAG.getBitcast(VT, Sel);
18554 return DAG.getBitcast(SelVT,
18555 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18557 // On pre-SSE41 targets we test for the sign bit by comparing to
18558 // zero - a negative value will set all bits of the lanes to true
18559 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18560 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18561 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18562 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18565 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18566 // We can safely do this using i16 shifts as we're only interested in
18567 // the 3 lower bits of each byte.
18568 Amt = DAG.getBitcast(ExtVT, Amt);
18569 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18570 Amt = DAG.getBitcast(VT, Amt);
18572 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18573 // r = VSELECT(r, shift(r, 4), a);
18575 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18576 R = SignBitSelect(VT, Amt, M, R);
18579 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18581 // r = VSELECT(r, shift(r, 2), a);
18582 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18583 R = SignBitSelect(VT, Amt, M, R);
18586 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18588 // return VSELECT(r, shift(r, 1), a);
18589 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18590 R = SignBitSelect(VT, Amt, M, R);
18594 if (Op->getOpcode() == ISD::SRA) {
18595 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18596 // so we can correctly sign extend. We don't care what happens to the
18598 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18599 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18600 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18601 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18602 ALo = DAG.getBitcast(ExtVT, ALo);
18603 AHi = DAG.getBitcast(ExtVT, AHi);
18604 RLo = DAG.getBitcast(ExtVT, RLo);
18605 RHi = DAG.getBitcast(ExtVT, RHi);
18607 // r = VSELECT(r, shift(r, 4), a);
18608 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18609 DAG.getConstant(4, dl, ExtVT));
18610 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18611 DAG.getConstant(4, dl, ExtVT));
18612 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18613 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18616 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18617 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18619 // r = VSELECT(r, shift(r, 2), a);
18620 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18621 DAG.getConstant(2, dl, ExtVT));
18622 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18623 DAG.getConstant(2, dl, ExtVT));
18624 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18625 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18628 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18629 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18631 // r = VSELECT(r, shift(r, 1), a);
18632 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18633 DAG.getConstant(1, dl, ExtVT));
18634 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18635 DAG.getConstant(1, dl, ExtVT));
18636 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18637 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18639 // Logical shift the result back to the lower byte, leaving a zero upper
18641 // meaning that we can safely pack with PACKUSWB.
18643 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18645 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18646 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18650 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18651 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18652 // solution better.
18653 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18654 MVT ExtVT = MVT::v8i32;
18656 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18657 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18658 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18659 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18660 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18663 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18664 MVT ExtVT = MVT::v8i32;
18665 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18666 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18667 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18668 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18669 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18670 ALo = DAG.getBitcast(ExtVT, ALo);
18671 AHi = DAG.getBitcast(ExtVT, AHi);
18672 RLo = DAG.getBitcast(ExtVT, RLo);
18673 RHi = DAG.getBitcast(ExtVT, RHi);
18674 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18675 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18676 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18677 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18678 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18681 if (VT == MVT::v8i16) {
18682 unsigned ShiftOpcode = Op->getOpcode();
18684 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18685 // On SSE41 targets we make use of the fact that VSELECT lowers
18686 // to PBLENDVB which selects bytes based just on the sign bit.
18687 if (Subtarget->hasSSE41()) {
18688 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18689 V0 = DAG.getBitcast(ExtVT, V0);
18690 V1 = DAG.getBitcast(ExtVT, V1);
18691 Sel = DAG.getBitcast(ExtVT, Sel);
18692 return DAG.getBitcast(
18693 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18695 // On pre-SSE41 targets we splat the sign bit - a negative value will
18696 // set all bits of the lanes to true and VSELECT uses that in
18697 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18699 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18700 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18703 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18704 if (Subtarget->hasSSE41()) {
18705 // On SSE41 targets we need to replicate the shift mask in both
18706 // bytes for PBLENDVB.
18709 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18710 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18712 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18715 // r = VSELECT(r, shift(r, 8), a);
18716 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18717 R = SignBitSelect(Amt, M, R);
18720 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18722 // r = VSELECT(r, shift(r, 4), a);
18723 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18724 R = SignBitSelect(Amt, M, R);
18727 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18729 // r = VSELECT(r, shift(r, 2), a);
18730 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18731 R = SignBitSelect(Amt, M, R);
18734 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18736 // return VSELECT(r, shift(r, 1), a);
18737 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18738 R = SignBitSelect(Amt, M, R);
18742 // Decompose 256-bit shifts into smaller 128-bit shifts.
18743 if (VT.is256BitVector()) {
18744 unsigned NumElems = VT.getVectorNumElements();
18745 MVT EltVT = VT.getVectorElementType();
18746 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18748 // Extract the two vectors
18749 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18750 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18752 // Recreate the shift amount vectors
18753 SDValue Amt1, Amt2;
18754 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18755 // Constant shift amount
18756 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18757 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18758 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18760 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18761 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18763 // Variable shift amount
18764 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18765 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18768 // Issue new vector shifts for the smaller types
18769 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18770 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18772 // Concatenate the result back
18773 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18779 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18780 SelectionDAG &DAG) {
18781 MVT VT = Op.getSimpleValueType();
18783 SDValue R = Op.getOperand(0);
18784 SDValue Amt = Op.getOperand(1);
18786 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18787 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18788 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18790 // XOP has 128-bit vector variable + immediate rotates.
18791 // +ve/-ve Amt = rotate left/right.
18793 // Split 256-bit integers.
18794 if (VT.is256BitVector())
18795 return Lower256IntArith(Op, DAG);
18797 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18799 // Attempt to rotate by immediate.
18800 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18801 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18802 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18803 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18804 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18805 DAG.getConstant(RotateAmt, DL, MVT::i8));
18809 // Use general rotate by variable (per-element).
18810 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18813 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18814 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18815 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18816 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18817 // has only one use.
18818 SDNode *N = Op.getNode();
18819 SDValue LHS = N->getOperand(0);
18820 SDValue RHS = N->getOperand(1);
18821 unsigned BaseOp = 0;
18824 switch (Op.getOpcode()) {
18825 default: llvm_unreachable("Unknown ovf instruction!");
18827 // A subtract of one will be selected as a INC. Note that INC doesn't
18828 // set CF, so we can't do this for UADDO.
18829 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18831 BaseOp = X86ISD::INC;
18832 Cond = X86::COND_O;
18835 BaseOp = X86ISD::ADD;
18836 Cond = X86::COND_O;
18839 BaseOp = X86ISD::ADD;
18840 Cond = X86::COND_B;
18843 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18844 // set CF, so we can't do this for USUBO.
18845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18847 BaseOp = X86ISD::DEC;
18848 Cond = X86::COND_O;
18851 BaseOp = X86ISD::SUB;
18852 Cond = X86::COND_O;
18855 BaseOp = X86ISD::SUB;
18856 Cond = X86::COND_B;
18859 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18860 Cond = X86::COND_O;
18862 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18863 if (N->getValueType(0) == MVT::i8) {
18864 BaseOp = X86ISD::UMUL8;
18865 Cond = X86::COND_O;
18868 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18870 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18873 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18874 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18875 SDValue(Sum.getNode(), 2));
18877 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18881 // Also sets EFLAGS.
18882 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18883 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18886 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18887 DAG.getConstant(Cond, DL, MVT::i32),
18888 SDValue(Sum.getNode(), 1));
18890 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18893 /// Returns true if the operand type is exactly twice the native width, and
18894 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18895 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18896 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18897 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18898 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18901 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18902 else if (OpWidth == 128)
18903 return Subtarget->hasCmpxchg16b();
18908 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18909 return needsCmpXchgNb(SI->getValueOperand()->getType());
18912 // Note: this turns large loads into lock cmpxchg8b/16b.
18913 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18914 TargetLowering::AtomicExpansionKind
18915 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18916 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18917 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18918 : AtomicExpansionKind::None;
18921 TargetLowering::AtomicExpansionKind
18922 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18923 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18924 Type *MemType = AI->getType();
18926 // If the operand is too big, we must see if cmpxchg8/16b is available
18927 // and default to library calls otherwise.
18928 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18929 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18930 : AtomicExpansionKind::None;
18933 AtomicRMWInst::BinOp Op = AI->getOperation();
18936 llvm_unreachable("Unknown atomic operation");
18937 case AtomicRMWInst::Xchg:
18938 case AtomicRMWInst::Add:
18939 case AtomicRMWInst::Sub:
18940 // It's better to use xadd, xsub or xchg for these in all cases.
18941 return AtomicExpansionKind::None;
18942 case AtomicRMWInst::Or:
18943 case AtomicRMWInst::And:
18944 case AtomicRMWInst::Xor:
18945 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18946 // prefix to a normal instruction for these operations.
18947 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18948 : AtomicExpansionKind::None;
18949 case AtomicRMWInst::Nand:
18950 case AtomicRMWInst::Max:
18951 case AtomicRMWInst::Min:
18952 case AtomicRMWInst::UMax:
18953 case AtomicRMWInst::UMin:
18954 // These always require a non-trivial set of data operations on x86. We must
18955 // use a cmpxchg loop.
18956 return AtomicExpansionKind::CmpXChg;
18960 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18961 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18962 // no-sse2). There isn't any reason to disable it if the target processor
18964 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18968 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18969 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18970 Type *MemType = AI->getType();
18971 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18972 // there is no benefit in turning such RMWs into loads, and it is actually
18973 // harmful as it introduces a mfence.
18974 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18977 auto Builder = IRBuilder<>(AI);
18978 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18979 auto SynchScope = AI->getSynchScope();
18980 // We must restrict the ordering to avoid generating loads with Release or
18981 // ReleaseAcquire orderings.
18982 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18983 auto Ptr = AI->getPointerOperand();
18985 // Before the load we need a fence. Here is an example lifted from
18986 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18989 // x.store(1, relaxed);
18990 // r1 = y.fetch_add(0, release);
18992 // y.fetch_add(42, acquire);
18993 // r2 = x.load(relaxed);
18994 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18995 // lowered to just a load without a fence. A mfence flushes the store buffer,
18996 // making the optimization clearly correct.
18997 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18998 // otherwise, we might be able to be more aggressive on relaxed idempotent
18999 // rmw. In practice, they do not look useful, so we don't try to be
19000 // especially clever.
19001 if (SynchScope == SingleThread)
19002 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19003 // the IR level, so we must wrap it in an intrinsic.
19006 if (!hasMFENCE(*Subtarget))
19007 // FIXME: it might make sense to use a locked operation here but on a
19008 // different cache-line to prevent cache-line bouncing. In practice it
19009 // is probably a small win, and x86 processors without mfence are rare
19010 // enough that we do not bother.
19014 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19015 Builder.CreateCall(MFence, {});
19017 // Finally we can emit the atomic load.
19018 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19019 AI->getType()->getPrimitiveSizeInBits());
19020 Loaded->setAtomic(Order, SynchScope);
19021 AI->replaceAllUsesWith(Loaded);
19022 AI->eraseFromParent();
19026 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19027 SelectionDAG &DAG) {
19029 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19030 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19031 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19032 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19034 // The only fence that needs an instruction is a sequentially-consistent
19035 // cross-thread fence.
19036 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19037 if (hasMFENCE(*Subtarget))
19038 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19040 SDValue Chain = Op.getOperand(0);
19041 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19043 DAG.getRegister(X86::ESP, MVT::i32), // Base
19044 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19045 DAG.getRegister(0, MVT::i32), // Index
19046 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19047 DAG.getRegister(0, MVT::i32), // Segment.
19051 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19052 return SDValue(Res, 0);
19055 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19056 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19059 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19060 SelectionDAG &DAG) {
19061 MVT T = Op.getSimpleValueType();
19065 switch(T.SimpleTy) {
19066 default: llvm_unreachable("Invalid value type!");
19067 case MVT::i8: Reg = X86::AL; size = 1; break;
19068 case MVT::i16: Reg = X86::AX; size = 2; break;
19069 case MVT::i32: Reg = X86::EAX; size = 4; break;
19071 assert(Subtarget->is64Bit() && "Node not type legal!");
19072 Reg = X86::RAX; size = 8;
19075 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19076 Op.getOperand(2), SDValue());
19077 SDValue Ops[] = { cpIn.getValue(0),
19080 DAG.getTargetConstant(size, DL, MVT::i8),
19081 cpIn.getValue(1) };
19082 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19083 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19084 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19088 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19089 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19090 MVT::i32, cpOut.getValue(2));
19091 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19092 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19095 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19096 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19097 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19101 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19102 SelectionDAG &DAG) {
19103 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19104 MVT DstVT = Op.getSimpleValueType();
19106 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19107 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19108 if (DstVT != MVT::f64)
19109 // This conversion needs to be expanded.
19112 SDValue InVec = Op->getOperand(0);
19114 unsigned NumElts = SrcVT.getVectorNumElements();
19115 MVT SVT = SrcVT.getVectorElementType();
19117 // Widen the vector in input in the case of MVT::v2i32.
19118 // Example: from MVT::v2i32 to MVT::v4i32.
19119 SmallVector<SDValue, 16> Elts;
19120 for (unsigned i = 0, e = NumElts; i != e; ++i)
19121 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19122 DAG.getIntPtrConstant(i, dl)));
19124 // Explicitly mark the extra elements as Undef.
19125 Elts.append(NumElts, DAG.getUNDEF(SVT));
19127 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19128 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19129 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19130 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19131 DAG.getIntPtrConstant(0, dl));
19134 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19135 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19136 assert((DstVT == MVT::i64 ||
19137 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19138 "Unexpected custom BITCAST");
19139 // i64 <=> MMX conversions are Legal.
19140 if (SrcVT==MVT::i64 && DstVT.isVector())
19142 if (DstVT==MVT::i64 && SrcVT.isVector())
19144 // MMX <=> MMX conversions are Legal.
19145 if (SrcVT.isVector() && DstVT.isVector())
19147 // All other conversions need to be expanded.
19151 /// Compute the horizontal sum of bytes in V for the elements of VT.
19153 /// Requires V to be a byte vector and VT to be an integer vector type with
19154 /// wider elements than V's type. The width of the elements of VT determines
19155 /// how many bytes of V are summed horizontally to produce each element of the
19157 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19158 const X86Subtarget *Subtarget,
19159 SelectionDAG &DAG) {
19161 MVT ByteVecVT = V.getSimpleValueType();
19162 MVT EltVT = VT.getVectorElementType();
19163 int NumElts = VT.getVectorNumElements();
19164 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19165 "Expected value to have byte element type.");
19166 assert(EltVT != MVT::i8 &&
19167 "Horizontal byte sum only makes sense for wider elements!");
19168 unsigned VecSize = VT.getSizeInBits();
19169 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19171 // PSADBW instruction horizontally add all bytes and leave the result in i64
19172 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19173 if (EltVT == MVT::i64) {
19174 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19175 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19176 return DAG.getBitcast(VT, V);
19179 if (EltVT == MVT::i32) {
19180 // We unpack the low half and high half into i32s interleaved with zeros so
19181 // that we can use PSADBW to horizontally sum them. The most useful part of
19182 // this is that it lines up the results of two PSADBW instructions to be
19183 // two v2i64 vectors which concatenated are the 4 population counts. We can
19184 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19185 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19186 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19187 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19189 // Do the horizontal sums into two v2i64s.
19190 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19191 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19192 DAG.getBitcast(ByteVecVT, Low), Zeros);
19193 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19194 DAG.getBitcast(ByteVecVT, High), Zeros);
19196 // Merge them together.
19197 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19198 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19199 DAG.getBitcast(ShortVecVT, Low),
19200 DAG.getBitcast(ShortVecVT, High));
19202 return DAG.getBitcast(VT, V);
19205 // The only element type left is i16.
19206 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19208 // To obtain pop count for each i16 element starting from the pop count for
19209 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19210 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19211 // directly supported.
19212 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19213 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19214 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19215 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19216 DAG.getBitcast(ByteVecVT, V));
19217 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19220 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19221 const X86Subtarget *Subtarget,
19222 SelectionDAG &DAG) {
19223 MVT VT = Op.getSimpleValueType();
19224 MVT EltVT = VT.getVectorElementType();
19225 unsigned VecSize = VT.getSizeInBits();
19227 // Implement a lookup table in register by using an algorithm based on:
19228 // http://wm.ite.pl/articles/sse-popcount.html
19230 // The general idea is that every lower byte nibble in the input vector is an
19231 // index into a in-register pre-computed pop count table. We then split up the
19232 // input vector in two new ones: (1) a vector with only the shifted-right
19233 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19234 // masked out higher ones) for each byte. PSHUB is used separately with both
19235 // to index the in-register table. Next, both are added and the result is a
19236 // i8 vector where each element contains the pop count for input byte.
19238 // To obtain the pop count for elements != i8, we follow up with the same
19239 // approach and use additional tricks as described below.
19241 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19242 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19243 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19244 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19246 int NumByteElts = VecSize / 8;
19247 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19248 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19249 SmallVector<SDValue, 16> LUTVec;
19250 for (int i = 0; i < NumByteElts; ++i)
19251 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19252 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19253 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19254 DAG.getConstant(0x0F, DL, MVT::i8));
19255 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19258 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19259 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19260 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19263 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19265 // The input vector is used as the shuffle mask that index elements into the
19266 // LUT. After counting low and high nibbles, add the vector to obtain the
19267 // final pop count per i8 element.
19268 SDValue HighPopCnt =
19269 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19270 SDValue LowPopCnt =
19271 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19272 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19274 if (EltVT == MVT::i8)
19277 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19280 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19281 const X86Subtarget *Subtarget,
19282 SelectionDAG &DAG) {
19283 MVT VT = Op.getSimpleValueType();
19284 assert(VT.is128BitVector() &&
19285 "Only 128-bit vector bitmath lowering supported.");
19287 int VecSize = VT.getSizeInBits();
19288 MVT EltVT = VT.getVectorElementType();
19289 int Len = EltVT.getSizeInBits();
19291 // This is the vectorized version of the "best" algorithm from
19292 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19293 // with a minor tweak to use a series of adds + shifts instead of vector
19294 // multiplications. Implemented for all integer vector types. We only use
19295 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19296 // much faster, even faster than using native popcnt instructions.
19298 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19299 MVT VT = V.getSimpleValueType();
19300 SmallVector<SDValue, 32> Shifters(
19301 VT.getVectorNumElements(),
19302 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19303 return DAG.getNode(OpCode, DL, VT, V,
19304 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19306 auto GetMask = [&](SDValue V, APInt Mask) {
19307 MVT VT = V.getSimpleValueType();
19308 SmallVector<SDValue, 32> Masks(
19309 VT.getVectorNumElements(),
19310 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19311 return DAG.getNode(ISD::AND, DL, VT, V,
19312 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19315 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19316 // x86, so set the SRL type to have elements at least i16 wide. This is
19317 // correct because all of our SRLs are followed immediately by a mask anyways
19318 // that handles any bits that sneak into the high bits of the byte elements.
19319 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19323 // v = v - ((v >> 1) & 0x55555555...)
19325 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19326 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19327 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19329 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19330 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19331 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19332 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19333 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19335 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19336 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19337 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19338 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19340 // At this point, V contains the byte-wise population count, and we are
19341 // merely doing a horizontal sum if necessary to get the wider element
19343 if (EltVT == MVT::i8)
19346 return LowerHorizontalByteSum(
19347 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19351 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19352 SelectionDAG &DAG) {
19353 MVT VT = Op.getSimpleValueType();
19354 // FIXME: Need to add AVX-512 support here!
19355 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19356 "Unknown CTPOP type to handle");
19357 SDLoc DL(Op.getNode());
19358 SDValue Op0 = Op.getOperand(0);
19360 if (!Subtarget->hasSSSE3()) {
19361 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19362 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19363 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19366 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19367 unsigned NumElems = VT.getVectorNumElements();
19369 // Extract each 128-bit vector, compute pop count and concat the result.
19370 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19371 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19373 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19374 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19375 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19378 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19381 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19382 SelectionDAG &DAG) {
19383 assert(Op.getSimpleValueType().isVector() &&
19384 "We only do custom lowering for vector population count.");
19385 return LowerVectorCTPOP(Op, Subtarget, DAG);
19388 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19389 SDNode *Node = Op.getNode();
19391 EVT T = Node->getValueType(0);
19392 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19393 DAG.getConstant(0, dl, T), Node->getOperand(2));
19394 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19395 cast<AtomicSDNode>(Node)->getMemoryVT(),
19396 Node->getOperand(0),
19397 Node->getOperand(1), negOp,
19398 cast<AtomicSDNode>(Node)->getMemOperand(),
19399 cast<AtomicSDNode>(Node)->getOrdering(),
19400 cast<AtomicSDNode>(Node)->getSynchScope());
19403 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19404 SDNode *Node = Op.getNode();
19406 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19408 // Convert seq_cst store -> xchg
19409 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19410 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19411 // (The only way to get a 16-byte store is cmpxchg16b)
19412 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19413 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19414 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19415 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19416 cast<AtomicSDNode>(Node)->getMemoryVT(),
19417 Node->getOperand(0),
19418 Node->getOperand(1), Node->getOperand(2),
19419 cast<AtomicSDNode>(Node)->getMemOperand(),
19420 cast<AtomicSDNode>(Node)->getOrdering(),
19421 cast<AtomicSDNode>(Node)->getSynchScope());
19422 return Swap.getValue(1);
19424 // Other atomic stores have a simple pattern.
19428 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19429 MVT VT = Op.getNode()->getSimpleValueType(0);
19431 // Let legalize expand this if it isn't a legal type yet.
19432 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19435 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19438 bool ExtraOp = false;
19439 switch (Op.getOpcode()) {
19440 default: llvm_unreachable("Invalid code");
19441 case ISD::ADDC: Opc = X86ISD::ADD; break;
19442 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19443 case ISD::SUBC: Opc = X86ISD::SUB; break;
19444 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19448 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19450 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19451 Op.getOperand(1), Op.getOperand(2));
19454 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19455 SelectionDAG &DAG) {
19456 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19458 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19459 // which returns the values as { float, float } (in XMM0) or
19460 // { double, double } (which is returned in XMM0, XMM1).
19462 SDValue Arg = Op.getOperand(0);
19463 EVT ArgVT = Arg.getValueType();
19464 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19466 TargetLowering::ArgListTy Args;
19467 TargetLowering::ArgListEntry Entry;
19471 Entry.isSExt = false;
19472 Entry.isZExt = false;
19473 Args.push_back(Entry);
19475 bool isF64 = ArgVT == MVT::f64;
19476 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19477 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19478 // the results are returned via SRet in memory.
19479 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19480 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19482 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19484 Type *RetTy = isF64
19485 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19486 : (Type*)VectorType::get(ArgTy, 4);
19488 TargetLowering::CallLoweringInfo CLI(DAG);
19489 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19490 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19492 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19495 // Returned in xmm0 and xmm1.
19496 return CallResult.first;
19498 // Returned in bits 0:31 and 32:64 xmm0.
19499 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19500 CallResult.first, DAG.getIntPtrConstant(0, dl));
19501 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19502 CallResult.first, DAG.getIntPtrConstant(1, dl));
19503 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19504 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19507 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19508 SelectionDAG &DAG) {
19509 assert(Subtarget->hasAVX512() &&
19510 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19512 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19513 MVT VT = N->getValue().getSimpleValueType();
19514 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19517 // X86 scatter kills mask register, so its type should be added to
19518 // the list of return values
19519 if (N->getNumValues() == 1) {
19520 SDValue Index = N->getIndex();
19521 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19522 !Index.getSimpleValueType().is512BitVector())
19523 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19525 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19526 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19527 N->getOperand(3), Index };
19529 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19530 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19531 return SDValue(NewScatter.getNode(), 0);
19536 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19537 SelectionDAG &DAG) {
19538 assert(Subtarget->hasAVX512() &&
19539 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19541 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19542 MVT VT = Op.getSimpleValueType();
19543 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19546 SDValue Index = N->getIndex();
19547 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19548 !Index.getSimpleValueType().is512BitVector()) {
19549 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19550 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19551 N->getOperand(3), Index };
19552 DAG.UpdateNodeOperands(N, Ops);
19557 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19558 SelectionDAG &DAG) const {
19559 // TODO: Eventually, the lowering of these nodes should be informed by or
19560 // deferred to the GC strategy for the function in which they appear. For
19561 // now, however, they must be lowered to something. Since they are logically
19562 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19563 // require special handling for these nodes), lower them as literal NOOPs for
19565 SmallVector<SDValue, 2> Ops;
19567 Ops.push_back(Op.getOperand(0));
19568 if (Op->getGluedNode())
19569 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19572 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19573 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19578 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19579 SelectionDAG &DAG) const {
19580 // TODO: Eventually, the lowering of these nodes should be informed by or
19581 // deferred to the GC strategy for the function in which they appear. For
19582 // now, however, they must be lowered to something. Since they are logically
19583 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19584 // require special handling for these nodes), lower them as literal NOOPs for
19586 SmallVector<SDValue, 2> Ops;
19588 Ops.push_back(Op.getOperand(0));
19589 if (Op->getGluedNode())
19590 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19593 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19594 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19599 /// LowerOperation - Provide custom lowering hooks for some operations.
19601 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19602 switch (Op.getOpcode()) {
19603 default: llvm_unreachable("Should not custom lower this!");
19604 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19605 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19606 return LowerCMP_SWAP(Op, Subtarget, DAG);
19607 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19608 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19609 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19610 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19611 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19612 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19613 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19614 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19615 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19616 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19617 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19618 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19619 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19620 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19621 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19622 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19623 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19624 case ISD::SHL_PARTS:
19625 case ISD::SRA_PARTS:
19626 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19627 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19628 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19629 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19630 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19631 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19632 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19633 case ISD::SIGN_EXTEND_VECTOR_INREG:
19634 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19635 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19636 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19637 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19638 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19640 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19641 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19642 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19643 case ISD::SETCC: return LowerSETCC(Op, DAG);
19644 case ISD::SELECT: return LowerSELECT(Op, DAG);
19645 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19646 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19647 case ISD::VASTART: return LowerVASTART(Op, DAG);
19648 case ISD::VAARG: return LowerVAARG(Op, DAG);
19649 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19650 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19651 case ISD::INTRINSIC_VOID:
19652 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19653 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19654 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19655 case ISD::FRAME_TO_ARGS_OFFSET:
19656 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19657 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19658 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19659 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19660 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19661 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19662 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19663 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19664 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19665 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19667 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19668 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19669 case ISD::UMUL_LOHI:
19670 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19671 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19674 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19680 case ISD::UMULO: return LowerXALUO(Op, DAG);
19681 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19682 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19686 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19687 case ISD::ADD: return LowerADD(Op, DAG);
19688 case ISD::SUB: return LowerSUB(Op, DAG);
19692 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19693 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19694 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19695 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19696 case ISD::GC_TRANSITION_START:
19697 return LowerGC_TRANSITION_START(Op, DAG);
19698 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19702 /// ReplaceNodeResults - Replace a node with an illegal result type
19703 /// with a new node built out of custom code.
19704 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19705 SmallVectorImpl<SDValue>&Results,
19706 SelectionDAG &DAG) const {
19708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19709 switch (N->getOpcode()) {
19711 llvm_unreachable("Do not know how to custom type legalize this operation!");
19712 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19713 case X86ISD::FMINC:
19715 case X86ISD::FMAXC:
19716 case X86ISD::FMAX: {
19717 EVT VT = N->getValueType(0);
19718 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19719 SDValue UNDEF = DAG.getUNDEF(VT);
19720 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19721 N->getOperand(0), UNDEF);
19722 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19723 N->getOperand(1), UNDEF);
19724 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19727 case ISD::SIGN_EXTEND_INREG:
19732 // We don't want to expand or promote these.
19739 case ISD::UDIVREM: {
19740 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19741 Results.push_back(V);
19744 case ISD::FP_TO_SINT:
19745 case ISD::FP_TO_UINT: {
19746 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19748 std::pair<SDValue,SDValue> Vals =
19749 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19750 SDValue FIST = Vals.first, StackSlot = Vals.second;
19751 if (FIST.getNode()) {
19752 EVT VT = N->getValueType(0);
19753 // Return a load from the stack slot.
19754 if (StackSlot.getNode())
19755 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19756 MachinePointerInfo(),
19757 false, false, false, 0));
19759 Results.push_back(FIST);
19763 case ISD::UINT_TO_FP: {
19764 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19765 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19766 N->getValueType(0) != MVT::v2f32)
19768 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19770 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19772 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19773 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19774 DAG.getBitcast(MVT::v2i64, VBias));
19775 Or = DAG.getBitcast(MVT::v2f64, Or);
19776 // TODO: Are there any fast-math-flags to propagate here?
19777 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19778 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19781 case ISD::FP_ROUND: {
19782 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19784 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19785 Results.push_back(V);
19788 case ISD::FP_EXTEND: {
19789 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19790 // No other ValueType for FP_EXTEND should reach this point.
19791 assert(N->getValueType(0) == MVT::v2f32 &&
19792 "Do not know how to legalize this Node");
19795 case ISD::INTRINSIC_W_CHAIN: {
19796 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19798 default : llvm_unreachable("Do not know how to custom type "
19799 "legalize this intrinsic operation!");
19800 case Intrinsic::x86_rdtsc:
19801 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19803 case Intrinsic::x86_rdtscp:
19804 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19806 case Intrinsic::x86_rdpmc:
19807 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19810 case ISD::READCYCLECOUNTER: {
19811 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19814 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19815 EVT T = N->getValueType(0);
19816 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19817 bool Regs64bit = T == MVT::i128;
19818 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19819 SDValue cpInL, cpInH;
19820 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19821 DAG.getConstant(0, dl, HalfT));
19822 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19823 DAG.getConstant(1, dl, HalfT));
19824 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19825 Regs64bit ? X86::RAX : X86::EAX,
19827 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19828 Regs64bit ? X86::RDX : X86::EDX,
19829 cpInH, cpInL.getValue(1));
19830 SDValue swapInL, swapInH;
19831 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19832 DAG.getConstant(0, dl, HalfT));
19833 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19834 DAG.getConstant(1, dl, HalfT));
19835 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19836 Regs64bit ? X86::RBX : X86::EBX,
19837 swapInL, cpInH.getValue(1));
19838 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19839 Regs64bit ? X86::RCX : X86::ECX,
19840 swapInH, swapInL.getValue(1));
19841 SDValue Ops[] = { swapInH.getValue(0),
19843 swapInH.getValue(1) };
19844 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19845 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19846 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19847 X86ISD::LCMPXCHG8_DAG;
19848 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19849 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19850 Regs64bit ? X86::RAX : X86::EAX,
19851 HalfT, Result.getValue(1));
19852 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19853 Regs64bit ? X86::RDX : X86::EDX,
19854 HalfT, cpOutL.getValue(2));
19855 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19857 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19858 MVT::i32, cpOutH.getValue(2));
19860 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19861 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19862 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19864 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19865 Results.push_back(Success);
19866 Results.push_back(EFLAGS.getValue(1));
19869 case ISD::ATOMIC_SWAP:
19870 case ISD::ATOMIC_LOAD_ADD:
19871 case ISD::ATOMIC_LOAD_SUB:
19872 case ISD::ATOMIC_LOAD_AND:
19873 case ISD::ATOMIC_LOAD_OR:
19874 case ISD::ATOMIC_LOAD_XOR:
19875 case ISD::ATOMIC_LOAD_NAND:
19876 case ISD::ATOMIC_LOAD_MIN:
19877 case ISD::ATOMIC_LOAD_MAX:
19878 case ISD::ATOMIC_LOAD_UMIN:
19879 case ISD::ATOMIC_LOAD_UMAX:
19880 case ISD::ATOMIC_LOAD: {
19881 // Delegate to generic TypeLegalization. Situations we can really handle
19882 // should have already been dealt with by AtomicExpandPass.cpp.
19885 case ISD::BITCAST: {
19886 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19887 EVT DstVT = N->getValueType(0);
19888 EVT SrcVT = N->getOperand(0)->getValueType(0);
19890 if (SrcVT != MVT::f64 ||
19891 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19894 unsigned NumElts = DstVT.getVectorNumElements();
19895 EVT SVT = DstVT.getVectorElementType();
19896 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19897 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19898 MVT::v2f64, N->getOperand(0));
19899 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19901 if (ExperimentalVectorWideningLegalization) {
19902 // If we are legalizing vectors by widening, we already have the desired
19903 // legal vector type, just return it.
19904 Results.push_back(ToVecInt);
19908 SmallVector<SDValue, 8> Elts;
19909 for (unsigned i = 0, e = NumElts; i != e; ++i)
19910 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19911 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19913 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19918 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19919 switch ((X86ISD::NodeType)Opcode) {
19920 case X86ISD::FIRST_NUMBER: break;
19921 case X86ISD::BSF: return "X86ISD::BSF";
19922 case X86ISD::BSR: return "X86ISD::BSR";
19923 case X86ISD::SHLD: return "X86ISD::SHLD";
19924 case X86ISD::SHRD: return "X86ISD::SHRD";
19925 case X86ISD::FAND: return "X86ISD::FAND";
19926 case X86ISD::FANDN: return "X86ISD::FANDN";
19927 case X86ISD::FOR: return "X86ISD::FOR";
19928 case X86ISD::FXOR: return "X86ISD::FXOR";
19929 case X86ISD::FILD: return "X86ISD::FILD";
19930 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19931 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19932 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19933 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19934 case X86ISD::FLD: return "X86ISD::FLD";
19935 case X86ISD::FST: return "X86ISD::FST";
19936 case X86ISD::CALL: return "X86ISD::CALL";
19937 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19938 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19939 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19940 case X86ISD::BT: return "X86ISD::BT";
19941 case X86ISD::CMP: return "X86ISD::CMP";
19942 case X86ISD::COMI: return "X86ISD::COMI";
19943 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19944 case X86ISD::CMPM: return "X86ISD::CMPM";
19945 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19946 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19947 case X86ISD::SETCC: return "X86ISD::SETCC";
19948 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19949 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19950 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19951 case X86ISD::CMOV: return "X86ISD::CMOV";
19952 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19953 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19954 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19955 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19956 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19957 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19958 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19959 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19960 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19961 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19962 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19963 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19964 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19965 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19966 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19967 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19968 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19969 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19970 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19971 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19972 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19973 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19974 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19975 case X86ISD::HADD: return "X86ISD::HADD";
19976 case X86ISD::HSUB: return "X86ISD::HSUB";
19977 case X86ISD::FHADD: return "X86ISD::FHADD";
19978 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19979 case X86ISD::ABS: return "X86ISD::ABS";
19980 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19981 case X86ISD::FMAX: return "X86ISD::FMAX";
19982 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19983 case X86ISD::FMIN: return "X86ISD::FMIN";
19984 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19985 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19986 case X86ISD::FMINC: return "X86ISD::FMINC";
19987 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19988 case X86ISD::FRCP: return "X86ISD::FRCP";
19989 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19990 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19991 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19992 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19993 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19994 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19995 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19996 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19997 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19998 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19999 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20000 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20001 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20002 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20003 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20004 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20005 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20006 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20007 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20008 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20009 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20010 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20011 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20012 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20013 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20014 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20015 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20016 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20017 case X86ISD::VSHL: return "X86ISD::VSHL";
20018 case X86ISD::VSRL: return "X86ISD::VSRL";
20019 case X86ISD::VSRA: return "X86ISD::VSRA";
20020 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20021 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20022 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20023 case X86ISD::CMPP: return "X86ISD::CMPP";
20024 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20025 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20026 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20027 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20028 case X86ISD::ADD: return "X86ISD::ADD";
20029 case X86ISD::SUB: return "X86ISD::SUB";
20030 case X86ISD::ADC: return "X86ISD::ADC";
20031 case X86ISD::SBB: return "X86ISD::SBB";
20032 case X86ISD::SMUL: return "X86ISD::SMUL";
20033 case X86ISD::UMUL: return "X86ISD::UMUL";
20034 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20035 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20036 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20037 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20038 case X86ISD::INC: return "X86ISD::INC";
20039 case X86ISD::DEC: return "X86ISD::DEC";
20040 case X86ISD::OR: return "X86ISD::OR";
20041 case X86ISD::XOR: return "X86ISD::XOR";
20042 case X86ISD::AND: return "X86ISD::AND";
20043 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20044 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20045 case X86ISD::PTEST: return "X86ISD::PTEST";
20046 case X86ISD::TESTP: return "X86ISD::TESTP";
20047 case X86ISD::TESTM: return "X86ISD::TESTM";
20048 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20049 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20050 case X86ISD::KTEST: return "X86ISD::KTEST";
20051 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20052 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20053 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20054 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20055 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20056 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20057 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20058 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20059 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20060 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20061 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20062 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20063 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20064 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20065 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20066 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20067 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20068 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20069 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20070 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20071 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20072 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20073 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20074 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20075 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20076 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20077 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20078 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20079 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20080 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20081 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20082 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20083 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20084 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20085 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20086 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20087 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20088 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20089 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20090 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20091 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20092 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20093 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20094 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20095 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20096 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20097 case X86ISD::SAHF: return "X86ISD::SAHF";
20098 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20099 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20100 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20101 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20102 case X86ISD::VPROT: return "X86ISD::VPROT";
20103 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20104 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20105 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20106 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20107 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20108 case X86ISD::FMADD: return "X86ISD::FMADD";
20109 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20110 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20111 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20112 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20113 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20114 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20115 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20116 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20117 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20118 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20119 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20120 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20121 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20122 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20123 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20124 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20125 case X86ISD::XTEST: return "X86ISD::XTEST";
20126 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20127 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20128 case X86ISD::SELECT: return "X86ISD::SELECT";
20129 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20130 case X86ISD::RCP28: return "X86ISD::RCP28";
20131 case X86ISD::EXP2: return "X86ISD::EXP2";
20132 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20133 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20134 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20135 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20136 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20137 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20138 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20139 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20140 case X86ISD::ADDS: return "X86ISD::ADDS";
20141 case X86ISD::SUBS: return "X86ISD::SUBS";
20142 case X86ISD::AVG: return "X86ISD::AVG";
20143 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20144 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20145 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20146 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20147 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20148 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20153 // isLegalAddressingMode - Return true if the addressing mode represented
20154 // by AM is legal for this target, for a load/store of the specified type.
20155 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20156 const AddrMode &AM, Type *Ty,
20157 unsigned AS) const {
20158 // X86 supports extremely general addressing modes.
20159 CodeModel::Model M = getTargetMachine().getCodeModel();
20160 Reloc::Model R = getTargetMachine().getRelocationModel();
20162 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20163 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20168 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20170 // If a reference to this global requires an extra load, we can't fold it.
20171 if (isGlobalStubReference(GVFlags))
20174 // If BaseGV requires a register for the PIC base, we cannot also have a
20175 // BaseReg specified.
20176 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20179 // If lower 4G is not available, then we must use rip-relative addressing.
20180 if ((M != CodeModel::Small || R != Reloc::Static) &&
20181 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20185 switch (AM.Scale) {
20191 // These scales always work.
20196 // These scales are formed with basereg+scalereg. Only accept if there is
20201 default: // Other stuff never works.
20208 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20209 unsigned Bits = Ty->getScalarSizeInBits();
20211 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20212 // particularly cheaper than those without.
20216 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20217 // variable shifts just as cheap as scalar ones.
20218 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20221 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20222 // fully general vector.
20226 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20227 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20229 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20230 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20231 return NumBits1 > NumBits2;
20234 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20235 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20238 if (!isTypeLegal(EVT::getEVT(Ty1)))
20241 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20243 // Assuming the caller doesn't have a zeroext or signext return parameter,
20244 // truncation all the way down to i1 is valid.
20248 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20249 return isInt<32>(Imm);
20252 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20253 // Can also use sub to handle negated immediates.
20254 return isInt<32>(Imm);
20257 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20258 if (!VT1.isInteger() || !VT2.isInteger())
20260 unsigned NumBits1 = VT1.getSizeInBits();
20261 unsigned NumBits2 = VT2.getSizeInBits();
20262 return NumBits1 > NumBits2;
20265 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20266 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20267 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20270 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20271 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20272 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20275 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20276 EVT VT1 = Val.getValueType();
20277 if (isZExtFree(VT1, VT2))
20280 if (Val.getOpcode() != ISD::LOAD)
20283 if (!VT1.isSimple() || !VT1.isInteger() ||
20284 !VT2.isSimple() || !VT2.isInteger())
20287 switch (VT1.getSimpleVT().SimpleTy) {
20292 // X86 has 8, 16, and 32-bit zero-extending loads.
20299 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20302 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20303 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20306 VT = VT.getScalarType();
20308 if (!VT.isSimple())
20311 switch (VT.getSimpleVT().SimpleTy) {
20322 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20323 // i16 instructions are longer (0x66 prefix) and potentially slower.
20324 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20327 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20328 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20329 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20330 /// are assumed to be legal.
20332 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20334 if (!VT.isSimple())
20337 // Not for i1 vectors
20338 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20341 // Very little shuffling can be done for 64-bit vectors right now.
20342 if (VT.getSimpleVT().getSizeInBits() == 64)
20345 // We only care that the types being shuffled are legal. The lowering can
20346 // handle any possible shuffle mask that results.
20347 return isTypeLegal(VT.getSimpleVT());
20351 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20353 // Just delegate to the generic legality, clear masks aren't special.
20354 return isShuffleMaskLegal(Mask, VT);
20357 //===----------------------------------------------------------------------===//
20358 // X86 Scheduler Hooks
20359 //===----------------------------------------------------------------------===//
20361 /// Utility function to emit xbegin specifying the start of an RTM region.
20362 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20363 const TargetInstrInfo *TII) {
20364 DebugLoc DL = MI->getDebugLoc();
20366 const BasicBlock *BB = MBB->getBasicBlock();
20367 MachineFunction::iterator I = ++MBB->getIterator();
20369 // For the v = xbegin(), we generate
20380 MachineBasicBlock *thisMBB = MBB;
20381 MachineFunction *MF = MBB->getParent();
20382 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20383 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20384 MF->insert(I, mainMBB);
20385 MF->insert(I, sinkMBB);
20387 // Transfer the remainder of BB and its successor edges to sinkMBB.
20388 sinkMBB->splice(sinkMBB->begin(), MBB,
20389 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20390 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20394 // # fallthrough to mainMBB
20395 // # abortion to sinkMBB
20396 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20397 thisMBB->addSuccessor(mainMBB);
20398 thisMBB->addSuccessor(sinkMBB);
20402 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20403 mainMBB->addSuccessor(sinkMBB);
20406 // EAX is live into the sinkMBB
20407 sinkMBB->addLiveIn(X86::EAX);
20408 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20409 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20412 MI->eraseFromParent();
20416 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20417 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20418 // in the .td file.
20419 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20420 const TargetInstrInfo *TII) {
20422 switch (MI->getOpcode()) {
20423 default: llvm_unreachable("illegal opcode!");
20424 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20425 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20426 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20427 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20428 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20429 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20430 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20431 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20434 DebugLoc dl = MI->getDebugLoc();
20435 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20437 unsigned NumArgs = MI->getNumOperands();
20438 for (unsigned i = 1; i < NumArgs; ++i) {
20439 MachineOperand &Op = MI->getOperand(i);
20440 if (!(Op.isReg() && Op.isImplicit()))
20441 MIB.addOperand(Op);
20443 if (MI->hasOneMemOperand())
20444 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20446 BuildMI(*BB, MI, dl,
20447 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20448 .addReg(X86::XMM0);
20450 MI->eraseFromParent();
20454 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20455 // defs in an instruction pattern
20456 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20457 const TargetInstrInfo *TII) {
20459 switch (MI->getOpcode()) {
20460 default: llvm_unreachable("illegal opcode!");
20461 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20462 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20463 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20464 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20465 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20466 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20467 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20468 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20471 DebugLoc dl = MI->getDebugLoc();
20472 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20474 unsigned NumArgs = MI->getNumOperands(); // remove the results
20475 for (unsigned i = 1; i < NumArgs; ++i) {
20476 MachineOperand &Op = MI->getOperand(i);
20477 if (!(Op.isReg() && Op.isImplicit()))
20478 MIB.addOperand(Op);
20480 if (MI->hasOneMemOperand())
20481 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20483 BuildMI(*BB, MI, dl,
20484 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20487 MI->eraseFromParent();
20491 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20492 const X86Subtarget *Subtarget) {
20493 DebugLoc dl = MI->getDebugLoc();
20494 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20495 // Address into RAX/EAX, other two args into ECX, EDX.
20496 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20497 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20498 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20499 for (int i = 0; i < X86::AddrNumOperands; ++i)
20500 MIB.addOperand(MI->getOperand(i));
20502 unsigned ValOps = X86::AddrNumOperands;
20503 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20504 .addReg(MI->getOperand(ValOps).getReg());
20505 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20506 .addReg(MI->getOperand(ValOps+1).getReg());
20508 // The instruction doesn't actually take any operands though.
20509 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20511 MI->eraseFromParent(); // The pseudo is gone now.
20515 MachineBasicBlock *
20516 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20517 MachineBasicBlock *MBB) const {
20518 // Emit va_arg instruction on X86-64.
20520 // Operands to this pseudo-instruction:
20521 // 0 ) Output : destination address (reg)
20522 // 1-5) Input : va_list address (addr, i64mem)
20523 // 6 ) ArgSize : Size (in bytes) of vararg type
20524 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20525 // 8 ) Align : Alignment of type
20526 // 9 ) EFLAGS (implicit-def)
20528 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20529 static_assert(X86::AddrNumOperands == 5,
20530 "VAARG_64 assumes 5 address operands");
20532 unsigned DestReg = MI->getOperand(0).getReg();
20533 MachineOperand &Base = MI->getOperand(1);
20534 MachineOperand &Scale = MI->getOperand(2);
20535 MachineOperand &Index = MI->getOperand(3);
20536 MachineOperand &Disp = MI->getOperand(4);
20537 MachineOperand &Segment = MI->getOperand(5);
20538 unsigned ArgSize = MI->getOperand(6).getImm();
20539 unsigned ArgMode = MI->getOperand(7).getImm();
20540 unsigned Align = MI->getOperand(8).getImm();
20542 // Memory Reference
20543 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20544 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20545 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20547 // Machine Information
20548 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20549 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20550 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20551 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20552 DebugLoc DL = MI->getDebugLoc();
20554 // struct va_list {
20557 // i64 overflow_area (address)
20558 // i64 reg_save_area (address)
20560 // sizeof(va_list) = 24
20561 // alignment(va_list) = 8
20563 unsigned TotalNumIntRegs = 6;
20564 unsigned TotalNumXMMRegs = 8;
20565 bool UseGPOffset = (ArgMode == 1);
20566 bool UseFPOffset = (ArgMode == 2);
20567 unsigned MaxOffset = TotalNumIntRegs * 8 +
20568 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20570 /* Align ArgSize to a multiple of 8 */
20571 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20572 bool NeedsAlign = (Align > 8);
20574 MachineBasicBlock *thisMBB = MBB;
20575 MachineBasicBlock *overflowMBB;
20576 MachineBasicBlock *offsetMBB;
20577 MachineBasicBlock *endMBB;
20579 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20580 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20581 unsigned OffsetReg = 0;
20583 if (!UseGPOffset && !UseFPOffset) {
20584 // If we only pull from the overflow region, we don't create a branch.
20585 // We don't need to alter control flow.
20586 OffsetDestReg = 0; // unused
20587 OverflowDestReg = DestReg;
20589 offsetMBB = nullptr;
20590 overflowMBB = thisMBB;
20593 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20594 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20595 // If not, pull from overflow_area. (branch to overflowMBB)
20600 // offsetMBB overflowMBB
20605 // Registers for the PHI in endMBB
20606 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20607 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20609 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20610 MachineFunction *MF = MBB->getParent();
20611 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20612 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20613 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20615 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20617 // Insert the new basic blocks
20618 MF->insert(MBBIter, offsetMBB);
20619 MF->insert(MBBIter, overflowMBB);
20620 MF->insert(MBBIter, endMBB);
20622 // Transfer the remainder of MBB and its successor edges to endMBB.
20623 endMBB->splice(endMBB->begin(), thisMBB,
20624 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20625 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20627 // Make offsetMBB and overflowMBB successors of thisMBB
20628 thisMBB->addSuccessor(offsetMBB);
20629 thisMBB->addSuccessor(overflowMBB);
20631 // endMBB is a successor of both offsetMBB and overflowMBB
20632 offsetMBB->addSuccessor(endMBB);
20633 overflowMBB->addSuccessor(endMBB);
20635 // Load the offset value into a register
20636 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20637 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20641 .addDisp(Disp, UseFPOffset ? 4 : 0)
20642 .addOperand(Segment)
20643 .setMemRefs(MMOBegin, MMOEnd);
20645 // Check if there is enough room left to pull this argument.
20646 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20648 .addImm(MaxOffset + 8 - ArgSizeA8);
20650 // Branch to "overflowMBB" if offset >= max
20651 // Fall through to "offsetMBB" otherwise
20652 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20653 .addMBB(overflowMBB);
20656 // In offsetMBB, emit code to use the reg_save_area.
20658 assert(OffsetReg != 0);
20660 // Read the reg_save_area address.
20661 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20662 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20667 .addOperand(Segment)
20668 .setMemRefs(MMOBegin, MMOEnd);
20670 // Zero-extend the offset
20671 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20672 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20675 .addImm(X86::sub_32bit);
20677 // Add the offset to the reg_save_area to get the final address.
20678 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20679 .addReg(OffsetReg64)
20680 .addReg(RegSaveReg);
20682 // Compute the offset for the next argument
20683 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20684 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20686 .addImm(UseFPOffset ? 16 : 8);
20688 // Store it back into the va_list.
20689 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20693 .addDisp(Disp, UseFPOffset ? 4 : 0)
20694 .addOperand(Segment)
20695 .addReg(NextOffsetReg)
20696 .setMemRefs(MMOBegin, MMOEnd);
20699 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20704 // Emit code to use overflow area
20707 // Load the overflow_area address into a register.
20708 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20709 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20714 .addOperand(Segment)
20715 .setMemRefs(MMOBegin, MMOEnd);
20717 // If we need to align it, do so. Otherwise, just copy the address
20718 // to OverflowDestReg.
20720 // Align the overflow address
20721 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20722 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20724 // aligned_addr = (addr + (align-1)) & ~(align-1)
20725 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20726 .addReg(OverflowAddrReg)
20729 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20731 .addImm(~(uint64_t)(Align-1));
20733 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20734 .addReg(OverflowAddrReg);
20737 // Compute the next overflow address after this argument.
20738 // (the overflow address should be kept 8-byte aligned)
20739 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20740 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20741 .addReg(OverflowDestReg)
20742 .addImm(ArgSizeA8);
20744 // Store the new overflow address.
20745 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20750 .addOperand(Segment)
20751 .addReg(NextAddrReg)
20752 .setMemRefs(MMOBegin, MMOEnd);
20754 // If we branched, emit the PHI to the front of endMBB.
20756 BuildMI(*endMBB, endMBB->begin(), DL,
20757 TII->get(X86::PHI), DestReg)
20758 .addReg(OffsetDestReg).addMBB(offsetMBB)
20759 .addReg(OverflowDestReg).addMBB(overflowMBB);
20762 // Erase the pseudo instruction
20763 MI->eraseFromParent();
20768 MachineBasicBlock *
20769 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20771 MachineBasicBlock *MBB) const {
20772 // Emit code to save XMM registers to the stack. The ABI says that the
20773 // number of registers to save is given in %al, so it's theoretically
20774 // possible to do an indirect jump trick to avoid saving all of them,
20775 // however this code takes a simpler approach and just executes all
20776 // of the stores if %al is non-zero. It's less code, and it's probably
20777 // easier on the hardware branch predictor, and stores aren't all that
20778 // expensive anyway.
20780 // Create the new basic blocks. One block contains all the XMM stores,
20781 // and one block is the final destination regardless of whether any
20782 // stores were performed.
20783 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20784 MachineFunction *F = MBB->getParent();
20785 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20786 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20787 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20788 F->insert(MBBIter, XMMSaveMBB);
20789 F->insert(MBBIter, EndMBB);
20791 // Transfer the remainder of MBB and its successor edges to EndMBB.
20792 EndMBB->splice(EndMBB->begin(), MBB,
20793 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20794 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20796 // The original block will now fall through to the XMM save block.
20797 MBB->addSuccessor(XMMSaveMBB);
20798 // The XMMSaveMBB will fall through to the end block.
20799 XMMSaveMBB->addSuccessor(EndMBB);
20801 // Now add the instructions.
20802 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20803 DebugLoc DL = MI->getDebugLoc();
20805 unsigned CountReg = MI->getOperand(0).getReg();
20806 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20807 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20809 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20810 // If %al is 0, branch around the XMM save block.
20811 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20812 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20813 MBB->addSuccessor(EndMBB);
20816 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20817 // that was just emitted, but clearly shouldn't be "saved".
20818 assert((MI->getNumOperands() <= 3 ||
20819 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20820 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20821 && "Expected last argument to be EFLAGS");
20822 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20823 // In the XMM save block, save all the XMM argument registers.
20824 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20825 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20826 MachineMemOperand *MMO = F->getMachineMemOperand(
20827 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20828 MachineMemOperand::MOStore,
20829 /*Size=*/16, /*Align=*/16);
20830 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20831 .addFrameIndex(RegSaveFrameIndex)
20832 .addImm(/*Scale=*/1)
20833 .addReg(/*IndexReg=*/0)
20834 .addImm(/*Disp=*/Offset)
20835 .addReg(/*Segment=*/0)
20836 .addReg(MI->getOperand(i).getReg())
20837 .addMemOperand(MMO);
20840 MI->eraseFromParent(); // The pseudo instruction is gone now.
20845 // The EFLAGS operand of SelectItr might be missing a kill marker
20846 // because there were multiple uses of EFLAGS, and ISel didn't know
20847 // which to mark. Figure out whether SelectItr should have had a
20848 // kill marker, and set it if it should. Returns the correct kill
20850 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20851 MachineBasicBlock* BB,
20852 const TargetRegisterInfo* TRI) {
20853 // Scan forward through BB for a use/def of EFLAGS.
20854 MachineBasicBlock::iterator miI(std::next(SelectItr));
20855 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20856 const MachineInstr& mi = *miI;
20857 if (mi.readsRegister(X86::EFLAGS))
20859 if (mi.definesRegister(X86::EFLAGS))
20860 break; // Should have kill-flag - update below.
20863 // If we hit the end of the block, check whether EFLAGS is live into a
20865 if (miI == BB->end()) {
20866 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20867 sEnd = BB->succ_end();
20868 sItr != sEnd; ++sItr) {
20869 MachineBasicBlock* succ = *sItr;
20870 if (succ->isLiveIn(X86::EFLAGS))
20875 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20876 // out. SelectMI should have a kill flag on EFLAGS.
20877 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20881 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20882 // together with other CMOV pseudo-opcodes into a single basic-block with
20883 // conditional jump around it.
20884 static bool isCMOVPseudo(MachineInstr *MI) {
20885 switch (MI->getOpcode()) {
20886 case X86::CMOV_FR32:
20887 case X86::CMOV_FR64:
20888 case X86::CMOV_GR8:
20889 case X86::CMOV_GR16:
20890 case X86::CMOV_GR32:
20891 case X86::CMOV_RFP32:
20892 case X86::CMOV_RFP64:
20893 case X86::CMOV_RFP80:
20894 case X86::CMOV_V2F64:
20895 case X86::CMOV_V2I64:
20896 case X86::CMOV_V4F32:
20897 case X86::CMOV_V4F64:
20898 case X86::CMOV_V4I64:
20899 case X86::CMOV_V16F32:
20900 case X86::CMOV_V8F32:
20901 case X86::CMOV_V8F64:
20902 case X86::CMOV_V8I64:
20903 case X86::CMOV_V8I1:
20904 case X86::CMOV_V16I1:
20905 case X86::CMOV_V32I1:
20906 case X86::CMOV_V64I1:
20914 MachineBasicBlock *
20915 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20916 MachineBasicBlock *BB) const {
20917 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20918 DebugLoc DL = MI->getDebugLoc();
20920 // To "insert" a SELECT_CC instruction, we actually have to insert the
20921 // diamond control-flow pattern. The incoming instruction knows the
20922 // destination vreg to set, the condition code register to branch on, the
20923 // true/false values to select between, and a branch opcode to use.
20924 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20925 MachineFunction::iterator It = ++BB->getIterator();
20930 // cmpTY ccX, r1, r2
20932 // fallthrough --> copy0MBB
20933 MachineBasicBlock *thisMBB = BB;
20934 MachineFunction *F = BB->getParent();
20936 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20937 // as described above, by inserting a BB, and then making a PHI at the join
20938 // point to select the true and false operands of the CMOV in the PHI.
20940 // The code also handles two different cases of multiple CMOV opcodes
20944 // In this case, there are multiple CMOVs in a row, all which are based on
20945 // the same condition setting (or the exact opposite condition setting).
20946 // In this case we can lower all the CMOVs using a single inserted BB, and
20947 // then make a number of PHIs at the join point to model the CMOVs. The only
20948 // trickiness here, is that in a case like:
20950 // t2 = CMOV cond1 t1, f1
20951 // t3 = CMOV cond1 t2, f2
20953 // when rewriting this into PHIs, we have to perform some renaming on the
20954 // temps since you cannot have a PHI operand refer to a PHI result earlier
20955 // in the same block. The "simple" but wrong lowering would be:
20957 // t2 = PHI t1(BB1), f1(BB2)
20958 // t3 = PHI t2(BB1), f2(BB2)
20960 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20961 // renaming is to note that on the path through BB1, t2 is really just a
20962 // copy of t1, and do that renaming, properly generating:
20964 // t2 = PHI t1(BB1), f1(BB2)
20965 // t3 = PHI t1(BB1), f2(BB2)
20967 // Case 2, we lower cascaded CMOVs such as
20969 // (CMOV (CMOV F, T, cc1), T, cc2)
20971 // to two successives branches. For that, we look for another CMOV as the
20972 // following instruction.
20974 // Without this, we would add a PHI between the two jumps, which ends up
20975 // creating a few copies all around. For instance, for
20977 // (sitofp (zext (fcmp une)))
20979 // we would generate:
20981 // ucomiss %xmm1, %xmm0
20982 // movss <1.0f>, %xmm0
20983 // movaps %xmm0, %xmm1
20985 // xorps %xmm1, %xmm1
20988 // movaps %xmm1, %xmm0
20992 // because this custom-inserter would have generated:
21004 // A: X = ...; Y = ...
21006 // C: Z = PHI [X, A], [Y, B]
21008 // E: PHI [X, C], [Z, D]
21010 // If we lower both CMOVs in a single step, we can instead generate:
21022 // A: X = ...; Y = ...
21024 // E: PHI [X, A], [X, C], [Y, D]
21026 // Which, in our sitofp/fcmp example, gives us something like:
21028 // ucomiss %xmm1, %xmm0
21029 // movss <1.0f>, %xmm0
21032 // xorps %xmm0, %xmm0
21036 MachineInstr *CascadedCMOV = nullptr;
21037 MachineInstr *LastCMOV = MI;
21038 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21039 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21040 MachineBasicBlock::iterator NextMIIt =
21041 std::next(MachineBasicBlock::iterator(MI));
21043 // Check for case 1, where there are multiple CMOVs with the same condition
21044 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21045 // number of jumps the most.
21047 if (isCMOVPseudo(MI)) {
21048 // See if we have a string of CMOVS with the same condition.
21049 while (NextMIIt != BB->end() &&
21050 isCMOVPseudo(NextMIIt) &&
21051 (NextMIIt->getOperand(3).getImm() == CC ||
21052 NextMIIt->getOperand(3).getImm() == OppCC)) {
21053 LastCMOV = &*NextMIIt;
21058 // This checks for case 2, but only do this if we didn't already find
21059 // case 1, as indicated by LastCMOV == MI.
21060 if (LastCMOV == MI &&
21061 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21062 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21063 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21064 CascadedCMOV = &*NextMIIt;
21067 MachineBasicBlock *jcc1MBB = nullptr;
21069 // If we have a cascaded CMOV, we lower it to two successive branches to
21070 // the same block. EFLAGS is used by both, so mark it as live in the second.
21071 if (CascadedCMOV) {
21072 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21073 F->insert(It, jcc1MBB);
21074 jcc1MBB->addLiveIn(X86::EFLAGS);
21077 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21078 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21079 F->insert(It, copy0MBB);
21080 F->insert(It, sinkMBB);
21082 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21083 // live into the sink and copy blocks.
21084 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21086 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21087 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21088 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21089 copy0MBB->addLiveIn(X86::EFLAGS);
21090 sinkMBB->addLiveIn(X86::EFLAGS);
21093 // Transfer the remainder of BB and its successor edges to sinkMBB.
21094 sinkMBB->splice(sinkMBB->begin(), BB,
21095 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21096 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21098 // Add the true and fallthrough blocks as its successors.
21099 if (CascadedCMOV) {
21100 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21101 BB->addSuccessor(jcc1MBB);
21103 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21104 // jump to the sinkMBB.
21105 jcc1MBB->addSuccessor(copy0MBB);
21106 jcc1MBB->addSuccessor(sinkMBB);
21108 BB->addSuccessor(copy0MBB);
21111 // The true block target of the first (or only) branch is always sinkMBB.
21112 BB->addSuccessor(sinkMBB);
21114 // Create the conditional branch instruction.
21115 unsigned Opc = X86::GetCondBranchFromCond(CC);
21116 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21118 if (CascadedCMOV) {
21119 unsigned Opc2 = X86::GetCondBranchFromCond(
21120 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21121 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21125 // %FalseValue = ...
21126 // # fallthrough to sinkMBB
21127 copy0MBB->addSuccessor(sinkMBB);
21130 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21132 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21133 MachineBasicBlock::iterator MIItEnd =
21134 std::next(MachineBasicBlock::iterator(LastCMOV));
21135 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21136 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21137 MachineInstrBuilder MIB;
21139 // As we are creating the PHIs, we have to be careful if there is more than
21140 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21141 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21142 // That also means that PHI construction must work forward from earlier to
21143 // later, and that the code must maintain a mapping from earlier PHI's
21144 // destination registers, and the registers that went into the PHI.
21146 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21147 unsigned DestReg = MIIt->getOperand(0).getReg();
21148 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21149 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21151 // If this CMOV we are generating is the opposite condition from
21152 // the jump we generated, then we have to swap the operands for the
21153 // PHI that is going to be generated.
21154 if (MIIt->getOperand(3).getImm() == OppCC)
21155 std::swap(Op1Reg, Op2Reg);
21157 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21158 Op1Reg = RegRewriteTable[Op1Reg].first;
21160 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21161 Op2Reg = RegRewriteTable[Op2Reg].second;
21163 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21164 TII->get(X86::PHI), DestReg)
21165 .addReg(Op1Reg).addMBB(copy0MBB)
21166 .addReg(Op2Reg).addMBB(thisMBB);
21168 // Add this PHI to the rewrite table.
21169 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21172 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21173 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21174 if (CascadedCMOV) {
21175 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21176 // Copy the PHI result to the register defined by the second CMOV.
21177 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21178 DL, TII->get(TargetOpcode::COPY),
21179 CascadedCMOV->getOperand(0).getReg())
21180 .addReg(MI->getOperand(0).getReg());
21181 CascadedCMOV->eraseFromParent();
21184 // Now remove the CMOV(s).
21185 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21186 (MIIt++)->eraseFromParent();
21191 MachineBasicBlock *
21192 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21193 MachineBasicBlock *BB) const {
21194 // Combine the following atomic floating-point modification pattern:
21195 // a.store(reg OP a.load(acquire), release)
21196 // Transform them into:
21197 // OPss (%gpr), %xmm
21198 // movss %xmm, (%gpr)
21199 // Or sd equivalent for 64-bit operations.
21201 switch (MI->getOpcode()) {
21202 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21203 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21204 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21206 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21207 DebugLoc DL = MI->getDebugLoc();
21208 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21209 MachineOperand MSrc = MI->getOperand(0);
21210 unsigned VSrc = MI->getOperand(5).getReg();
21211 const MachineOperand &Disp = MI->getOperand(3);
21212 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21213 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21214 if (hasDisp && MSrc.isReg())
21215 MSrc.setIsKill(false);
21216 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21217 .addOperand(/*Base=*/MSrc)
21218 .addImm(/*Scale=*/1)
21219 .addReg(/*Index=*/0)
21220 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21222 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21223 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21225 .addOperand(/*Base=*/MSrc)
21226 .addImm(/*Scale=*/1)
21227 .addReg(/*Index=*/0)
21228 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21229 .addReg(/*Segment=*/0);
21230 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21231 MI->eraseFromParent(); // The pseudo instruction is gone now.
21235 MachineBasicBlock *
21236 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21237 MachineBasicBlock *BB) const {
21238 MachineFunction *MF = BB->getParent();
21239 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21240 DebugLoc DL = MI->getDebugLoc();
21241 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21243 assert(MF->shouldSplitStack());
21245 const bool Is64Bit = Subtarget->is64Bit();
21246 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21248 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21249 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21252 // ... [Till the alloca]
21253 // If stacklet is not large enough, jump to mallocMBB
21256 // Allocate by subtracting from RSP
21257 // Jump to continueMBB
21260 // Allocate by call to runtime
21264 // [rest of original BB]
21267 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21268 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21269 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21271 MachineRegisterInfo &MRI = MF->getRegInfo();
21272 const TargetRegisterClass *AddrRegClass =
21273 getRegClassFor(getPointerTy(MF->getDataLayout()));
21275 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21276 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21277 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21278 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21279 sizeVReg = MI->getOperand(1).getReg(),
21280 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21282 MachineFunction::iterator MBBIter = ++BB->getIterator();
21284 MF->insert(MBBIter, bumpMBB);
21285 MF->insert(MBBIter, mallocMBB);
21286 MF->insert(MBBIter, continueMBB);
21288 continueMBB->splice(continueMBB->begin(), BB,
21289 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21290 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21292 // Add code to the main basic block to check if the stack limit has been hit,
21293 // and if so, jump to mallocMBB otherwise to bumpMBB.
21294 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21295 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21296 .addReg(tmpSPVReg).addReg(sizeVReg);
21297 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21298 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21299 .addReg(SPLimitVReg);
21300 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21302 // bumpMBB simply decreases the stack pointer, since we know the current
21303 // stacklet has enough space.
21304 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21305 .addReg(SPLimitVReg);
21306 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21307 .addReg(SPLimitVReg);
21308 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21310 // Calls into a routine in libgcc to allocate more space from the heap.
21311 const uint32_t *RegMask =
21312 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21314 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21316 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21317 .addExternalSymbol("__morestack_allocate_stack_space")
21318 .addRegMask(RegMask)
21319 .addReg(X86::RDI, RegState::Implicit)
21320 .addReg(X86::RAX, RegState::ImplicitDefine);
21321 } else if (Is64Bit) {
21322 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21324 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21325 .addExternalSymbol("__morestack_allocate_stack_space")
21326 .addRegMask(RegMask)
21327 .addReg(X86::EDI, RegState::Implicit)
21328 .addReg(X86::EAX, RegState::ImplicitDefine);
21330 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21332 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21333 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21334 .addExternalSymbol("__morestack_allocate_stack_space")
21335 .addRegMask(RegMask)
21336 .addReg(X86::EAX, RegState::ImplicitDefine);
21340 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21343 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21344 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21345 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21347 // Set up the CFG correctly.
21348 BB->addSuccessor(bumpMBB);
21349 BB->addSuccessor(mallocMBB);
21350 mallocMBB->addSuccessor(continueMBB);
21351 bumpMBB->addSuccessor(continueMBB);
21353 // Take care of the PHI nodes.
21354 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21355 MI->getOperand(0).getReg())
21356 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21357 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21359 // Delete the original pseudo instruction.
21360 MI->eraseFromParent();
21363 return continueMBB;
21366 MachineBasicBlock *
21367 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21368 MachineBasicBlock *BB) const {
21369 DebugLoc DL = MI->getDebugLoc();
21371 assert(!Subtarget->isTargetMachO());
21373 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21376 MI->eraseFromParent(); // The pseudo instruction is gone now.
21380 MachineBasicBlock *
21381 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21382 MachineBasicBlock *BB) const {
21383 MachineFunction *MF = BB->getParent();
21384 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21385 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21386 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21387 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21388 DebugLoc DL = MI->getDebugLoc();
21390 // SEH does not outline catch bodies into funclets. Turn CATCHRETs into
21391 // JMP_4s, possibly with some extra restoration code for 32-bit EH.
21393 if (Subtarget->is32Bit())
21394 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21395 BuildMI(*BB, MI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21396 MI->eraseFromParent();
21400 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21401 if (!Subtarget->is32Bit())
21404 // C++ EH creates a new target block to hold the restore code, and wires up
21405 // the new block to the return destination with a normal JMP_4.
21406 MachineBasicBlock *RestoreMBB =
21407 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21408 MF->insert(TargetMBB->getIterator(), RestoreMBB);
21409 BB->removeSuccessor(TargetMBB);
21410 BB->addSuccessor(RestoreMBB);
21411 RestoreMBB->addSuccessor(TargetMBB);
21412 MI->getOperand(0).setMBB(RestoreMBB);
21414 auto RestoreMBBI = RestoreMBB->begin();
21415 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21416 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21420 MachineBasicBlock *
21421 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21422 MachineBasicBlock *BB) const {
21423 // This is pretty easy. We're taking the value that we received from
21424 // our load from the relocation, sticking it in either RDI (x86-64)
21425 // or EAX and doing an indirect call. The return value will then
21426 // be in the normal return register.
21427 MachineFunction *F = BB->getParent();
21428 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21429 DebugLoc DL = MI->getDebugLoc();
21431 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21432 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21434 // Get a register mask for the lowered call.
21435 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21436 // proper register mask.
21437 const uint32_t *RegMask =
21438 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21439 if (Subtarget->is64Bit()) {
21440 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21441 TII->get(X86::MOV64rm), X86::RDI)
21443 .addImm(0).addReg(0)
21444 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21445 MI->getOperand(3).getTargetFlags())
21447 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21448 addDirectMem(MIB, X86::RDI);
21449 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21450 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21451 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21452 TII->get(X86::MOV32rm), X86::EAX)
21454 .addImm(0).addReg(0)
21455 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21456 MI->getOperand(3).getTargetFlags())
21458 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21459 addDirectMem(MIB, X86::EAX);
21460 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21462 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21463 TII->get(X86::MOV32rm), X86::EAX)
21464 .addReg(TII->getGlobalBaseReg(F))
21465 .addImm(0).addReg(0)
21466 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21467 MI->getOperand(3).getTargetFlags())
21469 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21470 addDirectMem(MIB, X86::EAX);
21471 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21474 MI->eraseFromParent(); // The pseudo instruction is gone now.
21478 MachineBasicBlock *
21479 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21480 MachineBasicBlock *MBB) const {
21481 DebugLoc DL = MI->getDebugLoc();
21482 MachineFunction *MF = MBB->getParent();
21483 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21484 MachineRegisterInfo &MRI = MF->getRegInfo();
21486 const BasicBlock *BB = MBB->getBasicBlock();
21487 MachineFunction::iterator I = ++MBB->getIterator();
21489 // Memory Reference
21490 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21491 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21494 unsigned MemOpndSlot = 0;
21496 unsigned CurOp = 0;
21498 DstReg = MI->getOperand(CurOp++).getReg();
21499 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21500 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21501 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21502 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21504 MemOpndSlot = CurOp;
21506 MVT PVT = getPointerTy(MF->getDataLayout());
21507 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21508 "Invalid Pointer Size!");
21510 // For v = setjmp(buf), we generate
21513 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21514 // SjLjSetup restoreMBB
21520 // v = phi(main, restore)
21523 // if base pointer being used, load it from frame
21526 MachineBasicBlock *thisMBB = MBB;
21527 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21528 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21529 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21530 MF->insert(I, mainMBB);
21531 MF->insert(I, sinkMBB);
21532 MF->push_back(restoreMBB);
21533 restoreMBB->setHasAddressTaken();
21535 MachineInstrBuilder MIB;
21537 // Transfer the remainder of BB and its successor edges to sinkMBB.
21538 sinkMBB->splice(sinkMBB->begin(), MBB,
21539 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21540 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21543 unsigned PtrStoreOpc = 0;
21544 unsigned LabelReg = 0;
21545 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21546 Reloc::Model RM = MF->getTarget().getRelocationModel();
21547 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21548 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21550 // Prepare IP either in reg or imm.
21551 if (!UseImmLabel) {
21552 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21553 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21554 LabelReg = MRI.createVirtualRegister(PtrRC);
21555 if (Subtarget->is64Bit()) {
21556 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21560 .addMBB(restoreMBB)
21563 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21564 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21565 .addReg(XII->getGlobalBaseReg(MF))
21568 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21572 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21574 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21575 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21576 if (i == X86::AddrDisp)
21577 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21579 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21582 MIB.addReg(LabelReg);
21584 MIB.addMBB(restoreMBB);
21585 MIB.setMemRefs(MMOBegin, MMOEnd);
21587 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21588 .addMBB(restoreMBB);
21590 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21591 MIB.addRegMask(RegInfo->getNoPreservedMask());
21592 thisMBB->addSuccessor(mainMBB);
21593 thisMBB->addSuccessor(restoreMBB);
21597 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21598 mainMBB->addSuccessor(sinkMBB);
21601 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21602 TII->get(X86::PHI), DstReg)
21603 .addReg(mainDstReg).addMBB(mainMBB)
21604 .addReg(restoreDstReg).addMBB(restoreMBB);
21607 if (RegInfo->hasBasePointer(*MF)) {
21608 const bool Uses64BitFramePtr =
21609 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21610 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21611 X86FI->setRestoreBasePointer(MF);
21612 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21613 unsigned BasePtr = RegInfo->getBaseRegister();
21614 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21615 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21616 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21617 .setMIFlag(MachineInstr::FrameSetup);
21619 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21620 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21621 restoreMBB->addSuccessor(sinkMBB);
21623 MI->eraseFromParent();
21627 MachineBasicBlock *
21628 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21629 MachineBasicBlock *MBB) const {
21630 DebugLoc DL = MI->getDebugLoc();
21631 MachineFunction *MF = MBB->getParent();
21632 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21633 MachineRegisterInfo &MRI = MF->getRegInfo();
21635 // Memory Reference
21636 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21637 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21639 MVT PVT = getPointerTy(MF->getDataLayout());
21640 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21641 "Invalid Pointer Size!");
21643 const TargetRegisterClass *RC =
21644 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21645 unsigned Tmp = MRI.createVirtualRegister(RC);
21646 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21647 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21648 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21649 unsigned SP = RegInfo->getStackRegister();
21651 MachineInstrBuilder MIB;
21653 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21654 const int64_t SPOffset = 2 * PVT.getStoreSize();
21656 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21657 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21660 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21661 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21662 MIB.addOperand(MI->getOperand(i));
21663 MIB.setMemRefs(MMOBegin, MMOEnd);
21665 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21666 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21667 if (i == X86::AddrDisp)
21668 MIB.addDisp(MI->getOperand(i), LabelOffset);
21670 MIB.addOperand(MI->getOperand(i));
21672 MIB.setMemRefs(MMOBegin, MMOEnd);
21674 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21675 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21676 if (i == X86::AddrDisp)
21677 MIB.addDisp(MI->getOperand(i), SPOffset);
21679 MIB.addOperand(MI->getOperand(i));
21681 MIB.setMemRefs(MMOBegin, MMOEnd);
21683 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21685 MI->eraseFromParent();
21689 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21690 // accumulator loops. Writing back to the accumulator allows the coalescer
21691 // to remove extra copies in the loop.
21692 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21693 MachineBasicBlock *
21694 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21695 MachineBasicBlock *MBB) const {
21696 MachineOperand &AddendOp = MI->getOperand(3);
21698 // Bail out early if the addend isn't a register - we can't switch these.
21699 if (!AddendOp.isReg())
21702 MachineFunction &MF = *MBB->getParent();
21703 MachineRegisterInfo &MRI = MF.getRegInfo();
21705 // Check whether the addend is defined by a PHI:
21706 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21707 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21708 if (!AddendDef.isPHI())
21711 // Look for the following pattern:
21713 // %addend = phi [%entry, 0], [%loop, %result]
21715 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21719 // %addend = phi [%entry, 0], [%loop, %result]
21721 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21723 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21724 assert(AddendDef.getOperand(i).isReg());
21725 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21726 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21727 if (&PHISrcInst == MI) {
21728 // Found a matching instruction.
21729 unsigned NewFMAOpc = 0;
21730 switch (MI->getOpcode()) {
21731 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21732 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21733 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21734 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21735 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21736 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21737 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21738 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21739 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21740 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21741 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21742 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21743 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21744 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21745 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21746 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21747 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21748 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21749 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21750 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21752 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21753 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21754 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21755 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21756 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21757 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21758 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21759 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21760 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21761 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21762 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21763 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21764 default: llvm_unreachable("Unrecognized FMA variant.");
21767 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21768 MachineInstrBuilder MIB =
21769 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21770 .addOperand(MI->getOperand(0))
21771 .addOperand(MI->getOperand(3))
21772 .addOperand(MI->getOperand(2))
21773 .addOperand(MI->getOperand(1));
21774 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21775 MI->eraseFromParent();
21782 MachineBasicBlock *
21783 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21784 MachineBasicBlock *BB) const {
21785 switch (MI->getOpcode()) {
21786 default: llvm_unreachable("Unexpected instr type to insert");
21787 case X86::TAILJMPd64:
21788 case X86::TAILJMPr64:
21789 case X86::TAILJMPm64:
21790 case X86::TAILJMPd64_REX:
21791 case X86::TAILJMPr64_REX:
21792 case X86::TAILJMPm64_REX:
21793 llvm_unreachable("TAILJMP64 would not be touched here.");
21794 case X86::TCRETURNdi64:
21795 case X86::TCRETURNri64:
21796 case X86::TCRETURNmi64:
21798 case X86::WIN_ALLOCA:
21799 return EmitLoweredWinAlloca(MI, BB);
21800 case X86::CATCHRET:
21801 return EmitLoweredCatchRet(MI, BB);
21802 case X86::SEG_ALLOCA_32:
21803 case X86::SEG_ALLOCA_64:
21804 return EmitLoweredSegAlloca(MI, BB);
21805 case X86::TLSCall_32:
21806 case X86::TLSCall_64:
21807 return EmitLoweredTLSCall(MI, BB);
21808 case X86::CMOV_FR32:
21809 case X86::CMOV_FR64:
21810 case X86::CMOV_GR8:
21811 case X86::CMOV_GR16:
21812 case X86::CMOV_GR32:
21813 case X86::CMOV_RFP32:
21814 case X86::CMOV_RFP64:
21815 case X86::CMOV_RFP80:
21816 case X86::CMOV_V2F64:
21817 case X86::CMOV_V2I64:
21818 case X86::CMOV_V4F32:
21819 case X86::CMOV_V4F64:
21820 case X86::CMOV_V4I64:
21821 case X86::CMOV_V16F32:
21822 case X86::CMOV_V8F32:
21823 case X86::CMOV_V8F64:
21824 case X86::CMOV_V8I64:
21825 case X86::CMOV_V8I1:
21826 case X86::CMOV_V16I1:
21827 case X86::CMOV_V32I1:
21828 case X86::CMOV_V64I1:
21829 return EmitLoweredSelect(MI, BB);
21831 case X86::RELEASE_FADD32mr:
21832 case X86::RELEASE_FADD64mr:
21833 return EmitLoweredAtomicFP(MI, BB);
21835 case X86::FP32_TO_INT16_IN_MEM:
21836 case X86::FP32_TO_INT32_IN_MEM:
21837 case X86::FP32_TO_INT64_IN_MEM:
21838 case X86::FP64_TO_INT16_IN_MEM:
21839 case X86::FP64_TO_INT32_IN_MEM:
21840 case X86::FP64_TO_INT64_IN_MEM:
21841 case X86::FP80_TO_INT16_IN_MEM:
21842 case X86::FP80_TO_INT32_IN_MEM:
21843 case X86::FP80_TO_INT64_IN_MEM: {
21844 MachineFunction *F = BB->getParent();
21845 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21846 DebugLoc DL = MI->getDebugLoc();
21848 // Change the floating point control register to use "round towards zero"
21849 // mode when truncating to an integer value.
21850 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21851 addFrameReference(BuildMI(*BB, MI, DL,
21852 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21854 // Load the old value of the high byte of the control word...
21856 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21857 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21860 // Set the high part to be round to zero...
21861 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21864 // Reload the modified control word now...
21865 addFrameReference(BuildMI(*BB, MI, DL,
21866 TII->get(X86::FLDCW16m)), CWFrameIdx);
21868 // Restore the memory image of control word to original value
21869 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21872 // Get the X86 opcode to use.
21874 switch (MI->getOpcode()) {
21875 default: llvm_unreachable("illegal opcode!");
21876 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21877 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21878 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21879 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21880 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21881 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21882 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21883 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21884 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21888 MachineOperand &Op = MI->getOperand(0);
21890 AM.BaseType = X86AddressMode::RegBase;
21891 AM.Base.Reg = Op.getReg();
21893 AM.BaseType = X86AddressMode::FrameIndexBase;
21894 AM.Base.FrameIndex = Op.getIndex();
21896 Op = MI->getOperand(1);
21898 AM.Scale = Op.getImm();
21899 Op = MI->getOperand(2);
21901 AM.IndexReg = Op.getImm();
21902 Op = MI->getOperand(3);
21903 if (Op.isGlobal()) {
21904 AM.GV = Op.getGlobal();
21906 AM.Disp = Op.getImm();
21908 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21909 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21911 // Reload the original control word now.
21912 addFrameReference(BuildMI(*BB, MI, DL,
21913 TII->get(X86::FLDCW16m)), CWFrameIdx);
21915 MI->eraseFromParent(); // The pseudo instruction is gone now.
21918 // String/text processing lowering.
21919 case X86::PCMPISTRM128REG:
21920 case X86::VPCMPISTRM128REG:
21921 case X86::PCMPISTRM128MEM:
21922 case X86::VPCMPISTRM128MEM:
21923 case X86::PCMPESTRM128REG:
21924 case X86::VPCMPESTRM128REG:
21925 case X86::PCMPESTRM128MEM:
21926 case X86::VPCMPESTRM128MEM:
21927 assert(Subtarget->hasSSE42() &&
21928 "Target must have SSE4.2 or AVX features enabled");
21929 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21931 // String/text processing lowering.
21932 case X86::PCMPISTRIREG:
21933 case X86::VPCMPISTRIREG:
21934 case X86::PCMPISTRIMEM:
21935 case X86::VPCMPISTRIMEM:
21936 case X86::PCMPESTRIREG:
21937 case X86::VPCMPESTRIREG:
21938 case X86::PCMPESTRIMEM:
21939 case X86::VPCMPESTRIMEM:
21940 assert(Subtarget->hasSSE42() &&
21941 "Target must have SSE4.2 or AVX features enabled");
21942 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21944 // Thread synchronization.
21946 return EmitMonitor(MI, BB, Subtarget);
21950 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21952 case X86::VASTART_SAVE_XMM_REGS:
21953 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21955 case X86::VAARG_64:
21956 return EmitVAARG64WithCustomInserter(MI, BB);
21958 case X86::EH_SjLj_SetJmp32:
21959 case X86::EH_SjLj_SetJmp64:
21960 return emitEHSjLjSetJmp(MI, BB);
21962 case X86::EH_SjLj_LongJmp32:
21963 case X86::EH_SjLj_LongJmp64:
21964 return emitEHSjLjLongJmp(MI, BB);
21966 case TargetOpcode::STATEPOINT:
21967 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21968 // this point in the process. We diverge later.
21969 return emitPatchPoint(MI, BB);
21971 case TargetOpcode::STACKMAP:
21972 case TargetOpcode::PATCHPOINT:
21973 return emitPatchPoint(MI, BB);
21975 case X86::VFMADDPDr213r:
21976 case X86::VFMADDPSr213r:
21977 case X86::VFMADDSDr213r:
21978 case X86::VFMADDSSr213r:
21979 case X86::VFMSUBPDr213r:
21980 case X86::VFMSUBPSr213r:
21981 case X86::VFMSUBSDr213r:
21982 case X86::VFMSUBSSr213r:
21983 case X86::VFNMADDPDr213r:
21984 case X86::VFNMADDPSr213r:
21985 case X86::VFNMADDSDr213r:
21986 case X86::VFNMADDSSr213r:
21987 case X86::VFNMSUBPDr213r:
21988 case X86::VFNMSUBPSr213r:
21989 case X86::VFNMSUBSDr213r:
21990 case X86::VFNMSUBSSr213r:
21991 case X86::VFMADDSUBPDr213r:
21992 case X86::VFMADDSUBPSr213r:
21993 case X86::VFMSUBADDPDr213r:
21994 case X86::VFMSUBADDPSr213r:
21995 case X86::VFMADDPDr213rY:
21996 case X86::VFMADDPSr213rY:
21997 case X86::VFMSUBPDr213rY:
21998 case X86::VFMSUBPSr213rY:
21999 case X86::VFNMADDPDr213rY:
22000 case X86::VFNMADDPSr213rY:
22001 case X86::VFNMSUBPDr213rY:
22002 case X86::VFNMSUBPSr213rY:
22003 case X86::VFMADDSUBPDr213rY:
22004 case X86::VFMADDSUBPSr213rY:
22005 case X86::VFMSUBADDPDr213rY:
22006 case X86::VFMSUBADDPSr213rY:
22007 return emitFMA3Instr(MI, BB);
22011 //===----------------------------------------------------------------------===//
22012 // X86 Optimization Hooks
22013 //===----------------------------------------------------------------------===//
22015 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22018 const SelectionDAG &DAG,
22019 unsigned Depth) const {
22020 unsigned BitWidth = KnownZero.getBitWidth();
22021 unsigned Opc = Op.getOpcode();
22022 assert((Opc >= ISD::BUILTIN_OP_END ||
22023 Opc == ISD::INTRINSIC_WO_CHAIN ||
22024 Opc == ISD::INTRINSIC_W_CHAIN ||
22025 Opc == ISD::INTRINSIC_VOID) &&
22026 "Should use MaskedValueIsZero if you don't know whether Op"
22027 " is a target node!");
22029 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22043 // These nodes' second result is a boolean.
22044 if (Op.getResNo() == 0)
22047 case X86ISD::SETCC:
22048 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22050 case ISD::INTRINSIC_WO_CHAIN: {
22051 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22052 unsigned NumLoBits = 0;
22055 case Intrinsic::x86_sse_movmsk_ps:
22056 case Intrinsic::x86_avx_movmsk_ps_256:
22057 case Intrinsic::x86_sse2_movmsk_pd:
22058 case Intrinsic::x86_avx_movmsk_pd_256:
22059 case Intrinsic::x86_mmx_pmovmskb:
22060 case Intrinsic::x86_sse2_pmovmskb_128:
22061 case Intrinsic::x86_avx2_pmovmskb: {
22062 // High bits of movmskp{s|d}, pmovmskb are known zero.
22064 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22065 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22066 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22067 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22068 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22069 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22070 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22071 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22073 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22082 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22084 const SelectionDAG &,
22085 unsigned Depth) const {
22086 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22087 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22088 return Op.getValueType().getScalarSizeInBits();
22094 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22095 /// node is a GlobalAddress + offset.
22096 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22097 const GlobalValue* &GA,
22098 int64_t &Offset) const {
22099 if (N->getOpcode() == X86ISD::Wrapper) {
22100 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22101 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22102 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22106 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22109 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22110 /// same as extracting the high 128-bit part of 256-bit vector and then
22111 /// inserting the result into the low part of a new 256-bit vector
22112 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22113 EVT VT = SVOp->getValueType(0);
22114 unsigned NumElems = VT.getVectorNumElements();
22116 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22117 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22118 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22119 SVOp->getMaskElt(j) >= 0)
22125 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22126 /// same as extracting the low 128-bit part of 256-bit vector and then
22127 /// inserting the result into the high part of a new 256-bit vector
22128 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22129 EVT VT = SVOp->getValueType(0);
22130 unsigned NumElems = VT.getVectorNumElements();
22132 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22133 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22134 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22135 SVOp->getMaskElt(j) >= 0)
22141 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22142 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22143 TargetLowering::DAGCombinerInfo &DCI,
22144 const X86Subtarget* Subtarget) {
22146 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22147 SDValue V1 = SVOp->getOperand(0);
22148 SDValue V2 = SVOp->getOperand(1);
22149 EVT VT = SVOp->getValueType(0);
22150 unsigned NumElems = VT.getVectorNumElements();
22152 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22153 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22157 // V UNDEF BUILD_VECTOR UNDEF
22159 // CONCAT_VECTOR CONCAT_VECTOR
22162 // RESULT: V + zero extended
22164 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22165 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22166 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22169 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22172 // To match the shuffle mask, the first half of the mask should
22173 // be exactly the first vector, and all the rest a splat with the
22174 // first element of the second one.
22175 for (unsigned i = 0; i != NumElems/2; ++i)
22176 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22177 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22180 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22181 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22182 if (Ld->hasNUsesOfValue(1, 0)) {
22183 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22184 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22186 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22188 Ld->getPointerInfo(),
22189 Ld->getAlignment(),
22190 false/*isVolatile*/, true/*ReadMem*/,
22191 false/*WriteMem*/);
22193 // Make sure the newly-created LOAD is in the same position as Ld in
22194 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22195 // and update uses of Ld's output chain to use the TokenFactor.
22196 if (Ld->hasAnyUseOfValue(1)) {
22197 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22198 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22199 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22200 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22201 SDValue(ResNode.getNode(), 1));
22204 return DAG.getBitcast(VT, ResNode);
22208 // Emit a zeroed vector and insert the desired subvector on its
22210 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22211 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22212 return DCI.CombineTo(N, InsV);
22215 //===--------------------------------------------------------------------===//
22216 // Combine some shuffles into subvector extracts and inserts:
22219 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22220 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22221 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22222 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22223 return DCI.CombineTo(N, InsV);
22226 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22227 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22228 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22229 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22230 return DCI.CombineTo(N, InsV);
22236 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22239 /// This is the leaf of the recursive combinine below. When we have found some
22240 /// chain of single-use x86 shuffle instructions and accumulated the combined
22241 /// shuffle mask represented by them, this will try to pattern match that mask
22242 /// into either a single instruction if there is a special purpose instruction
22243 /// for this operation, or into a PSHUFB instruction which is a fully general
22244 /// instruction but should only be used to replace chains over a certain depth.
22245 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22246 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22247 TargetLowering::DAGCombinerInfo &DCI,
22248 const X86Subtarget *Subtarget) {
22249 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22251 // Find the operand that enters the chain. Note that multiple uses are OK
22252 // here, we're not going to remove the operand we find.
22253 SDValue Input = Op.getOperand(0);
22254 while (Input.getOpcode() == ISD::BITCAST)
22255 Input = Input.getOperand(0);
22257 MVT VT = Input.getSimpleValueType();
22258 MVT RootVT = Root.getSimpleValueType();
22261 if (Mask.size() == 1) {
22262 int Index = Mask[0];
22263 assert((Index >= 0 || Index == SM_SentinelUndef ||
22264 Index == SM_SentinelZero) &&
22265 "Invalid shuffle index found!");
22267 // We may end up with an accumulated mask of size 1 as a result of
22268 // widening of shuffle operands (see function canWidenShuffleElements).
22269 // If the only shuffle index is equal to SM_SentinelZero then propagate
22270 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22271 // mask, and therefore the entire chain of shuffles can be folded away.
22272 if (Index == SM_SentinelZero)
22273 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22275 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22280 // Use the float domain if the operand type is a floating point type.
22281 bool FloatDomain = VT.isFloatingPoint();
22283 // For floating point shuffles, we don't have free copies in the shuffle
22284 // instructions or the ability to load as part of the instruction, so
22285 // canonicalize their shuffles to UNPCK or MOV variants.
22287 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22288 // vectors because it can have a load folded into it that UNPCK cannot. This
22289 // doesn't preclude something switching to the shorter encoding post-RA.
22291 // FIXME: Should teach these routines about AVX vector widths.
22292 if (FloatDomain && VT.is128BitVector()) {
22293 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22294 bool Lo = Mask.equals({0, 0});
22297 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22298 // is no slower than UNPCKLPD but has the option to fold the input operand
22299 // into even an unaligned memory load.
22300 if (Lo && Subtarget->hasSSE3()) {
22301 Shuffle = X86ISD::MOVDDUP;
22302 ShuffleVT = MVT::v2f64;
22304 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22305 // than the UNPCK variants.
22306 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22307 ShuffleVT = MVT::v4f32;
22309 if (Depth == 1 && Root->getOpcode() == Shuffle)
22310 return false; // Nothing to do!
22311 Op = DAG.getBitcast(ShuffleVT, Input);
22312 DCI.AddToWorklist(Op.getNode());
22313 if (Shuffle == X86ISD::MOVDDUP)
22314 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22316 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22317 DCI.AddToWorklist(Op.getNode());
22318 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22322 if (Subtarget->hasSSE3() &&
22323 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22324 bool Lo = Mask.equals({0, 0, 2, 2});
22325 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22326 MVT ShuffleVT = MVT::v4f32;
22327 if (Depth == 1 && Root->getOpcode() == Shuffle)
22328 return false; // Nothing to do!
22329 Op = DAG.getBitcast(ShuffleVT, Input);
22330 DCI.AddToWorklist(Op.getNode());
22331 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22332 DCI.AddToWorklist(Op.getNode());
22333 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22337 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22338 bool Lo = Mask.equals({0, 0, 1, 1});
22339 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22340 MVT ShuffleVT = MVT::v4f32;
22341 if (Depth == 1 && Root->getOpcode() == Shuffle)
22342 return false; // Nothing to do!
22343 Op = DAG.getBitcast(ShuffleVT, Input);
22344 DCI.AddToWorklist(Op.getNode());
22345 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22346 DCI.AddToWorklist(Op.getNode());
22347 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22353 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22354 // variants as none of these have single-instruction variants that are
22355 // superior to the UNPCK formulation.
22356 if (!FloatDomain && VT.is128BitVector() &&
22357 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22358 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22359 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22361 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22362 bool Lo = Mask[0] == 0;
22363 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22364 if (Depth == 1 && Root->getOpcode() == Shuffle)
22365 return false; // Nothing to do!
22367 switch (Mask.size()) {
22369 ShuffleVT = MVT::v8i16;
22372 ShuffleVT = MVT::v16i8;
22375 llvm_unreachable("Impossible mask size!");
22377 Op = DAG.getBitcast(ShuffleVT, Input);
22378 DCI.AddToWorklist(Op.getNode());
22379 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22380 DCI.AddToWorklist(Op.getNode());
22381 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22386 // Don't try to re-form single instruction chains under any circumstances now
22387 // that we've done encoding canonicalization for them.
22391 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22392 // can replace them with a single PSHUFB instruction profitably. Intel's
22393 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22394 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22395 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22396 SmallVector<SDValue, 16> PSHUFBMask;
22397 int NumBytes = VT.getSizeInBits() / 8;
22398 int Ratio = NumBytes / Mask.size();
22399 for (int i = 0; i < NumBytes; ++i) {
22400 if (Mask[i / Ratio] == SM_SentinelUndef) {
22401 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22404 int M = Mask[i / Ratio] != SM_SentinelZero
22405 ? Ratio * Mask[i / Ratio] + i % Ratio
22407 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22409 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22410 Op = DAG.getBitcast(ByteVT, Input);
22411 DCI.AddToWorklist(Op.getNode());
22412 SDValue PSHUFBMaskOp =
22413 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22414 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22415 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22416 DCI.AddToWorklist(Op.getNode());
22417 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22422 // Failed to find any combines.
22426 /// \brief Fully generic combining of x86 shuffle instructions.
22428 /// This should be the last combine run over the x86 shuffle instructions. Once
22429 /// they have been fully optimized, this will recursively consider all chains
22430 /// of single-use shuffle instructions, build a generic model of the cumulative
22431 /// shuffle operation, and check for simpler instructions which implement this
22432 /// operation. We use this primarily for two purposes:
22434 /// 1) Collapse generic shuffles to specialized single instructions when
22435 /// equivalent. In most cases, this is just an encoding size win, but
22436 /// sometimes we will collapse multiple generic shuffles into a single
22437 /// special-purpose shuffle.
22438 /// 2) Look for sequences of shuffle instructions with 3 or more total
22439 /// instructions, and replace them with the slightly more expensive SSSE3
22440 /// PSHUFB instruction if available. We do this as the last combining step
22441 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22442 /// a suitable short sequence of other instructions. The PHUFB will either
22443 /// use a register or have to read from memory and so is slightly (but only
22444 /// slightly) more expensive than the other shuffle instructions.
22446 /// Because this is inherently a quadratic operation (for each shuffle in
22447 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22448 /// This should never be an issue in practice as the shuffle lowering doesn't
22449 /// produce sequences of more than 8 instructions.
22451 /// FIXME: We will currently miss some cases where the redundant shuffling
22452 /// would simplify under the threshold for PSHUFB formation because of
22453 /// combine-ordering. To fix this, we should do the redundant instruction
22454 /// combining in this recursive walk.
22455 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22456 ArrayRef<int> RootMask,
22457 int Depth, bool HasPSHUFB,
22459 TargetLowering::DAGCombinerInfo &DCI,
22460 const X86Subtarget *Subtarget) {
22461 // Bound the depth of our recursive combine because this is ultimately
22462 // quadratic in nature.
22466 // Directly rip through bitcasts to find the underlying operand.
22467 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22468 Op = Op.getOperand(0);
22470 MVT VT = Op.getSimpleValueType();
22471 if (!VT.isVector())
22472 return false; // Bail if we hit a non-vector.
22474 assert(Root.getSimpleValueType().isVector() &&
22475 "Shuffles operate on vector types!");
22476 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22477 "Can only combine shuffles of the same vector register size.");
22479 if (!isTargetShuffle(Op.getOpcode()))
22481 SmallVector<int, 16> OpMask;
22483 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22484 // We only can combine unary shuffles which we can decode the mask for.
22485 if (!HaveMask || !IsUnary)
22488 assert(VT.getVectorNumElements() == OpMask.size() &&
22489 "Different mask size from vector size!");
22490 assert(((RootMask.size() > OpMask.size() &&
22491 RootMask.size() % OpMask.size() == 0) ||
22492 (OpMask.size() > RootMask.size() &&
22493 OpMask.size() % RootMask.size() == 0) ||
22494 OpMask.size() == RootMask.size()) &&
22495 "The smaller number of elements must divide the larger.");
22496 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22497 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22498 assert(((RootRatio == 1 && OpRatio == 1) ||
22499 (RootRatio == 1) != (OpRatio == 1)) &&
22500 "Must not have a ratio for both incoming and op masks!");
22502 SmallVector<int, 16> Mask;
22503 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22505 // Merge this shuffle operation's mask into our accumulated mask. Note that
22506 // this shuffle's mask will be the first applied to the input, followed by the
22507 // root mask to get us all the way to the root value arrangement. The reason
22508 // for this order is that we are recursing up the operation chain.
22509 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22510 int RootIdx = i / RootRatio;
22511 if (RootMask[RootIdx] < 0) {
22512 // This is a zero or undef lane, we're done.
22513 Mask.push_back(RootMask[RootIdx]);
22517 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22518 int OpIdx = RootMaskedIdx / OpRatio;
22519 if (OpMask[OpIdx] < 0) {
22520 // The incoming lanes are zero or undef, it doesn't matter which ones we
22522 Mask.push_back(OpMask[OpIdx]);
22526 // Ok, we have non-zero lanes, map them through.
22527 Mask.push_back(OpMask[OpIdx] * OpRatio +
22528 RootMaskedIdx % OpRatio);
22531 // See if we can recurse into the operand to combine more things.
22532 switch (Op.getOpcode()) {
22533 case X86ISD::PSHUFB:
22535 case X86ISD::PSHUFD:
22536 case X86ISD::PSHUFHW:
22537 case X86ISD::PSHUFLW:
22538 if (Op.getOperand(0).hasOneUse() &&
22539 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22540 HasPSHUFB, DAG, DCI, Subtarget))
22544 case X86ISD::UNPCKL:
22545 case X86ISD::UNPCKH:
22546 assert(Op.getOperand(0) == Op.getOperand(1) &&
22547 "We only combine unary shuffles!");
22548 // We can't check for single use, we have to check that this shuffle is the
22550 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22551 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22552 HasPSHUFB, DAG, DCI, Subtarget))
22557 // Minor canonicalization of the accumulated shuffle mask to make it easier
22558 // to match below. All this does is detect masks with squential pairs of
22559 // elements, and shrink them to the half-width mask. It does this in a loop
22560 // so it will reduce the size of the mask to the minimal width mask which
22561 // performs an equivalent shuffle.
22562 SmallVector<int, 16> WidenedMask;
22563 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22564 Mask = std::move(WidenedMask);
22565 WidenedMask.clear();
22568 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22572 /// \brief Get the PSHUF-style mask from PSHUF node.
22574 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22575 /// PSHUF-style masks that can be reused with such instructions.
22576 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22577 MVT VT = N.getSimpleValueType();
22578 SmallVector<int, 4> Mask;
22580 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22584 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22585 // matter. Check that the upper masks are repeats and remove them.
22586 if (VT.getSizeInBits() > 128) {
22587 int LaneElts = 128 / VT.getScalarSizeInBits();
22589 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22590 for (int j = 0; j < LaneElts; ++j)
22591 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22592 "Mask doesn't repeat in high 128-bit lanes!");
22594 Mask.resize(LaneElts);
22597 switch (N.getOpcode()) {
22598 case X86ISD::PSHUFD:
22600 case X86ISD::PSHUFLW:
22603 case X86ISD::PSHUFHW:
22604 Mask.erase(Mask.begin(), Mask.begin() + 4);
22605 for (int &M : Mask)
22609 llvm_unreachable("No valid shuffle instruction found!");
22613 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22615 /// We walk up the chain and look for a combinable shuffle, skipping over
22616 /// shuffles that we could hoist this shuffle's transformation past without
22617 /// altering anything.
22619 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22621 TargetLowering::DAGCombinerInfo &DCI) {
22622 assert(N.getOpcode() == X86ISD::PSHUFD &&
22623 "Called with something other than an x86 128-bit half shuffle!");
22626 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22627 // of the shuffles in the chain so that we can form a fresh chain to replace
22629 SmallVector<SDValue, 8> Chain;
22630 SDValue V = N.getOperand(0);
22631 for (; V.hasOneUse(); V = V.getOperand(0)) {
22632 switch (V.getOpcode()) {
22634 return SDValue(); // Nothing combined!
22637 // Skip bitcasts as we always know the type for the target specific
22641 case X86ISD::PSHUFD:
22642 // Found another dword shuffle.
22645 case X86ISD::PSHUFLW:
22646 // Check that the low words (being shuffled) are the identity in the
22647 // dword shuffle, and the high words are self-contained.
22648 if (Mask[0] != 0 || Mask[1] != 1 ||
22649 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22652 Chain.push_back(V);
22655 case X86ISD::PSHUFHW:
22656 // Check that the high words (being shuffled) are the identity in the
22657 // dword shuffle, and the low words are self-contained.
22658 if (Mask[2] != 2 || Mask[3] != 3 ||
22659 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22662 Chain.push_back(V);
22665 case X86ISD::UNPCKL:
22666 case X86ISD::UNPCKH:
22667 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22668 // shuffle into a preceding word shuffle.
22669 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22670 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22673 // Search for a half-shuffle which we can combine with.
22674 unsigned CombineOp =
22675 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22676 if (V.getOperand(0) != V.getOperand(1) ||
22677 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22679 Chain.push_back(V);
22680 V = V.getOperand(0);
22682 switch (V.getOpcode()) {
22684 return SDValue(); // Nothing to combine.
22686 case X86ISD::PSHUFLW:
22687 case X86ISD::PSHUFHW:
22688 if (V.getOpcode() == CombineOp)
22691 Chain.push_back(V);
22695 V = V.getOperand(0);
22699 } while (V.hasOneUse());
22702 // Break out of the loop if we break out of the switch.
22706 if (!V.hasOneUse())
22707 // We fell out of the loop without finding a viable combining instruction.
22710 // Merge this node's mask and our incoming mask.
22711 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22712 for (int &M : Mask)
22714 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22715 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22717 // Rebuild the chain around this new shuffle.
22718 while (!Chain.empty()) {
22719 SDValue W = Chain.pop_back_val();
22721 if (V.getValueType() != W.getOperand(0).getValueType())
22722 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22724 switch (W.getOpcode()) {
22726 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22728 case X86ISD::UNPCKL:
22729 case X86ISD::UNPCKH:
22730 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22733 case X86ISD::PSHUFD:
22734 case X86ISD::PSHUFLW:
22735 case X86ISD::PSHUFHW:
22736 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22740 if (V.getValueType() != N.getValueType())
22741 V = DAG.getBitcast(N.getValueType(), V);
22743 // Return the new chain to replace N.
22747 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22750 /// We walk up the chain, skipping shuffles of the other half and looking
22751 /// through shuffles which switch halves trying to find a shuffle of the same
22752 /// pair of dwords.
22753 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22755 TargetLowering::DAGCombinerInfo &DCI) {
22757 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22758 "Called with something other than an x86 128-bit half shuffle!");
22760 unsigned CombineOpcode = N.getOpcode();
22762 // Walk up a single-use chain looking for a combinable shuffle.
22763 SDValue V = N.getOperand(0);
22764 for (; V.hasOneUse(); V = V.getOperand(0)) {
22765 switch (V.getOpcode()) {
22767 return false; // Nothing combined!
22770 // Skip bitcasts as we always know the type for the target specific
22774 case X86ISD::PSHUFLW:
22775 case X86ISD::PSHUFHW:
22776 if (V.getOpcode() == CombineOpcode)
22779 // Other-half shuffles are no-ops.
22782 // Break out of the loop if we break out of the switch.
22786 if (!V.hasOneUse())
22787 // We fell out of the loop without finding a viable combining instruction.
22790 // Combine away the bottom node as its shuffle will be accumulated into
22791 // a preceding shuffle.
22792 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22794 // Record the old value.
22797 // Merge this node's mask and our incoming mask (adjusted to account for all
22798 // the pshufd instructions encountered).
22799 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22800 for (int &M : Mask)
22802 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22803 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22805 // Check that the shuffles didn't cancel each other out. If not, we need to
22806 // combine to the new one.
22808 // Replace the combinable shuffle with the combined one, updating all users
22809 // so that we re-evaluate the chain here.
22810 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22815 /// \brief Try to combine x86 target specific shuffles.
22816 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22817 TargetLowering::DAGCombinerInfo &DCI,
22818 const X86Subtarget *Subtarget) {
22820 MVT VT = N.getSimpleValueType();
22821 SmallVector<int, 4> Mask;
22823 switch (N.getOpcode()) {
22824 case X86ISD::PSHUFD:
22825 case X86ISD::PSHUFLW:
22826 case X86ISD::PSHUFHW:
22827 Mask = getPSHUFShuffleMask(N);
22828 assert(Mask.size() == 4);
22834 // Nuke no-op shuffles that show up after combining.
22835 if (isNoopShuffleMask(Mask))
22836 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22838 // Look for simplifications involving one or two shuffle instructions.
22839 SDValue V = N.getOperand(0);
22840 switch (N.getOpcode()) {
22843 case X86ISD::PSHUFLW:
22844 case X86ISD::PSHUFHW:
22845 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
22847 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22848 return SDValue(); // We combined away this shuffle, so we're done.
22850 // See if this reduces to a PSHUFD which is no more expensive and can
22851 // combine with more operations. Note that it has to at least flip the
22852 // dwords as otherwise it would have been removed as a no-op.
22853 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22854 int DMask[] = {0, 1, 2, 3};
22855 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22856 DMask[DOffset + 0] = DOffset + 1;
22857 DMask[DOffset + 1] = DOffset + 0;
22858 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22859 V = DAG.getBitcast(DVT, V);
22860 DCI.AddToWorklist(V.getNode());
22861 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22862 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22863 DCI.AddToWorklist(V.getNode());
22864 return DAG.getBitcast(VT, V);
22867 // Look for shuffle patterns which can be implemented as a single unpack.
22868 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22869 // only works when we have a PSHUFD followed by two half-shuffles.
22870 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22871 (V.getOpcode() == X86ISD::PSHUFLW ||
22872 V.getOpcode() == X86ISD::PSHUFHW) &&
22873 V.getOpcode() != N.getOpcode() &&
22875 SDValue D = V.getOperand(0);
22876 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22877 D = D.getOperand(0);
22878 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22879 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22880 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22881 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22882 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22884 for (int i = 0; i < 4; ++i) {
22885 WordMask[i + NOffset] = Mask[i] + NOffset;
22886 WordMask[i + VOffset] = VMask[i] + VOffset;
22888 // Map the word mask through the DWord mask.
22890 for (int i = 0; i < 8; ++i)
22891 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22892 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22893 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22894 // We can replace all three shuffles with an unpack.
22895 V = DAG.getBitcast(VT, D.getOperand(0));
22896 DCI.AddToWorklist(V.getNode());
22897 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22906 case X86ISD::PSHUFD:
22907 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22916 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22918 /// We combine this directly on the abstract vector shuffle nodes so it is
22919 /// easier to generically match. We also insert dummy vector shuffle nodes for
22920 /// the operands which explicitly discard the lanes which are unused by this
22921 /// operation to try to flow through the rest of the combiner the fact that
22922 /// they're unused.
22923 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22925 EVT VT = N->getValueType(0);
22927 // We only handle target-independent shuffles.
22928 // FIXME: It would be easy and harmless to use the target shuffle mask
22929 // extraction tool to support more.
22930 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22933 auto *SVN = cast<ShuffleVectorSDNode>(N);
22934 ArrayRef<int> Mask = SVN->getMask();
22935 SDValue V1 = N->getOperand(0);
22936 SDValue V2 = N->getOperand(1);
22938 // We require the first shuffle operand to be the SUB node, and the second to
22939 // be the ADD node.
22940 // FIXME: We should support the commuted patterns.
22941 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22944 // If there are other uses of these operations we can't fold them.
22945 if (!V1->hasOneUse() || !V2->hasOneUse())
22948 // Ensure that both operations have the same operands. Note that we can
22949 // commute the FADD operands.
22950 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22951 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22952 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22955 // We're looking for blends between FADD and FSUB nodes. We insist on these
22956 // nodes being lined up in a specific expected pattern.
22957 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22958 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22959 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22962 // Only specific types are legal at this point, assert so we notice if and
22963 // when these change.
22964 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22965 VT == MVT::v4f64) &&
22966 "Unknown vector type encountered!");
22968 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22971 /// PerformShuffleCombine - Performs several different shuffle combines.
22972 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22973 TargetLowering::DAGCombinerInfo &DCI,
22974 const X86Subtarget *Subtarget) {
22976 SDValue N0 = N->getOperand(0);
22977 SDValue N1 = N->getOperand(1);
22978 EVT VT = N->getValueType(0);
22980 // Don't create instructions with illegal types after legalize types has run.
22981 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22982 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22985 // If we have legalized the vector types, look for blends of FADD and FSUB
22986 // nodes that we can fuse into an ADDSUB node.
22987 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22988 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22991 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22992 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22993 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22994 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22996 // During Type Legalization, when promoting illegal vector types,
22997 // the backend might introduce new shuffle dag nodes and bitcasts.
22999 // This code performs the following transformation:
23000 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23001 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23003 // We do this only if both the bitcast and the BINOP dag nodes have
23004 // one use. Also, perform this transformation only if the new binary
23005 // operation is legal. This is to avoid introducing dag nodes that
23006 // potentially need to be further expanded (or custom lowered) into a
23007 // less optimal sequence of dag nodes.
23008 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23009 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23010 N0.getOpcode() == ISD::BITCAST) {
23011 SDValue BC0 = N0.getOperand(0);
23012 EVT SVT = BC0.getValueType();
23013 unsigned Opcode = BC0.getOpcode();
23014 unsigned NumElts = VT.getVectorNumElements();
23016 if (BC0.hasOneUse() && SVT.isVector() &&
23017 SVT.getVectorNumElements() * 2 == NumElts &&
23018 TLI.isOperationLegal(Opcode, VT)) {
23019 bool CanFold = false;
23031 unsigned SVTNumElts = SVT.getVectorNumElements();
23032 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23033 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23034 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23035 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23036 CanFold = SVOp->getMaskElt(i) < 0;
23039 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23040 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23041 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23042 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23047 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23048 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23049 // consecutive, non-overlapping, and in the right order.
23050 SmallVector<SDValue, 16> Elts;
23051 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23052 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23054 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23057 if (isTargetShuffle(N->getOpcode())) {
23059 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23060 if (Shuffle.getNode())
23063 // Try recursively combining arbitrary sequences of x86 shuffle
23064 // instructions into higher-order shuffles. We do this after combining
23065 // specific PSHUF instruction sequences into their minimal form so that we
23066 // can evaluate how many specialized shuffle instructions are involved in
23067 // a particular chain.
23068 SmallVector<int, 1> NonceMask; // Just a placeholder.
23069 NonceMask.push_back(0);
23070 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23071 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23073 return SDValue(); // This routine will use CombineTo to replace N.
23079 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23080 /// specific shuffle of a load can be folded into a single element load.
23081 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23082 /// shuffles have been custom lowered so we need to handle those here.
23083 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23084 TargetLowering::DAGCombinerInfo &DCI) {
23085 if (DCI.isBeforeLegalizeOps())
23088 SDValue InVec = N->getOperand(0);
23089 SDValue EltNo = N->getOperand(1);
23091 if (!isa<ConstantSDNode>(EltNo))
23094 EVT OriginalVT = InVec.getValueType();
23096 if (InVec.getOpcode() == ISD::BITCAST) {
23097 // Don't duplicate a load with other uses.
23098 if (!InVec.hasOneUse())
23100 EVT BCVT = InVec.getOperand(0).getValueType();
23101 if (!BCVT.isVector() ||
23102 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23104 InVec = InVec.getOperand(0);
23107 EVT CurrentVT = InVec.getValueType();
23109 if (!isTargetShuffle(InVec.getOpcode()))
23112 // Don't duplicate a load with other uses.
23113 if (!InVec.hasOneUse())
23116 SmallVector<int, 16> ShuffleMask;
23118 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23119 ShuffleMask, UnaryShuffle))
23122 // Select the input vector, guarding against out of range extract vector.
23123 unsigned NumElems = CurrentVT.getVectorNumElements();
23124 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23125 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23126 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23127 : InVec.getOperand(1);
23129 // If inputs to shuffle are the same for both ops, then allow 2 uses
23130 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23131 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23133 if (LdNode.getOpcode() == ISD::BITCAST) {
23134 // Don't duplicate a load with other uses.
23135 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23138 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23139 LdNode = LdNode.getOperand(0);
23142 if (!ISD::isNormalLoad(LdNode.getNode()))
23145 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23147 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23150 EVT EltVT = N->getValueType(0);
23151 // If there's a bitcast before the shuffle, check if the load type and
23152 // alignment is valid.
23153 unsigned Align = LN0->getAlignment();
23154 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23155 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23156 EltVT.getTypeForEVT(*DAG.getContext()));
23158 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23161 // All checks match so transform back to vector_shuffle so that DAG combiner
23162 // can finish the job
23165 // Create shuffle node taking into account the case that its a unary shuffle
23166 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23167 : InVec.getOperand(1);
23168 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23169 InVec.getOperand(0), Shuffle,
23171 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23172 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23176 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23177 const X86Subtarget *Subtarget) {
23178 SDValue N0 = N->getOperand(0);
23179 EVT VT = N->getValueType(0);
23181 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23182 // special and don't usually play with other vector types, it's better to
23183 // handle them early to be sure we emit efficient code by avoiding
23184 // store-load conversions.
23185 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23186 N0.getValueType() == MVT::v2i32 &&
23187 isa<ConstantSDNode>(N0.getOperand(1))) {
23188 SDValue N00 = N0->getOperand(0);
23189 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23190 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23193 // Convert a bitcasted integer logic operation that has one bitcasted
23194 // floating-point operand and one constant operand into a floating-point
23195 // logic operation. This may create a load of the constant, but that is
23196 // cheaper than materializing the constant in an integer register and
23197 // transferring it to an SSE register or transferring the SSE operand to
23198 // integer register and back.
23200 switch (N0.getOpcode()) {
23201 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23202 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23203 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23204 default: return SDValue();
23206 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23207 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23208 isa<ConstantSDNode>(N0.getOperand(1)) &&
23209 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23210 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23211 SDValue N000 = N0.getOperand(0).getOperand(0);
23212 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23213 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23219 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23220 /// generation and convert it from being a bunch of shuffles and extracts
23221 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23222 /// storing the value and loading scalars back, while for x64 we should
23223 /// use 64-bit extracts and shifts.
23224 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23225 TargetLowering::DAGCombinerInfo &DCI) {
23226 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23229 SDValue InputVector = N->getOperand(0);
23230 SDLoc dl(InputVector);
23231 // Detect mmx to i32 conversion through a v2i32 elt extract.
23232 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23233 N->getValueType(0) == MVT::i32 &&
23234 InputVector.getValueType() == MVT::v2i32) {
23236 // The bitcast source is a direct mmx result.
23237 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23238 if (MMXSrc.getValueType() == MVT::x86mmx)
23239 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23240 N->getValueType(0),
23241 InputVector.getNode()->getOperand(0));
23243 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23244 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23245 MMXSrc.getValueType() == MVT::i64) {
23246 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23247 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23248 MMXSrcOp.getValueType() == MVT::v1i64 &&
23249 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23250 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23251 N->getValueType(0), MMXSrcOp.getOperand(0));
23255 EVT VT = N->getValueType(0);
23257 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23258 InputVector.getOpcode() == ISD::BITCAST &&
23259 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23260 uint64_t ExtractedElt =
23261 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23262 uint64_t InputValue =
23263 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23264 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23265 return DAG.getConstant(Res, dl, MVT::i1);
23267 // Only operate on vectors of 4 elements, where the alternative shuffling
23268 // gets to be more expensive.
23269 if (InputVector.getValueType() != MVT::v4i32)
23272 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23273 // single use which is a sign-extend or zero-extend, and all elements are
23275 SmallVector<SDNode *, 4> Uses;
23276 unsigned ExtractedElements = 0;
23277 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23278 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23279 if (UI.getUse().getResNo() != InputVector.getResNo())
23282 SDNode *Extract = *UI;
23283 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23286 if (Extract->getValueType(0) != MVT::i32)
23288 if (!Extract->hasOneUse())
23290 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23291 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23293 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23296 // Record which element was extracted.
23297 ExtractedElements |=
23298 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23300 Uses.push_back(Extract);
23303 // If not all the elements were used, this may not be worthwhile.
23304 if (ExtractedElements != 15)
23307 // Ok, we've now decided to do the transformation.
23308 // If 64-bit shifts are legal, use the extract-shift sequence,
23309 // otherwise bounce the vector off the cache.
23310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23313 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23314 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23315 auto &DL = DAG.getDataLayout();
23316 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23317 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23318 DAG.getConstant(0, dl, VecIdxTy));
23319 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23320 DAG.getConstant(1, dl, VecIdxTy));
23322 SDValue ShAmt = DAG.getConstant(
23323 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23324 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23325 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23326 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23327 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23328 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23329 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23331 // Store the value to a temporary stack slot.
23332 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23333 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23334 MachinePointerInfo(), false, false, 0);
23336 EVT ElementType = InputVector.getValueType().getVectorElementType();
23337 unsigned EltSize = ElementType.getSizeInBits() / 8;
23339 // Replace each use (extract) with a load of the appropriate element.
23340 for (unsigned i = 0; i < 4; ++i) {
23341 uint64_t Offset = EltSize * i;
23342 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23343 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23345 SDValue ScalarAddr =
23346 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23348 // Load the scalar.
23349 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23350 ScalarAddr, MachinePointerInfo(),
23351 false, false, false, 0);
23356 // Replace the extracts
23357 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23358 UE = Uses.end(); UI != UE; ++UI) {
23359 SDNode *Extract = *UI;
23361 SDValue Idx = Extract->getOperand(1);
23362 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23363 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23366 // The replacement was made in place; don't return anything.
23371 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23372 const X86Subtarget *Subtarget) {
23374 SDValue Cond = N->getOperand(0);
23375 SDValue LHS = N->getOperand(1);
23376 SDValue RHS = N->getOperand(2);
23378 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23379 SDValue CondSrc = Cond->getOperand(0);
23380 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23381 Cond = CondSrc->getOperand(0);
23384 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23387 // A vselect where all conditions and data are constants can be optimized into
23388 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23389 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23390 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23393 unsigned MaskValue = 0;
23394 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23397 MVT VT = N->getSimpleValueType(0);
23398 unsigned NumElems = VT.getVectorNumElements();
23399 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23400 for (unsigned i = 0; i < NumElems; ++i) {
23401 // Be sure we emit undef where we can.
23402 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23403 ShuffleMask[i] = -1;
23405 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23409 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23411 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23414 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23416 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23417 TargetLowering::DAGCombinerInfo &DCI,
23418 const X86Subtarget *Subtarget) {
23420 SDValue Cond = N->getOperand(0);
23421 // Get the LHS/RHS of the select.
23422 SDValue LHS = N->getOperand(1);
23423 SDValue RHS = N->getOperand(2);
23424 EVT VT = LHS.getValueType();
23425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23427 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23428 // instructions match the semantics of the common C idiom x<y?x:y but not
23429 // x<=y?x:y, because of how they handle negative zero (which can be
23430 // ignored in unsafe-math mode).
23431 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23432 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23433 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23434 (Subtarget->hasSSE2() ||
23435 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23436 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23438 unsigned Opcode = 0;
23439 // Check for x CC y ? x : y.
23440 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23441 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23445 // Converting this to a min would handle NaNs incorrectly, and swapping
23446 // the operands would cause it to handle comparisons between positive
23447 // and negative zero incorrectly.
23448 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23449 if (!DAG.getTarget().Options.UnsafeFPMath &&
23450 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23452 std::swap(LHS, RHS);
23454 Opcode = X86ISD::FMIN;
23457 // Converting this to a min would handle comparisons between positive
23458 // and negative zero incorrectly.
23459 if (!DAG.getTarget().Options.UnsafeFPMath &&
23460 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23462 Opcode = X86ISD::FMIN;
23465 // Converting this to a min would handle both negative zeros and NaNs
23466 // incorrectly, but we can swap the operands to fix both.
23467 std::swap(LHS, RHS);
23471 Opcode = X86ISD::FMIN;
23475 // Converting this to a max would handle comparisons between positive
23476 // and negative zero incorrectly.
23477 if (!DAG.getTarget().Options.UnsafeFPMath &&
23478 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23480 Opcode = X86ISD::FMAX;
23483 // Converting this to a max would handle NaNs incorrectly, and swapping
23484 // the operands would cause it to handle comparisons between positive
23485 // and negative zero incorrectly.
23486 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23487 if (!DAG.getTarget().Options.UnsafeFPMath &&
23488 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23490 std::swap(LHS, RHS);
23492 Opcode = X86ISD::FMAX;
23495 // Converting this to a max would handle both negative zeros and NaNs
23496 // incorrectly, but we can swap the operands to fix both.
23497 std::swap(LHS, RHS);
23501 Opcode = X86ISD::FMAX;
23504 // Check for x CC y ? y : x -- a min/max with reversed arms.
23505 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23506 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23510 // Converting this to a min would handle comparisons between positive
23511 // and negative zero incorrectly, and swapping the operands would
23512 // cause it to handle NaNs incorrectly.
23513 if (!DAG.getTarget().Options.UnsafeFPMath &&
23514 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23515 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23517 std::swap(LHS, RHS);
23519 Opcode = X86ISD::FMIN;
23522 // Converting this to a min would handle NaNs incorrectly.
23523 if (!DAG.getTarget().Options.UnsafeFPMath &&
23524 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23526 Opcode = X86ISD::FMIN;
23529 // Converting this to a min would handle both negative zeros and NaNs
23530 // incorrectly, but we can swap the operands to fix both.
23531 std::swap(LHS, RHS);
23535 Opcode = X86ISD::FMIN;
23539 // Converting this to a max would handle NaNs incorrectly.
23540 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23542 Opcode = X86ISD::FMAX;
23545 // Converting this to a max would handle comparisons between positive
23546 // and negative zero incorrectly, and swapping the operands would
23547 // cause it to handle NaNs incorrectly.
23548 if (!DAG.getTarget().Options.UnsafeFPMath &&
23549 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23550 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23552 std::swap(LHS, RHS);
23554 Opcode = X86ISD::FMAX;
23557 // Converting this to a max would handle both negative zeros and NaNs
23558 // incorrectly, but we can swap the operands to fix both.
23559 std::swap(LHS, RHS);
23563 Opcode = X86ISD::FMAX;
23569 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23572 EVT CondVT = Cond.getValueType();
23573 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23574 CondVT.getVectorElementType() == MVT::i1) {
23575 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23576 // lowering on KNL. In this case we convert it to
23577 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23578 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23579 // Since SKX these selects have a proper lowering.
23580 EVT OpVT = LHS.getValueType();
23581 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23582 (OpVT.getVectorElementType() == MVT::i8 ||
23583 OpVT.getVectorElementType() == MVT::i16) &&
23584 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23585 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23586 DCI.AddToWorklist(Cond.getNode());
23587 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23590 // If this is a select between two integer constants, try to do some
23592 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23593 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23594 // Don't do this for crazy integer types.
23595 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23596 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23597 // so that TrueC (the true value) is larger than FalseC.
23598 bool NeedsCondInvert = false;
23600 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23601 // Efficiently invertible.
23602 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23603 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23604 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23605 NeedsCondInvert = true;
23606 std::swap(TrueC, FalseC);
23609 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23610 if (FalseC->getAPIntValue() == 0 &&
23611 TrueC->getAPIntValue().isPowerOf2()) {
23612 if (NeedsCondInvert) // Invert the condition if needed.
23613 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23614 DAG.getConstant(1, DL, Cond.getValueType()));
23616 // Zero extend the condition if needed.
23617 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23619 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23620 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23621 DAG.getConstant(ShAmt, DL, MVT::i8));
23624 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23625 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23626 if (NeedsCondInvert) // Invert the condition if needed.
23627 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23628 DAG.getConstant(1, DL, Cond.getValueType()));
23630 // Zero extend the condition if needed.
23631 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23632 FalseC->getValueType(0), Cond);
23633 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23634 SDValue(FalseC, 0));
23637 // Optimize cases that will turn into an LEA instruction. This requires
23638 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23639 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23640 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23641 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23643 bool isFastMultiplier = false;
23645 switch ((unsigned char)Diff) {
23647 case 1: // result = add base, cond
23648 case 2: // result = lea base( , cond*2)
23649 case 3: // result = lea base(cond, cond*2)
23650 case 4: // result = lea base( , cond*4)
23651 case 5: // result = lea base(cond, cond*4)
23652 case 8: // result = lea base( , cond*8)
23653 case 9: // result = lea base(cond, cond*8)
23654 isFastMultiplier = true;
23659 if (isFastMultiplier) {
23660 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23661 if (NeedsCondInvert) // Invert the condition if needed.
23662 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23663 DAG.getConstant(1, DL, Cond.getValueType()));
23665 // Zero extend the condition if needed.
23666 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23668 // Scale the condition by the difference.
23670 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23671 DAG.getConstant(Diff, DL,
23672 Cond.getValueType()));
23674 // Add the base if non-zero.
23675 if (FalseC->getAPIntValue() != 0)
23676 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23677 SDValue(FalseC, 0));
23684 // Canonicalize max and min:
23685 // (x > y) ? x : y -> (x >= y) ? x : y
23686 // (x < y) ? x : y -> (x <= y) ? x : y
23687 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23688 // the need for an extra compare
23689 // against zero. e.g.
23690 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23692 // testl %edi, %edi
23694 // cmovgl %edi, %eax
23698 // cmovsl %eax, %edi
23699 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23700 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23701 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23702 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23707 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23708 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23709 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23710 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23715 // Early exit check
23716 if (!TLI.isTypeLegal(VT))
23719 // Match VSELECTs into subs with unsigned saturation.
23720 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23721 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23722 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23723 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23724 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23726 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23727 // left side invert the predicate to simplify logic below.
23729 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23731 CC = ISD::getSetCCInverse(CC, true);
23732 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23736 if (Other.getNode() && Other->getNumOperands() == 2 &&
23737 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23738 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23739 SDValue CondRHS = Cond->getOperand(1);
23741 // Look for a general sub with unsigned saturation first.
23742 // x >= y ? x-y : 0 --> subus x, y
23743 // x > y ? x-y : 0 --> subus x, y
23744 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23745 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23746 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23748 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23749 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23750 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23751 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23752 // If the RHS is a constant we have to reverse the const
23753 // canonicalization.
23754 // x > C-1 ? x+-C : 0 --> subus x, C
23755 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23756 CondRHSConst->getAPIntValue() ==
23757 (-OpRHSConst->getAPIntValue() - 1))
23758 return DAG.getNode(
23759 X86ISD::SUBUS, DL, VT, OpLHS,
23760 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23762 // Another special case: If C was a sign bit, the sub has been
23763 // canonicalized into a xor.
23764 // FIXME: Would it be better to use computeKnownBits to determine
23765 // whether it's safe to decanonicalize the xor?
23766 // x s< 0 ? x^C : 0 --> subus x, C
23767 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23768 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23769 OpRHSConst->getAPIntValue().isSignBit())
23770 // Note that we have to rebuild the RHS constant here to ensure we
23771 // don't rely on particular values of undef lanes.
23772 return DAG.getNode(
23773 X86ISD::SUBUS, DL, VT, OpLHS,
23774 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23779 // Simplify vector selection if condition value type matches vselect
23781 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23782 assert(Cond.getValueType().isVector() &&
23783 "vector select expects a vector selector!");
23785 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23786 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23788 // Try invert the condition if true value is not all 1s and false value
23790 if (!TValIsAllOnes && !FValIsAllZeros &&
23791 // Check if the selector will be produced by CMPP*/PCMP*
23792 Cond.getOpcode() == ISD::SETCC &&
23793 // Check if SETCC has already been promoted
23794 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23796 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23797 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23799 if (TValIsAllZeros || FValIsAllOnes) {
23800 SDValue CC = Cond.getOperand(2);
23801 ISD::CondCode NewCC =
23802 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23803 Cond.getOperand(0).getValueType().isInteger());
23804 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23805 std::swap(LHS, RHS);
23806 TValIsAllOnes = FValIsAllOnes;
23807 FValIsAllZeros = TValIsAllZeros;
23811 if (TValIsAllOnes || FValIsAllZeros) {
23814 if (TValIsAllOnes && FValIsAllZeros)
23816 else if (TValIsAllOnes)
23818 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23819 else if (FValIsAllZeros)
23820 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23821 DAG.getBitcast(CondVT, LHS));
23823 return DAG.getBitcast(VT, Ret);
23827 // We should generate an X86ISD::BLENDI from a vselect if its argument
23828 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23829 // constants. This specific pattern gets generated when we split a
23830 // selector for a 512 bit vector in a machine without AVX512 (but with
23831 // 256-bit vectors), during legalization:
23833 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23835 // Iff we find this pattern and the build_vectors are built from
23836 // constants, we translate the vselect into a shuffle_vector that we
23837 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23838 if ((N->getOpcode() == ISD::VSELECT ||
23839 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23840 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23841 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23842 if (Shuffle.getNode())
23846 // If this is a *dynamic* select (non-constant condition) and we can match
23847 // this node with one of the variable blend instructions, restructure the
23848 // condition so that the blends can use the high bit of each element and use
23849 // SimplifyDemandedBits to simplify the condition operand.
23850 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23851 !DCI.isBeforeLegalize() &&
23852 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23853 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
23855 // Don't optimize vector selects that map to mask-registers.
23859 // We can only handle the cases where VSELECT is directly legal on the
23860 // subtarget. We custom lower VSELECT nodes with constant conditions and
23861 // this makes it hard to see whether a dynamic VSELECT will correctly
23862 // lower, so we both check the operation's status and explicitly handle the
23863 // cases where a *dynamic* blend will fail even though a constant-condition
23864 // blend could be custom lowered.
23865 // FIXME: We should find a better way to handle this class of problems.
23866 // Potentially, we should combine constant-condition vselect nodes
23867 // pre-legalization into shuffles and not mark as many types as custom
23869 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23871 // FIXME: We don't support i16-element blends currently. We could and
23872 // should support them by making *all* the bits in the condition be set
23873 // rather than just the high bit and using an i8-element blend.
23874 if (VT.getVectorElementType() == MVT::i16)
23876 // Dynamic blending was only available from SSE4.1 onward.
23877 if (VT.is128BitVector() && !Subtarget->hasSSE41())
23879 // Byte blends are only available in AVX2
23880 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
23883 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23884 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23886 APInt KnownZero, KnownOne;
23887 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23888 DCI.isBeforeLegalizeOps());
23889 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23890 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23892 // If we changed the computation somewhere in the DAG, this change
23893 // will affect all users of Cond.
23894 // Make sure it is fine and update all the nodes so that we do not
23895 // use the generic VSELECT anymore. Otherwise, we may perform
23896 // wrong optimizations as we messed up with the actual expectation
23897 // for the vector boolean values.
23898 if (Cond != TLO.Old) {
23899 // Check all uses of that condition operand to check whether it will be
23900 // consumed by non-BLEND instructions, which may depend on all bits are
23902 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23904 if (I->getOpcode() != ISD::VSELECT)
23905 // TODO: Add other opcodes eventually lowered into BLEND.
23908 // Update all the users of the condition, before committing the change,
23909 // so that the VSELECT optimizations that expect the correct vector
23910 // boolean value will not be triggered.
23911 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23913 DAG.ReplaceAllUsesOfValueWith(
23915 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23916 Cond, I->getOperand(1), I->getOperand(2)));
23917 DCI.CommitTargetLoweringOpt(TLO);
23920 // At this point, only Cond is changed. Change the condition
23921 // just for N to keep the opportunity to optimize all other
23922 // users their own way.
23923 DAG.ReplaceAllUsesOfValueWith(
23925 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23926 TLO.New, N->getOperand(1), N->getOperand(2)));
23934 // Check whether a boolean test is testing a boolean value generated by
23935 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23938 // Simplify the following patterns:
23939 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23940 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23941 // to (Op EFLAGS Cond)
23943 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23944 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23945 // to (Op EFLAGS !Cond)
23947 // where Op could be BRCOND or CMOV.
23949 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23950 // Quit if not CMP and SUB with its value result used.
23951 if (Cmp.getOpcode() != X86ISD::CMP &&
23952 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23955 // Quit if not used as a boolean value.
23956 if (CC != X86::COND_E && CC != X86::COND_NE)
23959 // Check CMP operands. One of them should be 0 or 1 and the other should be
23960 // an SetCC or extended from it.
23961 SDValue Op1 = Cmp.getOperand(0);
23962 SDValue Op2 = Cmp.getOperand(1);
23965 const ConstantSDNode* C = nullptr;
23966 bool needOppositeCond = (CC == X86::COND_E);
23967 bool checkAgainstTrue = false; // Is it a comparison against 1?
23969 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23971 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23973 else // Quit if all operands are not constants.
23976 if (C->getZExtValue() == 1) {
23977 needOppositeCond = !needOppositeCond;
23978 checkAgainstTrue = true;
23979 } else if (C->getZExtValue() != 0)
23980 // Quit if the constant is neither 0 or 1.
23983 bool truncatedToBoolWithAnd = false;
23984 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23985 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23986 SetCC.getOpcode() == ISD::TRUNCATE ||
23987 SetCC.getOpcode() == ISD::AND) {
23988 if (SetCC.getOpcode() == ISD::AND) {
23990 ConstantSDNode *CS;
23991 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23992 CS->getZExtValue() == 1)
23994 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23995 CS->getZExtValue() == 1)
23999 SetCC = SetCC.getOperand(OpIdx);
24000 truncatedToBoolWithAnd = true;
24002 SetCC = SetCC.getOperand(0);
24005 switch (SetCC.getOpcode()) {
24006 case X86ISD::SETCC_CARRY:
24007 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24008 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24009 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24010 // truncated to i1 using 'and'.
24011 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24013 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24014 "Invalid use of SETCC_CARRY!");
24016 case X86ISD::SETCC:
24017 // Set the condition code or opposite one if necessary.
24018 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24019 if (needOppositeCond)
24020 CC = X86::GetOppositeBranchCondition(CC);
24021 return SetCC.getOperand(1);
24022 case X86ISD::CMOV: {
24023 // Check whether false/true value has canonical one, i.e. 0 or 1.
24024 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24025 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24026 // Quit if true value is not a constant.
24029 // Quit if false value is not a constant.
24031 SDValue Op = SetCC.getOperand(0);
24032 // Skip 'zext' or 'trunc' node.
24033 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24034 Op.getOpcode() == ISD::TRUNCATE)
24035 Op = Op.getOperand(0);
24036 // A special case for rdrand/rdseed, where 0 is set if false cond is
24038 if ((Op.getOpcode() != X86ISD::RDRAND &&
24039 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24042 // Quit if false value is not the constant 0 or 1.
24043 bool FValIsFalse = true;
24044 if (FVal && FVal->getZExtValue() != 0) {
24045 if (FVal->getZExtValue() != 1)
24047 // If FVal is 1, opposite cond is needed.
24048 needOppositeCond = !needOppositeCond;
24049 FValIsFalse = false;
24051 // Quit if TVal is not the constant opposite of FVal.
24052 if (FValIsFalse && TVal->getZExtValue() != 1)
24054 if (!FValIsFalse && TVal->getZExtValue() != 0)
24056 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24057 if (needOppositeCond)
24058 CC = X86::GetOppositeBranchCondition(CC);
24059 return SetCC.getOperand(3);
24066 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24068 /// (X86or (X86setcc) (X86setcc))
24069 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24070 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24071 X86::CondCode &CC1, SDValue &Flags,
24073 if (Cond->getOpcode() == X86ISD::CMP) {
24074 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24075 if (!CondOp1C || !CondOp1C->isNullValue())
24078 Cond = Cond->getOperand(0);
24083 SDValue SetCC0, SetCC1;
24084 switch (Cond->getOpcode()) {
24085 default: return false;
24092 SetCC0 = Cond->getOperand(0);
24093 SetCC1 = Cond->getOperand(1);
24097 // Make sure we have SETCC nodes, using the same flags value.
24098 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24099 SetCC1.getOpcode() != X86ISD::SETCC ||
24100 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24103 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24104 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24105 Flags = SetCC0->getOperand(1);
24109 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24110 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24111 TargetLowering::DAGCombinerInfo &DCI,
24112 const X86Subtarget *Subtarget) {
24115 // If the flag operand isn't dead, don't touch this CMOV.
24116 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24119 SDValue FalseOp = N->getOperand(0);
24120 SDValue TrueOp = N->getOperand(1);
24121 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24122 SDValue Cond = N->getOperand(3);
24124 if (CC == X86::COND_E || CC == X86::COND_NE) {
24125 switch (Cond.getOpcode()) {
24129 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24130 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24131 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24137 Flags = checkBoolTestSetCCCombine(Cond, CC);
24138 if (Flags.getNode() &&
24139 // Extra check as FCMOV only supports a subset of X86 cond.
24140 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24141 SDValue Ops[] = { FalseOp, TrueOp,
24142 DAG.getConstant(CC, DL, MVT::i8), Flags };
24143 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24146 // If this is a select between two integer constants, try to do some
24147 // optimizations. Note that the operands are ordered the opposite of SELECT
24149 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24150 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24151 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24152 // larger than FalseC (the false value).
24153 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24154 CC = X86::GetOppositeBranchCondition(CC);
24155 std::swap(TrueC, FalseC);
24156 std::swap(TrueOp, FalseOp);
24159 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24160 // This is efficient for any integer data type (including i8/i16) and
24162 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24163 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24164 DAG.getConstant(CC, DL, MVT::i8), Cond);
24166 // Zero extend the condition if needed.
24167 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24169 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24170 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24171 DAG.getConstant(ShAmt, DL, MVT::i8));
24172 if (N->getNumValues() == 2) // Dead flag value?
24173 return DCI.CombineTo(N, Cond, SDValue());
24177 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24178 // for any integer data type, including i8/i16.
24179 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24180 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24181 DAG.getConstant(CC, DL, MVT::i8), Cond);
24183 // Zero extend the condition if needed.
24184 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24185 FalseC->getValueType(0), Cond);
24186 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24187 SDValue(FalseC, 0));
24189 if (N->getNumValues() == 2) // Dead flag value?
24190 return DCI.CombineTo(N, Cond, SDValue());
24194 // Optimize cases that will turn into an LEA instruction. This requires
24195 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24196 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24197 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24198 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24200 bool isFastMultiplier = false;
24202 switch ((unsigned char)Diff) {
24204 case 1: // result = add base, cond
24205 case 2: // result = lea base( , cond*2)
24206 case 3: // result = lea base(cond, cond*2)
24207 case 4: // result = lea base( , cond*4)
24208 case 5: // result = lea base(cond, cond*4)
24209 case 8: // result = lea base( , cond*8)
24210 case 9: // result = lea base(cond, cond*8)
24211 isFastMultiplier = true;
24216 if (isFastMultiplier) {
24217 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24218 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24219 DAG.getConstant(CC, DL, MVT::i8), Cond);
24220 // Zero extend the condition if needed.
24221 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24223 // Scale the condition by the difference.
24225 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24226 DAG.getConstant(Diff, DL, Cond.getValueType()));
24228 // Add the base if non-zero.
24229 if (FalseC->getAPIntValue() != 0)
24230 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24231 SDValue(FalseC, 0));
24232 if (N->getNumValues() == 2) // Dead flag value?
24233 return DCI.CombineTo(N, Cond, SDValue());
24240 // Handle these cases:
24241 // (select (x != c), e, c) -> select (x != c), e, x),
24242 // (select (x == c), c, e) -> select (x == c), x, e)
24243 // where the c is an integer constant, and the "select" is the combination
24244 // of CMOV and CMP.
24246 // The rationale for this change is that the conditional-move from a constant
24247 // needs two instructions, however, conditional-move from a register needs
24248 // only one instruction.
24250 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24251 // some instruction-combining opportunities. This opt needs to be
24252 // postponed as late as possible.
24254 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24255 // the DCI.xxxx conditions are provided to postpone the optimization as
24256 // late as possible.
24258 ConstantSDNode *CmpAgainst = nullptr;
24259 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24260 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24261 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24263 if (CC == X86::COND_NE &&
24264 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24265 CC = X86::GetOppositeBranchCondition(CC);
24266 std::swap(TrueOp, FalseOp);
24269 if (CC == X86::COND_E &&
24270 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24271 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24272 DAG.getConstant(CC, DL, MVT::i8), Cond };
24273 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24278 // Fold and/or of setcc's to double CMOV:
24279 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24280 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24282 // This combine lets us generate:
24283 // cmovcc1 (jcc1 if we don't have CMOV)
24289 // cmovne (jne if we don't have CMOV)
24290 // When we can't use the CMOV instruction, it might increase branch
24292 // When we can use CMOV, or when there is no mispredict, this improves
24293 // throughput and reduces register pressure.
24295 if (CC == X86::COND_NE) {
24297 X86::CondCode CC0, CC1;
24299 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24301 std::swap(FalseOp, TrueOp);
24302 CC0 = X86::GetOppositeBranchCondition(CC0);
24303 CC1 = X86::GetOppositeBranchCondition(CC1);
24306 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24308 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24309 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24310 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24311 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24319 /// PerformMulCombine - Optimize a single multiply with constant into two
24320 /// in order to implement it with two cheaper instructions, e.g.
24321 /// LEA + SHL, LEA + LEA.
24322 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24323 TargetLowering::DAGCombinerInfo &DCI) {
24324 // An imul is usually smaller than the alternative sequence.
24325 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24328 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24331 EVT VT = N->getValueType(0);
24332 if (VT != MVT::i64 && VT != MVT::i32)
24335 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24338 uint64_t MulAmt = C->getZExtValue();
24339 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24342 uint64_t MulAmt1 = 0;
24343 uint64_t MulAmt2 = 0;
24344 if ((MulAmt % 9) == 0) {
24346 MulAmt2 = MulAmt / 9;
24347 } else if ((MulAmt % 5) == 0) {
24349 MulAmt2 = MulAmt / 5;
24350 } else if ((MulAmt % 3) == 0) {
24352 MulAmt2 = MulAmt / 3;
24355 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24358 if (isPowerOf2_64(MulAmt2) &&
24359 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24360 // If second multiplifer is pow2, issue it first. We want the multiply by
24361 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24363 std::swap(MulAmt1, MulAmt2);
24366 if (isPowerOf2_64(MulAmt1))
24367 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24368 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24370 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24371 DAG.getConstant(MulAmt1, DL, VT));
24373 if (isPowerOf2_64(MulAmt2))
24374 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24375 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24377 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24378 DAG.getConstant(MulAmt2, DL, VT));
24380 // Do not add new nodes to DAG combiner worklist.
24381 DCI.CombineTo(N, NewMul, false);
24386 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24387 SDValue N0 = N->getOperand(0);
24388 SDValue N1 = N->getOperand(1);
24389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24390 EVT VT = N0.getValueType();
24392 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24393 // since the result of setcc_c is all zero's or all ones.
24394 if (VT.isInteger() && !VT.isVector() &&
24395 N1C && N0.getOpcode() == ISD::AND &&
24396 N0.getOperand(1).getOpcode() == ISD::Constant) {
24397 SDValue N00 = N0.getOperand(0);
24398 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24399 APInt ShAmt = N1C->getAPIntValue();
24400 Mask = Mask.shl(ShAmt);
24401 bool MaskOK = false;
24402 // We can handle cases concerning bit-widening nodes containing setcc_c if
24403 // we carefully interrogate the mask to make sure we are semantics
24405 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24406 // of the underlying setcc_c operation if the setcc_c was zero extended.
24407 // Consider the following example:
24408 // zext(setcc_c) -> i32 0x0000FFFF
24409 // c1 -> i32 0x0000FFFF
24410 // c2 -> i32 0x00000001
24411 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24412 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24413 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24415 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24416 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24418 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24419 N00.getOpcode() == ISD::ANY_EXTEND) &&
24420 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24421 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24423 if (MaskOK && Mask != 0) {
24425 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24429 // Hardware support for vector shifts is sparse which makes us scalarize the
24430 // vector operations in many cases. Also, on sandybridge ADD is faster than
24432 // (shl V, 1) -> add V,V
24433 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24434 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24435 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24436 // We shift all of the values by one. In many cases we do not have
24437 // hardware support for this operation. This is better expressed as an ADD
24439 if (N1SplatC->getAPIntValue() == 1)
24440 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24446 /// \brief Returns a vector of 0s if the node in input is a vector logical
24447 /// shift by a constant amount which is known to be bigger than or equal
24448 /// to the vector element size in bits.
24449 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24450 const X86Subtarget *Subtarget) {
24451 EVT VT = N->getValueType(0);
24453 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24454 (!Subtarget->hasInt256() ||
24455 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24458 SDValue Amt = N->getOperand(1);
24460 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24461 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24462 APInt ShiftAmt = AmtSplat->getAPIntValue();
24463 unsigned MaxAmount =
24464 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24466 // SSE2/AVX2 logical shifts always return a vector of 0s
24467 // if the shift amount is bigger than or equal to
24468 // the element size. The constant shift amount will be
24469 // encoded as a 8-bit immediate.
24470 if (ShiftAmt.trunc(8).uge(MaxAmount))
24471 return getZeroVector(VT, Subtarget, DAG, DL);
24477 /// PerformShiftCombine - Combine shifts.
24478 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24479 TargetLowering::DAGCombinerInfo &DCI,
24480 const X86Subtarget *Subtarget) {
24481 if (N->getOpcode() == ISD::SHL)
24482 if (SDValue V = PerformSHLCombine(N, DAG))
24485 // Try to fold this logical shift into a zero vector.
24486 if (N->getOpcode() != ISD::SRA)
24487 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24493 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24494 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24495 // and friends. Likewise for OR -> CMPNEQSS.
24496 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24497 TargetLowering::DAGCombinerInfo &DCI,
24498 const X86Subtarget *Subtarget) {
24501 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24502 // we're requiring SSE2 for both.
24503 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24504 SDValue N0 = N->getOperand(0);
24505 SDValue N1 = N->getOperand(1);
24506 SDValue CMP0 = N0->getOperand(1);
24507 SDValue CMP1 = N1->getOperand(1);
24510 // The SETCCs should both refer to the same CMP.
24511 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24514 SDValue CMP00 = CMP0->getOperand(0);
24515 SDValue CMP01 = CMP0->getOperand(1);
24516 EVT VT = CMP00.getValueType();
24518 if (VT == MVT::f32 || VT == MVT::f64) {
24519 bool ExpectingFlags = false;
24520 // Check for any users that want flags:
24521 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24522 !ExpectingFlags && UI != UE; ++UI)
24523 switch (UI->getOpcode()) {
24528 ExpectingFlags = true;
24530 case ISD::CopyToReg:
24531 case ISD::SIGN_EXTEND:
24532 case ISD::ZERO_EXTEND:
24533 case ISD::ANY_EXTEND:
24537 if (!ExpectingFlags) {
24538 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24539 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24541 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24542 X86::CondCode tmp = cc0;
24547 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24548 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24549 // FIXME: need symbolic constants for these magic numbers.
24550 // See X86ATTInstPrinter.cpp:printSSECC().
24551 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24552 if (Subtarget->hasAVX512()) {
24553 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24555 DAG.getConstant(x86cc, DL, MVT::i8));
24556 if (N->getValueType(0) != MVT::i1)
24557 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24561 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24562 CMP00.getValueType(), CMP00, CMP01,
24563 DAG.getConstant(x86cc, DL,
24566 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24567 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24569 if (is64BitFP && !Subtarget->is64Bit()) {
24570 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24571 // 64-bit integer, since that's not a legal type. Since
24572 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24573 // bits, but can do this little dance to extract the lowest 32 bits
24574 // and work with those going forward.
24575 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24577 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24578 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24579 Vector32, DAG.getIntPtrConstant(0, DL));
24583 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24584 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24585 DAG.getConstant(1, DL, IntVT));
24586 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24588 return OneBitOfTruth;
24596 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24597 /// so it can be folded inside ANDNP.
24598 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24599 EVT VT = N->getValueType(0);
24601 // Match direct AllOnes for 128 and 256-bit vectors
24602 if (ISD::isBuildVectorAllOnes(N))
24605 // Look through a bit convert.
24606 if (N->getOpcode() == ISD::BITCAST)
24607 N = N->getOperand(0).getNode();
24609 // Sometimes the operand may come from a insert_subvector building a 256-bit
24611 if (VT.is256BitVector() &&
24612 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24613 SDValue V1 = N->getOperand(0);
24614 SDValue V2 = N->getOperand(1);
24616 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24617 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24618 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24619 ISD::isBuildVectorAllOnes(V2.getNode()))
24626 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24627 // register. In most cases we actually compare or select YMM-sized registers
24628 // and mixing the two types creates horrible code. This method optimizes
24629 // some of the transition sequences.
24630 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24631 TargetLowering::DAGCombinerInfo &DCI,
24632 const X86Subtarget *Subtarget) {
24633 EVT VT = N->getValueType(0);
24634 if (!VT.is256BitVector())
24637 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24638 N->getOpcode() == ISD::ZERO_EXTEND ||
24639 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24641 SDValue Narrow = N->getOperand(0);
24642 EVT NarrowVT = Narrow->getValueType(0);
24643 if (!NarrowVT.is128BitVector())
24646 if (Narrow->getOpcode() != ISD::XOR &&
24647 Narrow->getOpcode() != ISD::AND &&
24648 Narrow->getOpcode() != ISD::OR)
24651 SDValue N0 = Narrow->getOperand(0);
24652 SDValue N1 = Narrow->getOperand(1);
24655 // The Left side has to be a trunc.
24656 if (N0.getOpcode() != ISD::TRUNCATE)
24659 // The type of the truncated inputs.
24660 EVT WideVT = N0->getOperand(0)->getValueType(0);
24664 // The right side has to be a 'trunc' or a constant vector.
24665 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24666 ConstantSDNode *RHSConstSplat = nullptr;
24667 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24668 RHSConstSplat = RHSBV->getConstantSplatNode();
24669 if (!RHSTrunc && !RHSConstSplat)
24672 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24674 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24677 // Set N0 and N1 to hold the inputs to the new wide operation.
24678 N0 = N0->getOperand(0);
24679 if (RHSConstSplat) {
24680 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24681 SDValue(RHSConstSplat, 0));
24682 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24683 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24684 } else if (RHSTrunc) {
24685 N1 = N1->getOperand(0);
24688 // Generate the wide operation.
24689 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24690 unsigned Opcode = N->getOpcode();
24692 case ISD::ANY_EXTEND:
24694 case ISD::ZERO_EXTEND: {
24695 unsigned InBits = NarrowVT.getScalarSizeInBits();
24696 APInt Mask = APInt::getAllOnesValue(InBits);
24697 Mask = Mask.zext(VT.getScalarSizeInBits());
24698 return DAG.getNode(ISD::AND, DL, VT,
24699 Op, DAG.getConstant(Mask, DL, VT));
24701 case ISD::SIGN_EXTEND:
24702 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24703 Op, DAG.getValueType(NarrowVT));
24705 llvm_unreachable("Unexpected opcode");
24709 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24710 TargetLowering::DAGCombinerInfo &DCI,
24711 const X86Subtarget *Subtarget) {
24712 SDValue N0 = N->getOperand(0);
24713 SDValue N1 = N->getOperand(1);
24716 // A vector zext_in_reg may be represented as a shuffle,
24717 // feeding into a bitcast (this represents anyext) feeding into
24718 // an and with a mask.
24719 // We'd like to try to combine that into a shuffle with zero
24720 // plus a bitcast, removing the and.
24721 if (N0.getOpcode() != ISD::BITCAST ||
24722 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24725 // The other side of the AND should be a splat of 2^C, where C
24726 // is the number of bits in the source type.
24727 if (N1.getOpcode() == ISD::BITCAST)
24728 N1 = N1.getOperand(0);
24729 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24731 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24733 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24734 EVT SrcType = Shuffle->getValueType(0);
24736 // We expect a single-source shuffle
24737 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24740 unsigned SrcSize = SrcType.getScalarSizeInBits();
24742 APInt SplatValue, SplatUndef;
24743 unsigned SplatBitSize;
24745 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24746 SplatBitSize, HasAnyUndefs))
24749 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24750 // Make sure the splat matches the mask we expect
24751 if (SplatBitSize > ResSize ||
24752 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24755 // Make sure the input and output size make sense
24756 if (SrcSize >= ResSize || ResSize % SrcSize)
24759 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24760 // The number of u's between each two values depends on the ratio between
24761 // the source and dest type.
24762 unsigned ZextRatio = ResSize / SrcSize;
24763 bool IsZext = true;
24764 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24765 if (i % ZextRatio) {
24766 if (Shuffle->getMaskElt(i) > 0) {
24772 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24773 // Expected element number
24783 // Ok, perform the transformation - replace the shuffle with
24784 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24785 // (instead of undef) where the k elements come from the zero vector.
24786 SmallVector<int, 8> Mask;
24787 unsigned NumElems = SrcType.getVectorNumElements();
24788 for (unsigned i = 0; i < NumElems; ++i)
24790 Mask.push_back(NumElems);
24792 Mask.push_back(i / ZextRatio);
24794 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24795 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24796 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24799 /// If both input operands of a logic op are being cast from floating point
24800 /// types, try to convert this into a floating point logic node to avoid
24801 /// unnecessary moves from SSE to integer registers.
24802 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24803 const X86Subtarget *Subtarget) {
24804 unsigned FPOpcode = ISD::DELETED_NODE;
24805 if (N->getOpcode() == ISD::AND)
24806 FPOpcode = X86ISD::FAND;
24807 else if (N->getOpcode() == ISD::OR)
24808 FPOpcode = X86ISD::FOR;
24809 else if (N->getOpcode() == ISD::XOR)
24810 FPOpcode = X86ISD::FXOR;
24812 assert(FPOpcode != ISD::DELETED_NODE &&
24813 "Unexpected input node for FP logic conversion");
24815 EVT VT = N->getValueType(0);
24816 SDValue N0 = N->getOperand(0);
24817 SDValue N1 = N->getOperand(1);
24819 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24820 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24821 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24822 SDValue N00 = N0.getOperand(0);
24823 SDValue N10 = N1.getOperand(0);
24824 EVT N00Type = N00.getValueType();
24825 EVT N10Type = N10.getValueType();
24826 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24827 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24828 return DAG.getBitcast(VT, FPLogic);
24834 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24835 TargetLowering::DAGCombinerInfo &DCI,
24836 const X86Subtarget *Subtarget) {
24837 if (DCI.isBeforeLegalizeOps())
24840 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24843 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24846 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24849 EVT VT = N->getValueType(0);
24850 SDValue N0 = N->getOperand(0);
24851 SDValue N1 = N->getOperand(1);
24854 // Create BEXTR instructions
24855 // BEXTR is ((X >> imm) & (2**size-1))
24856 if (VT == MVT::i32 || VT == MVT::i64) {
24857 // Check for BEXTR.
24858 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24859 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24860 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24861 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24862 if (MaskNode && ShiftNode) {
24863 uint64_t Mask = MaskNode->getZExtValue();
24864 uint64_t Shift = ShiftNode->getZExtValue();
24865 if (isMask_64(Mask)) {
24866 uint64_t MaskSize = countPopulation(Mask);
24867 if (Shift + MaskSize <= VT.getSizeInBits())
24868 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24869 DAG.getConstant(Shift | (MaskSize << 8), DL,
24878 // Want to form ANDNP nodes:
24879 // 1) In the hopes of then easily combining them with OR and AND nodes
24880 // to form PBLEND/PSIGN.
24881 // 2) To match ANDN packed intrinsics
24882 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24885 // Check LHS for vnot
24886 if (N0.getOpcode() == ISD::XOR &&
24887 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24888 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24889 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24891 // Check RHS for vnot
24892 if (N1.getOpcode() == ISD::XOR &&
24893 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24894 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24895 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24900 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24901 TargetLowering::DAGCombinerInfo &DCI,
24902 const X86Subtarget *Subtarget) {
24903 if (DCI.isBeforeLegalizeOps())
24906 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24909 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24912 SDValue N0 = N->getOperand(0);
24913 SDValue N1 = N->getOperand(1);
24914 EVT VT = N->getValueType(0);
24916 // look for psign/blend
24917 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24918 if (!Subtarget->hasSSSE3() ||
24919 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24922 // Canonicalize pandn to RHS
24923 if (N0.getOpcode() == X86ISD::ANDNP)
24925 // or (and (m, y), (pandn m, x))
24926 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24927 SDValue Mask = N1.getOperand(0);
24928 SDValue X = N1.getOperand(1);
24930 if (N0.getOperand(0) == Mask)
24931 Y = N0.getOperand(1);
24932 if (N0.getOperand(1) == Mask)
24933 Y = N0.getOperand(0);
24935 // Check to see if the mask appeared in both the AND and ANDNP and
24939 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24940 // Look through mask bitcast.
24941 if (Mask.getOpcode() == ISD::BITCAST)
24942 Mask = Mask.getOperand(0);
24943 if (X.getOpcode() == ISD::BITCAST)
24944 X = X.getOperand(0);
24945 if (Y.getOpcode() == ISD::BITCAST)
24946 Y = Y.getOperand(0);
24948 EVT MaskVT = Mask.getValueType();
24950 // Validate that the Mask operand is a vector sra node.
24951 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24952 // there is no psrai.b
24953 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24954 unsigned SraAmt = ~0;
24955 if (Mask.getOpcode() == ISD::SRA) {
24956 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24957 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24958 SraAmt = AmtConst->getZExtValue();
24959 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24960 SDValue SraC = Mask.getOperand(1);
24961 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24963 if ((SraAmt + 1) != EltBits)
24968 // Now we know we at least have a plendvb with the mask val. See if
24969 // we can form a psignb/w/d.
24970 // psign = x.type == y.type == mask.type && y = sub(0, x);
24971 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24972 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24973 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24974 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24975 "Unsupported VT for PSIGN");
24976 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24977 return DAG.getBitcast(VT, Mask);
24979 // PBLENDVB only available on SSE 4.1
24980 if (!Subtarget->hasSSE41())
24983 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24985 X = DAG.getBitcast(BlendVT, X);
24986 Y = DAG.getBitcast(BlendVT, Y);
24987 Mask = DAG.getBitcast(BlendVT, Mask);
24988 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24989 return DAG.getBitcast(VT, Mask);
24993 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24996 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24997 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24999 // SHLD/SHRD instructions have lower register pressure, but on some
25000 // platforms they have higher latency than the equivalent
25001 // series of shifts/or that would otherwise be generated.
25002 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25003 // have higher latencies and we are not optimizing for size.
25004 if (!OptForSize && Subtarget->isSHLDSlow())
25007 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25009 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25011 if (!N0.hasOneUse() || !N1.hasOneUse())
25014 SDValue ShAmt0 = N0.getOperand(1);
25015 if (ShAmt0.getValueType() != MVT::i8)
25017 SDValue ShAmt1 = N1.getOperand(1);
25018 if (ShAmt1.getValueType() != MVT::i8)
25020 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25021 ShAmt0 = ShAmt0.getOperand(0);
25022 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25023 ShAmt1 = ShAmt1.getOperand(0);
25026 unsigned Opc = X86ISD::SHLD;
25027 SDValue Op0 = N0.getOperand(0);
25028 SDValue Op1 = N1.getOperand(0);
25029 if (ShAmt0.getOpcode() == ISD::SUB) {
25030 Opc = X86ISD::SHRD;
25031 std::swap(Op0, Op1);
25032 std::swap(ShAmt0, ShAmt1);
25035 unsigned Bits = VT.getSizeInBits();
25036 if (ShAmt1.getOpcode() == ISD::SUB) {
25037 SDValue Sum = ShAmt1.getOperand(0);
25038 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25039 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25040 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25041 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25042 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25043 return DAG.getNode(Opc, DL, VT,
25045 DAG.getNode(ISD::TRUNCATE, DL,
25048 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25049 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25051 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25052 return DAG.getNode(Opc, DL, VT,
25053 N0.getOperand(0), N1.getOperand(0),
25054 DAG.getNode(ISD::TRUNCATE, DL,
25061 // Generate NEG and CMOV for integer abs.
25062 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25063 EVT VT = N->getValueType(0);
25065 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25066 // 8-bit integer abs to NEG and CMOV.
25067 if (VT.isInteger() && VT.getSizeInBits() == 8)
25070 SDValue N0 = N->getOperand(0);
25071 SDValue N1 = N->getOperand(1);
25074 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25075 // and change it to SUB and CMOV.
25076 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25077 N0.getOpcode() == ISD::ADD &&
25078 N0.getOperand(1) == N1 &&
25079 N1.getOpcode() == ISD::SRA &&
25080 N1.getOperand(0) == N0.getOperand(0))
25081 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25082 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25083 // Generate SUB & CMOV.
25084 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25085 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25087 SDValue Ops[] = { N0.getOperand(0), Neg,
25088 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25089 SDValue(Neg.getNode(), 1) };
25090 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25095 // Try to turn tests against the signbit in the form of:
25096 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25099 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25100 // This is only worth doing if the output type is i8.
25101 if (N->getValueType(0) != MVT::i8)
25104 SDValue N0 = N->getOperand(0);
25105 SDValue N1 = N->getOperand(1);
25107 // We should be performing an xor against a truncated shift.
25108 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25111 // Make sure we are performing an xor against one.
25112 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25115 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25116 SDValue Shift = N0.getOperand(0);
25117 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25120 // Make sure we are truncating from one of i16, i32 or i64.
25121 EVT ShiftTy = Shift.getValueType();
25122 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25125 // Make sure the shift amount extracts the sign bit.
25126 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25127 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25130 // Create a greater-than comparison against -1.
25131 // N.B. Using SETGE against 0 works but we want a canonical looking
25132 // comparison, using SETGT matches up with what TranslateX86CC.
25134 SDValue ShiftOp = Shift.getOperand(0);
25135 EVT ShiftOpTy = ShiftOp.getValueType();
25136 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25137 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25141 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25142 TargetLowering::DAGCombinerInfo &DCI,
25143 const X86Subtarget *Subtarget) {
25144 if (DCI.isBeforeLegalizeOps())
25147 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25150 if (Subtarget->hasCMov())
25151 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25154 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25160 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25161 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25162 TargetLowering::DAGCombinerInfo &DCI,
25163 const X86Subtarget *Subtarget) {
25164 LoadSDNode *Ld = cast<LoadSDNode>(N);
25165 EVT RegVT = Ld->getValueType(0);
25166 EVT MemVT = Ld->getMemoryVT();
25168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25170 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25171 // into two 16-byte operations.
25172 ISD::LoadExtType Ext = Ld->getExtensionType();
25174 unsigned AddressSpace = Ld->getAddressSpace();
25175 unsigned Alignment = Ld->getAlignment();
25176 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25177 Ext == ISD::NON_EXTLOAD &&
25178 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25179 AddressSpace, Alignment, &Fast) && !Fast) {
25180 unsigned NumElems = RegVT.getVectorNumElements();
25184 SDValue Ptr = Ld->getBasePtr();
25185 SDValue Increment =
25186 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25188 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25190 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25191 Ld->getPointerInfo(), Ld->isVolatile(),
25192 Ld->isNonTemporal(), Ld->isInvariant(),
25194 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25195 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25196 Ld->getPointerInfo(), Ld->isVolatile(),
25197 Ld->isNonTemporal(), Ld->isInvariant(),
25198 std::min(16U, Alignment));
25199 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25201 Load2.getValue(1));
25203 SDValue NewVec = DAG.getUNDEF(RegVT);
25204 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25205 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25206 return DCI.CombineTo(N, NewVec, TF, true);
25212 /// PerformMLOADCombine - Resolve extending loads
25213 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25214 TargetLowering::DAGCombinerInfo &DCI,
25215 const X86Subtarget *Subtarget) {
25216 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25217 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25220 EVT VT = Mld->getValueType(0);
25221 unsigned NumElems = VT.getVectorNumElements();
25222 EVT LdVT = Mld->getMemoryVT();
25225 assert(LdVT != VT && "Cannot extend to the same type");
25226 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25227 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25228 // From, To sizes and ElemCount must be pow of two
25229 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25230 "Unexpected size for extending masked load");
25232 unsigned SizeRatio = ToSz / FromSz;
25233 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25235 // Create a type on which we perform the shuffle
25236 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25237 LdVT.getScalarType(), NumElems*SizeRatio);
25238 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25240 // Convert Src0 value
25241 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25242 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25243 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25244 for (unsigned i = 0; i != NumElems; ++i)
25245 ShuffleVec[i] = i * SizeRatio;
25247 // Can't shuffle using an illegal type.
25248 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25249 "WideVecVT should be legal");
25250 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25251 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25253 // Prepare the new mask
25255 SDValue Mask = Mld->getMask();
25256 if (Mask.getValueType() == VT) {
25257 // Mask and original value have the same type
25258 NewMask = DAG.getBitcast(WideVecVT, Mask);
25259 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25260 for (unsigned i = 0; i != NumElems; ++i)
25261 ShuffleVec[i] = i * SizeRatio;
25262 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25263 ShuffleVec[i] = NumElems*SizeRatio;
25264 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25265 DAG.getConstant(0, dl, WideVecVT),
25269 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25270 unsigned WidenNumElts = NumElems*SizeRatio;
25271 unsigned MaskNumElts = VT.getVectorNumElements();
25272 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25275 unsigned NumConcat = WidenNumElts / MaskNumElts;
25276 SmallVector<SDValue, 16> Ops(NumConcat);
25277 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25279 for (unsigned i = 1; i != NumConcat; ++i)
25282 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25285 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25286 Mld->getBasePtr(), NewMask, WideSrc0,
25287 Mld->getMemoryVT(), Mld->getMemOperand(),
25289 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25290 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25292 /// PerformMSTORECombine - Resolve truncating stores
25293 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25294 const X86Subtarget *Subtarget) {
25295 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25296 if (!Mst->isTruncatingStore())
25299 EVT VT = Mst->getValue().getValueType();
25300 unsigned NumElems = VT.getVectorNumElements();
25301 EVT StVT = Mst->getMemoryVT();
25304 assert(StVT != VT && "Cannot truncate to the same type");
25305 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25306 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25310 // The truncating store is legal in some cases. For example
25311 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25312 // are designated for truncate store.
25313 // In this case we don't need any further transformations.
25314 if (TLI.isTruncStoreLegal(VT, StVT))
25317 // From, To sizes and ElemCount must be pow of two
25318 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25319 "Unexpected size for truncating masked store");
25320 // We are going to use the original vector elt for storing.
25321 // Accumulated smaller vector elements must be a multiple of the store size.
25322 assert (((NumElems * FromSz) % ToSz) == 0 &&
25323 "Unexpected ratio for truncating masked store");
25325 unsigned SizeRatio = FromSz / ToSz;
25326 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25328 // Create a type on which we perform the shuffle
25329 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25330 StVT.getScalarType(), NumElems*SizeRatio);
25332 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25334 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25335 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25336 for (unsigned i = 0; i != NumElems; ++i)
25337 ShuffleVec[i] = i * SizeRatio;
25339 // Can't shuffle using an illegal type.
25340 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25341 "WideVecVT should be legal");
25343 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25344 DAG.getUNDEF(WideVecVT),
25348 SDValue Mask = Mst->getMask();
25349 if (Mask.getValueType() == VT) {
25350 // Mask and original value have the same type
25351 NewMask = DAG.getBitcast(WideVecVT, Mask);
25352 for (unsigned i = 0; i != NumElems; ++i)
25353 ShuffleVec[i] = i * SizeRatio;
25354 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25355 ShuffleVec[i] = NumElems*SizeRatio;
25356 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25357 DAG.getConstant(0, dl, WideVecVT),
25361 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25362 unsigned WidenNumElts = NumElems*SizeRatio;
25363 unsigned MaskNumElts = VT.getVectorNumElements();
25364 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25367 unsigned NumConcat = WidenNumElts / MaskNumElts;
25368 SmallVector<SDValue, 16> Ops(NumConcat);
25369 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25371 for (unsigned i = 1; i != NumConcat; ++i)
25374 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25377 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25378 NewMask, StVT, Mst->getMemOperand(), false);
25380 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25381 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25382 const X86Subtarget *Subtarget) {
25383 StoreSDNode *St = cast<StoreSDNode>(N);
25384 EVT VT = St->getValue().getValueType();
25385 EVT StVT = St->getMemoryVT();
25387 SDValue StoredVal = St->getOperand(1);
25388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25390 // If we are saving a concatenation of two XMM registers and 32-byte stores
25391 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25393 unsigned AddressSpace = St->getAddressSpace();
25394 unsigned Alignment = St->getAlignment();
25395 if (VT.is256BitVector() && StVT == VT &&
25396 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25397 AddressSpace, Alignment, &Fast) && !Fast) {
25398 unsigned NumElems = VT.getVectorNumElements();
25402 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25403 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25406 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25407 SDValue Ptr0 = St->getBasePtr();
25408 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25410 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25411 St->getPointerInfo(), St->isVolatile(),
25412 St->isNonTemporal(), Alignment);
25413 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25414 St->getPointerInfo(), St->isVolatile(),
25415 St->isNonTemporal(),
25416 std::min(16U, Alignment));
25417 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25420 // Optimize trunc store (of multiple scalars) to shuffle and store.
25421 // First, pack all of the elements in one place. Next, store to memory
25422 // in fewer chunks.
25423 if (St->isTruncatingStore() && VT.isVector()) {
25424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25425 unsigned NumElems = VT.getVectorNumElements();
25426 assert(StVT != VT && "Cannot truncate to the same type");
25427 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25428 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25430 // The truncating store is legal in some cases. For example
25431 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25432 // are designated for truncate store.
25433 // In this case we don't need any further transformations.
25434 if (TLI.isTruncStoreLegal(VT, StVT))
25437 // From, To sizes and ElemCount must be pow of two
25438 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25439 // We are going to use the original vector elt for storing.
25440 // Accumulated smaller vector elements must be a multiple of the store size.
25441 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25443 unsigned SizeRatio = FromSz / ToSz;
25445 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25447 // Create a type on which we perform the shuffle
25448 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25449 StVT.getScalarType(), NumElems*SizeRatio);
25451 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25453 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25454 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25455 for (unsigned i = 0; i != NumElems; ++i)
25456 ShuffleVec[i] = i * SizeRatio;
25458 // Can't shuffle using an illegal type.
25459 if (!TLI.isTypeLegal(WideVecVT))
25462 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25463 DAG.getUNDEF(WideVecVT),
25465 // At this point all of the data is stored at the bottom of the
25466 // register. We now need to save it to mem.
25468 // Find the largest store unit
25469 MVT StoreType = MVT::i8;
25470 for (MVT Tp : MVT::integer_valuetypes()) {
25471 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25475 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25476 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25477 (64 <= NumElems * ToSz))
25478 StoreType = MVT::f64;
25480 // Bitcast the original vector into a vector of store-size units
25481 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25482 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25483 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25484 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25485 SmallVector<SDValue, 8> Chains;
25486 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25487 TLI.getPointerTy(DAG.getDataLayout()));
25488 SDValue Ptr = St->getBasePtr();
25490 // Perform one or more big stores into memory.
25491 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25492 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25493 StoreType, ShuffWide,
25494 DAG.getIntPtrConstant(i, dl));
25495 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25496 St->getPointerInfo(), St->isVolatile(),
25497 St->isNonTemporal(), St->getAlignment());
25498 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25499 Chains.push_back(Ch);
25502 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25505 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25506 // the FP state in cases where an emms may be missing.
25507 // A preferable solution to the general problem is to figure out the right
25508 // places to insert EMMS. This qualifies as a quick hack.
25510 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25511 if (VT.getSizeInBits() != 64)
25514 const Function *F = DAG.getMachineFunction().getFunction();
25515 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25517 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25518 if ((VT.isVector() ||
25519 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25520 isa<LoadSDNode>(St->getValue()) &&
25521 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25522 St->getChain().hasOneUse() && !St->isVolatile()) {
25523 SDNode* LdVal = St->getValue().getNode();
25524 LoadSDNode *Ld = nullptr;
25525 int TokenFactorIndex = -1;
25526 SmallVector<SDValue, 8> Ops;
25527 SDNode* ChainVal = St->getChain().getNode();
25528 // Must be a store of a load. We currently handle two cases: the load
25529 // is a direct child, and it's under an intervening TokenFactor. It is
25530 // possible to dig deeper under nested TokenFactors.
25531 if (ChainVal == LdVal)
25532 Ld = cast<LoadSDNode>(St->getChain());
25533 else if (St->getValue().hasOneUse() &&
25534 ChainVal->getOpcode() == ISD::TokenFactor) {
25535 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25536 if (ChainVal->getOperand(i).getNode() == LdVal) {
25537 TokenFactorIndex = i;
25538 Ld = cast<LoadSDNode>(St->getValue());
25540 Ops.push_back(ChainVal->getOperand(i));
25544 if (!Ld || !ISD::isNormalLoad(Ld))
25547 // If this is not the MMX case, i.e. we are just turning i64 load/store
25548 // into f64 load/store, avoid the transformation if there are multiple
25549 // uses of the loaded value.
25550 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25555 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25556 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25558 if (Subtarget->is64Bit() || F64IsLegal) {
25559 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25560 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25561 Ld->getPointerInfo(), Ld->isVolatile(),
25562 Ld->isNonTemporal(), Ld->isInvariant(),
25563 Ld->getAlignment());
25564 SDValue NewChain = NewLd.getValue(1);
25565 if (TokenFactorIndex != -1) {
25566 Ops.push_back(NewChain);
25567 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25569 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25570 St->getPointerInfo(),
25571 St->isVolatile(), St->isNonTemporal(),
25572 St->getAlignment());
25575 // Otherwise, lower to two pairs of 32-bit loads / stores.
25576 SDValue LoAddr = Ld->getBasePtr();
25577 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25578 DAG.getConstant(4, LdDL, MVT::i32));
25580 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25581 Ld->getPointerInfo(),
25582 Ld->isVolatile(), Ld->isNonTemporal(),
25583 Ld->isInvariant(), Ld->getAlignment());
25584 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25585 Ld->getPointerInfo().getWithOffset(4),
25586 Ld->isVolatile(), Ld->isNonTemporal(),
25588 MinAlign(Ld->getAlignment(), 4));
25590 SDValue NewChain = LoLd.getValue(1);
25591 if (TokenFactorIndex != -1) {
25592 Ops.push_back(LoLd);
25593 Ops.push_back(HiLd);
25594 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25597 LoAddr = St->getBasePtr();
25598 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25599 DAG.getConstant(4, StDL, MVT::i32));
25601 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25602 St->getPointerInfo(),
25603 St->isVolatile(), St->isNonTemporal(),
25604 St->getAlignment());
25605 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25606 St->getPointerInfo().getWithOffset(4),
25608 St->isNonTemporal(),
25609 MinAlign(St->getAlignment(), 4));
25610 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25613 // This is similar to the above case, but here we handle a scalar 64-bit
25614 // integer store that is extracted from a vector on a 32-bit target.
25615 // If we have SSE2, then we can treat it like a floating-point double
25616 // to get past legalization. The execution dependencies fixup pass will
25617 // choose the optimal machine instruction for the store if this really is
25618 // an integer or v2f32 rather than an f64.
25619 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25620 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25621 SDValue OldExtract = St->getOperand(1);
25622 SDValue ExtOp0 = OldExtract.getOperand(0);
25623 unsigned VecSize = ExtOp0.getValueSizeInBits();
25624 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25625 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25626 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25627 BitCast, OldExtract.getOperand(1));
25628 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25629 St->getPointerInfo(), St->isVolatile(),
25630 St->isNonTemporal(), St->getAlignment());
25636 /// Return 'true' if this vector operation is "horizontal"
25637 /// and return the operands for the horizontal operation in LHS and RHS. A
25638 /// horizontal operation performs the binary operation on successive elements
25639 /// of its first operand, then on successive elements of its second operand,
25640 /// returning the resulting values in a vector. For example, if
25641 /// A = < float a0, float a1, float a2, float a3 >
25643 /// B = < float b0, float b1, float b2, float b3 >
25644 /// then the result of doing a horizontal operation on A and B is
25645 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25646 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25647 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25648 /// set to A, RHS to B, and the routine returns 'true'.
25649 /// Note that the binary operation should have the property that if one of the
25650 /// operands is UNDEF then the result is UNDEF.
25651 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25652 // Look for the following pattern: if
25653 // A = < float a0, float a1, float a2, float a3 >
25654 // B = < float b0, float b1, float b2, float b3 >
25656 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25657 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25658 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25659 // which is A horizontal-op B.
25661 // At least one of the operands should be a vector shuffle.
25662 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25663 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25666 MVT VT = LHS.getSimpleValueType();
25668 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25669 "Unsupported vector type for horizontal add/sub");
25671 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25672 // operate independently on 128-bit lanes.
25673 unsigned NumElts = VT.getVectorNumElements();
25674 unsigned NumLanes = VT.getSizeInBits()/128;
25675 unsigned NumLaneElts = NumElts / NumLanes;
25676 assert((NumLaneElts % 2 == 0) &&
25677 "Vector type should have an even number of elements in each lane");
25678 unsigned HalfLaneElts = NumLaneElts/2;
25680 // View LHS in the form
25681 // LHS = VECTOR_SHUFFLE A, B, LMask
25682 // If LHS is not a shuffle then pretend it is the shuffle
25683 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25684 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25687 SmallVector<int, 16> LMask(NumElts);
25688 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25689 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25690 A = LHS.getOperand(0);
25691 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25692 B = LHS.getOperand(1);
25693 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25694 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25696 if (LHS.getOpcode() != ISD::UNDEF)
25698 for (unsigned i = 0; i != NumElts; ++i)
25702 // Likewise, view RHS in the form
25703 // RHS = VECTOR_SHUFFLE C, D, RMask
25705 SmallVector<int, 16> RMask(NumElts);
25706 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25707 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25708 C = RHS.getOperand(0);
25709 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25710 D = RHS.getOperand(1);
25711 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25712 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25714 if (RHS.getOpcode() != ISD::UNDEF)
25716 for (unsigned i = 0; i != NumElts; ++i)
25720 // Check that the shuffles are both shuffling the same vectors.
25721 if (!(A == C && B == D) && !(A == D && B == C))
25724 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25725 if (!A.getNode() && !B.getNode())
25728 // If A and B occur in reverse order in RHS, then "swap" them (which means
25729 // rewriting the mask).
25731 ShuffleVectorSDNode::commuteMask(RMask);
25733 // At this point LHS and RHS are equivalent to
25734 // LHS = VECTOR_SHUFFLE A, B, LMask
25735 // RHS = VECTOR_SHUFFLE A, B, RMask
25736 // Check that the masks correspond to performing a horizontal operation.
25737 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25738 for (unsigned i = 0; i != NumLaneElts; ++i) {
25739 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25741 // Ignore any UNDEF components.
25742 if (LIdx < 0 || RIdx < 0 ||
25743 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25744 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25747 // Check that successive elements are being operated on. If not, this is
25748 // not a horizontal operation.
25749 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25750 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25751 if (!(LIdx == Index && RIdx == Index + 1) &&
25752 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25757 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25758 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25762 /// Do target-specific dag combines on floating point adds.
25763 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25764 const X86Subtarget *Subtarget) {
25765 EVT VT = N->getValueType(0);
25766 SDValue LHS = N->getOperand(0);
25767 SDValue RHS = N->getOperand(1);
25769 // Try to synthesize horizontal adds from adds of shuffles.
25770 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25771 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25772 isHorizontalBinOp(LHS, RHS, true))
25773 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25777 /// Do target-specific dag combines on floating point subs.
25778 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25779 const X86Subtarget *Subtarget) {
25780 EVT VT = N->getValueType(0);
25781 SDValue LHS = N->getOperand(0);
25782 SDValue RHS = N->getOperand(1);
25784 // Try to synthesize horizontal subs from subs of shuffles.
25785 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25786 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25787 isHorizontalBinOp(LHS, RHS, false))
25788 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25792 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25793 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25794 const X86Subtarget *Subtarget) {
25795 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25797 // F[X]OR(0.0, x) -> x
25798 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25799 if (C->getValueAPF().isPosZero())
25800 return N->getOperand(1);
25802 // F[X]OR(x, 0.0) -> x
25803 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25804 if (C->getValueAPF().isPosZero())
25805 return N->getOperand(0);
25807 EVT VT = N->getValueType(0);
25808 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25810 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25811 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25813 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25814 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25815 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25816 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25817 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25822 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25823 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25824 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25826 // Only perform optimizations if UnsafeMath is used.
25827 if (!DAG.getTarget().Options.UnsafeFPMath)
25830 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25831 // into FMINC and FMAXC, which are Commutative operations.
25832 unsigned NewOp = 0;
25833 switch (N->getOpcode()) {
25834 default: llvm_unreachable("unknown opcode");
25835 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25836 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25839 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25840 N->getOperand(0), N->getOperand(1));
25843 /// Do target-specific dag combines on X86ISD::FAND nodes.
25844 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25845 // FAND(0.0, x) -> 0.0
25846 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25847 if (C->getValueAPF().isPosZero())
25848 return N->getOperand(0);
25850 // FAND(x, 0.0) -> 0.0
25851 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25852 if (C->getValueAPF().isPosZero())
25853 return N->getOperand(1);
25858 /// Do target-specific dag combines on X86ISD::FANDN nodes
25859 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25860 // FANDN(0.0, x) -> x
25861 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25862 if (C->getValueAPF().isPosZero())
25863 return N->getOperand(1);
25865 // FANDN(x, 0.0) -> 0.0
25866 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25867 if (C->getValueAPF().isPosZero())
25868 return N->getOperand(1);
25873 static SDValue PerformBTCombine(SDNode *N,
25875 TargetLowering::DAGCombinerInfo &DCI) {
25876 // BT ignores high bits in the bit index operand.
25877 SDValue Op1 = N->getOperand(1);
25878 if (Op1.hasOneUse()) {
25879 unsigned BitWidth = Op1.getValueSizeInBits();
25880 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25881 APInt KnownZero, KnownOne;
25882 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25883 !DCI.isBeforeLegalizeOps());
25884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25885 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25886 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25887 DCI.CommitTargetLoweringOpt(TLO);
25892 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25893 SDValue Op = N->getOperand(0);
25894 if (Op.getOpcode() == ISD::BITCAST)
25895 Op = Op.getOperand(0);
25896 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25897 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25898 VT.getVectorElementType().getSizeInBits() ==
25899 OpVT.getVectorElementType().getSizeInBits()) {
25900 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25905 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25906 const X86Subtarget *Subtarget) {
25907 EVT VT = N->getValueType(0);
25908 if (!VT.isVector())
25911 SDValue N0 = N->getOperand(0);
25912 SDValue N1 = N->getOperand(1);
25913 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25916 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25917 // both SSE and AVX2 since there is no sign-extended shift right
25918 // operation on a vector with 64-bit elements.
25919 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25920 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25921 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25922 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25923 SDValue N00 = N0.getOperand(0);
25925 // EXTLOAD has a better solution on AVX2,
25926 // it may be replaced with X86ISD::VSEXT node.
25927 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25928 if (!ISD::isNormalLoad(N00.getNode()))
25931 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25932 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25934 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25940 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25941 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25942 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25943 /// eliminate extend, add, and shift instructions.
25944 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25945 const X86Subtarget *Subtarget) {
25946 // TODO: This should be valid for other integer types.
25947 EVT VT = Sext->getValueType(0);
25948 if (VT != MVT::i64)
25951 // We need an 'add nsw' feeding into the 'sext'.
25952 SDValue Add = Sext->getOperand(0);
25953 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25956 // Having a constant operand to the 'add' ensures that we are not increasing
25957 // the instruction count because the constant is extended for free below.
25958 // A constant operand can also become the displacement field of an LEA.
25959 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25963 // Don't make the 'add' bigger if there's no hope of combining it with some
25964 // other 'add' or 'shl' instruction.
25965 // TODO: It may be profitable to generate simpler LEA instructions in place
25966 // of single 'add' instructions, but the cost model for selecting an LEA
25967 // currently has a high threshold.
25968 bool HasLEAPotential = false;
25969 for (auto *User : Sext->uses()) {
25970 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
25971 HasLEAPotential = true;
25975 if (!HasLEAPotential)
25978 // Everything looks good, so pull the 'sext' ahead of the 'add'.
25979 int64_t AddConstant = AddOp1->getSExtValue();
25980 SDValue AddOp0 = Add.getOperand(0);
25981 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
25982 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
25984 // The wider add is guaranteed to not wrap because both operands are
25987 Flags.setNoSignedWrap(true);
25988 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
25991 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25992 TargetLowering::DAGCombinerInfo &DCI,
25993 const X86Subtarget *Subtarget) {
25994 SDValue N0 = N->getOperand(0);
25995 EVT VT = N->getValueType(0);
25996 EVT SVT = VT.getScalarType();
25997 EVT InVT = N0.getValueType();
25998 EVT InSVT = InVT.getScalarType();
26001 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26002 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26003 // This exposes the sext to the sdivrem lowering, so that it directly extends
26004 // from AH (which we otherwise need to do contortions to access).
26005 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26006 InVT == MVT::i8 && VT == MVT::i32) {
26007 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26008 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26009 N0.getOperand(0), N0.getOperand(1));
26010 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26011 return R.getValue(1);
26014 if (!DCI.isBeforeLegalizeOps()) {
26015 if (InVT == MVT::i1) {
26016 SDValue Zero = DAG.getConstant(0, DL, VT);
26018 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26019 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26024 if (VT.isVector() && Subtarget->hasSSE2()) {
26025 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26026 EVT InVT = N.getValueType();
26027 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26028 Size / InVT.getScalarSizeInBits());
26029 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26030 DAG.getUNDEF(InVT));
26032 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26035 // If target-size is less than 128-bits, extend to a type that would extend
26036 // to 128 bits, extend that and extract the original target vector.
26037 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26038 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26039 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26040 unsigned Scale = 128 / VT.getSizeInBits();
26042 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26043 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26044 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26045 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26046 DAG.getIntPtrConstant(0, DL));
26049 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26050 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26051 if (VT.getSizeInBits() == 128 &&
26052 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26053 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26054 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26055 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26058 // On pre-AVX2 targets, split into 128-bit nodes of
26059 // ISD::SIGN_EXTEND_VECTOR_INREG.
26060 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26061 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26062 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26063 unsigned NumVecs = VT.getSizeInBits() / 128;
26064 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26065 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26066 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26068 SmallVector<SDValue, 8> Opnds;
26069 for (unsigned i = 0, Offset = 0; i != NumVecs;
26070 ++i, Offset += NumSubElts) {
26071 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26072 DAG.getIntPtrConstant(Offset, DL));
26073 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26074 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26075 Opnds.push_back(SrcVec);
26077 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26081 if (Subtarget->hasAVX() && VT.is256BitVector())
26082 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26085 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26091 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26092 const X86Subtarget* Subtarget) {
26094 EVT VT = N->getValueType(0);
26096 // Let legalize expand this if it isn't a legal type yet.
26097 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26100 EVT ScalarVT = VT.getScalarType();
26101 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26102 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26103 !Subtarget->hasAVX512()))
26106 SDValue A = N->getOperand(0);
26107 SDValue B = N->getOperand(1);
26108 SDValue C = N->getOperand(2);
26110 bool NegA = (A.getOpcode() == ISD::FNEG);
26111 bool NegB = (B.getOpcode() == ISD::FNEG);
26112 bool NegC = (C.getOpcode() == ISD::FNEG);
26114 // Negative multiplication when NegA xor NegB
26115 bool NegMul = (NegA != NegB);
26117 A = A.getOperand(0);
26119 B = B.getOperand(0);
26121 C = C.getOperand(0);
26125 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26127 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26129 return DAG.getNode(Opcode, dl, VT, A, B, C);
26132 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26133 TargetLowering::DAGCombinerInfo &DCI,
26134 const X86Subtarget *Subtarget) {
26135 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26136 // (and (i32 x86isd::setcc_carry), 1)
26137 // This eliminates the zext. This transformation is necessary because
26138 // ISD::SETCC is always legalized to i8.
26140 SDValue N0 = N->getOperand(0);
26141 EVT VT = N->getValueType(0);
26143 if (N0.getOpcode() == ISD::AND &&
26145 N0.getOperand(0).hasOneUse()) {
26146 SDValue N00 = N0.getOperand(0);
26147 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26148 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26149 if (!C || C->getZExtValue() != 1)
26151 return DAG.getNode(ISD::AND, dl, VT,
26152 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26153 N00.getOperand(0), N00.getOperand(1)),
26154 DAG.getConstant(1, dl, VT));
26158 if (N0.getOpcode() == ISD::TRUNCATE &&
26160 N0.getOperand(0).hasOneUse()) {
26161 SDValue N00 = N0.getOperand(0);
26162 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26163 return DAG.getNode(ISD::AND, dl, VT,
26164 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26165 N00.getOperand(0), N00.getOperand(1)),
26166 DAG.getConstant(1, dl, VT));
26170 if (VT.is256BitVector())
26171 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26174 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26175 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26176 // This exposes the zext to the udivrem lowering, so that it directly extends
26177 // from AH (which we otherwise need to do contortions to access).
26178 if (N0.getOpcode() == ISD::UDIVREM &&
26179 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26180 (VT == MVT::i32 || VT == MVT::i64)) {
26181 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26182 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26183 N0.getOperand(0), N0.getOperand(1));
26184 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26185 return R.getValue(1);
26191 // Optimize x == -y --> x+y == 0
26192 // x != -y --> x+y != 0
26193 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26194 const X86Subtarget* Subtarget) {
26195 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26196 SDValue LHS = N->getOperand(0);
26197 SDValue RHS = N->getOperand(1);
26198 EVT VT = N->getValueType(0);
26201 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26203 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26204 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26205 LHS.getOperand(1));
26206 return DAG.getSetCC(DL, N->getValueType(0), addV,
26207 DAG.getConstant(0, DL, addV.getValueType()), CC);
26209 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26211 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26212 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26213 RHS.getOperand(1));
26214 return DAG.getSetCC(DL, N->getValueType(0), addV,
26215 DAG.getConstant(0, DL, addV.getValueType()), CC);
26218 if (VT.getScalarType() == MVT::i1 &&
26219 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26221 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26222 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26223 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26225 if (!IsSEXT0 || !IsVZero1) {
26226 // Swap the operands and update the condition code.
26227 std::swap(LHS, RHS);
26228 CC = ISD::getSetCCSwappedOperands(CC);
26230 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26231 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26232 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26235 if (IsSEXT0 && IsVZero1) {
26236 assert(VT == LHS.getOperand(0).getValueType() &&
26237 "Uexpected operand type");
26238 if (CC == ISD::SETGT)
26239 return DAG.getConstant(0, DL, VT);
26240 if (CC == ISD::SETLE)
26241 return DAG.getConstant(1, DL, VT);
26242 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26243 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26245 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26246 "Unexpected condition code!");
26247 return LHS.getOperand(0);
26254 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26255 SDValue V0 = N->getOperand(0);
26256 SDValue V1 = N->getOperand(1);
26258 EVT VT = N->getValueType(0);
26260 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26261 // operands and changing the mask to 1. This saves us a bunch of
26262 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26263 // x86InstrInfo knows how to commute this back after instruction selection
26264 // if it would help register allocation.
26266 // TODO: If optimizing for size or a processor that doesn't suffer from
26267 // partial register update stalls, this should be transformed into a MOVSD
26268 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26270 if (VT == MVT::v2f64)
26271 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26272 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26273 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26274 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26280 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26281 // as "sbb reg,reg", since it can be extended without zext and produces
26282 // an all-ones bit which is more useful than 0/1 in some cases.
26283 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26286 return DAG.getNode(ISD::AND, DL, VT,
26287 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26288 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26290 DAG.getConstant(1, DL, VT));
26291 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26292 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26293 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26294 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26298 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26299 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26300 TargetLowering::DAGCombinerInfo &DCI,
26301 const X86Subtarget *Subtarget) {
26303 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26304 SDValue EFLAGS = N->getOperand(1);
26306 if (CC == X86::COND_A) {
26307 // Try to convert COND_A into COND_B in an attempt to facilitate
26308 // materializing "setb reg".
26310 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26311 // cannot take an immediate as its first operand.
26313 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26314 EFLAGS.getValueType().isInteger() &&
26315 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26316 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26317 EFLAGS.getNode()->getVTList(),
26318 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26319 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26320 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26324 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26325 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26327 if (CC == X86::COND_B)
26328 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26330 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26331 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26332 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26338 // Optimize branch condition evaluation.
26340 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26341 TargetLowering::DAGCombinerInfo &DCI,
26342 const X86Subtarget *Subtarget) {
26344 SDValue Chain = N->getOperand(0);
26345 SDValue Dest = N->getOperand(1);
26346 SDValue EFLAGS = N->getOperand(3);
26347 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26349 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26350 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26351 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26358 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26359 SelectionDAG &DAG) {
26360 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26361 // optimize away operation when it's from a constant.
26363 // The general transformation is:
26364 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26365 // AND(VECTOR_CMP(x,y), constant2)
26366 // constant2 = UNARYOP(constant)
26368 // Early exit if this isn't a vector operation, the operand of the
26369 // unary operation isn't a bitwise AND, or if the sizes of the operations
26370 // aren't the same.
26371 EVT VT = N->getValueType(0);
26372 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26373 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26374 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26377 // Now check that the other operand of the AND is a constant. We could
26378 // make the transformation for non-constant splats as well, but it's unclear
26379 // that would be a benefit as it would not eliminate any operations, just
26380 // perform one more step in scalar code before moving to the vector unit.
26381 if (BuildVectorSDNode *BV =
26382 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26383 // Bail out if the vector isn't a constant.
26384 if (!BV->isConstant())
26387 // Everything checks out. Build up the new and improved node.
26389 EVT IntVT = BV->getValueType(0);
26390 // Create a new constant of the appropriate type for the transformed
26392 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26393 // The AND node needs bitcasts to/from an integer vector type around it.
26394 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26395 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26396 N->getOperand(0)->getOperand(0), MaskConst);
26397 SDValue Res = DAG.getBitcast(VT, NewAnd);
26404 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26405 const X86Subtarget *Subtarget) {
26406 SDValue Op0 = N->getOperand(0);
26407 EVT VT = N->getValueType(0);
26408 EVT InVT = Op0.getValueType();
26409 EVT InSVT = InVT.getScalarType();
26410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26412 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26413 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26414 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26416 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26417 InVT.getVectorNumElements());
26418 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26420 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26421 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26423 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26429 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26430 const X86Subtarget *Subtarget) {
26431 // First try to optimize away the conversion entirely when it's
26432 // conditionally from a constant. Vectors only.
26433 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26436 // Now move on to more general possibilities.
26437 SDValue Op0 = N->getOperand(0);
26438 EVT VT = N->getValueType(0);
26439 EVT InVT = Op0.getValueType();
26440 EVT InSVT = InVT.getScalarType();
26442 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26443 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26444 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26446 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26447 InVT.getVectorNumElements());
26448 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26449 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26452 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26453 // a 32-bit target where SSE doesn't support i64->FP operations.
26454 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26455 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26456 EVT LdVT = Ld->getValueType(0);
26458 // This transformation is not supported if the result type is f16
26459 if (VT == MVT::f16)
26462 if (!Ld->isVolatile() && !VT.isVector() &&
26463 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26464 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26465 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26466 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26467 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26474 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26475 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26476 X86TargetLowering::DAGCombinerInfo &DCI) {
26477 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26478 // the result is either zero or one (depending on the input carry bit).
26479 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26480 if (X86::isZeroNode(N->getOperand(0)) &&
26481 X86::isZeroNode(N->getOperand(1)) &&
26482 // We don't have a good way to replace an EFLAGS use, so only do this when
26484 SDValue(N, 1).use_empty()) {
26486 EVT VT = N->getValueType(0);
26487 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26488 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26489 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26490 DAG.getConstant(X86::COND_B, DL,
26493 DAG.getConstant(1, DL, VT));
26494 return DCI.CombineTo(N, Res1, CarryOut);
26500 // fold (add Y, (sete X, 0)) -> adc 0, Y
26501 // (add Y, (setne X, 0)) -> sbb -1, Y
26502 // (sub (sete X, 0), Y) -> sbb 0, Y
26503 // (sub (setne X, 0), Y) -> adc -1, Y
26504 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26507 // Look through ZExts.
26508 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26509 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26512 SDValue SetCC = Ext.getOperand(0);
26513 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26516 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26517 if (CC != X86::COND_E && CC != X86::COND_NE)
26520 SDValue Cmp = SetCC.getOperand(1);
26521 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26522 !X86::isZeroNode(Cmp.getOperand(1)) ||
26523 !Cmp.getOperand(0).getValueType().isInteger())
26526 SDValue CmpOp0 = Cmp.getOperand(0);
26527 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26528 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26530 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26531 if (CC == X86::COND_NE)
26532 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26533 DL, OtherVal.getValueType(), OtherVal,
26534 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26536 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26537 DL, OtherVal.getValueType(), OtherVal,
26538 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26541 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26542 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26543 const X86Subtarget *Subtarget) {
26544 EVT VT = N->getValueType(0);
26545 SDValue Op0 = N->getOperand(0);
26546 SDValue Op1 = N->getOperand(1);
26548 // Try to synthesize horizontal adds from adds of shuffles.
26549 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26550 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26551 isHorizontalBinOp(Op0, Op1, true))
26552 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26554 return OptimizeConditionalInDecrement(N, DAG);
26557 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26558 const X86Subtarget *Subtarget) {
26559 SDValue Op0 = N->getOperand(0);
26560 SDValue Op1 = N->getOperand(1);
26562 // X86 can't encode an immediate LHS of a sub. See if we can push the
26563 // negation into a preceding instruction.
26564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26565 // If the RHS of the sub is a XOR with one use and a constant, invert the
26566 // immediate. Then add one to the LHS of the sub so we can turn
26567 // X-Y -> X+~Y+1, saving one register.
26568 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26569 isa<ConstantSDNode>(Op1.getOperand(1))) {
26570 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26571 EVT VT = Op0.getValueType();
26572 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26574 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26575 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26576 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26580 // Try to synthesize horizontal adds from adds of shuffles.
26581 EVT VT = N->getValueType(0);
26582 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26583 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26584 isHorizontalBinOp(Op0, Op1, true))
26585 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26587 return OptimizeConditionalInDecrement(N, DAG);
26590 /// performVZEXTCombine - Performs build vector combines
26591 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26592 TargetLowering::DAGCombinerInfo &DCI,
26593 const X86Subtarget *Subtarget) {
26595 MVT VT = N->getSimpleValueType(0);
26596 SDValue Op = N->getOperand(0);
26597 MVT OpVT = Op.getSimpleValueType();
26598 MVT OpEltVT = OpVT.getVectorElementType();
26599 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26601 // (vzext (bitcast (vzext (x)) -> (vzext x)
26603 while (V.getOpcode() == ISD::BITCAST)
26604 V = V.getOperand(0);
26606 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26607 MVT InnerVT = V.getSimpleValueType();
26608 MVT InnerEltVT = InnerVT.getVectorElementType();
26610 // If the element sizes match exactly, we can just do one larger vzext. This
26611 // is always an exact type match as vzext operates on integer types.
26612 if (OpEltVT == InnerEltVT) {
26613 assert(OpVT == InnerVT && "Types must match for vzext!");
26614 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26617 // The only other way we can combine them is if only a single element of the
26618 // inner vzext is used in the input to the outer vzext.
26619 if (InnerEltVT.getSizeInBits() < InputBits)
26622 // In this case, the inner vzext is completely dead because we're going to
26623 // only look at bits inside of the low element. Just do the outer vzext on
26624 // a bitcast of the input to the inner.
26625 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26628 // Check if we can bypass extracting and re-inserting an element of an input
26629 // vector. Essentially:
26630 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26631 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26632 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26633 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26634 SDValue ExtractedV = V.getOperand(0);
26635 SDValue OrigV = ExtractedV.getOperand(0);
26636 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26637 if (ExtractIdx->getZExtValue() == 0) {
26638 MVT OrigVT = OrigV.getSimpleValueType();
26639 // Extract a subvector if necessary...
26640 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26641 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26642 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26643 OrigVT.getVectorNumElements() / Ratio);
26644 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26645 DAG.getIntPtrConstant(0, DL));
26647 Op = DAG.getBitcast(OpVT, OrigV);
26648 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26655 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26656 DAGCombinerInfo &DCI) const {
26657 SelectionDAG &DAG = DCI.DAG;
26658 switch (N->getOpcode()) {
26660 case ISD::EXTRACT_VECTOR_ELT:
26661 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26664 case X86ISD::SHRUNKBLEND:
26665 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26666 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
26667 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26668 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26669 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26670 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26671 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26674 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26675 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26676 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26677 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26678 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26679 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26680 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26681 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26682 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26683 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26684 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26685 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26687 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26689 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26690 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26691 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26692 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26693 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26694 case ISD::ANY_EXTEND:
26695 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26696 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26697 case ISD::SIGN_EXTEND_INREG:
26698 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26699 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26700 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26701 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26702 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26703 case X86ISD::SHUFP: // Handle all target specific shuffles
26704 case X86ISD::PALIGNR:
26705 case X86ISD::UNPCKH:
26706 case X86ISD::UNPCKL:
26707 case X86ISD::MOVHLPS:
26708 case X86ISD::MOVLHPS:
26709 case X86ISD::PSHUFB:
26710 case X86ISD::PSHUFD:
26711 case X86ISD::PSHUFHW:
26712 case X86ISD::PSHUFLW:
26713 case X86ISD::MOVSS:
26714 case X86ISD::MOVSD:
26715 case X86ISD::VPERMILPI:
26716 case X86ISD::VPERM2X128:
26717 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26718 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26719 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26725 /// isTypeDesirableForOp - Return true if the target has native support for
26726 /// the specified value type and it is 'desirable' to use the type for the
26727 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26728 /// instruction encodings are longer and some i16 instructions are slow.
26729 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26730 if (!isTypeLegal(VT))
26732 if (VT != MVT::i16)
26739 case ISD::SIGN_EXTEND:
26740 case ISD::ZERO_EXTEND:
26741 case ISD::ANY_EXTEND:
26754 /// IsDesirableToPromoteOp - This method query the target whether it is
26755 /// beneficial for dag combiner to promote the specified node. If true, it
26756 /// should return the desired promotion type by reference.
26757 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26758 EVT VT = Op.getValueType();
26759 if (VT != MVT::i16)
26762 bool Promote = false;
26763 bool Commute = false;
26764 switch (Op.getOpcode()) {
26767 LoadSDNode *LD = cast<LoadSDNode>(Op);
26768 // If the non-extending load has a single use and it's not live out, then it
26769 // might be folded.
26770 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26771 Op.hasOneUse()*/) {
26772 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26773 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26774 // The only case where we'd want to promote LOAD (rather then it being
26775 // promoted as an operand is when it's only use is liveout.
26776 if (UI->getOpcode() != ISD::CopyToReg)
26783 case ISD::SIGN_EXTEND:
26784 case ISD::ZERO_EXTEND:
26785 case ISD::ANY_EXTEND:
26790 SDValue N0 = Op.getOperand(0);
26791 // Look out for (store (shl (load), x)).
26792 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26805 SDValue N0 = Op.getOperand(0);
26806 SDValue N1 = Op.getOperand(1);
26807 if (!Commute && MayFoldLoad(N1))
26809 // Avoid disabling potential load folding opportunities.
26810 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26812 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26822 //===----------------------------------------------------------------------===//
26823 // X86 Inline Assembly Support
26824 //===----------------------------------------------------------------------===//
26826 // Helper to match a string separated by whitespace.
26827 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26828 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26830 for (StringRef Piece : Pieces) {
26831 if (!S.startswith(Piece)) // Check if the piece matches.
26834 S = S.substr(Piece.size());
26835 StringRef::size_type Pos = S.find_first_not_of(" \t");
26836 if (Pos == 0) // We matched a prefix.
26845 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26847 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26848 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26849 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26850 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26852 if (AsmPieces.size() == 3)
26854 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26861 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26862 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26864 std::string AsmStr = IA->getAsmString();
26866 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26867 if (!Ty || Ty->getBitWidth() % 16 != 0)
26870 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26871 SmallVector<StringRef, 4> AsmPieces;
26872 SplitString(AsmStr, AsmPieces, ";\n");
26874 switch (AsmPieces.size()) {
26875 default: return false;
26877 // FIXME: this should verify that we are targeting a 486 or better. If not,
26878 // we will turn this bswap into something that will be lowered to logical
26879 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26880 // lower so don't worry about this.
26882 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26883 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26884 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26885 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26886 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26887 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26888 // No need to check constraints, nothing other than the equivalent of
26889 // "=r,0" would be valid here.
26890 return IntrinsicLowering::LowerToByteSwap(CI);
26893 // rorw $$8, ${0:w} --> llvm.bswap.i16
26894 if (CI->getType()->isIntegerTy(16) &&
26895 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26896 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26897 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26899 StringRef ConstraintsStr = IA->getConstraintString();
26900 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26901 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26902 if (clobbersFlagRegisters(AsmPieces))
26903 return IntrinsicLowering::LowerToByteSwap(CI);
26907 if (CI->getType()->isIntegerTy(32) &&
26908 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26909 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26910 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26911 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26913 StringRef ConstraintsStr = IA->getConstraintString();
26914 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26915 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26916 if (clobbersFlagRegisters(AsmPieces))
26917 return IntrinsicLowering::LowerToByteSwap(CI);
26920 if (CI->getType()->isIntegerTy(64)) {
26921 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26922 if (Constraints.size() >= 2 &&
26923 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26924 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26925 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26926 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26927 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26928 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26929 return IntrinsicLowering::LowerToByteSwap(CI);
26937 /// getConstraintType - Given a constraint letter, return the type of
26938 /// constraint it is for this target.
26939 X86TargetLowering::ConstraintType
26940 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26941 if (Constraint.size() == 1) {
26942 switch (Constraint[0]) {
26953 return C_RegisterClass;
26977 return TargetLowering::getConstraintType(Constraint);
26980 /// Examine constraint type and operand type and determine a weight value.
26981 /// This object must already have been set up with the operand type
26982 /// and the current alternative constraint selected.
26983 TargetLowering::ConstraintWeight
26984 X86TargetLowering::getSingleConstraintMatchWeight(
26985 AsmOperandInfo &info, const char *constraint) const {
26986 ConstraintWeight weight = CW_Invalid;
26987 Value *CallOperandVal = info.CallOperandVal;
26988 // If we don't have a value, we can't do a match,
26989 // but allow it at the lowest weight.
26990 if (!CallOperandVal)
26992 Type *type = CallOperandVal->getType();
26993 // Look at the constraint type.
26994 switch (*constraint) {
26996 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27007 if (CallOperandVal->getType()->isIntegerTy())
27008 weight = CW_SpecificReg;
27013 if (type->isFloatingPointTy())
27014 weight = CW_SpecificReg;
27017 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27018 weight = CW_SpecificReg;
27022 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27023 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27024 weight = CW_Register;
27027 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27028 if (C->getZExtValue() <= 31)
27029 weight = CW_Constant;
27033 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27034 if (C->getZExtValue() <= 63)
27035 weight = CW_Constant;
27039 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27040 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27041 weight = CW_Constant;
27045 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27046 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27047 weight = CW_Constant;
27051 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27052 if (C->getZExtValue() <= 3)
27053 weight = CW_Constant;
27057 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27058 if (C->getZExtValue() <= 0xff)
27059 weight = CW_Constant;
27064 if (isa<ConstantFP>(CallOperandVal)) {
27065 weight = CW_Constant;
27069 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27070 if ((C->getSExtValue() >= -0x80000000LL) &&
27071 (C->getSExtValue() <= 0x7fffffffLL))
27072 weight = CW_Constant;
27076 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27077 if (C->getZExtValue() <= 0xffffffff)
27078 weight = CW_Constant;
27085 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27086 /// with another that has more specific requirements based on the type of the
27087 /// corresponding operand.
27088 const char *X86TargetLowering::
27089 LowerXConstraint(EVT ConstraintVT) const {
27090 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27091 // 'f' like normal targets.
27092 if (ConstraintVT.isFloatingPoint()) {
27093 if (Subtarget->hasSSE2())
27095 if (Subtarget->hasSSE1())
27099 return TargetLowering::LowerXConstraint(ConstraintVT);
27102 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27103 /// vector. If it is invalid, don't add anything to Ops.
27104 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27105 std::string &Constraint,
27106 std::vector<SDValue>&Ops,
27107 SelectionDAG &DAG) const {
27110 // Only support length 1 constraints for now.
27111 if (Constraint.length() > 1) return;
27113 char ConstraintLetter = Constraint[0];
27114 switch (ConstraintLetter) {
27117 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27118 if (C->getZExtValue() <= 31) {
27119 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27120 Op.getValueType());
27126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27127 if (C->getZExtValue() <= 63) {
27128 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27129 Op.getValueType());
27135 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27136 if (isInt<8>(C->getSExtValue())) {
27137 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27138 Op.getValueType());
27144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27145 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27146 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27147 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27148 Op.getValueType());
27154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27155 if (C->getZExtValue() <= 3) {
27156 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27157 Op.getValueType());
27163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27164 if (C->getZExtValue() <= 255) {
27165 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27166 Op.getValueType());
27172 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27173 if (C->getZExtValue() <= 127) {
27174 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27175 Op.getValueType());
27181 // 32-bit signed value
27182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27183 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27184 C->getSExtValue())) {
27185 // Widen to 64 bits here to get it sign extended.
27186 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27189 // FIXME gcc accepts some relocatable values here too, but only in certain
27190 // memory models; it's complicated.
27195 // 32-bit unsigned value
27196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27197 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27198 C->getZExtValue())) {
27199 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27200 Op.getValueType());
27204 // FIXME gcc accepts some relocatable values here too, but only in certain
27205 // memory models; it's complicated.
27209 // Literal immediates are always ok.
27210 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27211 // Widen to 64 bits here to get it sign extended.
27212 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27216 // In any sort of PIC mode addresses need to be computed at runtime by
27217 // adding in a register or some sort of table lookup. These can't
27218 // be used as immediates.
27219 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27222 // If we are in non-pic codegen mode, we allow the address of a global (with
27223 // an optional displacement) to be used with 'i'.
27224 GlobalAddressSDNode *GA = nullptr;
27225 int64_t Offset = 0;
27227 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27229 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27230 Offset += GA->getOffset();
27232 } else if (Op.getOpcode() == ISD::ADD) {
27233 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27234 Offset += C->getZExtValue();
27235 Op = Op.getOperand(0);
27238 } else if (Op.getOpcode() == ISD::SUB) {
27239 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27240 Offset += -C->getZExtValue();
27241 Op = Op.getOperand(0);
27246 // Otherwise, this isn't something we can handle, reject it.
27250 const GlobalValue *GV = GA->getGlobal();
27251 // If we require an extra load to get this address, as in PIC mode, we
27252 // can't accept it.
27253 if (isGlobalStubReference(
27254 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27257 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27258 GA->getValueType(0), Offset);
27263 if (Result.getNode()) {
27264 Ops.push_back(Result);
27267 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27270 std::pair<unsigned, const TargetRegisterClass *>
27271 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27272 StringRef Constraint,
27274 // First, see if this is a constraint that directly corresponds to an LLVM
27276 if (Constraint.size() == 1) {
27277 // GCC Constraint Letters
27278 switch (Constraint[0]) {
27280 // TODO: Slight differences here in allocation order and leaving
27281 // RIP in the class. Do they matter any more here than they do
27282 // in the normal allocation?
27283 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27284 if (Subtarget->is64Bit()) {
27285 if (VT == MVT::i32 || VT == MVT::f32)
27286 return std::make_pair(0U, &X86::GR32RegClass);
27287 if (VT == MVT::i16)
27288 return std::make_pair(0U, &X86::GR16RegClass);
27289 if (VT == MVT::i8 || VT == MVT::i1)
27290 return std::make_pair(0U, &X86::GR8RegClass);
27291 if (VT == MVT::i64 || VT == MVT::f64)
27292 return std::make_pair(0U, &X86::GR64RegClass);
27295 // 32-bit fallthrough
27296 case 'Q': // Q_REGS
27297 if (VT == MVT::i32 || VT == MVT::f32)
27298 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27299 if (VT == MVT::i16)
27300 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27301 if (VT == MVT::i8 || VT == MVT::i1)
27302 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27303 if (VT == MVT::i64)
27304 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27306 case 'r': // GENERAL_REGS
27307 case 'l': // INDEX_REGS
27308 if (VT == MVT::i8 || VT == MVT::i1)
27309 return std::make_pair(0U, &X86::GR8RegClass);
27310 if (VT == MVT::i16)
27311 return std::make_pair(0U, &X86::GR16RegClass);
27312 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27313 return std::make_pair(0U, &X86::GR32RegClass);
27314 return std::make_pair(0U, &X86::GR64RegClass);
27315 case 'R': // LEGACY_REGS
27316 if (VT == MVT::i8 || VT == MVT::i1)
27317 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27318 if (VT == MVT::i16)
27319 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27320 if (VT == MVT::i32 || !Subtarget->is64Bit())
27321 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27322 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27323 case 'f': // FP Stack registers.
27324 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27325 // value to the correct fpstack register class.
27326 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27327 return std::make_pair(0U, &X86::RFP32RegClass);
27328 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27329 return std::make_pair(0U, &X86::RFP64RegClass);
27330 return std::make_pair(0U, &X86::RFP80RegClass);
27331 case 'y': // MMX_REGS if MMX allowed.
27332 if (!Subtarget->hasMMX()) break;
27333 return std::make_pair(0U, &X86::VR64RegClass);
27334 case 'Y': // SSE_REGS if SSE2 allowed
27335 if (!Subtarget->hasSSE2()) break;
27337 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27338 if (!Subtarget->hasSSE1()) break;
27340 switch (VT.SimpleTy) {
27342 // Scalar SSE types.
27345 return std::make_pair(0U, &X86::FR32RegClass);
27348 return std::make_pair(0U, &X86::FR64RegClass);
27356 return std::make_pair(0U, &X86::VR128RegClass);
27364 return std::make_pair(0U, &X86::VR256RegClass);
27369 return std::make_pair(0U, &X86::VR512RegClass);
27375 // Use the default implementation in TargetLowering to convert the register
27376 // constraint into a member of a register class.
27377 std::pair<unsigned, const TargetRegisterClass*> Res;
27378 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27380 // Not found as a standard register?
27382 // Map st(0) -> st(7) -> ST0
27383 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27384 tolower(Constraint[1]) == 's' &&
27385 tolower(Constraint[2]) == 't' &&
27386 Constraint[3] == '(' &&
27387 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27388 Constraint[5] == ')' &&
27389 Constraint[6] == '}') {
27391 Res.first = X86::FP0+Constraint[4]-'0';
27392 Res.second = &X86::RFP80RegClass;
27396 // GCC allows "st(0)" to be called just plain "st".
27397 if (StringRef("{st}").equals_lower(Constraint)) {
27398 Res.first = X86::FP0;
27399 Res.second = &X86::RFP80RegClass;
27404 if (StringRef("{flags}").equals_lower(Constraint)) {
27405 Res.first = X86::EFLAGS;
27406 Res.second = &X86::CCRRegClass;
27410 // 'A' means EAX + EDX.
27411 if (Constraint == "A") {
27412 Res.first = X86::EAX;
27413 Res.second = &X86::GR32_ADRegClass;
27419 // Otherwise, check to see if this is a register class of the wrong value
27420 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27421 // turn into {ax},{dx}.
27422 // MVT::Other is used to specify clobber names.
27423 if (Res.second->hasType(VT) || VT == MVT::Other)
27424 return Res; // Correct type already, nothing to do.
27426 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27427 // return "eax". This should even work for things like getting 64bit integer
27428 // registers when given an f64 type.
27429 const TargetRegisterClass *Class = Res.second;
27430 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27431 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27432 unsigned Size = VT.getSizeInBits();
27433 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27434 : Size == 16 ? MVT::i16
27435 : Size == 32 ? MVT::i32
27436 : Size == 64 ? MVT::i64
27438 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27440 Res.first = DestReg;
27441 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27442 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27443 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27444 : &X86::GR64RegClass;
27445 assert(Res.second->contains(Res.first) && "Register in register class");
27447 // No register found/type mismatch.
27449 Res.second = nullptr;
27451 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27452 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27453 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27454 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27455 Class == &X86::VR512RegClass) {
27456 // Handle references to XMM physical registers that got mapped into the
27457 // wrong class. This can happen with constraints like {xmm0} where the
27458 // target independent register mapper will just pick the first match it can
27459 // find, ignoring the required type.
27461 if (VT == MVT::f32 || VT == MVT::i32)
27462 Res.second = &X86::FR32RegClass;
27463 else if (VT == MVT::f64 || VT == MVT::i64)
27464 Res.second = &X86::FR64RegClass;
27465 else if (X86::VR128RegClass.hasType(VT))
27466 Res.second = &X86::VR128RegClass;
27467 else if (X86::VR256RegClass.hasType(VT))
27468 Res.second = &X86::VR256RegClass;
27469 else if (X86::VR512RegClass.hasType(VT))
27470 Res.second = &X86::VR512RegClass;
27472 // Type mismatch and not a clobber: Return an error;
27474 Res.second = nullptr;
27481 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27482 const AddrMode &AM, Type *Ty,
27483 unsigned AS) const {
27484 // Scaling factors are not free at all.
27485 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27486 // will take 2 allocations in the out of order engine instead of 1
27487 // for plain addressing mode, i.e. inst (reg1).
27489 // vaddps (%rsi,%drx), %ymm0, %ymm1
27490 // Requires two allocations (one for the load, one for the computation)
27492 // vaddps (%rsi), %ymm0, %ymm1
27493 // Requires just 1 allocation, i.e., freeing allocations for other operations
27494 // and having less micro operations to execute.
27496 // For some X86 architectures, this is even worse because for instance for
27497 // stores, the complex addressing mode forces the instruction to use the
27498 // "load" ports instead of the dedicated "store" port.
27499 // E.g., on Haswell:
27500 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27501 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27502 if (isLegalAddressingMode(DL, AM, Ty, AS))
27503 // Scale represents reg2 * scale, thus account for 1
27504 // as soon as we use a second register.
27505 return AM.Scale != 0;
27509 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27510 // Integer division on x86 is expensive. However, when aggressively optimizing
27511 // for code size, we prefer to use a div instruction, as it is usually smaller
27512 // than the alternative sequence.
27513 // The exception to this is vector division. Since x86 doesn't have vector
27514 // integer division, leaving the division as-is is a loss even in terms of
27515 // size, because it will have to be scalarized, while the alternative code
27516 // sequence can be performed in vector form.
27517 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27518 Attribute::MinSize);
27519 return OptSize && !VT.isVector();
27522 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27523 TargetLowering::ArgListTy& Args) const {
27524 // The MCU psABI requires some arguments to be passed in-register.
27525 // For regular calls, the inreg arguments are marked by the front-end.
27526 // However, for compiler generated library calls, we have to patch this
27528 if (!Subtarget->isTargetMCU() || !Args.size())
27531 unsigned FreeRegs = 3;
27532 for (auto &Arg : Args) {
27533 // For library functions, we do not expect any fancy types.
27534 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27535 unsigned SizeInRegs = (Size + 31) / 32;
27536 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27539 Arg.isInReg = true;
27540 FreeRegs -= SizeInRegs;