1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!Subtarget->useSoftFloat()) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!Subtarget->useSoftFloat()) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
850 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
851 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
852 MVT VT = (MVT::SimpleValueType)i;
853 // Do not attempt to custom lower non-power-of-2 vectors
854 if (!isPowerOf2_32(VT.getVectorNumElements()))
856 // Do not attempt to custom lower non-128-bit vectors
857 if (!VT.is128BitVector())
859 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
860 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
861 setOperationAction(ISD::VSELECT, VT, Custom);
862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
865 // We support custom legalizing of sext and anyext loads for specific
866 // memory vector types which we can load as a scalar (or sequence of
867 // scalars) and extend in-register to a legal 128-bit vector type. For sext
868 // loads these must work with a single scalar load.
869 for (MVT VT : MVT::integer_vector_valuetypes()) {
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
882 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
884 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
885 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
886 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
887 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
890 if (Subtarget->is64Bit()) {
891 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
892 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
895 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
896 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
897 MVT VT = (MVT::SimpleValueType)i;
899 // Do not attempt to promote non-128-bit vectors
900 if (!VT.is128BitVector())
903 setOperationAction(ISD::AND, VT, Promote);
904 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
905 setOperationAction(ISD::OR, VT, Promote);
906 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
907 setOperationAction(ISD::XOR, VT, Promote);
908 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
909 setOperationAction(ISD::LOAD, VT, Promote);
910 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
911 setOperationAction(ISD::SELECT, VT, Promote);
912 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
915 // Custom lower v2i64 and v2f64 selects.
916 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
917 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
918 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
919 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
921 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
922 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
924 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
925 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
926 // As there is no 64-bit GPR available, we need build a special custom
927 // sequence to convert from v2i32 to v2f32.
928 if (!Subtarget->is64Bit())
929 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
931 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
932 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
934 for (MVT VT : MVT::fp_vector_valuetypes())
935 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
937 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
939 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
942 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
943 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
944 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
945 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
946 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
947 setOperationAction(ISD::FRINT, RoundedTy, Legal);
948 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
951 // FIXME: Do we need to handle scalar-to-vector here?
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 // We directly match byte blends in the backend as they match the VSELECT
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
958 // SSE41 brings specific instructions for doing vector sign extend even in
959 // cases where we don't have SRA.
960 for (MVT VT : MVT::integer_vector_valuetypes()) {
961 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
962 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
963 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
966 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
967 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
968 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
969 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
970 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
971 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
972 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
974 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
975 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
976 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
977 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
978 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
979 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
981 // i8 and i16 vectors are custom because the source register and source
982 // source memory operand types are not the same width. f32 vectors are
983 // custom since the immediate controlling the insert encodes additional
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
995 // FIXME: these should be Legal, but that's only for the case where
996 // the index is constant. For now custom expand to deal with that.
997 if (Subtarget->is64Bit()) {
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1003 if (Subtarget->hasSSE2()) {
1004 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1009 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1011 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1012 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1014 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1015 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1017 // In the customized shift lowering, the legal cases in AVX2 will be
1019 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1020 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1022 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1023 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1025 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1028 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1029 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1031 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1032 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1033 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1034 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1036 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1037 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1038 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1040 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1047 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1050 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1051 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1053 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1060 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1063 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1064 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1066 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1067 // even though v8i16 is a legal type.
1068 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1069 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1070 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1072 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1073 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1074 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1079 for (MVT VT : MVT::fp_vector_valuetypes())
1080 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1082 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1083 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1085 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1086 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1088 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1089 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1091 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1092 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1093 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1094 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1096 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1097 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1098 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1100 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1104 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1105 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1106 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1107 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1108 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1109 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1110 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1111 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1113 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1114 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1115 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1116 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1118 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1119 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1120 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1121 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1122 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1123 setOperationAction(ISD::FMA, MVT::f32, Legal);
1124 setOperationAction(ISD::FMA, MVT::f64, Legal);
1127 if (Subtarget->hasInt256()) {
1128 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1130 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1131 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1133 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1134 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1135 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1136 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1138 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1139 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1140 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1141 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1143 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1144 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1145 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1146 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1148 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1149 // when we have a 256bit-wide blend with immediate.
1150 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1152 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1153 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1154 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1155 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1156 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1157 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1158 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1160 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1161 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1162 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1163 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1164 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1165 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1167 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1168 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1169 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1170 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1173 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1174 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1175 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1177 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1178 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1180 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1183 // In the customized shift lowering, the legal cases in AVX2 will be
1185 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1186 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1188 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1189 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1191 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1193 // Custom lower several nodes for 256-bit types.
1194 for (MVT VT : MVT::vector_valuetypes()) {
1195 if (VT.getScalarSizeInBits() >= 32) {
1196 setOperationAction(ISD::MLOAD, VT, Legal);
1197 setOperationAction(ISD::MSTORE, VT, Legal);
1199 // Extract subvector is special because the value type
1200 // (result) is 128-bit but the source is 256-bit wide.
1201 if (VT.is128BitVector()) {
1202 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1204 // Do not attempt to custom lower other non-256-bit vectors
1205 if (!VT.is256BitVector())
1208 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1209 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1210 setOperationAction(ISD::VSELECT, VT, Custom);
1211 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1213 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1214 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1215 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1218 if (Subtarget->hasInt256())
1219 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1222 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1223 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1224 MVT VT = (MVT::SimpleValueType)i;
1226 // Do not attempt to promote non-256-bit vectors
1227 if (!VT.is256BitVector())
1230 setOperationAction(ISD::AND, VT, Promote);
1231 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1232 setOperationAction(ISD::OR, VT, Promote);
1233 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1234 setOperationAction(ISD::XOR, VT, Promote);
1235 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1236 setOperationAction(ISD::LOAD, VT, Promote);
1237 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1238 setOperationAction(ISD::SELECT, VT, Promote);
1239 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1243 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1244 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1245 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1246 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1247 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1249 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1250 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1251 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1253 for (MVT VT : MVT::fp_vector_valuetypes())
1254 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1256 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1257 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1258 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1259 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1260 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1261 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1262 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1263 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1264 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1265 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1266 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1267 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1269 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1270 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1271 setOperationAction(ISD::XOR, MVT::i1, Legal);
1272 setOperationAction(ISD::OR, MVT::i1, Legal);
1273 setOperationAction(ISD::AND, MVT::i1, Legal);
1274 setOperationAction(ISD::SUB, MVT::i1, Custom);
1275 setOperationAction(ISD::ADD, MVT::i1, Custom);
1276 setOperationAction(ISD::MUL, MVT::i1, Custom);
1277 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1278 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1279 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1280 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1281 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1283 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1284 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1285 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1286 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1287 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1288 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1290 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1291 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1292 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1293 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1294 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1295 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1296 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1297 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1299 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1300 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1301 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1302 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1303 if (Subtarget->is64Bit()) {
1304 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1305 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1306 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1307 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1309 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1310 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1311 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1312 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1313 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1314 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1315 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1316 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1317 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1318 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1319 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1320 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1321 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1322 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1323 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1324 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1326 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1327 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1328 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1329 if (Subtarget->hasDQI()) {
1330 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1331 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1333 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1334 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1335 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1336 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1337 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1338 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1339 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1340 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1341 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1342 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1343 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1344 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1345 if (Subtarget->hasDQI()) {
1346 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1347 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1349 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1356 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1358 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1361 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1362 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1363 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1364 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1366 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1367 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1369 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1371 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1372 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1373 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1374 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1375 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1376 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1377 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1378 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1379 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1380 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1383 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1386 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1387 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1389 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1391 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1392 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1394 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1395 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1397 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1398 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1400 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1401 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1402 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1403 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1404 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1405 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1407 if (Subtarget->hasCDI()) {
1408 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1409 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1411 if (Subtarget->hasDQI()) {
1412 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1413 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1414 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1416 // Custom lower several nodes.
1417 for (MVT VT : MVT::vector_valuetypes()) {
1418 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1420 setOperationAction(ISD::AND, VT, Legal);
1421 setOperationAction(ISD::OR, VT, Legal);
1422 setOperationAction(ISD::XOR, VT, Legal);
1424 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1425 setOperationAction(ISD::MGATHER, VT, Custom);
1426 setOperationAction(ISD::MSCATTER, VT, Custom);
1428 // Extract subvector is special because the value type
1429 // (result) is 256/128-bit but the source is 512-bit wide.
1430 if (VT.is128BitVector() || VT.is256BitVector()) {
1431 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1433 if (VT.getVectorElementType() == MVT::i1)
1434 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1436 // Do not attempt to custom lower other non-512-bit vectors
1437 if (!VT.is512BitVector())
1440 if (EltSize >= 32) {
1441 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1442 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1443 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1444 setOperationAction(ISD::VSELECT, VT, Legal);
1445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1446 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1447 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1448 setOperationAction(ISD::MLOAD, VT, Legal);
1449 setOperationAction(ISD::MSTORE, VT, Legal);
1452 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1453 MVT VT = (MVT::SimpleValueType)i;
1455 // Do not attempt to promote non-512-bit vectors.
1456 if (!VT.is512BitVector())
1459 setOperationAction(ISD::SELECT, VT, Promote);
1460 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1464 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1465 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1466 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1468 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1469 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1471 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1472 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1473 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1474 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1475 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1476 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1477 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1478 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1479 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1480 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1481 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1482 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1483 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1484 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1485 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1486 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1487 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1488 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1489 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1490 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1491 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1492 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1493 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1494 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1495 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1496 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1497 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1499 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1500 const MVT VT = (MVT::SimpleValueType)i;
1502 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1504 // Do not attempt to promote non-512-bit vectors.
1505 if (!VT.is512BitVector())
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1515 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1516 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1517 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1519 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1520 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1521 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1522 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1523 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1524 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1525 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1526 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1527 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1528 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1530 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1531 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1532 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1533 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1534 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1535 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1536 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1537 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1540 // We want to custom lower some of our intrinsics.
1541 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1542 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1543 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1544 if (!Subtarget->is64Bit())
1545 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1547 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1548 // handle type legalization for these operations here.
1550 // FIXME: We really should do custom legalization for addition and
1551 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1552 // than generic legalization for 64-bit multiplication-with-overflow, though.
1553 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1554 // Add/Sub/Mul with overflow operations are custom lowered.
1556 setOperationAction(ISD::SADDO, VT, Custom);
1557 setOperationAction(ISD::UADDO, VT, Custom);
1558 setOperationAction(ISD::SSUBO, VT, Custom);
1559 setOperationAction(ISD::USUBO, VT, Custom);
1560 setOperationAction(ISD::SMULO, VT, Custom);
1561 setOperationAction(ISD::UMULO, VT, Custom);
1565 if (!Subtarget->is64Bit()) {
1566 // These libcalls are not available in 32-bit.
1567 setLibcallName(RTLIB::SHL_I128, nullptr);
1568 setLibcallName(RTLIB::SRL_I128, nullptr);
1569 setLibcallName(RTLIB::SRA_I128, nullptr);
1572 // Combine sin / cos into one node or libcall if possible.
1573 if (Subtarget->hasSinCos()) {
1574 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1575 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1576 if (Subtarget->isTargetDarwin()) {
1577 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1578 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1579 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1580 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1584 if (Subtarget->isTargetWin64()) {
1585 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1586 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1587 setOperationAction(ISD::SREM, MVT::i128, Custom);
1588 setOperationAction(ISD::UREM, MVT::i128, Custom);
1589 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1590 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1593 // We have target-specific dag combine patterns for the following nodes:
1594 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1595 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1596 setTargetDAGCombine(ISD::BITCAST);
1597 setTargetDAGCombine(ISD::VSELECT);
1598 setTargetDAGCombine(ISD::SELECT);
1599 setTargetDAGCombine(ISD::SHL);
1600 setTargetDAGCombine(ISD::SRA);
1601 setTargetDAGCombine(ISD::SRL);
1602 setTargetDAGCombine(ISD::OR);
1603 setTargetDAGCombine(ISD::AND);
1604 setTargetDAGCombine(ISD::ADD);
1605 setTargetDAGCombine(ISD::FADD);
1606 setTargetDAGCombine(ISD::FSUB);
1607 setTargetDAGCombine(ISD::FMA);
1608 setTargetDAGCombine(ISD::SUB);
1609 setTargetDAGCombine(ISD::LOAD);
1610 setTargetDAGCombine(ISD::MLOAD);
1611 setTargetDAGCombine(ISD::STORE);
1612 setTargetDAGCombine(ISD::MSTORE);
1613 setTargetDAGCombine(ISD::ZERO_EXTEND);
1614 setTargetDAGCombine(ISD::ANY_EXTEND);
1615 setTargetDAGCombine(ISD::SIGN_EXTEND);
1616 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1617 setTargetDAGCombine(ISD::SINT_TO_FP);
1618 setTargetDAGCombine(ISD::SETCC);
1619 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1620 setTargetDAGCombine(ISD::BUILD_VECTOR);
1621 setTargetDAGCombine(ISD::MUL);
1622 setTargetDAGCombine(ISD::XOR);
1624 computeRegisterProperties(Subtarget->getRegisterInfo());
1626 // On Darwin, -Os means optimize for size without hurting performance,
1627 // do not reduce the limit.
1628 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1629 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1630 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1631 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1632 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1633 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1634 setPrefLoopAlignment(4); // 2^4 bytes.
1636 // Predictable cmov don't hurt on atom because it's in-order.
1637 PredictableSelectIsExpensive = !Subtarget->isAtom();
1638 EnableExtLdPromotion = true;
1639 setPrefFunctionAlignment(4); // 2^4 bytes.
1641 verifyIntrinsicTables();
1644 // This has so far only been implemented for 64-bit MachO.
1645 bool X86TargetLowering::useLoadStackGuardNode() const {
1646 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1649 TargetLoweringBase::LegalizeTypeAction
1650 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1651 if (ExperimentalVectorWideningLegalization &&
1652 VT.getVectorNumElements() != 1 &&
1653 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1654 return TypeWidenVector;
1656 return TargetLoweringBase::getPreferredVectorAction(VT);
1659 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1661 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1663 const unsigned NumElts = VT.getVectorNumElements();
1664 const EVT EltVT = VT.getVectorElementType();
1665 if (VT.is512BitVector()) {
1666 if (Subtarget->hasAVX512())
1667 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1668 EltVT == MVT::f32 || EltVT == MVT::f64)
1670 case 8: return MVT::v8i1;
1671 case 16: return MVT::v16i1;
1673 if (Subtarget->hasBWI())
1674 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1676 case 32: return MVT::v32i1;
1677 case 64: return MVT::v64i1;
1681 if (VT.is256BitVector() || VT.is128BitVector()) {
1682 if (Subtarget->hasVLX())
1683 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1684 EltVT == MVT::f32 || EltVT == MVT::f64)
1686 case 2: return MVT::v2i1;
1687 case 4: return MVT::v4i1;
1688 case 8: return MVT::v8i1;
1690 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1691 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1693 case 8: return MVT::v8i1;
1694 case 16: return MVT::v16i1;
1695 case 32: return MVT::v32i1;
1699 return VT.changeVectorElementTypeToInteger();
1702 /// Helper for getByValTypeAlignment to determine
1703 /// the desired ByVal argument alignment.
1704 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1707 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1708 if (VTy->getBitWidth() == 128)
1710 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1711 unsigned EltAlign = 0;
1712 getMaxByValAlign(ATy->getElementType(), EltAlign);
1713 if (EltAlign > MaxAlign)
1714 MaxAlign = EltAlign;
1715 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1716 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1717 unsigned EltAlign = 0;
1718 getMaxByValAlign(STy->getElementType(i), EltAlign);
1719 if (EltAlign > MaxAlign)
1720 MaxAlign = EltAlign;
1727 /// Return the desired alignment for ByVal aggregate
1728 /// function arguments in the caller parameter area. For X86, aggregates
1729 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1730 /// are at 4-byte boundaries.
1731 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1732 if (Subtarget->is64Bit()) {
1733 // Max of 8 and alignment of type.
1734 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1741 if (Subtarget->hasSSE1())
1742 getMaxByValAlign(Ty, Align);
1746 /// Returns the target specific optimal type for load
1747 /// and store operations as a result of memset, memcpy, and memmove
1748 /// lowering. If DstAlign is zero that means it's safe to destination
1749 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1750 /// means there isn't a need to check it against alignment requirement,
1751 /// probably because the source does not need to be loaded. If 'IsMemset' is
1752 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1753 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1754 /// source is constant so it does not need to be loaded.
1755 /// It returns EVT::Other if the type should be determined using generic
1756 /// target-independent logic.
1758 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1759 unsigned DstAlign, unsigned SrcAlign,
1760 bool IsMemset, bool ZeroMemset,
1762 MachineFunction &MF) const {
1763 const Function *F = MF.getFunction();
1764 if ((!IsMemset || ZeroMemset) &&
1765 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1767 (Subtarget->isUnalignedMemAccessFast() ||
1768 ((DstAlign == 0 || DstAlign >= 16) &&
1769 (SrcAlign == 0 || SrcAlign >= 16)))) {
1771 if (Subtarget->hasInt256())
1773 if (Subtarget->hasFp256())
1776 if (Subtarget->hasSSE2())
1778 if (Subtarget->hasSSE1())
1780 } else if (!MemcpyStrSrc && Size >= 8 &&
1781 !Subtarget->is64Bit() &&
1782 Subtarget->hasSSE2()) {
1783 // Do not use f64 to lower memcpy if source is string constant. It's
1784 // better to use i32 to avoid the loads.
1788 if (Subtarget->is64Bit() && Size >= 8)
1793 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1795 return X86ScalarSSEf32;
1796 else if (VT == MVT::f64)
1797 return X86ScalarSSEf64;
1802 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1807 *Fast = Subtarget->isUnalignedMemAccessFast();
1811 /// Return the entry encoding for a jump table in the
1812 /// current function. The returned value is a member of the
1813 /// MachineJumpTableInfo::JTEntryKind enum.
1814 unsigned X86TargetLowering::getJumpTableEncoding() const {
1815 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1817 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1818 Subtarget->isPICStyleGOT())
1819 return MachineJumpTableInfo::EK_Custom32;
1821 // Otherwise, use the normal jump table encoding heuristics.
1822 return TargetLowering::getJumpTableEncoding();
1825 bool X86TargetLowering::useSoftFloat() const {
1826 return Subtarget->useSoftFloat();
1830 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1831 const MachineBasicBlock *MBB,
1832 unsigned uid,MCContext &Ctx) const{
1833 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1834 Subtarget->isPICStyleGOT());
1835 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1837 return MCSymbolRefExpr::create(MBB->getSymbol(),
1838 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1841 /// Returns relocation base for the given PIC jumptable.
1842 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1843 SelectionDAG &DAG) const {
1844 if (!Subtarget->is64Bit())
1845 // This doesn't have SDLoc associated with it, but is not really the
1846 // same as a Register.
1847 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1851 /// This returns the relocation base for the given PIC jumptable,
1852 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1853 const MCExpr *X86TargetLowering::
1854 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1855 MCContext &Ctx) const {
1856 // X86-64 uses RIP relative addressing based on the jump table label.
1857 if (Subtarget->isPICStyleRIPRel())
1858 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1860 // Otherwise, the reference is relative to the PIC base.
1861 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1864 std::pair<const TargetRegisterClass *, uint8_t>
1865 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1867 const TargetRegisterClass *RRC = nullptr;
1869 switch (VT.SimpleTy) {
1871 return TargetLowering::findRepresentativeClass(TRI, VT);
1872 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1873 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1876 RRC = &X86::VR64RegClass;
1878 case MVT::f32: case MVT::f64:
1879 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1880 case MVT::v4f32: case MVT::v2f64:
1881 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1883 RRC = &X86::VR128RegClass;
1886 return std::make_pair(RRC, Cost);
1889 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1890 unsigned &Offset) const {
1891 if (!Subtarget->isTargetLinux())
1894 if (Subtarget->is64Bit()) {
1895 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1897 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1909 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1910 unsigned DestAS) const {
1911 assert(SrcAS != DestAS && "Expected different address spaces!");
1913 return SrcAS < 256 && DestAS < 256;
1916 //===----------------------------------------------------------------------===//
1917 // Return Value Calling Convention Implementation
1918 //===----------------------------------------------------------------------===//
1920 #include "X86GenCallingConv.inc"
1923 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1924 MachineFunction &MF, bool isVarArg,
1925 const SmallVectorImpl<ISD::OutputArg> &Outs,
1926 LLVMContext &Context) const {
1927 SmallVector<CCValAssign, 16> RVLocs;
1928 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1929 return CCInfo.CheckReturn(Outs, RetCC_X86);
1932 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1933 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1938 X86TargetLowering::LowerReturn(SDValue Chain,
1939 CallingConv::ID CallConv, bool isVarArg,
1940 const SmallVectorImpl<ISD::OutputArg> &Outs,
1941 const SmallVectorImpl<SDValue> &OutVals,
1942 SDLoc dl, SelectionDAG &DAG) const {
1943 MachineFunction &MF = DAG.getMachineFunction();
1944 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1946 SmallVector<CCValAssign, 16> RVLocs;
1947 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1948 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1951 SmallVector<SDValue, 6> RetOps;
1952 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1953 // Operand #1 = Bytes To Pop
1954 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1957 // Copy the result values into the output registers.
1958 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1959 CCValAssign &VA = RVLocs[i];
1960 assert(VA.isRegLoc() && "Can only return in registers!");
1961 SDValue ValToCopy = OutVals[i];
1962 EVT ValVT = ValToCopy.getValueType();
1964 // Promote values to the appropriate types.
1965 if (VA.getLocInfo() == CCValAssign::SExt)
1966 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1967 else if (VA.getLocInfo() == CCValAssign::ZExt)
1968 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1969 else if (VA.getLocInfo() == CCValAssign::AExt) {
1970 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1971 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1973 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1975 else if (VA.getLocInfo() == CCValAssign::BCvt)
1976 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1978 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1979 "Unexpected FP-extend for return value.");
1981 // If this is x86-64, and we disabled SSE, we can't return FP values,
1982 // or SSE or MMX vectors.
1983 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1984 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1985 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1986 report_fatal_error("SSE register return with SSE disabled");
1988 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1989 // llvm-gcc has never done it right and no one has noticed, so this
1990 // should be OK for now.
1991 if (ValVT == MVT::f64 &&
1992 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1993 report_fatal_error("SSE2 register return with SSE2 disabled");
1995 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1996 // the RET instruction and handled by the FP Stackifier.
1997 if (VA.getLocReg() == X86::FP0 ||
1998 VA.getLocReg() == X86::FP1) {
1999 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2000 // change the value to the FP stack register class.
2001 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2002 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2003 RetOps.push_back(ValToCopy);
2004 // Don't emit a copytoreg.
2008 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2009 // which is returned in RAX / RDX.
2010 if (Subtarget->is64Bit()) {
2011 if (ValVT == MVT::x86mmx) {
2012 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2013 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2014 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2016 // If we don't have SSE2 available, convert to v4f32 so the generated
2017 // register is legal.
2018 if (!Subtarget->hasSSE2())
2019 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2024 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2025 Flag = Chain.getValue(1);
2026 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2029 // All x86 ABIs require that for returning structs by value we copy
2030 // the sret argument into %rax/%eax (depending on ABI) for the return.
2031 // We saved the argument into a virtual register in the entry block,
2032 // so now we copy the value out and into %rax/%eax.
2034 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2035 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2036 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2037 // either case FuncInfo->setSRetReturnReg() will have been called.
2038 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2039 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2042 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2043 X86::RAX : X86::EAX;
2044 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2045 Flag = Chain.getValue(1);
2047 // RAX/EAX now acts like a return value.
2048 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2051 RetOps[0] = Chain; // Update chain.
2053 // Add the flag if we have it.
2055 RetOps.push_back(Flag);
2057 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2060 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2061 if (N->getNumValues() != 1)
2063 if (!N->hasNUsesOfValue(1, 0))
2066 SDValue TCChain = Chain;
2067 SDNode *Copy = *N->use_begin();
2068 if (Copy->getOpcode() == ISD::CopyToReg) {
2069 // If the copy has a glue operand, we conservatively assume it isn't safe to
2070 // perform a tail call.
2071 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2073 TCChain = Copy->getOperand(0);
2074 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2077 bool HasRet = false;
2078 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2080 if (UI->getOpcode() != X86ISD::RET_FLAG)
2082 // If we are returning more than one value, we can definitely
2083 // not make a tail call see PR19530
2084 if (UI->getNumOperands() > 4)
2086 if (UI->getNumOperands() == 4 &&
2087 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2100 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2101 ISD::NodeType ExtendKind) const {
2103 // TODO: Is this also valid on 32-bit?
2104 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2105 ReturnMVT = MVT::i8;
2107 ReturnMVT = MVT::i32;
2109 EVT MinVT = getRegisterType(Context, ReturnMVT);
2110 return VT.bitsLT(MinVT) ? MinVT : VT;
2113 /// Lower the result values of a call into the
2114 /// appropriate copies out of appropriate physical registers.
2117 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2118 CallingConv::ID CallConv, bool isVarArg,
2119 const SmallVectorImpl<ISD::InputArg> &Ins,
2120 SDLoc dl, SelectionDAG &DAG,
2121 SmallVectorImpl<SDValue> &InVals) const {
2123 // Assign locations to each value returned by this call.
2124 SmallVector<CCValAssign, 16> RVLocs;
2125 bool Is64Bit = Subtarget->is64Bit();
2126 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2128 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2130 // Copy all of the result registers out of their specified physreg.
2131 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2132 CCValAssign &VA = RVLocs[i];
2133 EVT CopyVT = VA.getLocVT();
2135 // If this is x86-64, and we disabled SSE, we can't return FP values
2136 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2137 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2138 report_fatal_error("SSE register return with SSE disabled");
2141 // If we prefer to use the value in xmm registers, copy it out as f80 and
2142 // use a truncate to move it from fp stack reg to xmm reg.
2143 bool RoundAfterCopy = false;
2144 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2145 isScalarFPTypeInSSEReg(VA.getValVT())) {
2147 RoundAfterCopy = (CopyVT != VA.getLocVT());
2150 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2151 CopyVT, InFlag).getValue(1);
2152 SDValue Val = Chain.getValue(0);
2155 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2156 // This truncation won't change the value.
2157 DAG.getIntPtrConstant(1, dl));
2159 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2160 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2162 InFlag = Chain.getValue(2);
2163 InVals.push_back(Val);
2169 //===----------------------------------------------------------------------===//
2170 // C & StdCall & Fast Calling Convention implementation
2171 //===----------------------------------------------------------------------===//
2172 // StdCall calling convention seems to be standard for many Windows' API
2173 // routines and around. It differs from C calling convention just a little:
2174 // callee should clean up the stack, not caller. Symbols should be also
2175 // decorated in some fancy way :) It doesn't support any vector arguments.
2176 // For info on fast calling convention see Fast Calling Convention (tail call)
2177 // implementation LowerX86_32FastCCCallTo.
2179 /// CallIsStructReturn - Determines whether a call uses struct return
2181 enum StructReturnType {
2186 static StructReturnType
2187 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2189 return NotStructReturn;
2191 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2192 if (!Flags.isSRet())
2193 return NotStructReturn;
2194 if (Flags.isInReg())
2195 return RegStructReturn;
2196 return StackStructReturn;
2199 /// Determines whether a function uses struct return semantics.
2200 static StructReturnType
2201 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2203 return NotStructReturn;
2205 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2206 if (!Flags.isSRet())
2207 return NotStructReturn;
2208 if (Flags.isInReg())
2209 return RegStructReturn;
2210 return StackStructReturn;
2213 /// Make a copy of an aggregate at address specified by "Src" to address
2214 /// "Dst" with size and alignment information specified by the specific
2215 /// parameter attribute. The copy will be passed as a byval function parameter.
2217 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2218 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2220 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2222 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2223 /*isVolatile*/false, /*AlwaysInline=*/true,
2224 /*isTailCall*/false,
2225 MachinePointerInfo(), MachinePointerInfo());
2228 /// Return true if the calling convention is one that
2229 /// supports tail call optimization.
2230 static bool IsTailCallConvention(CallingConv::ID CC) {
2231 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2232 CC == CallingConv::HiPE);
2235 /// \brief Return true if the calling convention is a C calling convention.
2236 static bool IsCCallConvention(CallingConv::ID CC) {
2237 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2238 CC == CallingConv::X86_64_SysV);
2241 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2242 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2246 CallingConv::ID CalleeCC = CS.getCallingConv();
2247 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2253 /// Return true if the function is being made into
2254 /// a tailcall target by changing its ABI.
2255 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2256 bool GuaranteedTailCallOpt) {
2257 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2261 X86TargetLowering::LowerMemArgument(SDValue Chain,
2262 CallingConv::ID CallConv,
2263 const SmallVectorImpl<ISD::InputArg> &Ins,
2264 SDLoc dl, SelectionDAG &DAG,
2265 const CCValAssign &VA,
2266 MachineFrameInfo *MFI,
2268 // Create the nodes corresponding to a load from this parameter slot.
2269 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2270 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2271 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2272 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2275 // If value is passed by pointer we have address passed instead of the value
2277 bool ExtendedInMem = VA.isExtInLoc() &&
2278 VA.getValVT().getScalarType() == MVT::i1;
2280 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2281 ValVT = VA.getLocVT();
2283 ValVT = VA.getValVT();
2285 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2286 // changed with more analysis.
2287 // In case of tail call optimization mark all arguments mutable. Since they
2288 // could be overwritten by lowering of arguments in case of a tail call.
2289 if (Flags.isByVal()) {
2290 unsigned Bytes = Flags.getByValSize();
2291 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2292 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2293 return DAG.getFrameIndex(FI, getPointerTy());
2295 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2296 VA.getLocMemOffset(), isImmutable);
2297 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2298 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2299 MachinePointerInfo::getFixedStack(FI),
2300 false, false, false, 0);
2301 return ExtendedInMem ?
2302 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2306 // FIXME: Get this from tablegen.
2307 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2308 const X86Subtarget *Subtarget) {
2309 assert(Subtarget->is64Bit());
2311 if (Subtarget->isCallingConvWin64(CallConv)) {
2312 static const MCPhysReg GPR64ArgRegsWin64[] = {
2313 X86::RCX, X86::RDX, X86::R8, X86::R9
2315 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2318 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2319 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2321 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2324 // FIXME: Get this from tablegen.
2325 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2326 CallingConv::ID CallConv,
2327 const X86Subtarget *Subtarget) {
2328 assert(Subtarget->is64Bit());
2329 if (Subtarget->isCallingConvWin64(CallConv)) {
2330 // The XMM registers which might contain var arg parameters are shadowed
2331 // in their paired GPR. So we only need to save the GPR to their home
2333 // TODO: __vectorcall will change this.
2337 const Function *Fn = MF.getFunction();
2338 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2339 bool isSoftFloat = Subtarget->useSoftFloat();
2340 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2341 "SSE register cannot be used when SSE is disabled!");
2342 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2343 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2347 static const MCPhysReg XMMArgRegs64Bit[] = {
2348 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2349 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2351 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2355 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2356 CallingConv::ID CallConv,
2358 const SmallVectorImpl<ISD::InputArg> &Ins,
2361 SmallVectorImpl<SDValue> &InVals)
2363 MachineFunction &MF = DAG.getMachineFunction();
2364 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2365 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2367 const Function* Fn = MF.getFunction();
2368 if (Fn->hasExternalLinkage() &&
2369 Subtarget->isTargetCygMing() &&
2370 Fn->getName() == "main")
2371 FuncInfo->setForceFramePointer(true);
2373 MachineFrameInfo *MFI = MF.getFrameInfo();
2374 bool Is64Bit = Subtarget->is64Bit();
2375 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2377 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2378 "Var args not supported with calling convention fastcc, ghc or hipe");
2380 // Assign locations to all of the incoming arguments.
2381 SmallVector<CCValAssign, 16> ArgLocs;
2382 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2384 // Allocate shadow area for Win64
2386 CCInfo.AllocateStack(32, 8);
2388 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2390 unsigned LastVal = ~0U;
2392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2393 CCValAssign &VA = ArgLocs[i];
2394 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2396 assert(VA.getValNo() != LastVal &&
2397 "Don't support value assigned to multiple locs yet");
2399 LastVal = VA.getValNo();
2401 if (VA.isRegLoc()) {
2402 EVT RegVT = VA.getLocVT();
2403 const TargetRegisterClass *RC;
2404 if (RegVT == MVT::i32)
2405 RC = &X86::GR32RegClass;
2406 else if (Is64Bit && RegVT == MVT::i64)
2407 RC = &X86::GR64RegClass;
2408 else if (RegVT == MVT::f32)
2409 RC = &X86::FR32RegClass;
2410 else if (RegVT == MVT::f64)
2411 RC = &X86::FR64RegClass;
2412 else if (RegVT.is512BitVector())
2413 RC = &X86::VR512RegClass;
2414 else if (RegVT.is256BitVector())
2415 RC = &X86::VR256RegClass;
2416 else if (RegVT.is128BitVector())
2417 RC = &X86::VR128RegClass;
2418 else if (RegVT == MVT::x86mmx)
2419 RC = &X86::VR64RegClass;
2420 else if (RegVT == MVT::i1)
2421 RC = &X86::VK1RegClass;
2422 else if (RegVT == MVT::v8i1)
2423 RC = &X86::VK8RegClass;
2424 else if (RegVT == MVT::v16i1)
2425 RC = &X86::VK16RegClass;
2426 else if (RegVT == MVT::v32i1)
2427 RC = &X86::VK32RegClass;
2428 else if (RegVT == MVT::v64i1)
2429 RC = &X86::VK64RegClass;
2431 llvm_unreachable("Unknown argument type!");
2433 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2434 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2436 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2437 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2439 if (VA.getLocInfo() == CCValAssign::SExt)
2440 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2441 DAG.getValueType(VA.getValVT()));
2442 else if (VA.getLocInfo() == CCValAssign::ZExt)
2443 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2444 DAG.getValueType(VA.getValVT()));
2445 else if (VA.getLocInfo() == CCValAssign::BCvt)
2446 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2448 if (VA.isExtInLoc()) {
2449 // Handle MMX values passed in XMM regs.
2450 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2451 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2453 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2456 assert(VA.isMemLoc());
2457 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2460 // If value is passed via pointer - do a load.
2461 if (VA.getLocInfo() == CCValAssign::Indirect)
2462 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2463 MachinePointerInfo(), false, false, false, 0);
2465 InVals.push_back(ArgValue);
2468 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2469 // All x86 ABIs require that for returning structs by value we copy the
2470 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2471 // the argument into a virtual register so that we can access it from the
2473 if (Ins[i].Flags.isSRet()) {
2474 unsigned Reg = FuncInfo->getSRetReturnReg();
2476 MVT PtrTy = getPointerTy();
2477 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2478 FuncInfo->setSRetReturnReg(Reg);
2480 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2481 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2486 unsigned StackSize = CCInfo.getNextStackOffset();
2487 // Align stack specially for tail calls.
2488 if (FuncIsMadeTailCallSafe(CallConv,
2489 MF.getTarget().Options.GuaranteedTailCallOpt))
2490 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2492 // If the function takes variable number of arguments, make a frame index for
2493 // the start of the first vararg value... for expansion of llvm.va_start. We
2494 // can skip this if there are no va_start calls.
2495 if (MFI->hasVAStart() &&
2496 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2497 CallConv != CallingConv::X86_ThisCall))) {
2498 FuncInfo->setVarArgsFrameIndex(
2499 MFI->CreateFixedObject(1, StackSize, true));
2502 MachineModuleInfo &MMI = MF.getMMI();
2503 const Function *WinEHParent = nullptr;
2504 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2505 WinEHParent = MMI.getWinEHParent(Fn);
2506 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2507 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2509 // Figure out if XMM registers are in use.
2510 assert(!(Subtarget->useSoftFloat() &&
2511 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2512 "SSE register cannot be used when SSE is disabled!");
2514 // 64-bit calling conventions support varargs and register parameters, so we
2515 // have to do extra work to spill them in the prologue.
2516 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2517 // Find the first unallocated argument registers.
2518 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2519 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2520 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2521 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2522 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2523 "SSE register cannot be used when SSE is disabled!");
2525 // Gather all the live in physical registers.
2526 SmallVector<SDValue, 6> LiveGPRs;
2527 SmallVector<SDValue, 8> LiveXMMRegs;
2529 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2530 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2532 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2534 if (!ArgXMMs.empty()) {
2535 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2536 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2537 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2538 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2539 LiveXMMRegs.push_back(
2540 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2545 // Get to the caller-allocated home save location. Add 8 to account
2546 // for the return address.
2547 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2548 FuncInfo->setRegSaveFrameIndex(
2549 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2550 // Fixup to set vararg frame on shadow area (4 x i64).
2552 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2554 // For X86-64, if there are vararg parameters that are passed via
2555 // registers, then we must store them to their spots on the stack so
2556 // they may be loaded by deferencing the result of va_next.
2557 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2558 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2559 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2560 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2563 // Store the integer parameter registers.
2564 SmallVector<SDValue, 8> MemOps;
2565 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2567 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2568 for (SDValue Val : LiveGPRs) {
2569 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2570 DAG.getIntPtrConstant(Offset, dl));
2572 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2573 MachinePointerInfo::getFixedStack(
2574 FuncInfo->getRegSaveFrameIndex(), Offset),
2576 MemOps.push_back(Store);
2580 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2581 // Now store the XMM (fp + vector) parameter registers.
2582 SmallVector<SDValue, 12> SaveXMMOps;
2583 SaveXMMOps.push_back(Chain);
2584 SaveXMMOps.push_back(ALVal);
2585 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2586 FuncInfo->getRegSaveFrameIndex(), dl));
2587 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2588 FuncInfo->getVarArgsFPOffset(), dl));
2589 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2591 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2592 MVT::Other, SaveXMMOps));
2595 if (!MemOps.empty())
2596 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2597 } else if (IsWinEHOutlined) {
2598 // Get to the caller-allocated home save location. Add 8 to account
2599 // for the return address.
2600 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2601 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2602 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2604 MMI.getWinEHFuncInfo(Fn)
2605 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2606 FuncInfo->getRegSaveFrameIndex();
2608 // Store the second integer parameter (rdx) into rsp+16 relative to the
2609 // stack pointer at the entry of the function.
2611 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2612 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2613 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2614 Chain = DAG.getStore(
2615 Val.getValue(1), dl, Val, RSFIN,
2616 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2617 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2620 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2621 // Find the largest legal vector type.
2622 MVT VecVT = MVT::Other;
2623 // FIXME: Only some x86_32 calling conventions support AVX512.
2624 if (Subtarget->hasAVX512() &&
2625 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2626 CallConv == CallingConv::Intel_OCL_BI)))
2627 VecVT = MVT::v16f32;
2628 else if (Subtarget->hasAVX())
2630 else if (Subtarget->hasSSE2())
2633 // We forward some GPRs and some vector types.
2634 SmallVector<MVT, 2> RegParmTypes;
2635 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2636 RegParmTypes.push_back(IntVT);
2637 if (VecVT != MVT::Other)
2638 RegParmTypes.push_back(VecVT);
2640 // Compute the set of forwarded registers. The rest are scratch.
2641 SmallVectorImpl<ForwardedRegister> &Forwards =
2642 FuncInfo->getForwardedMustTailRegParms();
2643 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2645 // Conservatively forward AL on x86_64, since it might be used for varargs.
2646 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2647 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2648 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2651 // Copy all forwards from physical to virtual registers.
2652 for (ForwardedRegister &F : Forwards) {
2653 // FIXME: Can we use a less constrained schedule?
2654 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2655 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2656 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2660 // Some CCs need callee pop.
2661 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2662 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2663 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2665 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2666 // If this is an sret function, the return should pop the hidden pointer.
2667 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2668 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2669 argsAreStructReturn(Ins) == StackStructReturn)
2670 FuncInfo->setBytesToPopOnReturn(4);
2674 // RegSaveFrameIndex is X86-64 only.
2675 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2676 if (CallConv == CallingConv::X86_FastCall ||
2677 CallConv == CallingConv::X86_ThisCall)
2678 // fastcc functions can't have varargs.
2679 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2682 FuncInfo->setArgumentStackSize(StackSize);
2684 if (IsWinEHParent) {
2685 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2686 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2687 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2688 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2689 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2690 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2691 /*isVolatile=*/true,
2692 /*isNonTemporal=*/false, /*Alignment=*/0);
2699 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2700 SDValue StackPtr, SDValue Arg,
2701 SDLoc dl, SelectionDAG &DAG,
2702 const CCValAssign &VA,
2703 ISD::ArgFlagsTy Flags) const {
2704 unsigned LocMemOffset = VA.getLocMemOffset();
2705 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2706 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2707 if (Flags.isByVal())
2708 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2710 return DAG.getStore(Chain, dl, Arg, PtrOff,
2711 MachinePointerInfo::getStack(LocMemOffset),
2715 /// Emit a load of return address if tail call
2716 /// optimization is performed and it is required.
2718 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2719 SDValue &OutRetAddr, SDValue Chain,
2720 bool IsTailCall, bool Is64Bit,
2721 int FPDiff, SDLoc dl) const {
2722 // Adjust the Return address stack slot.
2723 EVT VT = getPointerTy();
2724 OutRetAddr = getReturnAddressFrameIndex(DAG);
2726 // Load the "old" Return address.
2727 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2728 false, false, false, 0);
2729 return SDValue(OutRetAddr.getNode(), 1);
2732 /// Emit a store of the return address if tail call
2733 /// optimization is performed and it is required (FPDiff!=0).
2734 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2735 SDValue Chain, SDValue RetAddrFrIdx,
2736 EVT PtrVT, unsigned SlotSize,
2737 int FPDiff, SDLoc dl) {
2738 // Store the return address to the appropriate stack slot.
2739 if (!FPDiff) return Chain;
2740 // Calculate the new stack slot for the return address.
2741 int NewReturnAddrFI =
2742 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2744 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2745 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2746 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2752 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2753 SmallVectorImpl<SDValue> &InVals) const {
2754 SelectionDAG &DAG = CLI.DAG;
2756 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2757 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2758 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2759 SDValue Chain = CLI.Chain;
2760 SDValue Callee = CLI.Callee;
2761 CallingConv::ID CallConv = CLI.CallConv;
2762 bool &isTailCall = CLI.IsTailCall;
2763 bool isVarArg = CLI.IsVarArg;
2765 MachineFunction &MF = DAG.getMachineFunction();
2766 bool Is64Bit = Subtarget->is64Bit();
2767 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2768 StructReturnType SR = callIsStructReturn(Outs);
2769 bool IsSibcall = false;
2770 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2772 if (MF.getTarget().Options.DisableTailCalls)
2775 if (Subtarget->isPICStyleGOT() &&
2776 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2777 // If we are using a GOT, disable tail calls to external symbols with
2778 // default visibility. Tail calling such a symbol requires using a GOT
2779 // relocation, which forces early binding of the symbol. This breaks code
2780 // that require lazy function symbol resolution. Using musttail or
2781 // GuaranteedTailCallOpt will override this.
2782 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2783 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2784 G->getGlobal()->hasDefaultVisibility()))
2788 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2790 // Force this to be a tail call. The verifier rules are enough to ensure
2791 // that we can lower this successfully without moving the return address
2794 } else if (isTailCall) {
2795 // Check if it's really possible to do a tail call.
2796 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2797 isVarArg, SR != NotStructReturn,
2798 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2799 Outs, OutVals, Ins, DAG);
2801 // Sibcalls are automatically detected tailcalls which do not require
2803 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2810 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2811 "Var args not supported with calling convention fastcc, ghc or hipe");
2813 // Analyze operands of the call, assigning locations to each operand.
2814 SmallVector<CCValAssign, 16> ArgLocs;
2815 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2817 // Allocate shadow area for Win64
2819 CCInfo.AllocateStack(32, 8);
2821 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2823 // Get a count of how many bytes are to be pushed on the stack.
2824 unsigned NumBytes = CCInfo.getNextStackOffset();
2826 // This is a sibcall. The memory operands are available in caller's
2827 // own caller's stack.
2829 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2830 IsTailCallConvention(CallConv))
2831 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2834 if (isTailCall && !IsSibcall && !IsMustTail) {
2835 // Lower arguments at fp - stackoffset + fpdiff.
2836 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2838 FPDiff = NumBytesCallerPushed - NumBytes;
2840 // Set the delta of movement of the returnaddr stackslot.
2841 // But only set if delta is greater than previous delta.
2842 if (FPDiff < X86Info->getTCReturnAddrDelta())
2843 X86Info->setTCReturnAddrDelta(FPDiff);
2846 unsigned NumBytesToPush = NumBytes;
2847 unsigned NumBytesToPop = NumBytes;
2849 // If we have an inalloca argument, all stack space has already been allocated
2850 // for us and be right at the top of the stack. We don't support multiple
2851 // arguments passed in memory when using inalloca.
2852 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2854 if (!ArgLocs.back().isMemLoc())
2855 report_fatal_error("cannot use inalloca attribute on a register "
2857 if (ArgLocs.back().getLocMemOffset() != 0)
2858 report_fatal_error("any parameter with the inalloca attribute must be "
2859 "the only memory argument");
2863 Chain = DAG.getCALLSEQ_START(
2864 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2866 SDValue RetAddrFrIdx;
2867 // Load return address for tail calls.
2868 if (isTailCall && FPDiff)
2869 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2870 Is64Bit, FPDiff, dl);
2872 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2873 SmallVector<SDValue, 8> MemOpChains;
2876 // Walk the register/memloc assignments, inserting copies/loads. In the case
2877 // of tail call optimization arguments are handle later.
2878 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2879 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2880 // Skip inalloca arguments, they have already been written.
2881 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2882 if (Flags.isInAlloca())
2885 CCValAssign &VA = ArgLocs[i];
2886 EVT RegVT = VA.getLocVT();
2887 SDValue Arg = OutVals[i];
2888 bool isByVal = Flags.isByVal();
2890 // Promote the value if needed.
2891 switch (VA.getLocInfo()) {
2892 default: llvm_unreachable("Unknown loc info!");
2893 case CCValAssign::Full: break;
2894 case CCValAssign::SExt:
2895 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2897 case CCValAssign::ZExt:
2898 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::AExt:
2901 if (Arg.getValueType().isVector() &&
2902 Arg.getValueType().getScalarType() == MVT::i1)
2903 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2904 else if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasLocalLinkage() &&
2973 G->getGlobal()->hasDefaultVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, dl,
3003 if (isVarArg && IsMustTail) {
3004 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3005 for (const auto &F : Forwards) {
3006 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3007 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3011 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3012 // don't need this because the eligibility check rejects calls that require
3013 // shuffling arguments passed in memory.
3014 if (!IsSibcall && isTailCall) {
3015 // Force all the incoming stack arguments to be loaded from the stack
3016 // before any new outgoing arguments are stored to the stack, because the
3017 // outgoing stack slots may alias the incoming argument stack slots, and
3018 // the alias isn't otherwise explicit. This is slightly more conservative
3019 // than necessary, because it means that each store effectively depends
3020 // on every argument instead of just those arguments it would clobber.
3021 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3023 SmallVector<SDValue, 8> MemOpChains2;
3026 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3027 CCValAssign &VA = ArgLocs[i];
3030 assert(VA.isMemLoc());
3031 SDValue Arg = OutVals[i];
3032 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3033 // Skip inalloca arguments. They don't require any work.
3034 if (Flags.isInAlloca())
3036 // Create frame index.
3037 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3038 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3039 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3040 FIN = DAG.getFrameIndex(FI, getPointerTy());
3042 if (Flags.isByVal()) {
3043 // Copy relative to framepointer.
3044 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3045 if (!StackPtr.getNode())
3046 StackPtr = DAG.getCopyFromReg(Chain, dl,
3047 RegInfo->getStackRegister(),
3049 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3051 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3055 // Store relative to framepointer.
3056 MemOpChains2.push_back(
3057 DAG.getStore(ArgChain, dl, Arg, FIN,
3058 MachinePointerInfo::getFixedStack(FI),
3063 if (!MemOpChains2.empty())
3064 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3066 // Store the return address to the appropriate stack slot.
3067 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3068 getPointerTy(), RegInfo->getSlotSize(),
3072 // Build a sequence of copy-to-reg nodes chained together with token chain
3073 // and flag operands which copy the outgoing args into registers.
3075 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3076 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3077 RegsToPass[i].second, InFlag);
3078 InFlag = Chain.getValue(1);
3081 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3082 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3083 // In the 64-bit large code model, we have to make all calls
3084 // through a register, since the call instruction's 32-bit
3085 // pc-relative offset may not be large enough to hold the whole
3087 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3088 // If the callee is a GlobalAddress node (quite common, every direct call
3089 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3091 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3093 // We should use extra load for direct calls to dllimported functions in
3095 const GlobalValue *GV = G->getGlobal();
3096 if (!GV->hasDLLImportStorageClass()) {
3097 unsigned char OpFlags = 0;
3098 bool ExtraLoad = false;
3099 unsigned WrapperKind = ISD::DELETED_NODE;
3101 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3102 // external symbols most go through the PLT in PIC mode. If the symbol
3103 // has hidden or protected visibility, or if it is static or local, then
3104 // we don't need to use the PLT - we can directly call it.
3105 if (Subtarget->isTargetELF() &&
3106 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3107 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3111 (!Subtarget->getTargetTriple().isMacOSX() ||
3112 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3113 // PC-relative references to external symbols should go through $stub,
3114 // unless we're building with the leopard linker or later, which
3115 // automatically synthesizes these stubs.
3116 OpFlags = X86II::MO_DARWIN_STUB;
3117 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3118 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3119 // If the function is marked as non-lazy, generate an indirect call
3120 // which loads from the GOT directly. This avoids runtime overhead
3121 // at the cost of eager binding (and one extra byte of encoding).
3122 OpFlags = X86II::MO_GOTPCREL;
3123 WrapperKind = X86ISD::WrapperRIP;
3127 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3128 G->getOffset(), OpFlags);
3130 // Add a wrapper if needed.
3131 if (WrapperKind != ISD::DELETED_NODE)
3132 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3133 // Add extra indirection if needed.
3135 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3136 MachinePointerInfo::getGOT(),
3137 false, false, false, 0);
3139 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3140 unsigned char OpFlags = 0;
3142 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3143 // external symbols should go through the PLT.
3144 if (Subtarget->isTargetELF() &&
3145 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3146 OpFlags = X86II::MO_PLT;
3147 } else if (Subtarget->isPICStyleStubAny() &&
3148 (!Subtarget->getTargetTriple().isMacOSX() ||
3149 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3150 // PC-relative references to external symbols should go through $stub,
3151 // unless we're building with the leopard linker or later, which
3152 // automatically synthesizes these stubs.
3153 OpFlags = X86II::MO_DARWIN_STUB;
3156 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3158 } else if (Subtarget->isTarget64BitILP32() &&
3159 Callee->getValueType(0) == MVT::i32) {
3160 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3161 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3164 // Returns a chain & a flag for retval copy to use.
3165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3166 SmallVector<SDValue, 8> Ops;
3168 if (!IsSibcall && isTailCall) {
3169 Chain = DAG.getCALLSEQ_END(Chain,
3170 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3171 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3172 InFlag = Chain.getValue(1);
3175 Ops.push_back(Chain);
3176 Ops.push_back(Callee);
3179 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3181 // Add argument registers to the end of the list so that they are known live
3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3185 RegsToPass[i].second.getValueType()));
3187 // Add a register mask operand representing the call-preserved registers.
3188 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3189 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3190 assert(Mask && "Missing call preserved mask for calling convention");
3191 Ops.push_back(DAG.getRegisterMask(Mask));
3193 if (InFlag.getNode())
3194 Ops.push_back(InFlag);
3198 //// If this is the first return lowered for this function, add the regs
3199 //// to the liveout set for the function.
3200 // This isn't right, although it's probably harmless on x86; liveouts
3201 // should be computed from returns not tail calls. Consider a void
3202 // function making a tail call to a function returning int.
3203 MF.getFrameInfo()->setHasTailCall();
3204 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3207 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3208 InFlag = Chain.getValue(1);
3210 // Create the CALLSEQ_END node.
3211 unsigned NumBytesForCalleeToPop;
3212 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3213 DAG.getTarget().Options.GuaranteedTailCallOpt))
3214 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3215 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3216 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3217 SR == StackStructReturn)
3218 // If this is a call to a struct-return function, the callee
3219 // pops the hidden struct pointer, so we have to push it back.
3220 // This is common for Darwin/X86, Linux & Mingw32 targets.
3221 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3222 NumBytesForCalleeToPop = 4;
3224 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3226 // Returns a flag for retval copy to use.
3228 Chain = DAG.getCALLSEQ_END(Chain,
3229 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3230 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3233 InFlag = Chain.getValue(1);
3236 // Handle result values, copying them out of physregs into vregs that we
3238 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3239 Ins, dl, DAG, InVals);
3242 //===----------------------------------------------------------------------===//
3243 // Fast Calling Convention (tail call) implementation
3244 //===----------------------------------------------------------------------===//
3246 // Like std call, callee cleans arguments, convention except that ECX is
3247 // reserved for storing the tail called function address. Only 2 registers are
3248 // free for argument passing (inreg). Tail call optimization is performed
3250 // * tailcallopt is enabled
3251 // * caller/callee are fastcc
3252 // On X86_64 architecture with GOT-style position independent code only local
3253 // (within module) calls are supported at the moment.
3254 // To keep the stack aligned according to platform abi the function
3255 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3256 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3257 // If a tail called function callee has more arguments than the caller the
3258 // caller needs to make sure that there is room to move the RETADDR to. This is
3259 // achieved by reserving an area the size of the argument delta right after the
3260 // original RETADDR, but before the saved framepointer or the spilled registers
3261 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3273 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3274 /// for a 16 byte align requirement.
3276 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3277 SelectionDAG& DAG) const {
3278 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3279 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3280 unsigned StackAlignment = TFI.getStackAlignment();
3281 uint64_t AlignMask = StackAlignment - 1;
3282 int64_t Offset = StackSize;
3283 unsigned SlotSize = RegInfo->getSlotSize();
3284 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3285 // Number smaller than 12 so just add the difference.
3286 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3288 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3289 Offset = ((~AlignMask) & Offset) + StackAlignment +
3290 (StackAlignment-SlotSize);
3295 /// MatchingStackOffset - Return true if the given stack call argument is
3296 /// already available in the same position (relatively) of the caller's
3297 /// incoming argument stack.
3299 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3300 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3301 const X86InstrInfo *TII) {
3302 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3304 if (Arg.getOpcode() == ISD::CopyFromReg) {
3305 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3306 if (!TargetRegisterInfo::isVirtualRegister(VR))
3308 MachineInstr *Def = MRI->getVRegDef(VR);
3311 if (!Flags.isByVal()) {
3312 if (!TII->isLoadFromStackSlot(Def, FI))
3315 unsigned Opcode = Def->getOpcode();
3316 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3317 Opcode == X86::LEA64_32r) &&
3318 Def->getOperand(1).isFI()) {
3319 FI = Def->getOperand(1).getIndex();
3320 Bytes = Flags.getByValSize();
3324 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3325 if (Flags.isByVal())
3326 // ByVal argument is passed in as a pointer but it's now being
3327 // dereferenced. e.g.
3328 // define @foo(%struct.X* %A) {
3329 // tail call @bar(%struct.X* byval %A)
3332 SDValue Ptr = Ld->getBasePtr();
3333 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3336 FI = FINode->getIndex();
3337 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3338 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3339 FI = FINode->getIndex();
3340 Bytes = Flags.getByValSize();
3344 assert(FI != INT_MAX);
3345 if (!MFI->isFixedObjectIndex(FI))
3347 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3350 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3351 /// for tail call optimization. Targets which want to do tail call
3352 /// optimization should implement this function.
3354 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3355 CallingConv::ID CalleeCC,
3357 bool isCalleeStructRet,
3358 bool isCallerStructRet,
3360 const SmallVectorImpl<ISD::OutputArg> &Outs,
3361 const SmallVectorImpl<SDValue> &OutVals,
3362 const SmallVectorImpl<ISD::InputArg> &Ins,
3363 SelectionDAG &DAG) const {
3364 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3367 // If -tailcallopt is specified, make fastcc functions tail-callable.
3368 const MachineFunction &MF = DAG.getMachineFunction();
3369 const Function *CallerF = MF.getFunction();
3371 // If the function return type is x86_fp80 and the callee return type is not,
3372 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3373 // perform a tailcall optimization here.
3374 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3377 CallingConv::ID CallerCC = CallerF->getCallingConv();
3378 bool CCMatch = CallerCC == CalleeCC;
3379 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3380 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3382 // Win64 functions have extra shadow space for argument homing. Don't do the
3383 // sibcall if the caller and callee have mismatched expectations for this
3385 if (IsCalleeWin64 != IsCallerWin64)
3388 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3389 if (IsTailCallConvention(CalleeCC) && CCMatch)
3394 // Look for obvious safe cases to perform tail call optimization that do not
3395 // require ABI changes. This is what gcc calls sibcall.
3397 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3398 // emit a special epilogue.
3399 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3400 if (RegInfo->needsStackRealignment(MF))
3403 // Also avoid sibcall optimization if either caller or callee uses struct
3404 // return semantics.
3405 if (isCalleeStructRet || isCallerStructRet)
3408 // An stdcall/thiscall caller is expected to clean up its arguments; the
3409 // callee isn't going to do that.
3410 // FIXME: this is more restrictive than needed. We could produce a tailcall
3411 // when the stack adjustment matches. For example, with a thiscall that takes
3412 // only one argument.
3413 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3414 CallerCC == CallingConv::X86_ThisCall))
3417 // Do not sibcall optimize vararg calls unless all arguments are passed via
3419 if (isVarArg && !Outs.empty()) {
3421 // Optimizing for varargs on Win64 is unlikely to be safe without
3422 // additional testing.
3423 if (IsCalleeWin64 || IsCallerWin64)
3426 SmallVector<CCValAssign, 16> ArgLocs;
3427 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3430 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3431 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3432 if (!ArgLocs[i].isRegLoc())
3436 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3437 // stack. Therefore, if it's not used by the call it is not safe to optimize
3438 // this into a sibcall.
3439 bool Unused = false;
3440 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3447 SmallVector<CCValAssign, 16> RVLocs;
3448 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3450 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3451 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3452 CCValAssign &VA = RVLocs[i];
3453 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3458 // If the calling conventions do not match, then we'd better make sure the
3459 // results are returned in the same way as what the caller expects.
3461 SmallVector<CCValAssign, 16> RVLocs1;
3462 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3464 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3466 SmallVector<CCValAssign, 16> RVLocs2;
3467 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3469 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3471 if (RVLocs1.size() != RVLocs2.size())
3473 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3474 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3476 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3478 if (RVLocs1[i].isRegLoc()) {
3479 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3482 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3488 // If the callee takes no arguments then go on to check the results of the
3490 if (!Outs.empty()) {
3491 // Check if stack adjustment is needed. For now, do not do this if any
3492 // argument is passed on the stack.
3493 SmallVector<CCValAssign, 16> ArgLocs;
3494 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3497 // Allocate shadow area for Win64
3499 CCInfo.AllocateStack(32, 8);
3501 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3502 if (CCInfo.getNextStackOffset()) {
3503 MachineFunction &MF = DAG.getMachineFunction();
3504 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3507 // Check if the arguments are already laid out in the right way as
3508 // the caller's fixed stack objects.
3509 MachineFrameInfo *MFI = MF.getFrameInfo();
3510 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3511 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3512 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3513 CCValAssign &VA = ArgLocs[i];
3514 SDValue Arg = OutVals[i];
3515 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3516 if (VA.getLocInfo() == CCValAssign::Indirect)
3518 if (!VA.isRegLoc()) {
3519 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3526 // If the tailcall address may be in a register, then make sure it's
3527 // possible to register allocate for it. In 32-bit, the call address can
3528 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3529 // callee-saved registers are restored. These happen to be the same
3530 // registers used to pass 'inreg' arguments so watch out for those.
3531 if (!Subtarget->is64Bit() &&
3532 ((!isa<GlobalAddressSDNode>(Callee) &&
3533 !isa<ExternalSymbolSDNode>(Callee)) ||
3534 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3535 unsigned NumInRegs = 0;
3536 // In PIC we need an extra register to formulate the address computation
3538 unsigned MaxInRegs =
3539 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3541 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3542 CCValAssign &VA = ArgLocs[i];
3545 unsigned Reg = VA.getLocReg();
3548 case X86::EAX: case X86::EDX: case X86::ECX:
3549 if (++NumInRegs == MaxInRegs)
3561 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3562 const TargetLibraryInfo *libInfo) const {
3563 return X86::createFastISel(funcInfo, libInfo);
3566 //===----------------------------------------------------------------------===//
3567 // Other Lowering Hooks
3568 //===----------------------------------------------------------------------===//
3570 static bool MayFoldLoad(SDValue Op) {
3571 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3574 static bool MayFoldIntoStore(SDValue Op) {
3575 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3578 static bool isTargetShuffle(unsigned Opcode) {
3580 default: return false;
3581 case X86ISD::BLENDI:
3582 case X86ISD::PSHUFB:
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3587 case X86ISD::PALIGNR:
3588 case X86ISD::MOVLHPS:
3589 case X86ISD::MOVLHPD:
3590 case X86ISD::MOVHLPS:
3591 case X86ISD::MOVLPS:
3592 case X86ISD::MOVLPD:
3593 case X86ISD::MOVSHDUP:
3594 case X86ISD::MOVSLDUP:
3595 case X86ISD::MOVDDUP:
3598 case X86ISD::UNPCKL:
3599 case X86ISD::UNPCKH:
3600 case X86ISD::VPERMILPI:
3601 case X86ISD::VPERM2X128:
3602 case X86ISD::VPERMI:
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, unsigned TargetMask,
3609 SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::PSHUFD:
3613 case X86ISD::PSHUFHW:
3614 case X86ISD::PSHUFLW:
3615 case X86ISD::VPERMILPI:
3616 case X86ISD::VPERMI:
3617 return DAG.getNode(Opc, dl, VT, V1,
3618 DAG.getConstant(TargetMask, dl, MVT::i8));
3622 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3623 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3625 default: llvm_unreachable("Unknown x86 shuffle node");
3626 case X86ISD::MOVLHPS:
3627 case X86ISD::MOVLHPD:
3628 case X86ISD::MOVHLPS:
3629 case X86ISD::MOVLPS:
3630 case X86ISD::MOVLPD:
3633 case X86ISD::UNPCKL:
3634 case X86ISD::UNPCKH:
3635 return DAG.getNode(Opc, dl, VT, V1, V2);
3639 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3640 MachineFunction &MF = DAG.getMachineFunction();
3641 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3642 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3643 int ReturnAddrIndex = FuncInfo->getRAIndex();
3645 if (ReturnAddrIndex == 0) {
3646 // Set up a frame object for the return address.
3647 unsigned SlotSize = RegInfo->getSlotSize();
3648 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3651 FuncInfo->setRAIndex(ReturnAddrIndex);
3654 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3657 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3658 bool hasSymbolicDisplacement) {
3659 // Offset should fit into 32 bit immediate field.
3660 if (!isInt<32>(Offset))
3663 // If we don't have a symbolic displacement - we don't have any extra
3665 if (!hasSymbolicDisplacement)
3668 // FIXME: Some tweaks might be needed for medium code model.
3669 if (M != CodeModel::Small && M != CodeModel::Kernel)
3672 // For small code model we assume that latest object is 16MB before end of 31
3673 // bits boundary. We may also accept pretty large negative constants knowing
3674 // that all objects are in the positive half of address space.
3675 if (M == CodeModel::Small && Offset < 16*1024*1024)
3678 // For kernel code model we know that all object resist in the negative half
3679 // of 32bits address space. We may not accept negative offsets, since they may
3680 // be just off and we may accept pretty large positive ones.
3681 if (M == CodeModel::Kernel && Offset >= 0)
3687 /// isCalleePop - Determines whether the callee is required to pop its
3688 /// own arguments. Callee pop is necessary to support tail calls.
3689 bool X86::isCalleePop(CallingConv::ID CallingConv,
3690 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3691 switch (CallingConv) {
3694 case CallingConv::X86_StdCall:
3695 case CallingConv::X86_FastCall:
3696 case CallingConv::X86_ThisCall:
3698 case CallingConv::Fast:
3699 case CallingConv::GHC:
3700 case CallingConv::HiPE:
3707 /// \brief Return true if the condition is an unsigned comparison operation.
3708 static bool isX86CCUnsigned(unsigned X86CC) {
3710 default: llvm_unreachable("Invalid integer condition!");
3711 case X86::COND_E: return true;
3712 case X86::COND_G: return false;
3713 case X86::COND_GE: return false;
3714 case X86::COND_L: return false;
3715 case X86::COND_LE: return false;
3716 case X86::COND_NE: return true;
3717 case X86::COND_B: return true;
3718 case X86::COND_A: return true;
3719 case X86::COND_BE: return true;
3720 case X86::COND_AE: return true;
3722 llvm_unreachable("covered switch fell through?!");
3725 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3726 /// specific condition code, returning the condition code and the LHS/RHS of the
3727 /// comparison to make.
3728 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3729 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3731 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3732 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3733 // X > -1 -> X == 0, jump !sign.
3734 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3735 return X86::COND_NS;
3737 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3738 // X < 0 -> X == 0, jump on sign.
3741 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3743 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3744 return X86::COND_LE;
3748 switch (SetCCOpcode) {
3749 default: llvm_unreachable("Invalid integer condition!");
3750 case ISD::SETEQ: return X86::COND_E;
3751 case ISD::SETGT: return X86::COND_G;
3752 case ISD::SETGE: return X86::COND_GE;
3753 case ISD::SETLT: return X86::COND_L;
3754 case ISD::SETLE: return X86::COND_LE;
3755 case ISD::SETNE: return X86::COND_NE;
3756 case ISD::SETULT: return X86::COND_B;
3757 case ISD::SETUGT: return X86::COND_A;
3758 case ISD::SETULE: return X86::COND_BE;
3759 case ISD::SETUGE: return X86::COND_AE;
3763 // First determine if it is required or is profitable to flip the operands.
3765 // If LHS is a foldable load, but RHS is not, flip the condition.
3766 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3767 !ISD::isNON_EXTLoad(RHS.getNode())) {
3768 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3769 std::swap(LHS, RHS);
3772 switch (SetCCOpcode) {
3778 std::swap(LHS, RHS);
3782 // On a floating point condition, the flags are set as follows:
3784 // 0 | 0 | 0 | X > Y
3785 // 0 | 0 | 1 | X < Y
3786 // 1 | 0 | 0 | X == Y
3787 // 1 | 1 | 1 | unordered
3788 switch (SetCCOpcode) {
3789 default: llvm_unreachable("Condcode should be pre-legalized away");
3791 case ISD::SETEQ: return X86::COND_E;
3792 case ISD::SETOLT: // flipped
3794 case ISD::SETGT: return X86::COND_A;
3795 case ISD::SETOLE: // flipped
3797 case ISD::SETGE: return X86::COND_AE;
3798 case ISD::SETUGT: // flipped
3800 case ISD::SETLT: return X86::COND_B;
3801 case ISD::SETUGE: // flipped
3803 case ISD::SETLE: return X86::COND_BE;
3805 case ISD::SETNE: return X86::COND_NE;
3806 case ISD::SETUO: return X86::COND_P;
3807 case ISD::SETO: return X86::COND_NP;
3809 case ISD::SETUNE: return X86::COND_INVALID;
3813 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3814 /// code. Current x86 isa includes the following FP cmov instructions:
3815 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3816 static bool hasFPCMov(unsigned X86CC) {
3832 /// isFPImmLegal - Returns true if the target can instruction select the
3833 /// specified FP immediate natively. If false, the legalizer will
3834 /// materialize the FP immediate as a load from a constant pool.
3835 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3836 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3837 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3843 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3844 ISD::LoadExtType ExtTy,
3846 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3847 // relocation target a movq or addq instruction: don't let the load shrink.
3848 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3849 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3850 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3851 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3855 /// \brief Returns true if it is beneficial to convert a load of a constant
3856 /// to just the constant itself.
3857 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3859 assert(Ty->isIntegerTy());
3861 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3862 if (BitSize == 0 || BitSize > 64)
3867 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3868 unsigned Index) const {
3869 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3872 return (Index == 0 || Index == ResVT.getVectorNumElements());
3875 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3876 // Speculate cttz only if we can directly use TZCNT.
3877 return Subtarget->hasBMI();
3880 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3881 // Speculate ctlz only if we can directly use LZCNT.
3882 return Subtarget->hasLZCNT();
3885 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3886 /// the specified range (L, H].
3887 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3888 return (Val < 0) || (Val >= Low && Val < Hi);
3891 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3892 /// specified value.
3893 static bool isUndefOrEqual(int Val, int CmpVal) {
3894 return (Val < 0 || Val == CmpVal);
3897 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3898 /// from position Pos and ending in Pos+Size, falls within the specified
3899 /// sequential range (Low, Low+Size]. or is undef.
3900 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3901 unsigned Pos, unsigned Size, int Low) {
3902 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3903 if (!isUndefOrEqual(Mask[i], Low))
3908 /// isVEXTRACTIndex - Return true if the specified
3909 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3910 /// suitable for instruction that extract 128 or 256 bit vectors
3911 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3912 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3913 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3916 // The index should be aligned on a vecWidth-bit boundary.
3918 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3920 MVT VT = N->getSimpleValueType(0);
3921 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3922 bool Result = (Index * ElSize) % vecWidth == 0;
3927 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3928 /// operand specifies a subvector insert that is suitable for input to
3929 /// insertion of 128 or 256-bit subvectors
3930 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3931 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3932 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3934 // The index should be aligned on a vecWidth-bit boundary.
3936 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3938 MVT VT = N->getSimpleValueType(0);
3939 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3940 bool Result = (Index * ElSize) % vecWidth == 0;
3945 bool X86::isVINSERT128Index(SDNode *N) {
3946 return isVINSERTIndex(N, 128);
3949 bool X86::isVINSERT256Index(SDNode *N) {
3950 return isVINSERTIndex(N, 256);
3953 bool X86::isVEXTRACT128Index(SDNode *N) {
3954 return isVEXTRACTIndex(N, 128);
3957 bool X86::isVEXTRACT256Index(SDNode *N) {
3958 return isVEXTRACTIndex(N, 256);
3961 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3962 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3963 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3964 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3967 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3969 MVT VecVT = N->getOperand(0).getSimpleValueType();
3970 MVT ElVT = VecVT.getVectorElementType();
3972 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3973 return Index / NumElemsPerChunk;
3976 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3977 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3978 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3979 llvm_unreachable("Illegal insert subvector for VINSERT");
3982 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3984 MVT VecVT = N->getSimpleValueType(0);
3985 MVT ElVT = VecVT.getVectorElementType();
3987 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3988 return Index / NumElemsPerChunk;
3991 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3992 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3993 /// and VINSERTI128 instructions.
3994 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3995 return getExtractVEXTRACTImmediate(N, 128);
3998 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3999 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4000 /// and VINSERTI64x4 instructions.
4001 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4002 return getExtractVEXTRACTImmediate(N, 256);
4005 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4006 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4007 /// and VINSERTI128 instructions.
4008 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4009 return getInsertVINSERTImmediate(N, 128);
4012 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4013 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4014 /// and VINSERTI64x4 instructions.
4015 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4016 return getInsertVINSERTImmediate(N, 256);
4019 /// isZero - Returns true if Elt is a constant integer zero
4020 static bool isZero(SDValue V) {
4021 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4022 return C && C->isNullValue();
4025 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4027 bool X86::isZeroNode(SDValue Elt) {
4030 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4031 return CFP->getValueAPF().isPosZero();
4035 /// getZeroVector - Returns a vector of specified type with all zero elements.
4037 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4038 SelectionDAG &DAG, SDLoc dl) {
4039 assert(VT.isVector() && "Expected a vector type");
4041 // Always build SSE zero vectors as <4 x i32> bitcasted
4042 // to their dest type. This ensures they get CSE'd.
4044 if (VT.is128BitVector()) { // SSE
4045 if (Subtarget->hasSSE2()) { // SSE2
4046 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4047 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4049 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4050 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4052 } else if (VT.is256BitVector()) { // AVX
4053 if (Subtarget->hasInt256()) { // AVX2
4054 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4055 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4056 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4058 // 256-bit logic and arithmetic instructions in AVX are all
4059 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4060 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4061 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4062 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4064 } else if (VT.is512BitVector()) { // AVX-512
4065 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4066 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4067 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4069 } else if (VT.getScalarType() == MVT::i1) {
4071 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4072 && "Unexpected vector type");
4073 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4074 && "Unexpected vector type");
4075 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4076 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4077 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4079 llvm_unreachable("Unexpected vector type");
4081 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4084 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4085 SelectionDAG &DAG, SDLoc dl,
4086 unsigned vectorWidth) {
4087 assert((vectorWidth == 128 || vectorWidth == 256) &&
4088 "Unsupported vector width");
4089 EVT VT = Vec.getValueType();
4090 EVT ElVT = VT.getVectorElementType();
4091 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4092 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4093 VT.getVectorNumElements()/Factor);
4095 // Extract from UNDEF is UNDEF.
4096 if (Vec.getOpcode() == ISD::UNDEF)
4097 return DAG.getUNDEF(ResultVT);
4099 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4102 // This is the index of the first element of the vectorWidth-bit chunk
4104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4107 // If the input is a buildvector just emit a smaller one.
4108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4120 /// instructions or a simple subregister reference. Idx is an index in the
4121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4122 /// lowering EXTRACT_VECTOR_ELT operations easier.
4123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4124 SelectionDAG &DAG, SDLoc dl) {
4125 assert((Vec.getValueType().is256BitVector() ||
4126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4132 SelectionDAG &DAG, SDLoc dl) {
4133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4138 unsigned IdxVal, SelectionDAG &DAG,
4139 SDLoc dl, unsigned vectorWidth) {
4140 assert((vectorWidth == 128 || vectorWidth == 256) &&
4141 "Unsupported vector width");
4142 // Inserting UNDEF is Result
4143 if (Vec.getOpcode() == ISD::UNDEF)
4145 EVT VT = Vec.getValueType();
4146 EVT ElVT = VT.getVectorElementType();
4147 EVT ResultVT = Result.getValueType();
4149 // Insert the relevant vectorWidth bits.
4150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4152 // This is the index of the first element of the vectorWidth-bit chunk
4154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4164 /// simple superregister reference. Idx is an index in the 128 bits
4165 /// we want. It need not be aligned to a 128-bit boundary. That makes
4166 /// lowering INSERT_VECTOR_ELT operations easier.
4167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4168 SelectionDAG &DAG, SDLoc dl) {
4169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4171 // For insertion into the zero index (low half) of a 256-bit vector, it is
4172 // more efficient to generate a blend with immediate instead of an insert*128.
4173 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4174 // extend the subvector to the size of the result vector. Make sure that
4175 // we are not recursing on that node by checking for undef here.
4176 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4177 Result.getOpcode() != ISD::UNDEF) {
4178 EVT ResultVT = Result.getValueType();
4179 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4180 SDValue Undef = DAG.getUNDEF(ResultVT);
4181 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4184 // The blend instruction, and therefore its mask, depend on the data type.
4185 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4186 if (ScalarType.isFloatingPoint()) {
4187 // Choose either vblendps (float) or vblendpd (double).
4188 unsigned ScalarSize = ScalarType.getSizeInBits();
4189 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4190 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4191 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4192 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4195 const X86Subtarget &Subtarget =
4196 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4198 // AVX2 is needed for 256-bit integer blend support.
4199 // Integers must be cast to 32-bit because there is only vpblendd;
4200 // vpblendw can't be used for this because it has a handicapped mask.
4202 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4203 // is still more efficient than using the wrong domain vinsertf128 that
4204 // will be created by InsertSubVector().
4205 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4207 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4208 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4209 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4210 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4213 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4216 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4217 SelectionDAG &DAG, SDLoc dl) {
4218 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4219 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4222 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4223 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4224 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4225 /// large BUILD_VECTORS.
4226 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4227 unsigned NumElems, SelectionDAG &DAG,
4229 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4230 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4233 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4234 unsigned NumElems, SelectionDAG &DAG,
4236 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4237 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4240 /// getOnesVector - Returns a vector of specified type with all bits set.
4241 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4242 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4243 /// Then bitcast to their original type, ensuring they get CSE'd.
4244 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4246 assert(VT.isVector() && "Expected a vector type");
4248 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4250 if (VT.is256BitVector()) {
4251 if (HasInt256) { // AVX2
4252 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4253 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4255 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4256 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4258 } else if (VT.is128BitVector()) {
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4261 llvm_unreachable("Unexpected vector type");
4263 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4266 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4267 /// operation of specified width.
4268 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4270 unsigned NumElems = VT.getVectorNumElements();
4271 SmallVector<int, 8> Mask;
4272 Mask.push_back(NumElems);
4273 for (unsigned i = 1; i != NumElems; ++i)
4275 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4278 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4279 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4281 unsigned NumElems = VT.getVectorNumElements();
4282 SmallVector<int, 8> Mask;
4283 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4285 Mask.push_back(i + NumElems);
4287 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4290 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4291 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4293 unsigned NumElems = VT.getVectorNumElements();
4294 SmallVector<int, 8> Mask;
4295 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4296 Mask.push_back(i + Half);
4297 Mask.push_back(i + NumElems + Half);
4299 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4302 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4303 /// vector of zero or undef vector. This produces a shuffle where the low
4304 /// element of V2 is swizzled into the zero/undef vector, landing at element
4305 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4306 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4308 const X86Subtarget *Subtarget,
4309 SelectionDAG &DAG) {
4310 MVT VT = V2.getSimpleValueType();
4312 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4313 unsigned NumElems = VT.getVectorNumElements();
4314 SmallVector<int, 16> MaskVec;
4315 for (unsigned i = 0; i != NumElems; ++i)
4316 // If this is the insertion idx, put the low elt of V2 here.
4317 MaskVec.push_back(i == Idx ? NumElems : i);
4318 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4321 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4322 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4323 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4324 /// shuffles which use a single input multiple times, and in those cases it will
4325 /// adjust the mask to only have indices within that single input.
4326 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4327 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4328 unsigned NumElems = VT.getVectorNumElements();
4332 bool IsFakeUnary = false;
4333 switch(N->getOpcode()) {
4334 case X86ISD::BLENDI:
4335 ImmN = N->getOperand(N->getNumOperands()-1);
4336 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4339 ImmN = N->getOperand(N->getNumOperands()-1);
4340 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4341 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4343 case X86ISD::UNPCKH:
4344 DecodeUNPCKHMask(VT, Mask);
4345 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4347 case X86ISD::UNPCKL:
4348 DecodeUNPCKLMask(VT, Mask);
4349 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4351 case X86ISD::MOVHLPS:
4352 DecodeMOVHLPSMask(NumElems, Mask);
4353 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4355 case X86ISD::MOVLHPS:
4356 DecodeMOVLHPSMask(NumElems, Mask);
4357 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4359 case X86ISD::PALIGNR:
4360 ImmN = N->getOperand(N->getNumOperands()-1);
4361 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4363 case X86ISD::PSHUFD:
4364 case X86ISD::VPERMILPI:
4365 ImmN = N->getOperand(N->getNumOperands()-1);
4366 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4369 case X86ISD::PSHUFHW:
4370 ImmN = N->getOperand(N->getNumOperands()-1);
4371 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4374 case X86ISD::PSHUFLW:
4375 ImmN = N->getOperand(N->getNumOperands()-1);
4376 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4379 case X86ISD::PSHUFB: {
4381 SDValue MaskNode = N->getOperand(1);
4382 while (MaskNode->getOpcode() == ISD::BITCAST)
4383 MaskNode = MaskNode->getOperand(0);
4385 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4386 // If we have a build-vector, then things are easy.
4387 EVT VT = MaskNode.getValueType();
4388 assert(VT.isVector() &&
4389 "Can't produce a non-vector with a build_vector!");
4390 if (!VT.isInteger())
4393 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4395 SmallVector<uint64_t, 32> RawMask;
4396 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4397 SDValue Op = MaskNode->getOperand(i);
4398 if (Op->getOpcode() == ISD::UNDEF) {
4399 RawMask.push_back((uint64_t)SM_SentinelUndef);
4402 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4405 APInt MaskElement = CN->getAPIntValue();
4407 // We now have to decode the element which could be any integer size and
4408 // extract each byte of it.
4409 for (int j = 0; j < NumBytesPerElement; ++j) {
4410 // Note that this is x86 and so always little endian: the low byte is
4411 // the first byte of the mask.
4412 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4413 MaskElement = MaskElement.lshr(8);
4416 DecodePSHUFBMask(RawMask, Mask);
4420 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4424 SDValue Ptr = MaskLoad->getBasePtr();
4425 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4426 Ptr->getOpcode() == X86ISD::WrapperRIP)
4427 Ptr = Ptr->getOperand(0);
4429 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4430 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4433 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4434 DecodePSHUFBMask(C, Mask);
4442 case X86ISD::VPERMI:
4443 ImmN = N->getOperand(N->getNumOperands()-1);
4444 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4449 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4451 case X86ISD::VPERM2X128:
4452 ImmN = N->getOperand(N->getNumOperands()-1);
4453 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4454 if (Mask.empty()) return false;
4456 case X86ISD::MOVSLDUP:
4457 DecodeMOVSLDUPMask(VT, Mask);
4460 case X86ISD::MOVSHDUP:
4461 DecodeMOVSHDUPMask(VT, Mask);
4464 case X86ISD::MOVDDUP:
4465 DecodeMOVDDUPMask(VT, Mask);
4468 case X86ISD::MOVLHPD:
4469 case X86ISD::MOVLPD:
4470 case X86ISD::MOVLPS:
4471 // Not yet implemented
4473 default: llvm_unreachable("unknown target shuffle node");
4476 // If we have a fake unary shuffle, the shuffle mask is spread across two
4477 // inputs that are actually the same node. Re-map the mask to always point
4478 // into the first input.
4481 if (M >= (int)Mask.size())
4487 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4488 /// element of the result of the vector shuffle.
4489 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4492 return SDValue(); // Limit search depth.
4494 SDValue V = SDValue(N, 0);
4495 EVT VT = V.getValueType();
4496 unsigned Opcode = V.getOpcode();
4498 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4499 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4500 int Elt = SV->getMaskElt(Index);
4503 return DAG.getUNDEF(VT.getVectorElementType());
4505 unsigned NumElems = VT.getVectorNumElements();
4506 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4507 : SV->getOperand(1);
4508 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4511 // Recurse into target specific vector shuffles to find scalars.
4512 if (isTargetShuffle(Opcode)) {
4513 MVT ShufVT = V.getSimpleValueType();
4514 unsigned NumElems = ShufVT.getVectorNumElements();
4515 SmallVector<int, 16> ShuffleMask;
4518 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4521 int Elt = ShuffleMask[Index];
4523 return DAG.getUNDEF(ShufVT.getVectorElementType());
4525 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4527 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4531 // Actual nodes that may contain scalar elements
4532 if (Opcode == ISD::BITCAST) {
4533 V = V.getOperand(0);
4534 EVT SrcVT = V.getValueType();
4535 unsigned NumElems = VT.getVectorNumElements();
4537 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4541 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4542 return (Index == 0) ? V.getOperand(0)
4543 : DAG.getUNDEF(VT.getVectorElementType());
4545 if (V.getOpcode() == ISD::BUILD_VECTOR)
4546 return V.getOperand(Index);
4551 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4553 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4554 unsigned NumNonZero, unsigned NumZero,
4556 const X86Subtarget* Subtarget,
4557 const TargetLowering &TLI) {
4565 // SSE4.1 - use PINSRB to insert each byte directly.
4566 if (Subtarget->hasSSE41()) {
4567 for (unsigned i = 0; i < 16; ++i) {
4568 bool isNonZero = (NonZeros & (1 << i)) != 0;
4572 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4574 V = DAG.getUNDEF(MVT::v16i8);
4577 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4578 MVT::v16i8, V, Op.getOperand(i),
4579 DAG.getIntPtrConstant(i, dl));
4586 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4587 for (unsigned i = 0; i < 16; ++i) {
4588 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4589 if (ThisIsNonZero && First) {
4591 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4593 V = DAG.getUNDEF(MVT::v8i16);
4598 SDValue ThisElt, LastElt;
4599 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4600 if (LastIsNonZero) {
4601 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4602 MVT::i16, Op.getOperand(i-1));
4604 if (ThisIsNonZero) {
4605 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4606 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4607 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4609 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4613 if (ThisElt.getNode())
4614 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4615 DAG.getIntPtrConstant(i/2, dl));
4619 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4622 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4624 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4625 unsigned NumNonZero, unsigned NumZero,
4627 const X86Subtarget* Subtarget,
4628 const TargetLowering &TLI) {
4635 for (unsigned i = 0; i < 8; ++i) {
4636 bool isNonZero = (NonZeros & (1 << i)) != 0;
4640 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4642 V = DAG.getUNDEF(MVT::v8i16);
4645 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4646 MVT::v8i16, V, Op.getOperand(i),
4647 DAG.getIntPtrConstant(i, dl));
4654 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4655 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4656 const X86Subtarget *Subtarget,
4657 const TargetLowering &TLI) {
4658 // Find all zeroable elements.
4659 std::bitset<4> Zeroable;
4660 for (int i=0; i < 4; ++i) {
4661 SDValue Elt = Op->getOperand(i);
4662 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4664 assert(Zeroable.size() - Zeroable.count() > 1 &&
4665 "We expect at least two non-zero elements!");
4667 // We only know how to deal with build_vector nodes where elements are either
4668 // zeroable or extract_vector_elt with constant index.
4669 SDValue FirstNonZero;
4670 unsigned FirstNonZeroIdx;
4671 for (unsigned i=0; i < 4; ++i) {
4674 SDValue Elt = Op->getOperand(i);
4675 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4676 !isa<ConstantSDNode>(Elt.getOperand(1)))
4678 // Make sure that this node is extracting from a 128-bit vector.
4679 MVT VT = Elt.getOperand(0).getSimpleValueType();
4680 if (!VT.is128BitVector())
4682 if (!FirstNonZero.getNode()) {
4684 FirstNonZeroIdx = i;
4688 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4689 SDValue V1 = FirstNonZero.getOperand(0);
4690 MVT VT = V1.getSimpleValueType();
4692 // See if this build_vector can be lowered as a blend with zero.
4694 unsigned EltMaskIdx, EltIdx;
4696 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4697 if (Zeroable[EltIdx]) {
4698 // The zero vector will be on the right hand side.
4699 Mask[EltIdx] = EltIdx+4;
4703 Elt = Op->getOperand(EltIdx);
4704 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4705 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4706 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4708 Mask[EltIdx] = EltIdx;
4712 // Let the shuffle legalizer deal with blend operations.
4713 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4714 if (V1.getSimpleValueType() != VT)
4715 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4716 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4719 // See if we can lower this build_vector to a INSERTPS.
4720 if (!Subtarget->hasSSE41())
4723 SDValue V2 = Elt.getOperand(0);
4724 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4727 bool CanFold = true;
4728 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4732 SDValue Current = Op->getOperand(i);
4733 SDValue SrcVector = Current->getOperand(0);
4736 CanFold = SrcVector == V1 &&
4737 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4743 assert(V1.getNode() && "Expected at least two non-zero elements!");
4744 if (V1.getSimpleValueType() != MVT::v4f32)
4745 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4746 if (V2.getSimpleValueType() != MVT::v4f32)
4747 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4749 // Ok, we can emit an INSERTPS instruction.
4750 unsigned ZMask = Zeroable.to_ulong();
4752 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4753 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4755 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4756 DAG.getIntPtrConstant(InsertPSMask, DL));
4757 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4760 /// Return a vector logical shift node.
4761 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4762 unsigned NumBits, SelectionDAG &DAG,
4763 const TargetLowering &TLI, SDLoc dl) {
4764 assert(VT.is128BitVector() && "Unknown type for VShift");
4765 MVT ShVT = MVT::v2i64;
4766 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4767 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4768 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4769 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4770 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4771 return DAG.getNode(ISD::BITCAST, dl, VT,
4772 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4776 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4778 // Check if the scalar load can be widened into a vector load. And if
4779 // the address is "base + cst" see if the cst can be "absorbed" into
4780 // the shuffle mask.
4781 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4782 SDValue Ptr = LD->getBasePtr();
4783 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4785 EVT PVT = LD->getValueType(0);
4786 if (PVT != MVT::i32 && PVT != MVT::f32)
4791 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4792 FI = FINode->getIndex();
4794 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4795 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4796 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4797 Offset = Ptr.getConstantOperandVal(1);
4798 Ptr = Ptr.getOperand(0);
4803 // FIXME: 256-bit vector instructions don't require a strict alignment,
4804 // improve this code to support it better.
4805 unsigned RequiredAlign = VT.getSizeInBits()/8;
4806 SDValue Chain = LD->getChain();
4807 // Make sure the stack object alignment is at least 16 or 32.
4808 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4809 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4810 if (MFI->isFixedObjectIndex(FI)) {
4811 // Can't change the alignment. FIXME: It's possible to compute
4812 // the exact stack offset and reference FI + adjust offset instead.
4813 // If someone *really* cares about this. That's the way to implement it.
4816 MFI->setObjectAlignment(FI, RequiredAlign);
4820 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4821 // Ptr + (Offset & ~15).
4824 if ((Offset % RequiredAlign) & 3)
4826 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4829 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4830 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4833 int EltNo = (Offset - StartOffset) >> 2;
4834 unsigned NumElems = VT.getVectorNumElements();
4836 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4837 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4838 LD->getPointerInfo().getWithOffset(StartOffset),
4839 false, false, false, 0);
4841 SmallVector<int, 8> Mask(NumElems, EltNo);
4843 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4849 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4850 /// elements can be replaced by a single large load which has the same value as
4851 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4853 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4855 /// FIXME: we'd also like to handle the case where the last elements are zero
4856 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4857 /// There's even a handy isZeroNode for that purpose.
4858 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4859 SDLoc &DL, SelectionDAG &DAG,
4860 bool isAfterLegalize) {
4861 unsigned NumElems = Elts.size();
4863 LoadSDNode *LDBase = nullptr;
4864 unsigned LastLoadedElt = -1U;
4866 // For each element in the initializer, see if we've found a load or an undef.
4867 // If we don't find an initial load element, or later load elements are
4868 // non-consecutive, bail out.
4869 for (unsigned i = 0; i < NumElems; ++i) {
4870 SDValue Elt = Elts[i];
4871 // Look through a bitcast.
4872 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4873 Elt = Elt.getOperand(0);
4874 if (!Elt.getNode() ||
4875 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4878 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4880 LDBase = cast<LoadSDNode>(Elt.getNode());
4884 if (Elt.getOpcode() == ISD::UNDEF)
4887 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4888 EVT LdVT = Elt.getValueType();
4889 // Each loaded element must be the correct fractional portion of the
4890 // requested vector load.
4891 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4893 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4898 // If we have found an entire vector of loads and undefs, then return a large
4899 // load of the entire vector width starting at the base pointer. If we found
4900 // consecutive loads for the low half, generate a vzext_load node.
4901 if (LastLoadedElt == NumElems - 1) {
4902 assert(LDBase && "Did not find base load for merging consecutive loads");
4903 EVT EltVT = LDBase->getValueType(0);
4904 // Ensure that the input vector size for the merged loads matches the
4905 // cumulative size of the input elements.
4906 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4909 if (isAfterLegalize &&
4910 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4913 SDValue NewLd = SDValue();
4915 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4916 LDBase->getPointerInfo(), LDBase->isVolatile(),
4917 LDBase->isNonTemporal(), LDBase->isInvariant(),
4918 LDBase->getAlignment());
4920 if (LDBase->hasAnyUseOfValue(1)) {
4921 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4923 SDValue(NewLd.getNode(), 1));
4924 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4925 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4926 SDValue(NewLd.getNode(), 1));
4932 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4933 //of a v4i32 / v4f32. It's probably worth generalizing.
4934 EVT EltVT = VT.getVectorElementType();
4935 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4936 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4937 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4938 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4940 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4941 LDBase->getPointerInfo(),
4942 LDBase->getAlignment(),
4943 false/*isVolatile*/, true/*ReadMem*/,
4946 // Make sure the newly-created LOAD is in the same position as LDBase in
4947 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4948 // update uses of LDBase's output chain to use the TokenFactor.
4949 if (LDBase->hasAnyUseOfValue(1)) {
4950 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4951 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4952 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4953 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4954 SDValue(ResNode.getNode(), 1));
4957 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4962 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4963 /// to generate a splat value for the following cases:
4964 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4965 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4966 /// a scalar load, or a constant.
4967 /// The VBROADCAST node is returned when a pattern is found,
4968 /// or SDValue() otherwise.
4969 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4970 SelectionDAG &DAG) {
4971 // VBROADCAST requires AVX.
4972 // TODO: Splats could be generated for non-AVX CPUs using SSE
4973 // instructions, but there's less potential gain for only 128-bit vectors.
4974 if (!Subtarget->hasAVX())
4977 MVT VT = Op.getSimpleValueType();
4980 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4981 "Unsupported vector type for broadcast.");
4986 switch (Op.getOpcode()) {
4988 // Unknown pattern found.
4991 case ISD::BUILD_VECTOR: {
4992 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4993 BitVector UndefElements;
4994 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4996 // We need a splat of a single value to use broadcast, and it doesn't
4997 // make any sense if the value is only in one element of the vector.
4998 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5002 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5003 Ld.getOpcode() == ISD::ConstantFP);
5005 // Make sure that all of the users of a non-constant load are from the
5006 // BUILD_VECTOR node.
5007 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5012 case ISD::VECTOR_SHUFFLE: {
5013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5015 // Shuffles must have a splat mask where the first element is
5017 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5020 SDValue Sc = Op.getOperand(0);
5021 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5022 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5024 if (!Subtarget->hasInt256())
5027 // Use the register form of the broadcast instruction available on AVX2.
5028 if (VT.getSizeInBits() >= 256)
5029 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5030 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5033 Ld = Sc.getOperand(0);
5034 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5035 Ld.getOpcode() == ISD::ConstantFP);
5037 // The scalar_to_vector node and the suspected
5038 // load node must have exactly one user.
5039 // Constants may have multiple users.
5041 // AVX-512 has register version of the broadcast
5042 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5043 Ld.getValueType().getSizeInBits() >= 32;
5044 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5051 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5052 bool IsGE256 = (VT.getSizeInBits() >= 256);
5054 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5055 // instruction to save 8 or more bytes of constant pool data.
5056 // TODO: If multiple splats are generated to load the same constant,
5057 // it may be detrimental to overall size. There needs to be a way to detect
5058 // that condition to know if this is truly a size win.
5059 const Function *F = DAG.getMachineFunction().getFunction();
5060 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5062 // Handle broadcasting a single constant scalar from the constant pool
5064 // On Sandybridge (no AVX2), it is still better to load a constant vector
5065 // from the constant pool and not to broadcast it from a scalar.
5066 // But override that restriction when optimizing for size.
5067 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5068 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5069 EVT CVT = Ld.getValueType();
5070 assert(!CVT.isVector() && "Must not broadcast a vector type");
5072 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5073 // For size optimization, also splat v2f64 and v2i64, and for size opt
5074 // with AVX2, also splat i8 and i16.
5075 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5076 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5077 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5078 const Constant *C = nullptr;
5079 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5080 C = CI->getConstantIntValue();
5081 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5082 C = CF->getConstantFPValue();
5084 assert(C && "Invalid constant type");
5086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5087 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5088 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5089 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5090 MachinePointerInfo::getConstantPool(),
5091 false, false, false, Alignment);
5093 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5097 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5099 // Handle AVX2 in-register broadcasts.
5100 if (!IsLoad && Subtarget->hasInt256() &&
5101 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5102 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5104 // The scalar source must be a normal load.
5108 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5109 (Subtarget->hasVLX() && ScalarSize == 64))
5110 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5112 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5113 // double since there is no vbroadcastsd xmm
5114 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5115 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5116 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5119 // Unsupported broadcast.
5123 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5124 /// underlying vector and index.
5126 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5128 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5130 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5131 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5134 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5136 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5138 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5139 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5142 // In this case the vector is the extract_subvector expression and the index
5143 // is 2, as specified by the shuffle.
5144 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5145 SDValue ShuffleVec = SVOp->getOperand(0);
5146 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5147 assert(ShuffleVecVT.getVectorElementType() ==
5148 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5150 int ShuffleIdx = SVOp->getMaskElt(Idx);
5151 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5152 ExtractedFromVec = ShuffleVec;
5158 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5159 MVT VT = Op.getSimpleValueType();
5161 // Skip if insert_vec_elt is not supported.
5162 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5163 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5167 unsigned NumElems = Op.getNumOperands();
5171 SmallVector<unsigned, 4> InsertIndices;
5172 SmallVector<int, 8> Mask(NumElems, -1);
5174 for (unsigned i = 0; i != NumElems; ++i) {
5175 unsigned Opc = Op.getOperand(i).getOpcode();
5177 if (Opc == ISD::UNDEF)
5180 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5181 // Quit if more than 1 elements need inserting.
5182 if (InsertIndices.size() > 1)
5185 InsertIndices.push_back(i);
5189 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5190 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5191 // Quit if non-constant index.
5192 if (!isa<ConstantSDNode>(ExtIdx))
5194 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5196 // Quit if extracted from vector of different type.
5197 if (ExtractedFromVec.getValueType() != VT)
5200 if (!VecIn1.getNode())
5201 VecIn1 = ExtractedFromVec;
5202 else if (VecIn1 != ExtractedFromVec) {
5203 if (!VecIn2.getNode())
5204 VecIn2 = ExtractedFromVec;
5205 else if (VecIn2 != ExtractedFromVec)
5206 // Quit if more than 2 vectors to shuffle
5210 if (ExtractedFromVec == VecIn1)
5212 else if (ExtractedFromVec == VecIn2)
5213 Mask[i] = Idx + NumElems;
5216 if (!VecIn1.getNode())
5219 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5220 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5221 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5222 unsigned Idx = InsertIndices[i];
5223 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5224 DAG.getIntPtrConstant(Idx, DL));
5230 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5231 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5232 Op.getScalarValueSizeInBits() == 1 &&
5233 "Can not convert non-constant vector");
5234 uint64_t Immediate = 0;
5235 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5236 SDValue In = Op.getOperand(idx);
5237 if (In.getOpcode() != ISD::UNDEF)
5238 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5242 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5243 return DAG.getConstant(Immediate, dl, VT);
5245 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5247 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5249 MVT VT = Op.getSimpleValueType();
5250 assert((VT.getVectorElementType() == MVT::i1) &&
5251 "Unexpected type in LowerBUILD_VECTORvXi1!");
5254 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5255 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5256 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5257 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5260 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5261 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5262 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5263 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5266 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5267 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5268 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5269 return DAG.getNode(ISD::BITCAST, dl, VT, Imm);
5270 SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
5271 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5272 DAG.getIntPtrConstant(0, dl));
5275 // Vector has one or more non-const elements
5276 uint64_t Immediate = 0;
5277 SmallVector<unsigned, 16> NonConstIdx;
5278 bool IsSplat = true;
5279 bool HasConstElts = false;
5281 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5282 SDValue In = Op.getOperand(idx);
5283 if (In.getOpcode() == ISD::UNDEF)
5285 if (!isa<ConstantSDNode>(In))
5286 NonConstIdx.push_back(idx);
5288 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5289 HasConstElts = true;
5293 else if (In != Op.getOperand(SplatIdx))
5297 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5299 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5300 DAG.getConstant(1, dl, VT),
5301 DAG.getConstant(0, dl, VT));
5303 // insert elements one by one
5307 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5308 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5310 else if (HasConstElts)
5311 Imm = DAG.getConstant(0, dl, VT);
5313 Imm = DAG.getUNDEF(VT);
5314 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5315 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, Imm);
5317 SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
5318 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5319 DAG.getIntPtrConstant(0, dl));
5322 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5323 unsigned InsertIdx = NonConstIdx[i];
5324 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5325 Op.getOperand(InsertIdx),
5326 DAG.getIntPtrConstant(InsertIdx, dl));
5331 /// \brief Return true if \p N implements a horizontal binop and return the
5332 /// operands for the horizontal binop into V0 and V1.
5334 /// This is a helper function of LowerToHorizontalOp().
5335 /// This function checks that the build_vector \p N in input implements a
5336 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5337 /// operation to match.
5338 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5339 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5340 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5343 /// This function only analyzes elements of \p N whose indices are
5344 /// in range [BaseIdx, LastIdx).
5345 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5347 unsigned BaseIdx, unsigned LastIdx,
5348 SDValue &V0, SDValue &V1) {
5349 EVT VT = N->getValueType(0);
5351 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5352 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5353 "Invalid Vector in input!");
5355 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5356 bool CanFold = true;
5357 unsigned ExpectedVExtractIdx = BaseIdx;
5358 unsigned NumElts = LastIdx - BaseIdx;
5359 V0 = DAG.getUNDEF(VT);
5360 V1 = DAG.getUNDEF(VT);
5362 // Check if N implements a horizontal binop.
5363 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5364 SDValue Op = N->getOperand(i + BaseIdx);
5367 if (Op->getOpcode() == ISD::UNDEF) {
5368 // Update the expected vector extract index.
5369 if (i * 2 == NumElts)
5370 ExpectedVExtractIdx = BaseIdx;
5371 ExpectedVExtractIdx += 2;
5375 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5380 SDValue Op0 = Op.getOperand(0);
5381 SDValue Op1 = Op.getOperand(1);
5383 // Try to match the following pattern:
5384 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5385 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5386 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5387 Op0.getOperand(0) == Op1.getOperand(0) &&
5388 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5389 isa<ConstantSDNode>(Op1.getOperand(1)));
5393 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5394 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5396 if (i * 2 < NumElts) {
5397 if (V0.getOpcode() == ISD::UNDEF) {
5398 V0 = Op0.getOperand(0);
5399 if (V0.getValueType() != VT)
5403 if (V1.getOpcode() == ISD::UNDEF) {
5404 V1 = Op0.getOperand(0);
5405 if (V1.getValueType() != VT)
5408 if (i * 2 == NumElts)
5409 ExpectedVExtractIdx = BaseIdx;
5412 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5413 if (I0 == ExpectedVExtractIdx)
5414 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5415 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5416 // Try to match the following dag sequence:
5417 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5418 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5422 ExpectedVExtractIdx += 2;
5428 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5429 /// a concat_vector.
5431 /// This is a helper function of LowerToHorizontalOp().
5432 /// This function expects two 256-bit vectors called V0 and V1.
5433 /// At first, each vector is split into two separate 128-bit vectors.
5434 /// Then, the resulting 128-bit vectors are used to implement two
5435 /// horizontal binary operations.
5437 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5439 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5440 /// the two new horizontal binop.
5441 /// When Mode is set, the first horizontal binop dag node would take as input
5442 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5443 /// horizontal binop dag node would take as input the lower 128-bit of V1
5444 /// and the upper 128-bit of V1.
5446 /// HADD V0_LO, V0_HI
5447 /// HADD V1_LO, V1_HI
5449 /// Otherwise, the first horizontal binop dag node takes as input the lower
5450 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5451 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5453 /// HADD V0_LO, V1_LO
5454 /// HADD V0_HI, V1_HI
5456 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5457 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5458 /// the upper 128-bits of the result.
5459 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5460 SDLoc DL, SelectionDAG &DAG,
5461 unsigned X86Opcode, bool Mode,
5462 bool isUndefLO, bool isUndefHI) {
5463 EVT VT = V0.getValueType();
5464 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5465 "Invalid nodes in input!");
5467 unsigned NumElts = VT.getVectorNumElements();
5468 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5469 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5470 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5471 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5472 EVT NewVT = V0_LO.getValueType();
5474 SDValue LO = DAG.getUNDEF(NewVT);
5475 SDValue HI = DAG.getUNDEF(NewVT);
5478 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5479 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5480 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5481 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5482 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5484 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5485 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5486 V1_LO->getOpcode() != ISD::UNDEF))
5487 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5489 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5490 V1_HI->getOpcode() != ISD::UNDEF))
5491 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5494 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5497 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5499 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5500 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5501 EVT VT = BV->getValueType(0);
5502 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5503 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5507 unsigned NumElts = VT.getVectorNumElements();
5508 SDValue InVec0 = DAG.getUNDEF(VT);
5509 SDValue InVec1 = DAG.getUNDEF(VT);
5511 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5512 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5514 // Odd-numbered elements in the input build vector are obtained from
5515 // adding two integer/float elements.
5516 // Even-numbered elements in the input build vector are obtained from
5517 // subtracting two integer/float elements.
5518 unsigned ExpectedOpcode = ISD::FSUB;
5519 unsigned NextExpectedOpcode = ISD::FADD;
5520 bool AddFound = false;
5521 bool SubFound = false;
5523 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5524 SDValue Op = BV->getOperand(i);
5526 // Skip 'undef' values.
5527 unsigned Opcode = Op.getOpcode();
5528 if (Opcode == ISD::UNDEF) {
5529 std::swap(ExpectedOpcode, NextExpectedOpcode);
5533 // Early exit if we found an unexpected opcode.
5534 if (Opcode != ExpectedOpcode)
5537 SDValue Op0 = Op.getOperand(0);
5538 SDValue Op1 = Op.getOperand(1);
5540 // Try to match the following pattern:
5541 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5542 // Early exit if we cannot match that sequence.
5543 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5544 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5545 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5546 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5547 Op0.getOperand(1) != Op1.getOperand(1))
5550 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5554 // We found a valid add/sub node. Update the information accordingly.
5560 // Update InVec0 and InVec1.
5561 if (InVec0.getOpcode() == ISD::UNDEF) {
5562 InVec0 = Op0.getOperand(0);
5563 if (InVec0.getValueType() != VT)
5566 if (InVec1.getOpcode() == ISD::UNDEF) {
5567 InVec1 = Op1.getOperand(0);
5568 if (InVec1.getValueType() != VT)
5572 // Make sure that operands in input to each add/sub node always
5573 // come from a same pair of vectors.
5574 if (InVec0 != Op0.getOperand(0)) {
5575 if (ExpectedOpcode == ISD::FSUB)
5578 // FADD is commutable. Try to commute the operands
5579 // and then test again.
5580 std::swap(Op0, Op1);
5581 if (InVec0 != Op0.getOperand(0))
5585 if (InVec1 != Op1.getOperand(0))
5588 // Update the pair of expected opcodes.
5589 std::swap(ExpectedOpcode, NextExpectedOpcode);
5592 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5593 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5594 InVec1.getOpcode() != ISD::UNDEF)
5595 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5600 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5601 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5602 const X86Subtarget *Subtarget,
5603 SelectionDAG &DAG) {
5604 EVT VT = BV->getValueType(0);
5605 unsigned NumElts = VT.getVectorNumElements();
5606 unsigned NumUndefsLO = 0;
5607 unsigned NumUndefsHI = 0;
5608 unsigned Half = NumElts/2;
5610 // Count the number of UNDEF operands in the build_vector in input.
5611 for (unsigned i = 0, e = Half; i != e; ++i)
5612 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5615 for (unsigned i = Half, e = NumElts; i != e; ++i)
5616 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5619 // Early exit if this is either a build_vector of all UNDEFs or all the
5620 // operands but one are UNDEF.
5621 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5625 SDValue InVec0, InVec1;
5626 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5627 // Try to match an SSE3 float HADD/HSUB.
5628 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5629 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5631 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5632 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5633 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5634 // Try to match an SSSE3 integer HADD/HSUB.
5635 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5636 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5638 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5639 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5642 if (!Subtarget->hasAVX())
5645 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5646 // Try to match an AVX horizontal add/sub of packed single/double
5647 // precision floating point values from 256-bit vectors.
5648 SDValue InVec2, InVec3;
5649 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5650 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5651 ((InVec0.getOpcode() == ISD::UNDEF ||
5652 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5653 ((InVec1.getOpcode() == ISD::UNDEF ||
5654 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5655 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5657 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5658 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5659 ((InVec0.getOpcode() == ISD::UNDEF ||
5660 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5661 ((InVec1.getOpcode() == ISD::UNDEF ||
5662 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5663 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5664 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5665 // Try to match an AVX2 horizontal add/sub of signed integers.
5666 SDValue InVec2, InVec3;
5668 bool CanFold = true;
5670 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5671 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5672 ((InVec0.getOpcode() == ISD::UNDEF ||
5673 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5674 ((InVec1.getOpcode() == ISD::UNDEF ||
5675 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5676 X86Opcode = X86ISD::HADD;
5677 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5678 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5679 ((InVec0.getOpcode() == ISD::UNDEF ||
5680 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5681 ((InVec1.getOpcode() == ISD::UNDEF ||
5682 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5683 X86Opcode = X86ISD::HSUB;
5688 // Fold this build_vector into a single horizontal add/sub.
5689 // Do this only if the target has AVX2.
5690 if (Subtarget->hasAVX2())
5691 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5693 // Do not try to expand this build_vector into a pair of horizontal
5694 // add/sub if we can emit a pair of scalar add/sub.
5695 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5698 // Convert this build_vector into a pair of horizontal binop followed by
5700 bool isUndefLO = NumUndefsLO == Half;
5701 bool isUndefHI = NumUndefsHI == Half;
5702 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5703 isUndefLO, isUndefHI);
5707 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5708 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5710 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5711 X86Opcode = X86ISD::HADD;
5712 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5713 X86Opcode = X86ISD::HSUB;
5714 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5715 X86Opcode = X86ISD::FHADD;
5716 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5717 X86Opcode = X86ISD::FHSUB;
5721 // Don't try to expand this build_vector into a pair of horizontal add/sub
5722 // if we can simply emit a pair of scalar add/sub.
5723 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5726 // Convert this build_vector into two horizontal add/sub followed by
5728 bool isUndefLO = NumUndefsLO == Half;
5729 bool isUndefHI = NumUndefsHI == Half;
5730 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5731 isUndefLO, isUndefHI);
5738 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5741 MVT VT = Op.getSimpleValueType();
5742 MVT ExtVT = VT.getVectorElementType();
5743 unsigned NumElems = Op.getNumOperands();
5745 // Generate vectors for predicate vectors.
5746 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5747 return LowerBUILD_VECTORvXi1(Op, DAG);
5749 // Vectors containing all zeros can be matched by pxor and xorps later
5750 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5751 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5752 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5753 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5756 return getZeroVector(VT, Subtarget, DAG, dl);
5759 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5760 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5761 // vpcmpeqd on 256-bit vectors.
5762 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5763 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5766 if (!VT.is512BitVector())
5767 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5770 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5771 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5773 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5774 return HorizontalOp;
5775 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5778 unsigned EVTBits = ExtVT.getSizeInBits();
5780 unsigned NumZero = 0;
5781 unsigned NumNonZero = 0;
5782 unsigned NonZeros = 0;
5783 bool IsAllConstants = true;
5784 SmallSet<SDValue, 8> Values;
5785 for (unsigned i = 0; i < NumElems; ++i) {
5786 SDValue Elt = Op.getOperand(i);
5787 if (Elt.getOpcode() == ISD::UNDEF)
5790 if (Elt.getOpcode() != ISD::Constant &&
5791 Elt.getOpcode() != ISD::ConstantFP)
5792 IsAllConstants = false;
5793 if (X86::isZeroNode(Elt))
5796 NonZeros |= (1 << i);
5801 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5802 if (NumNonZero == 0)
5803 return DAG.getUNDEF(VT);
5805 // Special case for single non-zero, non-undef, element.
5806 if (NumNonZero == 1) {
5807 unsigned Idx = countTrailingZeros(NonZeros);
5808 SDValue Item = Op.getOperand(Idx);
5810 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5811 // the value are obviously zero, truncate the value to i32 and do the
5812 // insertion that way. Only do this if the value is non-constant or if the
5813 // value is a constant being inserted into element 0. It is cheaper to do
5814 // a constant pool load than it is to do a movd + shuffle.
5815 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5816 (!IsAllConstants || Idx == 0)) {
5817 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5819 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5820 EVT VecVT = MVT::v4i32;
5822 // Truncate the value (which may itself be a constant) to i32, and
5823 // convert it to a vector with movd (S2V+shuffle to zero extend).
5824 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5825 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5827 ISD::BITCAST, dl, VT,
5828 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5832 // If we have a constant or non-constant insertion into the low element of
5833 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5834 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5835 // depending on what the source datatype is.
5838 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5840 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5841 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5842 if (VT.is512BitVector()) {
5843 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5844 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5845 Item, DAG.getIntPtrConstant(0, dl));
5847 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5848 "Expected an SSE value type!");
5849 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5850 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5851 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5854 // We can't directly insert an i8 or i16 into a vector, so zero extend
5856 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5857 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5858 if (VT.is256BitVector()) {
5859 if (Subtarget->hasAVX()) {
5860 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5861 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5863 // Without AVX, we need to extend to a 128-bit vector and then
5864 // insert into the 256-bit vector.
5865 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5866 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5867 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5870 assert(VT.is128BitVector() && "Expected an SSE value type!");
5871 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5872 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5874 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5878 // Is it a vector logical left shift?
5879 if (NumElems == 2 && Idx == 1 &&
5880 X86::isZeroNode(Op.getOperand(0)) &&
5881 !X86::isZeroNode(Op.getOperand(1))) {
5882 unsigned NumBits = VT.getSizeInBits();
5883 return getVShift(true, VT,
5884 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5885 VT, Op.getOperand(1)),
5886 NumBits/2, DAG, *this, dl);
5889 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5892 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5893 // is a non-constant being inserted into an element other than the low one,
5894 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5895 // movd/movss) to move this into the low element, then shuffle it into
5897 if (EVTBits == 32) {
5898 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5899 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5903 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5904 if (Values.size() == 1) {
5905 if (EVTBits == 32) {
5906 // Instead of a shuffle like this:
5907 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5908 // Check if it's possible to issue this instead.
5909 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5910 unsigned Idx = countTrailingZeros(NonZeros);
5911 SDValue Item = Op.getOperand(Idx);
5912 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5913 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5918 // A vector full of immediates; various special cases are already
5919 // handled, so this is best done with a single constant-pool load.
5923 // For AVX-length vectors, see if we can use a vector load to get all of the
5924 // elements, otherwise build the individual 128-bit pieces and use
5925 // shuffles to put them in place.
5926 if (VT.is256BitVector() || VT.is512BitVector()) {
5927 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5929 // Check for a build vector of consecutive loads.
5930 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5933 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5935 // Build both the lower and upper subvector.
5936 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5937 makeArrayRef(&V[0], NumElems/2));
5938 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5939 makeArrayRef(&V[NumElems / 2], NumElems/2));
5941 // Recreate the wider vector with the lower and upper part.
5942 if (VT.is256BitVector())
5943 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5944 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5947 // Let legalizer expand 2-wide build_vectors.
5948 if (EVTBits == 64) {
5949 if (NumNonZero == 1) {
5950 // One half is zero or undef.
5951 unsigned Idx = countTrailingZeros(NonZeros);
5952 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5953 Op.getOperand(Idx));
5954 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5959 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5960 if (EVTBits == 8 && NumElems == 16)
5961 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5965 if (EVTBits == 16 && NumElems == 8)
5966 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5970 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5971 if (EVTBits == 32 && NumElems == 4)
5972 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5975 // If element VT is == 32 bits, turn it into a number of shuffles.
5976 SmallVector<SDValue, 8> V(NumElems);
5977 if (NumElems == 4 && NumZero > 0) {
5978 for (unsigned i = 0; i < 4; ++i) {
5979 bool isZero = !(NonZeros & (1 << i));
5981 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5983 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5986 for (unsigned i = 0; i < 2; ++i) {
5987 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5990 V[i] = V[i*2]; // Must be a zero vector.
5993 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5996 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5999 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6004 bool Reverse1 = (NonZeros & 0x3) == 2;
6005 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6009 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6010 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6012 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6015 if (Values.size() > 1 && VT.is128BitVector()) {
6016 // Check for a build vector of consecutive loads.
6017 for (unsigned i = 0; i < NumElems; ++i)
6018 V[i] = Op.getOperand(i);
6020 // Check for elements which are consecutive loads.
6021 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6024 // Check for a build vector from mostly shuffle plus few inserting.
6025 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6028 // For SSE 4.1, use insertps to put the high elements into the low element.
6029 if (Subtarget->hasSSE41()) {
6031 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6032 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6034 Result = DAG.getUNDEF(VT);
6036 for (unsigned i = 1; i < NumElems; ++i) {
6037 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6038 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6039 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6044 // Otherwise, expand into a number of unpckl*, start by extending each of
6045 // our (non-undef) elements to the full vector width with the element in the
6046 // bottom slot of the vector (which generates no code for SSE).
6047 for (unsigned i = 0; i < NumElems; ++i) {
6048 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6049 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6051 V[i] = DAG.getUNDEF(VT);
6054 // Next, we iteratively mix elements, e.g. for v4f32:
6055 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6056 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6057 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6058 unsigned EltStride = NumElems >> 1;
6059 while (EltStride != 0) {
6060 for (unsigned i = 0; i < EltStride; ++i) {
6061 // If V[i+EltStride] is undef and this is the first round of mixing,
6062 // then it is safe to just drop this shuffle: V[i] is already in the
6063 // right place, the one element (since it's the first round) being
6064 // inserted as undef can be dropped. This isn't safe for successive
6065 // rounds because they will permute elements within both vectors.
6066 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6067 EltStride == NumElems/2)
6070 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6079 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6080 // to create 256-bit vectors from two other 128-bit ones.
6081 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6083 MVT ResVT = Op.getSimpleValueType();
6085 assert((ResVT.is256BitVector() ||
6086 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6088 SDValue V1 = Op.getOperand(0);
6089 SDValue V2 = Op.getOperand(1);
6090 unsigned NumElems = ResVT.getVectorNumElements();
6091 if (ResVT.is256BitVector())
6092 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6094 if (Op.getNumOperands() == 4) {
6095 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6096 ResVT.getVectorNumElements()/2);
6097 SDValue V3 = Op.getOperand(2);
6098 SDValue V4 = Op.getOperand(3);
6099 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6100 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6102 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6105 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6106 const X86Subtarget *Subtarget,
6107 SelectionDAG & DAG) {
6109 MVT ResVT = Op.getSimpleValueType();
6110 unsigned NumOfOperands = Op.getNumOperands();
6112 assert(isPowerOf2_32(NumOfOperands) &&
6113 "Unexpected number of operands in CONCAT_VECTORS");
6115 if (NumOfOperands > 2) {
6116 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6117 ResVT.getVectorNumElements()/2);
6118 SmallVector<SDValue, 2> Ops;
6119 for (unsigned i = 0; i < NumOfOperands/2; i++)
6120 Ops.push_back(Op.getOperand(i));
6121 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6123 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6124 Ops.push_back(Op.getOperand(i));
6125 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6126 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6129 SDValue V1 = Op.getOperand(0);
6130 SDValue V2 = Op.getOperand(1);
6131 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6132 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6134 if (IsZeroV1 && IsZeroV2)
6135 return getZeroVector(ResVT, Subtarget, DAG, dl);
6137 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6138 SDValue Undef = DAG.getUNDEF(ResVT);
6139 unsigned NumElems = ResVT.getVectorNumElements();
6140 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6142 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6143 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6147 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6148 // Zero the upper bits of V1
6149 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6150 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6153 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6156 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6157 const X86Subtarget *Subtarget,
6158 SelectionDAG &DAG) {
6159 MVT VT = Op.getSimpleValueType();
6160 if (VT.getVectorElementType() == MVT::i1)
6161 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6163 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6164 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6165 Op.getNumOperands() == 4)));
6167 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6168 // from two other 128-bit ones.
6170 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6171 return LowerAVXCONCAT_VECTORS(Op, DAG);
6175 //===----------------------------------------------------------------------===//
6176 // Vector shuffle lowering
6178 // This is an experimental code path for lowering vector shuffles on x86. It is
6179 // designed to handle arbitrary vector shuffles and blends, gracefully
6180 // degrading performance as necessary. It works hard to recognize idiomatic
6181 // shuffles and lower them to optimal instruction patterns without leaving
6182 // a framework that allows reasonably efficient handling of all vector shuffle
6184 //===----------------------------------------------------------------------===//
6186 /// \brief Tiny helper function to identify a no-op mask.
6188 /// This is a somewhat boring predicate function. It checks whether the mask
6189 /// array input, which is assumed to be a single-input shuffle mask of the kind
6190 /// used by the X86 shuffle instructions (not a fully general
6191 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6192 /// in-place shuffle are 'no-op's.
6193 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6194 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6195 if (Mask[i] != -1 && Mask[i] != i)
6200 /// \brief Helper function to classify a mask as a single-input mask.
6202 /// This isn't a generic single-input test because in the vector shuffle
6203 /// lowering we canonicalize single inputs to be the first input operand. This
6204 /// means we can more quickly test for a single input by only checking whether
6205 /// an input from the second operand exists. We also assume that the size of
6206 /// mask corresponds to the size of the input vectors which isn't true in the
6207 /// fully general case.
6208 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6210 if (M >= (int)Mask.size())
6215 /// \brief Test whether there are elements crossing 128-bit lanes in this
6218 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6219 /// and we routinely test for these.
6220 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6221 int LaneSize = 128 / VT.getScalarSizeInBits();
6222 int Size = Mask.size();
6223 for (int i = 0; i < Size; ++i)
6224 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6229 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6231 /// This checks a shuffle mask to see if it is performing the same
6232 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6233 /// that it is also not lane-crossing. It may however involve a blend from the
6234 /// same lane of a second vector.
6236 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6237 /// non-trivial to compute in the face of undef lanes. The representation is
6238 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6239 /// entries from both V1 and V2 inputs to the wider mask.
6241 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6242 SmallVectorImpl<int> &RepeatedMask) {
6243 int LaneSize = 128 / VT.getScalarSizeInBits();
6244 RepeatedMask.resize(LaneSize, -1);
6245 int Size = Mask.size();
6246 for (int i = 0; i < Size; ++i) {
6249 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6250 // This entry crosses lanes, so there is no way to model this shuffle.
6253 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6254 if (RepeatedMask[i % LaneSize] == -1)
6255 // This is the first non-undef entry in this slot of a 128-bit lane.
6256 RepeatedMask[i % LaneSize] =
6257 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6258 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6259 // Found a mismatch with the repeated mask.
6265 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6268 /// This is a fast way to test a shuffle mask against a fixed pattern:
6270 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6272 /// It returns true if the mask is exactly as wide as the argument list, and
6273 /// each element of the mask is either -1 (signifying undef) or the value given
6274 /// in the argument.
6275 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6276 ArrayRef<int> ExpectedMask) {
6277 if (Mask.size() != ExpectedMask.size())
6280 int Size = Mask.size();
6282 // If the values are build vectors, we can look through them to find
6283 // equivalent inputs that make the shuffles equivalent.
6284 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6285 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6287 for (int i = 0; i < Size; ++i)
6288 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6289 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6290 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6291 if (!MaskBV || !ExpectedBV ||
6292 MaskBV->getOperand(Mask[i] % Size) !=
6293 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6300 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6302 /// This helper function produces an 8-bit shuffle immediate corresponding to
6303 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6304 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6307 /// NB: We rely heavily on "undef" masks preserving the input lane.
6308 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6309 SelectionDAG &DAG) {
6310 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6311 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6312 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6313 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6314 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6317 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6318 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6319 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6320 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6321 return DAG.getConstant(Imm, DL, MVT::i8);
6324 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6326 /// This is used as a fallback approach when first class blend instructions are
6327 /// unavailable. Currently it is only suitable for integer vectors, but could
6328 /// be generalized for floating point vectors if desirable.
6329 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6330 SDValue V2, ArrayRef<int> Mask,
6331 SelectionDAG &DAG) {
6332 assert(VT.isInteger() && "Only supports integer vector types!");
6333 MVT EltVT = VT.getScalarType();
6334 int NumEltBits = EltVT.getSizeInBits();
6335 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6336 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6338 SmallVector<SDValue, 16> MaskOps;
6339 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6340 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6341 return SDValue(); // Shuffled input!
6342 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6345 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6346 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6347 // We have to cast V2 around.
6348 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6349 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6350 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6351 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6352 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6353 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6356 /// \brief Try to emit a blend instruction for a shuffle.
6358 /// This doesn't do any checks for the availability of instructions for blending
6359 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6360 /// be matched in the backend with the type given. What it does check for is
6361 /// that the shuffle mask is in fact a blend.
6362 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6363 SDValue V2, ArrayRef<int> Mask,
6364 const X86Subtarget *Subtarget,
6365 SelectionDAG &DAG) {
6366 unsigned BlendMask = 0;
6367 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6368 if (Mask[i] >= Size) {
6369 if (Mask[i] != i + Size)
6370 return SDValue(); // Shuffled V2 input!
6371 BlendMask |= 1u << i;
6374 if (Mask[i] >= 0 && Mask[i] != i)
6375 return SDValue(); // Shuffled V1 input!
6377 switch (VT.SimpleTy) {
6382 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6383 DAG.getConstant(BlendMask, DL, MVT::i8));
6387 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6391 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6392 // that instruction.
6393 if (Subtarget->hasAVX2()) {
6394 // Scale the blend by the number of 32-bit dwords per element.
6395 int Scale = VT.getScalarSizeInBits() / 32;
6397 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6398 if (Mask[i] >= Size)
6399 for (int j = 0; j < Scale; ++j)
6400 BlendMask |= 1u << (i * Scale + j);
6402 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6403 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6404 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6405 return DAG.getNode(ISD::BITCAST, DL, VT,
6406 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6407 DAG.getConstant(BlendMask, DL, MVT::i8)));
6411 // For integer shuffles we need to expand the mask and cast the inputs to
6412 // v8i16s prior to blending.
6413 int Scale = 8 / VT.getVectorNumElements();
6415 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6416 if (Mask[i] >= Size)
6417 for (int j = 0; j < Scale; ++j)
6418 BlendMask |= 1u << (i * Scale + j);
6420 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6421 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6422 return DAG.getNode(ISD::BITCAST, DL, VT,
6423 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6424 DAG.getConstant(BlendMask, DL, MVT::i8)));
6428 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6429 SmallVector<int, 8> RepeatedMask;
6430 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6431 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6432 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6434 for (int i = 0; i < 8; ++i)
6435 if (RepeatedMask[i] >= 16)
6436 BlendMask |= 1u << i;
6437 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6438 DAG.getConstant(BlendMask, DL, MVT::i8));
6444 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6445 "256-bit byte-blends require AVX2 support!");
6447 // Scale the blend by the number of bytes per element.
6448 int Scale = VT.getScalarSizeInBits() / 8;
6450 // This form of blend is always done on bytes. Compute the byte vector
6452 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6454 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6455 // mix of LLVM's code generator and the x86 backend. We tell the code
6456 // generator that boolean values in the elements of an x86 vector register
6457 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6458 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6459 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6460 // of the element (the remaining are ignored) and 0 in that high bit would
6461 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6462 // the LLVM model for boolean values in vector elements gets the relevant
6463 // bit set, it is set backwards and over constrained relative to x86's
6465 SmallVector<SDValue, 32> VSELECTMask;
6466 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6467 for (int j = 0; j < Scale; ++j)
6468 VSELECTMask.push_back(
6469 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6470 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6473 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6474 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6476 ISD::BITCAST, DL, VT,
6477 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6478 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6483 llvm_unreachable("Not a supported integer vector type!");
6487 /// \brief Try to lower as a blend of elements from two inputs followed by
6488 /// a single-input permutation.
6490 /// This matches the pattern where we can blend elements from two inputs and
6491 /// then reduce the shuffle to a single-input permutation.
6492 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6495 SelectionDAG &DAG) {
6496 // We build up the blend mask while checking whether a blend is a viable way
6497 // to reduce the shuffle.
6498 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6499 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6501 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6505 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6507 if (BlendMask[Mask[i] % Size] == -1)
6508 BlendMask[Mask[i] % Size] = Mask[i];
6509 else if (BlendMask[Mask[i] % Size] != Mask[i])
6510 return SDValue(); // Can't blend in the needed input!
6512 PermuteMask[i] = Mask[i] % Size;
6515 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6516 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6519 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6520 /// blends and permutes.
6522 /// This matches the extremely common pattern for handling combined
6523 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6524 /// operations. It will try to pick the best arrangement of shuffles and
6526 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6530 SelectionDAG &DAG) {
6531 // Shuffle the input elements into the desired positions in V1 and V2 and
6532 // blend them together.
6533 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6534 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6535 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6536 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6537 if (Mask[i] >= 0 && Mask[i] < Size) {
6538 V1Mask[i] = Mask[i];
6540 } else if (Mask[i] >= Size) {
6541 V2Mask[i] = Mask[i] - Size;
6542 BlendMask[i] = i + Size;
6545 // Try to lower with the simpler initial blend strategy unless one of the
6546 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6547 // shuffle may be able to fold with a load or other benefit. However, when
6548 // we'll have to do 2x as many shuffles in order to achieve this, blending
6549 // first is a better strategy.
6550 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6551 if (SDValue BlendPerm =
6552 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6555 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6556 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6557 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6560 /// \brief Try to lower a vector shuffle as a byte rotation.
6562 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6563 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6564 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6565 /// try to generically lower a vector shuffle through such an pattern. It
6566 /// does not check for the profitability of lowering either as PALIGNR or
6567 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6568 /// This matches shuffle vectors that look like:
6570 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6572 /// Essentially it concatenates V1 and V2, shifts right by some number of
6573 /// elements, and takes the low elements as the result. Note that while this is
6574 /// specified as a *right shift* because x86 is little-endian, it is a *left
6575 /// rotate* of the vector lanes.
6576 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6579 const X86Subtarget *Subtarget,
6580 SelectionDAG &DAG) {
6581 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6583 int NumElts = Mask.size();
6584 int NumLanes = VT.getSizeInBits() / 128;
6585 int NumLaneElts = NumElts / NumLanes;
6587 // We need to detect various ways of spelling a rotation:
6588 // [11, 12, 13, 14, 15, 0, 1, 2]
6589 // [-1, 12, 13, 14, -1, -1, 1, -1]
6590 // [-1, -1, -1, -1, -1, -1, 1, 2]
6591 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6592 // [-1, 4, 5, 6, -1, -1, 9, -1]
6593 // [-1, 4, 5, 6, -1, -1, -1, -1]
6596 for (int l = 0; l < NumElts; l += NumLaneElts) {
6597 for (int i = 0; i < NumLaneElts; ++i) {
6598 if (Mask[l + i] == -1)
6600 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6602 // Get the mod-Size index and lane correct it.
6603 int LaneIdx = (Mask[l + i] % NumElts) - l;
6604 // Make sure it was in this lane.
6605 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6608 // Determine where a rotated vector would have started.
6609 int StartIdx = i - LaneIdx;
6611 // The identity rotation isn't interesting, stop.
6614 // If we found the tail of a vector the rotation must be the missing
6615 // front. If we found the head of a vector, it must be how much of the
6617 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6620 Rotation = CandidateRotation;
6621 else if (Rotation != CandidateRotation)
6622 // The rotations don't match, so we can't match this mask.
6625 // Compute which value this mask is pointing at.
6626 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6628 // Compute which of the two target values this index should be assigned
6629 // to. This reflects whether the high elements are remaining or the low
6630 // elements are remaining.
6631 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6633 // Either set up this value if we've not encountered it before, or check
6634 // that it remains consistent.
6637 else if (TargetV != MaskV)
6638 // This may be a rotation, but it pulls from the inputs in some
6639 // unsupported interleaving.
6644 // Check that we successfully analyzed the mask, and normalize the results.
6645 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6646 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6652 // The actual rotate instruction rotates bytes, so we need to scale the
6653 // rotation based on how many bytes are in the vector lane.
6654 int Scale = 16 / NumLaneElts;
6656 // SSSE3 targets can use the palignr instruction.
6657 if (Subtarget->hasSSSE3()) {
6658 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6659 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6660 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6661 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6663 return DAG.getNode(ISD::BITCAST, DL, VT,
6664 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6665 DAG.getConstant(Rotation * Scale, DL,
6669 assert(VT.getSizeInBits() == 128 &&
6670 "Rotate-based lowering only supports 128-bit lowering!");
6671 assert(Mask.size() <= 16 &&
6672 "Can shuffle at most 16 bytes in a 128-bit vector!");
6674 // Default SSE2 implementation
6675 int LoByteShift = 16 - Rotation * Scale;
6676 int HiByteShift = Rotation * Scale;
6678 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6679 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6680 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6682 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6683 DAG.getConstant(LoByteShift, DL, MVT::i8));
6684 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6685 DAG.getConstant(HiByteShift, DL, MVT::i8));
6686 return DAG.getNode(ISD::BITCAST, DL, VT,
6687 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6690 /// \brief Compute whether each element of a shuffle is zeroable.
6692 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6693 /// Either it is an undef element in the shuffle mask, the element of the input
6694 /// referenced is undef, or the element of the input referenced is known to be
6695 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6696 /// as many lanes with this technique as possible to simplify the remaining
6698 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6699 SDValue V1, SDValue V2) {
6700 SmallBitVector Zeroable(Mask.size(), false);
6702 while (V1.getOpcode() == ISD::BITCAST)
6703 V1 = V1->getOperand(0);
6704 while (V2.getOpcode() == ISD::BITCAST)
6705 V2 = V2->getOperand(0);
6707 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6708 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6710 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6712 // Handle the easy cases.
6713 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6718 // If this is an index into a build_vector node (which has the same number
6719 // of elements), dig out the input value and use it.
6720 SDValue V = M < Size ? V1 : V2;
6721 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6724 SDValue Input = V.getOperand(M % Size);
6725 // The UNDEF opcode check really should be dead code here, but not quite
6726 // worth asserting on (it isn't invalid, just unexpected).
6727 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6734 /// \brief Try to emit a bitmask instruction for a shuffle.
6736 /// This handles cases where we can model a blend exactly as a bitmask due to
6737 /// one of the inputs being zeroable.
6738 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6739 SDValue V2, ArrayRef<int> Mask,
6740 SelectionDAG &DAG) {
6741 MVT EltVT = VT.getScalarType();
6742 int NumEltBits = EltVT.getSizeInBits();
6743 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6744 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6745 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6747 if (EltVT.isFloatingPoint()) {
6748 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6749 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6751 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6752 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6754 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6757 if (Mask[i] % Size != i)
6758 return SDValue(); // Not a blend.
6760 V = Mask[i] < Size ? V1 : V2;
6761 else if (V != (Mask[i] < Size ? V1 : V2))
6762 return SDValue(); // Can only let one input through the mask.
6764 VMaskOps[i] = AllOnes;
6767 return SDValue(); // No non-zeroable elements!
6769 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6770 V = DAG.getNode(VT.isFloatingPoint()
6771 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6776 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6778 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6779 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6780 /// matches elements from one of the input vectors shuffled to the left or
6781 /// right with zeroable elements 'shifted in'. It handles both the strictly
6782 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6785 /// PSHL : (little-endian) left bit shift.
6786 /// [ zz, 0, zz, 2 ]
6787 /// [ -1, 4, zz, -1 ]
6788 /// PSRL : (little-endian) right bit shift.
6790 /// [ -1, -1, 7, zz]
6791 /// PSLLDQ : (little-endian) left byte shift
6792 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6793 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6794 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6795 /// PSRLDQ : (little-endian) right byte shift
6796 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6797 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6798 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6799 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6800 SDValue V2, ArrayRef<int> Mask,
6801 SelectionDAG &DAG) {
6802 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6804 int Size = Mask.size();
6805 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6807 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6808 for (int i = 0; i < Size; i += Scale)
6809 for (int j = 0; j < Shift; ++j)
6810 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6816 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6817 for (int i = 0; i != Size; i += Scale) {
6818 unsigned Pos = Left ? i + Shift : i;
6819 unsigned Low = Left ? i : i + Shift;
6820 unsigned Len = Scale - Shift;
6821 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6822 Low + (V == V1 ? 0 : Size)))
6826 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6827 bool ByteShift = ShiftEltBits > 64;
6828 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6829 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6830 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6832 // Normalize the scale for byte shifts to still produce an i64 element
6834 Scale = ByteShift ? Scale / 2 : Scale;
6836 // We need to round trip through the appropriate type for the shift.
6837 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6838 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6839 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6840 "Illegal integer vector type");
6841 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6843 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6844 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6845 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6848 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6849 // keep doubling the size of the integer elements up to that. We can
6850 // then shift the elements of the integer vector by whole multiples of
6851 // their width within the elements of the larger integer vector. Test each
6852 // multiple to see if we can find a match with the moved element indices
6853 // and that the shifted in elements are all zeroable.
6854 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6855 for (int Shift = 1; Shift != Scale; ++Shift)
6856 for (bool Left : {true, false})
6857 if (CheckZeros(Shift, Scale, Left))
6858 for (SDValue V : {V1, V2})
6859 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6866 /// \brief Lower a vector shuffle as a zero or any extension.
6868 /// Given a specific number of elements, element bit width, and extension
6869 /// stride, produce either a zero or any extension based on the available
6870 /// features of the subtarget.
6871 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6872 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6873 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6874 assert(Scale > 1 && "Need a scale to extend.");
6875 int NumElements = VT.getVectorNumElements();
6876 int EltBits = VT.getScalarSizeInBits();
6877 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6878 "Only 8, 16, and 32 bit elements can be extended.");
6879 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6881 // Found a valid zext mask! Try various lowering strategies based on the
6882 // input type and available ISA extensions.
6883 if (Subtarget->hasSSE41()) {
6884 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6885 NumElements / Scale);
6886 return DAG.getNode(ISD::BITCAST, DL, VT,
6887 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6890 // For any extends we can cheat for larger element sizes and use shuffle
6891 // instructions that can fold with a load and/or copy.
6892 if (AnyExt && EltBits == 32) {
6893 int PSHUFDMask[4] = {0, -1, 1, -1};
6895 ISD::BITCAST, DL, VT,
6896 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6897 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6898 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6900 if (AnyExt && EltBits == 16 && Scale > 2) {
6901 int PSHUFDMask[4] = {0, -1, 0, -1};
6902 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6903 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6904 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6905 int PSHUFHWMask[4] = {1, -1, -1, -1};
6907 ISD::BITCAST, DL, VT,
6908 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6909 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6910 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6913 // If this would require more than 2 unpack instructions to expand, use
6914 // pshufb when available. We can only use more than 2 unpack instructions
6915 // when zero extending i8 elements which also makes it easier to use pshufb.
6916 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6917 assert(NumElements == 16 && "Unexpected byte vector width!");
6918 SDValue PSHUFBMask[16];
6919 for (int i = 0; i < 16; ++i)
6921 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6922 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6923 return DAG.getNode(ISD::BITCAST, DL, VT,
6924 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6925 DAG.getNode(ISD::BUILD_VECTOR, DL,
6926 MVT::v16i8, PSHUFBMask)));
6929 // Otherwise emit a sequence of unpacks.
6931 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6932 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6933 : getZeroVector(InputVT, Subtarget, DAG, DL);
6934 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6935 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6939 } while (Scale > 1);
6940 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6943 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6945 /// This routine will try to do everything in its power to cleverly lower
6946 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6947 /// check for the profitability of this lowering, it tries to aggressively
6948 /// match this pattern. It will use all of the micro-architectural details it
6949 /// can to emit an efficient lowering. It handles both blends with all-zero
6950 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6951 /// masking out later).
6953 /// The reason we have dedicated lowering for zext-style shuffles is that they
6954 /// are both incredibly common and often quite performance sensitive.
6955 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6956 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6957 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6958 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6960 int Bits = VT.getSizeInBits();
6961 int NumElements = VT.getVectorNumElements();
6962 assert(VT.getScalarSizeInBits() <= 32 &&
6963 "Exceeds 32-bit integer zero extension limit");
6964 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6966 // Define a helper function to check a particular ext-scale and lower to it if
6968 auto Lower = [&](int Scale) -> SDValue {
6971 for (int i = 0; i < NumElements; ++i) {
6973 continue; // Valid anywhere but doesn't tell us anything.
6974 if (i % Scale != 0) {
6975 // Each of the extended elements need to be zeroable.
6979 // We no longer are in the anyext case.
6984 // Each of the base elements needs to be consecutive indices into the
6985 // same input vector.
6986 SDValue V = Mask[i] < NumElements ? V1 : V2;
6989 else if (InputV != V)
6990 return SDValue(); // Flip-flopping inputs.
6992 if (Mask[i] % NumElements != i / Scale)
6993 return SDValue(); // Non-consecutive strided elements.
6996 // If we fail to find an input, we have a zero-shuffle which should always
6997 // have already been handled.
6998 // FIXME: Maybe handle this here in case during blending we end up with one?
7002 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7003 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
7006 // The widest scale possible for extending is to a 64-bit integer.
7007 assert(Bits % 64 == 0 &&
7008 "The number of bits in a vector must be divisible by 64 on x86!");
7009 int NumExtElements = Bits / 64;
7011 // Each iteration, try extending the elements half as much, but into twice as
7013 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7014 assert(NumElements % NumExtElements == 0 &&
7015 "The input vector size must be divisible by the extended size.");
7016 if (SDValue V = Lower(NumElements / NumExtElements))
7020 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7024 // Returns one of the source operands if the shuffle can be reduced to a
7025 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7026 auto CanZExtLowHalf = [&]() {
7027 for (int i = NumElements / 2; i != NumElements; ++i)
7030 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7032 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7037 if (SDValue V = CanZExtLowHalf()) {
7038 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
7039 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7040 return DAG.getNode(ISD::BITCAST, DL, VT, V);
7043 // No viable ext lowering found.
7047 /// \brief Try to get a scalar value for a specific element of a vector.
7049 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7050 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7051 SelectionDAG &DAG) {
7052 MVT VT = V.getSimpleValueType();
7053 MVT EltVT = VT.getVectorElementType();
7054 while (V.getOpcode() == ISD::BITCAST)
7055 V = V.getOperand(0);
7056 // If the bitcasts shift the element size, we can't extract an equivalent
7058 MVT NewVT = V.getSimpleValueType();
7059 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7062 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7063 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7064 // Ensure the scalar operand is the same size as the destination.
7065 // FIXME: Add support for scalar truncation where possible.
7066 SDValue S = V.getOperand(Idx);
7067 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7068 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7074 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7076 /// This is particularly important because the set of instructions varies
7077 /// significantly based on whether the operand is a load or not.
7078 static bool isShuffleFoldableLoad(SDValue V) {
7079 while (V.getOpcode() == ISD::BITCAST)
7080 V = V.getOperand(0);
7082 return ISD::isNON_EXTLoad(V.getNode());
7085 /// \brief Try to lower insertion of a single element into a zero vector.
7087 /// This is a common pattern that we have especially efficient patterns to lower
7088 /// across all subtarget feature sets.
7089 static SDValue lowerVectorShuffleAsElementInsertion(
7090 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7091 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7092 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7094 MVT EltVT = VT.getVectorElementType();
7096 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7097 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7099 bool IsV1Zeroable = true;
7100 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7101 if (i != V2Index && !Zeroable[i]) {
7102 IsV1Zeroable = false;
7106 // Check for a single input from a SCALAR_TO_VECTOR node.
7107 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7108 // all the smarts here sunk into that routine. However, the current
7109 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7110 // vector shuffle lowering is dead.
7111 if (SDValue V2S = getScalarValueForVectorElement(
7112 V2, Mask[V2Index] - Mask.size(), DAG)) {
7113 // We need to zext the scalar if it is smaller than an i32.
7114 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7115 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7116 // Using zext to expand a narrow element won't work for non-zero
7121 // Zero-extend directly to i32.
7123 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7125 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7126 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7127 EltVT == MVT::i16) {
7128 // Either not inserting from the low element of the input or the input
7129 // element size is too small to use VZEXT_MOVL to clear the high bits.
7133 if (!IsV1Zeroable) {
7134 // If V1 can't be treated as a zero vector we have fewer options to lower
7135 // this. We can't support integer vectors or non-zero targets cheaply, and
7136 // the V1 elements can't be permuted in any way.
7137 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7138 if (!VT.isFloatingPoint() || V2Index != 0)
7140 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7141 V1Mask[V2Index] = -1;
7142 if (!isNoopShuffleMask(V1Mask))
7144 // This is essentially a special case blend operation, but if we have
7145 // general purpose blend operations, they are always faster. Bail and let
7146 // the rest of the lowering handle these as blends.
7147 if (Subtarget->hasSSE41())
7150 // Otherwise, use MOVSD or MOVSS.
7151 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7152 "Only two types of floating point element types to handle!");
7153 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7157 // This lowering only works for the low element with floating point vectors.
7158 if (VT.isFloatingPoint() && V2Index != 0)
7161 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7163 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7166 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7167 // the desired position. Otherwise it is more efficient to do a vector
7168 // shift left. We know that we can do a vector shift left because all
7169 // the inputs are zero.
7170 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7171 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7172 V2Shuffle[V2Index] = 0;
7173 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7175 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7177 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7179 V2Index * EltVT.getSizeInBits()/8, DL,
7180 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7181 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7187 /// \brief Try to lower broadcast of a single element.
7189 /// For convenience, this code also bundles all of the subtarget feature set
7190 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7191 /// a convenient way to factor it out.
7192 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7194 const X86Subtarget *Subtarget,
7195 SelectionDAG &DAG) {
7196 if (!Subtarget->hasAVX())
7198 if (VT.isInteger() && !Subtarget->hasAVX2())
7201 // Check that the mask is a broadcast.
7202 int BroadcastIdx = -1;
7204 if (M >= 0 && BroadcastIdx == -1)
7206 else if (M >= 0 && M != BroadcastIdx)
7209 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7210 "a sorted mask where the broadcast "
7213 // Go up the chain of (vector) values to find a scalar load that we can
7214 // combine with the broadcast.
7216 switch (V.getOpcode()) {
7217 case ISD::CONCAT_VECTORS: {
7218 int OperandSize = Mask.size() / V.getNumOperands();
7219 V = V.getOperand(BroadcastIdx / OperandSize);
7220 BroadcastIdx %= OperandSize;
7224 case ISD::INSERT_SUBVECTOR: {
7225 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7226 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7230 int BeginIdx = (int)ConstantIdx->getZExtValue();
7232 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7233 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7234 BroadcastIdx -= BeginIdx;
7245 // Check if this is a broadcast of a scalar. We special case lowering
7246 // for scalars so that we can more effectively fold with loads.
7247 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7248 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7249 V = V.getOperand(BroadcastIdx);
7251 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7252 // Only AVX2 has register broadcasts.
7253 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7255 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7256 // We can't broadcast from a vector register without AVX2, and we can only
7257 // broadcast from the zero-element of a vector register.
7261 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7264 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7265 // INSERTPS when the V1 elements are already in the correct locations
7266 // because otherwise we can just always use two SHUFPS instructions which
7267 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7268 // perform INSERTPS if a single V1 element is out of place and all V2
7269 // elements are zeroable.
7270 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7272 SelectionDAG &DAG) {
7273 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7274 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7275 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7276 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7278 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7281 int V1DstIndex = -1;
7282 int V2DstIndex = -1;
7283 bool V1UsedInPlace = false;
7285 for (int i = 0; i < 4; ++i) {
7286 // Synthesize a zero mask from the zeroable elements (includes undefs).
7292 // Flag if we use any V1 inputs in place.
7294 V1UsedInPlace = true;
7298 // We can only insert a single non-zeroable element.
7299 if (V1DstIndex != -1 || V2DstIndex != -1)
7303 // V1 input out of place for insertion.
7306 // V2 input for insertion.
7311 // Don't bother if we have no (non-zeroable) element for insertion.
7312 if (V1DstIndex == -1 && V2DstIndex == -1)
7315 // Determine element insertion src/dst indices. The src index is from the
7316 // start of the inserted vector, not the start of the concatenated vector.
7317 unsigned V2SrcIndex = 0;
7318 if (V1DstIndex != -1) {
7319 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7320 // and don't use the original V2 at all.
7321 V2SrcIndex = Mask[V1DstIndex];
7322 V2DstIndex = V1DstIndex;
7325 V2SrcIndex = Mask[V2DstIndex] - 4;
7328 // If no V1 inputs are used in place, then the result is created only from
7329 // the zero mask and the V2 insertion - so remove V1 dependency.
7331 V1 = DAG.getUNDEF(MVT::v4f32);
7333 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7334 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7336 // Insert the V2 element into the desired position.
7338 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7339 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7342 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7343 /// UNPCK instruction.
7345 /// This specifically targets cases where we end up with alternating between
7346 /// the two inputs, and so can permute them into something that feeds a single
7347 /// UNPCK instruction. Note that this routine only targets integer vectors
7348 /// because for floating point vectors we have a generalized SHUFPS lowering
7349 /// strategy that handles everything that doesn't *exactly* match an unpack,
7350 /// making this clever lowering unnecessary.
7351 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7352 SDValue V2, ArrayRef<int> Mask,
7353 SelectionDAG &DAG) {
7354 assert(!VT.isFloatingPoint() &&
7355 "This routine only supports integer vectors.");
7356 assert(!isSingleInputShuffleMask(Mask) &&
7357 "This routine should only be used when blending two inputs.");
7358 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7360 int Size = Mask.size();
7362 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7363 return M >= 0 && M % Size < Size / 2;
7365 int NumHiInputs = std::count_if(
7366 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7368 bool UnpackLo = NumLoInputs >= NumHiInputs;
7370 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7371 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7372 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7374 for (int i = 0; i < Size; ++i) {
7378 // Each element of the unpack contains Scale elements from this mask.
7379 int UnpackIdx = i / Scale;
7381 // We only handle the case where V1 feeds the first slots of the unpack.
7382 // We rely on canonicalization to ensure this is the case.
7383 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7386 // Setup the mask for this input. The indexing is tricky as we have to
7387 // handle the unpack stride.
7388 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7389 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7393 // If we will have to shuffle both inputs to use the unpack, check whether
7394 // we can just unpack first and shuffle the result. If so, skip this unpack.
7395 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7396 !isNoopShuffleMask(V2Mask))
7399 // Shuffle the inputs into place.
7400 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7401 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7403 // Cast the inputs to the type we will use to unpack them.
7404 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7405 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7407 // Unpack the inputs and cast the result back to the desired type.
7408 return DAG.getNode(ISD::BITCAST, DL, VT,
7409 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7410 DL, UnpackVT, V1, V2));
7413 // We try each unpack from the largest to the smallest to try and find one
7414 // that fits this mask.
7415 int OrigNumElements = VT.getVectorNumElements();
7416 int OrigScalarSize = VT.getScalarSizeInBits();
7417 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7418 int Scale = ScalarSize / OrigScalarSize;
7419 int NumElements = OrigNumElements / Scale;
7420 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7421 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7425 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7427 if (NumLoInputs == 0 || NumHiInputs == 0) {
7428 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7429 "We have to have *some* inputs!");
7430 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7432 // FIXME: We could consider the total complexity of the permute of each
7433 // possible unpacking. Or at the least we should consider how many
7434 // half-crossings are created.
7435 // FIXME: We could consider commuting the unpacks.
7437 SmallVector<int, 32> PermMask;
7438 PermMask.assign(Size, -1);
7439 for (int i = 0; i < Size; ++i) {
7443 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7446 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7448 return DAG.getVectorShuffle(
7449 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7451 DAG.getUNDEF(VT), PermMask);
7457 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7459 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7460 /// support for floating point shuffles but not integer shuffles. These
7461 /// instructions will incur a domain crossing penalty on some chips though so
7462 /// it is better to avoid lowering through this for integer vectors where
7464 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7465 const X86Subtarget *Subtarget,
7466 SelectionDAG &DAG) {
7468 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7469 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7470 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7472 ArrayRef<int> Mask = SVOp->getMask();
7473 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7475 if (isSingleInputShuffleMask(Mask)) {
7476 // Use low duplicate instructions for masks that match their pattern.
7477 if (Subtarget->hasSSE3())
7478 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7479 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7481 // Straight shuffle of a single input vector. Simulate this by using the
7482 // single input as both of the "inputs" to this instruction..
7483 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7485 if (Subtarget->hasAVX()) {
7486 // If we have AVX, we can use VPERMILPS which will allow folding a load
7487 // into the shuffle.
7488 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7489 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7492 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7493 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7495 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7496 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7498 // If we have a single input, insert that into V1 if we can do so cheaply.
7499 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7500 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7501 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7503 // Try inverting the insertion since for v2 masks it is easy to do and we
7504 // can't reliably sort the mask one way or the other.
7505 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7506 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7507 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7508 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7512 // Try to use one of the special instruction patterns to handle two common
7513 // blend patterns if a zero-blend above didn't work.
7514 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7515 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7516 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7517 // We can either use a special instruction to load over the low double or
7518 // to move just the low double.
7520 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7522 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7524 if (Subtarget->hasSSE41())
7525 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7529 // Use dedicated unpack instructions for masks that match their pattern.
7530 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7531 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7532 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7533 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7535 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7536 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7537 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7540 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7542 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7543 /// the integer unit to minimize domain crossing penalties. However, for blends
7544 /// it falls back to the floating point shuffle operation with appropriate bit
7546 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7547 const X86Subtarget *Subtarget,
7548 SelectionDAG &DAG) {
7550 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7551 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7552 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7554 ArrayRef<int> Mask = SVOp->getMask();
7555 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7557 if (isSingleInputShuffleMask(Mask)) {
7558 // Check for being able to broadcast a single element.
7559 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7560 Mask, Subtarget, DAG))
7563 // Straight shuffle of a single input vector. For everything from SSE2
7564 // onward this has a single fast instruction with no scary immediates.
7565 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7566 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7567 int WidenedMask[4] = {
7568 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7569 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7571 ISD::BITCAST, DL, MVT::v2i64,
7572 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7573 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7575 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7576 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7577 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7578 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7580 // If we have a blend of two PACKUS operations an the blend aligns with the
7581 // low and half halves, we can just merge the PACKUS operations. This is
7582 // particularly important as it lets us merge shuffles that this routine itself
7584 auto GetPackNode = [](SDValue V) {
7585 while (V.getOpcode() == ISD::BITCAST)
7586 V = V.getOperand(0);
7588 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7590 if (SDValue V1Pack = GetPackNode(V1))
7591 if (SDValue V2Pack = GetPackNode(V2))
7592 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7593 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7594 Mask[0] == 0 ? V1Pack.getOperand(0)
7595 : V1Pack.getOperand(1),
7596 Mask[1] == 2 ? V2Pack.getOperand(0)
7597 : V2Pack.getOperand(1)));
7599 // Try to use shift instructions.
7601 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7604 // When loading a scalar and then shuffling it into a vector we can often do
7605 // the insertion cheaply.
7606 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7607 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7609 // Try inverting the insertion since for v2 masks it is easy to do and we
7610 // can't reliably sort the mask one way or the other.
7611 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7612 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7613 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7616 // We have different paths for blend lowering, but they all must use the
7617 // *exact* same predicate.
7618 bool IsBlendSupported = Subtarget->hasSSE41();
7619 if (IsBlendSupported)
7620 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7624 // Use dedicated unpack instructions for masks that match their pattern.
7625 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7626 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7627 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7628 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7630 // Try to use byte rotation instructions.
7631 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7632 if (Subtarget->hasSSSE3())
7633 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7634 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7637 // If we have direct support for blends, we should lower by decomposing into
7638 // a permute. That will be faster than the domain cross.
7639 if (IsBlendSupported)
7640 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7643 // We implement this with SHUFPD which is pretty lame because it will likely
7644 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7645 // However, all the alternatives are still more cycles and newer chips don't
7646 // have this problem. It would be really nice if x86 had better shuffles here.
7647 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7648 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7649 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7650 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7653 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7655 /// This is used to disable more specialized lowerings when the shufps lowering
7656 /// will happen to be efficient.
7657 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7658 // This routine only handles 128-bit shufps.
7659 assert(Mask.size() == 4 && "Unsupported mask size!");
7661 // To lower with a single SHUFPS we need to have the low half and high half
7662 // each requiring a single input.
7663 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7665 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7671 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7673 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7674 /// It makes no assumptions about whether this is the *best* lowering, it simply
7676 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7677 ArrayRef<int> Mask, SDValue V1,
7678 SDValue V2, SelectionDAG &DAG) {
7679 SDValue LowV = V1, HighV = V2;
7680 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7683 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7685 if (NumV2Elements == 1) {
7687 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7690 // Compute the index adjacent to V2Index and in the same half by toggling
7692 int V2AdjIndex = V2Index ^ 1;
7694 if (Mask[V2AdjIndex] == -1) {
7695 // Handles all the cases where we have a single V2 element and an undef.
7696 // This will only ever happen in the high lanes because we commute the
7697 // vector otherwise.
7699 std::swap(LowV, HighV);
7700 NewMask[V2Index] -= 4;
7702 // Handle the case where the V2 element ends up adjacent to a V1 element.
7703 // To make this work, blend them together as the first step.
7704 int V1Index = V2AdjIndex;
7705 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7706 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7707 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7709 // Now proceed to reconstruct the final blend as we have the necessary
7710 // high or low half formed.
7717 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7718 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7720 } else if (NumV2Elements == 2) {
7721 if (Mask[0] < 4 && Mask[1] < 4) {
7722 // Handle the easy case where we have V1 in the low lanes and V2 in the
7726 } else if (Mask[2] < 4 && Mask[3] < 4) {
7727 // We also handle the reversed case because this utility may get called
7728 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7729 // arrange things in the right direction.
7735 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7736 // trying to place elements directly, just blend them and set up the final
7737 // shuffle to place them.
7739 // The first two blend mask elements are for V1, the second two are for
7741 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7742 Mask[2] < 4 ? Mask[2] : Mask[3],
7743 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7744 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7745 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7746 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7748 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7751 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7752 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7753 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7754 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7757 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7758 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7761 /// \brief Lower 4-lane 32-bit floating point shuffles.
7763 /// Uses instructions exclusively from the floating point unit to minimize
7764 /// domain crossing penalties, as these are sufficient to implement all v4f32
7766 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7767 const X86Subtarget *Subtarget,
7768 SelectionDAG &DAG) {
7770 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7771 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7772 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7773 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7774 ArrayRef<int> Mask = SVOp->getMask();
7775 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7778 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7780 if (NumV2Elements == 0) {
7781 // Check for being able to broadcast a single element.
7782 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7783 Mask, Subtarget, DAG))
7786 // Use even/odd duplicate instructions for masks that match their pattern.
7787 if (Subtarget->hasSSE3()) {
7788 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7789 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7790 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7791 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7794 if (Subtarget->hasAVX()) {
7795 // If we have AVX, we can use VPERMILPS which will allow folding a load
7796 // into the shuffle.
7797 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7798 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7801 // Otherwise, use a straight shuffle of a single input vector. We pass the
7802 // input vector to both operands to simulate this with a SHUFPS.
7803 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7804 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7807 // There are special ways we can lower some single-element blends. However, we
7808 // have custom ways we can lower more complex single-element blends below that
7809 // we defer to if both this and BLENDPS fail to match, so restrict this to
7810 // when the V2 input is targeting element 0 of the mask -- that is the fast
7812 if (NumV2Elements == 1 && Mask[0] >= 4)
7813 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7814 Mask, Subtarget, DAG))
7817 if (Subtarget->hasSSE41()) {
7818 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7822 // Use INSERTPS if we can complete the shuffle efficiently.
7823 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7826 if (!isSingleSHUFPSMask(Mask))
7827 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7828 DL, MVT::v4f32, V1, V2, Mask, DAG))
7832 // Use dedicated unpack instructions for masks that match their pattern.
7833 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7834 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7835 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7836 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7837 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7838 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7839 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7840 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7842 // Otherwise fall back to a SHUFPS lowering strategy.
7843 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7846 /// \brief Lower 4-lane i32 vector shuffles.
7848 /// We try to handle these with integer-domain shuffles where we can, but for
7849 /// blends we use the floating point domain blend instructions.
7850 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7851 const X86Subtarget *Subtarget,
7852 SelectionDAG &DAG) {
7854 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7855 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7856 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7858 ArrayRef<int> Mask = SVOp->getMask();
7859 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7861 // Whenever we can lower this as a zext, that instruction is strictly faster
7862 // than any alternative. It also allows us to fold memory operands into the
7863 // shuffle in many cases.
7864 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7865 Mask, Subtarget, DAG))
7869 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7871 if (NumV2Elements == 0) {
7872 // Check for being able to broadcast a single element.
7873 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7874 Mask, Subtarget, DAG))
7877 // Straight shuffle of a single input vector. For everything from SSE2
7878 // onward this has a single fast instruction with no scary immediates.
7879 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7880 // but we aren't actually going to use the UNPCK instruction because doing
7881 // so prevents folding a load into this instruction or making a copy.
7882 const int UnpackLoMask[] = {0, 0, 1, 1};
7883 const int UnpackHiMask[] = {2, 2, 3, 3};
7884 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7885 Mask = UnpackLoMask;
7886 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7887 Mask = UnpackHiMask;
7889 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7890 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7893 // Try to use shift instructions.
7895 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7898 // There are special ways we can lower some single-element blends.
7899 if (NumV2Elements == 1)
7900 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7901 Mask, Subtarget, DAG))
7904 // We have different paths for blend lowering, but they all must use the
7905 // *exact* same predicate.
7906 bool IsBlendSupported = Subtarget->hasSSE41();
7907 if (IsBlendSupported)
7908 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7912 if (SDValue Masked =
7913 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7916 // Use dedicated unpack instructions for masks that match their pattern.
7917 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7918 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7919 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7920 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7921 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7922 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7923 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7924 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7926 // Try to use byte rotation instructions.
7927 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7928 if (Subtarget->hasSSSE3())
7929 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7930 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7933 // If we have direct support for blends, we should lower by decomposing into
7934 // a permute. That will be faster than the domain cross.
7935 if (IsBlendSupported)
7936 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7939 // Try to lower by permuting the inputs into an unpack instruction.
7940 if (SDValue Unpack =
7941 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7944 // We implement this with SHUFPS because it can blend from two vectors.
7945 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7946 // up the inputs, bypassing domain shift penalties that we would encur if we
7947 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7949 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7950 DAG.getVectorShuffle(
7952 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7953 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7956 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7957 /// shuffle lowering, and the most complex part.
7959 /// The lowering strategy is to try to form pairs of input lanes which are
7960 /// targeted at the same half of the final vector, and then use a dword shuffle
7961 /// to place them onto the right half, and finally unpack the paired lanes into
7962 /// their final position.
7964 /// The exact breakdown of how to form these dword pairs and align them on the
7965 /// correct sides is really tricky. See the comments within the function for
7966 /// more of the details.
7968 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7969 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7970 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7971 /// vector, form the analogous 128-bit 8-element Mask.
7972 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7973 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7974 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7975 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7976 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7978 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7979 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7980 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7982 SmallVector<int, 4> LoInputs;
7983 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7984 [](int M) { return M >= 0; });
7985 std::sort(LoInputs.begin(), LoInputs.end());
7986 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7987 SmallVector<int, 4> HiInputs;
7988 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7989 [](int M) { return M >= 0; });
7990 std::sort(HiInputs.begin(), HiInputs.end());
7991 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7993 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7994 int NumHToL = LoInputs.size() - NumLToL;
7996 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7997 int NumHToH = HiInputs.size() - NumLToH;
7998 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7999 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8000 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8001 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8003 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8004 // such inputs we can swap two of the dwords across the half mark and end up
8005 // with <=2 inputs to each half in each half. Once there, we can fall through
8006 // to the generic code below. For example:
8008 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8009 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8011 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8012 // and an existing 2-into-2 on the other half. In this case we may have to
8013 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8014 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8015 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8016 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8017 // half than the one we target for fixing) will be fixed when we re-enter this
8018 // path. We will also combine away any sequence of PSHUFD instructions that
8019 // result into a single instruction. Here is an example of the tricky case:
8021 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8022 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8024 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8026 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8027 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8029 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8030 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8032 // The result is fine to be handled by the generic logic.
8033 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8034 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8035 int AOffset, int BOffset) {
8036 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8037 "Must call this with A having 3 or 1 inputs from the A half.");
8038 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8039 "Must call this with B having 1 or 3 inputs from the B half.");
8040 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8041 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8043 // Compute the index of dword with only one word among the three inputs in
8044 // a half by taking the sum of the half with three inputs and subtracting
8045 // the sum of the actual three inputs. The difference is the remaining
8048 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8049 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8050 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8051 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8052 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8053 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8054 int TripleNonInputIdx =
8055 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8056 TripleDWord = TripleNonInputIdx / 2;
8058 // We use xor with one to compute the adjacent DWord to whichever one the
8060 OneInputDWord = (OneInput / 2) ^ 1;
8062 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8063 // and BToA inputs. If there is also such a problem with the BToB and AToB
8064 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8065 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8066 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8067 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8068 // Compute how many inputs will be flipped by swapping these DWords. We
8070 // to balance this to ensure we don't form a 3-1 shuffle in the other
8072 int NumFlippedAToBInputs =
8073 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8074 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8075 int NumFlippedBToBInputs =
8076 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8077 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8078 if ((NumFlippedAToBInputs == 1 &&
8079 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8080 (NumFlippedBToBInputs == 1 &&
8081 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8082 // We choose whether to fix the A half or B half based on whether that
8083 // half has zero flipped inputs. At zero, we may not be able to fix it
8084 // with that half. We also bias towards fixing the B half because that
8085 // will more commonly be the high half, and we have to bias one way.
8086 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8087 ArrayRef<int> Inputs) {
8088 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8089 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8090 PinnedIdx ^ 1) != Inputs.end();
8091 // Determine whether the free index is in the flipped dword or the
8092 // unflipped dword based on where the pinned index is. We use this bit
8093 // in an xor to conditionally select the adjacent dword.
8094 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8095 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8096 FixFreeIdx) != Inputs.end();
8097 if (IsFixIdxInput == IsFixFreeIdxInput)
8099 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8100 FixFreeIdx) != Inputs.end();
8101 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8102 "We need to be changing the number of flipped inputs!");
8103 int PSHUFHalfMask[] = {0, 1, 2, 3};
8104 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8105 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8107 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8110 if (M != -1 && M == FixIdx)
8112 else if (M != -1 && M == FixFreeIdx)
8115 if (NumFlippedBToBInputs != 0) {
8117 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8118 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8120 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8122 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8123 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8128 int PSHUFDMask[] = {0, 1, 2, 3};
8129 PSHUFDMask[ADWord] = BDWord;
8130 PSHUFDMask[BDWord] = ADWord;
8131 V = DAG.getNode(ISD::BITCAST, DL, VT,
8132 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8133 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8134 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8137 // Adjust the mask to match the new locations of A and B.
8139 if (M != -1 && M/2 == ADWord)
8140 M = 2 * BDWord + M % 2;
8141 else if (M != -1 && M/2 == BDWord)
8142 M = 2 * ADWord + M % 2;
8144 // Recurse back into this routine to re-compute state now that this isn't
8145 // a 3 and 1 problem.
8146 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8149 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8150 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8151 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8152 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8154 // At this point there are at most two inputs to the low and high halves from
8155 // each half. That means the inputs can always be grouped into dwords and
8156 // those dwords can then be moved to the correct half with a dword shuffle.
8157 // We use at most one low and one high word shuffle to collect these paired
8158 // inputs into dwords, and finally a dword shuffle to place them.
8159 int PSHUFLMask[4] = {-1, -1, -1, -1};
8160 int PSHUFHMask[4] = {-1, -1, -1, -1};
8161 int PSHUFDMask[4] = {-1, -1, -1, -1};
8163 // First fix the masks for all the inputs that are staying in their
8164 // original halves. This will then dictate the targets of the cross-half
8166 auto fixInPlaceInputs =
8167 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8168 MutableArrayRef<int> SourceHalfMask,
8169 MutableArrayRef<int> HalfMask, int HalfOffset) {
8170 if (InPlaceInputs.empty())
8172 if (InPlaceInputs.size() == 1) {
8173 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8174 InPlaceInputs[0] - HalfOffset;
8175 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8178 if (IncomingInputs.empty()) {
8179 // Just fix all of the in place inputs.
8180 for (int Input : InPlaceInputs) {
8181 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8182 PSHUFDMask[Input / 2] = Input / 2;
8187 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8188 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8189 InPlaceInputs[0] - HalfOffset;
8190 // Put the second input next to the first so that they are packed into
8191 // a dword. We find the adjacent index by toggling the low bit.
8192 int AdjIndex = InPlaceInputs[0] ^ 1;
8193 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8194 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8195 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8197 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8198 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8200 // Now gather the cross-half inputs and place them into a free dword of
8201 // their target half.
8202 // FIXME: This operation could almost certainly be simplified dramatically to
8203 // look more like the 3-1 fixing operation.
8204 auto moveInputsToRightHalf = [&PSHUFDMask](
8205 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8206 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8207 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8209 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8210 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8212 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8214 int LowWord = Word & ~1;
8215 int HighWord = Word | 1;
8216 return isWordClobbered(SourceHalfMask, LowWord) ||
8217 isWordClobbered(SourceHalfMask, HighWord);
8220 if (IncomingInputs.empty())
8223 if (ExistingInputs.empty()) {
8224 // Map any dwords with inputs from them into the right half.
8225 for (int Input : IncomingInputs) {
8226 // If the source half mask maps over the inputs, turn those into
8227 // swaps and use the swapped lane.
8228 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8229 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8230 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8231 Input - SourceOffset;
8232 // We have to swap the uses in our half mask in one sweep.
8233 for (int &M : HalfMask)
8234 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8236 else if (M == Input)
8237 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8239 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8240 Input - SourceOffset &&
8241 "Previous placement doesn't match!");
8243 // Note that this correctly re-maps both when we do a swap and when
8244 // we observe the other side of the swap above. We rely on that to
8245 // avoid swapping the members of the input list directly.
8246 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8249 // Map the input's dword into the correct half.
8250 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8251 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8253 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8255 "Previous placement doesn't match!");
8258 // And just directly shift any other-half mask elements to be same-half
8259 // as we will have mirrored the dword containing the element into the
8260 // same position within that half.
8261 for (int &M : HalfMask)
8262 if (M >= SourceOffset && M < SourceOffset + 4) {
8263 M = M - SourceOffset + DestOffset;
8264 assert(M >= 0 && "This should never wrap below zero!");
8269 // Ensure we have the input in a viable dword of its current half. This
8270 // is particularly tricky because the original position may be clobbered
8271 // by inputs being moved and *staying* in that half.
8272 if (IncomingInputs.size() == 1) {
8273 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8274 int InputFixed = std::find(std::begin(SourceHalfMask),
8275 std::end(SourceHalfMask), -1) -
8276 std::begin(SourceHalfMask) + SourceOffset;
8277 SourceHalfMask[InputFixed - SourceOffset] =
8278 IncomingInputs[0] - SourceOffset;
8279 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8281 IncomingInputs[0] = InputFixed;
8283 } else if (IncomingInputs.size() == 2) {
8284 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8285 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8286 // We have two non-adjacent or clobbered inputs we need to extract from
8287 // the source half. To do this, we need to map them into some adjacent
8288 // dword slot in the source mask.
8289 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8290 IncomingInputs[1] - SourceOffset};
8292 // If there is a free slot in the source half mask adjacent to one of
8293 // the inputs, place the other input in it. We use (Index XOR 1) to
8294 // compute an adjacent index.
8295 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8296 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8297 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8298 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8299 InputsFixed[1] = InputsFixed[0] ^ 1;
8300 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8301 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8302 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8303 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8304 InputsFixed[0] = InputsFixed[1] ^ 1;
8305 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8306 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8307 // The two inputs are in the same DWord but it is clobbered and the
8308 // adjacent DWord isn't used at all. Move both inputs to the free
8310 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8311 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8312 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8313 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8315 // The only way we hit this point is if there is no clobbering
8316 // (because there are no off-half inputs to this half) and there is no
8317 // free slot adjacent to one of the inputs. In this case, we have to
8318 // swap an input with a non-input.
8319 for (int i = 0; i < 4; ++i)
8320 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8321 "We can't handle any clobbers here!");
8322 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8323 "Cannot have adjacent inputs here!");
8325 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8326 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8328 // We also have to update the final source mask in this case because
8329 // it may need to undo the above swap.
8330 for (int &M : FinalSourceHalfMask)
8331 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8332 M = InputsFixed[1] + SourceOffset;
8333 else if (M == InputsFixed[1] + SourceOffset)
8334 M = (InputsFixed[0] ^ 1) + SourceOffset;
8336 InputsFixed[1] = InputsFixed[0] ^ 1;
8339 // Point everything at the fixed inputs.
8340 for (int &M : HalfMask)
8341 if (M == IncomingInputs[0])
8342 M = InputsFixed[0] + SourceOffset;
8343 else if (M == IncomingInputs[1])
8344 M = InputsFixed[1] + SourceOffset;
8346 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8347 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8350 llvm_unreachable("Unhandled input size!");
8353 // Now hoist the DWord down to the right half.
8354 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8355 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8356 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8357 for (int &M : HalfMask)
8358 for (int Input : IncomingInputs)
8360 M = FreeDWord * 2 + Input % 2;
8362 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8363 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8364 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8365 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8367 // Now enact all the shuffles we've computed to move the inputs into their
8369 if (!isNoopShuffleMask(PSHUFLMask))
8370 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8371 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8372 if (!isNoopShuffleMask(PSHUFHMask))
8373 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8374 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8375 if (!isNoopShuffleMask(PSHUFDMask))
8376 V = DAG.getNode(ISD::BITCAST, DL, VT,
8377 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8378 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8379 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8382 // At this point, each half should contain all its inputs, and we can then
8383 // just shuffle them into their final position.
8384 assert(std::count_if(LoMask.begin(), LoMask.end(),
8385 [](int M) { return M >= 4; }) == 0 &&
8386 "Failed to lift all the high half inputs to the low mask!");
8387 assert(std::count_if(HiMask.begin(), HiMask.end(),
8388 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8389 "Failed to lift all the low half inputs to the high mask!");
8391 // Do a half shuffle for the low mask.
8392 if (!isNoopShuffleMask(LoMask))
8393 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8394 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8396 // Do a half shuffle with the high mask after shifting its values down.
8397 for (int &M : HiMask)
8400 if (!isNoopShuffleMask(HiMask))
8401 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8402 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8407 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8408 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8409 SDValue V2, ArrayRef<int> Mask,
8410 SelectionDAG &DAG, bool &V1InUse,
8412 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8418 int Size = Mask.size();
8419 int Scale = 16 / Size;
8420 for (int i = 0; i < 16; ++i) {
8421 if (Mask[i / Scale] == -1) {
8422 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8424 const int ZeroMask = 0x80;
8425 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8427 int V2Idx = Mask[i / Scale] < Size
8429 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8430 if (Zeroable[i / Scale])
8431 V1Idx = V2Idx = ZeroMask;
8432 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8433 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8434 V1InUse |= (ZeroMask != V1Idx);
8435 V2InUse |= (ZeroMask != V2Idx);
8440 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8441 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8442 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8444 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8445 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8446 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8448 // If we need shuffled inputs from both, blend the two.
8450 if (V1InUse && V2InUse)
8451 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8453 V = V1InUse ? V1 : V2;
8455 // Cast the result back to the correct type.
8456 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8459 /// \brief Generic lowering of 8-lane i16 shuffles.
8461 /// This handles both single-input shuffles and combined shuffle/blends with
8462 /// two inputs. The single input shuffles are immediately delegated to
8463 /// a dedicated lowering routine.
8465 /// The blends are lowered in one of three fundamental ways. If there are few
8466 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8467 /// of the input is significantly cheaper when lowered as an interleaving of
8468 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8469 /// halves of the inputs separately (making them have relatively few inputs)
8470 /// and then concatenate them.
8471 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8472 const X86Subtarget *Subtarget,
8473 SelectionDAG &DAG) {
8475 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8476 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8477 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8479 ArrayRef<int> OrigMask = SVOp->getMask();
8480 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8481 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8482 MutableArrayRef<int> Mask(MaskStorage);
8484 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8486 // Whenever we can lower this as a zext, that instruction is strictly faster
8487 // than any alternative.
8488 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8489 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8492 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8494 auto isV2 = [](int M) { return M >= 8; };
8496 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8498 if (NumV2Inputs == 0) {
8499 // Check for being able to broadcast a single element.
8500 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8501 Mask, Subtarget, DAG))
8504 // Try to use shift instructions.
8506 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8509 // Use dedicated unpack instructions for masks that match their pattern.
8510 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8511 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8512 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8513 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8515 // Try to use byte rotation instructions.
8516 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8517 Mask, Subtarget, DAG))
8520 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8524 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8525 "All single-input shuffles should be canonicalized to be V1-input "
8528 // Try to use shift instructions.
8530 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8533 // There are special ways we can lower some single-element blends.
8534 if (NumV2Inputs == 1)
8535 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8536 Mask, Subtarget, DAG))
8539 // We have different paths for blend lowering, but they all must use the
8540 // *exact* same predicate.
8541 bool IsBlendSupported = Subtarget->hasSSE41();
8542 if (IsBlendSupported)
8543 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8547 if (SDValue Masked =
8548 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8551 // Use dedicated unpack instructions for masks that match their pattern.
8552 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8553 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8554 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8555 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8557 // Try to use byte rotation instructions.
8558 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8559 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8562 if (SDValue BitBlend =
8563 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8566 if (SDValue Unpack =
8567 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8570 // If we can't directly blend but can use PSHUFB, that will be better as it
8571 // can both shuffle and set up the inefficient blend.
8572 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8573 bool V1InUse, V2InUse;
8574 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8578 // We can always bit-blend if we have to so the fallback strategy is to
8579 // decompose into single-input permutes and blends.
8580 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8584 /// \brief Check whether a compaction lowering can be done by dropping even
8585 /// elements and compute how many times even elements must be dropped.
8587 /// This handles shuffles which take every Nth element where N is a power of
8588 /// two. Example shuffle masks:
8590 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8591 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8592 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8593 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8594 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8595 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8597 /// Any of these lanes can of course be undef.
8599 /// This routine only supports N <= 3.
8600 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8603 /// \returns N above, or the number of times even elements must be dropped if
8604 /// there is such a number. Otherwise returns zero.
8605 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8606 // Figure out whether we're looping over two inputs or just one.
8607 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8609 // The modulus for the shuffle vector entries is based on whether this is
8610 // a single input or not.
8611 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8612 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8613 "We should only be called with masks with a power-of-2 size!");
8615 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8617 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8618 // and 2^3 simultaneously. This is because we may have ambiguity with
8619 // partially undef inputs.
8620 bool ViableForN[3] = {true, true, true};
8622 for (int i = 0, e = Mask.size(); i < e; ++i) {
8623 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8628 bool IsAnyViable = false;
8629 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8630 if (ViableForN[j]) {
8633 // The shuffle mask must be equal to (i * 2^N) % M.
8634 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8637 ViableForN[j] = false;
8639 // Early exit if we exhaust the possible powers of two.
8644 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8648 // Return 0 as there is no viable power of two.
8652 /// \brief Generic lowering of v16i8 shuffles.
8654 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8655 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8656 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8657 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8659 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8660 const X86Subtarget *Subtarget,
8661 SelectionDAG &DAG) {
8663 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8664 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8665 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8666 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8667 ArrayRef<int> Mask = SVOp->getMask();
8668 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8670 // Try to use shift instructions.
8672 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8675 // Try to use byte rotation instructions.
8676 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8677 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8680 // Try to use a zext lowering.
8681 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8682 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8686 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8688 // For single-input shuffles, there are some nicer lowering tricks we can use.
8689 if (NumV2Elements == 0) {
8690 // Check for being able to broadcast a single element.
8691 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8692 Mask, Subtarget, DAG))
8695 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8696 // Notably, this handles splat and partial-splat shuffles more efficiently.
8697 // However, it only makes sense if the pre-duplication shuffle simplifies
8698 // things significantly. Currently, this means we need to be able to
8699 // express the pre-duplication shuffle as an i16 shuffle.
8701 // FIXME: We should check for other patterns which can be widened into an
8702 // i16 shuffle as well.
8703 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8704 for (int i = 0; i < 16; i += 2)
8705 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8710 auto tryToWidenViaDuplication = [&]() -> SDValue {
8711 if (!canWidenViaDuplication(Mask))
8713 SmallVector<int, 4> LoInputs;
8714 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8715 [](int M) { return M >= 0 && M < 8; });
8716 std::sort(LoInputs.begin(), LoInputs.end());
8717 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8719 SmallVector<int, 4> HiInputs;
8720 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8721 [](int M) { return M >= 8; });
8722 std::sort(HiInputs.begin(), HiInputs.end());
8723 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8726 bool TargetLo = LoInputs.size() >= HiInputs.size();
8727 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8728 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8730 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8731 SmallDenseMap<int, int, 8> LaneMap;
8732 for (int I : InPlaceInputs) {
8733 PreDupI16Shuffle[I/2] = I/2;
8736 int j = TargetLo ? 0 : 4, je = j + 4;
8737 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8738 // Check if j is already a shuffle of this input. This happens when
8739 // there are two adjacent bytes after we move the low one.
8740 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8741 // If we haven't yet mapped the input, search for a slot into which
8743 while (j < je && PreDupI16Shuffle[j] != -1)
8747 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8750 // Map this input with the i16 shuffle.
8751 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8754 // Update the lane map based on the mapping we ended up with.
8755 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8758 ISD::BITCAST, DL, MVT::v16i8,
8759 DAG.getVectorShuffle(MVT::v8i16, DL,
8760 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8761 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8763 // Unpack the bytes to form the i16s that will be shuffled into place.
8764 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8765 MVT::v16i8, V1, V1);
8767 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8768 for (int i = 0; i < 16; ++i)
8769 if (Mask[i] != -1) {
8770 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8771 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8772 if (PostDupI16Shuffle[i / 2] == -1)
8773 PostDupI16Shuffle[i / 2] = MappedMask;
8775 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8776 "Conflicting entrties in the original shuffle!");
8779 ISD::BITCAST, DL, MVT::v16i8,
8780 DAG.getVectorShuffle(MVT::v8i16, DL,
8781 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8782 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8784 if (SDValue V = tryToWidenViaDuplication())
8788 // Use dedicated unpack instructions for masks that match their pattern.
8789 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8790 0, 16, 1, 17, 2, 18, 3, 19,
8792 4, 20, 5, 21, 6, 22, 7, 23}))
8793 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8794 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8795 8, 24, 9, 25, 10, 26, 11, 27,
8797 12, 28, 13, 29, 14, 30, 15, 31}))
8798 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8800 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8801 // with PSHUFB. It is important to do this before we attempt to generate any
8802 // blends but after all of the single-input lowerings. If the single input
8803 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8804 // want to preserve that and we can DAG combine any longer sequences into
8805 // a PSHUFB in the end. But once we start blending from multiple inputs,
8806 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8807 // and there are *very* few patterns that would actually be faster than the
8808 // PSHUFB approach because of its ability to zero lanes.
8810 // FIXME: The only exceptions to the above are blends which are exact
8811 // interleavings with direct instructions supporting them. We currently don't
8812 // handle those well here.
8813 if (Subtarget->hasSSSE3()) {
8814 bool V1InUse = false;
8815 bool V2InUse = false;
8817 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8818 DAG, V1InUse, V2InUse);
8820 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8821 // do so. This avoids using them to handle blends-with-zero which is
8822 // important as a single pshufb is significantly faster for that.
8823 if (V1InUse && V2InUse) {
8824 if (Subtarget->hasSSE41())
8825 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8826 Mask, Subtarget, DAG))
8829 // We can use an unpack to do the blending rather than an or in some
8830 // cases. Even though the or may be (very minorly) more efficient, we
8831 // preference this lowering because there are common cases where part of
8832 // the complexity of the shuffles goes away when we do the final blend as
8834 // FIXME: It might be worth trying to detect if the unpack-feeding
8835 // shuffles will both be pshufb, in which case we shouldn't bother with
8837 if (SDValue Unpack =
8838 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8845 // There are special ways we can lower some single-element blends.
8846 if (NumV2Elements == 1)
8847 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8848 Mask, Subtarget, DAG))
8851 if (SDValue BitBlend =
8852 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8855 // Check whether a compaction lowering can be done. This handles shuffles
8856 // which take every Nth element for some even N. See the helper function for
8859 // We special case these as they can be particularly efficiently handled with
8860 // the PACKUSB instruction on x86 and they show up in common patterns of
8861 // rearranging bytes to truncate wide elements.
8862 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8863 // NumEvenDrops is the power of two stride of the elements. Another way of
8864 // thinking about it is that we need to drop the even elements this many
8865 // times to get the original input.
8866 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8868 // First we need to zero all the dropped bytes.
8869 assert(NumEvenDrops <= 3 &&
8870 "No support for dropping even elements more than 3 times.");
8871 // We use the mask type to pick which bytes are preserved based on how many
8872 // elements are dropped.
8873 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8874 SDValue ByteClearMask =
8875 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8876 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8877 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8879 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8881 // Now pack things back together.
8882 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8883 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8884 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8885 for (int i = 1; i < NumEvenDrops; ++i) {
8886 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8887 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8893 // Handle multi-input cases by blending single-input shuffles.
8894 if (NumV2Elements > 0)
8895 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8898 // The fallback path for single-input shuffles widens this into two v8i16
8899 // vectors with unpacks, shuffles those, and then pulls them back together
8903 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8904 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8905 for (int i = 0; i < 16; ++i)
8907 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8909 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8911 SDValue VLoHalf, VHiHalf;
8912 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8913 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8915 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8916 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8917 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8918 [](int M) { return M >= 0 && M % 2 == 1; })) {
8919 // Use a mask to drop the high bytes.
8920 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8921 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8922 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8924 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8925 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8927 // Squash the masks to point directly into VLoHalf.
8928 for (int &M : LoBlendMask)
8931 for (int &M : HiBlendMask)
8935 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8936 // VHiHalf so that we can blend them as i16s.
8937 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8938 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8939 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8940 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8943 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8944 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8946 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8949 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8951 /// This routine breaks down the specific type of 128-bit shuffle and
8952 /// dispatches to the lowering routines accordingly.
8953 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8954 MVT VT, const X86Subtarget *Subtarget,
8955 SelectionDAG &DAG) {
8956 switch (VT.SimpleTy) {
8958 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8960 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8962 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8964 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8966 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8968 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8971 llvm_unreachable("Unimplemented!");
8975 /// \brief Helper function to test whether a shuffle mask could be
8976 /// simplified by widening the elements being shuffled.
8978 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8979 /// leaves it in an unspecified state.
8981 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8982 /// shuffle masks. The latter have the special property of a '-2' representing
8983 /// a zero-ed lane of a vector.
8984 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8985 SmallVectorImpl<int> &WidenedMask) {
8986 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8987 // If both elements are undef, its trivial.
8988 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8989 WidenedMask.push_back(SM_SentinelUndef);
8993 // Check for an undef mask and a mask value properly aligned to fit with
8994 // a pair of values. If we find such a case, use the non-undef mask's value.
8995 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8996 WidenedMask.push_back(Mask[i + 1] / 2);
8999 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9000 WidenedMask.push_back(Mask[i] / 2);
9004 // When zeroing, we need to spread the zeroing across both lanes to widen.
9005 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9006 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9007 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9008 WidenedMask.push_back(SM_SentinelZero);
9014 // Finally check if the two mask values are adjacent and aligned with
9016 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9017 WidenedMask.push_back(Mask[i] / 2);
9021 // Otherwise we can't safely widen the elements used in this shuffle.
9024 assert(WidenedMask.size() == Mask.size() / 2 &&
9025 "Incorrect size of mask after widening the elements!");
9030 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9032 /// This routine just extracts two subvectors, shuffles them independently, and
9033 /// then concatenates them back together. This should work effectively with all
9034 /// AVX vector shuffle types.
9035 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9036 SDValue V2, ArrayRef<int> Mask,
9037 SelectionDAG &DAG) {
9038 assert(VT.getSizeInBits() >= 256 &&
9039 "Only for 256-bit or wider vector shuffles!");
9040 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9041 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9043 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9044 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9046 int NumElements = VT.getVectorNumElements();
9047 int SplitNumElements = NumElements / 2;
9048 MVT ScalarVT = VT.getScalarType();
9049 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9051 // Rather than splitting build-vectors, just build two narrower build
9052 // vectors. This helps shuffling with splats and zeros.
9053 auto SplitVector = [&](SDValue V) {
9054 while (V.getOpcode() == ISD::BITCAST)
9055 V = V->getOperand(0);
9057 MVT OrigVT = V.getSimpleValueType();
9058 int OrigNumElements = OrigVT.getVectorNumElements();
9059 int OrigSplitNumElements = OrigNumElements / 2;
9060 MVT OrigScalarVT = OrigVT.getScalarType();
9061 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9065 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9067 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9068 DAG.getIntPtrConstant(0, DL));
9069 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9070 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9073 SmallVector<SDValue, 16> LoOps, HiOps;
9074 for (int i = 0; i < OrigSplitNumElements; ++i) {
9075 LoOps.push_back(BV->getOperand(i));
9076 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9078 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9079 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9081 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
9082 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
9085 SDValue LoV1, HiV1, LoV2, HiV2;
9086 std::tie(LoV1, HiV1) = SplitVector(V1);
9087 std::tie(LoV2, HiV2) = SplitVector(V2);
9089 // Now create two 4-way blends of these half-width vectors.
9090 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9091 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9092 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9093 for (int i = 0; i < SplitNumElements; ++i) {
9094 int M = HalfMask[i];
9095 if (M >= NumElements) {
9096 if (M >= NumElements + SplitNumElements)
9100 V2BlendMask.push_back(M - NumElements);
9101 V1BlendMask.push_back(-1);
9102 BlendMask.push_back(SplitNumElements + i);
9103 } else if (M >= 0) {
9104 if (M >= SplitNumElements)
9108 V2BlendMask.push_back(-1);
9109 V1BlendMask.push_back(M);
9110 BlendMask.push_back(i);
9112 V2BlendMask.push_back(-1);
9113 V1BlendMask.push_back(-1);
9114 BlendMask.push_back(-1);
9118 // Because the lowering happens after all combining takes place, we need to
9119 // manually combine these blend masks as much as possible so that we create
9120 // a minimal number of high-level vector shuffle nodes.
9122 // First try just blending the halves of V1 or V2.
9123 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9124 return DAG.getUNDEF(SplitVT);
9125 if (!UseLoV2 && !UseHiV2)
9126 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9127 if (!UseLoV1 && !UseHiV1)
9128 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9130 SDValue V1Blend, V2Blend;
9131 if (UseLoV1 && UseHiV1) {
9133 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9135 // We only use half of V1 so map the usage down into the final blend mask.
9136 V1Blend = UseLoV1 ? LoV1 : HiV1;
9137 for (int i = 0; i < SplitNumElements; ++i)
9138 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9139 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9141 if (UseLoV2 && UseHiV2) {
9143 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9145 // We only use half of V2 so map the usage down into the final blend mask.
9146 V2Blend = UseLoV2 ? LoV2 : HiV2;
9147 for (int i = 0; i < SplitNumElements; ++i)
9148 if (BlendMask[i] >= SplitNumElements)
9149 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9151 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9153 SDValue Lo = HalfBlend(LoMask);
9154 SDValue Hi = HalfBlend(HiMask);
9155 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9158 /// \brief Either split a vector in halves or decompose the shuffles and the
9161 /// This is provided as a good fallback for many lowerings of non-single-input
9162 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9163 /// between splitting the shuffle into 128-bit components and stitching those
9164 /// back together vs. extracting the single-input shuffles and blending those
9166 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9167 SDValue V2, ArrayRef<int> Mask,
9168 SelectionDAG &DAG) {
9169 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9170 "lower single-input shuffles as it "
9171 "could then recurse on itself.");
9172 int Size = Mask.size();
9174 // If this can be modeled as a broadcast of two elements followed by a blend,
9175 // prefer that lowering. This is especially important because broadcasts can
9176 // often fold with memory operands.
9177 auto DoBothBroadcast = [&] {
9178 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9181 if (V2BroadcastIdx == -1)
9182 V2BroadcastIdx = M - Size;
9183 else if (M - Size != V2BroadcastIdx)
9185 } else if (M >= 0) {
9186 if (V1BroadcastIdx == -1)
9188 else if (M != V1BroadcastIdx)
9193 if (DoBothBroadcast())
9194 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9197 // If the inputs all stem from a single 128-bit lane of each input, then we
9198 // split them rather than blending because the split will decompose to
9199 // unusually few instructions.
9200 int LaneCount = VT.getSizeInBits() / 128;
9201 int LaneSize = Size / LaneCount;
9202 SmallBitVector LaneInputs[2];
9203 LaneInputs[0].resize(LaneCount, false);
9204 LaneInputs[1].resize(LaneCount, false);
9205 for (int i = 0; i < Size; ++i)
9207 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9208 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9209 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9211 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9212 // that the decomposed single-input shuffles don't end up here.
9213 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9216 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9217 /// a permutation and blend of those lanes.
9219 /// This essentially blends the out-of-lane inputs to each lane into the lane
9220 /// from a permuted copy of the vector. This lowering strategy results in four
9221 /// instructions in the worst case for a single-input cross lane shuffle which
9222 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9223 /// of. Special cases for each particular shuffle pattern should be handled
9224 /// prior to trying this lowering.
9225 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9226 SDValue V1, SDValue V2,
9228 SelectionDAG &DAG) {
9229 // FIXME: This should probably be generalized for 512-bit vectors as well.
9230 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9231 int LaneSize = Mask.size() / 2;
9233 // If there are only inputs from one 128-bit lane, splitting will in fact be
9234 // less expensive. The flags track whether the given lane contains an element
9235 // that crosses to another lane.
9236 bool LaneCrossing[2] = {false, false};
9237 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9238 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9239 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9240 if (!LaneCrossing[0] || !LaneCrossing[1])
9241 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9243 if (isSingleInputShuffleMask(Mask)) {
9244 SmallVector<int, 32> FlippedBlendMask;
9245 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9246 FlippedBlendMask.push_back(
9247 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9249 : Mask[i] % LaneSize +
9250 (i / LaneSize) * LaneSize + Size));
9252 // Flip the vector, and blend the results which should now be in-lane. The
9253 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9254 // 5 for the high source. The value 3 selects the high half of source 2 and
9255 // the value 2 selects the low half of source 2. We only use source 2 to
9256 // allow folding it into a memory operand.
9257 unsigned PERMMask = 3 | 2 << 4;
9258 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9259 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9260 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9263 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9264 // will be handled by the above logic and a blend of the results, much like
9265 // other patterns in AVX.
9266 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9269 /// \brief Handle lowering 2-lane 128-bit shuffles.
9270 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9271 SDValue V2, ArrayRef<int> Mask,
9272 const X86Subtarget *Subtarget,
9273 SelectionDAG &DAG) {
9274 // TODO: If minimizing size and one of the inputs is a zero vector and the
9275 // the zero vector has only one use, we could use a VPERM2X128 to save the
9276 // instruction bytes needed to explicitly generate the zero vector.
9278 // Blends are faster and handle all the non-lane-crossing cases.
9279 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9283 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9284 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9286 // If either input operand is a zero vector, use VPERM2X128 because its mask
9287 // allows us to replace the zero input with an implicit zero.
9288 if (!IsV1Zero && !IsV2Zero) {
9289 // Check for patterns which can be matched with a single insert of a 128-bit
9291 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9292 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9293 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9294 VT.getVectorNumElements() / 2);
9295 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9296 DAG.getIntPtrConstant(0, DL));
9297 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9298 OnlyUsesV1 ? V1 : V2,
9299 DAG.getIntPtrConstant(0, DL));
9300 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9304 // Otherwise form a 128-bit permutation. After accounting for undefs,
9305 // convert the 64-bit shuffle mask selection values into 128-bit
9306 // selection bits by dividing the indexes by 2 and shifting into positions
9307 // defined by a vperm2*128 instruction's immediate control byte.
9309 // The immediate permute control byte looks like this:
9310 // [1:0] - select 128 bits from sources for low half of destination
9312 // [3] - zero low half of destination
9313 // [5:4] - select 128 bits from sources for high half of destination
9315 // [7] - zero high half of destination
9317 int MaskLO = Mask[0];
9318 if (MaskLO == SM_SentinelUndef)
9319 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9321 int MaskHI = Mask[2];
9322 if (MaskHI == SM_SentinelUndef)
9323 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9325 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9327 // If either input is a zero vector, replace it with an undef input.
9328 // Shuffle mask values < 4 are selecting elements of V1.
9329 // Shuffle mask values >= 4 are selecting elements of V2.
9330 // Adjust each half of the permute mask by clearing the half that was
9331 // selecting the zero vector and setting the zero mask bit.
9333 V1 = DAG.getUNDEF(VT);
9335 PermMask = (PermMask & 0xf0) | 0x08;
9337 PermMask = (PermMask & 0x0f) | 0x80;
9340 V2 = DAG.getUNDEF(VT);
9342 PermMask = (PermMask & 0xf0) | 0x08;
9344 PermMask = (PermMask & 0x0f) | 0x80;
9347 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9348 DAG.getConstant(PermMask, DL, MVT::i8));
9351 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9352 /// shuffling each lane.
9354 /// This will only succeed when the result of fixing the 128-bit lanes results
9355 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9356 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9357 /// the lane crosses early and then use simpler shuffles within each lane.
9359 /// FIXME: It might be worthwhile at some point to support this without
9360 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9361 /// in x86 only floating point has interesting non-repeating shuffles, and even
9362 /// those are still *marginally* more expensive.
9363 static SDValue lowerVectorShuffleByMerging128BitLanes(
9364 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9365 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9366 assert(!isSingleInputShuffleMask(Mask) &&
9367 "This is only useful with multiple inputs.");
9369 int Size = Mask.size();
9370 int LaneSize = 128 / VT.getScalarSizeInBits();
9371 int NumLanes = Size / LaneSize;
9372 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9374 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9375 // check whether the in-128-bit lane shuffles share a repeating pattern.
9376 SmallVector<int, 4> Lanes;
9377 Lanes.resize(NumLanes, -1);
9378 SmallVector<int, 4> InLaneMask;
9379 InLaneMask.resize(LaneSize, -1);
9380 for (int i = 0; i < Size; ++i) {
9384 int j = i / LaneSize;
9387 // First entry we've seen for this lane.
9388 Lanes[j] = Mask[i] / LaneSize;
9389 } else if (Lanes[j] != Mask[i] / LaneSize) {
9390 // This doesn't match the lane selected previously!
9394 // Check that within each lane we have a consistent shuffle mask.
9395 int k = i % LaneSize;
9396 if (InLaneMask[k] < 0) {
9397 InLaneMask[k] = Mask[i] % LaneSize;
9398 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9399 // This doesn't fit a repeating in-lane mask.
9404 // First shuffle the lanes into place.
9405 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9406 VT.getSizeInBits() / 64);
9407 SmallVector<int, 8> LaneMask;
9408 LaneMask.resize(NumLanes * 2, -1);
9409 for (int i = 0; i < NumLanes; ++i)
9410 if (Lanes[i] >= 0) {
9411 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9412 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9415 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9416 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9417 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9419 // Cast it back to the type we actually want.
9420 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9422 // Now do a simple shuffle that isn't lane crossing.
9423 SmallVector<int, 8> NewMask;
9424 NewMask.resize(Size, -1);
9425 for (int i = 0; i < Size; ++i)
9427 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9428 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9429 "Must not introduce lane crosses at this point!");
9431 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9434 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9437 /// This returns true if the elements from a particular input are already in the
9438 /// slot required by the given mask and require no permutation.
9439 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9440 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9441 int Size = Mask.size();
9442 for (int i = 0; i < Size; ++i)
9443 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9449 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9451 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9452 /// isn't available.
9453 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9454 const X86Subtarget *Subtarget,
9455 SelectionDAG &DAG) {
9457 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9458 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9459 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9460 ArrayRef<int> Mask = SVOp->getMask();
9461 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9463 SmallVector<int, 4> WidenedMask;
9464 if (canWidenShuffleElements(Mask, WidenedMask))
9465 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9468 if (isSingleInputShuffleMask(Mask)) {
9469 // Check for being able to broadcast a single element.
9470 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9471 Mask, Subtarget, DAG))
9474 // Use low duplicate instructions for masks that match their pattern.
9475 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9476 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9478 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9479 // Non-half-crossing single input shuffles can be lowerid with an
9480 // interleaved permutation.
9481 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9482 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9483 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9484 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9487 // With AVX2 we have direct support for this permutation.
9488 if (Subtarget->hasAVX2())
9489 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9490 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9492 // Otherwise, fall back.
9493 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9497 // X86 has dedicated unpack instructions that can handle specific blend
9498 // operations: UNPCKH and UNPCKL.
9499 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9500 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9501 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9502 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9503 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9504 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9505 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9506 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9508 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9512 // Check if the blend happens to exactly fit that of SHUFPD.
9513 if ((Mask[0] == -1 || Mask[0] < 2) &&
9514 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9515 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9516 (Mask[3] == -1 || Mask[3] >= 6)) {
9517 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9518 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9519 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9520 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9522 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9523 (Mask[1] == -1 || Mask[1] < 2) &&
9524 (Mask[2] == -1 || Mask[2] >= 6) &&
9525 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9526 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9527 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9528 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9529 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9532 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9533 // shuffle. However, if we have AVX2 and either inputs are already in place,
9534 // we will be able to shuffle even across lanes the other input in a single
9535 // instruction so skip this pattern.
9536 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9537 isShuffleMaskInputInPlace(1, Mask))))
9538 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9539 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9542 // If we have AVX2 then we always want to lower with a blend because an v4 we
9543 // can fully permute the elements.
9544 if (Subtarget->hasAVX2())
9545 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9548 // Otherwise fall back on generic lowering.
9549 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9552 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9554 /// This routine is only called when we have AVX2 and thus a reasonable
9555 /// instruction set for v4i64 shuffling..
9556 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9557 const X86Subtarget *Subtarget,
9558 SelectionDAG &DAG) {
9560 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9561 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9562 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9563 ArrayRef<int> Mask = SVOp->getMask();
9564 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9565 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9567 SmallVector<int, 4> WidenedMask;
9568 if (canWidenShuffleElements(Mask, WidenedMask))
9569 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9572 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9576 // Check for being able to broadcast a single element.
9577 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9578 Mask, Subtarget, DAG))
9581 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9582 // use lower latency instructions that will operate on both 128-bit lanes.
9583 SmallVector<int, 2> RepeatedMask;
9584 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9585 if (isSingleInputShuffleMask(Mask)) {
9586 int PSHUFDMask[] = {-1, -1, -1, -1};
9587 for (int i = 0; i < 2; ++i)
9588 if (RepeatedMask[i] >= 0) {
9589 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9590 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9593 ISD::BITCAST, DL, MVT::v4i64,
9594 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9595 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9596 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9600 // AVX2 provides a direct instruction for permuting a single input across
9602 if (isSingleInputShuffleMask(Mask))
9603 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9604 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9606 // Try to use shift instructions.
9608 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9611 // Use dedicated unpack instructions for masks that match their pattern.
9612 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9613 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9614 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9615 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9616 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9617 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9618 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9619 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9621 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9622 // shuffle. However, if we have AVX2 and either inputs are already in place,
9623 // we will be able to shuffle even across lanes the other input in a single
9624 // instruction so skip this pattern.
9625 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9626 isShuffleMaskInputInPlace(1, Mask))))
9627 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9628 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9631 // Otherwise fall back on generic blend lowering.
9632 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9636 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9638 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9639 /// isn't available.
9640 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9641 const X86Subtarget *Subtarget,
9642 SelectionDAG &DAG) {
9644 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9645 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9646 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9647 ArrayRef<int> Mask = SVOp->getMask();
9648 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9650 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9654 // Check for being able to broadcast a single element.
9655 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9656 Mask, Subtarget, DAG))
9659 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9660 // options to efficiently lower the shuffle.
9661 SmallVector<int, 4> RepeatedMask;
9662 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9663 assert(RepeatedMask.size() == 4 &&
9664 "Repeated masks must be half the mask width!");
9666 // Use even/odd duplicate instructions for masks that match their pattern.
9667 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9668 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9669 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9670 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9672 if (isSingleInputShuffleMask(Mask))
9673 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9674 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9676 // Use dedicated unpack instructions for masks that match their pattern.
9677 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9678 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9679 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9680 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9681 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9682 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9683 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9684 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9686 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9687 // have already handled any direct blends. We also need to squash the
9688 // repeated mask into a simulated v4f32 mask.
9689 for (int i = 0; i < 4; ++i)
9690 if (RepeatedMask[i] >= 8)
9691 RepeatedMask[i] -= 4;
9692 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9695 // If we have a single input shuffle with different shuffle patterns in the
9696 // two 128-bit lanes use the variable mask to VPERMILPS.
9697 if (isSingleInputShuffleMask(Mask)) {
9698 SDValue VPermMask[8];
9699 for (int i = 0; i < 8; ++i)
9700 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9701 : DAG.getConstant(Mask[i], DL, MVT::i32);
9702 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9704 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9705 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9707 if (Subtarget->hasAVX2())
9708 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9709 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9710 DAG.getNode(ISD::BUILD_VECTOR, DL,
9711 MVT::v8i32, VPermMask)),
9714 // Otherwise, fall back.
9715 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9719 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9721 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9722 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9725 // If we have AVX2 then we always want to lower with a blend because at v8 we
9726 // can fully permute the elements.
9727 if (Subtarget->hasAVX2())
9728 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9731 // Otherwise fall back on generic lowering.
9732 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9735 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9737 /// This routine is only called when we have AVX2 and thus a reasonable
9738 /// instruction set for v8i32 shuffling..
9739 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9740 const X86Subtarget *Subtarget,
9741 SelectionDAG &DAG) {
9743 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9744 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9745 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9746 ArrayRef<int> Mask = SVOp->getMask();
9747 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9748 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9750 // Whenever we can lower this as a zext, that instruction is strictly faster
9751 // than any alternative. It also allows us to fold memory operands into the
9752 // shuffle in many cases.
9753 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9754 Mask, Subtarget, DAG))
9757 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9761 // Check for being able to broadcast a single element.
9762 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9763 Mask, Subtarget, DAG))
9766 // If the shuffle mask is repeated in each 128-bit lane we can use more
9767 // efficient instructions that mirror the shuffles across the two 128-bit
9769 SmallVector<int, 4> RepeatedMask;
9770 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9771 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9772 if (isSingleInputShuffleMask(Mask))
9773 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9774 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9776 // Use dedicated unpack instructions for masks that match their pattern.
9777 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9778 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9779 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9780 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9781 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9782 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9783 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9784 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9787 // Try to use shift instructions.
9789 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9792 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9793 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9796 // If the shuffle patterns aren't repeated but it is a single input, directly
9797 // generate a cross-lane VPERMD instruction.
9798 if (isSingleInputShuffleMask(Mask)) {
9799 SDValue VPermMask[8];
9800 for (int i = 0; i < 8; ++i)
9801 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9802 : DAG.getConstant(Mask[i], DL, MVT::i32);
9804 X86ISD::VPERMV, DL, MVT::v8i32,
9805 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9808 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9810 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9811 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9814 // Otherwise fall back on generic blend lowering.
9815 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9819 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9821 /// This routine is only called when we have AVX2 and thus a reasonable
9822 /// instruction set for v16i16 shuffling..
9823 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9824 const X86Subtarget *Subtarget,
9825 SelectionDAG &DAG) {
9827 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9828 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9830 ArrayRef<int> Mask = SVOp->getMask();
9831 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9832 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9834 // Whenever we can lower this as a zext, that instruction is strictly faster
9835 // than any alternative. It also allows us to fold memory operands into the
9836 // shuffle in many cases.
9837 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9838 Mask, Subtarget, DAG))
9841 // Check for being able to broadcast a single element.
9842 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9843 Mask, Subtarget, DAG))
9846 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9850 // Use dedicated unpack instructions for masks that match their pattern.
9851 if (isShuffleEquivalent(V1, V2, Mask,
9852 {// First 128-bit lane:
9853 0, 16, 1, 17, 2, 18, 3, 19,
9854 // Second 128-bit lane:
9855 8, 24, 9, 25, 10, 26, 11, 27}))
9856 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9857 if (isShuffleEquivalent(V1, V2, Mask,
9858 {// First 128-bit lane:
9859 4, 20, 5, 21, 6, 22, 7, 23,
9860 // Second 128-bit lane:
9861 12, 28, 13, 29, 14, 30, 15, 31}))
9862 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9864 // Try to use shift instructions.
9866 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9869 // Try to use byte rotation instructions.
9870 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9871 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9874 if (isSingleInputShuffleMask(Mask)) {
9875 // There are no generalized cross-lane shuffle operations available on i16
9877 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9878 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9881 SmallVector<int, 8> RepeatedMask;
9882 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9883 // As this is a single-input shuffle, the repeated mask should be
9884 // a strictly valid v8i16 mask that we can pass through to the v8i16
9885 // lowering to handle even the v16 case.
9886 return lowerV8I16GeneralSingleInputVectorShuffle(
9887 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9890 SDValue PSHUFBMask[32];
9891 for (int i = 0; i < 16; ++i) {
9892 if (Mask[i] == -1) {
9893 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9897 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9898 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9899 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9900 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9903 ISD::BITCAST, DL, MVT::v16i16,
9905 X86ISD::PSHUFB, DL, MVT::v32i8,
9906 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9907 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9910 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9912 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9913 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9916 // Otherwise fall back on generic lowering.
9917 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9920 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9922 /// This routine is only called when we have AVX2 and thus a reasonable
9923 /// instruction set for v32i8 shuffling..
9924 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9925 const X86Subtarget *Subtarget,
9926 SelectionDAG &DAG) {
9928 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9929 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9930 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9931 ArrayRef<int> Mask = SVOp->getMask();
9932 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9933 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9935 // Whenever we can lower this as a zext, that instruction is strictly faster
9936 // than any alternative. It also allows us to fold memory operands into the
9937 // shuffle in many cases.
9938 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9939 Mask, Subtarget, DAG))
9942 // Check for being able to broadcast a single element.
9943 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9944 Mask, Subtarget, DAG))
9947 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9951 // Use dedicated unpack instructions for masks that match their pattern.
9952 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9954 if (isShuffleEquivalent(
9956 {// First 128-bit lane:
9957 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9958 // Second 128-bit lane:
9959 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9960 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9961 if (isShuffleEquivalent(
9963 {// First 128-bit lane:
9964 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9965 // Second 128-bit lane:
9966 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9967 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9969 // Try to use shift instructions.
9971 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9974 // Try to use byte rotation instructions.
9975 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9976 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9979 if (isSingleInputShuffleMask(Mask)) {
9980 // There are no generalized cross-lane shuffle operations available on i8
9982 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9983 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9986 SDValue PSHUFBMask[32];
9987 for (int i = 0; i < 32; ++i)
9990 ? DAG.getUNDEF(MVT::i8)
9991 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9995 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9996 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9999 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10001 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10002 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10005 // Otherwise fall back on generic lowering.
10006 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10009 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10011 /// This routine either breaks down the specific type of a 256-bit x86 vector
10012 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10013 /// together based on the available instructions.
10014 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10015 MVT VT, const X86Subtarget *Subtarget,
10016 SelectionDAG &DAG) {
10018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10019 ArrayRef<int> Mask = SVOp->getMask();
10021 // If we have a single input to the zero element, insert that into V1 if we
10022 // can do so cheaply.
10023 int NumElts = VT.getVectorNumElements();
10024 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10025 return M >= NumElts;
10028 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10029 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10030 DL, VT, V1, V2, Mask, Subtarget, DAG))
10033 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10034 // check for those subtargets here and avoid much of the subtarget querying in
10035 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10036 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10037 // floating point types there eventually, just immediately cast everything to
10038 // a float and operate entirely in that domain.
10039 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10040 int ElementBits = VT.getScalarSizeInBits();
10041 if (ElementBits < 32)
10042 // No floating point type available, decompose into 128-bit vectors.
10043 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10045 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10046 VT.getVectorNumElements());
10047 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10048 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10049 return DAG.getNode(ISD::BITCAST, DL, VT,
10050 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10053 switch (VT.SimpleTy) {
10055 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10057 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10059 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10061 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10063 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10065 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10068 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10072 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10073 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10074 const X86Subtarget *Subtarget,
10075 SelectionDAG &DAG) {
10077 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10078 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10079 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10080 ArrayRef<int> Mask = SVOp->getMask();
10081 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10083 // X86 has dedicated unpack instructions that can handle specific blend
10084 // operations: UNPCKH and UNPCKL.
10085 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10086 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10087 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10088 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10090 // FIXME: Implement direct support for this type!
10091 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10094 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10095 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10096 const X86Subtarget *Subtarget,
10097 SelectionDAG &DAG) {
10099 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10100 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10101 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10102 ArrayRef<int> Mask = SVOp->getMask();
10103 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10105 // Use dedicated unpack instructions for masks that match their pattern.
10106 if (isShuffleEquivalent(V1, V2, Mask,
10107 {// First 128-bit lane.
10108 0, 16, 1, 17, 4, 20, 5, 21,
10109 // Second 128-bit lane.
10110 8, 24, 9, 25, 12, 28, 13, 29}))
10111 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10112 if (isShuffleEquivalent(V1, V2, Mask,
10113 {// First 128-bit lane.
10114 2, 18, 3, 19, 6, 22, 7, 23,
10115 // Second 128-bit lane.
10116 10, 26, 11, 27, 14, 30, 15, 31}))
10117 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10119 // FIXME: Implement direct support for this type!
10120 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10123 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10124 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10125 const X86Subtarget *Subtarget,
10126 SelectionDAG &DAG) {
10128 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10129 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10131 ArrayRef<int> Mask = SVOp->getMask();
10132 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10134 // X86 has dedicated unpack instructions that can handle specific blend
10135 // operations: UNPCKH and UNPCKL.
10136 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10137 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10138 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10139 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10141 // FIXME: Implement direct support for this type!
10142 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10145 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10146 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10147 const X86Subtarget *Subtarget,
10148 SelectionDAG &DAG) {
10150 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10151 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10152 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10153 ArrayRef<int> Mask = SVOp->getMask();
10154 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10156 // Use dedicated unpack instructions for masks that match their pattern.
10157 if (isShuffleEquivalent(V1, V2, Mask,
10158 {// First 128-bit lane.
10159 0, 16, 1, 17, 4, 20, 5, 21,
10160 // Second 128-bit lane.
10161 8, 24, 9, 25, 12, 28, 13, 29}))
10162 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10163 if (isShuffleEquivalent(V1, V2, Mask,
10164 {// First 128-bit lane.
10165 2, 18, 3, 19, 6, 22, 7, 23,
10166 // Second 128-bit lane.
10167 10, 26, 11, 27, 14, 30, 15, 31}))
10168 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10170 // FIXME: Implement direct support for this type!
10171 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10174 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10175 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10176 const X86Subtarget *Subtarget,
10177 SelectionDAG &DAG) {
10179 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10180 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10181 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10182 ArrayRef<int> Mask = SVOp->getMask();
10183 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10184 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10186 // FIXME: Implement direct support for this type!
10187 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10190 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10191 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10192 const X86Subtarget *Subtarget,
10193 SelectionDAG &DAG) {
10195 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10196 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10198 ArrayRef<int> Mask = SVOp->getMask();
10199 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10200 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10202 // FIXME: Implement direct support for this type!
10203 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10206 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10208 /// This routine either breaks down the specific type of a 512-bit x86 vector
10209 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10210 /// together based on the available instructions.
10211 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10212 MVT VT, const X86Subtarget *Subtarget,
10213 SelectionDAG &DAG) {
10215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10216 ArrayRef<int> Mask = SVOp->getMask();
10217 assert(Subtarget->hasAVX512() &&
10218 "Cannot lower 512-bit vectors w/ basic ISA!");
10220 // Check for being able to broadcast a single element.
10221 if (SDValue Broadcast =
10222 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10225 // Dispatch to each element type for lowering. If we don't have supprot for
10226 // specific element type shuffles at 512 bits, immediately split them and
10227 // lower them. Each lowering routine of a given type is allowed to assume that
10228 // the requisite ISA extensions for that element type are available.
10229 switch (VT.SimpleTy) {
10231 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10233 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10235 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10237 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10239 if (Subtarget->hasBWI())
10240 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10243 if (Subtarget->hasBWI())
10244 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10248 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10251 // Otherwise fall back on splitting.
10252 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10255 /// \brief Top-level lowering for x86 vector shuffles.
10257 /// This handles decomposition, canonicalization, and lowering of all x86
10258 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10259 /// above in helper routines. The canonicalization attempts to widen shuffles
10260 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10261 /// s.t. only one of the two inputs needs to be tested, etc.
10262 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10263 SelectionDAG &DAG) {
10264 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10265 ArrayRef<int> Mask = SVOp->getMask();
10266 SDValue V1 = Op.getOperand(0);
10267 SDValue V2 = Op.getOperand(1);
10268 MVT VT = Op.getSimpleValueType();
10269 int NumElements = VT.getVectorNumElements();
10272 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10274 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10275 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10276 if (V1IsUndef && V2IsUndef)
10277 return DAG.getUNDEF(VT);
10279 // When we create a shuffle node we put the UNDEF node to second operand,
10280 // but in some cases the first operand may be transformed to UNDEF.
10281 // In this case we should just commute the node.
10283 return DAG.getCommutedVectorShuffle(*SVOp);
10285 // Check for non-undef masks pointing at an undef vector and make the masks
10286 // undef as well. This makes it easier to match the shuffle based solely on
10290 if (M >= NumElements) {
10291 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10292 for (int &M : NewMask)
10293 if (M >= NumElements)
10295 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10298 // We actually see shuffles that are entirely re-arrangements of a set of
10299 // zero inputs. This mostly happens while decomposing complex shuffles into
10300 // simple ones. Directly lower these as a buildvector of zeros.
10301 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10302 if (Zeroable.all())
10303 return getZeroVector(VT, Subtarget, DAG, dl);
10305 // Try to collapse shuffles into using a vector type with fewer elements but
10306 // wider element types. We cap this to not form integers or floating point
10307 // elements wider than 64 bits, but it might be interesting to form i128
10308 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10309 SmallVector<int, 16> WidenedMask;
10310 if (VT.getScalarSizeInBits() < 64 &&
10311 canWidenShuffleElements(Mask, WidenedMask)) {
10312 MVT NewEltVT = VT.isFloatingPoint()
10313 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10314 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10315 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10316 // Make sure that the new vector type is legal. For example, v2f64 isn't
10318 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10319 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10320 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10321 return DAG.getNode(ISD::BITCAST, dl, VT,
10322 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10326 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10327 for (int M : SVOp->getMask())
10329 ++NumUndefElements;
10330 else if (M < NumElements)
10335 // Commute the shuffle as needed such that more elements come from V1 than
10336 // V2. This allows us to match the shuffle pattern strictly on how many
10337 // elements come from V1 without handling the symmetric cases.
10338 if (NumV2Elements > NumV1Elements)
10339 return DAG.getCommutedVectorShuffle(*SVOp);
10341 // When the number of V1 and V2 elements are the same, try to minimize the
10342 // number of uses of V2 in the low half of the vector. When that is tied,
10343 // ensure that the sum of indices for V1 is equal to or lower than the sum
10344 // indices for V2. When those are equal, try to ensure that the number of odd
10345 // indices for V1 is lower than the number of odd indices for V2.
10346 if (NumV1Elements == NumV2Elements) {
10347 int LowV1Elements = 0, LowV2Elements = 0;
10348 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10349 if (M >= NumElements)
10353 if (LowV2Elements > LowV1Elements) {
10354 return DAG.getCommutedVectorShuffle(*SVOp);
10355 } else if (LowV2Elements == LowV1Elements) {
10356 int SumV1Indices = 0, SumV2Indices = 0;
10357 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10358 if (SVOp->getMask()[i] >= NumElements)
10360 else if (SVOp->getMask()[i] >= 0)
10362 if (SumV2Indices < SumV1Indices) {
10363 return DAG.getCommutedVectorShuffle(*SVOp);
10364 } else if (SumV2Indices == SumV1Indices) {
10365 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10366 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10367 if (SVOp->getMask()[i] >= NumElements)
10368 NumV2OddIndices += i % 2;
10369 else if (SVOp->getMask()[i] >= 0)
10370 NumV1OddIndices += i % 2;
10371 if (NumV2OddIndices < NumV1OddIndices)
10372 return DAG.getCommutedVectorShuffle(*SVOp);
10377 // For each vector width, delegate to a specialized lowering routine.
10378 if (VT.getSizeInBits() == 128)
10379 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10381 if (VT.getSizeInBits() == 256)
10382 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10384 // Force AVX-512 vectors to be scalarized for now.
10385 // FIXME: Implement AVX-512 support!
10386 if (VT.getSizeInBits() == 512)
10387 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10389 llvm_unreachable("Unimplemented!");
10392 // This function assumes its argument is a BUILD_VECTOR of constants or
10393 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10395 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10396 unsigned &MaskValue) {
10398 unsigned NumElems = BuildVector->getNumOperands();
10399 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10400 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10401 unsigned NumElemsInLane = NumElems / NumLanes;
10403 // Blend for v16i16 should be symetric for the both lanes.
10404 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10405 SDValue EltCond = BuildVector->getOperand(i);
10406 SDValue SndLaneEltCond =
10407 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10409 int Lane1Cond = -1, Lane2Cond = -1;
10410 if (isa<ConstantSDNode>(EltCond))
10411 Lane1Cond = !isZero(EltCond);
10412 if (isa<ConstantSDNode>(SndLaneEltCond))
10413 Lane2Cond = !isZero(SndLaneEltCond);
10415 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10416 // Lane1Cond != 0, means we want the first argument.
10417 // Lane1Cond == 0, means we want the second argument.
10418 // The encoding of this argument is 0 for the first argument, 1
10419 // for the second. Therefore, invert the condition.
10420 MaskValue |= !Lane1Cond << i;
10421 else if (Lane1Cond < 0)
10422 MaskValue |= !Lane2Cond << i;
10429 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10430 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10431 const X86Subtarget *Subtarget,
10432 SelectionDAG &DAG) {
10433 SDValue Cond = Op.getOperand(0);
10434 SDValue LHS = Op.getOperand(1);
10435 SDValue RHS = Op.getOperand(2);
10437 MVT VT = Op.getSimpleValueType();
10439 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10441 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10443 // Only non-legal VSELECTs reach this lowering, convert those into generic
10444 // shuffles and re-use the shuffle lowering path for blends.
10445 SmallVector<int, 32> Mask;
10446 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10447 SDValue CondElt = CondBV->getOperand(i);
10449 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10451 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10454 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10455 // A vselect where all conditions and data are constants can be optimized into
10456 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10457 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10458 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10459 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10462 // Try to lower this to a blend-style vector shuffle. This can handle all
10463 // constant condition cases.
10464 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10467 // Variable blends are only legal from SSE4.1 onward.
10468 if (!Subtarget->hasSSE41())
10471 // Only some types will be legal on some subtargets. If we can emit a legal
10472 // VSELECT-matching blend, return Op, and but if we need to expand, return
10474 switch (Op.getSimpleValueType().SimpleTy) {
10476 // Most of the vector types have blends past SSE4.1.
10480 // The byte blends for AVX vectors were introduced only in AVX2.
10481 if (Subtarget->hasAVX2())
10488 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10489 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10492 // FIXME: We should custom lower this by fixing the condition and using i8
10498 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10499 MVT VT = Op.getSimpleValueType();
10502 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10505 if (VT.getSizeInBits() == 8) {
10506 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10507 Op.getOperand(0), Op.getOperand(1));
10508 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10509 DAG.getValueType(VT));
10510 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10513 if (VT.getSizeInBits() == 16) {
10514 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10515 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10517 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10518 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10519 DAG.getNode(ISD::BITCAST, dl,
10522 Op.getOperand(1)));
10523 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10524 Op.getOperand(0), Op.getOperand(1));
10525 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10526 DAG.getValueType(VT));
10527 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10530 if (VT == MVT::f32) {
10531 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10532 // the result back to FR32 register. It's only worth matching if the
10533 // result has a single use which is a store or a bitcast to i32. And in
10534 // the case of a store, it's not worth it if the index is a constant 0,
10535 // because a MOVSSmr can be used instead, which is smaller and faster.
10536 if (!Op.hasOneUse())
10538 SDNode *User = *Op.getNode()->use_begin();
10539 if ((User->getOpcode() != ISD::STORE ||
10540 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10541 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10542 (User->getOpcode() != ISD::BITCAST ||
10543 User->getValueType(0) != MVT::i32))
10545 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10546 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10549 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10552 if (VT == MVT::i32 || VT == MVT::i64) {
10553 // ExtractPS/pextrq works with constant index.
10554 if (isa<ConstantSDNode>(Op.getOperand(1)))
10560 /// Extract one bit from mask vector, like v16i1 or v8i1.
10561 /// AVX-512 feature.
10563 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10564 SDValue Vec = Op.getOperand(0);
10566 MVT VecVT = Vec.getSimpleValueType();
10567 SDValue Idx = Op.getOperand(1);
10568 MVT EltVT = Op.getSimpleValueType();
10570 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10571 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10572 "Unexpected vector type in ExtractBitFromMaskVector");
10574 // variable index can't be handled in mask registers,
10575 // extend vector to VR512
10576 if (!isa<ConstantSDNode>(Idx)) {
10577 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10578 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10579 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10580 ExtVT.getVectorElementType(), Ext, Idx);
10581 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10584 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10585 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10586 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10587 rc = getRegClassFor(MVT::v16i1);
10588 unsigned MaxSift = rc->getSize()*8 - 1;
10589 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10590 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10591 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10592 DAG.getConstant(MaxSift, dl, MVT::i8));
10593 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10594 DAG.getIntPtrConstant(0, dl));
10598 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10599 SelectionDAG &DAG) const {
10601 SDValue Vec = Op.getOperand(0);
10602 MVT VecVT = Vec.getSimpleValueType();
10603 SDValue Idx = Op.getOperand(1);
10605 if (Op.getSimpleValueType() == MVT::i1)
10606 return ExtractBitFromMaskVector(Op, DAG);
10608 if (!isa<ConstantSDNode>(Idx)) {
10609 if (VecVT.is512BitVector() ||
10610 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10611 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10614 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10615 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10616 MaskEltVT.getSizeInBits());
10618 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10619 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10620 getZeroVector(MaskVT, Subtarget, DAG, dl),
10621 Idx, DAG.getConstant(0, dl, getPointerTy()));
10622 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10623 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10624 Perm, DAG.getConstant(0, dl, getPointerTy()));
10629 // If this is a 256-bit vector result, first extract the 128-bit vector and
10630 // then extract the element from the 128-bit vector.
10631 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10633 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10634 // Get the 128-bit vector.
10635 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10636 MVT EltVT = VecVT.getVectorElementType();
10638 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10640 //if (IdxVal >= NumElems/2)
10641 // IdxVal -= NumElems/2;
10642 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10643 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10644 DAG.getConstant(IdxVal, dl, MVT::i32));
10647 assert(VecVT.is128BitVector() && "Unexpected vector length");
10649 if (Subtarget->hasSSE41()) {
10650 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10655 MVT VT = Op.getSimpleValueType();
10656 // TODO: handle v16i8.
10657 if (VT.getSizeInBits() == 16) {
10658 SDValue Vec = Op.getOperand(0);
10659 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10661 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10662 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10663 DAG.getNode(ISD::BITCAST, dl,
10665 Op.getOperand(1)));
10666 // Transform it so it match pextrw which produces a 32-bit result.
10667 MVT EltVT = MVT::i32;
10668 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10669 Op.getOperand(0), Op.getOperand(1));
10670 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10671 DAG.getValueType(VT));
10672 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10675 if (VT.getSizeInBits() == 32) {
10676 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10680 // SHUFPS the element to the lowest double word, then movss.
10681 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10682 MVT VVT = Op.getOperand(0).getSimpleValueType();
10683 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10684 DAG.getUNDEF(VVT), Mask);
10685 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10686 DAG.getIntPtrConstant(0, dl));
10689 if (VT.getSizeInBits() == 64) {
10690 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10691 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10692 // to match extract_elt for f64.
10693 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10697 // UNPCKHPD the element to the lowest double word, then movsd.
10698 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10699 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10700 int Mask[2] = { 1, -1 };
10701 MVT VVT = Op.getOperand(0).getSimpleValueType();
10702 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10703 DAG.getUNDEF(VVT), Mask);
10704 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10705 DAG.getIntPtrConstant(0, dl));
10711 /// Insert one bit to mask vector, like v16i1 or v8i1.
10712 /// AVX-512 feature.
10714 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10716 SDValue Vec = Op.getOperand(0);
10717 SDValue Elt = Op.getOperand(1);
10718 SDValue Idx = Op.getOperand(2);
10719 MVT VecVT = Vec.getSimpleValueType();
10721 if (!isa<ConstantSDNode>(Idx)) {
10722 // Non constant index. Extend source and destination,
10723 // insert element and then truncate the result.
10724 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10725 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10726 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10727 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10728 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10729 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10732 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10733 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10735 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10736 DAG.getConstant(IdxVal, dl, MVT::i8));
10737 if (Vec.getOpcode() == ISD::UNDEF)
10739 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10742 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10743 SelectionDAG &DAG) const {
10744 MVT VT = Op.getSimpleValueType();
10745 MVT EltVT = VT.getVectorElementType();
10747 if (EltVT == MVT::i1)
10748 return InsertBitToMaskVector(Op, DAG);
10751 SDValue N0 = Op.getOperand(0);
10752 SDValue N1 = Op.getOperand(1);
10753 SDValue N2 = Op.getOperand(2);
10754 if (!isa<ConstantSDNode>(N2))
10756 auto *N2C = cast<ConstantSDNode>(N2);
10757 unsigned IdxVal = N2C->getZExtValue();
10759 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10760 // into that, and then insert the subvector back into the result.
10761 if (VT.is256BitVector() || VT.is512BitVector()) {
10762 // With a 256-bit vector, we can insert into the zero element efficiently
10763 // using a blend if we have AVX or AVX2 and the right data type.
10764 if (VT.is256BitVector() && IdxVal == 0) {
10765 // TODO: It is worthwhile to cast integer to floating point and back
10766 // and incur a domain crossing penalty if that's what we'll end up
10767 // doing anyway after extracting to a 128-bit vector.
10768 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10769 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10770 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10771 N2 = DAG.getIntPtrConstant(1, dl);
10772 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10776 // Get the desired 128-bit vector chunk.
10777 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10779 // Insert the element into the desired chunk.
10780 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10781 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10783 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10784 DAG.getConstant(IdxIn128, dl, MVT::i32));
10786 // Insert the changed part back into the bigger vector
10787 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10789 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10791 if (Subtarget->hasSSE41()) {
10792 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10794 if (VT == MVT::v8i16) {
10795 Opc = X86ISD::PINSRW;
10797 assert(VT == MVT::v16i8);
10798 Opc = X86ISD::PINSRB;
10801 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10803 if (N1.getValueType() != MVT::i32)
10804 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10805 if (N2.getValueType() != MVT::i32)
10806 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10807 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10810 if (EltVT == MVT::f32) {
10811 // Bits [7:6] of the constant are the source select. This will always be
10812 // zero here. The DAG Combiner may combine an extract_elt index into
10813 // these bits. For example (insert (extract, 3), 2) could be matched by
10814 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10815 // Bits [5:4] of the constant are the destination select. This is the
10816 // value of the incoming immediate.
10817 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10818 // combine either bitwise AND or insert of float 0.0 to set these bits.
10820 const Function *F = DAG.getMachineFunction().getFunction();
10821 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10822 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10823 // If this is an insertion of 32-bits into the low 32-bits of
10824 // a vector, we prefer to generate a blend with immediate rather
10825 // than an insertps. Blends are simpler operations in hardware and so
10826 // will always have equal or better performance than insertps.
10827 // But if optimizing for size and there's a load folding opportunity,
10828 // generate insertps because blendps does not have a 32-bit memory
10830 N2 = DAG.getIntPtrConstant(1, dl);
10831 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10832 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10834 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10835 // Create this as a scalar to vector..
10836 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10837 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10840 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10841 // PINSR* works with constant index.
10846 if (EltVT == MVT::i8)
10849 if (EltVT.getSizeInBits() == 16) {
10850 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10851 // as its second argument.
10852 if (N1.getValueType() != MVT::i32)
10853 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10854 if (N2.getValueType() != MVT::i32)
10855 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10856 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10861 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10863 MVT OpVT = Op.getSimpleValueType();
10865 // If this is a 256-bit vector result, first insert into a 128-bit
10866 // vector and then insert into the 256-bit vector.
10867 if (!OpVT.is128BitVector()) {
10868 // Insert into a 128-bit vector.
10869 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10870 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10871 OpVT.getVectorNumElements() / SizeFactor);
10873 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10875 // Insert the 128-bit vector.
10876 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10879 if (OpVT == MVT::v1i64 &&
10880 Op.getOperand(0).getValueType() == MVT::i64)
10881 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10883 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10884 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10885 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10886 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10889 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10890 // a simple subregister reference or explicit instructions to grab
10891 // upper bits of a vector.
10892 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10893 SelectionDAG &DAG) {
10895 SDValue In = Op.getOperand(0);
10896 SDValue Idx = Op.getOperand(1);
10897 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10898 MVT ResVT = Op.getSimpleValueType();
10899 MVT InVT = In.getSimpleValueType();
10901 if (Subtarget->hasFp256()) {
10902 if (ResVT.is128BitVector() &&
10903 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10904 isa<ConstantSDNode>(Idx)) {
10905 return Extract128BitVector(In, IdxVal, DAG, dl);
10907 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10908 isa<ConstantSDNode>(Idx)) {
10909 return Extract256BitVector(In, IdxVal, DAG, dl);
10915 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10916 // simple superregister reference or explicit instructions to insert
10917 // the upper bits of a vector.
10918 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10919 SelectionDAG &DAG) {
10920 if (!Subtarget->hasAVX())
10924 SDValue Vec = Op.getOperand(0);
10925 SDValue SubVec = Op.getOperand(1);
10926 SDValue Idx = Op.getOperand(2);
10928 if (!isa<ConstantSDNode>(Idx))
10931 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10932 MVT OpVT = Op.getSimpleValueType();
10933 MVT SubVecVT = SubVec.getSimpleValueType();
10935 // Fold two 16-byte subvector loads into one 32-byte load:
10936 // (insert_subvector (insert_subvector undef, (load addr), 0),
10937 // (load addr + 16), Elts/2)
10939 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10940 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10941 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10942 !Subtarget->isUnalignedMem32Slow()) {
10943 SDValue SubVec2 = Vec.getOperand(1);
10944 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10945 if (Idx2->getZExtValue() == 0) {
10946 SDValue Ops[] = { SubVec2, SubVec };
10947 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10954 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10955 SubVecVT.is128BitVector())
10956 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10958 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10959 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10961 if (OpVT.getVectorElementType() == MVT::i1) {
10962 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10964 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10965 SDValue Undef = DAG.getUNDEF(OpVT);
10966 unsigned NumElems = OpVT.getVectorNumElements();
10967 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10969 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10970 // Zero upper bits of the Vec
10971 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10972 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10974 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10976 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10977 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10980 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10982 // Zero upper bits of the Vec2
10983 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10984 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10985 // Zero lower bits of the Vec
10986 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10987 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10988 // Merge them together
10989 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10995 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10996 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10997 // one of the above mentioned nodes. It has to be wrapped because otherwise
10998 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10999 // be used to form addressing mode. These wrapped nodes will be selected
11002 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11003 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11005 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11006 // global base reg.
11007 unsigned char OpFlag = 0;
11008 unsigned WrapperKind = X86ISD::Wrapper;
11009 CodeModel::Model M = DAG.getTarget().getCodeModel();
11011 if (Subtarget->isPICStyleRIPRel() &&
11012 (M == CodeModel::Small || M == CodeModel::Kernel))
11013 WrapperKind = X86ISD::WrapperRIP;
11014 else if (Subtarget->isPICStyleGOT())
11015 OpFlag = X86II::MO_GOTOFF;
11016 else if (Subtarget->isPICStyleStubPIC())
11017 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11019 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11020 CP->getAlignment(),
11021 CP->getOffset(), OpFlag);
11023 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11024 // With PIC, the address is actually $g + Offset.
11026 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11027 DAG.getNode(X86ISD::GlobalBaseReg,
11028 SDLoc(), getPointerTy()),
11035 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11036 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11038 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11039 // global base reg.
11040 unsigned char OpFlag = 0;
11041 unsigned WrapperKind = X86ISD::Wrapper;
11042 CodeModel::Model M = DAG.getTarget().getCodeModel();
11044 if (Subtarget->isPICStyleRIPRel() &&
11045 (M == CodeModel::Small || M == CodeModel::Kernel))
11046 WrapperKind = X86ISD::WrapperRIP;
11047 else if (Subtarget->isPICStyleGOT())
11048 OpFlag = X86II::MO_GOTOFF;
11049 else if (Subtarget->isPICStyleStubPIC())
11050 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11052 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11055 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11057 // With PIC, the address is actually $g + Offset.
11059 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11060 DAG.getNode(X86ISD::GlobalBaseReg,
11061 SDLoc(), getPointerTy()),
11068 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11069 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11071 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11072 // global base reg.
11073 unsigned char OpFlag = 0;
11074 unsigned WrapperKind = X86ISD::Wrapper;
11075 CodeModel::Model M = DAG.getTarget().getCodeModel();
11077 if (Subtarget->isPICStyleRIPRel() &&
11078 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11079 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11080 OpFlag = X86II::MO_GOTPCREL;
11081 WrapperKind = X86ISD::WrapperRIP;
11082 } else if (Subtarget->isPICStyleGOT()) {
11083 OpFlag = X86II::MO_GOT;
11084 } else if (Subtarget->isPICStyleStubPIC()) {
11085 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11086 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11087 OpFlag = X86II::MO_DARWIN_NONLAZY;
11090 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11093 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11095 // With PIC, the address is actually $g + Offset.
11096 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11097 !Subtarget->is64Bit()) {
11098 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11099 DAG.getNode(X86ISD::GlobalBaseReg,
11100 SDLoc(), getPointerTy()),
11104 // For symbols that require a load from a stub to get the address, emit the
11106 if (isGlobalStubReference(OpFlag))
11107 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11108 MachinePointerInfo::getGOT(), false, false, false, 0);
11114 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11115 // Create the TargetBlockAddressAddress node.
11116 unsigned char OpFlags =
11117 Subtarget->ClassifyBlockAddressReference();
11118 CodeModel::Model M = DAG.getTarget().getCodeModel();
11119 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11120 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11122 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11125 if (Subtarget->isPICStyleRIPRel() &&
11126 (M == CodeModel::Small || M == CodeModel::Kernel))
11127 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11129 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11131 // With PIC, the address is actually $g + Offset.
11132 if (isGlobalRelativeToPICBase(OpFlags)) {
11133 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11134 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11142 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11143 int64_t Offset, SelectionDAG &DAG) const {
11144 // Create the TargetGlobalAddress node, folding in the constant
11145 // offset if it is legal.
11146 unsigned char OpFlags =
11147 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11148 CodeModel::Model M = DAG.getTarget().getCodeModel();
11150 if (OpFlags == X86II::MO_NO_FLAG &&
11151 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11152 // A direct static reference to a global.
11153 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11156 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11159 if (Subtarget->isPICStyleRIPRel() &&
11160 (M == CodeModel::Small || M == CodeModel::Kernel))
11161 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11163 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11165 // With PIC, the address is actually $g + Offset.
11166 if (isGlobalRelativeToPICBase(OpFlags)) {
11167 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11168 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11172 // For globals that require a load from a stub to get the address, emit the
11174 if (isGlobalStubReference(OpFlags))
11175 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11176 MachinePointerInfo::getGOT(), false, false, false, 0);
11178 // If there was a non-zero offset that we didn't fold, create an explicit
11179 // addition for it.
11181 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11182 DAG.getConstant(Offset, dl, getPointerTy()));
11188 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11189 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11190 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11191 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11195 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11196 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11197 unsigned char OperandFlags, bool LocalDynamic = false) {
11198 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11199 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11201 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11202 GA->getValueType(0),
11206 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11210 SDValue Ops[] = { Chain, TGA, *InFlag };
11211 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11213 SDValue Ops[] = { Chain, TGA };
11214 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11217 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11218 MFI->setAdjustsStack(true);
11219 MFI->setHasCalls(true);
11221 SDValue Flag = Chain.getValue(1);
11222 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11225 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11227 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11230 SDLoc dl(GA); // ? function entry point might be better
11231 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11232 DAG.getNode(X86ISD::GlobalBaseReg,
11233 SDLoc(), PtrVT), InFlag);
11234 InFlag = Chain.getValue(1);
11236 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11239 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11241 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11243 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11244 X86::RAX, X86II::MO_TLSGD);
11247 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11253 // Get the start address of the TLS block for this module.
11254 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11255 .getInfo<X86MachineFunctionInfo>();
11256 MFI->incNumLocalDynamicTLSAccesses();
11260 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11261 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11264 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11265 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11266 InFlag = Chain.getValue(1);
11267 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11268 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11271 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11275 unsigned char OperandFlags = X86II::MO_DTPOFF;
11276 unsigned WrapperKind = X86ISD::Wrapper;
11277 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11278 GA->getValueType(0),
11279 GA->getOffset(), OperandFlags);
11280 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11282 // Add x@dtpoff with the base.
11283 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11286 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11287 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11288 const EVT PtrVT, TLSModel::Model model,
11289 bool is64Bit, bool isPIC) {
11292 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11293 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11294 is64Bit ? 257 : 256));
11296 SDValue ThreadPointer =
11297 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11298 MachinePointerInfo(Ptr), false, false, false, 0);
11300 unsigned char OperandFlags = 0;
11301 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11303 unsigned WrapperKind = X86ISD::Wrapper;
11304 if (model == TLSModel::LocalExec) {
11305 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11306 } else if (model == TLSModel::InitialExec) {
11308 OperandFlags = X86II::MO_GOTTPOFF;
11309 WrapperKind = X86ISD::WrapperRIP;
11311 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11314 llvm_unreachable("Unexpected model");
11317 // emit "addl x@ntpoff,%eax" (local exec)
11318 // or "addl x@indntpoff,%eax" (initial exec)
11319 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11321 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11322 GA->getOffset(), OperandFlags);
11323 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11325 if (model == TLSModel::InitialExec) {
11326 if (isPIC && !is64Bit) {
11327 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11328 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11332 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11333 MachinePointerInfo::getGOT(), false, false, false, 0);
11336 // The address of the thread local variable is the add of the thread
11337 // pointer with the offset of the variable.
11338 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11342 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11344 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11345 const GlobalValue *GV = GA->getGlobal();
11347 if (Subtarget->isTargetELF()) {
11348 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11350 case TLSModel::GeneralDynamic:
11351 if (Subtarget->is64Bit())
11352 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11353 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11354 case TLSModel::LocalDynamic:
11355 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11356 Subtarget->is64Bit());
11357 case TLSModel::InitialExec:
11358 case TLSModel::LocalExec:
11359 return LowerToTLSExecModel(
11360 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11361 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11363 llvm_unreachable("Unknown TLS model.");
11366 if (Subtarget->isTargetDarwin()) {
11367 // Darwin only has one model of TLS. Lower to that.
11368 unsigned char OpFlag = 0;
11369 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11370 X86ISD::WrapperRIP : X86ISD::Wrapper;
11372 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11373 // global base reg.
11374 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11375 !Subtarget->is64Bit();
11377 OpFlag = X86II::MO_TLVP_PIC_BASE;
11379 OpFlag = X86II::MO_TLVP;
11381 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11382 GA->getValueType(0),
11383 GA->getOffset(), OpFlag);
11384 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11386 // With PIC32, the address is actually $g + Offset.
11388 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11389 DAG.getNode(X86ISD::GlobalBaseReg,
11390 SDLoc(), getPointerTy()),
11393 // Lowering the machine isd will make sure everything is in the right
11395 SDValue Chain = DAG.getEntryNode();
11396 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11397 SDValue Args[] = { Chain, Offset };
11398 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11400 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11401 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11402 MFI->setAdjustsStack(true);
11404 // And our return value (tls address) is in the standard call return value
11406 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11407 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11408 Chain.getValue(1));
11411 if (Subtarget->isTargetKnownWindowsMSVC() ||
11412 Subtarget->isTargetWindowsGNU()) {
11413 // Just use the implicit TLS architecture
11414 // Need to generate someting similar to:
11415 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11417 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11418 // mov rcx, qword [rdx+rcx*8]
11419 // mov eax, .tls$:tlsvar
11420 // [rax+rcx] contains the address
11421 // Windows 64bit: gs:0x58
11422 // Windows 32bit: fs:__tls_array
11425 SDValue Chain = DAG.getEntryNode();
11427 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11428 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11429 // use its literal value of 0x2C.
11430 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11431 ? Type::getInt8PtrTy(*DAG.getContext(),
11433 : Type::getInt32PtrTy(*DAG.getContext(),
11437 Subtarget->is64Bit()
11438 ? DAG.getIntPtrConstant(0x58, dl)
11439 : (Subtarget->isTargetWindowsGNU()
11440 ? DAG.getIntPtrConstant(0x2C, dl)
11441 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11443 SDValue ThreadPointer =
11444 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11445 MachinePointerInfo(Ptr), false, false, false, 0);
11448 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11449 res = ThreadPointer;
11451 // Load the _tls_index variable
11452 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11453 if (Subtarget->is64Bit())
11454 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11455 MachinePointerInfo(), MVT::i32, false, false,
11458 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11459 false, false, false, 0);
11461 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11463 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11465 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11468 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11469 false, false, false, 0);
11471 // Get the offset of start of .tls section
11472 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11473 GA->getValueType(0),
11474 GA->getOffset(), X86II::MO_SECREL);
11475 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11477 // The address of the thread local variable is the add of the thread
11478 // pointer with the offset of the variable.
11479 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11482 llvm_unreachable("TLS not implemented for this target.");
11485 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11486 /// and take a 2 x i32 value to shift plus a shift amount.
11487 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11488 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11489 MVT VT = Op.getSimpleValueType();
11490 unsigned VTBits = VT.getSizeInBits();
11492 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11493 SDValue ShOpLo = Op.getOperand(0);
11494 SDValue ShOpHi = Op.getOperand(1);
11495 SDValue ShAmt = Op.getOperand(2);
11496 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11497 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11499 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11500 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11501 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11502 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11503 : DAG.getConstant(0, dl, VT);
11505 SDValue Tmp2, Tmp3;
11506 if (Op.getOpcode() == ISD::SHL_PARTS) {
11507 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11508 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11510 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11511 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11514 // If the shift amount is larger or equal than the width of a part we can't
11515 // rely on the results of shld/shrd. Insert a test and select the appropriate
11516 // values for large shift amounts.
11517 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11518 DAG.getConstant(VTBits, dl, MVT::i8));
11519 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11520 AndNode, DAG.getConstant(0, dl, MVT::i8));
11523 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11524 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11525 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11527 if (Op.getOpcode() == ISD::SHL_PARTS) {
11528 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11529 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11531 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11532 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11535 SDValue Ops[2] = { Lo, Hi };
11536 return DAG.getMergeValues(Ops, dl);
11539 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11540 SelectionDAG &DAG) const {
11541 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11544 if (SrcVT.isVector()) {
11545 if (SrcVT.getVectorElementType() == MVT::i1) {
11546 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11547 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11548 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11549 Op.getOperand(0)));
11554 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11555 "Unknown SINT_TO_FP to lower!");
11557 // These are really Legal; return the operand so the caller accepts it as
11559 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11561 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11562 Subtarget->is64Bit()) {
11566 unsigned Size = SrcVT.getSizeInBits()/8;
11567 MachineFunction &MF = DAG.getMachineFunction();
11568 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11570 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11572 MachinePointerInfo::getFixedStack(SSFI),
11574 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11577 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11579 SelectionDAG &DAG) const {
11583 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11585 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11587 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11589 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11591 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11592 MachineMemOperand *MMO;
11594 int SSFI = FI->getIndex();
11596 DAG.getMachineFunction()
11597 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11598 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11600 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11601 StackSlot = StackSlot.getOperand(1);
11603 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11604 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11606 Tys, Ops, SrcVT, MMO);
11609 Chain = Result.getValue(1);
11610 SDValue InFlag = Result.getValue(2);
11612 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11613 // shouldn't be necessary except that RFP cannot be live across
11614 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11615 MachineFunction &MF = DAG.getMachineFunction();
11616 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11617 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11618 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11619 Tys = DAG.getVTList(MVT::Other);
11621 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11623 MachineMemOperand *MMO =
11624 DAG.getMachineFunction()
11625 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11626 MachineMemOperand::MOStore, SSFISize, SSFISize);
11628 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11629 Ops, Op.getValueType(), MMO);
11630 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11631 MachinePointerInfo::getFixedStack(SSFI),
11632 false, false, false, 0);
11638 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11639 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11640 SelectionDAG &DAG) const {
11641 // This algorithm is not obvious. Here it is what we're trying to output:
11644 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11645 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11647 haddpd %xmm0, %xmm0
11649 pshufd $0x4e, %xmm0, %xmm1
11655 LLVMContext *Context = DAG.getContext();
11657 // Build some magic constants.
11658 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11659 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11660 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11662 SmallVector<Constant*,2> CV1;
11664 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11665 APInt(64, 0x4330000000000000ULL))));
11667 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11668 APInt(64, 0x4530000000000000ULL))));
11669 Constant *C1 = ConstantVector::get(CV1);
11670 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11672 // Load the 64-bit value into an XMM register.
11673 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11675 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11676 MachinePointerInfo::getConstantPool(),
11677 false, false, false, 16);
11678 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11679 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11682 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11683 MachinePointerInfo::getConstantPool(),
11684 false, false, false, 16);
11685 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11686 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11689 if (Subtarget->hasSSE3()) {
11690 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11691 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11693 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11694 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11696 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11697 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11701 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11702 DAG.getIntPtrConstant(0, dl));
11705 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11706 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11707 SelectionDAG &DAG) const {
11709 // FP constant to bias correct the final result.
11710 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11713 // Load the 32-bit value into an XMM register.
11714 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11717 // Zero out the upper parts of the register.
11718 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11720 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11721 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11722 DAG.getIntPtrConstant(0, dl));
11724 // Or the load with the bias.
11725 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11726 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11727 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11728 MVT::v2f64, Load)),
11729 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11730 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11731 MVT::v2f64, Bias)));
11732 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11733 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11734 DAG.getIntPtrConstant(0, dl));
11736 // Subtract the bias.
11737 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11739 // Handle final rounding.
11740 EVT DestVT = Op.getValueType();
11742 if (DestVT.bitsLT(MVT::f64))
11743 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11744 DAG.getIntPtrConstant(0, dl));
11745 if (DestVT.bitsGT(MVT::f64))
11746 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11748 // Handle final rounding.
11752 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11753 const X86Subtarget &Subtarget) {
11754 // The algorithm is the following:
11755 // #ifdef __SSE4_1__
11756 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11757 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11758 // (uint4) 0x53000000, 0xaa);
11760 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11761 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11763 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11764 // return (float4) lo + fhi;
11767 SDValue V = Op->getOperand(0);
11768 EVT VecIntVT = V.getValueType();
11769 bool Is128 = VecIntVT == MVT::v4i32;
11770 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11771 // If we convert to something else than the supported type, e.g., to v4f64,
11773 if (VecFloatVT != Op->getValueType(0))
11776 unsigned NumElts = VecIntVT.getVectorNumElements();
11777 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11778 "Unsupported custom type");
11779 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11781 // In the #idef/#else code, we have in common:
11782 // - The vector of constants:
11788 // Create the splat vector for 0x4b000000.
11789 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11790 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11791 CstLow, CstLow, CstLow, CstLow};
11792 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11793 makeArrayRef(&CstLowArray[0], NumElts));
11794 // Create the splat vector for 0x53000000.
11795 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11796 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11797 CstHigh, CstHigh, CstHigh, CstHigh};
11798 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11799 makeArrayRef(&CstHighArray[0], NumElts));
11801 // Create the right shift.
11802 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11803 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11804 CstShift, CstShift, CstShift, CstShift};
11805 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11806 makeArrayRef(&CstShiftArray[0], NumElts));
11807 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11810 if (Subtarget.hasSSE41()) {
11811 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11812 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11813 SDValue VecCstLowBitcast =
11814 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11815 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11816 // Low will be bitcasted right away, so do not bother bitcasting back to its
11818 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11819 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11820 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11821 // (uint4) 0x53000000, 0xaa);
11822 SDValue VecCstHighBitcast =
11823 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11824 SDValue VecShiftBitcast =
11825 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11826 // High will be bitcasted right away, so do not bother bitcasting back to
11827 // its original type.
11828 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11829 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11831 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11832 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11833 CstMask, CstMask, CstMask);
11834 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11835 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11836 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11838 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11839 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11842 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11843 SDValue CstFAdd = DAG.getConstantFP(
11844 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11845 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11846 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11847 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11848 makeArrayRef(&CstFAddArray[0], NumElts));
11850 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11851 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11853 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11854 // return (float4) lo + fhi;
11855 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11856 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11859 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11860 SelectionDAG &DAG) const {
11861 SDValue N0 = Op.getOperand(0);
11862 MVT SVT = N0.getSimpleValueType();
11865 switch (SVT.SimpleTy) {
11867 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11872 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11873 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11874 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11878 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11881 if (Subtarget->hasAVX512())
11882 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11883 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11885 llvm_unreachable(nullptr);
11888 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11889 SelectionDAG &DAG) const {
11890 SDValue N0 = Op.getOperand(0);
11893 if (Op.getValueType().isVector())
11894 return lowerUINT_TO_FP_vec(Op, DAG);
11896 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11897 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11898 // the optimization here.
11899 if (DAG.SignBitIsZero(N0))
11900 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11902 MVT SrcVT = N0.getSimpleValueType();
11903 MVT DstVT = Op.getSimpleValueType();
11904 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11905 return LowerUINT_TO_FP_i64(Op, DAG);
11906 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11907 return LowerUINT_TO_FP_i32(Op, DAG);
11908 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11911 // Make a 64-bit buffer, and use it to build an FILD.
11912 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11913 if (SrcVT == MVT::i32) {
11914 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11915 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11916 getPointerTy(), StackSlot, WordOff);
11917 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11918 StackSlot, MachinePointerInfo(),
11920 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11921 OffsetSlot, MachinePointerInfo(),
11923 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11927 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11928 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11929 StackSlot, MachinePointerInfo(),
11931 // For i64 source, we need to add the appropriate power of 2 if the input
11932 // was negative. This is the same as the optimization in
11933 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11934 // we must be careful to do the computation in x87 extended precision, not
11935 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11936 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11937 MachineMemOperand *MMO =
11938 DAG.getMachineFunction()
11939 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11940 MachineMemOperand::MOLoad, 8, 8);
11942 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11943 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11944 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11947 APInt FF(32, 0x5F800000ULL);
11949 // Check whether the sign bit is set.
11950 SDValue SignSet = DAG.getSetCC(dl,
11951 getSetCCResultType(*DAG.getContext(), MVT::i64),
11953 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11955 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11956 SDValue FudgePtr = DAG.getConstantPool(
11957 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11960 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11961 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11962 SDValue Four = DAG.getIntPtrConstant(4, dl);
11963 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11965 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11967 // Load the value out, extending it from f32 to f80.
11968 // FIXME: Avoid the extend by constructing the right constant pool?
11969 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11970 FudgePtr, MachinePointerInfo::getConstantPool(),
11971 MVT::f32, false, false, false, 4);
11972 // Extend everything to 80 bits to force it to be done on x87.
11973 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11974 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11975 DAG.getIntPtrConstant(0, dl));
11978 std::pair<SDValue,SDValue>
11979 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11980 bool IsSigned, bool IsReplace) const {
11983 EVT DstTy = Op.getValueType();
11985 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11986 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11990 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11991 DstTy.getSimpleVT() >= MVT::i16 &&
11992 "Unknown FP_TO_INT to lower!");
11994 // These are really Legal.
11995 if (DstTy == MVT::i32 &&
11996 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11997 return std::make_pair(SDValue(), SDValue());
11998 if (Subtarget->is64Bit() &&
11999 DstTy == MVT::i64 &&
12000 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12001 return std::make_pair(SDValue(), SDValue());
12003 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12004 // stack slot, or into the FTOL runtime function.
12005 MachineFunction &MF = DAG.getMachineFunction();
12006 unsigned MemSize = DstTy.getSizeInBits()/8;
12007 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12008 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12011 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12012 Opc = X86ISD::WIN_FTOL;
12014 switch (DstTy.getSimpleVT().SimpleTy) {
12015 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12016 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12017 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12018 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12021 SDValue Chain = DAG.getEntryNode();
12022 SDValue Value = Op.getOperand(0);
12023 EVT TheVT = Op.getOperand(0).getValueType();
12024 // FIXME This causes a redundant load/store if the SSE-class value is already
12025 // in memory, such as if it is on the callstack.
12026 if (isScalarFPTypeInSSEReg(TheVT)) {
12027 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12028 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12029 MachinePointerInfo::getFixedStack(SSFI),
12031 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12033 Chain, StackSlot, DAG.getValueType(TheVT)
12036 MachineMemOperand *MMO =
12037 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12038 MachineMemOperand::MOLoad, MemSize, MemSize);
12039 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12040 Chain = Value.getValue(1);
12041 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12042 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12045 MachineMemOperand *MMO =
12046 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12047 MachineMemOperand::MOStore, MemSize, MemSize);
12049 if (Opc != X86ISD::WIN_FTOL) {
12050 // Build the FP_TO_INT*_IN_MEM
12051 SDValue Ops[] = { Chain, Value, StackSlot };
12052 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12054 return std::make_pair(FIST, StackSlot);
12056 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12057 DAG.getVTList(MVT::Other, MVT::Glue),
12059 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12060 MVT::i32, ftol.getValue(1));
12061 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12062 MVT::i32, eax.getValue(2));
12063 SDValue Ops[] = { eax, edx };
12064 SDValue pair = IsReplace
12065 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12066 : DAG.getMergeValues(Ops, DL);
12067 return std::make_pair(pair, SDValue());
12071 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12072 const X86Subtarget *Subtarget) {
12073 MVT VT = Op->getSimpleValueType(0);
12074 SDValue In = Op->getOperand(0);
12075 MVT InVT = In.getSimpleValueType();
12078 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12079 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12081 // Optimize vectors in AVX mode:
12084 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12085 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12086 // Concat upper and lower parts.
12089 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12090 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12091 // Concat upper and lower parts.
12094 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12095 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12096 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12099 if (Subtarget->hasInt256())
12100 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12102 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12103 SDValue Undef = DAG.getUNDEF(InVT);
12104 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12105 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12106 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12108 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12109 VT.getVectorNumElements()/2);
12111 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12112 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12114 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12117 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12118 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12119 MVT VT = Op->getSimpleValueType(0);
12120 SDValue In = Op->getOperand(0);
12121 MVT InVT = In.getSimpleValueType();
12123 unsigned int NumElts = VT.getVectorNumElements();
12124 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12127 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12128 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12130 assert(InVT.getVectorElementType() == MVT::i1);
12131 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12133 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12135 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12137 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12138 if (VT.is512BitVector())
12140 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12143 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12144 SelectionDAG &DAG) {
12145 if (Subtarget->hasFp256()) {
12146 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12154 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12155 SelectionDAG &DAG) {
12157 MVT VT = Op.getSimpleValueType();
12158 SDValue In = Op.getOperand(0);
12159 MVT SVT = In.getSimpleValueType();
12161 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12162 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12164 if (Subtarget->hasFp256()) {
12165 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12170 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12171 VT.getVectorNumElements() != SVT.getVectorNumElements());
12175 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12177 MVT VT = Op.getSimpleValueType();
12178 SDValue In = Op.getOperand(0);
12179 MVT InVT = In.getSimpleValueType();
12181 if (VT == MVT::i1) {
12182 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12183 "Invalid scalar TRUNCATE operation");
12184 if (InVT.getSizeInBits() >= 32)
12186 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12187 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12189 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12190 "Invalid TRUNCATE operation");
12192 // move vector to mask - truncate solution for SKX
12193 if (VT.getVectorElementType() == MVT::i1) {
12194 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12195 Subtarget->hasBWI())
12196 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12197 if ((InVT.is256BitVector() || InVT.is128BitVector())
12198 && InVT.getScalarSizeInBits() <= 16 &&
12199 Subtarget->hasBWI() && Subtarget->hasVLX())
12200 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12201 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12202 Subtarget->hasDQI())
12203 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12204 if ((InVT.is256BitVector() || InVT.is128BitVector())
12205 && InVT.getScalarSizeInBits() >= 32 &&
12206 Subtarget->hasDQI() && Subtarget->hasVLX())
12207 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12209 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12210 if (VT.getVectorElementType().getSizeInBits() >=8)
12211 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12213 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12214 unsigned NumElts = InVT.getVectorNumElements();
12215 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12216 if (InVT.getSizeInBits() < 512) {
12217 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12218 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12223 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12224 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12225 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12228 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12229 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12230 if (Subtarget->hasInt256()) {
12231 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12232 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12233 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12235 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12236 DAG.getIntPtrConstant(0, DL));
12239 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12240 DAG.getIntPtrConstant(0, DL));
12241 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12242 DAG.getIntPtrConstant(2, DL));
12243 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12244 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12245 static const int ShufMask[] = {0, 2, 4, 6};
12246 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12249 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12250 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12251 if (Subtarget->hasInt256()) {
12252 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12254 SmallVector<SDValue,32> pshufbMask;
12255 for (unsigned i = 0; i < 2; ++i) {
12256 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12257 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12258 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12259 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12260 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12261 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12262 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12263 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12264 for (unsigned j = 0; j < 8; ++j)
12265 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12267 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12268 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12269 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12271 static const int ShufMask[] = {0, 2, -1, -1};
12272 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12274 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12275 DAG.getIntPtrConstant(0, DL));
12276 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12279 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12280 DAG.getIntPtrConstant(0, DL));
12282 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12283 DAG.getIntPtrConstant(4, DL));
12285 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12286 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12288 // The PSHUFB mask:
12289 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12290 -1, -1, -1, -1, -1, -1, -1, -1};
12292 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12293 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12294 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12296 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12297 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12299 // The MOVLHPS Mask:
12300 static const int ShufMask2[] = {0, 1, 4, 5};
12301 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12302 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12305 // Handle truncation of V256 to V128 using shuffles.
12306 if (!VT.is128BitVector() || !InVT.is256BitVector())
12309 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12311 unsigned NumElems = VT.getVectorNumElements();
12312 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12314 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12315 // Prepare truncation shuffle mask
12316 for (unsigned i = 0; i != NumElems; ++i)
12317 MaskVec[i] = i * 2;
12318 SDValue V = DAG.getVectorShuffle(NVT, DL,
12319 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12320 DAG.getUNDEF(NVT), &MaskVec[0]);
12321 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12322 DAG.getIntPtrConstant(0, DL));
12325 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12326 SelectionDAG &DAG) const {
12327 assert(!Op.getSimpleValueType().isVector());
12329 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12330 /*IsSigned=*/ true, /*IsReplace=*/ false);
12331 SDValue FIST = Vals.first, StackSlot = Vals.second;
12332 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12333 if (!FIST.getNode()) return Op;
12335 if (StackSlot.getNode())
12336 // Load the result.
12337 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12338 FIST, StackSlot, MachinePointerInfo(),
12339 false, false, false, 0);
12341 // The node is the result.
12345 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12346 SelectionDAG &DAG) const {
12347 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12348 /*IsSigned=*/ false, /*IsReplace=*/ false);
12349 SDValue FIST = Vals.first, StackSlot = Vals.second;
12350 assert(FIST.getNode() && "Unexpected failure");
12352 if (StackSlot.getNode())
12353 // Load the result.
12354 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12355 FIST, StackSlot, MachinePointerInfo(),
12356 false, false, false, 0);
12358 // The node is the result.
12362 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12364 MVT VT = Op.getSimpleValueType();
12365 SDValue In = Op.getOperand(0);
12366 MVT SVT = In.getSimpleValueType();
12368 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12370 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12371 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12372 In, DAG.getUNDEF(SVT)));
12375 /// The only differences between FABS and FNEG are the mask and the logic op.
12376 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12377 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12378 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12379 "Wrong opcode for lowering FABS or FNEG.");
12381 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12383 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12384 // into an FNABS. We'll lower the FABS after that if it is still in use.
12386 for (SDNode *User : Op->uses())
12387 if (User->getOpcode() == ISD::FNEG)
12390 SDValue Op0 = Op.getOperand(0);
12391 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12394 MVT VT = Op.getSimpleValueType();
12395 // Assume scalar op for initialization; update for vector if needed.
12396 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12397 // generate a 16-byte vector constant and logic op even for the scalar case.
12398 // Using a 16-byte mask allows folding the load of the mask with
12399 // the logic op, so it can save (~4 bytes) on code size.
12401 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12402 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12403 // decide if we should generate a 16-byte constant mask when we only need 4 or
12404 // 8 bytes for the scalar case.
12405 if (VT.isVector()) {
12406 EltVT = VT.getVectorElementType();
12407 NumElts = VT.getVectorNumElements();
12410 unsigned EltBits = EltVT.getSizeInBits();
12411 LLVMContext *Context = DAG.getContext();
12412 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12414 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12415 Constant *C = ConstantInt::get(*Context, MaskElt);
12416 C = ConstantVector::getSplat(NumElts, C);
12417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12418 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12419 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12420 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12421 MachinePointerInfo::getConstantPool(),
12422 false, false, false, Alignment);
12424 if (VT.isVector()) {
12425 // For a vector, cast operands to a vector type, perform the logic op,
12426 // and cast the result back to the original value type.
12427 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12428 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12429 SDValue Operand = IsFNABS ?
12430 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12431 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12432 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12433 return DAG.getNode(ISD::BITCAST, dl, VT,
12434 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12437 // If not vector, then scalar.
12438 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12439 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12440 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12443 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12444 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12445 LLVMContext *Context = DAG.getContext();
12446 SDValue Op0 = Op.getOperand(0);
12447 SDValue Op1 = Op.getOperand(1);
12449 MVT VT = Op.getSimpleValueType();
12450 MVT SrcVT = Op1.getSimpleValueType();
12452 // If second operand is smaller, extend it first.
12453 if (SrcVT.bitsLT(VT)) {
12454 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12457 // And if it is bigger, shrink it first.
12458 if (SrcVT.bitsGT(VT)) {
12459 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12463 // At this point the operands and the result should have the same
12464 // type, and that won't be f80 since that is not custom lowered.
12466 const fltSemantics &Sem =
12467 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12468 const unsigned SizeInBits = VT.getSizeInBits();
12470 SmallVector<Constant *, 4> CV(
12471 VT == MVT::f64 ? 2 : 4,
12472 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12474 // First, clear all bits but the sign bit from the second operand (sign).
12475 CV[0] = ConstantFP::get(*Context,
12476 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12477 Constant *C = ConstantVector::get(CV);
12478 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12479 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12480 MachinePointerInfo::getConstantPool(),
12481 false, false, false, 16);
12482 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12484 // Next, clear the sign bit from the first operand (magnitude).
12485 // If it's a constant, we can clear it here.
12486 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12487 APFloat APF = Op0CN->getValueAPF();
12488 // If the magnitude is a positive zero, the sign bit alone is enough.
12489 if (APF.isPosZero())
12492 CV[0] = ConstantFP::get(*Context, APF);
12494 CV[0] = ConstantFP::get(
12496 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12498 C = ConstantVector::get(CV);
12499 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12500 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12501 MachinePointerInfo::getConstantPool(),
12502 false, false, false, 16);
12503 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12504 if (!isa<ConstantFPSDNode>(Op0))
12505 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12507 // OR the magnitude value with the sign bit.
12508 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12511 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12512 SDValue N0 = Op.getOperand(0);
12514 MVT VT = Op.getSimpleValueType();
12516 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12517 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12518 DAG.getConstant(1, dl, VT));
12519 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12522 // Check whether an OR'd tree is PTEST-able.
12523 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12524 SelectionDAG &DAG) {
12525 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12527 if (!Subtarget->hasSSE41())
12530 if (!Op->hasOneUse())
12533 SDNode *N = Op.getNode();
12536 SmallVector<SDValue, 8> Opnds;
12537 DenseMap<SDValue, unsigned> VecInMap;
12538 SmallVector<SDValue, 8> VecIns;
12539 EVT VT = MVT::Other;
12541 // Recognize a special case where a vector is casted into wide integer to
12543 Opnds.push_back(N->getOperand(0));
12544 Opnds.push_back(N->getOperand(1));
12546 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12547 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12548 // BFS traverse all OR'd operands.
12549 if (I->getOpcode() == ISD::OR) {
12550 Opnds.push_back(I->getOperand(0));
12551 Opnds.push_back(I->getOperand(1));
12552 // Re-evaluate the number of nodes to be traversed.
12553 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12557 // Quit if a non-EXTRACT_VECTOR_ELT
12558 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12561 // Quit if without a constant index.
12562 SDValue Idx = I->getOperand(1);
12563 if (!isa<ConstantSDNode>(Idx))
12566 SDValue ExtractedFromVec = I->getOperand(0);
12567 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12568 if (M == VecInMap.end()) {
12569 VT = ExtractedFromVec.getValueType();
12570 // Quit if not 128/256-bit vector.
12571 if (!VT.is128BitVector() && !VT.is256BitVector())
12573 // Quit if not the same type.
12574 if (VecInMap.begin() != VecInMap.end() &&
12575 VT != VecInMap.begin()->first.getValueType())
12577 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12578 VecIns.push_back(ExtractedFromVec);
12580 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12583 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12584 "Not extracted from 128-/256-bit vector.");
12586 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12588 for (DenseMap<SDValue, unsigned>::const_iterator
12589 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12590 // Quit if not all elements are used.
12591 if (I->second != FullMask)
12595 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12597 // Cast all vectors into TestVT for PTEST.
12598 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12599 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12601 // If more than one full vectors are evaluated, OR them first before PTEST.
12602 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12603 // Each iteration will OR 2 nodes and append the result until there is only
12604 // 1 node left, i.e. the final OR'd value of all vectors.
12605 SDValue LHS = VecIns[Slot];
12606 SDValue RHS = VecIns[Slot + 1];
12607 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12610 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12611 VecIns.back(), VecIns.back());
12614 /// \brief return true if \c Op has a use that doesn't just read flags.
12615 static bool hasNonFlagsUse(SDValue Op) {
12616 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12618 SDNode *User = *UI;
12619 unsigned UOpNo = UI.getOperandNo();
12620 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12621 // Look pass truncate.
12622 UOpNo = User->use_begin().getOperandNo();
12623 User = *User->use_begin();
12626 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12627 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12633 /// Emit nodes that will be selected as "test Op0,Op0", or something
12635 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12636 SelectionDAG &DAG) const {
12637 if (Op.getValueType() == MVT::i1) {
12638 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12639 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12640 DAG.getConstant(0, dl, MVT::i8));
12642 // CF and OF aren't always set the way we want. Determine which
12643 // of these we need.
12644 bool NeedCF = false;
12645 bool NeedOF = false;
12648 case X86::COND_A: case X86::COND_AE:
12649 case X86::COND_B: case X86::COND_BE:
12652 case X86::COND_G: case X86::COND_GE:
12653 case X86::COND_L: case X86::COND_LE:
12654 case X86::COND_O: case X86::COND_NO: {
12655 // Check if we really need to set the
12656 // Overflow flag. If NoSignedWrap is present
12657 // that is not actually needed.
12658 switch (Op->getOpcode()) {
12663 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12664 if (BinNode->Flags.hasNoSignedWrap())
12674 // See if we can use the EFLAGS value from the operand instead of
12675 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12676 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12677 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12678 // Emit a CMP with 0, which is the TEST pattern.
12679 //if (Op.getValueType() == MVT::i1)
12680 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12681 // DAG.getConstant(0, MVT::i1));
12682 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12683 DAG.getConstant(0, dl, Op.getValueType()));
12685 unsigned Opcode = 0;
12686 unsigned NumOperands = 0;
12688 // Truncate operations may prevent the merge of the SETCC instruction
12689 // and the arithmetic instruction before it. Attempt to truncate the operands
12690 // of the arithmetic instruction and use a reduced bit-width instruction.
12691 bool NeedTruncation = false;
12692 SDValue ArithOp = Op;
12693 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12694 SDValue Arith = Op->getOperand(0);
12695 // Both the trunc and the arithmetic op need to have one user each.
12696 if (Arith->hasOneUse())
12697 switch (Arith.getOpcode()) {
12704 NeedTruncation = true;
12710 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12711 // which may be the result of a CAST. We use the variable 'Op', which is the
12712 // non-casted variable when we check for possible users.
12713 switch (ArithOp.getOpcode()) {
12715 // Due to an isel shortcoming, be conservative if this add is likely to be
12716 // selected as part of a load-modify-store instruction. When the root node
12717 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12718 // uses of other nodes in the match, such as the ADD in this case. This
12719 // leads to the ADD being left around and reselected, with the result being
12720 // two adds in the output. Alas, even if none our users are stores, that
12721 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12722 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12723 // climbing the DAG back to the root, and it doesn't seem to be worth the
12725 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12726 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12727 if (UI->getOpcode() != ISD::CopyToReg &&
12728 UI->getOpcode() != ISD::SETCC &&
12729 UI->getOpcode() != ISD::STORE)
12732 if (ConstantSDNode *C =
12733 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12734 // An add of one will be selected as an INC.
12735 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12736 Opcode = X86ISD::INC;
12741 // An add of negative one (subtract of one) will be selected as a DEC.
12742 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12743 Opcode = X86ISD::DEC;
12749 // Otherwise use a regular EFLAGS-setting add.
12750 Opcode = X86ISD::ADD;
12755 // If we have a constant logical shift that's only used in a comparison
12756 // against zero turn it into an equivalent AND. This allows turning it into
12757 // a TEST instruction later.
12758 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12759 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12760 EVT VT = Op.getValueType();
12761 unsigned BitWidth = VT.getSizeInBits();
12762 unsigned ShAmt = Op->getConstantOperandVal(1);
12763 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12765 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12766 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12767 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12768 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12770 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12771 DAG.getConstant(Mask, dl, VT));
12772 DAG.ReplaceAllUsesWith(Op, New);
12778 // If the primary and result isn't used, don't bother using X86ISD::AND,
12779 // because a TEST instruction will be better.
12780 if (!hasNonFlagsUse(Op))
12786 // Due to the ISEL shortcoming noted above, be conservative if this op is
12787 // likely to be selected as part of a load-modify-store instruction.
12788 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12789 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12790 if (UI->getOpcode() == ISD::STORE)
12793 // Otherwise use a regular EFLAGS-setting instruction.
12794 switch (ArithOp.getOpcode()) {
12795 default: llvm_unreachable("unexpected operator!");
12796 case ISD::SUB: Opcode = X86ISD::SUB; break;
12797 case ISD::XOR: Opcode = X86ISD::XOR; break;
12798 case ISD::AND: Opcode = X86ISD::AND; break;
12800 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12801 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12802 if (EFLAGS.getNode())
12805 Opcode = X86ISD::OR;
12819 return SDValue(Op.getNode(), 1);
12825 // If we found that truncation is beneficial, perform the truncation and
12827 if (NeedTruncation) {
12828 EVT VT = Op.getValueType();
12829 SDValue WideVal = Op->getOperand(0);
12830 EVT WideVT = WideVal.getValueType();
12831 unsigned ConvertedOp = 0;
12832 // Use a target machine opcode to prevent further DAGCombine
12833 // optimizations that may separate the arithmetic operations
12834 // from the setcc node.
12835 switch (WideVal.getOpcode()) {
12837 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12838 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12839 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12840 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12841 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12846 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12847 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12848 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12849 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12855 // Emit a CMP with 0, which is the TEST pattern.
12856 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12857 DAG.getConstant(0, dl, Op.getValueType()));
12859 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12860 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12862 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12863 DAG.ReplaceAllUsesWith(Op, New);
12864 return SDValue(New.getNode(), 1);
12867 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12869 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12870 SDLoc dl, SelectionDAG &DAG) const {
12871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12872 if (C->getAPIntValue() == 0)
12873 return EmitTest(Op0, X86CC, dl, DAG);
12875 if (Op0.getValueType() == MVT::i1)
12876 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12879 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12880 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12881 // Do the comparison at i32 if it's smaller, besides the Atom case.
12882 // This avoids subregister aliasing issues. Keep the smaller reference
12883 // if we're optimizing for size, however, as that'll allow better folding
12884 // of memory operations.
12885 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12886 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12887 Attribute::MinSize) &&
12888 !Subtarget->isAtom()) {
12889 unsigned ExtendOp =
12890 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12891 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12892 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12894 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12895 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12896 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12898 return SDValue(Sub.getNode(), 1);
12900 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12903 /// Convert a comparison if required by the subtarget.
12904 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12905 SelectionDAG &DAG) const {
12906 // If the subtarget does not support the FUCOMI instruction, floating-point
12907 // comparisons have to be converted.
12908 if (Subtarget->hasCMov() ||
12909 Cmp.getOpcode() != X86ISD::CMP ||
12910 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12911 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12914 // The instruction selector will select an FUCOM instruction instead of
12915 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12916 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12917 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12919 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12920 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12921 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12922 DAG.getConstant(8, dl, MVT::i8));
12923 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12924 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12927 /// The minimum architected relative accuracy is 2^-12. We need one
12928 /// Newton-Raphson step to have a good float result (24 bits of precision).
12929 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12930 DAGCombinerInfo &DCI,
12931 unsigned &RefinementSteps,
12932 bool &UseOneConstNR) const {
12933 // FIXME: We should use instruction latency models to calculate the cost of
12934 // each potential sequence, but this is very hard to do reliably because
12935 // at least Intel's Core* chips have variable timing based on the number of
12936 // significant digits in the divisor and/or sqrt operand.
12937 if (!Subtarget->useSqrtEst())
12940 EVT VT = Op.getValueType();
12942 // SSE1 has rsqrtss and rsqrtps.
12943 // TODO: Add support for AVX512 (v16f32).
12944 // It is likely not profitable to do this for f64 because a double-precision
12945 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12946 // instructions: convert to single, rsqrtss, convert back to double, refine
12947 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12948 // along with FMA, this could be a throughput win.
12949 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12950 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12951 RefinementSteps = 1;
12952 UseOneConstNR = false;
12953 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12958 /// The minimum architected relative accuracy is 2^-12. We need one
12959 /// Newton-Raphson step to have a good float result (24 bits of precision).
12960 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12961 DAGCombinerInfo &DCI,
12962 unsigned &RefinementSteps) const {
12963 // FIXME: We should use instruction latency models to calculate the cost of
12964 // each potential sequence, but this is very hard to do reliably because
12965 // at least Intel's Core* chips have variable timing based on the number of
12966 // significant digits in the divisor.
12967 if (!Subtarget->useReciprocalEst())
12970 EVT VT = Op.getValueType();
12972 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12973 // TODO: Add support for AVX512 (v16f32).
12974 // It is likely not profitable to do this for f64 because a double-precision
12975 // reciprocal estimate with refinement on x86 prior to FMA requires
12976 // 15 instructions: convert to single, rcpss, convert back to double, refine
12977 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12978 // along with FMA, this could be a throughput win.
12979 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12980 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12981 RefinementSteps = ReciprocalEstimateRefinementSteps;
12982 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12987 /// If we have at least two divisions that use the same divisor, convert to
12988 /// multplication by a reciprocal. This may need to be adjusted for a given
12989 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12990 /// This is because we still need one division to calculate the reciprocal and
12991 /// then we need two multiplies by that reciprocal as replacements for the
12992 /// original divisions.
12993 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12994 return NumUsers > 1;
12997 static bool isAllOnes(SDValue V) {
12998 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12999 return C && C->isAllOnesValue();
13002 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13003 /// if it's possible.
13004 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13005 SDLoc dl, SelectionDAG &DAG) const {
13006 SDValue Op0 = And.getOperand(0);
13007 SDValue Op1 = And.getOperand(1);
13008 if (Op0.getOpcode() == ISD::TRUNCATE)
13009 Op0 = Op0.getOperand(0);
13010 if (Op1.getOpcode() == ISD::TRUNCATE)
13011 Op1 = Op1.getOperand(0);
13014 if (Op1.getOpcode() == ISD::SHL)
13015 std::swap(Op0, Op1);
13016 if (Op0.getOpcode() == ISD::SHL) {
13017 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13018 if (And00C->getZExtValue() == 1) {
13019 // If we looked past a truncate, check that it's only truncating away
13021 unsigned BitWidth = Op0.getValueSizeInBits();
13022 unsigned AndBitWidth = And.getValueSizeInBits();
13023 if (BitWidth > AndBitWidth) {
13025 DAG.computeKnownBits(Op0, Zeros, Ones);
13026 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13030 RHS = Op0.getOperand(1);
13032 } else if (Op1.getOpcode() == ISD::Constant) {
13033 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13034 uint64_t AndRHSVal = AndRHS->getZExtValue();
13035 SDValue AndLHS = Op0;
13037 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13038 LHS = AndLHS.getOperand(0);
13039 RHS = AndLHS.getOperand(1);
13042 // Use BT if the immediate can't be encoded in a TEST instruction.
13043 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13045 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13049 if (LHS.getNode()) {
13050 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13051 // instruction. Since the shift amount is in-range-or-undefined, we know
13052 // that doing a bittest on the i32 value is ok. We extend to i32 because
13053 // the encoding for the i16 version is larger than the i32 version.
13054 // Also promote i16 to i32 for performance / code size reason.
13055 if (LHS.getValueType() == MVT::i8 ||
13056 LHS.getValueType() == MVT::i16)
13057 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13059 // If the operand types disagree, extend the shift amount to match. Since
13060 // BT ignores high bits (like shifts) we can use anyextend.
13061 if (LHS.getValueType() != RHS.getValueType())
13062 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13064 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13065 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13066 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13067 DAG.getConstant(Cond, dl, MVT::i8), BT);
13073 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13075 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13080 // SSE Condition code mapping:
13089 switch (SetCCOpcode) {
13090 default: llvm_unreachable("Unexpected SETCC condition");
13092 case ISD::SETEQ: SSECC = 0; break;
13094 case ISD::SETGT: Swap = true; // Fallthrough
13096 case ISD::SETOLT: SSECC = 1; break;
13098 case ISD::SETGE: Swap = true; // Fallthrough
13100 case ISD::SETOLE: SSECC = 2; break;
13101 case ISD::SETUO: SSECC = 3; break;
13103 case ISD::SETNE: SSECC = 4; break;
13104 case ISD::SETULE: Swap = true; // Fallthrough
13105 case ISD::SETUGE: SSECC = 5; break;
13106 case ISD::SETULT: Swap = true; // Fallthrough
13107 case ISD::SETUGT: SSECC = 6; break;
13108 case ISD::SETO: SSECC = 7; break;
13110 case ISD::SETONE: SSECC = 8; break;
13113 std::swap(Op0, Op1);
13118 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13119 // ones, and then concatenate the result back.
13120 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13121 MVT VT = Op.getSimpleValueType();
13123 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13124 "Unsupported value type for operation");
13126 unsigned NumElems = VT.getVectorNumElements();
13128 SDValue CC = Op.getOperand(2);
13130 // Extract the LHS vectors
13131 SDValue LHS = Op.getOperand(0);
13132 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13133 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13135 // Extract the RHS vectors
13136 SDValue RHS = Op.getOperand(1);
13137 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13138 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13140 // Issue the operation on the smaller types and concatenate the result back
13141 MVT EltVT = VT.getVectorElementType();
13142 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13143 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13144 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13145 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13148 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13149 SDValue Op0 = Op.getOperand(0);
13150 SDValue Op1 = Op.getOperand(1);
13151 SDValue CC = Op.getOperand(2);
13152 MVT VT = Op.getSimpleValueType();
13155 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13156 "Unexpected type for boolean compare operation");
13157 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13158 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13159 DAG.getConstant(-1, dl, VT));
13160 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13161 DAG.getConstant(-1, dl, VT));
13162 switch (SetCCOpcode) {
13163 default: llvm_unreachable("Unexpected SETCC condition");
13165 // (x != y) -> ~(x ^ y)
13166 return DAG.getNode(ISD::XOR, dl, VT,
13167 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13168 DAG.getConstant(-1, dl, VT));
13170 // (x == y) -> (x ^ y)
13171 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13174 // (x > y) -> (x & ~y)
13175 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13178 // (x < y) -> (~x & y)
13179 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13182 // (x <= y) -> (~x | y)
13183 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13186 // (x >=y) -> (x | ~y)
13187 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13191 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13192 const X86Subtarget *Subtarget) {
13193 SDValue Op0 = Op.getOperand(0);
13194 SDValue Op1 = Op.getOperand(1);
13195 SDValue CC = Op.getOperand(2);
13196 MVT VT = Op.getSimpleValueType();
13199 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13200 Op.getValueType().getScalarType() == MVT::i1 &&
13201 "Cannot set masked compare for this operation");
13203 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13205 bool Unsigned = false;
13208 switch (SetCCOpcode) {
13209 default: llvm_unreachable("Unexpected SETCC condition");
13210 case ISD::SETNE: SSECC = 4; break;
13211 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13212 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13213 case ISD::SETLT: Swap = true; //fall-through
13214 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13215 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13216 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13217 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13218 case ISD::SETULE: Unsigned = true; //fall-through
13219 case ISD::SETLE: SSECC = 2; break;
13223 std::swap(Op0, Op1);
13225 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13226 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13227 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13228 DAG.getConstant(SSECC, dl, MVT::i8));
13231 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13232 /// operand \p Op1. If non-trivial (for example because it's not constant)
13233 /// return an empty value.
13234 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13236 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13240 MVT VT = Op1.getSimpleValueType();
13241 MVT EVT = VT.getVectorElementType();
13242 unsigned n = VT.getVectorNumElements();
13243 SmallVector<SDValue, 8> ULTOp1;
13245 for (unsigned i = 0; i < n; ++i) {
13246 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13247 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13250 // Avoid underflow.
13251 APInt Val = Elt->getAPIntValue();
13255 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13258 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13261 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13262 SelectionDAG &DAG) {
13263 SDValue Op0 = Op.getOperand(0);
13264 SDValue Op1 = Op.getOperand(1);
13265 SDValue CC = Op.getOperand(2);
13266 MVT VT = Op.getSimpleValueType();
13267 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13268 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13273 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13274 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13277 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13278 unsigned Opc = X86ISD::CMPP;
13279 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13280 assert(VT.getVectorNumElements() <= 16);
13281 Opc = X86ISD::CMPM;
13283 // In the two special cases we can't handle, emit two comparisons.
13286 unsigned CombineOpc;
13287 if (SetCCOpcode == ISD::SETUEQ) {
13288 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13290 assert(SetCCOpcode == ISD::SETONE);
13291 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13294 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13295 DAG.getConstant(CC0, dl, MVT::i8));
13296 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13297 DAG.getConstant(CC1, dl, MVT::i8));
13298 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13300 // Handle all other FP comparisons here.
13301 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13302 DAG.getConstant(SSECC, dl, MVT::i8));
13305 // Break 256-bit integer vector compare into smaller ones.
13306 if (VT.is256BitVector() && !Subtarget->hasInt256())
13307 return Lower256IntVSETCC(Op, DAG);
13309 EVT OpVT = Op1.getValueType();
13310 if (OpVT.getVectorElementType() == MVT::i1)
13311 return LowerBoolVSETCC_AVX512(Op, DAG);
13313 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13314 if (Subtarget->hasAVX512()) {
13315 if (Op1.getValueType().is512BitVector() ||
13316 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13317 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13318 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13320 // In AVX-512 architecture setcc returns mask with i1 elements,
13321 // But there is no compare instruction for i8 and i16 elements in KNL.
13322 // We are not talking about 512-bit operands in this case, these
13323 // types are illegal.
13325 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13326 OpVT.getVectorElementType().getSizeInBits() >= 8))
13327 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13328 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13331 // We are handling one of the integer comparisons here. Since SSE only has
13332 // GT and EQ comparisons for integer, swapping operands and multiple
13333 // operations may be required for some comparisons.
13335 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13336 bool Subus = false;
13338 switch (SetCCOpcode) {
13339 default: llvm_unreachable("Unexpected SETCC condition");
13340 case ISD::SETNE: Invert = true;
13341 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13342 case ISD::SETLT: Swap = true;
13343 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13344 case ISD::SETGE: Swap = true;
13345 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13346 Invert = true; break;
13347 case ISD::SETULT: Swap = true;
13348 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13349 FlipSigns = true; break;
13350 case ISD::SETUGE: Swap = true;
13351 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13352 FlipSigns = true; Invert = true; break;
13355 // Special case: Use min/max operations for SETULE/SETUGE
13356 MVT VET = VT.getVectorElementType();
13358 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13359 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13362 switch (SetCCOpcode) {
13364 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13365 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13368 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13371 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13372 if (!MinMax && hasSubus) {
13373 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13375 // t = psubus Op0, Op1
13376 // pcmpeq t, <0..0>
13377 switch (SetCCOpcode) {
13379 case ISD::SETULT: {
13380 // If the comparison is against a constant we can turn this into a
13381 // setule. With psubus, setule does not require a swap. This is
13382 // beneficial because the constant in the register is no longer
13383 // destructed as the destination so it can be hoisted out of a loop.
13384 // Only do this pre-AVX since vpcmp* is no longer destructive.
13385 if (Subtarget->hasAVX())
13387 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13388 if (ULEOp1.getNode()) {
13390 Subus = true; Invert = false; Swap = false;
13394 // Psubus is better than flip-sign because it requires no inversion.
13395 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13396 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13400 Opc = X86ISD::SUBUS;
13406 std::swap(Op0, Op1);
13408 // Check that the operation in question is available (most are plain SSE2,
13409 // but PCMPGTQ and PCMPEQQ have different requirements).
13410 if (VT == MVT::v2i64) {
13411 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13412 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13414 // First cast everything to the right type.
13415 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13416 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13418 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13419 // bits of the inputs before performing those operations. The lower
13420 // compare is always unsigned.
13423 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13425 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13426 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13427 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13428 Sign, Zero, Sign, Zero);
13430 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13431 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13433 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13434 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13435 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13437 // Create masks for only the low parts/high parts of the 64 bit integers.
13438 static const int MaskHi[] = { 1, 1, 3, 3 };
13439 static const int MaskLo[] = { 0, 0, 2, 2 };
13440 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13441 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13442 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13444 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13445 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13448 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13450 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13453 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13454 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13455 // pcmpeqd + pshufd + pand.
13456 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13458 // First cast everything to the right type.
13459 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13460 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13463 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13465 // Make sure the lower and upper halves are both all-ones.
13466 static const int Mask[] = { 1, 0, 3, 2 };
13467 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13468 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13471 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13473 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13477 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13478 // bits of the inputs before performing those operations.
13480 EVT EltVT = VT.getVectorElementType();
13481 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13483 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13484 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13487 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13489 // If the logical-not of the result is required, perform that now.
13491 Result = DAG.getNOT(dl, Result, VT);
13494 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13497 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13498 getZeroVector(VT, Subtarget, DAG, dl));
13503 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13505 MVT VT = Op.getSimpleValueType();
13507 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13509 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13510 && "SetCC type must be 8-bit or 1-bit integer");
13511 SDValue Op0 = Op.getOperand(0);
13512 SDValue Op1 = Op.getOperand(1);
13514 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13516 // Optimize to BT if possible.
13517 // Lower (X & (1 << N)) == 0 to BT(X, N).
13518 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13519 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13520 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13521 Op1.getOpcode() == ISD::Constant &&
13522 cast<ConstantSDNode>(Op1)->isNullValue() &&
13523 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13524 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13525 if (NewSetCC.getNode()) {
13527 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13532 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13534 if (Op1.getOpcode() == ISD::Constant &&
13535 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13536 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13537 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13539 // If the input is a setcc, then reuse the input setcc or use a new one with
13540 // the inverted condition.
13541 if (Op0.getOpcode() == X86ISD::SETCC) {
13542 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13543 bool Invert = (CC == ISD::SETNE) ^
13544 cast<ConstantSDNode>(Op1)->isNullValue();
13548 CCode = X86::GetOppositeBranchCondition(CCode);
13549 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13550 DAG.getConstant(CCode, dl, MVT::i8),
13551 Op0.getOperand(1));
13553 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13557 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13558 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13559 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13561 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13562 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13565 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13566 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13567 if (X86CC == X86::COND_INVALID)
13570 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13571 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13572 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13573 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13575 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13579 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13580 static bool isX86LogicalCmp(SDValue Op) {
13581 unsigned Opc = Op.getNode()->getOpcode();
13582 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13583 Opc == X86ISD::SAHF)
13585 if (Op.getResNo() == 1 &&
13586 (Opc == X86ISD::ADD ||
13587 Opc == X86ISD::SUB ||
13588 Opc == X86ISD::ADC ||
13589 Opc == X86ISD::SBB ||
13590 Opc == X86ISD::SMUL ||
13591 Opc == X86ISD::UMUL ||
13592 Opc == X86ISD::INC ||
13593 Opc == X86ISD::DEC ||
13594 Opc == X86ISD::OR ||
13595 Opc == X86ISD::XOR ||
13596 Opc == X86ISD::AND))
13599 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13605 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13606 if (V.getOpcode() != ISD::TRUNCATE)
13609 SDValue VOp0 = V.getOperand(0);
13610 unsigned InBits = VOp0.getValueSizeInBits();
13611 unsigned Bits = V.getValueSizeInBits();
13612 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13615 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13616 bool addTest = true;
13617 SDValue Cond = Op.getOperand(0);
13618 SDValue Op1 = Op.getOperand(1);
13619 SDValue Op2 = Op.getOperand(2);
13621 EVT VT = Op1.getValueType();
13624 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13625 // are available or VBLENDV if AVX is available.
13626 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13627 if (Cond.getOpcode() == ISD::SETCC &&
13628 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13629 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13630 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13631 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13632 int SSECC = translateX86FSETCC(
13633 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13636 if (Subtarget->hasAVX512()) {
13637 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13638 DAG.getConstant(SSECC, DL, MVT::i8));
13639 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13642 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13643 DAG.getConstant(SSECC, DL, MVT::i8));
13645 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13646 // of 3 logic instructions for size savings and potentially speed.
13647 // Unfortunately, there is no scalar form of VBLENDV.
13649 // If either operand is a constant, don't try this. We can expect to
13650 // optimize away at least one of the logic instructions later in that
13651 // case, so that sequence would be faster than a variable blend.
13653 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13654 // uses XMM0 as the selection register. That may need just as many
13655 // instructions as the AND/ANDN/OR sequence due to register moves, so
13658 if (Subtarget->hasAVX() &&
13659 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13661 // Convert to vectors, do a VSELECT, and convert back to scalar.
13662 // All of the conversions should be optimized away.
13664 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13665 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13666 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13667 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13669 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13670 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13672 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13674 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13675 VSel, DAG.getIntPtrConstant(0, DL));
13677 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13678 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13679 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13683 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13685 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13686 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13687 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13688 Op1Scalar = Op1.getOperand(0);
13690 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13691 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13692 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13693 Op2Scalar = Op2.getOperand(0);
13694 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13695 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13696 Op1Scalar.getValueType(),
13697 Cond, Op1Scalar, Op2Scalar);
13698 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13699 return DAG.getNode(ISD::BITCAST, DL, VT, newSelect);
13700 SDValue ExtVec = DAG.getNode(ISD::BITCAST, DL, MVT::v8i1, newSelect);
13701 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13702 DAG.getIntPtrConstant(0, DL));
13706 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13707 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13708 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13709 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13710 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13711 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13712 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13714 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13717 if (Cond.getOpcode() == ISD::SETCC) {
13718 SDValue NewCond = LowerSETCC(Cond, DAG);
13719 if (NewCond.getNode())
13723 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13724 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13725 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13726 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13727 if (Cond.getOpcode() == X86ISD::SETCC &&
13728 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13729 isZero(Cond.getOperand(1).getOperand(1))) {
13730 SDValue Cmp = Cond.getOperand(1);
13732 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13734 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13735 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13736 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13738 SDValue CmpOp0 = Cmp.getOperand(0);
13739 // Apply further optimizations for special cases
13740 // (select (x != 0), -1, 0) -> neg & sbb
13741 // (select (x == 0), 0, -1) -> neg & sbb
13742 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13743 if (YC->isNullValue() &&
13744 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13745 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13746 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13747 DAG.getConstant(0, DL,
13748 CmpOp0.getValueType()),
13750 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13751 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13752 SDValue(Neg.getNode(), 1));
13756 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13757 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13758 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13760 SDValue Res = // Res = 0 or -1.
13761 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13762 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13764 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13765 Res = DAG.getNOT(DL, Res, Res.getValueType());
13767 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13768 if (!N2C || !N2C->isNullValue())
13769 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13774 // Look past (and (setcc_carry (cmp ...)), 1).
13775 if (Cond.getOpcode() == ISD::AND &&
13776 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13777 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13778 if (C && C->getAPIntValue() == 1)
13779 Cond = Cond.getOperand(0);
13782 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13783 // setting operand in place of the X86ISD::SETCC.
13784 unsigned CondOpcode = Cond.getOpcode();
13785 if (CondOpcode == X86ISD::SETCC ||
13786 CondOpcode == X86ISD::SETCC_CARRY) {
13787 CC = Cond.getOperand(0);
13789 SDValue Cmp = Cond.getOperand(1);
13790 unsigned Opc = Cmp.getOpcode();
13791 MVT VT = Op.getSimpleValueType();
13793 bool IllegalFPCMov = false;
13794 if (VT.isFloatingPoint() && !VT.isVector() &&
13795 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13796 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13798 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13799 Opc == X86ISD::BT) { // FIXME
13803 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13804 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13805 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13806 Cond.getOperand(0).getValueType() != MVT::i8)) {
13807 SDValue LHS = Cond.getOperand(0);
13808 SDValue RHS = Cond.getOperand(1);
13809 unsigned X86Opcode;
13812 switch (CondOpcode) {
13813 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13814 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13815 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13816 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13817 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13818 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13819 default: llvm_unreachable("unexpected overflowing operator");
13821 if (CondOpcode == ISD::UMULO)
13822 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13825 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13827 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13829 if (CondOpcode == ISD::UMULO)
13830 Cond = X86Op.getValue(2);
13832 Cond = X86Op.getValue(1);
13834 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13839 // Look pass the truncate if the high bits are known zero.
13840 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13841 Cond = Cond.getOperand(0);
13843 // We know the result of AND is compared against zero. Try to match
13845 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13846 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13847 if (NewSetCC.getNode()) {
13848 CC = NewSetCC.getOperand(0);
13849 Cond = NewSetCC.getOperand(1);
13856 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13857 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13860 // a < b ? -1 : 0 -> RES = ~setcc_carry
13861 // a < b ? 0 : -1 -> RES = setcc_carry
13862 // a >= b ? -1 : 0 -> RES = setcc_carry
13863 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13864 if (Cond.getOpcode() == X86ISD::SUB) {
13865 Cond = ConvertCmpIfNecessary(Cond, DAG);
13866 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13868 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13869 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13870 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13871 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13873 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13874 return DAG.getNOT(DL, Res, Res.getValueType());
13879 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13880 // widen the cmov and push the truncate through. This avoids introducing a new
13881 // branch during isel and doesn't add any extensions.
13882 if (Op.getValueType() == MVT::i8 &&
13883 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13884 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13885 if (T1.getValueType() == T2.getValueType() &&
13886 // Blacklist CopyFromReg to avoid partial register stalls.
13887 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13888 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13889 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13890 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13894 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13895 // condition is true.
13896 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13897 SDValue Ops[] = { Op2, Op1, CC, Cond };
13898 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13901 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13902 const X86Subtarget *Subtarget,
13903 SelectionDAG &DAG) {
13904 MVT VT = Op->getSimpleValueType(0);
13905 SDValue In = Op->getOperand(0);
13906 MVT InVT = In.getSimpleValueType();
13907 MVT VTElt = VT.getVectorElementType();
13908 MVT InVTElt = InVT.getVectorElementType();
13912 if ((InVTElt == MVT::i1) &&
13913 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13914 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13916 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13917 VTElt.getSizeInBits() <= 16)) ||
13919 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13920 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13922 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13923 VTElt.getSizeInBits() >= 32))))
13924 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13926 unsigned int NumElts = VT.getVectorNumElements();
13928 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13931 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13932 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13933 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13934 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13937 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13938 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13940 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13943 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13945 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13946 if (VT.is512BitVector())
13948 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13951 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
13952 const X86Subtarget *Subtarget,
13953 SelectionDAG &DAG) {
13954 SDValue In = Op->getOperand(0);
13955 MVT VT = Op->getSimpleValueType(0);
13956 MVT InVT = In.getSimpleValueType();
13957 assert(VT.getSizeInBits() == InVT.getSizeInBits());
13959 MVT InSVT = InVT.getScalarType();
13960 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
13962 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13964 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
13969 // SSE41 targets can use the pmovsx* instructions directly.
13970 if (Subtarget->hasSSE41())
13971 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13973 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
13977 // As SRAI is only available on i16/i32 types, we expand only up to i32
13978 // and handle i64 separately.
13979 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
13980 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
13981 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
13982 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
13983 Curr = DAG.getNode(ISD::BITCAST, dl, CurrVT, Curr);
13986 SDValue SignExt = Curr;
13987 if (CurrVT != InVT) {
13988 unsigned SignExtShift =
13989 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
13990 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13991 DAG.getConstant(SignExtShift, dl, MVT::i8));
13997 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
13998 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13999 DAG.getConstant(31, dl, MVT::i8));
14000 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14001 return DAG.getNode(ISD::BITCAST, dl, VT, Ext);
14007 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14008 SelectionDAG &DAG) {
14009 MVT VT = Op->getSimpleValueType(0);
14010 SDValue In = Op->getOperand(0);
14011 MVT InVT = In.getSimpleValueType();
14014 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14015 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14017 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14018 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14019 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14022 if (Subtarget->hasInt256())
14023 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14025 // Optimize vectors in AVX mode
14026 // Sign extend v8i16 to v8i32 and
14029 // Divide input vector into two parts
14030 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14031 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14032 // concat the vectors to original VT
14034 unsigned NumElems = InVT.getVectorNumElements();
14035 SDValue Undef = DAG.getUNDEF(InVT);
14037 SmallVector<int,8> ShufMask1(NumElems, -1);
14038 for (unsigned i = 0; i != NumElems/2; ++i)
14041 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14043 SmallVector<int,8> ShufMask2(NumElems, -1);
14044 for (unsigned i = 0; i != NumElems/2; ++i)
14045 ShufMask2[i] = i + NumElems/2;
14047 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14049 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14050 VT.getVectorNumElements()/2);
14052 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14053 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14055 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14058 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14059 // may emit an illegal shuffle but the expansion is still better than scalar
14060 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14061 // we'll emit a shuffle and a arithmetic shift.
14062 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14063 // TODO: It is possible to support ZExt by zeroing the undef values during
14064 // the shuffle phase or after the shuffle.
14065 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14066 SelectionDAG &DAG) {
14067 MVT RegVT = Op.getSimpleValueType();
14068 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14069 assert(RegVT.isInteger() &&
14070 "We only custom lower integer vector sext loads.");
14072 // Nothing useful we can do without SSE2 shuffles.
14073 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14075 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14077 EVT MemVT = Ld->getMemoryVT();
14078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14079 unsigned RegSz = RegVT.getSizeInBits();
14081 ISD::LoadExtType Ext = Ld->getExtensionType();
14083 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14084 && "Only anyext and sext are currently implemented.");
14085 assert(MemVT != RegVT && "Cannot extend to the same type");
14086 assert(MemVT.isVector() && "Must load a vector from memory");
14088 unsigned NumElems = RegVT.getVectorNumElements();
14089 unsigned MemSz = MemVT.getSizeInBits();
14090 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14092 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14093 // The only way in which we have a legal 256-bit vector result but not the
14094 // integer 256-bit operations needed to directly lower a sextload is if we
14095 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14096 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14097 // correctly legalized. We do this late to allow the canonical form of
14098 // sextload to persist throughout the rest of the DAG combiner -- it wants
14099 // to fold together any extensions it can, and so will fuse a sign_extend
14100 // of an sextload into a sextload targeting a wider value.
14102 if (MemSz == 128) {
14103 // Just switch this to a normal load.
14104 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14105 "it must be a legal 128-bit vector "
14107 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14108 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14109 Ld->isInvariant(), Ld->getAlignment());
14111 assert(MemSz < 128 &&
14112 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14113 // Do an sext load to a 128-bit vector type. We want to use the same
14114 // number of elements, but elements half as wide. This will end up being
14115 // recursively lowered by this routine, but will succeed as we definitely
14116 // have all the necessary features if we're using AVX1.
14118 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14119 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14121 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14122 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14123 Ld->isNonTemporal(), Ld->isInvariant(),
14124 Ld->getAlignment());
14127 // Replace chain users with the new chain.
14128 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14129 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14131 // Finally, do a normal sign-extend to the desired register.
14132 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14135 // All sizes must be a power of two.
14136 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14137 "Non-power-of-two elements are not custom lowered!");
14139 // Attempt to load the original value using scalar loads.
14140 // Find the largest scalar type that divides the total loaded size.
14141 MVT SclrLoadTy = MVT::i8;
14142 for (MVT Tp : MVT::integer_valuetypes()) {
14143 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14148 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14149 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14151 SclrLoadTy = MVT::f64;
14153 // Calculate the number of scalar loads that we need to perform
14154 // in order to load our vector from memory.
14155 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14157 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14158 "Can only lower sext loads with a single scalar load!");
14160 unsigned loadRegZize = RegSz;
14161 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14164 // Represent our vector as a sequence of elements which are the
14165 // largest scalar that we can load.
14166 EVT LoadUnitVecVT = EVT::getVectorVT(
14167 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14169 // Represent the data using the same element type that is stored in
14170 // memory. In practice, we ''widen'' MemVT.
14172 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14173 loadRegZize / MemVT.getScalarType().getSizeInBits());
14175 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14176 "Invalid vector type");
14178 // We can't shuffle using an illegal type.
14179 assert(TLI.isTypeLegal(WideVecVT) &&
14180 "We only lower types that form legal widened vector types");
14182 SmallVector<SDValue, 8> Chains;
14183 SDValue Ptr = Ld->getBasePtr();
14184 SDValue Increment =
14185 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14186 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14188 for (unsigned i = 0; i < NumLoads; ++i) {
14189 // Perform a single load.
14190 SDValue ScalarLoad =
14191 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14192 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14193 Ld->getAlignment());
14194 Chains.push_back(ScalarLoad.getValue(1));
14195 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14196 // another round of DAGCombining.
14198 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14200 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14201 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14203 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14206 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14208 // Bitcast the loaded value to a vector of the original element type, in
14209 // the size of the target vector type.
14210 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14211 unsigned SizeRatio = RegSz / MemSz;
14213 if (Ext == ISD::SEXTLOAD) {
14214 // If we have SSE4.1, we can directly emit a VSEXT node.
14215 if (Subtarget->hasSSE41()) {
14216 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14217 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14221 // Otherwise we'll shuffle the small elements in the high bits of the
14222 // larger type and perform an arithmetic shift. If the shift is not legal
14223 // it's better to scalarize.
14224 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14225 "We can't implement a sext load without an arithmetic right shift!");
14227 // Redistribute the loaded elements into the different locations.
14228 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14229 for (unsigned i = 0; i != NumElems; ++i)
14230 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14232 SDValue Shuff = DAG.getVectorShuffle(
14233 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14235 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14237 // Build the arithmetic shift.
14238 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14239 MemVT.getVectorElementType().getSizeInBits();
14241 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14242 DAG.getConstant(Amt, dl, RegVT));
14244 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14248 // Redistribute the loaded elements into the different locations.
14249 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14250 for (unsigned i = 0; i != NumElems; ++i)
14251 ShuffleVec[i * SizeRatio] = i;
14253 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14254 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14256 // Bitcast to the requested type.
14257 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14258 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14262 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14263 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14264 // from the AND / OR.
14265 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14266 Opc = Op.getOpcode();
14267 if (Opc != ISD::OR && Opc != ISD::AND)
14269 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14270 Op.getOperand(0).hasOneUse() &&
14271 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14272 Op.getOperand(1).hasOneUse());
14275 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14276 // 1 and that the SETCC node has a single use.
14277 static bool isXor1OfSetCC(SDValue Op) {
14278 if (Op.getOpcode() != ISD::XOR)
14280 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14281 if (N1C && N1C->getAPIntValue() == 1) {
14282 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14283 Op.getOperand(0).hasOneUse();
14288 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14289 bool addTest = true;
14290 SDValue Chain = Op.getOperand(0);
14291 SDValue Cond = Op.getOperand(1);
14292 SDValue Dest = Op.getOperand(2);
14295 bool Inverted = false;
14297 if (Cond.getOpcode() == ISD::SETCC) {
14298 // Check for setcc([su]{add,sub,mul}o == 0).
14299 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14300 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14301 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14302 Cond.getOperand(0).getResNo() == 1 &&
14303 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14304 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14305 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14306 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14307 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14308 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14310 Cond = Cond.getOperand(0);
14312 SDValue NewCond = LowerSETCC(Cond, DAG);
14313 if (NewCond.getNode())
14318 // FIXME: LowerXALUO doesn't handle these!!
14319 else if (Cond.getOpcode() == X86ISD::ADD ||
14320 Cond.getOpcode() == X86ISD::SUB ||
14321 Cond.getOpcode() == X86ISD::SMUL ||
14322 Cond.getOpcode() == X86ISD::UMUL)
14323 Cond = LowerXALUO(Cond, DAG);
14326 // Look pass (and (setcc_carry (cmp ...)), 1).
14327 if (Cond.getOpcode() == ISD::AND &&
14328 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14329 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14330 if (C && C->getAPIntValue() == 1)
14331 Cond = Cond.getOperand(0);
14334 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14335 // setting operand in place of the X86ISD::SETCC.
14336 unsigned CondOpcode = Cond.getOpcode();
14337 if (CondOpcode == X86ISD::SETCC ||
14338 CondOpcode == X86ISD::SETCC_CARRY) {
14339 CC = Cond.getOperand(0);
14341 SDValue Cmp = Cond.getOperand(1);
14342 unsigned Opc = Cmp.getOpcode();
14343 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14344 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14348 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14352 // These can only come from an arithmetic instruction with overflow,
14353 // e.g. SADDO, UADDO.
14354 Cond = Cond.getNode()->getOperand(1);
14360 CondOpcode = Cond.getOpcode();
14361 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14362 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14363 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14364 Cond.getOperand(0).getValueType() != MVT::i8)) {
14365 SDValue LHS = Cond.getOperand(0);
14366 SDValue RHS = Cond.getOperand(1);
14367 unsigned X86Opcode;
14370 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14371 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14373 switch (CondOpcode) {
14374 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14376 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14378 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14381 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14382 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14386 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14389 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14390 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14391 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14392 default: llvm_unreachable("unexpected overflowing operator");
14395 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14396 if (CondOpcode == ISD::UMULO)
14397 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14400 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14402 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14404 if (CondOpcode == ISD::UMULO)
14405 Cond = X86Op.getValue(2);
14407 Cond = X86Op.getValue(1);
14409 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14413 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14414 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14415 if (CondOpc == ISD::OR) {
14416 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14417 // two branches instead of an explicit OR instruction with a
14419 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14420 isX86LogicalCmp(Cmp)) {
14421 CC = Cond.getOperand(0).getOperand(0);
14422 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14423 Chain, Dest, CC, Cmp);
14424 CC = Cond.getOperand(1).getOperand(0);
14428 } else { // ISD::AND
14429 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14430 // two branches instead of an explicit AND instruction with a
14431 // separate test. However, we only do this if this block doesn't
14432 // have a fall-through edge, because this requires an explicit
14433 // jmp when the condition is false.
14434 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14435 isX86LogicalCmp(Cmp) &&
14436 Op.getNode()->hasOneUse()) {
14437 X86::CondCode CCode =
14438 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14439 CCode = X86::GetOppositeBranchCondition(CCode);
14440 CC = DAG.getConstant(CCode, dl, MVT::i8);
14441 SDNode *User = *Op.getNode()->use_begin();
14442 // Look for an unconditional branch following this conditional branch.
14443 // We need this because we need to reverse the successors in order
14444 // to implement FCMP_OEQ.
14445 if (User->getOpcode() == ISD::BR) {
14446 SDValue FalseBB = User->getOperand(1);
14448 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14449 assert(NewBR == User);
14453 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14454 Chain, Dest, CC, Cmp);
14455 X86::CondCode CCode =
14456 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14457 CCode = X86::GetOppositeBranchCondition(CCode);
14458 CC = DAG.getConstant(CCode, dl, MVT::i8);
14464 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14465 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14466 // It should be transformed during dag combiner except when the condition
14467 // is set by a arithmetics with overflow node.
14468 X86::CondCode CCode =
14469 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14470 CCode = X86::GetOppositeBranchCondition(CCode);
14471 CC = DAG.getConstant(CCode, dl, MVT::i8);
14472 Cond = Cond.getOperand(0).getOperand(1);
14474 } else if (Cond.getOpcode() == ISD::SETCC &&
14475 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14476 // For FCMP_OEQ, we can emit
14477 // two branches instead of an explicit AND instruction with a
14478 // separate test. However, we only do this if this block doesn't
14479 // have a fall-through edge, because this requires an explicit
14480 // jmp when the condition is false.
14481 if (Op.getNode()->hasOneUse()) {
14482 SDNode *User = *Op.getNode()->use_begin();
14483 // Look for an unconditional branch following this conditional branch.
14484 // We need this because we need to reverse the successors in order
14485 // to implement FCMP_OEQ.
14486 if (User->getOpcode() == ISD::BR) {
14487 SDValue FalseBB = User->getOperand(1);
14489 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14490 assert(NewBR == User);
14494 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14495 Cond.getOperand(0), Cond.getOperand(1));
14496 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14497 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14498 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14499 Chain, Dest, CC, Cmp);
14500 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14505 } else if (Cond.getOpcode() == ISD::SETCC &&
14506 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14507 // For FCMP_UNE, we can emit
14508 // two branches instead of an explicit AND instruction with a
14509 // separate test. However, we only do this if this block doesn't
14510 // have a fall-through edge, because this requires an explicit
14511 // jmp when the condition is false.
14512 if (Op.getNode()->hasOneUse()) {
14513 SDNode *User = *Op.getNode()->use_begin();
14514 // Look for an unconditional branch following this conditional branch.
14515 // We need this because we need to reverse the successors in order
14516 // to implement FCMP_UNE.
14517 if (User->getOpcode() == ISD::BR) {
14518 SDValue FalseBB = User->getOperand(1);
14520 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14521 assert(NewBR == User);
14524 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14525 Cond.getOperand(0), Cond.getOperand(1));
14526 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14527 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14528 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14529 Chain, Dest, CC, Cmp);
14530 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14540 // Look pass the truncate if the high bits are known zero.
14541 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14542 Cond = Cond.getOperand(0);
14544 // We know the result of AND is compared against zero. Try to match
14546 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14547 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14548 if (NewSetCC.getNode()) {
14549 CC = NewSetCC.getOperand(0);
14550 Cond = NewSetCC.getOperand(1);
14557 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14558 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14559 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14561 Cond = ConvertCmpIfNecessary(Cond, DAG);
14562 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14563 Chain, Dest, CC, Cond);
14566 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14567 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14568 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14569 // that the guard pages used by the OS virtual memory manager are allocated in
14570 // correct sequence.
14572 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14573 SelectionDAG &DAG) const {
14574 MachineFunction &MF = DAG.getMachineFunction();
14575 bool SplitStack = MF.shouldSplitStack();
14576 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14581 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14582 SDNode* Node = Op.getNode();
14584 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14585 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14586 " not tell us which reg is the stack pointer!");
14587 EVT VT = Node->getValueType(0);
14588 SDValue Tmp1 = SDValue(Node, 0);
14589 SDValue Tmp2 = SDValue(Node, 1);
14590 SDValue Tmp3 = Node->getOperand(2);
14591 SDValue Chain = Tmp1.getOperand(0);
14593 // Chain the dynamic stack allocation so that it doesn't modify the stack
14594 // pointer when other instructions are using the stack.
14595 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14598 SDValue Size = Tmp2.getOperand(1);
14599 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14600 Chain = SP.getValue(1);
14601 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14602 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14603 unsigned StackAlign = TFI.getStackAlignment();
14604 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14605 if (Align > StackAlign)
14606 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14607 DAG.getConstant(-(uint64_t)Align, dl, VT));
14608 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14610 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14611 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14614 SDValue Ops[2] = { Tmp1, Tmp2 };
14615 return DAG.getMergeValues(Ops, dl);
14619 SDValue Chain = Op.getOperand(0);
14620 SDValue Size = Op.getOperand(1);
14621 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14622 EVT VT = Op.getNode()->getValueType(0);
14624 bool Is64Bit = Subtarget->is64Bit();
14625 EVT SPTy = getPointerTy();
14628 MachineRegisterInfo &MRI = MF.getRegInfo();
14631 // The 64 bit implementation of segmented stacks needs to clobber both r10
14632 // r11. This makes it impossible to use it along with nested parameters.
14633 const Function *F = MF.getFunction();
14635 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14637 if (I->hasNestAttr())
14638 report_fatal_error("Cannot use segmented stacks with functions that "
14639 "have nested arguments.");
14642 const TargetRegisterClass *AddrRegClass =
14643 getRegClassFor(getPointerTy());
14644 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14645 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14646 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14647 DAG.getRegister(Vreg, SPTy));
14648 SDValue Ops1[2] = { Value, Chain };
14649 return DAG.getMergeValues(Ops1, dl);
14652 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14654 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14655 Flag = Chain.getValue(1);
14656 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14658 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14660 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14661 unsigned SPReg = RegInfo->getStackRegister();
14662 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14663 Chain = SP.getValue(1);
14666 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14667 DAG.getConstant(-(uint64_t)Align, dl, VT));
14668 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14671 SDValue Ops1[2] = { SP, Chain };
14672 return DAG.getMergeValues(Ops1, dl);
14676 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14677 MachineFunction &MF = DAG.getMachineFunction();
14678 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14680 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14683 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14684 // vastart just stores the address of the VarArgsFrameIndex slot into the
14685 // memory location argument.
14686 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14688 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14689 MachinePointerInfo(SV), false, false, 0);
14693 // gp_offset (0 - 6 * 8)
14694 // fp_offset (48 - 48 + 8 * 16)
14695 // overflow_arg_area (point to parameters coming in memory).
14697 SmallVector<SDValue, 8> MemOps;
14698 SDValue FIN = Op.getOperand(1);
14700 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14701 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14703 FIN, MachinePointerInfo(SV), false, false, 0);
14704 MemOps.push_back(Store);
14707 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14708 FIN, DAG.getIntPtrConstant(4, DL));
14709 Store = DAG.getStore(Op.getOperand(0), DL,
14710 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14712 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14713 MemOps.push_back(Store);
14715 // Store ptr to overflow_arg_area
14716 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14717 FIN, DAG.getIntPtrConstant(4, DL));
14718 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14720 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14721 MachinePointerInfo(SV, 8),
14723 MemOps.push_back(Store);
14725 // Store ptr to reg_save_area.
14726 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14727 FIN, DAG.getIntPtrConstant(8, DL));
14728 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14730 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14731 MachinePointerInfo(SV, 16), false, false, 0);
14732 MemOps.push_back(Store);
14733 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14736 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14737 assert(Subtarget->is64Bit() &&
14738 "LowerVAARG only handles 64-bit va_arg!");
14739 assert((Subtarget->isTargetLinux() ||
14740 Subtarget->isTargetDarwin()) &&
14741 "Unhandled target in LowerVAARG");
14742 assert(Op.getNode()->getNumOperands() == 4);
14743 SDValue Chain = Op.getOperand(0);
14744 SDValue SrcPtr = Op.getOperand(1);
14745 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14746 unsigned Align = Op.getConstantOperandVal(3);
14749 EVT ArgVT = Op.getNode()->getValueType(0);
14750 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14751 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14754 // Decide which area this value should be read from.
14755 // TODO: Implement the AMD64 ABI in its entirety. This simple
14756 // selection mechanism works only for the basic types.
14757 if (ArgVT == MVT::f80) {
14758 llvm_unreachable("va_arg for f80 not yet implemented");
14759 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14760 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14761 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14762 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14764 llvm_unreachable("Unhandled argument type in LowerVAARG");
14767 if (ArgMode == 2) {
14768 // Sanity Check: Make sure using fp_offset makes sense.
14769 assert(!Subtarget->useSoftFloat() &&
14770 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14771 Attribute::NoImplicitFloat)) &&
14772 Subtarget->hasSSE1());
14775 // Insert VAARG_64 node into the DAG
14776 // VAARG_64 returns two values: Variable Argument Address, Chain
14777 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14778 DAG.getConstant(ArgMode, dl, MVT::i8),
14779 DAG.getConstant(Align, dl, MVT::i32)};
14780 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14781 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14782 VTs, InstOps, MVT::i64,
14783 MachinePointerInfo(SV),
14785 /*Volatile=*/false,
14787 /*WriteMem=*/true);
14788 Chain = VAARG.getValue(1);
14790 // Load the next argument and return it
14791 return DAG.getLoad(ArgVT, dl,
14794 MachinePointerInfo(),
14795 false, false, false, 0);
14798 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14799 SelectionDAG &DAG) {
14800 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14801 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14802 SDValue Chain = Op.getOperand(0);
14803 SDValue DstPtr = Op.getOperand(1);
14804 SDValue SrcPtr = Op.getOperand(2);
14805 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14806 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14809 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14810 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14812 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14815 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14816 // amount is a constant. Takes immediate version of shift as input.
14817 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14818 SDValue SrcOp, uint64_t ShiftAmt,
14819 SelectionDAG &DAG) {
14820 MVT ElementType = VT.getVectorElementType();
14822 // Fold this packed shift into its first operand if ShiftAmt is 0.
14826 // Check for ShiftAmt >= element width
14827 if (ShiftAmt >= ElementType.getSizeInBits()) {
14828 if (Opc == X86ISD::VSRAI)
14829 ShiftAmt = ElementType.getSizeInBits() - 1;
14831 return DAG.getConstant(0, dl, VT);
14834 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14835 && "Unknown target vector shift-by-constant node");
14837 // Fold this packed vector shift into a build vector if SrcOp is a
14838 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14839 if (VT == SrcOp.getSimpleValueType() &&
14840 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14841 SmallVector<SDValue, 8> Elts;
14842 unsigned NumElts = SrcOp->getNumOperands();
14843 ConstantSDNode *ND;
14846 default: llvm_unreachable(nullptr);
14847 case X86ISD::VSHLI:
14848 for (unsigned i=0; i!=NumElts; ++i) {
14849 SDValue CurrentOp = SrcOp->getOperand(i);
14850 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14851 Elts.push_back(CurrentOp);
14854 ND = cast<ConstantSDNode>(CurrentOp);
14855 const APInt &C = ND->getAPIntValue();
14856 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14859 case X86ISD::VSRLI:
14860 for (unsigned i=0; i!=NumElts; ++i) {
14861 SDValue CurrentOp = SrcOp->getOperand(i);
14862 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14863 Elts.push_back(CurrentOp);
14866 ND = cast<ConstantSDNode>(CurrentOp);
14867 const APInt &C = ND->getAPIntValue();
14868 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14871 case X86ISD::VSRAI:
14872 for (unsigned i=0; i!=NumElts; ++i) {
14873 SDValue CurrentOp = SrcOp->getOperand(i);
14874 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14875 Elts.push_back(CurrentOp);
14878 ND = cast<ConstantSDNode>(CurrentOp);
14879 const APInt &C = ND->getAPIntValue();
14880 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14885 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14888 return DAG.getNode(Opc, dl, VT, SrcOp,
14889 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14892 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14893 // may or may not be a constant. Takes immediate version of shift as input.
14894 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14895 SDValue SrcOp, SDValue ShAmt,
14896 SelectionDAG &DAG) {
14897 MVT SVT = ShAmt.getSimpleValueType();
14898 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14900 // Catch shift-by-constant.
14901 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14902 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14903 CShAmt->getZExtValue(), DAG);
14905 // Change opcode to non-immediate version
14907 default: llvm_unreachable("Unknown target vector shift node");
14908 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14909 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14910 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14913 const X86Subtarget &Subtarget =
14914 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14915 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14916 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14917 // Let the shuffle legalizer expand this shift amount node.
14918 SDValue Op0 = ShAmt.getOperand(0);
14919 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14920 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14922 // Need to build a vector containing shift amount.
14923 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14924 SmallVector<SDValue, 4> ShOps;
14925 ShOps.push_back(ShAmt);
14926 if (SVT == MVT::i32) {
14927 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14928 ShOps.push_back(DAG.getUNDEF(SVT));
14930 ShOps.push_back(DAG.getUNDEF(SVT));
14932 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14933 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14936 // The return type has to be a 128-bit type with the same element
14937 // type as the input type.
14938 MVT EltVT = VT.getVectorElementType();
14939 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14941 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14942 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14945 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14946 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14947 /// necessary casting for \p Mask when lowering masking intrinsics.
14948 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14949 SDValue PreservedSrc,
14950 const X86Subtarget *Subtarget,
14951 SelectionDAG &DAG) {
14952 EVT VT = Op.getValueType();
14953 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14954 MVT::i1, VT.getVectorNumElements());
14955 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14956 Mask.getValueType().getSizeInBits());
14959 assert(MaskVT.isSimple() && "invalid mask type");
14961 if (isAllOnes(Mask))
14964 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14965 // are extracted by EXTRACT_SUBVECTOR.
14966 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14967 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14968 DAG.getIntPtrConstant(0, dl));
14970 switch (Op.getOpcode()) {
14972 case X86ISD::PCMPEQM:
14973 case X86ISD::PCMPGTM:
14975 case X86ISD::CMPMU:
14976 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14978 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14979 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14980 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14983 /// \brief Creates an SDNode for a predicated scalar operation.
14984 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14985 /// The mask is comming as MVT::i8 and it should be truncated
14986 /// to MVT::i1 while lowering masking intrinsics.
14987 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14988 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14989 /// a scalar instruction.
14990 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14991 SDValue PreservedSrc,
14992 const X86Subtarget *Subtarget,
14993 SelectionDAG &DAG) {
14994 if (isAllOnes(Mask))
14997 EVT VT = Op.getValueType();
14999 // The mask should be of type MVT::i1
15000 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15002 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15003 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15004 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15007 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15008 SelectionDAG &DAG) {
15010 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15011 EVT VT = Op.getValueType();
15012 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15014 switch(IntrData->Type) {
15015 case INTR_TYPE_1OP:
15016 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15017 case INTR_TYPE_2OP:
15018 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15020 case INTR_TYPE_3OP:
15021 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15022 Op.getOperand(2), Op.getOperand(3));
15023 case INTR_TYPE_1OP_MASK_RM: {
15024 SDValue Src = Op.getOperand(1);
15025 SDValue Src0 = Op.getOperand(2);
15026 SDValue Mask = Op.getOperand(3);
15027 SDValue RoundingMode = Op.getOperand(4);
15028 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15030 Mask, Src0, Subtarget, DAG);
15032 case INTR_TYPE_SCALAR_MASK_RM: {
15033 SDValue Src1 = Op.getOperand(1);
15034 SDValue Src2 = Op.getOperand(2);
15035 SDValue Src0 = Op.getOperand(3);
15036 SDValue Mask = Op.getOperand(4);
15037 // There are 2 kinds of intrinsics in this group:
15038 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15039 // (2) With rounding mode and sae - 7 operands.
15040 if (Op.getNumOperands() == 6) {
15041 SDValue Sae = Op.getOperand(5);
15042 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15043 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15045 Mask, Src0, Subtarget, DAG);
15047 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15048 SDValue RoundingMode = Op.getOperand(5);
15049 SDValue Sae = Op.getOperand(6);
15050 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15051 RoundingMode, Sae),
15052 Mask, Src0, Subtarget, DAG);
15054 case INTR_TYPE_2OP_MASK: {
15055 SDValue Src1 = Op.getOperand(1);
15056 SDValue Src2 = Op.getOperand(2);
15057 SDValue PassThru = Op.getOperand(3);
15058 SDValue Mask = Op.getOperand(4);
15059 // We specify 2 possible opcodes for intrinsics with rounding modes.
15060 // First, we check if the intrinsic may have non-default rounding mode,
15061 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15062 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15063 if (IntrWithRoundingModeOpcode != 0) {
15064 SDValue Rnd = Op.getOperand(5);
15065 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15066 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15067 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15068 dl, Op.getValueType(),
15070 Mask, PassThru, Subtarget, DAG);
15073 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15075 Mask, PassThru, Subtarget, DAG);
15077 case FMA_OP_MASK: {
15078 SDValue Src1 = Op.getOperand(1);
15079 SDValue Src2 = Op.getOperand(2);
15080 SDValue Src3 = Op.getOperand(3);
15081 SDValue Mask = Op.getOperand(4);
15082 // We specify 2 possible opcodes for intrinsics with rounding modes.
15083 // First, we check if the intrinsic may have non-default rounding mode,
15084 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15085 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15086 if (IntrWithRoundingModeOpcode != 0) {
15087 SDValue Rnd = Op.getOperand(5);
15088 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15089 X86::STATIC_ROUNDING::CUR_DIRECTION)
15090 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15091 dl, Op.getValueType(),
15092 Src1, Src2, Src3, Rnd),
15093 Mask, Src1, Subtarget, DAG);
15095 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15096 dl, Op.getValueType(),
15098 Mask, Src1, Subtarget, DAG);
15101 case CMP_MASK_CC: {
15102 // Comparison intrinsics with masks.
15103 // Example of transformation:
15104 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15105 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15107 // (v8i1 (insert_subvector undef,
15108 // (v2i1 (and (PCMPEQM %a, %b),
15109 // (extract_subvector
15110 // (v8i1 (bitcast %mask)), 0))), 0))))
15111 EVT VT = Op.getOperand(1).getValueType();
15112 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15113 VT.getVectorNumElements());
15114 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15115 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15116 Mask.getValueType().getSizeInBits());
15118 if (IntrData->Type == CMP_MASK_CC) {
15119 SDValue CC = Op.getOperand(3);
15120 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15121 // We specify 2 possible opcodes for intrinsics with rounding modes.
15122 // First, we check if the intrinsic may have non-default rounding mode,
15123 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15124 if (IntrData->Opc1 != 0) {
15125 SDValue Rnd = Op.getOperand(5);
15126 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15127 X86::STATIC_ROUNDING::CUR_DIRECTION)
15128 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15129 Op.getOperand(2), CC, Rnd);
15131 //default rounding mode
15133 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15134 Op.getOperand(2), CC);
15137 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15138 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15141 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15142 DAG.getTargetConstant(0, dl,
15145 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15146 DAG.getUNDEF(BitcastVT), CmpMask,
15147 DAG.getIntPtrConstant(0, dl));
15148 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15150 case COMI: { // Comparison intrinsics
15151 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15152 SDValue LHS = Op.getOperand(1);
15153 SDValue RHS = Op.getOperand(2);
15154 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15155 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15156 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15157 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15158 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15159 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15162 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15163 Op.getOperand(1), Op.getOperand(2), DAG);
15165 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15166 Op.getSimpleValueType(),
15168 Op.getOperand(2), DAG),
15169 Op.getOperand(4), Op.getOperand(3), Subtarget,
15171 case COMPRESS_EXPAND_IN_REG: {
15172 SDValue Mask = Op.getOperand(3);
15173 SDValue DataToCompress = Op.getOperand(1);
15174 SDValue PassThru = Op.getOperand(2);
15175 if (isAllOnes(Mask)) // return data as is
15176 return Op.getOperand(1);
15177 EVT VT = Op.getValueType();
15178 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15179 VT.getVectorNumElements());
15180 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15181 Mask.getValueType().getSizeInBits());
15183 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15184 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15185 DAG.getIntPtrConstant(0, dl));
15187 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15191 SDValue Mask = Op.getOperand(3);
15192 EVT VT = Op.getValueType();
15193 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15194 VT.getVectorNumElements());
15195 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15196 Mask.getValueType().getSizeInBits());
15198 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15199 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15200 DAG.getIntPtrConstant(0, dl));
15201 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15210 default: return SDValue(); // Don't custom lower most intrinsics.
15212 case Intrinsic::x86_avx2_permd:
15213 case Intrinsic::x86_avx2_permps:
15214 // Operands intentionally swapped. Mask is last operand to intrinsic,
15215 // but second operand for node/instruction.
15216 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15217 Op.getOperand(2), Op.getOperand(1));
15219 case Intrinsic::x86_avx512_mask_valign_q_512:
15220 case Intrinsic::x86_avx512_mask_valign_d_512:
15221 // Vector source operands are swapped.
15222 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15223 Op.getValueType(), Op.getOperand(2),
15226 Op.getOperand(5), Op.getOperand(4),
15229 // ptest and testp intrinsics. The intrinsic these come from are designed to
15230 // return an integer value, not just an instruction so lower it to the ptest
15231 // or testp pattern and a setcc for the result.
15232 case Intrinsic::x86_sse41_ptestz:
15233 case Intrinsic::x86_sse41_ptestc:
15234 case Intrinsic::x86_sse41_ptestnzc:
15235 case Intrinsic::x86_avx_ptestz_256:
15236 case Intrinsic::x86_avx_ptestc_256:
15237 case Intrinsic::x86_avx_ptestnzc_256:
15238 case Intrinsic::x86_avx_vtestz_ps:
15239 case Intrinsic::x86_avx_vtestc_ps:
15240 case Intrinsic::x86_avx_vtestnzc_ps:
15241 case Intrinsic::x86_avx_vtestz_pd:
15242 case Intrinsic::x86_avx_vtestc_pd:
15243 case Intrinsic::x86_avx_vtestnzc_pd:
15244 case Intrinsic::x86_avx_vtestz_ps_256:
15245 case Intrinsic::x86_avx_vtestc_ps_256:
15246 case Intrinsic::x86_avx_vtestnzc_ps_256:
15247 case Intrinsic::x86_avx_vtestz_pd_256:
15248 case Intrinsic::x86_avx_vtestc_pd_256:
15249 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15250 bool IsTestPacked = false;
15253 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15254 case Intrinsic::x86_avx_vtestz_ps:
15255 case Intrinsic::x86_avx_vtestz_pd:
15256 case Intrinsic::x86_avx_vtestz_ps_256:
15257 case Intrinsic::x86_avx_vtestz_pd_256:
15258 IsTestPacked = true; // Fallthrough
15259 case Intrinsic::x86_sse41_ptestz:
15260 case Intrinsic::x86_avx_ptestz_256:
15262 X86CC = X86::COND_E;
15264 case Intrinsic::x86_avx_vtestc_ps:
15265 case Intrinsic::x86_avx_vtestc_pd:
15266 case Intrinsic::x86_avx_vtestc_ps_256:
15267 case Intrinsic::x86_avx_vtestc_pd_256:
15268 IsTestPacked = true; // Fallthrough
15269 case Intrinsic::x86_sse41_ptestc:
15270 case Intrinsic::x86_avx_ptestc_256:
15272 X86CC = X86::COND_B;
15274 case Intrinsic::x86_avx_vtestnzc_ps:
15275 case Intrinsic::x86_avx_vtestnzc_pd:
15276 case Intrinsic::x86_avx_vtestnzc_ps_256:
15277 case Intrinsic::x86_avx_vtestnzc_pd_256:
15278 IsTestPacked = true; // Fallthrough
15279 case Intrinsic::x86_sse41_ptestnzc:
15280 case Intrinsic::x86_avx_ptestnzc_256:
15282 X86CC = X86::COND_A;
15286 SDValue LHS = Op.getOperand(1);
15287 SDValue RHS = Op.getOperand(2);
15288 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15289 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15290 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15291 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15292 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15294 case Intrinsic::x86_avx512_kortestz_w:
15295 case Intrinsic::x86_avx512_kortestc_w: {
15296 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15297 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15298 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15299 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15300 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15301 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15302 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15305 case Intrinsic::x86_sse42_pcmpistria128:
15306 case Intrinsic::x86_sse42_pcmpestria128:
15307 case Intrinsic::x86_sse42_pcmpistric128:
15308 case Intrinsic::x86_sse42_pcmpestric128:
15309 case Intrinsic::x86_sse42_pcmpistrio128:
15310 case Intrinsic::x86_sse42_pcmpestrio128:
15311 case Intrinsic::x86_sse42_pcmpistris128:
15312 case Intrinsic::x86_sse42_pcmpestris128:
15313 case Intrinsic::x86_sse42_pcmpistriz128:
15314 case Intrinsic::x86_sse42_pcmpestriz128: {
15318 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15319 case Intrinsic::x86_sse42_pcmpistria128:
15320 Opcode = X86ISD::PCMPISTRI;
15321 X86CC = X86::COND_A;
15323 case Intrinsic::x86_sse42_pcmpestria128:
15324 Opcode = X86ISD::PCMPESTRI;
15325 X86CC = X86::COND_A;
15327 case Intrinsic::x86_sse42_pcmpistric128:
15328 Opcode = X86ISD::PCMPISTRI;
15329 X86CC = X86::COND_B;
15331 case Intrinsic::x86_sse42_pcmpestric128:
15332 Opcode = X86ISD::PCMPESTRI;
15333 X86CC = X86::COND_B;
15335 case Intrinsic::x86_sse42_pcmpistrio128:
15336 Opcode = X86ISD::PCMPISTRI;
15337 X86CC = X86::COND_O;
15339 case Intrinsic::x86_sse42_pcmpestrio128:
15340 Opcode = X86ISD::PCMPESTRI;
15341 X86CC = X86::COND_O;
15343 case Intrinsic::x86_sse42_pcmpistris128:
15344 Opcode = X86ISD::PCMPISTRI;
15345 X86CC = X86::COND_S;
15347 case Intrinsic::x86_sse42_pcmpestris128:
15348 Opcode = X86ISD::PCMPESTRI;
15349 X86CC = X86::COND_S;
15351 case Intrinsic::x86_sse42_pcmpistriz128:
15352 Opcode = X86ISD::PCMPISTRI;
15353 X86CC = X86::COND_E;
15355 case Intrinsic::x86_sse42_pcmpestriz128:
15356 Opcode = X86ISD::PCMPESTRI;
15357 X86CC = X86::COND_E;
15360 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15361 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15362 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15363 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15364 DAG.getConstant(X86CC, dl, MVT::i8),
15365 SDValue(PCMP.getNode(), 1));
15366 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15369 case Intrinsic::x86_sse42_pcmpistri128:
15370 case Intrinsic::x86_sse42_pcmpestri128: {
15372 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15373 Opcode = X86ISD::PCMPISTRI;
15375 Opcode = X86ISD::PCMPESTRI;
15377 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15378 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15379 return DAG.getNode(Opcode, dl, VTs, NewOps);
15382 case Intrinsic::x86_seh_lsda: {
15383 // Compute the symbol for the LSDA. We know it'll get emitted later.
15384 MachineFunction &MF = DAG.getMachineFunction();
15385 SDValue Op1 = Op.getOperand(1);
15386 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15387 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15388 GlobalValue::getRealLinkageName(Fn->getName()));
15389 StringRef Name = LSDASym->getName();
15390 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15392 // Generate a simple absolute symbol reference. This intrinsic is only
15393 // supported on 32-bit Windows, which isn't PIC.
15395 DAG.getTargetExternalSymbol(Name.data(), VT, X86II::MO_NOPREFIX);
15396 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15401 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15402 SDValue Src, SDValue Mask, SDValue Base,
15403 SDValue Index, SDValue ScaleOp, SDValue Chain,
15404 const X86Subtarget * Subtarget) {
15406 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15407 assert(C && "Invalid scale type");
15408 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15409 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15410 Index.getSimpleValueType().getVectorNumElements());
15412 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15414 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15416 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15417 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15418 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15419 SDValue Segment = DAG.getRegister(0, MVT::i32);
15420 if (Src.getOpcode() == ISD::UNDEF)
15421 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15422 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15423 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15424 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15425 return DAG.getMergeValues(RetOps, dl);
15428 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15429 SDValue Src, SDValue Mask, SDValue Base,
15430 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15432 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15433 assert(C && "Invalid scale type");
15434 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15435 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15436 SDValue Segment = DAG.getRegister(0, MVT::i32);
15437 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15438 Index.getSimpleValueType().getVectorNumElements());
15440 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15442 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15444 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15445 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15446 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15447 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15448 return SDValue(Res, 1);
15451 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15452 SDValue Mask, SDValue Base, SDValue Index,
15453 SDValue ScaleOp, SDValue Chain) {
15455 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15456 assert(C && "Invalid scale type");
15457 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15458 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15459 SDValue Segment = DAG.getRegister(0, MVT::i32);
15461 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15463 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15465 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15467 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15468 //SDVTList VTs = DAG.getVTList(MVT::Other);
15469 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15470 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15471 return SDValue(Res, 0);
15474 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15475 // read performance monitor counters (x86_rdpmc).
15476 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15477 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15478 SmallVectorImpl<SDValue> &Results) {
15479 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15480 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15483 // The ECX register is used to select the index of the performance counter
15485 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15487 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15489 // Reads the content of a 64-bit performance counter and returns it in the
15490 // registers EDX:EAX.
15491 if (Subtarget->is64Bit()) {
15492 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15493 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15496 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15497 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15500 Chain = HI.getValue(1);
15502 if (Subtarget->is64Bit()) {
15503 // The EAX register is loaded with the low-order 32 bits. The EDX register
15504 // is loaded with the supported high-order bits of the counter.
15505 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15506 DAG.getConstant(32, DL, MVT::i8));
15507 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15508 Results.push_back(Chain);
15512 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15513 SDValue Ops[] = { LO, HI };
15514 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15515 Results.push_back(Pair);
15516 Results.push_back(Chain);
15519 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15520 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15521 // also used to custom lower READCYCLECOUNTER nodes.
15522 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15523 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15524 SmallVectorImpl<SDValue> &Results) {
15525 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15526 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15529 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15530 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15531 // and the EAX register is loaded with the low-order 32 bits.
15532 if (Subtarget->is64Bit()) {
15533 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15534 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15537 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15538 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15541 SDValue Chain = HI.getValue(1);
15543 if (Opcode == X86ISD::RDTSCP_DAG) {
15544 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15546 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15547 // the ECX register. Add 'ecx' explicitly to the chain.
15548 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15550 // Explicitly store the content of ECX at the location passed in input
15551 // to the 'rdtscp' intrinsic.
15552 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15553 MachinePointerInfo(), false, false, 0);
15556 if (Subtarget->is64Bit()) {
15557 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15558 // the EAX register is loaded with the low-order 32 bits.
15559 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15560 DAG.getConstant(32, DL, MVT::i8));
15561 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15562 Results.push_back(Chain);
15566 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15567 SDValue Ops[] = { LO, HI };
15568 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15569 Results.push_back(Pair);
15570 Results.push_back(Chain);
15573 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15574 SelectionDAG &DAG) {
15575 SmallVector<SDValue, 2> Results;
15577 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15579 return DAG.getMergeValues(Results, DL);
15583 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15584 SelectionDAG &DAG) {
15585 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15587 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15592 switch(IntrData->Type) {
15594 llvm_unreachable("Unknown Intrinsic Type");
15598 // Emit the node with the right value type.
15599 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15600 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15602 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15603 // Otherwise return the value from Rand, which is always 0, casted to i32.
15604 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15605 DAG.getConstant(1, dl, Op->getValueType(1)),
15606 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15607 SDValue(Result.getNode(), 1) };
15608 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15609 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15612 // Return { result, isValid, chain }.
15613 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15614 SDValue(Result.getNode(), 2));
15617 //gather(v1, mask, index, base, scale);
15618 SDValue Chain = Op.getOperand(0);
15619 SDValue Src = Op.getOperand(2);
15620 SDValue Base = Op.getOperand(3);
15621 SDValue Index = Op.getOperand(4);
15622 SDValue Mask = Op.getOperand(5);
15623 SDValue Scale = Op.getOperand(6);
15624 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15628 //scatter(base, mask, index, v1, scale);
15629 SDValue Chain = Op.getOperand(0);
15630 SDValue Base = Op.getOperand(2);
15631 SDValue Mask = Op.getOperand(3);
15632 SDValue Index = Op.getOperand(4);
15633 SDValue Src = Op.getOperand(5);
15634 SDValue Scale = Op.getOperand(6);
15635 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15639 SDValue Hint = Op.getOperand(6);
15640 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15641 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15642 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15643 SDValue Chain = Op.getOperand(0);
15644 SDValue Mask = Op.getOperand(2);
15645 SDValue Index = Op.getOperand(3);
15646 SDValue Base = Op.getOperand(4);
15647 SDValue Scale = Op.getOperand(5);
15648 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15650 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15652 SmallVector<SDValue, 2> Results;
15653 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15655 return DAG.getMergeValues(Results, dl);
15657 // Read Performance Monitoring Counters.
15659 SmallVector<SDValue, 2> Results;
15660 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15661 return DAG.getMergeValues(Results, dl);
15663 // XTEST intrinsics.
15665 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15666 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15667 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15668 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15670 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15671 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15672 Ret, SDValue(InTrans.getNode(), 1));
15676 SmallVector<SDValue, 2> Results;
15677 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15678 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15679 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15680 DAG.getConstant(-1, dl, MVT::i8));
15681 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15682 Op.getOperand(4), GenCF.getValue(1));
15683 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15684 Op.getOperand(5), MachinePointerInfo(),
15686 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15687 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15689 Results.push_back(SetCC);
15690 Results.push_back(Store);
15691 return DAG.getMergeValues(Results, dl);
15693 case COMPRESS_TO_MEM: {
15695 SDValue Mask = Op.getOperand(4);
15696 SDValue DataToCompress = Op.getOperand(3);
15697 SDValue Addr = Op.getOperand(2);
15698 SDValue Chain = Op.getOperand(0);
15700 if (isAllOnes(Mask)) // return just a store
15701 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15702 MachinePointerInfo(), false, false, 0);
15704 EVT VT = DataToCompress.getValueType();
15705 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15706 VT.getVectorNumElements());
15707 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15708 Mask.getValueType().getSizeInBits());
15709 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15710 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15711 DAG.getIntPtrConstant(0, dl));
15713 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15714 DataToCompress, DAG.getUNDEF(VT));
15715 return DAG.getStore(Chain, dl, Compressed, Addr,
15716 MachinePointerInfo(), false, false, 0);
15718 case EXPAND_FROM_MEM: {
15720 SDValue Mask = Op.getOperand(4);
15721 SDValue PathThru = Op.getOperand(3);
15722 SDValue Addr = Op.getOperand(2);
15723 SDValue Chain = Op.getOperand(0);
15724 EVT VT = Op.getValueType();
15726 if (isAllOnes(Mask)) // return just a load
15727 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15729 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15730 VT.getVectorNumElements());
15731 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15732 Mask.getValueType().getSizeInBits());
15733 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15734 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15735 DAG.getIntPtrConstant(0, dl));
15737 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15738 false, false, false, 0);
15740 SDValue Results[] = {
15741 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15743 return DAG.getMergeValues(Results, dl);
15748 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15749 SelectionDAG &DAG) const {
15750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15751 MFI->setReturnAddressIsTaken(true);
15753 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15756 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15758 EVT PtrVT = getPointerTy();
15761 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15762 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15763 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15764 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15765 DAG.getNode(ISD::ADD, dl, PtrVT,
15766 FrameAddr, Offset),
15767 MachinePointerInfo(), false, false, false, 0);
15770 // Just load the return address.
15771 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15772 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15773 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15776 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15777 MachineFunction &MF = DAG.getMachineFunction();
15778 MachineFrameInfo *MFI = MF.getFrameInfo();
15779 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15780 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15781 EVT VT = Op.getValueType();
15783 MFI->setFrameAddressIsTaken(true);
15785 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15786 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15787 // is not possible to crawl up the stack without looking at the unwind codes
15789 int FrameAddrIndex = FuncInfo->getFAIndex();
15790 if (!FrameAddrIndex) {
15791 // Set up a frame object for the return address.
15792 unsigned SlotSize = RegInfo->getSlotSize();
15793 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15794 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15795 FuncInfo->setFAIndex(FrameAddrIndex);
15797 return DAG.getFrameIndex(FrameAddrIndex, VT);
15800 unsigned FrameReg =
15801 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15802 SDLoc dl(Op); // FIXME probably not meaningful
15803 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15804 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15805 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15806 "Invalid Frame Register!");
15807 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15809 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15810 MachinePointerInfo(),
15811 false, false, false, 0);
15815 // FIXME? Maybe this could be a TableGen attribute on some registers and
15816 // this table could be generated automatically from RegInfo.
15817 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15819 unsigned Reg = StringSwitch<unsigned>(RegName)
15820 .Case("esp", X86::ESP)
15821 .Case("rsp", X86::RSP)
15825 report_fatal_error("Invalid register name global variable");
15828 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15829 SelectionDAG &DAG) const {
15830 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15831 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15834 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15835 SDValue Chain = Op.getOperand(0);
15836 SDValue Offset = Op.getOperand(1);
15837 SDValue Handler = Op.getOperand(2);
15840 EVT PtrVT = getPointerTy();
15841 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15842 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15843 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15844 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15845 "Invalid Frame Register!");
15846 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15847 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15849 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15850 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15852 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15853 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15855 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15857 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15858 DAG.getRegister(StoreAddrReg, PtrVT));
15861 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15862 SelectionDAG &DAG) const {
15864 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15865 DAG.getVTList(MVT::i32, MVT::Other),
15866 Op.getOperand(0), Op.getOperand(1));
15869 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15870 SelectionDAG &DAG) const {
15872 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15873 Op.getOperand(0), Op.getOperand(1));
15876 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15877 return Op.getOperand(0);
15880 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15881 SelectionDAG &DAG) const {
15882 SDValue Root = Op.getOperand(0);
15883 SDValue Trmp = Op.getOperand(1); // trampoline
15884 SDValue FPtr = Op.getOperand(2); // nested function
15885 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15888 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15889 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15891 if (Subtarget->is64Bit()) {
15892 SDValue OutChains[6];
15894 // Large code-model.
15895 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15896 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15898 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15899 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15901 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15903 // Load the pointer to the nested function into R11.
15904 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15905 SDValue Addr = Trmp;
15906 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15907 Addr, MachinePointerInfo(TrmpAddr),
15910 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15911 DAG.getConstant(2, dl, MVT::i64));
15912 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15913 MachinePointerInfo(TrmpAddr, 2),
15916 // Load the 'nest' parameter value into R10.
15917 // R10 is specified in X86CallingConv.td
15918 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15919 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15920 DAG.getConstant(10, dl, MVT::i64));
15921 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15922 Addr, MachinePointerInfo(TrmpAddr, 10),
15925 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15926 DAG.getConstant(12, dl, MVT::i64));
15927 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15928 MachinePointerInfo(TrmpAddr, 12),
15931 // Jump to the nested function.
15932 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15933 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15934 DAG.getConstant(20, dl, MVT::i64));
15935 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15936 Addr, MachinePointerInfo(TrmpAddr, 20),
15939 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15940 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15941 DAG.getConstant(22, dl, MVT::i64));
15942 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15943 Addr, MachinePointerInfo(TrmpAddr, 22),
15946 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15948 const Function *Func =
15949 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15950 CallingConv::ID CC = Func->getCallingConv();
15955 llvm_unreachable("Unsupported calling convention");
15956 case CallingConv::C:
15957 case CallingConv::X86_StdCall: {
15958 // Pass 'nest' parameter in ECX.
15959 // Must be kept in sync with X86CallingConv.td
15960 NestReg = X86::ECX;
15962 // Check that ECX wasn't needed by an 'inreg' parameter.
15963 FunctionType *FTy = Func->getFunctionType();
15964 const AttributeSet &Attrs = Func->getAttributes();
15966 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15967 unsigned InRegCount = 0;
15970 for (FunctionType::param_iterator I = FTy->param_begin(),
15971 E = FTy->param_end(); I != E; ++I, ++Idx)
15972 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15973 // FIXME: should only count parameters that are lowered to integers.
15974 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15976 if (InRegCount > 2) {
15977 report_fatal_error("Nest register in use - reduce number of inreg"
15983 case CallingConv::X86_FastCall:
15984 case CallingConv::X86_ThisCall:
15985 case CallingConv::Fast:
15986 // Pass 'nest' parameter in EAX.
15987 // Must be kept in sync with X86CallingConv.td
15988 NestReg = X86::EAX;
15992 SDValue OutChains[4];
15993 SDValue Addr, Disp;
15995 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15996 DAG.getConstant(10, dl, MVT::i32));
15997 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15999 // This is storing the opcode for MOV32ri.
16000 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16001 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16002 OutChains[0] = DAG.getStore(Root, dl,
16003 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16004 Trmp, MachinePointerInfo(TrmpAddr),
16007 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16008 DAG.getConstant(1, dl, MVT::i32));
16009 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16010 MachinePointerInfo(TrmpAddr, 1),
16013 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16014 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16015 DAG.getConstant(5, dl, MVT::i32));
16016 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16017 Addr, MachinePointerInfo(TrmpAddr, 5),
16020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16021 DAG.getConstant(6, dl, MVT::i32));
16022 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16023 MachinePointerInfo(TrmpAddr, 6),
16026 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16030 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16031 SelectionDAG &DAG) const {
16033 The rounding mode is in bits 11:10 of FPSR, and has the following
16035 00 Round to nearest
16040 FLT_ROUNDS, on the other hand, expects the following:
16047 To perform the conversion, we do:
16048 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16051 MachineFunction &MF = DAG.getMachineFunction();
16052 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16053 unsigned StackAlignment = TFI.getStackAlignment();
16054 MVT VT = Op.getSimpleValueType();
16057 // Save FP Control Word to stack slot
16058 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16059 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16061 MachineMemOperand *MMO =
16062 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16063 MachineMemOperand::MOStore, 2, 2);
16065 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16066 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16067 DAG.getVTList(MVT::Other),
16068 Ops, MVT::i16, MMO);
16070 // Load FP Control Word from stack slot
16071 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16072 MachinePointerInfo(), false, false, false, 0);
16074 // Transform as necessary
16076 DAG.getNode(ISD::SRL, DL, MVT::i16,
16077 DAG.getNode(ISD::AND, DL, MVT::i16,
16078 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16079 DAG.getConstant(11, DL, MVT::i8));
16081 DAG.getNode(ISD::SRL, DL, MVT::i16,
16082 DAG.getNode(ISD::AND, DL, MVT::i16,
16083 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16084 DAG.getConstant(9, DL, MVT::i8));
16087 DAG.getNode(ISD::AND, DL, MVT::i16,
16088 DAG.getNode(ISD::ADD, DL, MVT::i16,
16089 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16090 DAG.getConstant(1, DL, MVT::i16)),
16091 DAG.getConstant(3, DL, MVT::i16));
16093 return DAG.getNode((VT.getSizeInBits() < 16 ?
16094 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16097 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16098 MVT VT = Op.getSimpleValueType();
16100 unsigned NumBits = VT.getSizeInBits();
16103 Op = Op.getOperand(0);
16104 if (VT == MVT::i8) {
16105 // Zero extend to i32 since there is not an i8 bsr.
16107 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16110 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16111 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16112 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16114 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16117 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16118 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16121 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16123 // Finally xor with NumBits-1.
16124 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16125 DAG.getConstant(NumBits - 1, dl, OpVT));
16128 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16132 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16133 MVT VT = Op.getSimpleValueType();
16135 unsigned NumBits = VT.getSizeInBits();
16138 Op = Op.getOperand(0);
16139 if (VT == MVT::i8) {
16140 // Zero extend to i32 since there is not an i8 bsr.
16142 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16145 // Issue a bsr (scan bits in reverse).
16146 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16147 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16149 // And xor with NumBits-1.
16150 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16151 DAG.getConstant(NumBits - 1, dl, OpVT));
16154 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16158 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16159 MVT VT = Op.getSimpleValueType();
16160 unsigned NumBits = VT.getSizeInBits();
16162 Op = Op.getOperand(0);
16164 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16165 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16166 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16168 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16171 DAG.getConstant(NumBits, dl, VT),
16172 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16175 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16178 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16179 // ones, and then concatenate the result back.
16180 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16181 MVT VT = Op.getSimpleValueType();
16183 assert(VT.is256BitVector() && VT.isInteger() &&
16184 "Unsupported value type for operation");
16186 unsigned NumElems = VT.getVectorNumElements();
16189 // Extract the LHS vectors
16190 SDValue LHS = Op.getOperand(0);
16191 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16192 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16194 // Extract the RHS vectors
16195 SDValue RHS = Op.getOperand(1);
16196 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16197 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16199 MVT EltVT = VT.getVectorElementType();
16200 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16202 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16203 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16204 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16207 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16208 if (Op.getValueType() == MVT::i1)
16209 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16210 Op.getOperand(0), Op.getOperand(1));
16211 assert(Op.getSimpleValueType().is256BitVector() &&
16212 Op.getSimpleValueType().isInteger() &&
16213 "Only handle AVX 256-bit vector integer operation");
16214 return Lower256IntArith(Op, DAG);
16217 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16218 if (Op.getValueType() == MVT::i1)
16219 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16220 Op.getOperand(0), Op.getOperand(1));
16221 assert(Op.getSimpleValueType().is256BitVector() &&
16222 Op.getSimpleValueType().isInteger() &&
16223 "Only handle AVX 256-bit vector integer operation");
16224 return Lower256IntArith(Op, DAG);
16227 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16228 SelectionDAG &DAG) {
16230 MVT VT = Op.getSimpleValueType();
16233 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16235 // Decompose 256-bit ops into smaller 128-bit ops.
16236 if (VT.is256BitVector() && !Subtarget->hasInt256())
16237 return Lower256IntArith(Op, DAG);
16239 SDValue A = Op.getOperand(0);
16240 SDValue B = Op.getOperand(1);
16242 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16243 // pairs, multiply and truncate.
16244 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16245 if (Subtarget->hasInt256()) {
16246 if (VT == MVT::v32i8) {
16247 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16248 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16249 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16250 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16251 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16252 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16253 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16254 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16255 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16256 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16259 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16260 return DAG.getNode(
16261 ISD::TRUNCATE, dl, VT,
16262 DAG.getNode(ISD::MUL, dl, ExVT,
16263 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16264 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16267 assert(VT == MVT::v16i8 &&
16268 "Pre-AVX2 support only supports v16i8 multiplication");
16269 MVT ExVT = MVT::v8i16;
16271 // Extract the lo parts and sign extend to i16
16273 if (Subtarget->hasSSE41()) {
16274 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16275 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16277 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16278 -1, 4, -1, 5, -1, 6, -1, 7};
16279 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16280 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16281 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16282 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16283 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16284 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16287 // Extract the hi parts and sign extend to i16
16289 if (Subtarget->hasSSE41()) {
16290 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16291 -1, -1, -1, -1, -1, -1, -1, -1};
16292 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16293 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16294 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16295 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16297 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16298 -1, 12, -1, 13, -1, 14, -1, 15};
16299 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16300 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16301 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16302 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16303 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16304 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16307 // Multiply, mask the lower 8bits of the lo/hi results and pack
16308 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16309 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16310 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16311 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16312 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16315 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16316 if (VT == MVT::v4i32) {
16317 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16318 "Should not custom lower when pmuldq is available!");
16320 // Extract the odd parts.
16321 static const int UnpackMask[] = { 1, -1, 3, -1 };
16322 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16323 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16325 // Multiply the even parts.
16326 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16327 // Now multiply odd parts.
16328 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16330 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16331 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16333 // Merge the two vectors back together with a shuffle. This expands into 2
16335 static const int ShufMask[] = { 0, 4, 2, 6 };
16336 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16339 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16340 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16342 // Ahi = psrlqi(a, 32);
16343 // Bhi = psrlqi(b, 32);
16345 // AloBlo = pmuludq(a, b);
16346 // AloBhi = pmuludq(a, Bhi);
16347 // AhiBlo = pmuludq(Ahi, b);
16349 // AloBhi = psllqi(AloBhi, 32);
16350 // AhiBlo = psllqi(AhiBlo, 32);
16351 // return AloBlo + AloBhi + AhiBlo;
16353 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16354 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16356 // Bit cast to 32-bit vectors for MULUDQ
16357 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16358 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16359 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16360 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16361 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16362 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16364 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16365 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16366 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16368 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16369 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16371 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16372 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16375 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16376 assert(Subtarget->isTargetWin64() && "Unexpected target");
16377 EVT VT = Op.getValueType();
16378 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16379 "Unexpected return type for lowering");
16383 switch (Op->getOpcode()) {
16384 default: llvm_unreachable("Unexpected request for libcall!");
16385 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16386 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16387 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16388 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16389 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16390 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16394 SDValue InChain = DAG.getEntryNode();
16396 TargetLowering::ArgListTy Args;
16397 TargetLowering::ArgListEntry Entry;
16398 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16399 EVT ArgVT = Op->getOperand(i).getValueType();
16400 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16401 "Unexpected argument type for lowering");
16402 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16403 Entry.Node = StackPtr;
16404 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16406 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16407 Entry.Ty = PointerType::get(ArgTy,0);
16408 Entry.isSExt = false;
16409 Entry.isZExt = false;
16410 Args.push_back(Entry);
16413 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16416 TargetLowering::CallLoweringInfo CLI(DAG);
16417 CLI.setDebugLoc(dl).setChain(InChain)
16418 .setCallee(getLibcallCallingConv(LC),
16419 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16420 Callee, std::move(Args), 0)
16421 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16423 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16424 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16427 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16428 SelectionDAG &DAG) {
16429 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16430 EVT VT = Op0.getValueType();
16433 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16434 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16436 // PMULxD operations multiply each even value (starting at 0) of LHS with
16437 // the related value of RHS and produce a widen result.
16438 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16439 // => <2 x i64> <ae|cg>
16441 // In other word, to have all the results, we need to perform two PMULxD:
16442 // 1. one with the even values.
16443 // 2. one with the odd values.
16444 // To achieve #2, with need to place the odd values at an even position.
16446 // Place the odd value at an even position (basically, shift all values 1
16447 // step to the left):
16448 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16449 // <a|b|c|d> => <b|undef|d|undef>
16450 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16451 // <e|f|g|h> => <f|undef|h|undef>
16452 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16454 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16456 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16457 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16459 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16460 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16461 // => <2 x i64> <ae|cg>
16462 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16463 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16464 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16465 // => <2 x i64> <bf|dh>
16466 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16467 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16469 // Shuffle it back into the right order.
16470 SDValue Highs, Lows;
16471 if (VT == MVT::v8i32) {
16472 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16473 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16474 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16475 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16477 const int HighMask[] = {1, 5, 3, 7};
16478 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16479 const int LowMask[] = {0, 4, 2, 6};
16480 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16483 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16484 // unsigned multiply.
16485 if (IsSigned && !Subtarget->hasSSE41()) {
16487 DAG.getConstant(31, dl,
16488 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16489 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16490 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16491 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16492 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16494 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16495 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16498 // The first result of MUL_LOHI is actually the low value, followed by the
16500 SDValue Ops[] = {Lows, Highs};
16501 return DAG.getMergeValues(Ops, dl);
16504 // Return true if the requred (according to Opcode) shift-imm form is natively
16505 // supported by the Subtarget
16506 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16508 if (VT.getScalarSizeInBits() < 16)
16511 if (VT.is512BitVector() &&
16512 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16515 bool LShift = VT.is128BitVector() ||
16516 (VT.is256BitVector() && Subtarget->hasInt256());
16518 bool AShift = LShift && (Subtarget->hasVLX() ||
16519 (VT != MVT::v2i64 && VT != MVT::v4i64));
16520 return (Opcode == ISD::SRA) ? AShift : LShift;
16523 // The shift amount is a variable, but it is the same for all vector lanes.
16524 // These instrcutions are defined together with shift-immediate.
16526 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16528 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16531 // Return true if the requred (according to Opcode) variable-shift form is
16532 // natively supported by the Subtarget
16533 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16536 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16539 // vXi16 supported only on AVX-512, BWI
16540 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16543 if (VT.is512BitVector() || Subtarget->hasVLX())
16546 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16547 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16548 return (Opcode == ISD::SRA) ? AShift : LShift;
16551 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16552 const X86Subtarget *Subtarget) {
16553 MVT VT = Op.getSimpleValueType();
16555 SDValue R = Op.getOperand(0);
16556 SDValue Amt = Op.getOperand(1);
16558 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16559 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16561 // Optimize shl/srl/sra with constant shift amount.
16562 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16563 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16564 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16566 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16567 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16569 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16570 unsigned NumElts = VT.getVectorNumElements();
16571 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16573 if (Op.getOpcode() == ISD::SHL) {
16574 // Simple i8 add case
16576 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16578 // Make a large shift.
16579 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16581 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16582 // Zero out the rightmost bits.
16583 SmallVector<SDValue, 32> V(
16584 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16585 return DAG.getNode(ISD::AND, dl, VT, SHL,
16586 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16588 if (Op.getOpcode() == ISD::SRL) {
16589 // Make a large shift.
16590 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16592 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16593 // Zero out the leftmost bits.
16594 SmallVector<SDValue, 32> V(
16595 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16596 return DAG.getNode(ISD::AND, dl, VT, SRL,
16597 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16599 if (Op.getOpcode() == ISD::SRA) {
16600 if (ShiftAmt == 7) {
16601 // R s>> 7 === R s< 0
16602 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16603 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16606 // R s>> a === ((R u>> a) ^ m) - m
16607 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16608 SmallVector<SDValue, 32> V(NumElts,
16609 DAG.getConstant(128 >> ShiftAmt, dl,
16611 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16612 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16613 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16616 llvm_unreachable("Unknown shift opcode.");
16621 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16622 if (!Subtarget->is64Bit() &&
16623 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16624 Amt.getOpcode() == ISD::BITCAST &&
16625 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16626 Amt = Amt.getOperand(0);
16627 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16628 VT.getVectorNumElements();
16629 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16630 uint64_t ShiftAmt = 0;
16631 for (unsigned i = 0; i != Ratio; ++i) {
16632 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16636 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16638 // Check remaining shift amounts.
16639 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16640 uint64_t ShAmt = 0;
16641 for (unsigned j = 0; j != Ratio; ++j) {
16642 ConstantSDNode *C =
16643 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16647 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16649 if (ShAmt != ShiftAmt)
16652 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16658 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16659 const X86Subtarget* Subtarget) {
16660 MVT VT = Op.getSimpleValueType();
16662 SDValue R = Op.getOperand(0);
16663 SDValue Amt = Op.getOperand(1);
16665 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16666 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16668 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16669 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16671 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16673 EVT EltVT = VT.getVectorElementType();
16675 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16676 // Check if this build_vector node is doing a splat.
16677 // If so, then set BaseShAmt equal to the splat value.
16678 BaseShAmt = BV->getSplatValue();
16679 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16680 BaseShAmt = SDValue();
16682 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16683 Amt = Amt.getOperand(0);
16685 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16686 if (SVN && SVN->isSplat()) {
16687 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16688 SDValue InVec = Amt.getOperand(0);
16689 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16690 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16691 "Unexpected shuffle index found!");
16692 BaseShAmt = InVec.getOperand(SplatIdx);
16693 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16694 if (ConstantSDNode *C =
16695 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16696 if (C->getZExtValue() == SplatIdx)
16697 BaseShAmt = InVec.getOperand(1);
16702 // Avoid introducing an extract element from a shuffle.
16703 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16704 DAG.getIntPtrConstant(SplatIdx, dl));
16708 if (BaseShAmt.getNode()) {
16709 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16710 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16711 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16712 else if (EltVT.bitsLT(MVT::i32))
16713 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16715 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16719 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16720 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16721 Amt.getOpcode() == ISD::BITCAST &&
16722 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16723 Amt = Amt.getOperand(0);
16724 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16725 VT.getVectorNumElements();
16726 std::vector<SDValue> Vals(Ratio);
16727 for (unsigned i = 0; i != Ratio; ++i)
16728 Vals[i] = Amt.getOperand(i);
16729 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16730 for (unsigned j = 0; j != Ratio; ++j)
16731 if (Vals[j] != Amt.getOperand(i + j))
16734 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16739 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16740 SelectionDAG &DAG) {
16741 MVT VT = Op.getSimpleValueType();
16743 SDValue R = Op.getOperand(0);
16744 SDValue Amt = Op.getOperand(1);
16746 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16747 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16749 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16752 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16755 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16758 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16759 // shifts per-lane and then shuffle the partial results back together.
16760 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16761 // Splat the shift amounts so the scalar shifts above will catch it.
16762 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16763 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16764 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16765 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16766 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16769 // If possible, lower this packed shift into a vector multiply instead of
16770 // expanding it into a sequence of scalar shifts.
16771 // Do this only if the vector shift count is a constant build_vector.
16772 if (Op.getOpcode() == ISD::SHL &&
16773 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16774 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16775 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16776 SmallVector<SDValue, 8> Elts;
16777 EVT SVT = VT.getScalarType();
16778 unsigned SVTBits = SVT.getSizeInBits();
16779 const APInt &One = APInt(SVTBits, 1);
16780 unsigned NumElems = VT.getVectorNumElements();
16782 for (unsigned i=0; i !=NumElems; ++i) {
16783 SDValue Op = Amt->getOperand(i);
16784 if (Op->getOpcode() == ISD::UNDEF) {
16785 Elts.push_back(Op);
16789 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16790 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16791 uint64_t ShAmt = C.getZExtValue();
16792 if (ShAmt >= SVTBits) {
16793 Elts.push_back(DAG.getUNDEF(SVT));
16796 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16798 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16799 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16802 // Lower SHL with variable shift amount.
16803 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16804 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16806 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16807 DAG.getConstant(0x3f800000U, dl, VT));
16808 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16809 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16810 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16813 // If possible, lower this shift as a sequence of two shifts by
16814 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16816 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16818 // Could be rewritten as:
16819 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16821 // The advantage is that the two shifts from the example would be
16822 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16823 // the vector shift into four scalar shifts plus four pairs of vector
16825 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16826 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16827 unsigned TargetOpcode = X86ISD::MOVSS;
16828 bool CanBeSimplified;
16829 // The splat value for the first packed shift (the 'X' from the example).
16830 SDValue Amt1 = Amt->getOperand(0);
16831 // The splat value for the second packed shift (the 'Y' from the example).
16832 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16833 Amt->getOperand(2);
16835 // See if it is possible to replace this node with a sequence of
16836 // two shifts followed by a MOVSS/MOVSD
16837 if (VT == MVT::v4i32) {
16838 // Check if it is legal to use a MOVSS.
16839 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16840 Amt2 == Amt->getOperand(3);
16841 if (!CanBeSimplified) {
16842 // Otherwise, check if we can still simplify this node using a MOVSD.
16843 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16844 Amt->getOperand(2) == Amt->getOperand(3);
16845 TargetOpcode = X86ISD::MOVSD;
16846 Amt2 = Amt->getOperand(2);
16849 // Do similar checks for the case where the machine value type
16851 CanBeSimplified = Amt1 == Amt->getOperand(1);
16852 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16853 CanBeSimplified = Amt2 == Amt->getOperand(i);
16855 if (!CanBeSimplified) {
16856 TargetOpcode = X86ISD::MOVSD;
16857 CanBeSimplified = true;
16858 Amt2 = Amt->getOperand(4);
16859 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16860 CanBeSimplified = Amt1 == Amt->getOperand(i);
16861 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16862 CanBeSimplified = Amt2 == Amt->getOperand(j);
16866 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16867 isa<ConstantSDNode>(Amt2)) {
16868 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16869 EVT CastVT = MVT::v4i32;
16871 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16872 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16874 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16875 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16876 if (TargetOpcode == X86ISD::MOVSD)
16877 CastVT = MVT::v2i64;
16878 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16879 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16880 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16882 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16886 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16887 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16888 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16890 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16891 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16892 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16894 // r = VSELECT(r, shl(r, 4), a);
16895 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16896 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16899 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16900 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16901 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16903 // r = VSELECT(r, shl(r, 2), a);
16904 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16905 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16908 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16909 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16910 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16912 // return VSELECT(r, r+r, a);
16913 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16914 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16918 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16919 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16920 // solution better.
16921 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16922 MVT ExtVT = MVT::v8i32;
16924 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16925 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
16926 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
16927 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16928 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
16931 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
16932 MVT ExtVT = MVT::v8i32;
16933 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
16934 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
16935 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
16936 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
16937 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
16938 ALo = DAG.getNode(ISD::BITCAST, dl, ExtVT, ALo);
16939 AHi = DAG.getNode(ISD::BITCAST, dl, ExtVT, AHi);
16940 RLo = DAG.getNode(ISD::BITCAST, dl, ExtVT, RLo);
16941 RHi = DAG.getNode(ISD::BITCAST, dl, ExtVT, RHi);
16942 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
16943 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
16944 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
16945 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
16946 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
16949 // Decompose 256-bit shifts into smaller 128-bit shifts.
16950 if (VT.is256BitVector()) {
16951 unsigned NumElems = VT.getVectorNumElements();
16952 MVT EltVT = VT.getVectorElementType();
16953 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16955 // Extract the two vectors
16956 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16957 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16959 // Recreate the shift amount vectors
16960 SDValue Amt1, Amt2;
16961 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16962 // Constant shift amount
16963 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16964 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16965 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16967 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16968 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16970 // Variable shift amount
16971 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16972 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16975 // Issue new vector shifts for the smaller types
16976 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16977 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16979 // Concatenate the result back
16980 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16986 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16987 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16988 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16989 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16990 // has only one use.
16991 SDNode *N = Op.getNode();
16992 SDValue LHS = N->getOperand(0);
16993 SDValue RHS = N->getOperand(1);
16994 unsigned BaseOp = 0;
16997 switch (Op.getOpcode()) {
16998 default: llvm_unreachable("Unknown ovf instruction!");
17000 // A subtract of one will be selected as a INC. Note that INC doesn't
17001 // set CF, so we can't do this for UADDO.
17002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17004 BaseOp = X86ISD::INC;
17005 Cond = X86::COND_O;
17008 BaseOp = X86ISD::ADD;
17009 Cond = X86::COND_O;
17012 BaseOp = X86ISD::ADD;
17013 Cond = X86::COND_B;
17016 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17017 // set CF, so we can't do this for USUBO.
17018 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17020 BaseOp = X86ISD::DEC;
17021 Cond = X86::COND_O;
17024 BaseOp = X86ISD::SUB;
17025 Cond = X86::COND_O;
17028 BaseOp = X86ISD::SUB;
17029 Cond = X86::COND_B;
17032 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17033 Cond = X86::COND_O;
17035 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17036 if (N->getValueType(0) == MVT::i8) {
17037 BaseOp = X86ISD::UMUL8;
17038 Cond = X86::COND_O;
17041 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17043 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17046 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17047 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17048 SDValue(Sum.getNode(), 2));
17050 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17054 // Also sets EFLAGS.
17055 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17056 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17059 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17060 DAG.getConstant(Cond, DL, MVT::i32),
17061 SDValue(Sum.getNode(), 1));
17063 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17066 /// Returns true if the operand type is exactly twice the native width, and
17067 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17068 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17069 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17070 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17071 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17074 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17075 else if (OpWidth == 128)
17076 return Subtarget->hasCmpxchg16b();
17081 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17082 return needsCmpXchgNb(SI->getValueOperand()->getType());
17085 // Note: this turns large loads into lock cmpxchg8b/16b.
17086 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17087 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17088 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17089 return needsCmpXchgNb(PTy->getElementType());
17092 TargetLoweringBase::AtomicRMWExpansionKind
17093 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17094 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17095 const Type *MemType = AI->getType();
17097 // If the operand is too big, we must see if cmpxchg8/16b is available
17098 // and default to library calls otherwise.
17099 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17100 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17101 : AtomicRMWExpansionKind::None;
17104 AtomicRMWInst::BinOp Op = AI->getOperation();
17107 llvm_unreachable("Unknown atomic operation");
17108 case AtomicRMWInst::Xchg:
17109 case AtomicRMWInst::Add:
17110 case AtomicRMWInst::Sub:
17111 // It's better to use xadd, xsub or xchg for these in all cases.
17112 return AtomicRMWExpansionKind::None;
17113 case AtomicRMWInst::Or:
17114 case AtomicRMWInst::And:
17115 case AtomicRMWInst::Xor:
17116 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17117 // prefix to a normal instruction for these operations.
17118 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17119 : AtomicRMWExpansionKind::None;
17120 case AtomicRMWInst::Nand:
17121 case AtomicRMWInst::Max:
17122 case AtomicRMWInst::Min:
17123 case AtomicRMWInst::UMax:
17124 case AtomicRMWInst::UMin:
17125 // These always require a non-trivial set of data operations on x86. We must
17126 // use a cmpxchg loop.
17127 return AtomicRMWExpansionKind::CmpXChg;
17131 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17132 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17133 // no-sse2). There isn't any reason to disable it if the target processor
17135 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17139 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17140 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17141 const Type *MemType = AI->getType();
17142 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17143 // there is no benefit in turning such RMWs into loads, and it is actually
17144 // harmful as it introduces a mfence.
17145 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17148 auto Builder = IRBuilder<>(AI);
17149 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17150 auto SynchScope = AI->getSynchScope();
17151 // We must restrict the ordering to avoid generating loads with Release or
17152 // ReleaseAcquire orderings.
17153 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17154 auto Ptr = AI->getPointerOperand();
17156 // Before the load we need a fence. Here is an example lifted from
17157 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17160 // x.store(1, relaxed);
17161 // r1 = y.fetch_add(0, release);
17163 // y.fetch_add(42, acquire);
17164 // r2 = x.load(relaxed);
17165 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17166 // lowered to just a load without a fence. A mfence flushes the store buffer,
17167 // making the optimization clearly correct.
17168 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17169 // otherwise, we might be able to be more agressive on relaxed idempotent
17170 // rmw. In practice, they do not look useful, so we don't try to be
17171 // especially clever.
17172 if (SynchScope == SingleThread)
17173 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17174 // the IR level, so we must wrap it in an intrinsic.
17177 if (!hasMFENCE(*Subtarget))
17178 // FIXME: it might make sense to use a locked operation here but on a
17179 // different cache-line to prevent cache-line bouncing. In practice it
17180 // is probably a small win, and x86 processors without mfence are rare
17181 // enough that we do not bother.
17185 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17186 Builder.CreateCall(MFence, {});
17188 // Finally we can emit the atomic load.
17189 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17190 AI->getType()->getPrimitiveSizeInBits());
17191 Loaded->setAtomic(Order, SynchScope);
17192 AI->replaceAllUsesWith(Loaded);
17193 AI->eraseFromParent();
17197 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17198 SelectionDAG &DAG) {
17200 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17201 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17202 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17203 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17205 // The only fence that needs an instruction is a sequentially-consistent
17206 // cross-thread fence.
17207 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17208 if (hasMFENCE(*Subtarget))
17209 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17211 SDValue Chain = Op.getOperand(0);
17212 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17214 DAG.getRegister(X86::ESP, MVT::i32), // Base
17215 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17216 DAG.getRegister(0, MVT::i32), // Index
17217 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17218 DAG.getRegister(0, MVT::i32), // Segment.
17222 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17223 return SDValue(Res, 0);
17226 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17227 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17230 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17231 SelectionDAG &DAG) {
17232 MVT T = Op.getSimpleValueType();
17236 switch(T.SimpleTy) {
17237 default: llvm_unreachable("Invalid value type!");
17238 case MVT::i8: Reg = X86::AL; size = 1; break;
17239 case MVT::i16: Reg = X86::AX; size = 2; break;
17240 case MVT::i32: Reg = X86::EAX; size = 4; break;
17242 assert(Subtarget->is64Bit() && "Node not type legal!");
17243 Reg = X86::RAX; size = 8;
17246 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17247 Op.getOperand(2), SDValue());
17248 SDValue Ops[] = { cpIn.getValue(0),
17251 DAG.getTargetConstant(size, DL, MVT::i8),
17252 cpIn.getValue(1) };
17253 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17254 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17255 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17259 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17260 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17261 MVT::i32, cpOut.getValue(2));
17262 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17263 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17266 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17267 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17268 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17272 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17273 SelectionDAG &DAG) {
17274 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17275 MVT DstVT = Op.getSimpleValueType();
17277 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17278 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17279 if (DstVT != MVT::f64)
17280 // This conversion needs to be expanded.
17283 SDValue InVec = Op->getOperand(0);
17285 unsigned NumElts = SrcVT.getVectorNumElements();
17286 EVT SVT = SrcVT.getVectorElementType();
17288 // Widen the vector in input in the case of MVT::v2i32.
17289 // Example: from MVT::v2i32 to MVT::v4i32.
17290 SmallVector<SDValue, 16> Elts;
17291 for (unsigned i = 0, e = NumElts; i != e; ++i)
17292 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17293 DAG.getIntPtrConstant(i, dl)));
17295 // Explicitly mark the extra elements as Undef.
17296 Elts.append(NumElts, DAG.getUNDEF(SVT));
17298 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17299 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17300 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17301 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17302 DAG.getIntPtrConstant(0, dl));
17305 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17306 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17307 assert((DstVT == MVT::i64 ||
17308 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17309 "Unexpected custom BITCAST");
17310 // i64 <=> MMX conversions are Legal.
17311 if (SrcVT==MVT::i64 && DstVT.isVector())
17313 if (DstVT==MVT::i64 && SrcVT.isVector())
17315 // MMX <=> MMX conversions are Legal.
17316 if (SrcVT.isVector() && DstVT.isVector())
17318 // All other conversions need to be expanded.
17322 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17323 const X86Subtarget *Subtarget,
17324 SelectionDAG &DAG) {
17325 EVT VT = Op.getValueType();
17326 MVT EltVT = VT.getVectorElementType().getSimpleVT();
17327 unsigned VecSize = VT.getSizeInBits();
17329 // Implement a lookup table in register by using an algorithm based on:
17330 // http://wm.ite.pl/articles/sse-popcount.html
17332 // The general idea is that every lower byte nibble in the input vector is an
17333 // index into a in-register pre-computed pop count table. We then split up the
17334 // input vector in two new ones: (1) a vector with only the shifted-right
17335 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17336 // masked out higher ones) for each byte. PSHUB is used separately with both
17337 // to index the in-register table. Next, both are added and the result is a
17338 // i8 vector where each element contains the pop count for input byte.
17340 // To obtain the pop count for elements != i8, we follow up with the same
17341 // approach and use additional tricks as described below.
17343 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17344 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17345 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17346 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17348 int NumByteElts = VecSize / 8;
17349 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17350 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17351 SmallVector<SDValue, 16> LUTVec;
17352 for (int i = 0; i < NumByteElts; ++i)
17353 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17354 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17355 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17356 DAG.getConstant(0x0F, DL, MVT::i8));
17357 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17360 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17361 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17362 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17365 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17367 // The input vector is used as the shuffle mask that index elements into the
17368 // LUT. After counting low and high nibbles, add the vector to obtain the
17369 // final pop count per i8 element.
17370 SDValue HighPopCnt =
17371 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17372 SDValue LowPopCnt =
17373 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17374 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17376 if (EltVT == MVT::i8)
17379 // PSADBW instruction horizontally add all bytes and leave the result in i64
17380 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17381 if (EltVT == MVT::i64) {
17382 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17383 PopCnt = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, PopCnt, Zeros);
17384 return DAG.getBitcast(VT, PopCnt);
17387 int NumI64Elts = VecSize / 64;
17388 MVT VecI64VT = MVT::getVectorVT(MVT::i64, NumI64Elts);
17390 if (EltVT == MVT::i32) {
17391 // We unpack the low half and high half into i32s interleaved with zeros so
17392 // that we can use PSADBW to horizontally sum them. The most useful part of
17393 // this is that it lines up the results of two PSADBW instructions to be
17394 // two v2i64 vectors which concatenated are the 4 population counts. We can
17395 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17396 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17397 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, PopCnt, Zeros);
17398 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, PopCnt, Zeros);
17400 // Do the horizontal sums into two v2i64s.
17401 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17402 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17403 DAG.getBitcast(ByteVecVT, Low), Zeros);
17404 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17405 DAG.getBitcast(ByteVecVT, High), Zeros);
17407 // Merge them together.
17408 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17409 PopCnt = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17410 DAG.getBitcast(ShortVecVT, Low),
17411 DAG.getBitcast(ShortVecVT, High));
17413 return DAG.getBitcast(VT, PopCnt);
17416 // To obtain pop count for each i16 element, shuffle the byte pop count to get
17417 // even and odd elements into distinct vectors, add them and zero-extend each
17418 // i8 elemento into i16, i.e.:
17420 // B -> pop count per i8
17421 // W -> pop count per i16
17423 // Y = shuffle B, undef <0, 2, ...>
17424 // Z = shuffle B, undef <1, 3, ...>
17425 // W = zext <... x i8> to <... x i16> (Y + Z)
17427 // Use a byte shuffle mask that matches PSHUFB.
17429 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17430 SDValue Undef = DAG.getUNDEF(ByteVecVT);
17431 SmallVector<int, 32> MaskA, MaskB;
17433 // We can't use PSHUFB across lanes, so do the shuffle and sum inside each
17434 // 128-bit lane, and then collapse the result.
17435 int NumLanes = NumByteElts / 16;
17436 assert(NumByteElts % 16 == 0 && "Must have 16-byte multiple vectors!");
17437 for (int i = 0; i < NumLanes; ++i) {
17438 for (int j = 0; j < 8; ++j) {
17439 MaskA.push_back(i * 16 + j * 2);
17440 MaskB.push_back(i * 16 + (j * 2) + 1);
17442 MaskA.append((size_t)8, -1);
17443 MaskB.append((size_t)8, -1);
17446 SDValue ShuffA = DAG.getVectorShuffle(ByteVecVT, DL, PopCnt, Undef, MaskA);
17447 SDValue ShuffB = DAG.getVectorShuffle(ByteVecVT, DL, PopCnt, Undef, MaskB);
17448 PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, ShuffA, ShuffB);
17450 SmallVector<int, 4> Mask;
17451 for (int i = 0; i < NumLanes; ++i)
17452 Mask.push_back(2 * i);
17453 Mask.append((size_t)NumLanes, -1);
17455 PopCnt = DAG.getBitcast(VecI64VT, PopCnt);
17457 DAG.getVectorShuffle(VecI64VT, DL, PopCnt, DAG.getUNDEF(VecI64VT), Mask);
17458 PopCnt = DAG.getBitcast(ByteVecVT, PopCnt);
17460 // Zero extend i8s into i16 elts
17461 SmallVector<int, 16> ZExtInRegMask;
17462 for (int i = 0; i < NumByteElts / 2; ++i) {
17463 ZExtInRegMask.push_back(i);
17464 ZExtInRegMask.push_back(NumByteElts);
17467 return DAG.getBitcast(
17468 VT, DAG.getVectorShuffle(ByteVecVT, DL, PopCnt,
17469 getZeroVector(ByteVecVT, Subtarget, DAG, DL),
17473 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17474 const X86Subtarget *Subtarget,
17475 SelectionDAG &DAG) {
17476 MVT VT = Op.getSimpleValueType();
17477 assert(VT.is128BitVector() &&
17478 "Only 128-bit vector bitmath lowering supported.");
17480 int VecSize = VT.getSizeInBits();
17481 MVT EltVT = VT.getVectorElementType();
17482 int Len = EltVT.getSizeInBits();
17484 // This is the vectorized version of the "best" algorithm from
17485 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17486 // with a minor tweak to use a series of adds + shifts instead of vector
17487 // multiplications. Implemented for all integer vector types. We only use
17488 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17489 // much faster, even faster than using native popcnt instructions.
17491 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17492 MVT VT = V.getSimpleValueType();
17493 SmallVector<SDValue, 32> Shifters(
17494 VT.getVectorNumElements(),
17495 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
17496 return DAG.getNode(OpCode, DL, VT, V,
17497 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
17499 auto GetMask = [&](SDValue V, APInt Mask) {
17500 MVT VT = V.getSimpleValueType();
17501 SmallVector<SDValue, 32> Masks(
17502 VT.getVectorNumElements(),
17503 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
17504 return DAG.getNode(ISD::AND, DL, VT, V,
17505 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
17508 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
17509 // x86, so set the SRL type to have elements at least i16 wide. This is
17510 // correct because all of our SRLs are followed immediately by a mask anyways
17511 // that handles any bits that sneak into the high bits of the byte elements.
17512 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
17516 // v = v - ((v >> 1) & 0x55555555...)
17518 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
17519 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
17520 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17522 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17523 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
17524 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
17525 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
17526 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17528 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17529 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
17530 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17531 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
17533 // At this point, V contains the byte-wise population count, and we are
17534 // merely doing a horizontal sum if necessary to get the wider element
17537 // FIXME: There is a different lowering strategy above for the horizontal sum
17538 // of byte-wise population counts. This one and that one should be merged,
17539 // using the fastest of the two for each size.
17540 MVT ByteVT = MVT::getVectorVT(MVT::i8, VecSize / 8);
17541 MVT ShiftVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
17542 V = DAG.getBitcast(ByteVT, V);
17543 assert(Len <= 64 && "We don't support element sizes of more than 64 bits!");
17544 assert(isPowerOf2_32(Len) && "Only power of two element sizes supported!");
17545 for (int i = Len; i > 8; i /= 2) {
17546 SDValue Shl = DAG.getBitcast(
17547 ByteVT, GetShift(ISD::SHL, DAG.getBitcast(ShiftVT, V), i / 2));
17548 V = DAG.getNode(ISD::ADD, DL, ByteVT, V, Shl);
17551 // The high byte now contains the sum of the element bytes. Shift it right
17552 // (if needed) to make it the low byte.
17553 V = DAG.getBitcast(VT, V);
17555 V = GetShift(ISD::SRL, V, Len - 8);
17560 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17561 SelectionDAG &DAG) {
17562 MVT VT = Op.getSimpleValueType();
17563 // FIXME: Need to add AVX-512 support here!
17564 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17565 "Unknown CTPOP type to handle");
17566 SDLoc DL(Op.getNode());
17567 SDValue Op0 = Op.getOperand(0);
17569 if (!Subtarget->hasSSSE3()) {
17570 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
17571 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
17572 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17575 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17576 unsigned NumElems = VT.getVectorNumElements();
17578 // Extract each 128-bit vector, compute pop count and concat the result.
17579 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17580 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17582 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17583 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
17584 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
17587 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
17590 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17591 SelectionDAG &DAG) {
17592 assert(Op.getValueType().isVector() &&
17593 "We only do custom lowering for vector population count.");
17594 return LowerVectorCTPOP(Op, Subtarget, DAG);
17597 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17598 SDNode *Node = Op.getNode();
17600 EVT T = Node->getValueType(0);
17601 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17602 DAG.getConstant(0, dl, T), Node->getOperand(2));
17603 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17604 cast<AtomicSDNode>(Node)->getMemoryVT(),
17605 Node->getOperand(0),
17606 Node->getOperand(1), negOp,
17607 cast<AtomicSDNode>(Node)->getMemOperand(),
17608 cast<AtomicSDNode>(Node)->getOrdering(),
17609 cast<AtomicSDNode>(Node)->getSynchScope());
17612 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17613 SDNode *Node = Op.getNode();
17615 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17617 // Convert seq_cst store -> xchg
17618 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17619 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17620 // (The only way to get a 16-byte store is cmpxchg16b)
17621 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17622 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17623 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17624 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17625 cast<AtomicSDNode>(Node)->getMemoryVT(),
17626 Node->getOperand(0),
17627 Node->getOperand(1), Node->getOperand(2),
17628 cast<AtomicSDNode>(Node)->getMemOperand(),
17629 cast<AtomicSDNode>(Node)->getOrdering(),
17630 cast<AtomicSDNode>(Node)->getSynchScope());
17631 return Swap.getValue(1);
17633 // Other atomic stores have a simple pattern.
17637 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17638 EVT VT = Op.getNode()->getSimpleValueType(0);
17640 // Let legalize expand this if it isn't a legal type yet.
17641 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17644 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17647 bool ExtraOp = false;
17648 switch (Op.getOpcode()) {
17649 default: llvm_unreachable("Invalid code");
17650 case ISD::ADDC: Opc = X86ISD::ADD; break;
17651 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17652 case ISD::SUBC: Opc = X86ISD::SUB; break;
17653 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17657 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17659 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17660 Op.getOperand(1), Op.getOperand(2));
17663 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17664 SelectionDAG &DAG) {
17665 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17667 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17668 // which returns the values as { float, float } (in XMM0) or
17669 // { double, double } (which is returned in XMM0, XMM1).
17671 SDValue Arg = Op.getOperand(0);
17672 EVT ArgVT = Arg.getValueType();
17673 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17675 TargetLowering::ArgListTy Args;
17676 TargetLowering::ArgListEntry Entry;
17680 Entry.isSExt = false;
17681 Entry.isZExt = false;
17682 Args.push_back(Entry);
17684 bool isF64 = ArgVT == MVT::f64;
17685 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17686 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17687 // the results are returned via SRet in memory.
17688 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17689 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17690 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17692 Type *RetTy = isF64
17693 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17694 : (Type*)VectorType::get(ArgTy, 4);
17696 TargetLowering::CallLoweringInfo CLI(DAG);
17697 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17698 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17700 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17703 // Returned in xmm0 and xmm1.
17704 return CallResult.first;
17706 // Returned in bits 0:31 and 32:64 xmm0.
17707 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17708 CallResult.first, DAG.getIntPtrConstant(0, dl));
17709 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17710 CallResult.first, DAG.getIntPtrConstant(1, dl));
17711 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17712 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17715 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17716 SelectionDAG &DAG) {
17717 assert(Subtarget->hasAVX512() &&
17718 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17720 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17721 EVT VT = N->getValue().getValueType();
17722 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17725 // X86 scatter kills mask register, so its type should be added to
17726 // the list of return values
17727 if (N->getNumValues() == 1) {
17728 SDValue Index = N->getIndex();
17729 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17730 !Index.getValueType().is512BitVector())
17731 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17733 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17734 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17735 N->getOperand(3), Index };
17737 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17738 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17739 return SDValue(NewScatter.getNode(), 0);
17744 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17745 SelectionDAG &DAG) {
17746 assert(Subtarget->hasAVX512() &&
17747 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17749 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17750 EVT VT = Op.getValueType();
17751 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17754 SDValue Index = N->getIndex();
17755 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17756 !Index.getValueType().is512BitVector()) {
17757 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17758 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17759 N->getOperand(3), Index };
17760 DAG.UpdateNodeOperands(N, Ops);
17765 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17766 SelectionDAG &DAG) const {
17767 // TODO: Eventually, the lowering of these nodes should be informed by or
17768 // deferred to the GC strategy for the function in which they appear. For
17769 // now, however, they must be lowered to something. Since they are logically
17770 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17771 // require special handling for these nodes), lower them as literal NOOPs for
17773 SmallVector<SDValue, 2> Ops;
17775 Ops.push_back(Op.getOperand(0));
17776 if (Op->getGluedNode())
17777 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17780 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17781 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17786 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17787 SelectionDAG &DAG) const {
17788 // TODO: Eventually, the lowering of these nodes should be informed by or
17789 // deferred to the GC strategy for the function in which they appear. For
17790 // now, however, they must be lowered to something. Since they are logically
17791 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17792 // require special handling for these nodes), lower them as literal NOOPs for
17794 SmallVector<SDValue, 2> Ops;
17796 Ops.push_back(Op.getOperand(0));
17797 if (Op->getGluedNode())
17798 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17801 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17802 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17807 /// LowerOperation - Provide custom lowering hooks for some operations.
17809 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17810 switch (Op.getOpcode()) {
17811 default: llvm_unreachable("Should not custom lower this!");
17812 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17813 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17814 return LowerCMP_SWAP(Op, Subtarget, DAG);
17815 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17816 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17817 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17818 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17819 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17820 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17821 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17822 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17823 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17824 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17825 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17826 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17827 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17828 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17829 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17830 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17831 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17832 case ISD::SHL_PARTS:
17833 case ISD::SRA_PARTS:
17834 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17835 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17836 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17837 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17838 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17839 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17840 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17841 case ISD::SIGN_EXTEND_VECTOR_INREG:
17842 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
17843 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17844 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17845 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17846 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17848 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17849 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17850 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17851 case ISD::SETCC: return LowerSETCC(Op, DAG);
17852 case ISD::SELECT: return LowerSELECT(Op, DAG);
17853 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17854 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17855 case ISD::VASTART: return LowerVASTART(Op, DAG);
17856 case ISD::VAARG: return LowerVAARG(Op, DAG);
17857 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17858 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17859 case ISD::INTRINSIC_VOID:
17860 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17861 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17862 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17863 case ISD::FRAME_TO_ARGS_OFFSET:
17864 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17865 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17866 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17867 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17868 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17869 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17870 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17871 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17872 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17873 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17874 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17875 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17876 case ISD::UMUL_LOHI:
17877 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17880 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17886 case ISD::UMULO: return LowerXALUO(Op, DAG);
17887 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17888 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17892 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17893 case ISD::ADD: return LowerADD(Op, DAG);
17894 case ISD::SUB: return LowerSUB(Op, DAG);
17895 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17896 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17897 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17898 case ISD::GC_TRANSITION_START:
17899 return LowerGC_TRANSITION_START(Op, DAG);
17900 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17904 /// ReplaceNodeResults - Replace a node with an illegal result type
17905 /// with a new node built out of custom code.
17906 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17907 SmallVectorImpl<SDValue>&Results,
17908 SelectionDAG &DAG) const {
17910 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17911 switch (N->getOpcode()) {
17913 llvm_unreachable("Do not know how to custom type legalize this operation!");
17914 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17915 case X86ISD::FMINC:
17917 case X86ISD::FMAXC:
17918 case X86ISD::FMAX: {
17919 EVT VT = N->getValueType(0);
17920 if (VT != MVT::v2f32)
17921 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17922 SDValue UNDEF = DAG.getUNDEF(VT);
17923 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17924 N->getOperand(0), UNDEF);
17925 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17926 N->getOperand(1), UNDEF);
17927 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17930 case ISD::SIGN_EXTEND_INREG:
17935 // We don't want to expand or promote these.
17942 case ISD::UDIVREM: {
17943 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17944 Results.push_back(V);
17947 case ISD::FP_TO_SINT:
17948 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
17949 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
17950 if (N->getOperand(0).getValueType() == MVT::f16)
17953 case ISD::FP_TO_UINT: {
17954 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17956 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17959 std::pair<SDValue,SDValue> Vals =
17960 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17961 SDValue FIST = Vals.first, StackSlot = Vals.second;
17962 if (FIST.getNode()) {
17963 EVT VT = N->getValueType(0);
17964 // Return a load from the stack slot.
17965 if (StackSlot.getNode())
17966 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17967 MachinePointerInfo(),
17968 false, false, false, 0));
17970 Results.push_back(FIST);
17974 case ISD::UINT_TO_FP: {
17975 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17976 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17977 N->getValueType(0) != MVT::v2f32)
17979 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17981 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17983 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17984 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17985 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17986 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17987 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17988 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17991 case ISD::FP_ROUND: {
17992 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17994 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17995 Results.push_back(V);
17998 case ISD::FP_EXTEND: {
17999 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18000 // No other ValueType for FP_EXTEND should reach this point.
18001 assert(N->getValueType(0) == MVT::v2f32 &&
18002 "Do not know how to legalize this Node");
18005 case ISD::INTRINSIC_W_CHAIN: {
18006 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18008 default : llvm_unreachable("Do not know how to custom type "
18009 "legalize this intrinsic operation!");
18010 case Intrinsic::x86_rdtsc:
18011 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18013 case Intrinsic::x86_rdtscp:
18014 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18016 case Intrinsic::x86_rdpmc:
18017 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18020 case ISD::READCYCLECOUNTER: {
18021 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18024 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18025 EVT T = N->getValueType(0);
18026 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18027 bool Regs64bit = T == MVT::i128;
18028 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18029 SDValue cpInL, cpInH;
18030 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18031 DAG.getConstant(0, dl, HalfT));
18032 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18033 DAG.getConstant(1, dl, HalfT));
18034 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18035 Regs64bit ? X86::RAX : X86::EAX,
18037 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18038 Regs64bit ? X86::RDX : X86::EDX,
18039 cpInH, cpInL.getValue(1));
18040 SDValue swapInL, swapInH;
18041 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18042 DAG.getConstant(0, dl, HalfT));
18043 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18044 DAG.getConstant(1, dl, HalfT));
18045 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18046 Regs64bit ? X86::RBX : X86::EBX,
18047 swapInL, cpInH.getValue(1));
18048 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18049 Regs64bit ? X86::RCX : X86::ECX,
18050 swapInH, swapInL.getValue(1));
18051 SDValue Ops[] = { swapInH.getValue(0),
18053 swapInH.getValue(1) };
18054 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18055 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18056 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18057 X86ISD::LCMPXCHG8_DAG;
18058 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18059 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18060 Regs64bit ? X86::RAX : X86::EAX,
18061 HalfT, Result.getValue(1));
18062 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18063 Regs64bit ? X86::RDX : X86::EDX,
18064 HalfT, cpOutL.getValue(2));
18065 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18067 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18068 MVT::i32, cpOutH.getValue(2));
18070 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18071 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18072 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18074 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18075 Results.push_back(Success);
18076 Results.push_back(EFLAGS.getValue(1));
18079 case ISD::ATOMIC_SWAP:
18080 case ISD::ATOMIC_LOAD_ADD:
18081 case ISD::ATOMIC_LOAD_SUB:
18082 case ISD::ATOMIC_LOAD_AND:
18083 case ISD::ATOMIC_LOAD_OR:
18084 case ISD::ATOMIC_LOAD_XOR:
18085 case ISD::ATOMIC_LOAD_NAND:
18086 case ISD::ATOMIC_LOAD_MIN:
18087 case ISD::ATOMIC_LOAD_MAX:
18088 case ISD::ATOMIC_LOAD_UMIN:
18089 case ISD::ATOMIC_LOAD_UMAX:
18090 case ISD::ATOMIC_LOAD: {
18091 // Delegate to generic TypeLegalization. Situations we can really handle
18092 // should have already been dealt with by AtomicExpandPass.cpp.
18095 case ISD::BITCAST: {
18096 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18097 EVT DstVT = N->getValueType(0);
18098 EVT SrcVT = N->getOperand(0)->getValueType(0);
18100 if (SrcVT != MVT::f64 ||
18101 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18104 unsigned NumElts = DstVT.getVectorNumElements();
18105 EVT SVT = DstVT.getVectorElementType();
18106 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18107 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18108 MVT::v2f64, N->getOperand(0));
18109 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18111 if (ExperimentalVectorWideningLegalization) {
18112 // If we are legalizing vectors by widening, we already have the desired
18113 // legal vector type, just return it.
18114 Results.push_back(ToVecInt);
18118 SmallVector<SDValue, 8> Elts;
18119 for (unsigned i = 0, e = NumElts; i != e; ++i)
18120 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18121 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18123 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18128 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18129 switch ((X86ISD::NodeType)Opcode) {
18130 case X86ISD::FIRST_NUMBER: break;
18131 case X86ISD::BSF: return "X86ISD::BSF";
18132 case X86ISD::BSR: return "X86ISD::BSR";
18133 case X86ISD::SHLD: return "X86ISD::SHLD";
18134 case X86ISD::SHRD: return "X86ISD::SHRD";
18135 case X86ISD::FAND: return "X86ISD::FAND";
18136 case X86ISD::FANDN: return "X86ISD::FANDN";
18137 case X86ISD::FOR: return "X86ISD::FOR";
18138 case X86ISD::FXOR: return "X86ISD::FXOR";
18139 case X86ISD::FSRL: return "X86ISD::FSRL";
18140 case X86ISD::FILD: return "X86ISD::FILD";
18141 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18142 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18143 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18144 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18145 case X86ISD::FLD: return "X86ISD::FLD";
18146 case X86ISD::FST: return "X86ISD::FST";
18147 case X86ISD::CALL: return "X86ISD::CALL";
18148 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18149 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18150 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18151 case X86ISD::BT: return "X86ISD::BT";
18152 case X86ISD::CMP: return "X86ISD::CMP";
18153 case X86ISD::COMI: return "X86ISD::COMI";
18154 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18155 case X86ISD::CMPM: return "X86ISD::CMPM";
18156 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18157 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18158 case X86ISD::SETCC: return "X86ISD::SETCC";
18159 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18160 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18161 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18162 case X86ISD::CMOV: return "X86ISD::CMOV";
18163 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18164 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18165 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18166 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18167 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18168 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18169 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18170 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18171 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18172 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18173 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18174 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18175 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18176 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18177 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18178 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18179 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18180 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18181 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18182 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18183 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18184 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18185 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18186 case X86ISD::HADD: return "X86ISD::HADD";
18187 case X86ISD::HSUB: return "X86ISD::HSUB";
18188 case X86ISD::FHADD: return "X86ISD::FHADD";
18189 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18190 case X86ISD::UMAX: return "X86ISD::UMAX";
18191 case X86ISD::UMIN: return "X86ISD::UMIN";
18192 case X86ISD::SMAX: return "X86ISD::SMAX";
18193 case X86ISD::SMIN: return "X86ISD::SMIN";
18194 case X86ISD::FMAX: return "X86ISD::FMAX";
18195 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18196 case X86ISD::FMIN: return "X86ISD::FMIN";
18197 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18198 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18199 case X86ISD::FMINC: return "X86ISD::FMINC";
18200 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18201 case X86ISD::FRCP: return "X86ISD::FRCP";
18202 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18203 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18204 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18205 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18206 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18207 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18208 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18209 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18210 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18211 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18212 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18213 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18214 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18215 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18216 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18217 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18218 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18219 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18220 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18221 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18222 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18223 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18224 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18225 case X86ISD::VSHL: return "X86ISD::VSHL";
18226 case X86ISD::VSRL: return "X86ISD::VSRL";
18227 case X86ISD::VSRA: return "X86ISD::VSRA";
18228 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18229 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18230 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18231 case X86ISD::CMPP: return "X86ISD::CMPP";
18232 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18233 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18234 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18235 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18236 case X86ISD::ADD: return "X86ISD::ADD";
18237 case X86ISD::SUB: return "X86ISD::SUB";
18238 case X86ISD::ADC: return "X86ISD::ADC";
18239 case X86ISD::SBB: return "X86ISD::SBB";
18240 case X86ISD::SMUL: return "X86ISD::SMUL";
18241 case X86ISD::UMUL: return "X86ISD::UMUL";
18242 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18243 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18244 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18245 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18246 case X86ISD::INC: return "X86ISD::INC";
18247 case X86ISD::DEC: return "X86ISD::DEC";
18248 case X86ISD::OR: return "X86ISD::OR";
18249 case X86ISD::XOR: return "X86ISD::XOR";
18250 case X86ISD::AND: return "X86ISD::AND";
18251 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18252 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18253 case X86ISD::PTEST: return "X86ISD::PTEST";
18254 case X86ISD::TESTP: return "X86ISD::TESTP";
18255 case X86ISD::TESTM: return "X86ISD::TESTM";
18256 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18257 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18258 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18259 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18260 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18261 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18262 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18263 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18264 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18265 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18266 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18267 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18268 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18269 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18270 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18271 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18272 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18273 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18274 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18275 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18276 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18277 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18278 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18279 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18280 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18281 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18282 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18283 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18284 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18285 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18286 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18287 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18288 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18289 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18290 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18291 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18292 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18293 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18294 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18295 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18296 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18297 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18298 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18299 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18300 case X86ISD::SAHF: return "X86ISD::SAHF";
18301 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18302 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18303 case X86ISD::FMADD: return "X86ISD::FMADD";
18304 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18305 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18306 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18307 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18308 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18309 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18310 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18311 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18312 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18313 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18314 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18315 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18316 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18317 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18318 case X86ISD::XTEST: return "X86ISD::XTEST";
18319 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18320 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18321 case X86ISD::SELECT: return "X86ISD::SELECT";
18322 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18323 case X86ISD::RCP28: return "X86ISD::RCP28";
18324 case X86ISD::EXP2: return "X86ISD::EXP2";
18325 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18326 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18327 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18328 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18329 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18330 case X86ISD::ADDS: return "X86ISD::ADDS";
18331 case X86ISD::SUBS: return "X86ISD::SUBS";
18336 // isLegalAddressingMode - Return true if the addressing mode represented
18337 // by AM is legal for this target, for a load/store of the specified type.
18338 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18340 // X86 supports extremely general addressing modes.
18341 CodeModel::Model M = getTargetMachine().getCodeModel();
18342 Reloc::Model R = getTargetMachine().getRelocationModel();
18344 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18345 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18350 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18352 // If a reference to this global requires an extra load, we can't fold it.
18353 if (isGlobalStubReference(GVFlags))
18356 // If BaseGV requires a register for the PIC base, we cannot also have a
18357 // BaseReg specified.
18358 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18361 // If lower 4G is not available, then we must use rip-relative addressing.
18362 if ((M != CodeModel::Small || R != Reloc::Static) &&
18363 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18367 switch (AM.Scale) {
18373 // These scales always work.
18378 // These scales are formed with basereg+scalereg. Only accept if there is
18383 default: // Other stuff never works.
18390 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18391 unsigned Bits = Ty->getScalarSizeInBits();
18393 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18394 // particularly cheaper than those without.
18398 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18399 // variable shifts just as cheap as scalar ones.
18400 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18403 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18404 // fully general vector.
18408 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18409 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18411 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18412 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18413 return NumBits1 > NumBits2;
18416 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18417 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18420 if (!isTypeLegal(EVT::getEVT(Ty1)))
18423 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18425 // Assuming the caller doesn't have a zeroext or signext return parameter,
18426 // truncation all the way down to i1 is valid.
18430 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18431 return isInt<32>(Imm);
18434 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18435 // Can also use sub to handle negated immediates.
18436 return isInt<32>(Imm);
18439 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18440 if (!VT1.isInteger() || !VT2.isInteger())
18442 unsigned NumBits1 = VT1.getSizeInBits();
18443 unsigned NumBits2 = VT2.getSizeInBits();
18444 return NumBits1 > NumBits2;
18447 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18448 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18449 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18452 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18453 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18454 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18457 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18458 EVT VT1 = Val.getValueType();
18459 if (isZExtFree(VT1, VT2))
18462 if (Val.getOpcode() != ISD::LOAD)
18465 if (!VT1.isSimple() || !VT1.isInteger() ||
18466 !VT2.isSimple() || !VT2.isInteger())
18469 switch (VT1.getSimpleVT().SimpleTy) {
18474 // X86 has 8, 16, and 32-bit zero-extending loads.
18481 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18484 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18485 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18488 VT = VT.getScalarType();
18490 if (!VT.isSimple())
18493 switch (VT.getSimpleVT().SimpleTy) {
18504 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18505 // i16 instructions are longer (0x66 prefix) and potentially slower.
18506 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18509 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18510 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18511 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18512 /// are assumed to be legal.
18514 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18516 if (!VT.isSimple())
18519 // Not for i1 vectors
18520 if (VT.getScalarType() == MVT::i1)
18523 // Very little shuffling can be done for 64-bit vectors right now.
18524 if (VT.getSizeInBits() == 64)
18527 // We only care that the types being shuffled are legal. The lowering can
18528 // handle any possible shuffle mask that results.
18529 return isTypeLegal(VT.getSimpleVT());
18533 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18535 // Just delegate to the generic legality, clear masks aren't special.
18536 return isShuffleMaskLegal(Mask, VT);
18539 //===----------------------------------------------------------------------===//
18540 // X86 Scheduler Hooks
18541 //===----------------------------------------------------------------------===//
18543 /// Utility function to emit xbegin specifying the start of an RTM region.
18544 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18545 const TargetInstrInfo *TII) {
18546 DebugLoc DL = MI->getDebugLoc();
18548 const BasicBlock *BB = MBB->getBasicBlock();
18549 MachineFunction::iterator I = MBB;
18552 // For the v = xbegin(), we generate
18563 MachineBasicBlock *thisMBB = MBB;
18564 MachineFunction *MF = MBB->getParent();
18565 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18566 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18567 MF->insert(I, mainMBB);
18568 MF->insert(I, sinkMBB);
18570 // Transfer the remainder of BB and its successor edges to sinkMBB.
18571 sinkMBB->splice(sinkMBB->begin(), MBB,
18572 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18573 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18577 // # fallthrough to mainMBB
18578 // # abortion to sinkMBB
18579 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18580 thisMBB->addSuccessor(mainMBB);
18581 thisMBB->addSuccessor(sinkMBB);
18585 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18586 mainMBB->addSuccessor(sinkMBB);
18589 // EAX is live into the sinkMBB
18590 sinkMBB->addLiveIn(X86::EAX);
18591 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18592 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18595 MI->eraseFromParent();
18599 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18600 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18601 // in the .td file.
18602 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18603 const TargetInstrInfo *TII) {
18605 switch (MI->getOpcode()) {
18606 default: llvm_unreachable("illegal opcode!");
18607 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18608 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18609 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18610 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18611 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18612 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18613 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18614 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18617 DebugLoc dl = MI->getDebugLoc();
18618 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18620 unsigned NumArgs = MI->getNumOperands();
18621 for (unsigned i = 1; i < NumArgs; ++i) {
18622 MachineOperand &Op = MI->getOperand(i);
18623 if (!(Op.isReg() && Op.isImplicit()))
18624 MIB.addOperand(Op);
18626 if (MI->hasOneMemOperand())
18627 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18629 BuildMI(*BB, MI, dl,
18630 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18631 .addReg(X86::XMM0);
18633 MI->eraseFromParent();
18637 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18638 // defs in an instruction pattern
18639 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18640 const TargetInstrInfo *TII) {
18642 switch (MI->getOpcode()) {
18643 default: llvm_unreachable("illegal opcode!");
18644 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18645 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18646 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18647 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18648 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18649 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18650 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18651 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18654 DebugLoc dl = MI->getDebugLoc();
18655 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18657 unsigned NumArgs = MI->getNumOperands(); // remove the results
18658 for (unsigned i = 1; i < NumArgs; ++i) {
18659 MachineOperand &Op = MI->getOperand(i);
18660 if (!(Op.isReg() && Op.isImplicit()))
18661 MIB.addOperand(Op);
18663 if (MI->hasOneMemOperand())
18664 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18666 BuildMI(*BB, MI, dl,
18667 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18670 MI->eraseFromParent();
18674 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18675 const X86Subtarget *Subtarget) {
18676 DebugLoc dl = MI->getDebugLoc();
18677 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18678 // Address into RAX/EAX, other two args into ECX, EDX.
18679 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18680 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18681 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18682 for (int i = 0; i < X86::AddrNumOperands; ++i)
18683 MIB.addOperand(MI->getOperand(i));
18685 unsigned ValOps = X86::AddrNumOperands;
18686 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18687 .addReg(MI->getOperand(ValOps).getReg());
18688 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18689 .addReg(MI->getOperand(ValOps+1).getReg());
18691 // The instruction doesn't actually take any operands though.
18692 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18694 MI->eraseFromParent(); // The pseudo is gone now.
18698 MachineBasicBlock *
18699 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18700 MachineBasicBlock *MBB) const {
18701 // Emit va_arg instruction on X86-64.
18703 // Operands to this pseudo-instruction:
18704 // 0 ) Output : destination address (reg)
18705 // 1-5) Input : va_list address (addr, i64mem)
18706 // 6 ) ArgSize : Size (in bytes) of vararg type
18707 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18708 // 8 ) Align : Alignment of type
18709 // 9 ) EFLAGS (implicit-def)
18711 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18712 static_assert(X86::AddrNumOperands == 5,
18713 "VAARG_64 assumes 5 address operands");
18715 unsigned DestReg = MI->getOperand(0).getReg();
18716 MachineOperand &Base = MI->getOperand(1);
18717 MachineOperand &Scale = MI->getOperand(2);
18718 MachineOperand &Index = MI->getOperand(3);
18719 MachineOperand &Disp = MI->getOperand(4);
18720 MachineOperand &Segment = MI->getOperand(5);
18721 unsigned ArgSize = MI->getOperand(6).getImm();
18722 unsigned ArgMode = MI->getOperand(7).getImm();
18723 unsigned Align = MI->getOperand(8).getImm();
18725 // Memory Reference
18726 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18727 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18728 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18730 // Machine Information
18731 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18732 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18733 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18734 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18735 DebugLoc DL = MI->getDebugLoc();
18737 // struct va_list {
18740 // i64 overflow_area (address)
18741 // i64 reg_save_area (address)
18743 // sizeof(va_list) = 24
18744 // alignment(va_list) = 8
18746 unsigned TotalNumIntRegs = 6;
18747 unsigned TotalNumXMMRegs = 8;
18748 bool UseGPOffset = (ArgMode == 1);
18749 bool UseFPOffset = (ArgMode == 2);
18750 unsigned MaxOffset = TotalNumIntRegs * 8 +
18751 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18753 /* Align ArgSize to a multiple of 8 */
18754 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18755 bool NeedsAlign = (Align > 8);
18757 MachineBasicBlock *thisMBB = MBB;
18758 MachineBasicBlock *overflowMBB;
18759 MachineBasicBlock *offsetMBB;
18760 MachineBasicBlock *endMBB;
18762 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18763 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18764 unsigned OffsetReg = 0;
18766 if (!UseGPOffset && !UseFPOffset) {
18767 // If we only pull from the overflow region, we don't create a branch.
18768 // We don't need to alter control flow.
18769 OffsetDestReg = 0; // unused
18770 OverflowDestReg = DestReg;
18772 offsetMBB = nullptr;
18773 overflowMBB = thisMBB;
18776 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18777 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18778 // If not, pull from overflow_area. (branch to overflowMBB)
18783 // offsetMBB overflowMBB
18788 // Registers for the PHI in endMBB
18789 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18790 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18792 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18793 MachineFunction *MF = MBB->getParent();
18794 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18795 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18796 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18798 MachineFunction::iterator MBBIter = MBB;
18801 // Insert the new basic blocks
18802 MF->insert(MBBIter, offsetMBB);
18803 MF->insert(MBBIter, overflowMBB);
18804 MF->insert(MBBIter, endMBB);
18806 // Transfer the remainder of MBB and its successor edges to endMBB.
18807 endMBB->splice(endMBB->begin(), thisMBB,
18808 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18809 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18811 // Make offsetMBB and overflowMBB successors of thisMBB
18812 thisMBB->addSuccessor(offsetMBB);
18813 thisMBB->addSuccessor(overflowMBB);
18815 // endMBB is a successor of both offsetMBB and overflowMBB
18816 offsetMBB->addSuccessor(endMBB);
18817 overflowMBB->addSuccessor(endMBB);
18819 // Load the offset value into a register
18820 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18821 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18825 .addDisp(Disp, UseFPOffset ? 4 : 0)
18826 .addOperand(Segment)
18827 .setMemRefs(MMOBegin, MMOEnd);
18829 // Check if there is enough room left to pull this argument.
18830 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18832 .addImm(MaxOffset + 8 - ArgSizeA8);
18834 // Branch to "overflowMBB" if offset >= max
18835 // Fall through to "offsetMBB" otherwise
18836 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18837 .addMBB(overflowMBB);
18840 // In offsetMBB, emit code to use the reg_save_area.
18842 assert(OffsetReg != 0);
18844 // Read the reg_save_area address.
18845 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18846 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18851 .addOperand(Segment)
18852 .setMemRefs(MMOBegin, MMOEnd);
18854 // Zero-extend the offset
18855 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18856 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18859 .addImm(X86::sub_32bit);
18861 // Add the offset to the reg_save_area to get the final address.
18862 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18863 .addReg(OffsetReg64)
18864 .addReg(RegSaveReg);
18866 // Compute the offset for the next argument
18867 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18868 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18870 .addImm(UseFPOffset ? 16 : 8);
18872 // Store it back into the va_list.
18873 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18877 .addDisp(Disp, UseFPOffset ? 4 : 0)
18878 .addOperand(Segment)
18879 .addReg(NextOffsetReg)
18880 .setMemRefs(MMOBegin, MMOEnd);
18883 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18888 // Emit code to use overflow area
18891 // Load the overflow_area address into a register.
18892 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18893 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18898 .addOperand(Segment)
18899 .setMemRefs(MMOBegin, MMOEnd);
18901 // If we need to align it, do so. Otherwise, just copy the address
18902 // to OverflowDestReg.
18904 // Align the overflow address
18905 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18906 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18908 // aligned_addr = (addr + (align-1)) & ~(align-1)
18909 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18910 .addReg(OverflowAddrReg)
18913 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18915 .addImm(~(uint64_t)(Align-1));
18917 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18918 .addReg(OverflowAddrReg);
18921 // Compute the next overflow address after this argument.
18922 // (the overflow address should be kept 8-byte aligned)
18923 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18924 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18925 .addReg(OverflowDestReg)
18926 .addImm(ArgSizeA8);
18928 // Store the new overflow address.
18929 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18934 .addOperand(Segment)
18935 .addReg(NextAddrReg)
18936 .setMemRefs(MMOBegin, MMOEnd);
18938 // If we branched, emit the PHI to the front of endMBB.
18940 BuildMI(*endMBB, endMBB->begin(), DL,
18941 TII->get(X86::PHI), DestReg)
18942 .addReg(OffsetDestReg).addMBB(offsetMBB)
18943 .addReg(OverflowDestReg).addMBB(overflowMBB);
18946 // Erase the pseudo instruction
18947 MI->eraseFromParent();
18952 MachineBasicBlock *
18953 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18955 MachineBasicBlock *MBB) const {
18956 // Emit code to save XMM registers to the stack. The ABI says that the
18957 // number of registers to save is given in %al, so it's theoretically
18958 // possible to do an indirect jump trick to avoid saving all of them,
18959 // however this code takes a simpler approach and just executes all
18960 // of the stores if %al is non-zero. It's less code, and it's probably
18961 // easier on the hardware branch predictor, and stores aren't all that
18962 // expensive anyway.
18964 // Create the new basic blocks. One block contains all the XMM stores,
18965 // and one block is the final destination regardless of whether any
18966 // stores were performed.
18967 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18968 MachineFunction *F = MBB->getParent();
18969 MachineFunction::iterator MBBIter = MBB;
18971 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18972 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18973 F->insert(MBBIter, XMMSaveMBB);
18974 F->insert(MBBIter, EndMBB);
18976 // Transfer the remainder of MBB and its successor edges to EndMBB.
18977 EndMBB->splice(EndMBB->begin(), MBB,
18978 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18979 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18981 // The original block will now fall through to the XMM save block.
18982 MBB->addSuccessor(XMMSaveMBB);
18983 // The XMMSaveMBB will fall through to the end block.
18984 XMMSaveMBB->addSuccessor(EndMBB);
18986 // Now add the instructions.
18987 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18988 DebugLoc DL = MI->getDebugLoc();
18990 unsigned CountReg = MI->getOperand(0).getReg();
18991 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18992 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18994 if (!Subtarget->isTargetWin64()) {
18995 // If %al is 0, branch around the XMM save block.
18996 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18997 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18998 MBB->addSuccessor(EndMBB);
19001 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19002 // that was just emitted, but clearly shouldn't be "saved".
19003 assert((MI->getNumOperands() <= 3 ||
19004 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19005 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19006 && "Expected last argument to be EFLAGS");
19007 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19008 // In the XMM save block, save all the XMM argument registers.
19009 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19010 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19011 MachineMemOperand *MMO =
19012 F->getMachineMemOperand(
19013 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19014 MachineMemOperand::MOStore,
19015 /*Size=*/16, /*Align=*/16);
19016 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19017 .addFrameIndex(RegSaveFrameIndex)
19018 .addImm(/*Scale=*/1)
19019 .addReg(/*IndexReg=*/0)
19020 .addImm(/*Disp=*/Offset)
19021 .addReg(/*Segment=*/0)
19022 .addReg(MI->getOperand(i).getReg())
19023 .addMemOperand(MMO);
19026 MI->eraseFromParent(); // The pseudo instruction is gone now.
19031 // The EFLAGS operand of SelectItr might be missing a kill marker
19032 // because there were multiple uses of EFLAGS, and ISel didn't know
19033 // which to mark. Figure out whether SelectItr should have had a
19034 // kill marker, and set it if it should. Returns the correct kill
19036 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19037 MachineBasicBlock* BB,
19038 const TargetRegisterInfo* TRI) {
19039 // Scan forward through BB for a use/def of EFLAGS.
19040 MachineBasicBlock::iterator miI(std::next(SelectItr));
19041 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19042 const MachineInstr& mi = *miI;
19043 if (mi.readsRegister(X86::EFLAGS))
19045 if (mi.definesRegister(X86::EFLAGS))
19046 break; // Should have kill-flag - update below.
19049 // If we hit the end of the block, check whether EFLAGS is live into a
19051 if (miI == BB->end()) {
19052 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19053 sEnd = BB->succ_end();
19054 sItr != sEnd; ++sItr) {
19055 MachineBasicBlock* succ = *sItr;
19056 if (succ->isLiveIn(X86::EFLAGS))
19061 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19062 // out. SelectMI should have a kill flag on EFLAGS.
19063 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19067 MachineBasicBlock *
19068 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19069 MachineBasicBlock *BB) const {
19070 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19071 DebugLoc DL = MI->getDebugLoc();
19073 // To "insert" a SELECT_CC instruction, we actually have to insert the
19074 // diamond control-flow pattern. The incoming instruction knows the
19075 // destination vreg to set, the condition code register to branch on, the
19076 // true/false values to select between, and a branch opcode to use.
19077 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19078 MachineFunction::iterator It = BB;
19084 // cmpTY ccX, r1, r2
19086 // fallthrough --> copy0MBB
19087 MachineBasicBlock *thisMBB = BB;
19088 MachineFunction *F = BB->getParent();
19090 // We also lower double CMOVs:
19091 // (CMOV (CMOV F, T, cc1), T, cc2)
19092 // to two successives branches. For that, we look for another CMOV as the
19093 // following instruction.
19095 // Without this, we would add a PHI between the two jumps, which ends up
19096 // creating a few copies all around. For instance, for
19098 // (sitofp (zext (fcmp une)))
19100 // we would generate:
19102 // ucomiss %xmm1, %xmm0
19103 // movss <1.0f>, %xmm0
19104 // movaps %xmm0, %xmm1
19106 // xorps %xmm1, %xmm1
19109 // movaps %xmm1, %xmm0
19113 // because this custom-inserter would have generated:
19125 // A: X = ...; Y = ...
19127 // C: Z = PHI [X, A], [Y, B]
19129 // E: PHI [X, C], [Z, D]
19131 // If we lower both CMOVs in a single step, we can instead generate:
19143 // A: X = ...; Y = ...
19145 // E: PHI [X, A], [X, C], [Y, D]
19147 // Which, in our sitofp/fcmp example, gives us something like:
19149 // ucomiss %xmm1, %xmm0
19150 // movss <1.0f>, %xmm0
19153 // xorps %xmm0, %xmm0
19157 MachineInstr *NextCMOV = nullptr;
19158 MachineBasicBlock::iterator NextMIIt =
19159 std::next(MachineBasicBlock::iterator(MI));
19160 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19161 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19162 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19163 NextCMOV = &*NextMIIt;
19165 MachineBasicBlock *jcc1MBB = nullptr;
19167 // If we have a double CMOV, we lower it to two successive branches to
19168 // the same block. EFLAGS is used by both, so mark it as live in the second.
19170 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19171 F->insert(It, jcc1MBB);
19172 jcc1MBB->addLiveIn(X86::EFLAGS);
19175 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19176 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19177 F->insert(It, copy0MBB);
19178 F->insert(It, sinkMBB);
19180 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19181 // live into the sink and copy blocks.
19182 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19184 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19185 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19186 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19187 copy0MBB->addLiveIn(X86::EFLAGS);
19188 sinkMBB->addLiveIn(X86::EFLAGS);
19191 // Transfer the remainder of BB and its successor edges to sinkMBB.
19192 sinkMBB->splice(sinkMBB->begin(), BB,
19193 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19194 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19196 // Add the true and fallthrough blocks as its successors.
19198 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19199 BB->addSuccessor(jcc1MBB);
19201 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19202 // jump to the sinkMBB.
19203 jcc1MBB->addSuccessor(copy0MBB);
19204 jcc1MBB->addSuccessor(sinkMBB);
19206 BB->addSuccessor(copy0MBB);
19209 // The true block target of the first (or only) branch is always sinkMBB.
19210 BB->addSuccessor(sinkMBB);
19212 // Create the conditional branch instruction.
19214 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19215 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19218 unsigned Opc2 = X86::GetCondBranchFromCond(
19219 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19220 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19224 // %FalseValue = ...
19225 // # fallthrough to sinkMBB
19226 copy0MBB->addSuccessor(sinkMBB);
19229 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19231 MachineInstrBuilder MIB =
19232 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19233 MI->getOperand(0).getReg())
19234 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19235 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19237 // If we have a double CMOV, the second Jcc provides the same incoming
19238 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19240 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19241 // Copy the PHI result to the register defined by the second CMOV.
19242 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19243 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19244 .addReg(MI->getOperand(0).getReg());
19245 NextCMOV->eraseFromParent();
19248 MI->eraseFromParent(); // The pseudo instruction is gone now.
19252 MachineBasicBlock *
19253 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19254 MachineBasicBlock *BB) const {
19255 MachineFunction *MF = BB->getParent();
19256 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19257 DebugLoc DL = MI->getDebugLoc();
19258 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19260 assert(MF->shouldSplitStack());
19262 const bool Is64Bit = Subtarget->is64Bit();
19263 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19265 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19266 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19269 // ... [Till the alloca]
19270 // If stacklet is not large enough, jump to mallocMBB
19273 // Allocate by subtracting from RSP
19274 // Jump to continueMBB
19277 // Allocate by call to runtime
19281 // [rest of original BB]
19284 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19285 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19286 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19288 MachineRegisterInfo &MRI = MF->getRegInfo();
19289 const TargetRegisterClass *AddrRegClass =
19290 getRegClassFor(getPointerTy());
19292 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19293 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19294 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19295 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19296 sizeVReg = MI->getOperand(1).getReg(),
19297 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19299 MachineFunction::iterator MBBIter = BB;
19302 MF->insert(MBBIter, bumpMBB);
19303 MF->insert(MBBIter, mallocMBB);
19304 MF->insert(MBBIter, continueMBB);
19306 continueMBB->splice(continueMBB->begin(), BB,
19307 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19308 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19310 // Add code to the main basic block to check if the stack limit has been hit,
19311 // and if so, jump to mallocMBB otherwise to bumpMBB.
19312 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19313 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19314 .addReg(tmpSPVReg).addReg(sizeVReg);
19315 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19316 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19317 .addReg(SPLimitVReg);
19318 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19320 // bumpMBB simply decreases the stack pointer, since we know the current
19321 // stacklet has enough space.
19322 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19323 .addReg(SPLimitVReg);
19324 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19325 .addReg(SPLimitVReg);
19326 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19328 // Calls into a routine in libgcc to allocate more space from the heap.
19329 const uint32_t *RegMask =
19330 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19332 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19334 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19335 .addExternalSymbol("__morestack_allocate_stack_space")
19336 .addRegMask(RegMask)
19337 .addReg(X86::RDI, RegState::Implicit)
19338 .addReg(X86::RAX, RegState::ImplicitDefine);
19339 } else if (Is64Bit) {
19340 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19342 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19343 .addExternalSymbol("__morestack_allocate_stack_space")
19344 .addRegMask(RegMask)
19345 .addReg(X86::EDI, RegState::Implicit)
19346 .addReg(X86::EAX, RegState::ImplicitDefine);
19348 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19350 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19351 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19352 .addExternalSymbol("__morestack_allocate_stack_space")
19353 .addRegMask(RegMask)
19354 .addReg(X86::EAX, RegState::ImplicitDefine);
19358 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19361 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19362 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19363 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19365 // Set up the CFG correctly.
19366 BB->addSuccessor(bumpMBB);
19367 BB->addSuccessor(mallocMBB);
19368 mallocMBB->addSuccessor(continueMBB);
19369 bumpMBB->addSuccessor(continueMBB);
19371 // Take care of the PHI nodes.
19372 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19373 MI->getOperand(0).getReg())
19374 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19375 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19377 // Delete the original pseudo instruction.
19378 MI->eraseFromParent();
19381 return continueMBB;
19384 MachineBasicBlock *
19385 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19386 MachineBasicBlock *BB) const {
19387 DebugLoc DL = MI->getDebugLoc();
19389 assert(!Subtarget->isTargetMachO());
19391 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19393 MI->eraseFromParent(); // The pseudo instruction is gone now.
19397 MachineBasicBlock *
19398 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19399 MachineBasicBlock *BB) const {
19400 // This is pretty easy. We're taking the value that we received from
19401 // our load from the relocation, sticking it in either RDI (x86-64)
19402 // or EAX and doing an indirect call. The return value will then
19403 // be in the normal return register.
19404 MachineFunction *F = BB->getParent();
19405 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19406 DebugLoc DL = MI->getDebugLoc();
19408 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19409 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19411 // Get a register mask for the lowered call.
19412 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19413 // proper register mask.
19414 const uint32_t *RegMask =
19415 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19416 if (Subtarget->is64Bit()) {
19417 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19418 TII->get(X86::MOV64rm), X86::RDI)
19420 .addImm(0).addReg(0)
19421 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19422 MI->getOperand(3).getTargetFlags())
19424 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19425 addDirectMem(MIB, X86::RDI);
19426 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19427 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19428 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19429 TII->get(X86::MOV32rm), X86::EAX)
19431 .addImm(0).addReg(0)
19432 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19433 MI->getOperand(3).getTargetFlags())
19435 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19436 addDirectMem(MIB, X86::EAX);
19437 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19439 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19440 TII->get(X86::MOV32rm), X86::EAX)
19441 .addReg(TII->getGlobalBaseReg(F))
19442 .addImm(0).addReg(0)
19443 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19444 MI->getOperand(3).getTargetFlags())
19446 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19447 addDirectMem(MIB, X86::EAX);
19448 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19451 MI->eraseFromParent(); // The pseudo instruction is gone now.
19455 MachineBasicBlock *
19456 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19457 MachineBasicBlock *MBB) const {
19458 DebugLoc DL = MI->getDebugLoc();
19459 MachineFunction *MF = MBB->getParent();
19460 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19461 MachineRegisterInfo &MRI = MF->getRegInfo();
19463 const BasicBlock *BB = MBB->getBasicBlock();
19464 MachineFunction::iterator I = MBB;
19467 // Memory Reference
19468 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19469 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19472 unsigned MemOpndSlot = 0;
19474 unsigned CurOp = 0;
19476 DstReg = MI->getOperand(CurOp++).getReg();
19477 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19478 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19479 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19480 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19482 MemOpndSlot = CurOp;
19484 MVT PVT = getPointerTy();
19485 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19486 "Invalid Pointer Size!");
19488 // For v = setjmp(buf), we generate
19491 // buf[LabelOffset] = restoreMBB
19492 // SjLjSetup restoreMBB
19498 // v = phi(main, restore)
19501 // if base pointer being used, load it from frame
19504 MachineBasicBlock *thisMBB = MBB;
19505 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19506 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19507 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19508 MF->insert(I, mainMBB);
19509 MF->insert(I, sinkMBB);
19510 MF->push_back(restoreMBB);
19512 MachineInstrBuilder MIB;
19514 // Transfer the remainder of BB and its successor edges to sinkMBB.
19515 sinkMBB->splice(sinkMBB->begin(), MBB,
19516 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19517 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19520 unsigned PtrStoreOpc = 0;
19521 unsigned LabelReg = 0;
19522 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19523 Reloc::Model RM = MF->getTarget().getRelocationModel();
19524 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19525 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19527 // Prepare IP either in reg or imm.
19528 if (!UseImmLabel) {
19529 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19530 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19531 LabelReg = MRI.createVirtualRegister(PtrRC);
19532 if (Subtarget->is64Bit()) {
19533 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19537 .addMBB(restoreMBB)
19540 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19541 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19542 .addReg(XII->getGlobalBaseReg(MF))
19545 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19549 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19551 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19552 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19553 if (i == X86::AddrDisp)
19554 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19556 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19559 MIB.addReg(LabelReg);
19561 MIB.addMBB(restoreMBB);
19562 MIB.setMemRefs(MMOBegin, MMOEnd);
19564 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19565 .addMBB(restoreMBB);
19567 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19568 MIB.addRegMask(RegInfo->getNoPreservedMask());
19569 thisMBB->addSuccessor(mainMBB);
19570 thisMBB->addSuccessor(restoreMBB);
19574 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19575 mainMBB->addSuccessor(sinkMBB);
19578 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19579 TII->get(X86::PHI), DstReg)
19580 .addReg(mainDstReg).addMBB(mainMBB)
19581 .addReg(restoreDstReg).addMBB(restoreMBB);
19584 if (RegInfo->hasBasePointer(*MF)) {
19585 const bool Uses64BitFramePtr =
19586 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19587 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19588 X86FI->setRestoreBasePointer(MF);
19589 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19590 unsigned BasePtr = RegInfo->getBaseRegister();
19591 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19592 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19593 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19594 .setMIFlag(MachineInstr::FrameSetup);
19596 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19597 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19598 restoreMBB->addSuccessor(sinkMBB);
19600 MI->eraseFromParent();
19604 MachineBasicBlock *
19605 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19606 MachineBasicBlock *MBB) const {
19607 DebugLoc DL = MI->getDebugLoc();
19608 MachineFunction *MF = MBB->getParent();
19609 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19610 MachineRegisterInfo &MRI = MF->getRegInfo();
19612 // Memory Reference
19613 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19614 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19616 MVT PVT = getPointerTy();
19617 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19618 "Invalid Pointer Size!");
19620 const TargetRegisterClass *RC =
19621 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19622 unsigned Tmp = MRI.createVirtualRegister(RC);
19623 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19624 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19625 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19626 unsigned SP = RegInfo->getStackRegister();
19628 MachineInstrBuilder MIB;
19630 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19631 const int64_t SPOffset = 2 * PVT.getStoreSize();
19633 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19634 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19637 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19638 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19639 MIB.addOperand(MI->getOperand(i));
19640 MIB.setMemRefs(MMOBegin, MMOEnd);
19642 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19643 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19644 if (i == X86::AddrDisp)
19645 MIB.addDisp(MI->getOperand(i), LabelOffset);
19647 MIB.addOperand(MI->getOperand(i));
19649 MIB.setMemRefs(MMOBegin, MMOEnd);
19651 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19652 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19653 if (i == X86::AddrDisp)
19654 MIB.addDisp(MI->getOperand(i), SPOffset);
19656 MIB.addOperand(MI->getOperand(i));
19658 MIB.setMemRefs(MMOBegin, MMOEnd);
19660 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19662 MI->eraseFromParent();
19666 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19667 // accumulator loops. Writing back to the accumulator allows the coalescer
19668 // to remove extra copies in the loop.
19669 MachineBasicBlock *
19670 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19671 MachineBasicBlock *MBB) const {
19672 MachineOperand &AddendOp = MI->getOperand(3);
19674 // Bail out early if the addend isn't a register - we can't switch these.
19675 if (!AddendOp.isReg())
19678 MachineFunction &MF = *MBB->getParent();
19679 MachineRegisterInfo &MRI = MF.getRegInfo();
19681 // Check whether the addend is defined by a PHI:
19682 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19683 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19684 if (!AddendDef.isPHI())
19687 // Look for the following pattern:
19689 // %addend = phi [%entry, 0], [%loop, %result]
19691 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19695 // %addend = phi [%entry, 0], [%loop, %result]
19697 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19699 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19700 assert(AddendDef.getOperand(i).isReg());
19701 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19702 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19703 if (&PHISrcInst == MI) {
19704 // Found a matching instruction.
19705 unsigned NewFMAOpc = 0;
19706 switch (MI->getOpcode()) {
19707 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19708 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19709 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19710 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19711 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19712 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19713 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19714 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19715 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19716 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19717 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19718 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19719 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19720 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19721 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19722 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19723 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19724 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19725 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19726 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19728 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19729 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19730 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19731 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19732 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19733 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19734 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19735 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19736 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19737 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19738 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19739 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19740 default: llvm_unreachable("Unrecognized FMA variant.");
19743 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19744 MachineInstrBuilder MIB =
19745 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19746 .addOperand(MI->getOperand(0))
19747 .addOperand(MI->getOperand(3))
19748 .addOperand(MI->getOperand(2))
19749 .addOperand(MI->getOperand(1));
19750 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19751 MI->eraseFromParent();
19758 MachineBasicBlock *
19759 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19760 MachineBasicBlock *BB) const {
19761 switch (MI->getOpcode()) {
19762 default: llvm_unreachable("Unexpected instr type to insert");
19763 case X86::TAILJMPd64:
19764 case X86::TAILJMPr64:
19765 case X86::TAILJMPm64:
19766 case X86::TAILJMPd64_REX:
19767 case X86::TAILJMPr64_REX:
19768 case X86::TAILJMPm64_REX:
19769 llvm_unreachable("TAILJMP64 would not be touched here.");
19770 case X86::TCRETURNdi64:
19771 case X86::TCRETURNri64:
19772 case X86::TCRETURNmi64:
19774 case X86::WIN_ALLOCA:
19775 return EmitLoweredWinAlloca(MI, BB);
19776 case X86::SEG_ALLOCA_32:
19777 case X86::SEG_ALLOCA_64:
19778 return EmitLoweredSegAlloca(MI, BB);
19779 case X86::TLSCall_32:
19780 case X86::TLSCall_64:
19781 return EmitLoweredTLSCall(MI, BB);
19782 case X86::CMOV_GR8:
19783 case X86::CMOV_FR32:
19784 case X86::CMOV_FR64:
19785 case X86::CMOV_V4F32:
19786 case X86::CMOV_V2F64:
19787 case X86::CMOV_V2I64:
19788 case X86::CMOV_V8F32:
19789 case X86::CMOV_V4F64:
19790 case X86::CMOV_V4I64:
19791 case X86::CMOV_V16F32:
19792 case X86::CMOV_V8F64:
19793 case X86::CMOV_V8I64:
19794 case X86::CMOV_GR16:
19795 case X86::CMOV_GR32:
19796 case X86::CMOV_RFP32:
19797 case X86::CMOV_RFP64:
19798 case X86::CMOV_RFP80:
19799 case X86::CMOV_V8I1:
19800 case X86::CMOV_V16I1:
19801 case X86::CMOV_V32I1:
19802 case X86::CMOV_V64I1:
19803 return EmitLoweredSelect(MI, BB);
19805 case X86::FP32_TO_INT16_IN_MEM:
19806 case X86::FP32_TO_INT32_IN_MEM:
19807 case X86::FP32_TO_INT64_IN_MEM:
19808 case X86::FP64_TO_INT16_IN_MEM:
19809 case X86::FP64_TO_INT32_IN_MEM:
19810 case X86::FP64_TO_INT64_IN_MEM:
19811 case X86::FP80_TO_INT16_IN_MEM:
19812 case X86::FP80_TO_INT32_IN_MEM:
19813 case X86::FP80_TO_INT64_IN_MEM: {
19814 MachineFunction *F = BB->getParent();
19815 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19816 DebugLoc DL = MI->getDebugLoc();
19818 // Change the floating point control register to use "round towards zero"
19819 // mode when truncating to an integer value.
19820 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19821 addFrameReference(BuildMI(*BB, MI, DL,
19822 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19824 // Load the old value of the high byte of the control word...
19826 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19827 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19830 // Set the high part to be round to zero...
19831 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19834 // Reload the modified control word now...
19835 addFrameReference(BuildMI(*BB, MI, DL,
19836 TII->get(X86::FLDCW16m)), CWFrameIdx);
19838 // Restore the memory image of control word to original value
19839 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19842 // Get the X86 opcode to use.
19844 switch (MI->getOpcode()) {
19845 default: llvm_unreachable("illegal opcode!");
19846 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19847 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19848 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19849 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19850 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19851 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19852 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19853 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19854 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19858 MachineOperand &Op = MI->getOperand(0);
19860 AM.BaseType = X86AddressMode::RegBase;
19861 AM.Base.Reg = Op.getReg();
19863 AM.BaseType = X86AddressMode::FrameIndexBase;
19864 AM.Base.FrameIndex = Op.getIndex();
19866 Op = MI->getOperand(1);
19868 AM.Scale = Op.getImm();
19869 Op = MI->getOperand(2);
19871 AM.IndexReg = Op.getImm();
19872 Op = MI->getOperand(3);
19873 if (Op.isGlobal()) {
19874 AM.GV = Op.getGlobal();
19876 AM.Disp = Op.getImm();
19878 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19879 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19881 // Reload the original control word now.
19882 addFrameReference(BuildMI(*BB, MI, DL,
19883 TII->get(X86::FLDCW16m)), CWFrameIdx);
19885 MI->eraseFromParent(); // The pseudo instruction is gone now.
19888 // String/text processing lowering.
19889 case X86::PCMPISTRM128REG:
19890 case X86::VPCMPISTRM128REG:
19891 case X86::PCMPISTRM128MEM:
19892 case X86::VPCMPISTRM128MEM:
19893 case X86::PCMPESTRM128REG:
19894 case X86::VPCMPESTRM128REG:
19895 case X86::PCMPESTRM128MEM:
19896 case X86::VPCMPESTRM128MEM:
19897 assert(Subtarget->hasSSE42() &&
19898 "Target must have SSE4.2 or AVX features enabled");
19899 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19901 // String/text processing lowering.
19902 case X86::PCMPISTRIREG:
19903 case X86::VPCMPISTRIREG:
19904 case X86::PCMPISTRIMEM:
19905 case X86::VPCMPISTRIMEM:
19906 case X86::PCMPESTRIREG:
19907 case X86::VPCMPESTRIREG:
19908 case X86::PCMPESTRIMEM:
19909 case X86::VPCMPESTRIMEM:
19910 assert(Subtarget->hasSSE42() &&
19911 "Target must have SSE4.2 or AVX features enabled");
19912 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19914 // Thread synchronization.
19916 return EmitMonitor(MI, BB, Subtarget);
19920 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19922 case X86::VASTART_SAVE_XMM_REGS:
19923 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19925 case X86::VAARG_64:
19926 return EmitVAARG64WithCustomInserter(MI, BB);
19928 case X86::EH_SjLj_SetJmp32:
19929 case X86::EH_SjLj_SetJmp64:
19930 return emitEHSjLjSetJmp(MI, BB);
19932 case X86::EH_SjLj_LongJmp32:
19933 case X86::EH_SjLj_LongJmp64:
19934 return emitEHSjLjLongJmp(MI, BB);
19936 case TargetOpcode::STATEPOINT:
19937 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19938 // this point in the process. We diverge later.
19939 return emitPatchPoint(MI, BB);
19941 case TargetOpcode::STACKMAP:
19942 case TargetOpcode::PATCHPOINT:
19943 return emitPatchPoint(MI, BB);
19945 case X86::VFMADDPDr213r:
19946 case X86::VFMADDPSr213r:
19947 case X86::VFMADDSDr213r:
19948 case X86::VFMADDSSr213r:
19949 case X86::VFMSUBPDr213r:
19950 case X86::VFMSUBPSr213r:
19951 case X86::VFMSUBSDr213r:
19952 case X86::VFMSUBSSr213r:
19953 case X86::VFNMADDPDr213r:
19954 case X86::VFNMADDPSr213r:
19955 case X86::VFNMADDSDr213r:
19956 case X86::VFNMADDSSr213r:
19957 case X86::VFNMSUBPDr213r:
19958 case X86::VFNMSUBPSr213r:
19959 case X86::VFNMSUBSDr213r:
19960 case X86::VFNMSUBSSr213r:
19961 case X86::VFMADDSUBPDr213r:
19962 case X86::VFMADDSUBPSr213r:
19963 case X86::VFMSUBADDPDr213r:
19964 case X86::VFMSUBADDPSr213r:
19965 case X86::VFMADDPDr213rY:
19966 case X86::VFMADDPSr213rY:
19967 case X86::VFMSUBPDr213rY:
19968 case X86::VFMSUBPSr213rY:
19969 case X86::VFNMADDPDr213rY:
19970 case X86::VFNMADDPSr213rY:
19971 case X86::VFNMSUBPDr213rY:
19972 case X86::VFNMSUBPSr213rY:
19973 case X86::VFMADDSUBPDr213rY:
19974 case X86::VFMADDSUBPSr213rY:
19975 case X86::VFMSUBADDPDr213rY:
19976 case X86::VFMSUBADDPSr213rY:
19977 return emitFMA3Instr(MI, BB);
19981 //===----------------------------------------------------------------------===//
19982 // X86 Optimization Hooks
19983 //===----------------------------------------------------------------------===//
19985 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19988 const SelectionDAG &DAG,
19989 unsigned Depth) const {
19990 unsigned BitWidth = KnownZero.getBitWidth();
19991 unsigned Opc = Op.getOpcode();
19992 assert((Opc >= ISD::BUILTIN_OP_END ||
19993 Opc == ISD::INTRINSIC_WO_CHAIN ||
19994 Opc == ISD::INTRINSIC_W_CHAIN ||
19995 Opc == ISD::INTRINSIC_VOID) &&
19996 "Should use MaskedValueIsZero if you don't know whether Op"
19997 " is a target node!");
19999 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20013 // These nodes' second result is a boolean.
20014 if (Op.getResNo() == 0)
20017 case X86ISD::SETCC:
20018 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20020 case ISD::INTRINSIC_WO_CHAIN: {
20021 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20022 unsigned NumLoBits = 0;
20025 case Intrinsic::x86_sse_movmsk_ps:
20026 case Intrinsic::x86_avx_movmsk_ps_256:
20027 case Intrinsic::x86_sse2_movmsk_pd:
20028 case Intrinsic::x86_avx_movmsk_pd_256:
20029 case Intrinsic::x86_mmx_pmovmskb:
20030 case Intrinsic::x86_sse2_pmovmskb_128:
20031 case Intrinsic::x86_avx2_pmovmskb: {
20032 // High bits of movmskp{s|d}, pmovmskb are known zero.
20034 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20035 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20036 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20037 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20038 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20039 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20040 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20041 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20043 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20052 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20054 const SelectionDAG &,
20055 unsigned Depth) const {
20056 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20057 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20058 return Op.getValueType().getScalarType().getSizeInBits();
20064 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20065 /// node is a GlobalAddress + offset.
20066 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20067 const GlobalValue* &GA,
20068 int64_t &Offset) const {
20069 if (N->getOpcode() == X86ISD::Wrapper) {
20070 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20071 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20072 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20076 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20079 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20080 /// same as extracting the high 128-bit part of 256-bit vector and then
20081 /// inserting the result into the low part of a new 256-bit vector
20082 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20083 EVT VT = SVOp->getValueType(0);
20084 unsigned NumElems = VT.getVectorNumElements();
20086 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20087 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20088 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20089 SVOp->getMaskElt(j) >= 0)
20095 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20096 /// same as extracting the low 128-bit part of 256-bit vector and then
20097 /// inserting the result into the high part of a new 256-bit vector
20098 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20099 EVT VT = SVOp->getValueType(0);
20100 unsigned NumElems = VT.getVectorNumElements();
20102 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20103 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20104 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20105 SVOp->getMaskElt(j) >= 0)
20111 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20112 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20113 TargetLowering::DAGCombinerInfo &DCI,
20114 const X86Subtarget* Subtarget) {
20116 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20117 SDValue V1 = SVOp->getOperand(0);
20118 SDValue V2 = SVOp->getOperand(1);
20119 EVT VT = SVOp->getValueType(0);
20120 unsigned NumElems = VT.getVectorNumElements();
20122 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20123 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20127 // V UNDEF BUILD_VECTOR UNDEF
20129 // CONCAT_VECTOR CONCAT_VECTOR
20132 // RESULT: V + zero extended
20134 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20135 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20136 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20139 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20142 // To match the shuffle mask, the first half of the mask should
20143 // be exactly the first vector, and all the rest a splat with the
20144 // first element of the second one.
20145 for (unsigned i = 0; i != NumElems/2; ++i)
20146 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20147 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20150 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20151 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20152 if (Ld->hasNUsesOfValue(1, 0)) {
20153 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20154 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20156 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20158 Ld->getPointerInfo(),
20159 Ld->getAlignment(),
20160 false/*isVolatile*/, true/*ReadMem*/,
20161 false/*WriteMem*/);
20163 // Make sure the newly-created LOAD is in the same position as Ld in
20164 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20165 // and update uses of Ld's output chain to use the TokenFactor.
20166 if (Ld->hasAnyUseOfValue(1)) {
20167 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20168 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20169 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20170 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20171 SDValue(ResNode.getNode(), 1));
20174 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20178 // Emit a zeroed vector and insert the desired subvector on its
20180 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20181 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20182 return DCI.CombineTo(N, InsV);
20185 //===--------------------------------------------------------------------===//
20186 // Combine some shuffles into subvector extracts and inserts:
20189 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20190 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20191 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20192 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20193 return DCI.CombineTo(N, InsV);
20196 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20197 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20198 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20199 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20200 return DCI.CombineTo(N, InsV);
20206 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20209 /// This is the leaf of the recursive combinine below. When we have found some
20210 /// chain of single-use x86 shuffle instructions and accumulated the combined
20211 /// shuffle mask represented by them, this will try to pattern match that mask
20212 /// into either a single instruction if there is a special purpose instruction
20213 /// for this operation, or into a PSHUFB instruction which is a fully general
20214 /// instruction but should only be used to replace chains over a certain depth.
20215 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20216 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20217 TargetLowering::DAGCombinerInfo &DCI,
20218 const X86Subtarget *Subtarget) {
20219 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20221 // Find the operand that enters the chain. Note that multiple uses are OK
20222 // here, we're not going to remove the operand we find.
20223 SDValue Input = Op.getOperand(0);
20224 while (Input.getOpcode() == ISD::BITCAST)
20225 Input = Input.getOperand(0);
20227 MVT VT = Input.getSimpleValueType();
20228 MVT RootVT = Root.getSimpleValueType();
20231 // Just remove no-op shuffle masks.
20232 if (Mask.size() == 1) {
20233 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20238 // Use the float domain if the operand type is a floating point type.
20239 bool FloatDomain = VT.isFloatingPoint();
20241 // For floating point shuffles, we don't have free copies in the shuffle
20242 // instructions or the ability to load as part of the instruction, so
20243 // canonicalize their shuffles to UNPCK or MOV variants.
20245 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20246 // vectors because it can have a load folded into it that UNPCK cannot. This
20247 // doesn't preclude something switching to the shorter encoding post-RA.
20249 // FIXME: Should teach these routines about AVX vector widths.
20250 if (FloatDomain && VT.getSizeInBits() == 128) {
20251 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20252 bool Lo = Mask.equals({0, 0});
20255 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20256 // is no slower than UNPCKLPD but has the option to fold the input operand
20257 // into even an unaligned memory load.
20258 if (Lo && Subtarget->hasSSE3()) {
20259 Shuffle = X86ISD::MOVDDUP;
20260 ShuffleVT = MVT::v2f64;
20262 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20263 // than the UNPCK variants.
20264 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20265 ShuffleVT = MVT::v4f32;
20267 if (Depth == 1 && Root->getOpcode() == Shuffle)
20268 return false; // Nothing to do!
20269 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20270 DCI.AddToWorklist(Op.getNode());
20271 if (Shuffle == X86ISD::MOVDDUP)
20272 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20274 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20275 DCI.AddToWorklist(Op.getNode());
20276 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20280 if (Subtarget->hasSSE3() &&
20281 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20282 bool Lo = Mask.equals({0, 0, 2, 2});
20283 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20284 MVT ShuffleVT = MVT::v4f32;
20285 if (Depth == 1 && Root->getOpcode() == Shuffle)
20286 return false; // Nothing to do!
20287 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20288 DCI.AddToWorklist(Op.getNode());
20289 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20290 DCI.AddToWorklist(Op.getNode());
20291 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20295 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20296 bool Lo = Mask.equals({0, 0, 1, 1});
20297 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20298 MVT ShuffleVT = MVT::v4f32;
20299 if (Depth == 1 && Root->getOpcode() == Shuffle)
20300 return false; // Nothing to do!
20301 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20302 DCI.AddToWorklist(Op.getNode());
20303 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20304 DCI.AddToWorklist(Op.getNode());
20305 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20311 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20312 // variants as none of these have single-instruction variants that are
20313 // superior to the UNPCK formulation.
20314 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20315 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20316 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20317 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20319 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20320 bool Lo = Mask[0] == 0;
20321 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20322 if (Depth == 1 && Root->getOpcode() == Shuffle)
20323 return false; // Nothing to do!
20325 switch (Mask.size()) {
20327 ShuffleVT = MVT::v8i16;
20330 ShuffleVT = MVT::v16i8;
20333 llvm_unreachable("Impossible mask size!");
20335 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20336 DCI.AddToWorklist(Op.getNode());
20337 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20338 DCI.AddToWorklist(Op.getNode());
20339 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20344 // Don't try to re-form single instruction chains under any circumstances now
20345 // that we've done encoding canonicalization for them.
20349 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20350 // can replace them with a single PSHUFB instruction profitably. Intel's
20351 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20352 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20353 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20354 SmallVector<SDValue, 16> PSHUFBMask;
20355 int NumBytes = VT.getSizeInBits() / 8;
20356 int Ratio = NumBytes / Mask.size();
20357 for (int i = 0; i < NumBytes; ++i) {
20358 if (Mask[i / Ratio] == SM_SentinelUndef) {
20359 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20362 int M = Mask[i / Ratio] != SM_SentinelZero
20363 ? Ratio * Mask[i / Ratio] + i % Ratio
20365 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20367 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20368 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
20369 DCI.AddToWorklist(Op.getNode());
20370 SDValue PSHUFBMaskOp =
20371 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20372 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20373 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20374 DCI.AddToWorklist(Op.getNode());
20375 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20380 // Failed to find any combines.
20384 /// \brief Fully generic combining of x86 shuffle instructions.
20386 /// This should be the last combine run over the x86 shuffle instructions. Once
20387 /// they have been fully optimized, this will recursively consider all chains
20388 /// of single-use shuffle instructions, build a generic model of the cumulative
20389 /// shuffle operation, and check for simpler instructions which implement this
20390 /// operation. We use this primarily for two purposes:
20392 /// 1) Collapse generic shuffles to specialized single instructions when
20393 /// equivalent. In most cases, this is just an encoding size win, but
20394 /// sometimes we will collapse multiple generic shuffles into a single
20395 /// special-purpose shuffle.
20396 /// 2) Look for sequences of shuffle instructions with 3 or more total
20397 /// instructions, and replace them with the slightly more expensive SSSE3
20398 /// PSHUFB instruction if available. We do this as the last combining step
20399 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20400 /// a suitable short sequence of other instructions. The PHUFB will either
20401 /// use a register or have to read from memory and so is slightly (but only
20402 /// slightly) more expensive than the other shuffle instructions.
20404 /// Because this is inherently a quadratic operation (for each shuffle in
20405 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20406 /// This should never be an issue in practice as the shuffle lowering doesn't
20407 /// produce sequences of more than 8 instructions.
20409 /// FIXME: We will currently miss some cases where the redundant shuffling
20410 /// would simplify under the threshold for PSHUFB formation because of
20411 /// combine-ordering. To fix this, we should do the redundant instruction
20412 /// combining in this recursive walk.
20413 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20414 ArrayRef<int> RootMask,
20415 int Depth, bool HasPSHUFB,
20417 TargetLowering::DAGCombinerInfo &DCI,
20418 const X86Subtarget *Subtarget) {
20419 // Bound the depth of our recursive combine because this is ultimately
20420 // quadratic in nature.
20424 // Directly rip through bitcasts to find the underlying operand.
20425 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20426 Op = Op.getOperand(0);
20428 MVT VT = Op.getSimpleValueType();
20429 if (!VT.isVector())
20430 return false; // Bail if we hit a non-vector.
20432 assert(Root.getSimpleValueType().isVector() &&
20433 "Shuffles operate on vector types!");
20434 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20435 "Can only combine shuffles of the same vector register size.");
20437 if (!isTargetShuffle(Op.getOpcode()))
20439 SmallVector<int, 16> OpMask;
20441 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20442 // We only can combine unary shuffles which we can decode the mask for.
20443 if (!HaveMask || !IsUnary)
20446 assert(VT.getVectorNumElements() == OpMask.size() &&
20447 "Different mask size from vector size!");
20448 assert(((RootMask.size() > OpMask.size() &&
20449 RootMask.size() % OpMask.size() == 0) ||
20450 (OpMask.size() > RootMask.size() &&
20451 OpMask.size() % RootMask.size() == 0) ||
20452 OpMask.size() == RootMask.size()) &&
20453 "The smaller number of elements must divide the larger.");
20454 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20455 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20456 assert(((RootRatio == 1 && OpRatio == 1) ||
20457 (RootRatio == 1) != (OpRatio == 1)) &&
20458 "Must not have a ratio for both incoming and op masks!");
20460 SmallVector<int, 16> Mask;
20461 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20463 // Merge this shuffle operation's mask into our accumulated mask. Note that
20464 // this shuffle's mask will be the first applied to the input, followed by the
20465 // root mask to get us all the way to the root value arrangement. The reason
20466 // for this order is that we are recursing up the operation chain.
20467 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20468 int RootIdx = i / RootRatio;
20469 if (RootMask[RootIdx] < 0) {
20470 // This is a zero or undef lane, we're done.
20471 Mask.push_back(RootMask[RootIdx]);
20475 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20476 int OpIdx = RootMaskedIdx / OpRatio;
20477 if (OpMask[OpIdx] < 0) {
20478 // The incoming lanes are zero or undef, it doesn't matter which ones we
20480 Mask.push_back(OpMask[OpIdx]);
20484 // Ok, we have non-zero lanes, map them through.
20485 Mask.push_back(OpMask[OpIdx] * OpRatio +
20486 RootMaskedIdx % OpRatio);
20489 // See if we can recurse into the operand to combine more things.
20490 switch (Op.getOpcode()) {
20491 case X86ISD::PSHUFB:
20493 case X86ISD::PSHUFD:
20494 case X86ISD::PSHUFHW:
20495 case X86ISD::PSHUFLW:
20496 if (Op.getOperand(0).hasOneUse() &&
20497 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20498 HasPSHUFB, DAG, DCI, Subtarget))
20502 case X86ISD::UNPCKL:
20503 case X86ISD::UNPCKH:
20504 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20505 // We can't check for single use, we have to check that this shuffle is the only user.
20506 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20507 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20508 HasPSHUFB, DAG, DCI, Subtarget))
20513 // Minor canonicalization of the accumulated shuffle mask to make it easier
20514 // to match below. All this does is detect masks with squential pairs of
20515 // elements, and shrink them to the half-width mask. It does this in a loop
20516 // so it will reduce the size of the mask to the minimal width mask which
20517 // performs an equivalent shuffle.
20518 SmallVector<int, 16> WidenedMask;
20519 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20520 Mask = std::move(WidenedMask);
20521 WidenedMask.clear();
20524 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20528 /// \brief Get the PSHUF-style mask from PSHUF node.
20530 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20531 /// PSHUF-style masks that can be reused with such instructions.
20532 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20533 MVT VT = N.getSimpleValueType();
20534 SmallVector<int, 4> Mask;
20536 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20540 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20541 // matter. Check that the upper masks are repeats and remove them.
20542 if (VT.getSizeInBits() > 128) {
20543 int LaneElts = 128 / VT.getScalarSizeInBits();
20545 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20546 for (int j = 0; j < LaneElts; ++j)
20547 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20548 "Mask doesn't repeat in high 128-bit lanes!");
20550 Mask.resize(LaneElts);
20553 switch (N.getOpcode()) {
20554 case X86ISD::PSHUFD:
20556 case X86ISD::PSHUFLW:
20559 case X86ISD::PSHUFHW:
20560 Mask.erase(Mask.begin(), Mask.begin() + 4);
20561 for (int &M : Mask)
20565 llvm_unreachable("No valid shuffle instruction found!");
20569 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20571 /// We walk up the chain and look for a combinable shuffle, skipping over
20572 /// shuffles that we could hoist this shuffle's transformation past without
20573 /// altering anything.
20575 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20577 TargetLowering::DAGCombinerInfo &DCI) {
20578 assert(N.getOpcode() == X86ISD::PSHUFD &&
20579 "Called with something other than an x86 128-bit half shuffle!");
20582 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20583 // of the shuffles in the chain so that we can form a fresh chain to replace
20585 SmallVector<SDValue, 8> Chain;
20586 SDValue V = N.getOperand(0);
20587 for (; V.hasOneUse(); V = V.getOperand(0)) {
20588 switch (V.getOpcode()) {
20590 return SDValue(); // Nothing combined!
20593 // Skip bitcasts as we always know the type for the target specific
20597 case X86ISD::PSHUFD:
20598 // Found another dword shuffle.
20601 case X86ISD::PSHUFLW:
20602 // Check that the low words (being shuffled) are the identity in the
20603 // dword shuffle, and the high words are self-contained.
20604 if (Mask[0] != 0 || Mask[1] != 1 ||
20605 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20608 Chain.push_back(V);
20611 case X86ISD::PSHUFHW:
20612 // Check that the high words (being shuffled) are the identity in the
20613 // dword shuffle, and the low words are self-contained.
20614 if (Mask[2] != 2 || Mask[3] != 3 ||
20615 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20618 Chain.push_back(V);
20621 case X86ISD::UNPCKL:
20622 case X86ISD::UNPCKH:
20623 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20624 // shuffle into a preceding word shuffle.
20625 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20626 V.getSimpleValueType().getScalarType() != MVT::i16)
20629 // Search for a half-shuffle which we can combine with.
20630 unsigned CombineOp =
20631 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20632 if (V.getOperand(0) != V.getOperand(1) ||
20633 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20635 Chain.push_back(V);
20636 V = V.getOperand(0);
20638 switch (V.getOpcode()) {
20640 return SDValue(); // Nothing to combine.
20642 case X86ISD::PSHUFLW:
20643 case X86ISD::PSHUFHW:
20644 if (V.getOpcode() == CombineOp)
20647 Chain.push_back(V);
20651 V = V.getOperand(0);
20655 } while (V.hasOneUse());
20658 // Break out of the loop if we break out of the switch.
20662 if (!V.hasOneUse())
20663 // We fell out of the loop without finding a viable combining instruction.
20666 // Merge this node's mask and our incoming mask.
20667 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20668 for (int &M : Mask)
20670 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20671 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20673 // Rebuild the chain around this new shuffle.
20674 while (!Chain.empty()) {
20675 SDValue W = Chain.pop_back_val();
20677 if (V.getValueType() != W.getOperand(0).getValueType())
20678 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20680 switch (W.getOpcode()) {
20682 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20684 case X86ISD::UNPCKL:
20685 case X86ISD::UNPCKH:
20686 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20689 case X86ISD::PSHUFD:
20690 case X86ISD::PSHUFLW:
20691 case X86ISD::PSHUFHW:
20692 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20696 if (V.getValueType() != N.getValueType())
20697 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20699 // Return the new chain to replace N.
20703 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20705 /// We walk up the chain, skipping shuffles of the other half and looking
20706 /// through shuffles which switch halves trying to find a shuffle of the same
20707 /// pair of dwords.
20708 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20710 TargetLowering::DAGCombinerInfo &DCI) {
20712 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20713 "Called with something other than an x86 128-bit half shuffle!");
20715 unsigned CombineOpcode = N.getOpcode();
20717 // Walk up a single-use chain looking for a combinable shuffle.
20718 SDValue V = N.getOperand(0);
20719 for (; V.hasOneUse(); V = V.getOperand(0)) {
20720 switch (V.getOpcode()) {
20722 return false; // Nothing combined!
20725 // Skip bitcasts as we always know the type for the target specific
20729 case X86ISD::PSHUFLW:
20730 case X86ISD::PSHUFHW:
20731 if (V.getOpcode() == CombineOpcode)
20734 // Other-half shuffles are no-ops.
20737 // Break out of the loop if we break out of the switch.
20741 if (!V.hasOneUse())
20742 // We fell out of the loop without finding a viable combining instruction.
20745 // Combine away the bottom node as its shuffle will be accumulated into
20746 // a preceding shuffle.
20747 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20749 // Record the old value.
20752 // Merge this node's mask and our incoming mask (adjusted to account for all
20753 // the pshufd instructions encountered).
20754 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20755 for (int &M : Mask)
20757 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20758 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20760 // Check that the shuffles didn't cancel each other out. If not, we need to
20761 // combine to the new one.
20763 // Replace the combinable shuffle with the combined one, updating all users
20764 // so that we re-evaluate the chain here.
20765 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20770 /// \brief Try to combine x86 target specific shuffles.
20771 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20772 TargetLowering::DAGCombinerInfo &DCI,
20773 const X86Subtarget *Subtarget) {
20775 MVT VT = N.getSimpleValueType();
20776 SmallVector<int, 4> Mask;
20778 switch (N.getOpcode()) {
20779 case X86ISD::PSHUFD:
20780 case X86ISD::PSHUFLW:
20781 case X86ISD::PSHUFHW:
20782 Mask = getPSHUFShuffleMask(N);
20783 assert(Mask.size() == 4);
20789 // Nuke no-op shuffles that show up after combining.
20790 if (isNoopShuffleMask(Mask))
20791 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20793 // Look for simplifications involving one or two shuffle instructions.
20794 SDValue V = N.getOperand(0);
20795 switch (N.getOpcode()) {
20798 case X86ISD::PSHUFLW:
20799 case X86ISD::PSHUFHW:
20800 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20802 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20803 return SDValue(); // We combined away this shuffle, so we're done.
20805 // See if this reduces to a PSHUFD which is no more expensive and can
20806 // combine with more operations. Note that it has to at least flip the
20807 // dwords as otherwise it would have been removed as a no-op.
20808 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20809 int DMask[] = {0, 1, 2, 3};
20810 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20811 DMask[DOffset + 0] = DOffset + 1;
20812 DMask[DOffset + 1] = DOffset + 0;
20813 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20814 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20815 DCI.AddToWorklist(V.getNode());
20816 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20817 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20818 DCI.AddToWorklist(V.getNode());
20819 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20822 // Look for shuffle patterns which can be implemented as a single unpack.
20823 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20824 // only works when we have a PSHUFD followed by two half-shuffles.
20825 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20826 (V.getOpcode() == X86ISD::PSHUFLW ||
20827 V.getOpcode() == X86ISD::PSHUFHW) &&
20828 V.getOpcode() != N.getOpcode() &&
20830 SDValue D = V.getOperand(0);
20831 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20832 D = D.getOperand(0);
20833 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20834 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20835 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20836 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20837 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20839 for (int i = 0; i < 4; ++i) {
20840 WordMask[i + NOffset] = Mask[i] + NOffset;
20841 WordMask[i + VOffset] = VMask[i] + VOffset;
20843 // Map the word mask through the DWord mask.
20845 for (int i = 0; i < 8; ++i)
20846 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20847 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20848 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20849 // We can replace all three shuffles with an unpack.
20850 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20851 DCI.AddToWorklist(V.getNode());
20852 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20861 case X86ISD::PSHUFD:
20862 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20871 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20873 /// We combine this directly on the abstract vector shuffle nodes so it is
20874 /// easier to generically match. We also insert dummy vector shuffle nodes for
20875 /// the operands which explicitly discard the lanes which are unused by this
20876 /// operation to try to flow through the rest of the combiner the fact that
20877 /// they're unused.
20878 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20880 EVT VT = N->getValueType(0);
20882 // We only handle target-independent shuffles.
20883 // FIXME: It would be easy and harmless to use the target shuffle mask
20884 // extraction tool to support more.
20885 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20888 auto *SVN = cast<ShuffleVectorSDNode>(N);
20889 ArrayRef<int> Mask = SVN->getMask();
20890 SDValue V1 = N->getOperand(0);
20891 SDValue V2 = N->getOperand(1);
20893 // We require the first shuffle operand to be the SUB node, and the second to
20894 // be the ADD node.
20895 // FIXME: We should support the commuted patterns.
20896 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20899 // If there are other uses of these operations we can't fold them.
20900 if (!V1->hasOneUse() || !V2->hasOneUse())
20903 // Ensure that both operations have the same operands. Note that we can
20904 // commute the FADD operands.
20905 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20906 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20907 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20910 // We're looking for blends between FADD and FSUB nodes. We insist on these
20911 // nodes being lined up in a specific expected pattern.
20912 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20913 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20914 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20917 // Only specific types are legal at this point, assert so we notice if and
20918 // when these change.
20919 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20920 VT == MVT::v4f64) &&
20921 "Unknown vector type encountered!");
20923 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20926 /// PerformShuffleCombine - Performs several different shuffle combines.
20927 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20928 TargetLowering::DAGCombinerInfo &DCI,
20929 const X86Subtarget *Subtarget) {
20931 SDValue N0 = N->getOperand(0);
20932 SDValue N1 = N->getOperand(1);
20933 EVT VT = N->getValueType(0);
20935 // Don't create instructions with illegal types after legalize types has run.
20936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20937 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20940 // If we have legalized the vector types, look for blends of FADD and FSUB
20941 // nodes that we can fuse into an ADDSUB node.
20942 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20943 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20946 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20947 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20948 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20949 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20951 // During Type Legalization, when promoting illegal vector types,
20952 // the backend might introduce new shuffle dag nodes and bitcasts.
20954 // This code performs the following transformation:
20955 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20956 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20958 // We do this only if both the bitcast and the BINOP dag nodes have
20959 // one use. Also, perform this transformation only if the new binary
20960 // operation is legal. This is to avoid introducing dag nodes that
20961 // potentially need to be further expanded (or custom lowered) into a
20962 // less optimal sequence of dag nodes.
20963 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20964 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20965 N0.getOpcode() == ISD::BITCAST) {
20966 SDValue BC0 = N0.getOperand(0);
20967 EVT SVT = BC0.getValueType();
20968 unsigned Opcode = BC0.getOpcode();
20969 unsigned NumElts = VT.getVectorNumElements();
20971 if (BC0.hasOneUse() && SVT.isVector() &&
20972 SVT.getVectorNumElements() * 2 == NumElts &&
20973 TLI.isOperationLegal(Opcode, VT)) {
20974 bool CanFold = false;
20986 unsigned SVTNumElts = SVT.getVectorNumElements();
20987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20988 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20989 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20990 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20991 CanFold = SVOp->getMaskElt(i) < 0;
20994 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20995 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20996 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20997 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21002 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21003 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21004 // consecutive, non-overlapping, and in the right order.
21005 SmallVector<SDValue, 16> Elts;
21006 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21007 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21009 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21013 if (isTargetShuffle(N->getOpcode())) {
21015 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21016 if (Shuffle.getNode())
21019 // Try recursively combining arbitrary sequences of x86 shuffle
21020 // instructions into higher-order shuffles. We do this after combining
21021 // specific PSHUF instruction sequences into their minimal form so that we
21022 // can evaluate how many specialized shuffle instructions are involved in
21023 // a particular chain.
21024 SmallVector<int, 1> NonceMask; // Just a placeholder.
21025 NonceMask.push_back(0);
21026 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21027 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21029 return SDValue(); // This routine will use CombineTo to replace N.
21035 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21036 /// specific shuffle of a load can be folded into a single element load.
21037 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21038 /// shuffles have been custom lowered so we need to handle those here.
21039 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21040 TargetLowering::DAGCombinerInfo &DCI) {
21041 if (DCI.isBeforeLegalizeOps())
21044 SDValue InVec = N->getOperand(0);
21045 SDValue EltNo = N->getOperand(1);
21047 if (!isa<ConstantSDNode>(EltNo))
21050 EVT OriginalVT = InVec.getValueType();
21052 if (InVec.getOpcode() == ISD::BITCAST) {
21053 // Don't duplicate a load with other uses.
21054 if (!InVec.hasOneUse())
21056 EVT BCVT = InVec.getOperand(0).getValueType();
21057 if (!BCVT.isVector() ||
21058 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21060 InVec = InVec.getOperand(0);
21063 EVT CurrentVT = InVec.getValueType();
21065 if (!isTargetShuffle(InVec.getOpcode()))
21068 // Don't duplicate a load with other uses.
21069 if (!InVec.hasOneUse())
21072 SmallVector<int, 16> ShuffleMask;
21074 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21075 ShuffleMask, UnaryShuffle))
21078 // Select the input vector, guarding against out of range extract vector.
21079 unsigned NumElems = CurrentVT.getVectorNumElements();
21080 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21081 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21082 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21083 : InVec.getOperand(1);
21085 // If inputs to shuffle are the same for both ops, then allow 2 uses
21086 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21087 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21089 if (LdNode.getOpcode() == ISD::BITCAST) {
21090 // Don't duplicate a load with other uses.
21091 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21094 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21095 LdNode = LdNode.getOperand(0);
21098 if (!ISD::isNormalLoad(LdNode.getNode()))
21101 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21103 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21106 EVT EltVT = N->getValueType(0);
21107 // If there's a bitcast before the shuffle, check if the load type and
21108 // alignment is valid.
21109 unsigned Align = LN0->getAlignment();
21110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21111 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21112 EltVT.getTypeForEVT(*DAG.getContext()));
21114 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21117 // All checks match so transform back to vector_shuffle so that DAG combiner
21118 // can finish the job
21121 // Create shuffle node taking into account the case that its a unary shuffle
21122 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21123 : InVec.getOperand(1);
21124 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21125 InVec.getOperand(0), Shuffle,
21127 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
21128 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21132 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21133 /// special and don't usually play with other vector types, it's better to
21134 /// handle them early to be sure we emit efficient code by avoiding
21135 /// store-load conversions.
21136 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21137 if (N->getValueType(0) != MVT::x86mmx ||
21138 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21139 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21142 SDValue V = N->getOperand(0);
21143 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21144 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21145 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21146 N->getValueType(0), V.getOperand(0));
21151 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21152 /// generation and convert it from being a bunch of shuffles and extracts
21153 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21154 /// storing the value and loading scalars back, while for x64 we should
21155 /// use 64-bit extracts and shifts.
21156 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21157 TargetLowering::DAGCombinerInfo &DCI) {
21158 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21159 if (NewOp.getNode())
21162 SDValue InputVector = N->getOperand(0);
21163 SDLoc dl(InputVector);
21164 // Detect mmx to i32 conversion through a v2i32 elt extract.
21165 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21166 N->getValueType(0) == MVT::i32 &&
21167 InputVector.getValueType() == MVT::v2i32) {
21169 // The bitcast source is a direct mmx result.
21170 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21171 if (MMXSrc.getValueType() == MVT::x86mmx)
21172 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21173 N->getValueType(0),
21174 InputVector.getNode()->getOperand(0));
21176 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21177 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21178 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21179 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21180 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21181 MMXSrcOp.getValueType() == MVT::v1i64 &&
21182 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21183 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21184 N->getValueType(0),
21185 MMXSrcOp.getOperand(0));
21188 EVT VT = N->getValueType(0);
21190 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21191 InputVector.getOpcode() == ISD::BITCAST &&
21192 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21193 uint64_t ExtractedElt =
21194 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21195 uint64_t InputValue =
21196 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21197 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21198 return DAG.getConstant(Res, dl, MVT::i1);
21200 // Only operate on vectors of 4 elements, where the alternative shuffling
21201 // gets to be more expensive.
21202 if (InputVector.getValueType() != MVT::v4i32)
21205 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21206 // single use which is a sign-extend or zero-extend, and all elements are
21208 SmallVector<SDNode *, 4> Uses;
21209 unsigned ExtractedElements = 0;
21210 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21211 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21212 if (UI.getUse().getResNo() != InputVector.getResNo())
21215 SDNode *Extract = *UI;
21216 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21219 if (Extract->getValueType(0) != MVT::i32)
21221 if (!Extract->hasOneUse())
21223 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21224 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21226 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21229 // Record which element was extracted.
21230 ExtractedElements |=
21231 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21233 Uses.push_back(Extract);
21236 // If not all the elements were used, this may not be worthwhile.
21237 if (ExtractedElements != 15)
21240 // Ok, we've now decided to do the transformation.
21241 // If 64-bit shifts are legal, use the extract-shift sequence,
21242 // otherwise bounce the vector off the cache.
21243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21246 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21247 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
21248 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21249 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21250 DAG.getConstant(0, dl, VecIdxTy));
21251 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21252 DAG.getConstant(1, dl, VecIdxTy));
21254 SDValue ShAmt = DAG.getConstant(32, dl,
21255 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21256 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21257 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21258 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21259 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21260 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21261 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21263 // Store the value to a temporary stack slot.
21264 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21265 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21266 MachinePointerInfo(), false, false, 0);
21268 EVT ElementType = InputVector.getValueType().getVectorElementType();
21269 unsigned EltSize = ElementType.getSizeInBits() / 8;
21271 // Replace each use (extract) with a load of the appropriate element.
21272 for (unsigned i = 0; i < 4; ++i) {
21273 uint64_t Offset = EltSize * i;
21274 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21276 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21277 StackPtr, OffsetVal);
21279 // Load the scalar.
21280 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21281 ScalarAddr, MachinePointerInfo(),
21282 false, false, false, 0);
21287 // Replace the extracts
21288 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21289 UE = Uses.end(); UI != UE; ++UI) {
21290 SDNode *Extract = *UI;
21292 SDValue Idx = Extract->getOperand(1);
21293 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21294 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21297 // The replacement was made in place; don't return anything.
21301 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21302 static std::pair<unsigned, bool>
21303 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21304 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21305 if (!VT.isVector())
21306 return std::make_pair(0, false);
21308 bool NeedSplit = false;
21309 switch (VT.getSimpleVT().SimpleTy) {
21310 default: return std::make_pair(0, false);
21313 if (!Subtarget->hasVLX())
21314 return std::make_pair(0, false);
21318 if (!Subtarget->hasBWI())
21319 return std::make_pair(0, false);
21323 if (!Subtarget->hasAVX512())
21324 return std::make_pair(0, false);
21329 if (!Subtarget->hasAVX2())
21331 if (!Subtarget->hasAVX())
21332 return std::make_pair(0, false);
21337 if (!Subtarget->hasSSE2())
21338 return std::make_pair(0, false);
21341 // SSE2 has only a small subset of the operations.
21342 bool hasUnsigned = Subtarget->hasSSE41() ||
21343 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21344 bool hasSigned = Subtarget->hasSSE41() ||
21345 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21347 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21350 // Check for x CC y ? x : y.
21351 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21352 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21357 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21360 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21363 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21366 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21368 // Check for x CC y ? y : x -- a min/max with reversed arms.
21369 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21370 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21375 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21378 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21381 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21384 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21388 return std::make_pair(Opc, NeedSplit);
21392 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21393 const X86Subtarget *Subtarget) {
21395 SDValue Cond = N->getOperand(0);
21396 SDValue LHS = N->getOperand(1);
21397 SDValue RHS = N->getOperand(2);
21399 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21400 SDValue CondSrc = Cond->getOperand(0);
21401 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21402 Cond = CondSrc->getOperand(0);
21405 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21408 // A vselect where all conditions and data are constants can be optimized into
21409 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21410 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21411 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21414 unsigned MaskValue = 0;
21415 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21418 MVT VT = N->getSimpleValueType(0);
21419 unsigned NumElems = VT.getVectorNumElements();
21420 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21421 for (unsigned i = 0; i < NumElems; ++i) {
21422 // Be sure we emit undef where we can.
21423 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21424 ShuffleMask[i] = -1;
21426 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21430 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21432 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21435 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21437 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21438 TargetLowering::DAGCombinerInfo &DCI,
21439 const X86Subtarget *Subtarget) {
21441 SDValue Cond = N->getOperand(0);
21442 // Get the LHS/RHS of the select.
21443 SDValue LHS = N->getOperand(1);
21444 SDValue RHS = N->getOperand(2);
21445 EVT VT = LHS.getValueType();
21446 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21448 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21449 // instructions match the semantics of the common C idiom x<y?x:y but not
21450 // x<=y?x:y, because of how they handle negative zero (which can be
21451 // ignored in unsafe-math mode).
21452 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21453 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21454 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21455 (Subtarget->hasSSE2() ||
21456 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21457 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21459 unsigned Opcode = 0;
21460 // Check for x CC y ? x : y.
21461 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21462 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21466 // Converting this to a min would handle NaNs incorrectly, and swapping
21467 // the operands would cause it to handle comparisons between positive
21468 // and negative zero incorrectly.
21469 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21470 if (!DAG.getTarget().Options.UnsafeFPMath &&
21471 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21473 std::swap(LHS, RHS);
21475 Opcode = X86ISD::FMIN;
21478 // Converting this to a min would handle comparisons between positive
21479 // and negative zero incorrectly.
21480 if (!DAG.getTarget().Options.UnsafeFPMath &&
21481 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21483 Opcode = X86ISD::FMIN;
21486 // Converting this to a min would handle both negative zeros and NaNs
21487 // incorrectly, but we can swap the operands to fix both.
21488 std::swap(LHS, RHS);
21492 Opcode = X86ISD::FMIN;
21496 // Converting this to a max would handle comparisons between positive
21497 // and negative zero incorrectly.
21498 if (!DAG.getTarget().Options.UnsafeFPMath &&
21499 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21501 Opcode = X86ISD::FMAX;
21504 // Converting this to a max would handle NaNs incorrectly, and swapping
21505 // the operands would cause it to handle comparisons between positive
21506 // and negative zero incorrectly.
21507 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21508 if (!DAG.getTarget().Options.UnsafeFPMath &&
21509 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21511 std::swap(LHS, RHS);
21513 Opcode = X86ISD::FMAX;
21516 // Converting this to a max would handle both negative zeros and NaNs
21517 // incorrectly, but we can swap the operands to fix both.
21518 std::swap(LHS, RHS);
21522 Opcode = X86ISD::FMAX;
21525 // Check for x CC y ? y : x -- a min/max with reversed arms.
21526 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21527 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21531 // Converting this to a min would handle comparisons between positive
21532 // and negative zero incorrectly, and swapping the operands would
21533 // cause it to handle NaNs incorrectly.
21534 if (!DAG.getTarget().Options.UnsafeFPMath &&
21535 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21536 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21538 std::swap(LHS, RHS);
21540 Opcode = X86ISD::FMIN;
21543 // Converting this to a min would handle NaNs incorrectly.
21544 if (!DAG.getTarget().Options.UnsafeFPMath &&
21545 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21547 Opcode = X86ISD::FMIN;
21550 // Converting this to a min would handle both negative zeros and NaNs
21551 // incorrectly, but we can swap the operands to fix both.
21552 std::swap(LHS, RHS);
21556 Opcode = X86ISD::FMIN;
21560 // Converting this to a max would handle NaNs incorrectly.
21561 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21563 Opcode = X86ISD::FMAX;
21566 // Converting this to a max would handle comparisons between positive
21567 // and negative zero incorrectly, and swapping the operands would
21568 // cause it to handle NaNs incorrectly.
21569 if (!DAG.getTarget().Options.UnsafeFPMath &&
21570 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21571 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21573 std::swap(LHS, RHS);
21575 Opcode = X86ISD::FMAX;
21578 // Converting this to a max would handle both negative zeros and NaNs
21579 // incorrectly, but we can swap the operands to fix both.
21580 std::swap(LHS, RHS);
21584 Opcode = X86ISD::FMAX;
21590 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21593 EVT CondVT = Cond.getValueType();
21594 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21595 CondVT.getVectorElementType() == MVT::i1) {
21596 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21597 // lowering on KNL. In this case we convert it to
21598 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21599 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21600 // Since SKX these selects have a proper lowering.
21601 EVT OpVT = LHS.getValueType();
21602 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21603 (OpVT.getVectorElementType() == MVT::i8 ||
21604 OpVT.getVectorElementType() == MVT::i16) &&
21605 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21606 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21607 DCI.AddToWorklist(Cond.getNode());
21608 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21611 // If this is a select between two integer constants, try to do some
21613 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21614 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21615 // Don't do this for crazy integer types.
21616 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21617 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21618 // so that TrueC (the true value) is larger than FalseC.
21619 bool NeedsCondInvert = false;
21621 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21622 // Efficiently invertible.
21623 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21624 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21625 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21626 NeedsCondInvert = true;
21627 std::swap(TrueC, FalseC);
21630 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21631 if (FalseC->getAPIntValue() == 0 &&
21632 TrueC->getAPIntValue().isPowerOf2()) {
21633 if (NeedsCondInvert) // Invert the condition if needed.
21634 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21635 DAG.getConstant(1, DL, Cond.getValueType()));
21637 // Zero extend the condition if needed.
21638 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21640 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21641 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21642 DAG.getConstant(ShAmt, DL, MVT::i8));
21645 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21646 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21647 if (NeedsCondInvert) // Invert the condition if needed.
21648 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21649 DAG.getConstant(1, DL, Cond.getValueType()));
21651 // Zero extend the condition if needed.
21652 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21653 FalseC->getValueType(0), Cond);
21654 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21655 SDValue(FalseC, 0));
21658 // Optimize cases that will turn into an LEA instruction. This requires
21659 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21660 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21661 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21662 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21664 bool isFastMultiplier = false;
21666 switch ((unsigned char)Diff) {
21668 case 1: // result = add base, cond
21669 case 2: // result = lea base( , cond*2)
21670 case 3: // result = lea base(cond, cond*2)
21671 case 4: // result = lea base( , cond*4)
21672 case 5: // result = lea base(cond, cond*4)
21673 case 8: // result = lea base( , cond*8)
21674 case 9: // result = lea base(cond, cond*8)
21675 isFastMultiplier = true;
21680 if (isFastMultiplier) {
21681 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21682 if (NeedsCondInvert) // Invert the condition if needed.
21683 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21684 DAG.getConstant(1, DL, Cond.getValueType()));
21686 // Zero extend the condition if needed.
21687 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21689 // Scale the condition by the difference.
21691 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21692 DAG.getConstant(Diff, DL,
21693 Cond.getValueType()));
21695 // Add the base if non-zero.
21696 if (FalseC->getAPIntValue() != 0)
21697 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21698 SDValue(FalseC, 0));
21705 // Canonicalize max and min:
21706 // (x > y) ? x : y -> (x >= y) ? x : y
21707 // (x < y) ? x : y -> (x <= y) ? x : y
21708 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21709 // the need for an extra compare
21710 // against zero. e.g.
21711 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21713 // testl %edi, %edi
21715 // cmovgl %edi, %eax
21719 // cmovsl %eax, %edi
21720 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21721 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21722 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21723 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21728 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21729 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21730 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21731 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21736 // Early exit check
21737 if (!TLI.isTypeLegal(VT))
21740 // Match VSELECTs into subs with unsigned saturation.
21741 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21742 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21743 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21744 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21745 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21747 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21748 // left side invert the predicate to simplify logic below.
21750 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21752 CC = ISD::getSetCCInverse(CC, true);
21753 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21757 if (Other.getNode() && Other->getNumOperands() == 2 &&
21758 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21759 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21760 SDValue CondRHS = Cond->getOperand(1);
21762 // Look for a general sub with unsigned saturation first.
21763 // x >= y ? x-y : 0 --> subus x, y
21764 // x > y ? x-y : 0 --> subus x, y
21765 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21766 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21767 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21769 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21770 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21771 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21772 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21773 // If the RHS is a constant we have to reverse the const
21774 // canonicalization.
21775 // x > C-1 ? x+-C : 0 --> subus x, C
21776 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21777 CondRHSConst->getAPIntValue() ==
21778 (-OpRHSConst->getAPIntValue() - 1))
21779 return DAG.getNode(
21780 X86ISD::SUBUS, DL, VT, OpLHS,
21781 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21783 // Another special case: If C was a sign bit, the sub has been
21784 // canonicalized into a xor.
21785 // FIXME: Would it be better to use computeKnownBits to determine
21786 // whether it's safe to decanonicalize the xor?
21787 // x s< 0 ? x^C : 0 --> subus x, C
21788 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21789 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21790 OpRHSConst->getAPIntValue().isSignBit())
21791 // Note that we have to rebuild the RHS constant here to ensure we
21792 // don't rely on particular values of undef lanes.
21793 return DAG.getNode(
21794 X86ISD::SUBUS, DL, VT, OpLHS,
21795 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21800 // Try to match a min/max vector operation.
21801 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21802 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21803 unsigned Opc = ret.first;
21804 bool NeedSplit = ret.second;
21806 if (Opc && NeedSplit) {
21807 unsigned NumElems = VT.getVectorNumElements();
21808 // Extract the LHS vectors
21809 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21810 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21812 // Extract the RHS vectors
21813 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21814 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21816 // Create min/max for each subvector
21817 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21818 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21820 // Merge the result
21821 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21823 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21826 // Simplify vector selection if condition value type matches vselect
21828 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21829 assert(Cond.getValueType().isVector() &&
21830 "vector select expects a vector selector!");
21832 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21833 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21835 // Try invert the condition if true value is not all 1s and false value
21837 if (!TValIsAllOnes && !FValIsAllZeros &&
21838 // Check if the selector will be produced by CMPP*/PCMP*
21839 Cond.getOpcode() == ISD::SETCC &&
21840 // Check if SETCC has already been promoted
21841 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21842 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21843 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21845 if (TValIsAllZeros || FValIsAllOnes) {
21846 SDValue CC = Cond.getOperand(2);
21847 ISD::CondCode NewCC =
21848 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21849 Cond.getOperand(0).getValueType().isInteger());
21850 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21851 std::swap(LHS, RHS);
21852 TValIsAllOnes = FValIsAllOnes;
21853 FValIsAllZeros = TValIsAllZeros;
21857 if (TValIsAllOnes || FValIsAllZeros) {
21860 if (TValIsAllOnes && FValIsAllZeros)
21862 else if (TValIsAllOnes)
21863 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21864 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21865 else if (FValIsAllZeros)
21866 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21867 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21869 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21873 // We should generate an X86ISD::BLENDI from a vselect if its argument
21874 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21875 // constants. This specific pattern gets generated when we split a
21876 // selector for a 512 bit vector in a machine without AVX512 (but with
21877 // 256-bit vectors), during legalization:
21879 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21881 // Iff we find this pattern and the build_vectors are built from
21882 // constants, we translate the vselect into a shuffle_vector that we
21883 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21884 if ((N->getOpcode() == ISD::VSELECT ||
21885 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21886 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
21887 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21888 if (Shuffle.getNode())
21892 // If this is a *dynamic* select (non-constant condition) and we can match
21893 // this node with one of the variable blend instructions, restructure the
21894 // condition so that the blends can use the high bit of each element and use
21895 // SimplifyDemandedBits to simplify the condition operand.
21896 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21897 !DCI.isBeforeLegalize() &&
21898 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21899 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21901 // Don't optimize vector selects that map to mask-registers.
21905 // We can only handle the cases where VSELECT is directly legal on the
21906 // subtarget. We custom lower VSELECT nodes with constant conditions and
21907 // this makes it hard to see whether a dynamic VSELECT will correctly
21908 // lower, so we both check the operation's status and explicitly handle the
21909 // cases where a *dynamic* blend will fail even though a constant-condition
21910 // blend could be custom lowered.
21911 // FIXME: We should find a better way to handle this class of problems.
21912 // Potentially, we should combine constant-condition vselect nodes
21913 // pre-legalization into shuffles and not mark as many types as custom
21915 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21917 // FIXME: We don't support i16-element blends currently. We could and
21918 // should support them by making *all* the bits in the condition be set
21919 // rather than just the high bit and using an i8-element blend.
21920 if (VT.getScalarType() == MVT::i16)
21922 // Dynamic blending was only available from SSE4.1 onward.
21923 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21925 // Byte blends are only available in AVX2
21926 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21927 !Subtarget->hasAVX2())
21930 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21931 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21933 APInt KnownZero, KnownOne;
21934 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21935 DCI.isBeforeLegalizeOps());
21936 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21937 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21939 // If we changed the computation somewhere in the DAG, this change
21940 // will affect all users of Cond.
21941 // Make sure it is fine and update all the nodes so that we do not
21942 // use the generic VSELECT anymore. Otherwise, we may perform
21943 // wrong optimizations as we messed up with the actual expectation
21944 // for the vector boolean values.
21945 if (Cond != TLO.Old) {
21946 // Check all uses of that condition operand to check whether it will be
21947 // consumed by non-BLEND instructions, which may depend on all bits are
21949 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21951 if (I->getOpcode() != ISD::VSELECT)
21952 // TODO: Add other opcodes eventually lowered into BLEND.
21955 // Update all the users of the condition, before committing the change,
21956 // so that the VSELECT optimizations that expect the correct vector
21957 // boolean value will not be triggered.
21958 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21960 DAG.ReplaceAllUsesOfValueWith(
21962 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21963 Cond, I->getOperand(1), I->getOperand(2)));
21964 DCI.CommitTargetLoweringOpt(TLO);
21967 // At this point, only Cond is changed. Change the condition
21968 // just for N to keep the opportunity to optimize all other
21969 // users their own way.
21970 DAG.ReplaceAllUsesOfValueWith(
21972 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21973 TLO.New, N->getOperand(1), N->getOperand(2)));
21981 // Check whether a boolean test is testing a boolean value generated by
21982 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21985 // Simplify the following patterns:
21986 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21987 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21988 // to (Op EFLAGS Cond)
21990 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21991 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21992 // to (Op EFLAGS !Cond)
21994 // where Op could be BRCOND or CMOV.
21996 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21997 // Quit if not CMP and SUB with its value result used.
21998 if (Cmp.getOpcode() != X86ISD::CMP &&
21999 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22002 // Quit if not used as a boolean value.
22003 if (CC != X86::COND_E && CC != X86::COND_NE)
22006 // Check CMP operands. One of them should be 0 or 1 and the other should be
22007 // an SetCC or extended from it.
22008 SDValue Op1 = Cmp.getOperand(0);
22009 SDValue Op2 = Cmp.getOperand(1);
22012 const ConstantSDNode* C = nullptr;
22013 bool needOppositeCond = (CC == X86::COND_E);
22014 bool checkAgainstTrue = false; // Is it a comparison against 1?
22016 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22018 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22020 else // Quit if all operands are not constants.
22023 if (C->getZExtValue() == 1) {
22024 needOppositeCond = !needOppositeCond;
22025 checkAgainstTrue = true;
22026 } else if (C->getZExtValue() != 0)
22027 // Quit if the constant is neither 0 or 1.
22030 bool truncatedToBoolWithAnd = false;
22031 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22032 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22033 SetCC.getOpcode() == ISD::TRUNCATE ||
22034 SetCC.getOpcode() == ISD::AND) {
22035 if (SetCC.getOpcode() == ISD::AND) {
22037 ConstantSDNode *CS;
22038 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22039 CS->getZExtValue() == 1)
22041 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22042 CS->getZExtValue() == 1)
22046 SetCC = SetCC.getOperand(OpIdx);
22047 truncatedToBoolWithAnd = true;
22049 SetCC = SetCC.getOperand(0);
22052 switch (SetCC.getOpcode()) {
22053 case X86ISD::SETCC_CARRY:
22054 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22055 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22056 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22057 // truncated to i1 using 'and'.
22058 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22060 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22061 "Invalid use of SETCC_CARRY!");
22063 case X86ISD::SETCC:
22064 // Set the condition code or opposite one if necessary.
22065 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22066 if (needOppositeCond)
22067 CC = X86::GetOppositeBranchCondition(CC);
22068 return SetCC.getOperand(1);
22069 case X86ISD::CMOV: {
22070 // Check whether false/true value has canonical one, i.e. 0 or 1.
22071 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22072 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22073 // Quit if true value is not a constant.
22076 // Quit if false value is not a constant.
22078 SDValue Op = SetCC.getOperand(0);
22079 // Skip 'zext' or 'trunc' node.
22080 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22081 Op.getOpcode() == ISD::TRUNCATE)
22082 Op = Op.getOperand(0);
22083 // A special case for rdrand/rdseed, where 0 is set if false cond is
22085 if ((Op.getOpcode() != X86ISD::RDRAND &&
22086 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22089 // Quit if false value is not the constant 0 or 1.
22090 bool FValIsFalse = true;
22091 if (FVal && FVal->getZExtValue() != 0) {
22092 if (FVal->getZExtValue() != 1)
22094 // If FVal is 1, opposite cond is needed.
22095 needOppositeCond = !needOppositeCond;
22096 FValIsFalse = false;
22098 // Quit if TVal is not the constant opposite of FVal.
22099 if (FValIsFalse && TVal->getZExtValue() != 1)
22101 if (!FValIsFalse && TVal->getZExtValue() != 0)
22103 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22104 if (needOppositeCond)
22105 CC = X86::GetOppositeBranchCondition(CC);
22106 return SetCC.getOperand(3);
22113 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22115 /// (X86or (X86setcc) (X86setcc))
22116 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22117 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22118 X86::CondCode &CC1, SDValue &Flags,
22120 if (Cond->getOpcode() == X86ISD::CMP) {
22121 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22122 if (!CondOp1C || !CondOp1C->isNullValue())
22125 Cond = Cond->getOperand(0);
22130 SDValue SetCC0, SetCC1;
22131 switch (Cond->getOpcode()) {
22132 default: return false;
22139 SetCC0 = Cond->getOperand(0);
22140 SetCC1 = Cond->getOperand(1);
22144 // Make sure we have SETCC nodes, using the same flags value.
22145 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22146 SetCC1.getOpcode() != X86ISD::SETCC ||
22147 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22150 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22151 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22152 Flags = SetCC0->getOperand(1);
22156 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22157 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22158 TargetLowering::DAGCombinerInfo &DCI,
22159 const X86Subtarget *Subtarget) {
22162 // If the flag operand isn't dead, don't touch this CMOV.
22163 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22166 SDValue FalseOp = N->getOperand(0);
22167 SDValue TrueOp = N->getOperand(1);
22168 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22169 SDValue Cond = N->getOperand(3);
22171 if (CC == X86::COND_E || CC == X86::COND_NE) {
22172 switch (Cond.getOpcode()) {
22176 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22177 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22178 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22184 Flags = checkBoolTestSetCCCombine(Cond, CC);
22185 if (Flags.getNode() &&
22186 // Extra check as FCMOV only supports a subset of X86 cond.
22187 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22188 SDValue Ops[] = { FalseOp, TrueOp,
22189 DAG.getConstant(CC, DL, MVT::i8), Flags };
22190 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22193 // If this is a select between two integer constants, try to do some
22194 // optimizations. Note that the operands are ordered the opposite of SELECT
22196 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22197 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22198 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22199 // larger than FalseC (the false value).
22200 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22201 CC = X86::GetOppositeBranchCondition(CC);
22202 std::swap(TrueC, FalseC);
22203 std::swap(TrueOp, FalseOp);
22206 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22207 // This is efficient for any integer data type (including i8/i16) and
22209 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22210 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22211 DAG.getConstant(CC, DL, MVT::i8), Cond);
22213 // Zero extend the condition if needed.
22214 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22216 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22217 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22218 DAG.getConstant(ShAmt, DL, MVT::i8));
22219 if (N->getNumValues() == 2) // Dead flag value?
22220 return DCI.CombineTo(N, Cond, SDValue());
22224 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22225 // for any integer data type, including i8/i16.
22226 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22227 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22228 DAG.getConstant(CC, DL, MVT::i8), Cond);
22230 // Zero extend the condition if needed.
22231 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22232 FalseC->getValueType(0), Cond);
22233 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22234 SDValue(FalseC, 0));
22236 if (N->getNumValues() == 2) // Dead flag value?
22237 return DCI.CombineTo(N, Cond, SDValue());
22241 // Optimize cases that will turn into an LEA instruction. This requires
22242 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22243 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22244 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22245 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22247 bool isFastMultiplier = false;
22249 switch ((unsigned char)Diff) {
22251 case 1: // result = add base, cond
22252 case 2: // result = lea base( , cond*2)
22253 case 3: // result = lea base(cond, cond*2)
22254 case 4: // result = lea base( , cond*4)
22255 case 5: // result = lea base(cond, cond*4)
22256 case 8: // result = lea base( , cond*8)
22257 case 9: // result = lea base(cond, cond*8)
22258 isFastMultiplier = true;
22263 if (isFastMultiplier) {
22264 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22265 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22266 DAG.getConstant(CC, DL, MVT::i8), Cond);
22267 // Zero extend the condition if needed.
22268 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22270 // Scale the condition by the difference.
22272 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22273 DAG.getConstant(Diff, DL, Cond.getValueType()));
22275 // Add the base if non-zero.
22276 if (FalseC->getAPIntValue() != 0)
22277 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22278 SDValue(FalseC, 0));
22279 if (N->getNumValues() == 2) // Dead flag value?
22280 return DCI.CombineTo(N, Cond, SDValue());
22287 // Handle these cases:
22288 // (select (x != c), e, c) -> select (x != c), e, x),
22289 // (select (x == c), c, e) -> select (x == c), x, e)
22290 // where the c is an integer constant, and the "select" is the combination
22291 // of CMOV and CMP.
22293 // The rationale for this change is that the conditional-move from a constant
22294 // needs two instructions, however, conditional-move from a register needs
22295 // only one instruction.
22297 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22298 // some instruction-combining opportunities. This opt needs to be
22299 // postponed as late as possible.
22301 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22302 // the DCI.xxxx conditions are provided to postpone the optimization as
22303 // late as possible.
22305 ConstantSDNode *CmpAgainst = nullptr;
22306 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22307 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22308 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22310 if (CC == X86::COND_NE &&
22311 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22312 CC = X86::GetOppositeBranchCondition(CC);
22313 std::swap(TrueOp, FalseOp);
22316 if (CC == X86::COND_E &&
22317 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22318 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22319 DAG.getConstant(CC, DL, MVT::i8), Cond };
22320 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22325 // Fold and/or of setcc's to double CMOV:
22326 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22327 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22329 // This combine lets us generate:
22330 // cmovcc1 (jcc1 if we don't have CMOV)
22336 // cmovne (jne if we don't have CMOV)
22337 // When we can't use the CMOV instruction, it might increase branch
22339 // When we can use CMOV, or when there is no mispredict, this improves
22340 // throughput and reduces register pressure.
22342 if (CC == X86::COND_NE) {
22344 X86::CondCode CC0, CC1;
22346 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22348 std::swap(FalseOp, TrueOp);
22349 CC0 = X86::GetOppositeBranchCondition(CC0);
22350 CC1 = X86::GetOppositeBranchCondition(CC1);
22353 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22355 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22356 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22357 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22358 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22366 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22367 const X86Subtarget *Subtarget) {
22368 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22370 default: return SDValue();
22371 // SSE/AVX/AVX2 blend intrinsics.
22372 case Intrinsic::x86_avx2_pblendvb:
22373 // Don't try to simplify this intrinsic if we don't have AVX2.
22374 if (!Subtarget->hasAVX2())
22377 case Intrinsic::x86_avx_blendv_pd_256:
22378 case Intrinsic::x86_avx_blendv_ps_256:
22379 // Don't try to simplify this intrinsic if we don't have AVX.
22380 if (!Subtarget->hasAVX())
22383 case Intrinsic::x86_sse41_blendvps:
22384 case Intrinsic::x86_sse41_blendvpd:
22385 case Intrinsic::x86_sse41_pblendvb: {
22386 SDValue Op0 = N->getOperand(1);
22387 SDValue Op1 = N->getOperand(2);
22388 SDValue Mask = N->getOperand(3);
22390 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22391 if (!Subtarget->hasSSE41())
22394 // fold (blend A, A, Mask) -> A
22397 // fold (blend A, B, allZeros) -> A
22398 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22400 // fold (blend A, B, allOnes) -> B
22401 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22404 // Simplify the case where the mask is a constant i32 value.
22405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22406 if (C->isNullValue())
22408 if (C->isAllOnesValue())
22415 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22416 case Intrinsic::x86_sse2_psrai_w:
22417 case Intrinsic::x86_sse2_psrai_d:
22418 case Intrinsic::x86_avx2_psrai_w:
22419 case Intrinsic::x86_avx2_psrai_d:
22420 case Intrinsic::x86_sse2_psra_w:
22421 case Intrinsic::x86_sse2_psra_d:
22422 case Intrinsic::x86_avx2_psra_w:
22423 case Intrinsic::x86_avx2_psra_d: {
22424 SDValue Op0 = N->getOperand(1);
22425 SDValue Op1 = N->getOperand(2);
22426 EVT VT = Op0.getValueType();
22427 assert(VT.isVector() && "Expected a vector type!");
22429 if (isa<BuildVectorSDNode>(Op1))
22430 Op1 = Op1.getOperand(0);
22432 if (!isa<ConstantSDNode>(Op1))
22435 EVT SVT = VT.getVectorElementType();
22436 unsigned SVTBits = SVT.getSizeInBits();
22438 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22439 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22440 uint64_t ShAmt = C.getZExtValue();
22442 // Don't try to convert this shift into a ISD::SRA if the shift
22443 // count is bigger than or equal to the element size.
22444 if (ShAmt >= SVTBits)
22447 // Trivial case: if the shift count is zero, then fold this
22448 // into the first operand.
22452 // Replace this packed shift intrinsic with a target independent
22455 SDValue Splat = DAG.getConstant(C, DL, VT);
22456 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22461 /// PerformMulCombine - Optimize a single multiply with constant into two
22462 /// in order to implement it with two cheaper instructions, e.g.
22463 /// LEA + SHL, LEA + LEA.
22464 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22465 TargetLowering::DAGCombinerInfo &DCI) {
22466 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22469 EVT VT = N->getValueType(0);
22470 if (VT != MVT::i64 && VT != MVT::i32)
22473 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22476 uint64_t MulAmt = C->getZExtValue();
22477 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22480 uint64_t MulAmt1 = 0;
22481 uint64_t MulAmt2 = 0;
22482 if ((MulAmt % 9) == 0) {
22484 MulAmt2 = MulAmt / 9;
22485 } else if ((MulAmt % 5) == 0) {
22487 MulAmt2 = MulAmt / 5;
22488 } else if ((MulAmt % 3) == 0) {
22490 MulAmt2 = MulAmt / 3;
22493 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22496 if (isPowerOf2_64(MulAmt2) &&
22497 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22498 // If second multiplifer is pow2, issue it first. We want the multiply by
22499 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22501 std::swap(MulAmt1, MulAmt2);
22504 if (isPowerOf2_64(MulAmt1))
22505 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22506 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22508 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22509 DAG.getConstant(MulAmt1, DL, VT));
22511 if (isPowerOf2_64(MulAmt2))
22512 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22513 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22515 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22516 DAG.getConstant(MulAmt2, DL, VT));
22518 // Do not add new nodes to DAG combiner worklist.
22519 DCI.CombineTo(N, NewMul, false);
22524 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22525 SDValue N0 = N->getOperand(0);
22526 SDValue N1 = N->getOperand(1);
22527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22528 EVT VT = N0.getValueType();
22530 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22531 // since the result of setcc_c is all zero's or all ones.
22532 if (VT.isInteger() && !VT.isVector() &&
22533 N1C && N0.getOpcode() == ISD::AND &&
22534 N0.getOperand(1).getOpcode() == ISD::Constant) {
22535 SDValue N00 = N0.getOperand(0);
22536 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22537 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22538 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22539 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22540 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22541 APInt ShAmt = N1C->getAPIntValue();
22542 Mask = Mask.shl(ShAmt);
22545 return DAG.getNode(ISD::AND, DL, VT,
22546 N00, DAG.getConstant(Mask, DL, VT));
22551 // Hardware support for vector shifts is sparse which makes us scalarize the
22552 // vector operations in many cases. Also, on sandybridge ADD is faster than
22554 // (shl V, 1) -> add V,V
22555 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22556 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22557 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22558 // We shift all of the values by one. In many cases we do not have
22559 // hardware support for this operation. This is better expressed as an ADD
22561 if (N1SplatC->getZExtValue() == 1)
22562 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22568 /// \brief Returns a vector of 0s if the node in input is a vector logical
22569 /// shift by a constant amount which is known to be bigger than or equal
22570 /// to the vector element size in bits.
22571 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22572 const X86Subtarget *Subtarget) {
22573 EVT VT = N->getValueType(0);
22575 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22576 (!Subtarget->hasInt256() ||
22577 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22580 SDValue Amt = N->getOperand(1);
22582 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22583 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22584 APInt ShiftAmt = AmtSplat->getAPIntValue();
22585 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22587 // SSE2/AVX2 logical shifts always return a vector of 0s
22588 // if the shift amount is bigger than or equal to
22589 // the element size. The constant shift amount will be
22590 // encoded as a 8-bit immediate.
22591 if (ShiftAmt.trunc(8).uge(MaxAmount))
22592 return getZeroVector(VT, Subtarget, DAG, DL);
22598 /// PerformShiftCombine - Combine shifts.
22599 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22600 TargetLowering::DAGCombinerInfo &DCI,
22601 const X86Subtarget *Subtarget) {
22602 if (N->getOpcode() == ISD::SHL) {
22603 SDValue V = PerformSHLCombine(N, DAG);
22604 if (V.getNode()) return V;
22607 if (N->getOpcode() != ISD::SRA) {
22608 // Try to fold this logical shift into a zero vector.
22609 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22610 if (V.getNode()) return V;
22616 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22617 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22618 // and friends. Likewise for OR -> CMPNEQSS.
22619 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22620 TargetLowering::DAGCombinerInfo &DCI,
22621 const X86Subtarget *Subtarget) {
22624 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22625 // we're requiring SSE2 for both.
22626 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22627 SDValue N0 = N->getOperand(0);
22628 SDValue N1 = N->getOperand(1);
22629 SDValue CMP0 = N0->getOperand(1);
22630 SDValue CMP1 = N1->getOperand(1);
22633 // The SETCCs should both refer to the same CMP.
22634 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22637 SDValue CMP00 = CMP0->getOperand(0);
22638 SDValue CMP01 = CMP0->getOperand(1);
22639 EVT VT = CMP00.getValueType();
22641 if (VT == MVT::f32 || VT == MVT::f64) {
22642 bool ExpectingFlags = false;
22643 // Check for any users that want flags:
22644 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22645 !ExpectingFlags && UI != UE; ++UI)
22646 switch (UI->getOpcode()) {
22651 ExpectingFlags = true;
22653 case ISD::CopyToReg:
22654 case ISD::SIGN_EXTEND:
22655 case ISD::ZERO_EXTEND:
22656 case ISD::ANY_EXTEND:
22660 if (!ExpectingFlags) {
22661 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22662 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22664 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22665 X86::CondCode tmp = cc0;
22670 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22671 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22672 // FIXME: need symbolic constants for these magic numbers.
22673 // See X86ATTInstPrinter.cpp:printSSECC().
22674 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22675 if (Subtarget->hasAVX512()) {
22676 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22678 DAG.getConstant(x86cc, DL, MVT::i8));
22679 if (N->getValueType(0) != MVT::i1)
22680 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22684 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22685 CMP00.getValueType(), CMP00, CMP01,
22686 DAG.getConstant(x86cc, DL,
22689 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22690 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22692 if (is64BitFP && !Subtarget->is64Bit()) {
22693 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22694 // 64-bit integer, since that's not a legal type. Since
22695 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22696 // bits, but can do this little dance to extract the lowest 32 bits
22697 // and work with those going forward.
22698 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22700 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22702 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22703 Vector32, DAG.getIntPtrConstant(0, DL));
22707 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22709 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22710 DAG.getConstant(1, DL, IntVT));
22711 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22713 return OneBitOfTruth;
22721 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22722 /// so it can be folded inside ANDNP.
22723 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22724 EVT VT = N->getValueType(0);
22726 // Match direct AllOnes for 128 and 256-bit vectors
22727 if (ISD::isBuildVectorAllOnes(N))
22730 // Look through a bit convert.
22731 if (N->getOpcode() == ISD::BITCAST)
22732 N = N->getOperand(0).getNode();
22734 // Sometimes the operand may come from a insert_subvector building a 256-bit
22736 if (VT.is256BitVector() &&
22737 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22738 SDValue V1 = N->getOperand(0);
22739 SDValue V2 = N->getOperand(1);
22741 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22742 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22743 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22744 ISD::isBuildVectorAllOnes(V2.getNode()))
22751 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22752 // register. In most cases we actually compare or select YMM-sized registers
22753 // and mixing the two types creates horrible code. This method optimizes
22754 // some of the transition sequences.
22755 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22756 TargetLowering::DAGCombinerInfo &DCI,
22757 const X86Subtarget *Subtarget) {
22758 EVT VT = N->getValueType(0);
22759 if (!VT.is256BitVector())
22762 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22763 N->getOpcode() == ISD::ZERO_EXTEND ||
22764 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22766 SDValue Narrow = N->getOperand(0);
22767 EVT NarrowVT = Narrow->getValueType(0);
22768 if (!NarrowVT.is128BitVector())
22771 if (Narrow->getOpcode() != ISD::XOR &&
22772 Narrow->getOpcode() != ISD::AND &&
22773 Narrow->getOpcode() != ISD::OR)
22776 SDValue N0 = Narrow->getOperand(0);
22777 SDValue N1 = Narrow->getOperand(1);
22780 // The Left side has to be a trunc.
22781 if (N0.getOpcode() != ISD::TRUNCATE)
22784 // The type of the truncated inputs.
22785 EVT WideVT = N0->getOperand(0)->getValueType(0);
22789 // The right side has to be a 'trunc' or a constant vector.
22790 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22791 ConstantSDNode *RHSConstSplat = nullptr;
22792 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22793 RHSConstSplat = RHSBV->getConstantSplatNode();
22794 if (!RHSTrunc && !RHSConstSplat)
22797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22799 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22802 // Set N0 and N1 to hold the inputs to the new wide operation.
22803 N0 = N0->getOperand(0);
22804 if (RHSConstSplat) {
22805 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22806 SDValue(RHSConstSplat, 0));
22807 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22808 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22809 } else if (RHSTrunc) {
22810 N1 = N1->getOperand(0);
22813 // Generate the wide operation.
22814 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22815 unsigned Opcode = N->getOpcode();
22817 case ISD::ANY_EXTEND:
22819 case ISD::ZERO_EXTEND: {
22820 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22821 APInt Mask = APInt::getAllOnesValue(InBits);
22822 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22823 return DAG.getNode(ISD::AND, DL, VT,
22824 Op, DAG.getConstant(Mask, DL, VT));
22826 case ISD::SIGN_EXTEND:
22827 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22828 Op, DAG.getValueType(NarrowVT));
22830 llvm_unreachable("Unexpected opcode");
22834 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22835 TargetLowering::DAGCombinerInfo &DCI,
22836 const X86Subtarget *Subtarget) {
22837 SDValue N0 = N->getOperand(0);
22838 SDValue N1 = N->getOperand(1);
22841 // A vector zext_in_reg may be represented as a shuffle,
22842 // feeding into a bitcast (this represents anyext) feeding into
22843 // an and with a mask.
22844 // We'd like to try to combine that into a shuffle with zero
22845 // plus a bitcast, removing the and.
22846 if (N0.getOpcode() != ISD::BITCAST ||
22847 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22850 // The other side of the AND should be a splat of 2^C, where C
22851 // is the number of bits in the source type.
22852 if (N1.getOpcode() == ISD::BITCAST)
22853 N1 = N1.getOperand(0);
22854 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22856 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22858 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22859 EVT SrcType = Shuffle->getValueType(0);
22861 // We expect a single-source shuffle
22862 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22865 unsigned SrcSize = SrcType.getScalarSizeInBits();
22867 APInt SplatValue, SplatUndef;
22868 unsigned SplatBitSize;
22870 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22871 SplatBitSize, HasAnyUndefs))
22874 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22875 // Make sure the splat matches the mask we expect
22876 if (SplatBitSize > ResSize ||
22877 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22880 // Make sure the input and output size make sense
22881 if (SrcSize >= ResSize || ResSize % SrcSize)
22884 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22885 // The number of u's between each two values depends on the ratio between
22886 // the source and dest type.
22887 unsigned ZextRatio = ResSize / SrcSize;
22888 bool IsZext = true;
22889 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22890 if (i % ZextRatio) {
22891 if (Shuffle->getMaskElt(i) > 0) {
22897 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22898 // Expected element number
22908 // Ok, perform the transformation - replace the shuffle with
22909 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22910 // (instead of undef) where the k elements come from the zero vector.
22911 SmallVector<int, 8> Mask;
22912 unsigned NumElems = SrcType.getVectorNumElements();
22913 for (unsigned i = 0; i < NumElems; ++i)
22915 Mask.push_back(NumElems);
22917 Mask.push_back(i / ZextRatio);
22919 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22920 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22921 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22924 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22925 TargetLowering::DAGCombinerInfo &DCI,
22926 const X86Subtarget *Subtarget) {
22927 if (DCI.isBeforeLegalizeOps())
22930 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22933 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22936 EVT VT = N->getValueType(0);
22937 SDValue N0 = N->getOperand(0);
22938 SDValue N1 = N->getOperand(1);
22941 // Create BEXTR instructions
22942 // BEXTR is ((X >> imm) & (2**size-1))
22943 if (VT == MVT::i32 || VT == MVT::i64) {
22944 // Check for BEXTR.
22945 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22946 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22947 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22948 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22949 if (MaskNode && ShiftNode) {
22950 uint64_t Mask = MaskNode->getZExtValue();
22951 uint64_t Shift = ShiftNode->getZExtValue();
22952 if (isMask_64(Mask)) {
22953 uint64_t MaskSize = countPopulation(Mask);
22954 if (Shift + MaskSize <= VT.getSizeInBits())
22955 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22956 DAG.getConstant(Shift | (MaskSize << 8), DL,
22965 // Want to form ANDNP nodes:
22966 // 1) In the hopes of then easily combining them with OR and AND nodes
22967 // to form PBLEND/PSIGN.
22968 // 2) To match ANDN packed intrinsics
22969 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22972 // Check LHS for vnot
22973 if (N0.getOpcode() == ISD::XOR &&
22974 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22975 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22976 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22978 // Check RHS for vnot
22979 if (N1.getOpcode() == ISD::XOR &&
22980 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22981 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22982 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22987 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22988 TargetLowering::DAGCombinerInfo &DCI,
22989 const X86Subtarget *Subtarget) {
22990 if (DCI.isBeforeLegalizeOps())
22993 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22997 SDValue N0 = N->getOperand(0);
22998 SDValue N1 = N->getOperand(1);
22999 EVT VT = N->getValueType(0);
23001 // look for psign/blend
23002 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23003 if (!Subtarget->hasSSSE3() ||
23004 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23007 // Canonicalize pandn to RHS
23008 if (N0.getOpcode() == X86ISD::ANDNP)
23010 // or (and (m, y), (pandn m, x))
23011 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23012 SDValue Mask = N1.getOperand(0);
23013 SDValue X = N1.getOperand(1);
23015 if (N0.getOperand(0) == Mask)
23016 Y = N0.getOperand(1);
23017 if (N0.getOperand(1) == Mask)
23018 Y = N0.getOperand(0);
23020 // Check to see if the mask appeared in both the AND and ANDNP and
23024 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23025 // Look through mask bitcast.
23026 if (Mask.getOpcode() == ISD::BITCAST)
23027 Mask = Mask.getOperand(0);
23028 if (X.getOpcode() == ISD::BITCAST)
23029 X = X.getOperand(0);
23030 if (Y.getOpcode() == ISD::BITCAST)
23031 Y = Y.getOperand(0);
23033 EVT MaskVT = Mask.getValueType();
23035 // Validate that the Mask operand is a vector sra node.
23036 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23037 // there is no psrai.b
23038 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23039 unsigned SraAmt = ~0;
23040 if (Mask.getOpcode() == ISD::SRA) {
23041 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23042 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23043 SraAmt = AmtConst->getZExtValue();
23044 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23045 SDValue SraC = Mask.getOperand(1);
23046 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23048 if ((SraAmt + 1) != EltBits)
23053 // Now we know we at least have a plendvb with the mask val. See if
23054 // we can form a psignb/w/d.
23055 // psign = x.type == y.type == mask.type && y = sub(0, x);
23056 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23057 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23058 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23059 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23060 "Unsupported VT for PSIGN");
23061 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23062 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23064 // PBLENDVB only available on SSE 4.1
23065 if (!Subtarget->hasSSE41())
23068 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23070 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23071 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23072 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23073 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23074 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23078 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23081 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23082 MachineFunction &MF = DAG.getMachineFunction();
23084 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23086 // SHLD/SHRD instructions have lower register pressure, but on some
23087 // platforms they have higher latency than the equivalent
23088 // series of shifts/or that would otherwise be generated.
23089 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23090 // have higher latencies and we are not optimizing for size.
23091 if (!OptForSize && Subtarget->isSHLDSlow())
23094 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23096 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23098 if (!N0.hasOneUse() || !N1.hasOneUse())
23101 SDValue ShAmt0 = N0.getOperand(1);
23102 if (ShAmt0.getValueType() != MVT::i8)
23104 SDValue ShAmt1 = N1.getOperand(1);
23105 if (ShAmt1.getValueType() != MVT::i8)
23107 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23108 ShAmt0 = ShAmt0.getOperand(0);
23109 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23110 ShAmt1 = ShAmt1.getOperand(0);
23113 unsigned Opc = X86ISD::SHLD;
23114 SDValue Op0 = N0.getOperand(0);
23115 SDValue Op1 = N1.getOperand(0);
23116 if (ShAmt0.getOpcode() == ISD::SUB) {
23117 Opc = X86ISD::SHRD;
23118 std::swap(Op0, Op1);
23119 std::swap(ShAmt0, ShAmt1);
23122 unsigned Bits = VT.getSizeInBits();
23123 if (ShAmt1.getOpcode() == ISD::SUB) {
23124 SDValue Sum = ShAmt1.getOperand(0);
23125 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23126 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23127 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23128 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23129 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23130 return DAG.getNode(Opc, DL, VT,
23132 DAG.getNode(ISD::TRUNCATE, DL,
23135 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23136 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23138 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23139 return DAG.getNode(Opc, DL, VT,
23140 N0.getOperand(0), N1.getOperand(0),
23141 DAG.getNode(ISD::TRUNCATE, DL,
23148 // Generate NEG and CMOV for integer abs.
23149 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23150 EVT VT = N->getValueType(0);
23152 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23153 // 8-bit integer abs to NEG and CMOV.
23154 if (VT.isInteger() && VT.getSizeInBits() == 8)
23157 SDValue N0 = N->getOperand(0);
23158 SDValue N1 = N->getOperand(1);
23161 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23162 // and change it to SUB and CMOV.
23163 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23164 N0.getOpcode() == ISD::ADD &&
23165 N0.getOperand(1) == N1 &&
23166 N1.getOpcode() == ISD::SRA &&
23167 N1.getOperand(0) == N0.getOperand(0))
23168 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23169 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23170 // Generate SUB & CMOV.
23171 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23172 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23174 SDValue Ops[] = { N0.getOperand(0), Neg,
23175 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23176 SDValue(Neg.getNode(), 1) };
23177 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23182 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23183 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23184 TargetLowering::DAGCombinerInfo &DCI,
23185 const X86Subtarget *Subtarget) {
23186 if (DCI.isBeforeLegalizeOps())
23189 if (Subtarget->hasCMov()) {
23190 SDValue RV = performIntegerAbsCombine(N, DAG);
23198 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23199 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23200 TargetLowering::DAGCombinerInfo &DCI,
23201 const X86Subtarget *Subtarget) {
23202 LoadSDNode *Ld = cast<LoadSDNode>(N);
23203 EVT RegVT = Ld->getValueType(0);
23204 EVT MemVT = Ld->getMemoryVT();
23206 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23208 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23209 // into two 16-byte operations.
23210 ISD::LoadExtType Ext = Ld->getExtensionType();
23211 unsigned Alignment = Ld->getAlignment();
23212 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23213 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23214 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23215 unsigned NumElems = RegVT.getVectorNumElements();
23219 SDValue Ptr = Ld->getBasePtr();
23220 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23222 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23224 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23225 Ld->getPointerInfo(), Ld->isVolatile(),
23226 Ld->isNonTemporal(), Ld->isInvariant(),
23228 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23229 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23230 Ld->getPointerInfo(), Ld->isVolatile(),
23231 Ld->isNonTemporal(), Ld->isInvariant(),
23232 std::min(16U, Alignment));
23233 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23235 Load2.getValue(1));
23237 SDValue NewVec = DAG.getUNDEF(RegVT);
23238 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23239 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23240 return DCI.CombineTo(N, NewVec, TF, true);
23246 /// PerformMLOADCombine - Resolve extending loads
23247 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23248 TargetLowering::DAGCombinerInfo &DCI,
23249 const X86Subtarget *Subtarget) {
23250 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23251 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23254 EVT VT = Mld->getValueType(0);
23255 unsigned NumElems = VT.getVectorNumElements();
23256 EVT LdVT = Mld->getMemoryVT();
23259 assert(LdVT != VT && "Cannot extend to the same type");
23260 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23261 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23262 // From, To sizes and ElemCount must be pow of two
23263 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23264 "Unexpected size for extending masked load");
23266 unsigned SizeRatio = ToSz / FromSz;
23267 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23269 // Create a type on which we perform the shuffle
23270 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23271 LdVT.getScalarType(), NumElems*SizeRatio);
23272 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23274 // Convert Src0 value
23275 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
23276 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23277 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23278 for (unsigned i = 0; i != NumElems; ++i)
23279 ShuffleVec[i] = i * SizeRatio;
23281 // Can't shuffle using an illegal type.
23282 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23283 && "WideVecVT should be legal");
23284 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23285 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23287 // Prepare the new mask
23289 SDValue Mask = Mld->getMask();
23290 if (Mask.getValueType() == VT) {
23291 // Mask and original value have the same type
23292 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23293 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23294 for (unsigned i = 0; i != NumElems; ++i)
23295 ShuffleVec[i] = i * SizeRatio;
23296 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23297 ShuffleVec[i] = NumElems*SizeRatio;
23298 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23299 DAG.getConstant(0, dl, WideVecVT),
23303 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23304 unsigned WidenNumElts = NumElems*SizeRatio;
23305 unsigned MaskNumElts = VT.getVectorNumElements();
23306 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23309 unsigned NumConcat = WidenNumElts / MaskNumElts;
23310 SmallVector<SDValue, 16> Ops(NumConcat);
23311 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23313 for (unsigned i = 1; i != NumConcat; ++i)
23316 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23319 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23320 Mld->getBasePtr(), NewMask, WideSrc0,
23321 Mld->getMemoryVT(), Mld->getMemOperand(),
23323 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23324 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23327 /// PerformMSTORECombine - Resolve truncating stores
23328 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23329 const X86Subtarget *Subtarget) {
23330 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23331 if (!Mst->isTruncatingStore())
23334 EVT VT = Mst->getValue().getValueType();
23335 unsigned NumElems = VT.getVectorNumElements();
23336 EVT StVT = Mst->getMemoryVT();
23339 assert(StVT != VT && "Cannot truncate to the same type");
23340 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23341 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23343 // From, To sizes and ElemCount must be pow of two
23344 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23345 "Unexpected size for truncating masked store");
23346 // We are going to use the original vector elt for storing.
23347 // Accumulated smaller vector elements must be a multiple of the store size.
23348 assert (((NumElems * FromSz) % ToSz) == 0 &&
23349 "Unexpected ratio for truncating masked store");
23351 unsigned SizeRatio = FromSz / ToSz;
23352 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23354 // Create a type on which we perform the shuffle
23355 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23356 StVT.getScalarType(), NumElems*SizeRatio);
23358 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23360 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
23361 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23362 for (unsigned i = 0; i != NumElems; ++i)
23363 ShuffleVec[i] = i * SizeRatio;
23365 // Can't shuffle using an illegal type.
23366 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23367 && "WideVecVT should be legal");
23369 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23370 DAG.getUNDEF(WideVecVT),
23374 SDValue Mask = Mst->getMask();
23375 if (Mask.getValueType() == VT) {
23376 // Mask and original value have the same type
23377 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23378 for (unsigned i = 0; i != NumElems; ++i)
23379 ShuffleVec[i] = i * SizeRatio;
23380 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23381 ShuffleVec[i] = NumElems*SizeRatio;
23382 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23383 DAG.getConstant(0, dl, WideVecVT),
23387 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23388 unsigned WidenNumElts = NumElems*SizeRatio;
23389 unsigned MaskNumElts = VT.getVectorNumElements();
23390 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23393 unsigned NumConcat = WidenNumElts / MaskNumElts;
23394 SmallVector<SDValue, 16> Ops(NumConcat);
23395 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23397 for (unsigned i = 1; i != NumConcat; ++i)
23400 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23403 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23404 NewMask, StVT, Mst->getMemOperand(), false);
23406 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23407 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23408 const X86Subtarget *Subtarget) {
23409 StoreSDNode *St = cast<StoreSDNode>(N);
23410 EVT VT = St->getValue().getValueType();
23411 EVT StVT = St->getMemoryVT();
23413 SDValue StoredVal = St->getOperand(1);
23414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23416 // If we are saving a concatenation of two XMM registers and 32-byte stores
23417 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23418 unsigned Alignment = St->getAlignment();
23419 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23420 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23421 StVT == VT && !IsAligned) {
23422 unsigned NumElems = VT.getVectorNumElements();
23426 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23427 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23429 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23430 SDValue Ptr0 = St->getBasePtr();
23431 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23433 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23434 St->getPointerInfo(), St->isVolatile(),
23435 St->isNonTemporal(), Alignment);
23436 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23437 St->getPointerInfo(), St->isVolatile(),
23438 St->isNonTemporal(),
23439 std::min(16U, Alignment));
23440 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23443 // Optimize trunc store (of multiple scalars) to shuffle and store.
23444 // First, pack all of the elements in one place. Next, store to memory
23445 // in fewer chunks.
23446 if (St->isTruncatingStore() && VT.isVector()) {
23447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23448 unsigned NumElems = VT.getVectorNumElements();
23449 assert(StVT != VT && "Cannot truncate to the same type");
23450 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23451 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23453 // From, To sizes and ElemCount must be pow of two
23454 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23455 // We are going to use the original vector elt for storing.
23456 // Accumulated smaller vector elements must be a multiple of the store size.
23457 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23459 unsigned SizeRatio = FromSz / ToSz;
23461 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23463 // Create a type on which we perform the shuffle
23464 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23465 StVT.getScalarType(), NumElems*SizeRatio);
23467 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23469 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23470 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23471 for (unsigned i = 0; i != NumElems; ++i)
23472 ShuffleVec[i] = i * SizeRatio;
23474 // Can't shuffle using an illegal type.
23475 if (!TLI.isTypeLegal(WideVecVT))
23478 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23479 DAG.getUNDEF(WideVecVT),
23481 // At this point all of the data is stored at the bottom of the
23482 // register. We now need to save it to mem.
23484 // Find the largest store unit
23485 MVT StoreType = MVT::i8;
23486 for (MVT Tp : MVT::integer_valuetypes()) {
23487 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23491 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23492 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23493 (64 <= NumElems * ToSz))
23494 StoreType = MVT::f64;
23496 // Bitcast the original vector into a vector of store-size units
23497 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23498 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23499 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23500 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23501 SmallVector<SDValue, 8> Chains;
23502 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23503 TLI.getPointerTy());
23504 SDValue Ptr = St->getBasePtr();
23506 // Perform one or more big stores into memory.
23507 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23508 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23509 StoreType, ShuffWide,
23510 DAG.getIntPtrConstant(i, dl));
23511 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23512 St->getPointerInfo(), St->isVolatile(),
23513 St->isNonTemporal(), St->getAlignment());
23514 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23515 Chains.push_back(Ch);
23518 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23521 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23522 // the FP state in cases where an emms may be missing.
23523 // A preferable solution to the general problem is to figure out the right
23524 // places to insert EMMS. This qualifies as a quick hack.
23526 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23527 if (VT.getSizeInBits() != 64)
23530 const Function *F = DAG.getMachineFunction().getFunction();
23531 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23533 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23534 if ((VT.isVector() ||
23535 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23536 isa<LoadSDNode>(St->getValue()) &&
23537 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23538 St->getChain().hasOneUse() && !St->isVolatile()) {
23539 SDNode* LdVal = St->getValue().getNode();
23540 LoadSDNode *Ld = nullptr;
23541 int TokenFactorIndex = -1;
23542 SmallVector<SDValue, 8> Ops;
23543 SDNode* ChainVal = St->getChain().getNode();
23544 // Must be a store of a load. We currently handle two cases: the load
23545 // is a direct child, and it's under an intervening TokenFactor. It is
23546 // possible to dig deeper under nested TokenFactors.
23547 if (ChainVal == LdVal)
23548 Ld = cast<LoadSDNode>(St->getChain());
23549 else if (St->getValue().hasOneUse() &&
23550 ChainVal->getOpcode() == ISD::TokenFactor) {
23551 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23552 if (ChainVal->getOperand(i).getNode() == LdVal) {
23553 TokenFactorIndex = i;
23554 Ld = cast<LoadSDNode>(St->getValue());
23556 Ops.push_back(ChainVal->getOperand(i));
23560 if (!Ld || !ISD::isNormalLoad(Ld))
23563 // If this is not the MMX case, i.e. we are just turning i64 load/store
23564 // into f64 load/store, avoid the transformation if there are multiple
23565 // uses of the loaded value.
23566 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23571 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23572 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23574 if (Subtarget->is64Bit() || F64IsLegal) {
23575 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23576 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23577 Ld->getPointerInfo(), Ld->isVolatile(),
23578 Ld->isNonTemporal(), Ld->isInvariant(),
23579 Ld->getAlignment());
23580 SDValue NewChain = NewLd.getValue(1);
23581 if (TokenFactorIndex != -1) {
23582 Ops.push_back(NewChain);
23583 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23585 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23586 St->getPointerInfo(),
23587 St->isVolatile(), St->isNonTemporal(),
23588 St->getAlignment());
23591 // Otherwise, lower to two pairs of 32-bit loads / stores.
23592 SDValue LoAddr = Ld->getBasePtr();
23593 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23594 DAG.getConstant(4, LdDL, MVT::i32));
23596 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23597 Ld->getPointerInfo(),
23598 Ld->isVolatile(), Ld->isNonTemporal(),
23599 Ld->isInvariant(), Ld->getAlignment());
23600 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23601 Ld->getPointerInfo().getWithOffset(4),
23602 Ld->isVolatile(), Ld->isNonTemporal(),
23604 MinAlign(Ld->getAlignment(), 4));
23606 SDValue NewChain = LoLd.getValue(1);
23607 if (TokenFactorIndex != -1) {
23608 Ops.push_back(LoLd);
23609 Ops.push_back(HiLd);
23610 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23613 LoAddr = St->getBasePtr();
23614 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23615 DAG.getConstant(4, StDL, MVT::i32));
23617 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23618 St->getPointerInfo(),
23619 St->isVolatile(), St->isNonTemporal(),
23620 St->getAlignment());
23621 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23622 St->getPointerInfo().getWithOffset(4),
23624 St->isNonTemporal(),
23625 MinAlign(St->getAlignment(), 4));
23626 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23629 // This is similar to the above case, but here we handle a scalar 64-bit
23630 // integer store that is extracted from a vector on a 32-bit target.
23631 // If we have SSE2, then we can treat it like a floating-point double
23632 // to get past legalization. The execution dependencies fixup pass will
23633 // choose the optimal machine instruction for the store if this really is
23634 // an integer or v2f32 rather than an f64.
23635 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23636 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23637 SDValue OldExtract = St->getOperand(1);
23638 SDValue ExtOp0 = OldExtract.getOperand(0);
23639 unsigned VecSize = ExtOp0.getValueSizeInBits();
23640 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23641 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23642 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23643 BitCast, OldExtract.getOperand(1));
23644 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23645 St->getPointerInfo(), St->isVolatile(),
23646 St->isNonTemporal(), St->getAlignment());
23652 /// Return 'true' if this vector operation is "horizontal"
23653 /// and return the operands for the horizontal operation in LHS and RHS. A
23654 /// horizontal operation performs the binary operation on successive elements
23655 /// of its first operand, then on successive elements of its second operand,
23656 /// returning the resulting values in a vector. For example, if
23657 /// A = < float a0, float a1, float a2, float a3 >
23659 /// B = < float b0, float b1, float b2, float b3 >
23660 /// then the result of doing a horizontal operation on A and B is
23661 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23662 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23663 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23664 /// set to A, RHS to B, and the routine returns 'true'.
23665 /// Note that the binary operation should have the property that if one of the
23666 /// operands is UNDEF then the result is UNDEF.
23667 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23668 // Look for the following pattern: if
23669 // A = < float a0, float a1, float a2, float a3 >
23670 // B = < float b0, float b1, float b2, float b3 >
23672 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23673 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23674 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23675 // which is A horizontal-op B.
23677 // At least one of the operands should be a vector shuffle.
23678 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23679 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23682 MVT VT = LHS.getSimpleValueType();
23684 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23685 "Unsupported vector type for horizontal add/sub");
23687 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23688 // operate independently on 128-bit lanes.
23689 unsigned NumElts = VT.getVectorNumElements();
23690 unsigned NumLanes = VT.getSizeInBits()/128;
23691 unsigned NumLaneElts = NumElts / NumLanes;
23692 assert((NumLaneElts % 2 == 0) &&
23693 "Vector type should have an even number of elements in each lane");
23694 unsigned HalfLaneElts = NumLaneElts/2;
23696 // View LHS in the form
23697 // LHS = VECTOR_SHUFFLE A, B, LMask
23698 // If LHS is not a shuffle then pretend it is the shuffle
23699 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23700 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23703 SmallVector<int, 16> LMask(NumElts);
23704 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23705 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23706 A = LHS.getOperand(0);
23707 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23708 B = LHS.getOperand(1);
23709 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23710 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23712 if (LHS.getOpcode() != ISD::UNDEF)
23714 for (unsigned i = 0; i != NumElts; ++i)
23718 // Likewise, view RHS in the form
23719 // RHS = VECTOR_SHUFFLE C, D, RMask
23721 SmallVector<int, 16> RMask(NumElts);
23722 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23723 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23724 C = RHS.getOperand(0);
23725 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23726 D = RHS.getOperand(1);
23727 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23728 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23730 if (RHS.getOpcode() != ISD::UNDEF)
23732 for (unsigned i = 0; i != NumElts; ++i)
23736 // Check that the shuffles are both shuffling the same vectors.
23737 if (!(A == C && B == D) && !(A == D && B == C))
23740 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23741 if (!A.getNode() && !B.getNode())
23744 // If A and B occur in reverse order in RHS, then "swap" them (which means
23745 // rewriting the mask).
23747 ShuffleVectorSDNode::commuteMask(RMask);
23749 // At this point LHS and RHS are equivalent to
23750 // LHS = VECTOR_SHUFFLE A, B, LMask
23751 // RHS = VECTOR_SHUFFLE A, B, RMask
23752 // Check that the masks correspond to performing a horizontal operation.
23753 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23754 for (unsigned i = 0; i != NumLaneElts; ++i) {
23755 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23757 // Ignore any UNDEF components.
23758 if (LIdx < 0 || RIdx < 0 ||
23759 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23760 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23763 // Check that successive elements are being operated on. If not, this is
23764 // not a horizontal operation.
23765 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23766 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23767 if (!(LIdx == Index && RIdx == Index + 1) &&
23768 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23773 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23774 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23778 /// Do target-specific dag combines on floating point adds.
23779 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23780 const X86Subtarget *Subtarget) {
23781 EVT VT = N->getValueType(0);
23782 SDValue LHS = N->getOperand(0);
23783 SDValue RHS = N->getOperand(1);
23785 // Try to synthesize horizontal adds from adds of shuffles.
23786 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23787 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23788 isHorizontalBinOp(LHS, RHS, true))
23789 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23793 /// Do target-specific dag combines on floating point subs.
23794 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23795 const X86Subtarget *Subtarget) {
23796 EVT VT = N->getValueType(0);
23797 SDValue LHS = N->getOperand(0);
23798 SDValue RHS = N->getOperand(1);
23800 // Try to synthesize horizontal subs from subs of shuffles.
23801 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23802 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23803 isHorizontalBinOp(LHS, RHS, false))
23804 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23808 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23809 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23810 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23812 // F[X]OR(0.0, x) -> x
23813 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23814 if (C->getValueAPF().isPosZero())
23815 return N->getOperand(1);
23817 // F[X]OR(x, 0.0) -> x
23818 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23819 if (C->getValueAPF().isPosZero())
23820 return N->getOperand(0);
23824 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23825 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23826 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23828 // Only perform optimizations if UnsafeMath is used.
23829 if (!DAG.getTarget().Options.UnsafeFPMath)
23832 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23833 // into FMINC and FMAXC, which are Commutative operations.
23834 unsigned NewOp = 0;
23835 switch (N->getOpcode()) {
23836 default: llvm_unreachable("unknown opcode");
23837 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23838 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23841 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23842 N->getOperand(0), N->getOperand(1));
23845 /// Do target-specific dag combines on X86ISD::FAND nodes.
23846 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23847 // FAND(0.0, x) -> 0.0
23848 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23849 if (C->getValueAPF().isPosZero())
23850 return N->getOperand(0);
23852 // FAND(x, 0.0) -> 0.0
23853 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23854 if (C->getValueAPF().isPosZero())
23855 return N->getOperand(1);
23860 /// Do target-specific dag combines on X86ISD::FANDN nodes
23861 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23862 // FANDN(0.0, x) -> x
23863 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23864 if (C->getValueAPF().isPosZero())
23865 return N->getOperand(1);
23867 // FANDN(x, 0.0) -> 0.0
23868 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23869 if (C->getValueAPF().isPosZero())
23870 return N->getOperand(1);
23875 static SDValue PerformBTCombine(SDNode *N,
23877 TargetLowering::DAGCombinerInfo &DCI) {
23878 // BT ignores high bits in the bit index operand.
23879 SDValue Op1 = N->getOperand(1);
23880 if (Op1.hasOneUse()) {
23881 unsigned BitWidth = Op1.getValueSizeInBits();
23882 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23883 APInt KnownZero, KnownOne;
23884 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23885 !DCI.isBeforeLegalizeOps());
23886 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23887 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23888 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23889 DCI.CommitTargetLoweringOpt(TLO);
23894 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23895 SDValue Op = N->getOperand(0);
23896 if (Op.getOpcode() == ISD::BITCAST)
23897 Op = Op.getOperand(0);
23898 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23899 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23900 VT.getVectorElementType().getSizeInBits() ==
23901 OpVT.getVectorElementType().getSizeInBits()) {
23902 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23907 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23908 const X86Subtarget *Subtarget) {
23909 EVT VT = N->getValueType(0);
23910 if (!VT.isVector())
23913 SDValue N0 = N->getOperand(0);
23914 SDValue N1 = N->getOperand(1);
23915 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23918 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23919 // both SSE and AVX2 since there is no sign-extended shift right
23920 // operation on a vector with 64-bit elements.
23921 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23922 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23923 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23924 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23925 SDValue N00 = N0.getOperand(0);
23927 // EXTLOAD has a better solution on AVX2,
23928 // it may be replaced with X86ISD::VSEXT node.
23929 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23930 if (!ISD::isNormalLoad(N00.getNode()))
23933 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23934 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23936 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23942 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23943 TargetLowering::DAGCombinerInfo &DCI,
23944 const X86Subtarget *Subtarget) {
23945 SDValue N0 = N->getOperand(0);
23946 EVT VT = N->getValueType(0);
23947 EVT SVT = VT.getScalarType();
23948 EVT InVT = N0->getValueType(0);
23949 EVT InSVT = InVT.getScalarType();
23952 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23953 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23954 // This exposes the sext to the sdivrem lowering, so that it directly extends
23955 // from AH (which we otherwise need to do contortions to access).
23956 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23957 InVT == MVT::i8 && VT == MVT::i32) {
23958 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23959 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
23960 N0.getOperand(0), N0.getOperand(1));
23961 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23962 return R.getValue(1);
23965 if (!DCI.isBeforeLegalizeOps()) {
23966 if (N0.getValueType() == MVT::i1) {
23967 SDValue Zero = DAG.getConstant(0, DL, VT);
23969 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
23970 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
23975 if (VT.isVector()) {
23976 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
23977 EVT InVT = N->getValueType(0);
23978 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
23979 128 / InVT.getScalarSizeInBits());
23980 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
23981 DAG.getUNDEF(InVT));
23983 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
23986 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
23987 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
23988 if (VT.getSizeInBits() == 128 &&
23989 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
23990 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
23991 SDValue ExOp = ExtendToVec128(DL, N0);
23992 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
23995 // On pre-AVX2 targets, split into 128-bit nodes of
23996 // ISD::SIGN_EXTEND_VECTOR_INREG.
23997 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
23998 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
23999 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24000 unsigned NumVecs = VT.getSizeInBits() / 128;
24001 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24002 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24003 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24005 SmallVector<SDValue, 8> Opnds;
24006 for (unsigned i = 0, Offset = 0; i != NumVecs;
24007 ++i, Offset += NumSubElts) {
24008 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24009 DAG.getIntPtrConstant(Offset, DL));
24010 SrcVec = ExtendToVec128(DL, SrcVec);
24011 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24012 Opnds.push_back(SrcVec);
24014 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24018 if (!Subtarget->hasFp256())
24021 if (VT.isVector() && VT.getSizeInBits() == 256) {
24022 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24030 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24031 const X86Subtarget* Subtarget) {
24033 EVT VT = N->getValueType(0);
24035 // Let legalize expand this if it isn't a legal type yet.
24036 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24039 EVT ScalarVT = VT.getScalarType();
24040 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24041 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24044 SDValue A = N->getOperand(0);
24045 SDValue B = N->getOperand(1);
24046 SDValue C = N->getOperand(2);
24048 bool NegA = (A.getOpcode() == ISD::FNEG);
24049 bool NegB = (B.getOpcode() == ISD::FNEG);
24050 bool NegC = (C.getOpcode() == ISD::FNEG);
24052 // Negative multiplication when NegA xor NegB
24053 bool NegMul = (NegA != NegB);
24055 A = A.getOperand(0);
24057 B = B.getOperand(0);
24059 C = C.getOperand(0);
24063 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24065 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24067 return DAG.getNode(Opcode, dl, VT, A, B, C);
24070 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24071 TargetLowering::DAGCombinerInfo &DCI,
24072 const X86Subtarget *Subtarget) {
24073 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24074 // (and (i32 x86isd::setcc_carry), 1)
24075 // This eliminates the zext. This transformation is necessary because
24076 // ISD::SETCC is always legalized to i8.
24078 SDValue N0 = N->getOperand(0);
24079 EVT VT = N->getValueType(0);
24081 if (N0.getOpcode() == ISD::AND &&
24083 N0.getOperand(0).hasOneUse()) {
24084 SDValue N00 = N0.getOperand(0);
24085 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24086 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24087 if (!C || C->getZExtValue() != 1)
24089 return DAG.getNode(ISD::AND, dl, VT,
24090 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24091 N00.getOperand(0), N00.getOperand(1)),
24092 DAG.getConstant(1, dl, VT));
24096 if (N0.getOpcode() == ISD::TRUNCATE &&
24098 N0.getOperand(0).hasOneUse()) {
24099 SDValue N00 = N0.getOperand(0);
24100 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24101 return DAG.getNode(ISD::AND, dl, VT,
24102 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24103 N00.getOperand(0), N00.getOperand(1)),
24104 DAG.getConstant(1, dl, VT));
24107 if (VT.is256BitVector()) {
24108 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24113 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24114 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24115 // This exposes the zext to the udivrem lowering, so that it directly extends
24116 // from AH (which we otherwise need to do contortions to access).
24117 if (N0.getOpcode() == ISD::UDIVREM &&
24118 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24119 (VT == MVT::i32 || VT == MVT::i64)) {
24120 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24121 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24122 N0.getOperand(0), N0.getOperand(1));
24123 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24124 return R.getValue(1);
24130 // Optimize x == -y --> x+y == 0
24131 // x != -y --> x+y != 0
24132 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24133 const X86Subtarget* Subtarget) {
24134 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24135 SDValue LHS = N->getOperand(0);
24136 SDValue RHS = N->getOperand(1);
24137 EVT VT = N->getValueType(0);
24140 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24141 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24142 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24143 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24144 LHS.getOperand(1));
24145 return DAG.getSetCC(DL, N->getValueType(0), addV,
24146 DAG.getConstant(0, DL, addV.getValueType()), CC);
24148 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24150 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24151 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24152 RHS.getOperand(1));
24153 return DAG.getSetCC(DL, N->getValueType(0), addV,
24154 DAG.getConstant(0, DL, addV.getValueType()), CC);
24157 if (VT.getScalarType() == MVT::i1 &&
24158 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24160 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24161 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24162 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24164 if (!IsSEXT0 || !IsVZero1) {
24165 // Swap the operands and update the condition code.
24166 std::swap(LHS, RHS);
24167 CC = ISD::getSetCCSwappedOperands(CC);
24169 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24170 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24171 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24174 if (IsSEXT0 && IsVZero1) {
24175 assert(VT == LHS.getOperand(0).getValueType() &&
24176 "Uexpected operand type");
24177 if (CC == ISD::SETGT)
24178 return DAG.getConstant(0, DL, VT);
24179 if (CC == ISD::SETLE)
24180 return DAG.getConstant(1, DL, VT);
24181 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24182 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24184 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24185 "Unexpected condition code!");
24186 return LHS.getOperand(0);
24193 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24194 SelectionDAG &DAG) {
24196 MVT VT = Load->getSimpleValueType(0);
24197 MVT EVT = VT.getVectorElementType();
24198 SDValue Addr = Load->getOperand(1);
24199 SDValue NewAddr = DAG.getNode(
24200 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24201 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24202 Addr.getSimpleValueType()));
24205 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24206 DAG.getMachineFunction().getMachineMemOperand(
24207 Load->getMemOperand(), 0, EVT.getStoreSize()));
24211 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24212 const X86Subtarget *Subtarget) {
24214 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24215 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24216 "X86insertps is only defined for v4x32");
24218 SDValue Ld = N->getOperand(1);
24219 if (MayFoldLoad(Ld)) {
24220 // Extract the countS bits from the immediate so we can get the proper
24221 // address when narrowing the vector load to a specific element.
24222 // When the second source op is a memory address, insertps doesn't use
24223 // countS and just gets an f32 from that address.
24224 unsigned DestIndex =
24225 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24227 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24229 // Create this as a scalar to vector to match the instruction pattern.
24230 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24231 // countS bits are ignored when loading from memory on insertps, which
24232 // means we don't need to explicitly set them to 0.
24233 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24234 LoadScalarToVector, N->getOperand(2));
24239 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24240 SDValue V0 = N->getOperand(0);
24241 SDValue V1 = N->getOperand(1);
24243 EVT VT = N->getValueType(0);
24245 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24246 // operands and changing the mask to 1. This saves us a bunch of
24247 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24248 // x86InstrInfo knows how to commute this back after instruction selection
24249 // if it would help register allocation.
24251 // TODO: If optimizing for size or a processor that doesn't suffer from
24252 // partial register update stalls, this should be transformed into a MOVSD
24253 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24255 if (VT == MVT::v2f64)
24256 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24257 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24258 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24259 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24265 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24266 // as "sbb reg,reg", since it can be extended without zext and produces
24267 // an all-ones bit which is more useful than 0/1 in some cases.
24268 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24271 return DAG.getNode(ISD::AND, DL, VT,
24272 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24273 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24275 DAG.getConstant(1, DL, VT));
24276 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24277 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24278 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24279 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24283 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24284 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24285 TargetLowering::DAGCombinerInfo &DCI,
24286 const X86Subtarget *Subtarget) {
24288 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24289 SDValue EFLAGS = N->getOperand(1);
24291 if (CC == X86::COND_A) {
24292 // Try to convert COND_A into COND_B in an attempt to facilitate
24293 // materializing "setb reg".
24295 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24296 // cannot take an immediate as its first operand.
24298 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24299 EFLAGS.getValueType().isInteger() &&
24300 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24301 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24302 EFLAGS.getNode()->getVTList(),
24303 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24304 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24305 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24309 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24310 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24312 if (CC == X86::COND_B)
24313 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24317 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24318 if (Flags.getNode()) {
24319 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24320 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24326 // Optimize branch condition evaluation.
24328 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24329 TargetLowering::DAGCombinerInfo &DCI,
24330 const X86Subtarget *Subtarget) {
24332 SDValue Chain = N->getOperand(0);
24333 SDValue Dest = N->getOperand(1);
24334 SDValue EFLAGS = N->getOperand(3);
24335 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24339 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24340 if (Flags.getNode()) {
24341 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24342 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24349 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24350 SelectionDAG &DAG) {
24351 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24352 // optimize away operation when it's from a constant.
24354 // The general transformation is:
24355 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24356 // AND(VECTOR_CMP(x,y), constant2)
24357 // constant2 = UNARYOP(constant)
24359 // Early exit if this isn't a vector operation, the operand of the
24360 // unary operation isn't a bitwise AND, or if the sizes of the operations
24361 // aren't the same.
24362 EVT VT = N->getValueType(0);
24363 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24364 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24365 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24368 // Now check that the other operand of the AND is a constant. We could
24369 // make the transformation for non-constant splats as well, but it's unclear
24370 // that would be a benefit as it would not eliminate any operations, just
24371 // perform one more step in scalar code before moving to the vector unit.
24372 if (BuildVectorSDNode *BV =
24373 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24374 // Bail out if the vector isn't a constant.
24375 if (!BV->isConstant())
24378 // Everything checks out. Build up the new and improved node.
24380 EVT IntVT = BV->getValueType(0);
24381 // Create a new constant of the appropriate type for the transformed
24383 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24384 // The AND node needs bitcasts to/from an integer vector type around it.
24385 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24386 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24387 N->getOperand(0)->getOperand(0), MaskConst);
24388 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24395 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24396 const X86Subtarget *Subtarget) {
24397 // First try to optimize away the conversion entirely when it's
24398 // conditionally from a constant. Vectors only.
24399 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24400 if (Res != SDValue())
24403 // Now move on to more general possibilities.
24404 SDValue Op0 = N->getOperand(0);
24405 EVT InVT = Op0->getValueType(0);
24407 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24408 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24410 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24411 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24412 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24415 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24416 // a 32-bit target where SSE doesn't support i64->FP operations.
24417 if (Op0.getOpcode() == ISD::LOAD) {
24418 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24419 EVT VT = Ld->getValueType(0);
24421 // This transformation is not supported if the result type is f16
24422 if (N->getValueType(0) == MVT::f16)
24425 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24426 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24427 !Subtarget->is64Bit() && VT == MVT::i64) {
24428 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24429 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24430 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24437 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24438 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24439 X86TargetLowering::DAGCombinerInfo &DCI) {
24440 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24441 // the result is either zero or one (depending on the input carry bit).
24442 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24443 if (X86::isZeroNode(N->getOperand(0)) &&
24444 X86::isZeroNode(N->getOperand(1)) &&
24445 // We don't have a good way to replace an EFLAGS use, so only do this when
24447 SDValue(N, 1).use_empty()) {
24449 EVT VT = N->getValueType(0);
24450 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24451 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24452 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24453 DAG.getConstant(X86::COND_B, DL,
24456 DAG.getConstant(1, DL, VT));
24457 return DCI.CombineTo(N, Res1, CarryOut);
24463 // fold (add Y, (sete X, 0)) -> adc 0, Y
24464 // (add Y, (setne X, 0)) -> sbb -1, Y
24465 // (sub (sete X, 0), Y) -> sbb 0, Y
24466 // (sub (setne X, 0), Y) -> adc -1, Y
24467 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24470 // Look through ZExts.
24471 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24472 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24475 SDValue SetCC = Ext.getOperand(0);
24476 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24479 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24480 if (CC != X86::COND_E && CC != X86::COND_NE)
24483 SDValue Cmp = SetCC.getOperand(1);
24484 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24485 !X86::isZeroNode(Cmp.getOperand(1)) ||
24486 !Cmp.getOperand(0).getValueType().isInteger())
24489 SDValue CmpOp0 = Cmp.getOperand(0);
24490 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24491 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24493 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24494 if (CC == X86::COND_NE)
24495 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24496 DL, OtherVal.getValueType(), OtherVal,
24497 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24499 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24500 DL, OtherVal.getValueType(), OtherVal,
24501 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24504 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24505 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24506 const X86Subtarget *Subtarget) {
24507 EVT VT = N->getValueType(0);
24508 SDValue Op0 = N->getOperand(0);
24509 SDValue Op1 = N->getOperand(1);
24511 // Try to synthesize horizontal adds from adds of shuffles.
24512 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24513 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24514 isHorizontalBinOp(Op0, Op1, true))
24515 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24517 return OptimizeConditionalInDecrement(N, DAG);
24520 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24521 const X86Subtarget *Subtarget) {
24522 SDValue Op0 = N->getOperand(0);
24523 SDValue Op1 = N->getOperand(1);
24525 // X86 can't encode an immediate LHS of a sub. See if we can push the
24526 // negation into a preceding instruction.
24527 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24528 // If the RHS of the sub is a XOR with one use and a constant, invert the
24529 // immediate. Then add one to the LHS of the sub so we can turn
24530 // X-Y -> X+~Y+1, saving one register.
24531 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24532 isa<ConstantSDNode>(Op1.getOperand(1))) {
24533 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24534 EVT VT = Op0.getValueType();
24535 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24537 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24538 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24539 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24543 // Try to synthesize horizontal adds from adds of shuffles.
24544 EVT VT = N->getValueType(0);
24545 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24546 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24547 isHorizontalBinOp(Op0, Op1, true))
24548 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24550 return OptimizeConditionalInDecrement(N, DAG);
24553 /// performVZEXTCombine - Performs build vector combines
24554 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24555 TargetLowering::DAGCombinerInfo &DCI,
24556 const X86Subtarget *Subtarget) {
24558 MVT VT = N->getSimpleValueType(0);
24559 SDValue Op = N->getOperand(0);
24560 MVT OpVT = Op.getSimpleValueType();
24561 MVT OpEltVT = OpVT.getVectorElementType();
24562 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24564 // (vzext (bitcast (vzext (x)) -> (vzext x)
24566 while (V.getOpcode() == ISD::BITCAST)
24567 V = V.getOperand(0);
24569 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24570 MVT InnerVT = V.getSimpleValueType();
24571 MVT InnerEltVT = InnerVT.getVectorElementType();
24573 // If the element sizes match exactly, we can just do one larger vzext. This
24574 // is always an exact type match as vzext operates on integer types.
24575 if (OpEltVT == InnerEltVT) {
24576 assert(OpVT == InnerVT && "Types must match for vzext!");
24577 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24580 // The only other way we can combine them is if only a single element of the
24581 // inner vzext is used in the input to the outer vzext.
24582 if (InnerEltVT.getSizeInBits() < InputBits)
24585 // In this case, the inner vzext is completely dead because we're going to
24586 // only look at bits inside of the low element. Just do the outer vzext on
24587 // a bitcast of the input to the inner.
24588 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24589 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24592 // Check if we can bypass extracting and re-inserting an element of an input
24593 // vector. Essentialy:
24594 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24595 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24596 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24597 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24598 SDValue ExtractedV = V.getOperand(0);
24599 SDValue OrigV = ExtractedV.getOperand(0);
24600 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24601 if (ExtractIdx->getZExtValue() == 0) {
24602 MVT OrigVT = OrigV.getSimpleValueType();
24603 // Extract a subvector if necessary...
24604 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24605 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24606 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24607 OrigVT.getVectorNumElements() / Ratio);
24608 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24609 DAG.getIntPtrConstant(0, DL));
24611 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24612 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24619 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24620 DAGCombinerInfo &DCI) const {
24621 SelectionDAG &DAG = DCI.DAG;
24622 switch (N->getOpcode()) {
24624 case ISD::EXTRACT_VECTOR_ELT:
24625 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24628 case X86ISD::SHRUNKBLEND:
24629 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24630 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24631 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24632 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24633 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24634 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24635 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24638 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24639 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24640 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24641 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24642 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24643 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24644 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24645 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24646 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24647 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24648 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24650 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24652 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24653 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24654 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24655 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24656 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24657 case ISD::ANY_EXTEND:
24658 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24659 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24660 case ISD::SIGN_EXTEND_INREG:
24661 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24662 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24663 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24664 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24665 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24666 case X86ISD::SHUFP: // Handle all target specific shuffles
24667 case X86ISD::PALIGNR:
24668 case X86ISD::UNPCKH:
24669 case X86ISD::UNPCKL:
24670 case X86ISD::MOVHLPS:
24671 case X86ISD::MOVLHPS:
24672 case X86ISD::PSHUFB:
24673 case X86ISD::PSHUFD:
24674 case X86ISD::PSHUFHW:
24675 case X86ISD::PSHUFLW:
24676 case X86ISD::MOVSS:
24677 case X86ISD::MOVSD:
24678 case X86ISD::VPERMILPI:
24679 case X86ISD::VPERM2X128:
24680 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24681 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24682 case ISD::INTRINSIC_WO_CHAIN:
24683 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24684 case X86ISD::INSERTPS: {
24685 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24686 return PerformINSERTPSCombine(N, DAG, Subtarget);
24689 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24695 /// isTypeDesirableForOp - Return true if the target has native support for
24696 /// the specified value type and it is 'desirable' to use the type for the
24697 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24698 /// instruction encodings are longer and some i16 instructions are slow.
24699 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24700 if (!isTypeLegal(VT))
24702 if (VT != MVT::i16)
24709 case ISD::SIGN_EXTEND:
24710 case ISD::ZERO_EXTEND:
24711 case ISD::ANY_EXTEND:
24724 /// IsDesirableToPromoteOp - This method query the target whether it is
24725 /// beneficial for dag combiner to promote the specified node. If true, it
24726 /// should return the desired promotion type by reference.
24727 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24728 EVT VT = Op.getValueType();
24729 if (VT != MVT::i16)
24732 bool Promote = false;
24733 bool Commute = false;
24734 switch (Op.getOpcode()) {
24737 LoadSDNode *LD = cast<LoadSDNode>(Op);
24738 // If the non-extending load has a single use and it's not live out, then it
24739 // might be folded.
24740 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24741 Op.hasOneUse()*/) {
24742 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24743 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24744 // The only case where we'd want to promote LOAD (rather then it being
24745 // promoted as an operand is when it's only use is liveout.
24746 if (UI->getOpcode() != ISD::CopyToReg)
24753 case ISD::SIGN_EXTEND:
24754 case ISD::ZERO_EXTEND:
24755 case ISD::ANY_EXTEND:
24760 SDValue N0 = Op.getOperand(0);
24761 // Look out for (store (shl (load), x)).
24762 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24775 SDValue N0 = Op.getOperand(0);
24776 SDValue N1 = Op.getOperand(1);
24777 if (!Commute && MayFoldLoad(N1))
24779 // Avoid disabling potential load folding opportunities.
24780 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24782 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24792 //===----------------------------------------------------------------------===//
24793 // X86 Inline Assembly Support
24794 //===----------------------------------------------------------------------===//
24796 // Helper to match a string separated by whitespace.
24797 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24798 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24800 for (StringRef Piece : Pieces) {
24801 if (!S.startswith(Piece)) // Check if the piece matches.
24804 S = S.substr(Piece.size());
24805 StringRef::size_type Pos = S.find_first_not_of(" \t");
24806 if (Pos == 0) // We matched a prefix.
24815 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24817 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24818 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24819 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24820 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24822 if (AsmPieces.size() == 3)
24824 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24831 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24832 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24834 std::string AsmStr = IA->getAsmString();
24836 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24837 if (!Ty || Ty->getBitWidth() % 16 != 0)
24840 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24841 SmallVector<StringRef, 4> AsmPieces;
24842 SplitString(AsmStr, AsmPieces, ";\n");
24844 switch (AsmPieces.size()) {
24845 default: return false;
24847 // FIXME: this should verify that we are targeting a 486 or better. If not,
24848 // we will turn this bswap into something that will be lowered to logical
24849 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24850 // lower so don't worry about this.
24852 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24853 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24854 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24855 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24856 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24857 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24858 // No need to check constraints, nothing other than the equivalent of
24859 // "=r,0" would be valid here.
24860 return IntrinsicLowering::LowerToByteSwap(CI);
24863 // rorw $$8, ${0:w} --> llvm.bswap.i16
24864 if (CI->getType()->isIntegerTy(16) &&
24865 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24866 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24867 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24869 const std::string &ConstraintsStr = IA->getConstraintString();
24870 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24871 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24872 if (clobbersFlagRegisters(AsmPieces))
24873 return IntrinsicLowering::LowerToByteSwap(CI);
24877 if (CI->getType()->isIntegerTy(32) &&
24878 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24879 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24880 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24881 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24883 const std::string &ConstraintsStr = IA->getConstraintString();
24884 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24885 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24886 if (clobbersFlagRegisters(AsmPieces))
24887 return IntrinsicLowering::LowerToByteSwap(CI);
24890 if (CI->getType()->isIntegerTy(64)) {
24891 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24892 if (Constraints.size() >= 2 &&
24893 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24894 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24895 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24896 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24897 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24898 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24899 return IntrinsicLowering::LowerToByteSwap(CI);
24907 /// getConstraintType - Given a constraint letter, return the type of
24908 /// constraint it is for this target.
24909 X86TargetLowering::ConstraintType
24910 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24911 if (Constraint.size() == 1) {
24912 switch (Constraint[0]) {
24923 return C_RegisterClass;
24947 return TargetLowering::getConstraintType(Constraint);
24950 /// Examine constraint type and operand type and determine a weight value.
24951 /// This object must already have been set up with the operand type
24952 /// and the current alternative constraint selected.
24953 TargetLowering::ConstraintWeight
24954 X86TargetLowering::getSingleConstraintMatchWeight(
24955 AsmOperandInfo &info, const char *constraint) const {
24956 ConstraintWeight weight = CW_Invalid;
24957 Value *CallOperandVal = info.CallOperandVal;
24958 // If we don't have a value, we can't do a match,
24959 // but allow it at the lowest weight.
24960 if (!CallOperandVal)
24962 Type *type = CallOperandVal->getType();
24963 // Look at the constraint type.
24964 switch (*constraint) {
24966 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24977 if (CallOperandVal->getType()->isIntegerTy())
24978 weight = CW_SpecificReg;
24983 if (type->isFloatingPointTy())
24984 weight = CW_SpecificReg;
24987 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24988 weight = CW_SpecificReg;
24992 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24993 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24994 weight = CW_Register;
24997 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24998 if (C->getZExtValue() <= 31)
24999 weight = CW_Constant;
25003 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25004 if (C->getZExtValue() <= 63)
25005 weight = CW_Constant;
25009 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25010 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25011 weight = CW_Constant;
25015 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25016 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25017 weight = CW_Constant;
25021 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25022 if (C->getZExtValue() <= 3)
25023 weight = CW_Constant;
25027 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25028 if (C->getZExtValue() <= 0xff)
25029 weight = CW_Constant;
25034 if (isa<ConstantFP>(CallOperandVal)) {
25035 weight = CW_Constant;
25039 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25040 if ((C->getSExtValue() >= -0x80000000LL) &&
25041 (C->getSExtValue() <= 0x7fffffffLL))
25042 weight = CW_Constant;
25046 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25047 if (C->getZExtValue() <= 0xffffffff)
25048 weight = CW_Constant;
25055 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25056 /// with another that has more specific requirements based on the type of the
25057 /// corresponding operand.
25058 const char *X86TargetLowering::
25059 LowerXConstraint(EVT ConstraintVT) const {
25060 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25061 // 'f' like normal targets.
25062 if (ConstraintVT.isFloatingPoint()) {
25063 if (Subtarget->hasSSE2())
25065 if (Subtarget->hasSSE1())
25069 return TargetLowering::LowerXConstraint(ConstraintVT);
25072 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25073 /// vector. If it is invalid, don't add anything to Ops.
25074 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25075 std::string &Constraint,
25076 std::vector<SDValue>&Ops,
25077 SelectionDAG &DAG) const {
25080 // Only support length 1 constraints for now.
25081 if (Constraint.length() > 1) return;
25083 char ConstraintLetter = Constraint[0];
25084 switch (ConstraintLetter) {
25087 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25088 if (C->getZExtValue() <= 31) {
25089 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25090 Op.getValueType());
25096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25097 if (C->getZExtValue() <= 63) {
25098 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25099 Op.getValueType());
25105 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25106 if (isInt<8>(C->getSExtValue())) {
25107 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25108 Op.getValueType());
25114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25115 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25116 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25117 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25118 Op.getValueType());
25124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25125 if (C->getZExtValue() <= 3) {
25126 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25127 Op.getValueType());
25133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25134 if (C->getZExtValue() <= 255) {
25135 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25136 Op.getValueType());
25142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25143 if (C->getZExtValue() <= 127) {
25144 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25145 Op.getValueType());
25151 // 32-bit signed value
25152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25153 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25154 C->getSExtValue())) {
25155 // Widen to 64 bits here to get it sign extended.
25156 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25159 // FIXME gcc accepts some relocatable values here too, but only in certain
25160 // memory models; it's complicated.
25165 // 32-bit unsigned value
25166 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25167 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25168 C->getZExtValue())) {
25169 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25170 Op.getValueType());
25174 // FIXME gcc accepts some relocatable values here too, but only in certain
25175 // memory models; it's complicated.
25179 // Literal immediates are always ok.
25180 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25181 // Widen to 64 bits here to get it sign extended.
25182 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25186 // In any sort of PIC mode addresses need to be computed at runtime by
25187 // adding in a register or some sort of table lookup. These can't
25188 // be used as immediates.
25189 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25192 // If we are in non-pic codegen mode, we allow the address of a global (with
25193 // an optional displacement) to be used with 'i'.
25194 GlobalAddressSDNode *GA = nullptr;
25195 int64_t Offset = 0;
25197 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25199 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25200 Offset += GA->getOffset();
25202 } else if (Op.getOpcode() == ISD::ADD) {
25203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25204 Offset += C->getZExtValue();
25205 Op = Op.getOperand(0);
25208 } else if (Op.getOpcode() == ISD::SUB) {
25209 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25210 Offset += -C->getZExtValue();
25211 Op = Op.getOperand(0);
25216 // Otherwise, this isn't something we can handle, reject it.
25220 const GlobalValue *GV = GA->getGlobal();
25221 // If we require an extra load to get this address, as in PIC mode, we
25222 // can't accept it.
25223 if (isGlobalStubReference(
25224 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25227 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25228 GA->getValueType(0), Offset);
25233 if (Result.getNode()) {
25234 Ops.push_back(Result);
25237 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25240 std::pair<unsigned, const TargetRegisterClass *>
25241 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25242 const std::string &Constraint,
25244 // First, see if this is a constraint that directly corresponds to an LLVM
25246 if (Constraint.size() == 1) {
25247 // GCC Constraint Letters
25248 switch (Constraint[0]) {
25250 // TODO: Slight differences here in allocation order and leaving
25251 // RIP in the class. Do they matter any more here than they do
25252 // in the normal allocation?
25253 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25254 if (Subtarget->is64Bit()) {
25255 if (VT == MVT::i32 || VT == MVT::f32)
25256 return std::make_pair(0U, &X86::GR32RegClass);
25257 if (VT == MVT::i16)
25258 return std::make_pair(0U, &X86::GR16RegClass);
25259 if (VT == MVT::i8 || VT == MVT::i1)
25260 return std::make_pair(0U, &X86::GR8RegClass);
25261 if (VT == MVT::i64 || VT == MVT::f64)
25262 return std::make_pair(0U, &X86::GR64RegClass);
25265 // 32-bit fallthrough
25266 case 'Q': // Q_REGS
25267 if (VT == MVT::i32 || VT == MVT::f32)
25268 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25269 if (VT == MVT::i16)
25270 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25271 if (VT == MVT::i8 || VT == MVT::i1)
25272 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25273 if (VT == MVT::i64)
25274 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25276 case 'r': // GENERAL_REGS
25277 case 'l': // INDEX_REGS
25278 if (VT == MVT::i8 || VT == MVT::i1)
25279 return std::make_pair(0U, &X86::GR8RegClass);
25280 if (VT == MVT::i16)
25281 return std::make_pair(0U, &X86::GR16RegClass);
25282 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25283 return std::make_pair(0U, &X86::GR32RegClass);
25284 return std::make_pair(0U, &X86::GR64RegClass);
25285 case 'R': // LEGACY_REGS
25286 if (VT == MVT::i8 || VT == MVT::i1)
25287 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25288 if (VT == MVT::i16)
25289 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25290 if (VT == MVT::i32 || !Subtarget->is64Bit())
25291 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25292 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25293 case 'f': // FP Stack registers.
25294 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25295 // value to the correct fpstack register class.
25296 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25297 return std::make_pair(0U, &X86::RFP32RegClass);
25298 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25299 return std::make_pair(0U, &X86::RFP64RegClass);
25300 return std::make_pair(0U, &X86::RFP80RegClass);
25301 case 'y': // MMX_REGS if MMX allowed.
25302 if (!Subtarget->hasMMX()) break;
25303 return std::make_pair(0U, &X86::VR64RegClass);
25304 case 'Y': // SSE_REGS if SSE2 allowed
25305 if (!Subtarget->hasSSE2()) break;
25307 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25308 if (!Subtarget->hasSSE1()) break;
25310 switch (VT.SimpleTy) {
25312 // Scalar SSE types.
25315 return std::make_pair(0U, &X86::FR32RegClass);
25318 return std::make_pair(0U, &X86::FR64RegClass);
25326 return std::make_pair(0U, &X86::VR128RegClass);
25334 return std::make_pair(0U, &X86::VR256RegClass);
25339 return std::make_pair(0U, &X86::VR512RegClass);
25345 // Use the default implementation in TargetLowering to convert the register
25346 // constraint into a member of a register class.
25347 std::pair<unsigned, const TargetRegisterClass*> Res;
25348 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25350 // Not found as a standard register?
25352 // Map st(0) -> st(7) -> ST0
25353 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25354 tolower(Constraint[1]) == 's' &&
25355 tolower(Constraint[2]) == 't' &&
25356 Constraint[3] == '(' &&
25357 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25358 Constraint[5] == ')' &&
25359 Constraint[6] == '}') {
25361 Res.first = X86::FP0+Constraint[4]-'0';
25362 Res.second = &X86::RFP80RegClass;
25366 // GCC allows "st(0)" to be called just plain "st".
25367 if (StringRef("{st}").equals_lower(Constraint)) {
25368 Res.first = X86::FP0;
25369 Res.second = &X86::RFP80RegClass;
25374 if (StringRef("{flags}").equals_lower(Constraint)) {
25375 Res.first = X86::EFLAGS;
25376 Res.second = &X86::CCRRegClass;
25380 // 'A' means EAX + EDX.
25381 if (Constraint == "A") {
25382 Res.first = X86::EAX;
25383 Res.second = &X86::GR32_ADRegClass;
25389 // Otherwise, check to see if this is a register class of the wrong value
25390 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25391 // turn into {ax},{dx}.
25392 if (Res.second->hasType(VT))
25393 return Res; // Correct type already, nothing to do.
25395 // All of the single-register GCC register classes map their values onto
25396 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25397 // really want an 8-bit or 32-bit register, map to the appropriate register
25398 // class and return the appropriate register.
25399 if (Res.second == &X86::GR16RegClass) {
25400 if (VT == MVT::i8 || VT == MVT::i1) {
25401 unsigned DestReg = 0;
25402 switch (Res.first) {
25404 case X86::AX: DestReg = X86::AL; break;
25405 case X86::DX: DestReg = X86::DL; break;
25406 case X86::CX: DestReg = X86::CL; break;
25407 case X86::BX: DestReg = X86::BL; break;
25410 Res.first = DestReg;
25411 Res.second = &X86::GR8RegClass;
25413 } else if (VT == MVT::i32 || VT == MVT::f32) {
25414 unsigned DestReg = 0;
25415 switch (Res.first) {
25417 case X86::AX: DestReg = X86::EAX; break;
25418 case X86::DX: DestReg = X86::EDX; break;
25419 case X86::CX: DestReg = X86::ECX; break;
25420 case X86::BX: DestReg = X86::EBX; break;
25421 case X86::SI: DestReg = X86::ESI; break;
25422 case X86::DI: DestReg = X86::EDI; break;
25423 case X86::BP: DestReg = X86::EBP; break;
25424 case X86::SP: DestReg = X86::ESP; break;
25427 Res.first = DestReg;
25428 Res.second = &X86::GR32RegClass;
25430 } else if (VT == MVT::i64 || VT == MVT::f64) {
25431 unsigned DestReg = 0;
25432 switch (Res.first) {
25434 case X86::AX: DestReg = X86::RAX; break;
25435 case X86::DX: DestReg = X86::RDX; break;
25436 case X86::CX: DestReg = X86::RCX; break;
25437 case X86::BX: DestReg = X86::RBX; break;
25438 case X86::SI: DestReg = X86::RSI; break;
25439 case X86::DI: DestReg = X86::RDI; break;
25440 case X86::BP: DestReg = X86::RBP; break;
25441 case X86::SP: DestReg = X86::RSP; break;
25444 Res.first = DestReg;
25445 Res.second = &X86::GR64RegClass;
25448 } else if (Res.second == &X86::FR32RegClass ||
25449 Res.second == &X86::FR64RegClass ||
25450 Res.second == &X86::VR128RegClass ||
25451 Res.second == &X86::VR256RegClass ||
25452 Res.second == &X86::FR32XRegClass ||
25453 Res.second == &X86::FR64XRegClass ||
25454 Res.second == &X86::VR128XRegClass ||
25455 Res.second == &X86::VR256XRegClass ||
25456 Res.second == &X86::VR512RegClass) {
25457 // Handle references to XMM physical registers that got mapped into the
25458 // wrong class. This can happen with constraints like {xmm0} where the
25459 // target independent register mapper will just pick the first match it can
25460 // find, ignoring the required type.
25462 if (VT == MVT::f32 || VT == MVT::i32)
25463 Res.second = &X86::FR32RegClass;
25464 else if (VT == MVT::f64 || VT == MVT::i64)
25465 Res.second = &X86::FR64RegClass;
25466 else if (X86::VR128RegClass.hasType(VT))
25467 Res.second = &X86::VR128RegClass;
25468 else if (X86::VR256RegClass.hasType(VT))
25469 Res.second = &X86::VR256RegClass;
25470 else if (X86::VR512RegClass.hasType(VT))
25471 Res.second = &X86::VR512RegClass;
25477 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25479 // Scaling factors are not free at all.
25480 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25481 // will take 2 allocations in the out of order engine instead of 1
25482 // for plain addressing mode, i.e. inst (reg1).
25484 // vaddps (%rsi,%drx), %ymm0, %ymm1
25485 // Requires two allocations (one for the load, one for the computation)
25487 // vaddps (%rsi), %ymm0, %ymm1
25488 // Requires just 1 allocation, i.e., freeing allocations for other operations
25489 // and having less micro operations to execute.
25491 // For some X86 architectures, this is even worse because for instance for
25492 // stores, the complex addressing mode forces the instruction to use the
25493 // "load" ports instead of the dedicated "store" port.
25494 // E.g., on Haswell:
25495 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25496 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25497 if (isLegalAddressingMode(AM, Ty))
25498 // Scale represents reg2 * scale, thus account for 1
25499 // as soon as we use a second register.
25500 return AM.Scale != 0;
25504 bool X86TargetLowering::isTargetFTOL() const {
25505 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();