1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
161 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
163 RegInfo = TM.getRegisterInfo();
164 TD = getTargetData();
166 // Set up the TargetLowering object.
167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
169 // X86 is weird, it always uses i8 for shift amounts and setcc results.
170 setBooleanContents(ZeroOrOneBooleanContent);
171 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
172 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
174 // For 64-bit since we have so many registers use the ILP scheduler, for
175 // 32-bit code use the register pressure specific scheduling.
176 // For Atom, always use ILP scheduling.
177 if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::ILP);
179 else if (Subtarget->is64Bit())
180 setSchedulingPreference(Sched::ILP);
182 setSchedulingPreference(Sched::RegPressure);
183 setStackPointerRegisterToSaveRestore(X86StackPtr);
185 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
186 // Setup Windows compiler runtime calls.
187 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
188 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
189 setLibcallName(RTLIB::SREM_I64, "_allrem");
190 setLibcallName(RTLIB::UREM_I64, "_aullrem");
191 setLibcallName(RTLIB::MUL_I64, "_allmul");
192 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
198 // The _ftol2 runtime function has an unusual calling conv, which
199 // is modeled by a special pseudo-instruction.
200 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
202 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
203 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
206 if (Subtarget->isTargetDarwin()) {
207 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
208 setUseUnderscoreSetJmp(false);
209 setUseUnderscoreLongJmp(false);
210 } else if (Subtarget->isTargetMingw()) {
211 // MS runtime is weird: it exports _setjmp, but longjmp!
212 setUseUnderscoreSetJmp(true);
213 setUseUnderscoreLongJmp(false);
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(true);
219 // Set up the register classes.
220 addRegisterClass(MVT::i8, &X86::GR8RegClass);
221 addRegisterClass(MVT::i16, &X86::GR16RegClass);
222 addRegisterClass(MVT::i32, &X86::GR32RegClass);
223 if (Subtarget->is64Bit())
224 addRegisterClass(MVT::i64, &X86::GR64RegClass);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
228 // We don't accept any truncstore of integer registers.
229 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
233 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
234 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
236 // SETOEQ and SETUNE require checking two conditions.
237 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
244 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
246 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
248 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
250 if (Subtarget->is64Bit()) {
251 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
253 } else if (!TM.Options.UseSoftFloat) {
254 // We have an algorithm for SSE2->double, and we turn this into a
255 // 64-bit FILD followed by conditional FADD for other targets.
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
257 // We have an algorithm for SSE2, and we turn this into a 64-bit
258 // FILD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
262 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
264 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
265 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
267 if (!TM.Options.UseSoftFloat) {
268 // SSE has no i16 to fp conversion, only i32
269 if (X86ScalarSSEf32) {
270 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 // f32 and f64 cases are Legal, f80 case is not
272 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
282 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
283 // are Legal, f80 is custom lowered.
284 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
287 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
289 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
290 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 if (X86ScalarSSEf32) {
293 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 // f32 and f64 cases are Legal, f80 case is not
295 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 // Handle FP_TO_UINT by promoting the destination to a larger signed
303 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
305 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
310 } else if (!TM.Options.UseSoftFloat) {
311 // Since AVX is a superset of SSE3, only check for SSE here.
312 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
313 // Expand FP_TO_UINT into a select.
314 // FIXME: We would like to use a Custom expander here eventually to do
315 // the optimal thing for SSE vs. the default expansion in the legalizer.
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
318 // With SSE3 we can use fisttpll to convert to a signed i64; without
319 // SSE, we're stuck with a fistpll.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
323 if (isTargetFTOL()) {
324 // Use the _ftol2 runtime function, which has a pseudo-instruction
325 // to handle its weird calling convention.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 // Promote the i8 variants and force them on up to i32 which has a shorter
383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
387 if (Subtarget->hasBMI()) {
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
390 if (Subtarget->is64Bit())
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
399 if (Subtarget->hasLZCNT()) {
400 // When promoting the i8 variants, force them to i32 for a shorter
402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
408 if (Subtarget->is64Bit())
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
423 if (Subtarget->hasPOPCNT()) {
424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
429 if (Subtarget->is64Bit())
430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
436 // These should be promoted to a larger select which is supported.
437 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
438 // X86 wants to expand cmov itself.
439 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
441 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
483 if (Subtarget->hasSSE1())
484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
489 // On X86 and X86-64, atomic operations are lowered to locked instructions.
490 // Locked instructions, in turn, have implicit fence semantics (all memory
491 // operations are flushed before issuing the locked instruction, and they
492 // are not buffered), so we can fold away the common pattern of
493 // fence-atomic-fence.
494 setShouldFoldAtomicFences(true);
496 // Expand certain atomics
497 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
504 if (!Subtarget->is64Bit()) {
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 if (Subtarget->hasCmpxchg16b()) {
516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
519 // FIXME - use subtarget debug flags
520 if (!Subtarget->isTargetDarwin() &&
521 !Subtarget->isTargetELF() &&
522 !Subtarget->isTargetCygMing()) {
523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
530 if (Subtarget->is64Bit()) {
531 setExceptionPointerRegister(X86::RAX);
532 setExceptionSelectorRegister(X86::RDX);
534 setExceptionPointerRegister(X86::EAX);
535 setExceptionSelectorRegister(X86::EDX);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
543 setOperationAction(ISD::TRAP, MVT::Other, Legal);
545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
546 setOperationAction(ISD::VASTART , MVT::Other, Custom);
547 setOperationAction(ISD::VAEND , MVT::Other, Expand);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::VAARG , MVT::Other, Custom);
550 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
552 setOperationAction(ISD::VAARG , MVT::Other, Expand);
553 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
562 else if (TM.Options.EnableSegmentedStacks)
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Custom);
566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
567 MVT::i64 : MVT::i32, Expand);
569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
570 // f32 and f64 use SSE.
571 // Set up the FP register classes.
572 addRegisterClass(MVT::f32, &X86::FR32RegClass);
573 addRegisterClass(MVT::f64, &X86::FR64RegClass);
575 // Use ANDPD to simulate FABS.
576 setOperationAction(ISD::FABS , MVT::f64, Custom);
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f64, Custom);
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 // Use ANDPD and ORPD to simulate FCOPYSIGN.
584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
587 // Lower this to FGETSIGNx86 plus an AND.
588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
591 // We don't support sin/cos/fmod
592 setOperationAction(ISD::FSIN , MVT::f64, Expand);
593 setOperationAction(ISD::FCOS , MVT::f64, Expand);
594 setOperationAction(ISD::FSIN , MVT::f32, Expand);
595 setOperationAction(ISD::FCOS , MVT::f32, Expand);
597 // Expand FP immediates into loads from the stack, except for the special
599 addLegalFPImmediate(APFloat(+0.0)); // xorpd
600 addLegalFPImmediate(APFloat(+0.0f)); // xorps
601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
602 // Use SSE for f32, x87 for f64.
603 // Set up the FP register classes.
604 addRegisterClass(MVT::f32, &X86::FR32RegClass);
605 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
607 // Use ANDPS to simulate FABS.
608 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 // Use XORP to simulate FNEG.
611 setOperationAction(ISD::FNEG , MVT::f32, Custom);
613 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
615 // Use ANDPS and ORPS to simulate FCOPYSIGN.
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
623 // Special cases we handle for FP constants.
624 addLegalFPImmediate(APFloat(+0.0f)); // xorps
625 addLegalFPImmediate(APFloat(+0.0)); // FLD0
626 addLegalFPImmediate(APFloat(+1.0)); // FLD1
627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
630 if (!TM.Options.UnsafeFPMath) {
631 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
632 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
634 } else if (!TM.Options.UseSoftFloat) {
635 // f32 and f64 in x87.
636 // Set up the FP register classes.
637 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
638 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
640 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
641 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
645 if (!TM.Options.UnsafeFPMath) {
646 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
647 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
649 addLegalFPImmediate(APFloat(+0.0)); // FLD0
650 addLegalFPImmediate(APFloat(+1.0)); // FLD1
651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
659 // We don't support FMA.
660 setOperationAction(ISD::FMA, MVT::f64, Expand);
661 setOperationAction(ISD::FMA, MVT::f32, Expand);
663 // Long double always uses X87.
664 if (!TM.Options.UseSoftFloat) {
665 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
666 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
670 addLegalFPImmediate(TmpFlt); // FLD0
672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
675 APFloat TmpFlt2(+1.0);
676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
678 addLegalFPImmediate(TmpFlt2); // FLD1
679 TmpFlt2.changeSign();
680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
683 if (!TM.Options.UnsafeFPMath) {
684 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
685 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
689 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
691 setOperationAction(ISD::FRINT, MVT::f80, Expand);
692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
693 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 // Always use a library call for pow.
697 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
699 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
701 setOperationAction(ISD::FLOG, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
703 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP, MVT::f80, Expand);
705 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
707 // First set operation action for all vector types to either promote
708 // (for widening) or expand (for scalarization). Then we will selectively
709 // turn on ones that can be effectively codegen'd.
710 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
711 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
765 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
770 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
771 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
772 setTruncStoreAction((MVT::SimpleValueType)VT,
773 (MVT::SimpleValueType)InnerVT, Expand);
774 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
780 // with -msoft-float, disable use of MMX as well.
781 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
782 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
783 // No operations on x86mmx supported, everything uses intrinsics.
786 // MMX-sized vectors (other than x86mmx) are expected to be expanded
787 // into smaller operations.
788 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
789 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
790 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
791 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
792 setOperationAction(ISD::AND, MVT::v8i8, Expand);
793 setOperationAction(ISD::AND, MVT::v4i16, Expand);
794 setOperationAction(ISD::AND, MVT::v2i32, Expand);
795 setOperationAction(ISD::AND, MVT::v1i64, Expand);
796 setOperationAction(ISD::OR, MVT::v8i8, Expand);
797 setOperationAction(ISD::OR, MVT::v4i16, Expand);
798 setOperationAction(ISD::OR, MVT::v2i32, Expand);
799 setOperationAction(ISD::OR, MVT::v1i64, Expand);
800 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
809 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
810 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
811 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
812 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
815 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
818 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
819 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
821 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
823 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
826 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
827 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
828 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
829 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
831 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
835 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
838 // registers cannot be used even for integer operations.
839 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
840 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
841 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
842 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
844 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
845 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
846 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
847 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
848 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
849 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
850 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
851 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
852 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
853 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
854 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
874 MVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
920 // Custom lower v2i64 and v2f64 selects.
921 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
922 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
923 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
924 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
926 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
927 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
930 if (Subtarget->hasSSE41()) {
931 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
932 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
933 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
934 setOperationAction(ISD::FRINT, MVT::f32, Legal);
935 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
936 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
937 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
938 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
939 setOperationAction(ISD::FRINT, MVT::f64, Legal);
940 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
942 // FIXME: Do we need to handle scalar-to-vector here?
943 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
945 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
946 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
947 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
948 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
951 // i8 and i16 vectors are custom , because the source register and source
952 // source memory operand types are not the same width. f32 vectors are
953 // custom since the immediate controlling the insert encodes additional
955 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
956 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
957 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
958 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
960 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
961 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
962 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
963 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
965 // FIXME: these should be Legal but thats only for the case where
966 // the index is constant. For now custom expand to deal with that.
967 if (Subtarget->is64Bit()) {
968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
973 if (Subtarget->hasSSE2()) {
974 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
975 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
977 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
978 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
980 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
981 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
983 if (Subtarget->hasAVX2()) {
984 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
985 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
987 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
988 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
990 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
992 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
993 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
995 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
996 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
998 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1002 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1003 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1004 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1005 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1006 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1007 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1008 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1010 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1011 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1012 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1014 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1015 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1016 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1017 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1018 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1019 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1021 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1028 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1029 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1030 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1032 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1041 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1042 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1043 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1044 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1046 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1047 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1048 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1050 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1051 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1052 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1053 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1055 if (Subtarget->hasFMA()) {
1056 setOperationAction(ISD::FMA, MVT::v8f32, Custom);
1057 setOperationAction(ISD::FMA, MVT::v4f64, Custom);
1058 setOperationAction(ISD::FMA, MVT::v4f32, Custom);
1059 setOperationAction(ISD::FMA, MVT::v2f64, Custom);
1060 setOperationAction(ISD::FMA, MVT::f32, Custom);
1061 setOperationAction(ISD::FMA, MVT::f64, Custom);
1064 if (Subtarget->hasAVX2()) {
1065 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1066 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1067 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1068 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1070 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1071 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1072 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1073 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1075 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1076 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1077 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1078 // Don't lower v32i8 because there is no 128-bit byte mul
1080 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1082 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1086 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1088 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1090 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1091 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1092 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1093 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1096 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1097 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1098 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1100 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1101 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1102 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1103 // Don't lower v32i8 because there is no 128-bit byte mul
1105 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1114 // Custom lower several nodes for 256-bit types.
1115 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1116 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1117 MVT VT = (MVT::SimpleValueType)i;
1119 // Extract subvector is special because the value type
1120 // (result) is 128-bit but the source is 256-bit wide.
1121 if (VT.is128BitVector())
1122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1124 // Do not attempt to custom lower other non-256-bit vectors
1125 if (!VT.is256BitVector())
1128 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1129 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1132 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1133 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1134 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1137 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1138 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1139 MVT VT = (MVT::SimpleValueType)i;
1141 // Do not attempt to promote non-256-bit vectors
1142 if (!VT.is256BitVector())
1145 setOperationAction(ISD::AND, VT, Promote);
1146 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1147 setOperationAction(ISD::OR, VT, Promote);
1148 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1149 setOperationAction(ISD::XOR, VT, Promote);
1150 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1151 setOperationAction(ISD::LOAD, VT, Promote);
1152 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1153 setOperationAction(ISD::SELECT, VT, Promote);
1154 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1158 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1159 // of this type with custom code.
1160 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1161 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1162 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1166 // We want to custom lower some of our intrinsics.
1167 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1168 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1171 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1172 // handle type legalization for these operations here.
1174 // FIXME: We really should do custom legalization for addition and
1175 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1176 // than generic legalization for 64-bit multiplication-with-overflow, though.
1177 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1178 // Add/Sub/Mul with overflow operations are custom lowered.
1180 setOperationAction(ISD::SADDO, VT, Custom);
1181 setOperationAction(ISD::UADDO, VT, Custom);
1182 setOperationAction(ISD::SSUBO, VT, Custom);
1183 setOperationAction(ISD::USUBO, VT, Custom);
1184 setOperationAction(ISD::SMULO, VT, Custom);
1185 setOperationAction(ISD::UMULO, VT, Custom);
1188 // There are no 8-bit 3-address imul/mul instructions
1189 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1190 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1192 if (!Subtarget->is64Bit()) {
1193 // These libcalls are not available in 32-bit.
1194 setLibcallName(RTLIB::SHL_I128, 0);
1195 setLibcallName(RTLIB::SRL_I128, 0);
1196 setLibcallName(RTLIB::SRA_I128, 0);
1199 // We have target-specific dag combine patterns for the following nodes:
1200 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1201 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1202 setTargetDAGCombine(ISD::VSELECT);
1203 setTargetDAGCombine(ISD::SELECT);
1204 setTargetDAGCombine(ISD::SHL);
1205 setTargetDAGCombine(ISD::SRA);
1206 setTargetDAGCombine(ISD::SRL);
1207 setTargetDAGCombine(ISD::OR);
1208 setTargetDAGCombine(ISD::AND);
1209 setTargetDAGCombine(ISD::ADD);
1210 setTargetDAGCombine(ISD::FADD);
1211 setTargetDAGCombine(ISD::FSUB);
1212 setTargetDAGCombine(ISD::FMA);
1213 setTargetDAGCombine(ISD::SUB);
1214 setTargetDAGCombine(ISD::LOAD);
1215 setTargetDAGCombine(ISD::STORE);
1216 setTargetDAGCombine(ISD::ZERO_EXTEND);
1217 setTargetDAGCombine(ISD::ANY_EXTEND);
1218 setTargetDAGCombine(ISD::SIGN_EXTEND);
1219 setTargetDAGCombine(ISD::TRUNCATE);
1220 setTargetDAGCombine(ISD::UINT_TO_FP);
1221 setTargetDAGCombine(ISD::SINT_TO_FP);
1222 setTargetDAGCombine(ISD::SETCC);
1223 setTargetDAGCombine(ISD::FP_TO_SINT);
1224 if (Subtarget->is64Bit())
1225 setTargetDAGCombine(ISD::MUL);
1226 setTargetDAGCombine(ISD::XOR);
1228 computeRegisterProperties();
1230 // On Darwin, -Os means optimize for size without hurting performance,
1231 // do not reduce the limit.
1232 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1233 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1234 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1235 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1236 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1237 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1238 setPrefLoopAlignment(4); // 2^4 bytes.
1239 benefitFromCodePlacementOpt = true;
1241 // Predictable cmov don't hurt on atom because it's in-order.
1242 predictableSelectIsExpensive = !Subtarget->isAtom();
1244 setPrefFunctionAlignment(4); // 2^4 bytes.
1248 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1249 if (!VT.isVector()) return MVT::i8;
1250 return VT.changeVectorElementTypeToInteger();
1254 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1255 /// the desired ByVal argument alignment.
1256 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1259 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1260 if (VTy->getBitWidth() == 128)
1262 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1263 unsigned EltAlign = 0;
1264 getMaxByValAlign(ATy->getElementType(), EltAlign);
1265 if (EltAlign > MaxAlign)
1266 MaxAlign = EltAlign;
1267 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1268 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1269 unsigned EltAlign = 0;
1270 getMaxByValAlign(STy->getElementType(i), EltAlign);
1271 if (EltAlign > MaxAlign)
1272 MaxAlign = EltAlign;
1279 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1280 /// function arguments in the caller parameter area. For X86, aggregates
1281 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1282 /// are at 4-byte boundaries.
1283 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1284 if (Subtarget->is64Bit()) {
1285 // Max of 8 and alignment of type.
1286 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1293 if (Subtarget->hasSSE1())
1294 getMaxByValAlign(Ty, Align);
1298 /// getOptimalMemOpType - Returns the target specific optimal type for load
1299 /// and store operations as a result of memset, memcpy, and memmove
1300 /// lowering. If DstAlign is zero that means it's safe to destination
1301 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1302 /// means there isn't a need to check it against alignment requirement,
1303 /// probably because the source does not need to be loaded. If
1304 /// 'IsZeroVal' is true, that means it's safe to return a
1305 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1306 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1307 /// constant so it does not need to be loaded.
1308 /// It returns EVT::Other if the type should be determined using generic
1309 /// target-independent logic.
1311 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1312 unsigned DstAlign, unsigned SrcAlign,
1315 MachineFunction &MF) const {
1316 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1317 // linux. This is because the stack realignment code can't handle certain
1318 // cases like PR2962. This should be removed when PR2962 is fixed.
1319 const Function *F = MF.getFunction();
1321 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1323 (Subtarget->isUnalignedMemAccessFast() ||
1324 ((DstAlign == 0 || DstAlign >= 16) &&
1325 (SrcAlign == 0 || SrcAlign >= 16))) &&
1326 Subtarget->getStackAlignment() >= 16) {
1327 if (Subtarget->getStackAlignment() >= 32) {
1328 if (Subtarget->hasAVX2())
1330 if (Subtarget->hasAVX())
1333 if (Subtarget->hasSSE2())
1335 if (Subtarget->hasSSE1())
1337 } else if (!MemcpyStrSrc && Size >= 8 &&
1338 !Subtarget->is64Bit() &&
1339 Subtarget->getStackAlignment() >= 8 &&
1340 Subtarget->hasSSE2()) {
1341 // Do not use f64 to lower memcpy if source is string constant. It's
1342 // better to use i32 to avoid the loads.
1346 if (Subtarget->is64Bit() && Size >= 8)
1351 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1352 /// current function. The returned value is a member of the
1353 /// MachineJumpTableInfo::JTEntryKind enum.
1354 unsigned X86TargetLowering::getJumpTableEncoding() const {
1355 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1357 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1358 Subtarget->isPICStyleGOT())
1359 return MachineJumpTableInfo::EK_Custom32;
1361 // Otherwise, use the normal jump table encoding heuristics.
1362 return TargetLowering::getJumpTableEncoding();
1366 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1367 const MachineBasicBlock *MBB,
1368 unsigned uid,MCContext &Ctx) const{
1369 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1370 Subtarget->isPICStyleGOT());
1371 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1373 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1374 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1377 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1379 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1380 SelectionDAG &DAG) const {
1381 if (!Subtarget->is64Bit())
1382 // This doesn't have DebugLoc associated with it, but is not really the
1383 // same as a Register.
1384 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1388 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1389 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1391 const MCExpr *X86TargetLowering::
1392 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1393 MCContext &Ctx) const {
1394 // X86-64 uses RIP relative addressing based on the jump table label.
1395 if (Subtarget->isPICStyleRIPRel())
1396 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1398 // Otherwise, the reference is relative to the PIC base.
1399 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1402 // FIXME: Why this routine is here? Move to RegInfo!
1403 std::pair<const TargetRegisterClass*, uint8_t>
1404 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1405 const TargetRegisterClass *RRC = 0;
1407 switch (VT.getSimpleVT().SimpleTy) {
1409 return TargetLowering::findRepresentativeClass(VT);
1410 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1411 RRC = Subtarget->is64Bit() ?
1412 (const TargetRegisterClass*)&X86::GR64RegClass :
1413 (const TargetRegisterClass*)&X86::GR32RegClass;
1416 RRC = &X86::VR64RegClass;
1418 case MVT::f32: case MVT::f64:
1419 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1420 case MVT::v4f32: case MVT::v2f64:
1421 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1423 RRC = &X86::VR128RegClass;
1426 return std::make_pair(RRC, Cost);
1429 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1430 unsigned &Offset) const {
1431 if (!Subtarget->isTargetLinux())
1434 if (Subtarget->is64Bit()) {
1435 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1437 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1450 //===----------------------------------------------------------------------===//
1451 // Return Value Calling Convention Implementation
1452 //===----------------------------------------------------------------------===//
1454 #include "X86GenCallingConv.inc"
1457 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1458 MachineFunction &MF, bool isVarArg,
1459 const SmallVectorImpl<ISD::OutputArg> &Outs,
1460 LLVMContext &Context) const {
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1464 return CCInfo.CheckReturn(Outs, RetCC_X86);
1468 X86TargetLowering::LowerReturn(SDValue Chain,
1469 CallingConv::ID CallConv, bool isVarArg,
1470 const SmallVectorImpl<ISD::OutputArg> &Outs,
1471 const SmallVectorImpl<SDValue> &OutVals,
1472 DebugLoc dl, SelectionDAG &DAG) const {
1473 MachineFunction &MF = DAG.getMachineFunction();
1474 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1476 SmallVector<CCValAssign, 16> RVLocs;
1477 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1478 RVLocs, *DAG.getContext());
1479 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1481 // Add the regs to the liveout set for the function.
1482 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1483 for (unsigned i = 0; i != RVLocs.size(); ++i)
1484 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1485 MRI.addLiveOut(RVLocs[i].getLocReg());
1489 SmallVector<SDValue, 6> RetOps;
1490 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1491 // Operand #1 = Bytes To Pop
1492 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1495 // Copy the result values into the output registers.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 assert(VA.isRegLoc() && "Can only return in registers!");
1499 SDValue ValToCopy = OutVals[i];
1500 EVT ValVT = ValToCopy.getValueType();
1502 // Promote values to the appropriate types
1503 if (VA.getLocInfo() == CCValAssign::SExt)
1504 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1505 else if (VA.getLocInfo() == CCValAssign::ZExt)
1506 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1507 else if (VA.getLocInfo() == CCValAssign::AExt)
1508 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1509 else if (VA.getLocInfo() == CCValAssign::BCvt)
1510 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1512 // If this is x86-64, and we disabled SSE, we can't return FP values,
1513 // or SSE or MMX vectors.
1514 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1515 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1516 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1517 report_fatal_error("SSE register return with SSE disabled");
1519 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1520 // llvm-gcc has never done it right and no one has noticed, so this
1521 // should be OK for now.
1522 if (ValVT == MVT::f64 &&
1523 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1524 report_fatal_error("SSE2 register return with SSE2 disabled");
1526 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1527 // the RET instruction and handled by the FP Stackifier.
1528 if (VA.getLocReg() == X86::ST0 ||
1529 VA.getLocReg() == X86::ST1) {
1530 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1531 // change the value to the FP stack register class.
1532 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1533 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1534 RetOps.push_back(ValToCopy);
1535 // Don't emit a copytoreg.
1539 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1540 // which is returned in RAX / RDX.
1541 if (Subtarget->is64Bit()) {
1542 if (ValVT == MVT::x86mmx) {
1543 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1544 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1545 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1547 // If we don't have SSE2 available, convert to v4f32 so the generated
1548 // register is legal.
1549 if (!Subtarget->hasSSE2())
1550 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1555 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1556 Flag = Chain.getValue(1);
1559 // The x86-64 ABI for returning structs by value requires that we copy
1560 // the sret argument into %rax for the return. We saved the argument into
1561 // a virtual register in the entry block, so now we copy the value out
1563 if (Subtarget->is64Bit() &&
1564 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1565 MachineFunction &MF = DAG.getMachineFunction();
1566 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1567 unsigned Reg = FuncInfo->getSRetReturnReg();
1569 "SRetReturnReg should have been set in LowerFormalArguments().");
1570 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1572 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1573 Flag = Chain.getValue(1);
1575 // RAX now acts like a return value.
1576 MRI.addLiveOut(X86::RAX);
1579 RetOps[0] = Chain; // Update chain.
1581 // Add the flag if we have it.
1583 RetOps.push_back(Flag);
1585 return DAG.getNode(X86ISD::RET_FLAG, dl,
1586 MVT::Other, &RetOps[0], RetOps.size());
1589 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1590 if (N->getNumValues() != 1)
1592 if (!N->hasNUsesOfValue(1, 0))
1595 SDValue TCChain = Chain;
1596 SDNode *Copy = *N->use_begin();
1597 if (Copy->getOpcode() == ISD::CopyToReg) {
1598 // If the copy has a glue operand, we conservatively assume it isn't safe to
1599 // perform a tail call.
1600 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1602 TCChain = Copy->getOperand(0);
1603 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1606 bool HasRet = false;
1607 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1609 if (UI->getOpcode() != X86ISD::RET_FLAG)
1622 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1623 ISD::NodeType ExtendKind) const {
1625 // TODO: Is this also valid on 32-bit?
1626 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1627 ReturnMVT = MVT::i8;
1629 ReturnMVT = MVT::i32;
1631 EVT MinVT = getRegisterType(Context, ReturnMVT);
1632 return VT.bitsLT(MinVT) ? MinVT : VT;
1635 /// LowerCallResult - Lower the result values of a call into the
1636 /// appropriate copies out of appropriate physical registers.
1639 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1640 CallingConv::ID CallConv, bool isVarArg,
1641 const SmallVectorImpl<ISD::InputArg> &Ins,
1642 DebugLoc dl, SelectionDAG &DAG,
1643 SmallVectorImpl<SDValue> &InVals) const {
1645 // Assign locations to each value returned by this call.
1646 SmallVector<CCValAssign, 16> RVLocs;
1647 bool Is64Bit = Subtarget->is64Bit();
1648 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1649 getTargetMachine(), RVLocs, *DAG.getContext());
1650 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1652 // Copy all of the result registers out of their specified physreg.
1653 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1654 CCValAssign &VA = RVLocs[i];
1655 EVT CopyVT = VA.getValVT();
1657 // If this is x86-64, and we disabled SSE, we can't return FP values
1658 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1659 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1660 report_fatal_error("SSE register return with SSE disabled");
1665 // If this is a call to a function that returns an fp value on the floating
1666 // point stack, we must guarantee the value is popped from the stack, so
1667 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1668 // if the return value is not used. We use the FpPOP_RETVAL instruction
1670 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1671 // If we prefer to use the value in xmm registers, copy it out as f80 and
1672 // use a truncate to move it from fp stack reg to xmm reg.
1673 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1674 SDValue Ops[] = { Chain, InFlag };
1675 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1676 MVT::Other, MVT::Glue, Ops, 2), 1);
1677 Val = Chain.getValue(0);
1679 // Round the f80 to the right size, which also moves it to the appropriate
1681 if (CopyVT != VA.getValVT())
1682 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1683 // This truncation won't change the value.
1684 DAG.getIntPtrConstant(1));
1686 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1687 CopyVT, InFlag).getValue(1);
1688 Val = Chain.getValue(0);
1690 InFlag = Chain.getValue(2);
1691 InVals.push_back(Val);
1698 //===----------------------------------------------------------------------===//
1699 // C & StdCall & Fast Calling Convention implementation
1700 //===----------------------------------------------------------------------===//
1701 // StdCall calling convention seems to be standard for many Windows' API
1702 // routines and around. It differs from C calling convention just a little:
1703 // callee should clean up the stack, not caller. Symbols should be also
1704 // decorated in some fancy way :) It doesn't support any vector arguments.
1705 // For info on fast calling convention see Fast Calling Convention (tail call)
1706 // implementation LowerX86_32FastCCCallTo.
1708 /// CallIsStructReturn - Determines whether a call uses struct return
1710 enum StructReturnType {
1715 static StructReturnType
1716 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1718 return NotStructReturn;
1720 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1721 if (!Flags.isSRet())
1722 return NotStructReturn;
1723 if (Flags.isInReg())
1724 return RegStructReturn;
1725 return StackStructReturn;
1728 /// ArgsAreStructReturn - Determines whether a function uses struct
1729 /// return semantics.
1730 static StructReturnType
1731 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1733 return NotStructReturn;
1735 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1736 if (!Flags.isSRet())
1737 return NotStructReturn;
1738 if (Flags.isInReg())
1739 return RegStructReturn;
1740 return StackStructReturn;
1743 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1744 /// by "Src" to address "Dst" with size and alignment information specified by
1745 /// the specific parameter attribute. The copy will be passed as a byval
1746 /// function parameter.
1748 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1749 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1751 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1753 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1754 /*isVolatile*/false, /*AlwaysInline=*/true,
1755 MachinePointerInfo(), MachinePointerInfo());
1758 /// IsTailCallConvention - Return true if the calling convention is one that
1759 /// supports tail call optimization.
1760 static bool IsTailCallConvention(CallingConv::ID CC) {
1761 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1764 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1765 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1769 CallingConv::ID CalleeCC = CS.getCallingConv();
1770 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1776 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1777 /// a tailcall target by changing its ABI.
1778 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1779 bool GuaranteedTailCallOpt) {
1780 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1784 X86TargetLowering::LowerMemArgument(SDValue Chain,
1785 CallingConv::ID CallConv,
1786 const SmallVectorImpl<ISD::InputArg> &Ins,
1787 DebugLoc dl, SelectionDAG &DAG,
1788 const CCValAssign &VA,
1789 MachineFrameInfo *MFI,
1791 // Create the nodes corresponding to a load from this parameter slot.
1792 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1793 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1794 getTargetMachine().Options.GuaranteedTailCallOpt);
1795 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1798 // If value is passed by pointer we have address passed instead of the value
1800 if (VA.getLocInfo() == CCValAssign::Indirect)
1801 ValVT = VA.getLocVT();
1803 ValVT = VA.getValVT();
1805 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1806 // changed with more analysis.
1807 // In case of tail call optimization mark all arguments mutable. Since they
1808 // could be overwritten by lowering of arguments in case of a tail call.
1809 if (Flags.isByVal()) {
1810 unsigned Bytes = Flags.getByValSize();
1811 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1812 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1813 return DAG.getFrameIndex(FI, getPointerTy());
1815 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1816 VA.getLocMemOffset(), isImmutable);
1817 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1818 return DAG.getLoad(ValVT, dl, Chain, FIN,
1819 MachinePointerInfo::getFixedStack(FI),
1820 false, false, false, 0);
1825 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1826 CallingConv::ID CallConv,
1828 const SmallVectorImpl<ISD::InputArg> &Ins,
1831 SmallVectorImpl<SDValue> &InVals)
1833 MachineFunction &MF = DAG.getMachineFunction();
1834 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1836 const Function* Fn = MF.getFunction();
1837 if (Fn->hasExternalLinkage() &&
1838 Subtarget->isTargetCygMing() &&
1839 Fn->getName() == "main")
1840 FuncInfo->setForceFramePointer(true);
1842 MachineFrameInfo *MFI = MF.getFrameInfo();
1843 bool Is64Bit = Subtarget->is64Bit();
1844 bool IsWindows = Subtarget->isTargetWindows();
1845 bool IsWin64 = Subtarget->isTargetWin64();
1847 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1848 "Var args not supported with calling convention fastcc or ghc");
1850 // Assign locations to all of the incoming arguments.
1851 SmallVector<CCValAssign, 16> ArgLocs;
1852 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1853 ArgLocs, *DAG.getContext());
1855 // Allocate shadow area for Win64
1857 CCInfo.AllocateStack(32, 8);
1860 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1862 unsigned LastVal = ~0U;
1864 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1865 CCValAssign &VA = ArgLocs[i];
1866 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1868 assert(VA.getValNo() != LastVal &&
1869 "Don't support value assigned to multiple locs yet");
1871 LastVal = VA.getValNo();
1873 if (VA.isRegLoc()) {
1874 EVT RegVT = VA.getLocVT();
1875 const TargetRegisterClass *RC;
1876 if (RegVT == MVT::i32)
1877 RC = &X86::GR32RegClass;
1878 else if (Is64Bit && RegVT == MVT::i64)
1879 RC = &X86::GR64RegClass;
1880 else if (RegVT == MVT::f32)
1881 RC = &X86::FR32RegClass;
1882 else if (RegVT == MVT::f64)
1883 RC = &X86::FR64RegClass;
1884 else if (RegVT.is256BitVector())
1885 RC = &X86::VR256RegClass;
1886 else if (RegVT.is128BitVector())
1887 RC = &X86::VR128RegClass;
1888 else if (RegVT == MVT::x86mmx)
1889 RC = &X86::VR64RegClass;
1891 llvm_unreachable("Unknown argument type!");
1893 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1894 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1896 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1897 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1899 if (VA.getLocInfo() == CCValAssign::SExt)
1900 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1901 DAG.getValueType(VA.getValVT()));
1902 else if (VA.getLocInfo() == CCValAssign::ZExt)
1903 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1904 DAG.getValueType(VA.getValVT()));
1905 else if (VA.getLocInfo() == CCValAssign::BCvt)
1906 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1908 if (VA.isExtInLoc()) {
1909 // Handle MMX values passed in XMM regs.
1910 if (RegVT.isVector()) {
1911 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1914 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1917 assert(VA.isMemLoc());
1918 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1921 // If value is passed via pointer - do a load.
1922 if (VA.getLocInfo() == CCValAssign::Indirect)
1923 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1924 MachinePointerInfo(), false, false, false, 0);
1926 InVals.push_back(ArgValue);
1929 // The x86-64 ABI for returning structs by value requires that we copy
1930 // the sret argument into %rax for the return. Save the argument into
1931 // a virtual register so that we can access it from the return points.
1932 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1933 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1934 unsigned Reg = FuncInfo->getSRetReturnReg();
1936 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1937 FuncInfo->setSRetReturnReg(Reg);
1939 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1940 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1943 unsigned StackSize = CCInfo.getNextStackOffset();
1944 // Align stack specially for tail calls.
1945 if (FuncIsMadeTailCallSafe(CallConv,
1946 MF.getTarget().Options.GuaranteedTailCallOpt))
1947 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1949 // If the function takes variable number of arguments, make a frame index for
1950 // the start of the first vararg value... for expansion of llvm.va_start.
1952 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1953 CallConv != CallingConv::X86_ThisCall)) {
1954 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1957 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1959 // FIXME: We should really autogenerate these arrays
1960 static const uint16_t GPR64ArgRegsWin64[] = {
1961 X86::RCX, X86::RDX, X86::R8, X86::R9
1963 static const uint16_t GPR64ArgRegs64Bit[] = {
1964 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1966 static const uint16_t XMMArgRegs64Bit[] = {
1967 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1968 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1970 const uint16_t *GPR64ArgRegs;
1971 unsigned NumXMMRegs = 0;
1974 // The XMM registers which might contain var arg parameters are shadowed
1975 // in their paired GPR. So we only need to save the GPR to their home
1977 TotalNumIntRegs = 4;
1978 GPR64ArgRegs = GPR64ArgRegsWin64;
1980 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1981 GPR64ArgRegs = GPR64ArgRegs64Bit;
1983 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1986 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1989 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1990 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1991 "SSE register cannot be used when SSE is disabled!");
1992 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1993 NoImplicitFloatOps) &&
1994 "SSE register cannot be used when SSE is disabled!");
1995 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1996 !Subtarget->hasSSE1())
1997 // Kernel mode asks for SSE to be disabled, so don't push them
1999 TotalNumXMMRegs = 0;
2002 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2003 // Get to the caller-allocated home save location. Add 8 to account
2004 // for the return address.
2005 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2006 FuncInfo->setRegSaveFrameIndex(
2007 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2008 // Fixup to set vararg frame on shadow area (4 x i64).
2010 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2012 // For X86-64, if there are vararg parameters that are passed via
2013 // registers, then we must store them to their spots on the stack so
2014 // they may be loaded by deferencing the result of va_next.
2015 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2016 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2017 FuncInfo->setRegSaveFrameIndex(
2018 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2022 // Store the integer parameter registers.
2023 SmallVector<SDValue, 8> MemOps;
2024 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2026 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2027 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2028 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2029 DAG.getIntPtrConstant(Offset));
2030 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2031 &X86::GR64RegClass);
2032 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2034 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2035 MachinePointerInfo::getFixedStack(
2036 FuncInfo->getRegSaveFrameIndex(), Offset),
2038 MemOps.push_back(Store);
2042 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2043 // Now store the XMM (fp + vector) parameter registers.
2044 SmallVector<SDValue, 11> SaveXMMOps;
2045 SaveXMMOps.push_back(Chain);
2047 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2048 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2049 SaveXMMOps.push_back(ALVal);
2051 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2052 FuncInfo->getRegSaveFrameIndex()));
2053 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2054 FuncInfo->getVarArgsFPOffset()));
2056 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2057 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2058 &X86::VR128RegClass);
2059 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2060 SaveXMMOps.push_back(Val);
2062 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2064 &SaveXMMOps[0], SaveXMMOps.size()));
2067 if (!MemOps.empty())
2068 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2069 &MemOps[0], MemOps.size());
2073 // Some CCs need callee pop.
2074 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2075 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2076 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2078 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2079 // If this is an sret function, the return should pop the hidden pointer.
2080 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2081 argsAreStructReturn(Ins) == StackStructReturn)
2082 FuncInfo->setBytesToPopOnReturn(4);
2086 // RegSaveFrameIndex is X86-64 only.
2087 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2088 if (CallConv == CallingConv::X86_FastCall ||
2089 CallConv == CallingConv::X86_ThisCall)
2090 // fastcc functions can't have varargs.
2091 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2094 FuncInfo->setArgumentStackSize(StackSize);
2100 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2101 SDValue StackPtr, SDValue Arg,
2102 DebugLoc dl, SelectionDAG &DAG,
2103 const CCValAssign &VA,
2104 ISD::ArgFlagsTy Flags) const {
2105 unsigned LocMemOffset = VA.getLocMemOffset();
2106 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2107 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2108 if (Flags.isByVal())
2109 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2111 return DAG.getStore(Chain, dl, Arg, PtrOff,
2112 MachinePointerInfo::getStack(LocMemOffset),
2116 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2117 /// optimization is performed and it is required.
2119 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2120 SDValue &OutRetAddr, SDValue Chain,
2121 bool IsTailCall, bool Is64Bit,
2122 int FPDiff, DebugLoc dl) const {
2123 // Adjust the Return address stack slot.
2124 EVT VT = getPointerTy();
2125 OutRetAddr = getReturnAddressFrameIndex(DAG);
2127 // Load the "old" Return address.
2128 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2129 false, false, false, 0);
2130 return SDValue(OutRetAddr.getNode(), 1);
2133 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2134 /// optimization is performed and it is required (FPDiff!=0).
2136 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2137 SDValue Chain, SDValue RetAddrFrIdx,
2138 bool Is64Bit, int FPDiff, DebugLoc dl) {
2139 // Store the return address to the appropriate stack slot.
2140 if (!FPDiff) return Chain;
2141 // Calculate the new stack slot for the return address.
2142 int SlotSize = Is64Bit ? 8 : 4;
2143 int NewReturnAddrFI =
2144 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2145 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2146 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2147 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2148 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2154 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2155 SmallVectorImpl<SDValue> &InVals) const {
2156 SelectionDAG &DAG = CLI.DAG;
2157 DebugLoc &dl = CLI.DL;
2158 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2159 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2160 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2161 SDValue Chain = CLI.Chain;
2162 SDValue Callee = CLI.Callee;
2163 CallingConv::ID CallConv = CLI.CallConv;
2164 bool &isTailCall = CLI.IsTailCall;
2165 bool isVarArg = CLI.IsVarArg;
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 bool Is64Bit = Subtarget->is64Bit();
2169 bool IsWin64 = Subtarget->isTargetWin64();
2170 bool IsWindows = Subtarget->isTargetWindows();
2171 StructReturnType SR = callIsStructReturn(Outs);
2172 bool IsSibcall = false;
2174 if (MF.getTarget().Options.DisableTailCalls)
2178 // Check if it's really possible to do a tail call.
2179 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2180 isVarArg, SR != NotStructReturn,
2181 MF.getFunction()->hasStructRetAttr(),
2182 Outs, OutVals, Ins, DAG);
2184 // Sibcalls are automatically detected tailcalls which do not require
2186 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2193 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2194 "Var args not supported with calling convention fastcc or ghc");
2196 // Analyze operands of the call, assigning locations to each operand.
2197 SmallVector<CCValAssign, 16> ArgLocs;
2198 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2199 ArgLocs, *DAG.getContext());
2201 // Allocate shadow area for Win64
2203 CCInfo.AllocateStack(32, 8);
2206 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2208 // Get a count of how many bytes are to be pushed on the stack.
2209 unsigned NumBytes = CCInfo.getNextStackOffset();
2211 // This is a sibcall. The memory operands are available in caller's
2212 // own caller's stack.
2214 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2215 IsTailCallConvention(CallConv))
2216 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2219 if (isTailCall && !IsSibcall) {
2220 // Lower arguments at fp - stackoffset + fpdiff.
2221 unsigned NumBytesCallerPushed =
2222 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2223 FPDiff = NumBytesCallerPushed - NumBytes;
2225 // Set the delta of movement of the returnaddr stackslot.
2226 // But only set if delta is greater than previous delta.
2227 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2228 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2232 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2234 SDValue RetAddrFrIdx;
2235 // Load return address for tail calls.
2236 if (isTailCall && FPDiff)
2237 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2238 Is64Bit, FPDiff, dl);
2240 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2241 SmallVector<SDValue, 8> MemOpChains;
2244 // Walk the register/memloc assignments, inserting copies/loads. In the case
2245 // of tail call optimization arguments are handle later.
2246 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2247 CCValAssign &VA = ArgLocs[i];
2248 EVT RegVT = VA.getLocVT();
2249 SDValue Arg = OutVals[i];
2250 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2251 bool isByVal = Flags.isByVal();
2253 // Promote the value if needed.
2254 switch (VA.getLocInfo()) {
2255 default: llvm_unreachable("Unknown loc info!");
2256 case CCValAssign::Full: break;
2257 case CCValAssign::SExt:
2258 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2260 case CCValAssign::ZExt:
2261 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2263 case CCValAssign::AExt:
2264 if (RegVT.is128BitVector()) {
2265 // Special case: passing MMX values in XMM registers.
2266 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2267 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2268 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2270 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2272 case CCValAssign::BCvt:
2273 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2275 case CCValAssign::Indirect: {
2276 // Store the argument.
2277 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2278 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2279 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2280 MachinePointerInfo::getFixedStack(FI),
2287 if (VA.isRegLoc()) {
2288 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2289 if (isVarArg && IsWin64) {
2290 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2291 // shadow reg if callee is a varargs function.
2292 unsigned ShadowReg = 0;
2293 switch (VA.getLocReg()) {
2294 case X86::XMM0: ShadowReg = X86::RCX; break;
2295 case X86::XMM1: ShadowReg = X86::RDX; break;
2296 case X86::XMM2: ShadowReg = X86::R8; break;
2297 case X86::XMM3: ShadowReg = X86::R9; break;
2300 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2302 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2303 assert(VA.isMemLoc());
2304 if (StackPtr.getNode() == 0)
2305 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2306 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2307 dl, DAG, VA, Flags));
2311 if (!MemOpChains.empty())
2312 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2313 &MemOpChains[0], MemOpChains.size());
2315 if (Subtarget->isPICStyleGOT()) {
2316 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2319 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2320 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2322 // If we are tail calling and generating PIC/GOT style code load the
2323 // address of the callee into ECX. The value in ecx is used as target of
2324 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2325 // for tail calls on PIC/GOT architectures. Normally we would just put the
2326 // address of GOT into ebx and then call target@PLT. But for tail calls
2327 // ebx would be restored (since ebx is callee saved) before jumping to the
2330 // Note: The actual moving to ECX is done further down.
2331 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2332 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2333 !G->getGlobal()->hasProtectedVisibility())
2334 Callee = LowerGlobalAddress(Callee, DAG);
2335 else if (isa<ExternalSymbolSDNode>(Callee))
2336 Callee = LowerExternalSymbol(Callee, DAG);
2340 if (Is64Bit && isVarArg && !IsWin64) {
2341 // From AMD64 ABI document:
2342 // For calls that may call functions that use varargs or stdargs
2343 // (prototype-less calls or calls to functions containing ellipsis (...) in
2344 // the declaration) %al is used as hidden argument to specify the number
2345 // of SSE registers used. The contents of %al do not need to match exactly
2346 // the number of registers, but must be an ubound on the number of SSE
2347 // registers used and is in the range 0 - 8 inclusive.
2349 // Count the number of XMM registers allocated.
2350 static const uint16_t XMMArgRegs[] = {
2351 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2352 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2354 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2355 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2356 && "SSE registers cannot be used when SSE is disabled");
2358 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2359 DAG.getConstant(NumXMMRegs, MVT::i8)));
2362 // For tail calls lower the arguments to the 'real' stack slot.
2364 // Force all the incoming stack arguments to be loaded from the stack
2365 // before any new outgoing arguments are stored to the stack, because the
2366 // outgoing stack slots may alias the incoming argument stack slots, and
2367 // the alias isn't otherwise explicit. This is slightly more conservative
2368 // than necessary, because it means that each store effectively depends
2369 // on every argument instead of just those arguments it would clobber.
2370 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2372 SmallVector<SDValue, 8> MemOpChains2;
2375 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2377 CCValAssign &VA = ArgLocs[i];
2380 assert(VA.isMemLoc());
2381 SDValue Arg = OutVals[i];
2382 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2383 // Create frame index.
2384 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2385 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2386 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2387 FIN = DAG.getFrameIndex(FI, getPointerTy());
2389 if (Flags.isByVal()) {
2390 // Copy relative to framepointer.
2391 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2392 if (StackPtr.getNode() == 0)
2393 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2395 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2397 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2401 // Store relative to framepointer.
2402 MemOpChains2.push_back(
2403 DAG.getStore(ArgChain, dl, Arg, FIN,
2404 MachinePointerInfo::getFixedStack(FI),
2410 if (!MemOpChains2.empty())
2411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2412 &MemOpChains2[0], MemOpChains2.size());
2414 // Store the return address to the appropriate stack slot.
2415 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2419 // Build a sequence of copy-to-reg nodes chained together with token chain
2420 // and flag operands which copy the outgoing args into registers.
2422 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2423 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2424 RegsToPass[i].second, InFlag);
2425 InFlag = Chain.getValue(1);
2428 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2429 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2430 // In the 64-bit large code model, we have to make all calls
2431 // through a register, since the call instruction's 32-bit
2432 // pc-relative offset may not be large enough to hold the whole
2434 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2435 // If the callee is a GlobalAddress node (quite common, every direct call
2436 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2439 // We should use extra load for direct calls to dllimported functions in
2441 const GlobalValue *GV = G->getGlobal();
2442 if (!GV->hasDLLImportLinkage()) {
2443 unsigned char OpFlags = 0;
2444 bool ExtraLoad = false;
2445 unsigned WrapperKind = ISD::DELETED_NODE;
2447 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2448 // external symbols most go through the PLT in PIC mode. If the symbol
2449 // has hidden or protected visibility, or if it is static or local, then
2450 // we don't need to use the PLT - we can directly call it.
2451 if (Subtarget->isTargetELF() &&
2452 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2453 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2454 OpFlags = X86II::MO_PLT;
2455 } else if (Subtarget->isPICStyleStubAny() &&
2456 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2457 (!Subtarget->getTargetTriple().isMacOSX() ||
2458 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2459 // PC-relative references to external symbols should go through $stub,
2460 // unless we're building with the leopard linker or later, which
2461 // automatically synthesizes these stubs.
2462 OpFlags = X86II::MO_DARWIN_STUB;
2463 } else if (Subtarget->isPICStyleRIPRel() &&
2464 isa<Function>(GV) &&
2465 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2466 // If the function is marked as non-lazy, generate an indirect call
2467 // which loads from the GOT directly. This avoids runtime overhead
2468 // at the cost of eager binding (and one extra byte of encoding).
2469 OpFlags = X86II::MO_GOTPCREL;
2470 WrapperKind = X86ISD::WrapperRIP;
2474 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2475 G->getOffset(), OpFlags);
2477 // Add a wrapper if needed.
2478 if (WrapperKind != ISD::DELETED_NODE)
2479 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2480 // Add extra indirection if needed.
2482 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2483 MachinePointerInfo::getGOT(),
2484 false, false, false, 0);
2486 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2487 unsigned char OpFlags = 0;
2489 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2490 // external symbols should go through the PLT.
2491 if (Subtarget->isTargetELF() &&
2492 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2493 OpFlags = X86II::MO_PLT;
2494 } else if (Subtarget->isPICStyleStubAny() &&
2495 (!Subtarget->getTargetTriple().isMacOSX() ||
2496 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2497 // PC-relative references to external symbols should go through $stub,
2498 // unless we're building with the leopard linker or later, which
2499 // automatically synthesizes these stubs.
2500 OpFlags = X86II::MO_DARWIN_STUB;
2503 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2507 // Returns a chain & a flag for retval copy to use.
2508 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2509 SmallVector<SDValue, 8> Ops;
2511 if (!IsSibcall && isTailCall) {
2512 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2513 DAG.getIntPtrConstant(0, true), InFlag);
2514 InFlag = Chain.getValue(1);
2517 Ops.push_back(Chain);
2518 Ops.push_back(Callee);
2521 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2523 // Add argument registers to the end of the list so that they are known live
2525 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2526 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2527 RegsToPass[i].second.getValueType()));
2529 // Add a register mask operand representing the call-preserved registers.
2530 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2531 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2532 assert(Mask && "Missing call preserved mask for calling convention");
2533 Ops.push_back(DAG.getRegisterMask(Mask));
2535 if (InFlag.getNode())
2536 Ops.push_back(InFlag);
2540 //// If this is the first return lowered for this function, add the regs
2541 //// to the liveout set for the function.
2542 // This isn't right, although it's probably harmless on x86; liveouts
2543 // should be computed from returns not tail calls. Consider a void
2544 // function making a tail call to a function returning int.
2545 return DAG.getNode(X86ISD::TC_RETURN, dl,
2546 NodeTys, &Ops[0], Ops.size());
2549 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2550 InFlag = Chain.getValue(1);
2552 // Create the CALLSEQ_END node.
2553 unsigned NumBytesForCalleeToPush;
2554 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2555 getTargetMachine().Options.GuaranteedTailCallOpt))
2556 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2557 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2558 SR == StackStructReturn)
2559 // If this is a call to a struct-return function, the callee
2560 // pops the hidden struct pointer, so we have to push it back.
2561 // This is common for Darwin/X86, Linux & Mingw32 targets.
2562 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2563 NumBytesForCalleeToPush = 4;
2565 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2567 // Returns a flag for retval copy to use.
2569 Chain = DAG.getCALLSEQ_END(Chain,
2570 DAG.getIntPtrConstant(NumBytes, true),
2571 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2574 InFlag = Chain.getValue(1);
2577 // Handle result values, copying them out of physregs into vregs that we
2579 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2580 Ins, dl, DAG, InVals);
2584 //===----------------------------------------------------------------------===//
2585 // Fast Calling Convention (tail call) implementation
2586 //===----------------------------------------------------------------------===//
2588 // Like std call, callee cleans arguments, convention except that ECX is
2589 // reserved for storing the tail called function address. Only 2 registers are
2590 // free for argument passing (inreg). Tail call optimization is performed
2592 // * tailcallopt is enabled
2593 // * caller/callee are fastcc
2594 // On X86_64 architecture with GOT-style position independent code only local
2595 // (within module) calls are supported at the moment.
2596 // To keep the stack aligned according to platform abi the function
2597 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2598 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2599 // If a tail called function callee has more arguments than the caller the
2600 // caller needs to make sure that there is room to move the RETADDR to. This is
2601 // achieved by reserving an area the size of the argument delta right after the
2602 // original REtADDR, but before the saved framepointer or the spilled registers
2603 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2615 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2616 /// for a 16 byte align requirement.
2618 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2619 SelectionDAG& DAG) const {
2620 MachineFunction &MF = DAG.getMachineFunction();
2621 const TargetMachine &TM = MF.getTarget();
2622 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2623 unsigned StackAlignment = TFI.getStackAlignment();
2624 uint64_t AlignMask = StackAlignment - 1;
2625 int64_t Offset = StackSize;
2626 uint64_t SlotSize = TD->getPointerSize();
2627 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2628 // Number smaller than 12 so just add the difference.
2629 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2631 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2632 Offset = ((~AlignMask) & Offset) + StackAlignment +
2633 (StackAlignment-SlotSize);
2638 /// MatchingStackOffset - Return true if the given stack call argument is
2639 /// already available in the same position (relatively) of the caller's
2640 /// incoming argument stack.
2642 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2643 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2644 const X86InstrInfo *TII) {
2645 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2647 if (Arg.getOpcode() == ISD::CopyFromReg) {
2648 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2649 if (!TargetRegisterInfo::isVirtualRegister(VR))
2651 MachineInstr *Def = MRI->getVRegDef(VR);
2654 if (!Flags.isByVal()) {
2655 if (!TII->isLoadFromStackSlot(Def, FI))
2658 unsigned Opcode = Def->getOpcode();
2659 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2660 Def->getOperand(1).isFI()) {
2661 FI = Def->getOperand(1).getIndex();
2662 Bytes = Flags.getByValSize();
2666 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2667 if (Flags.isByVal())
2668 // ByVal argument is passed in as a pointer but it's now being
2669 // dereferenced. e.g.
2670 // define @foo(%struct.X* %A) {
2671 // tail call @bar(%struct.X* byval %A)
2674 SDValue Ptr = Ld->getBasePtr();
2675 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2678 FI = FINode->getIndex();
2679 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2680 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2681 FI = FINode->getIndex();
2682 Bytes = Flags.getByValSize();
2686 assert(FI != INT_MAX);
2687 if (!MFI->isFixedObjectIndex(FI))
2689 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2692 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2693 /// for tail call optimization. Targets which want to do tail call
2694 /// optimization should implement this function.
2696 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2697 CallingConv::ID CalleeCC,
2699 bool isCalleeStructRet,
2700 bool isCallerStructRet,
2701 const SmallVectorImpl<ISD::OutputArg> &Outs,
2702 const SmallVectorImpl<SDValue> &OutVals,
2703 const SmallVectorImpl<ISD::InputArg> &Ins,
2704 SelectionDAG& DAG) const {
2705 if (!IsTailCallConvention(CalleeCC) &&
2706 CalleeCC != CallingConv::C)
2709 // If -tailcallopt is specified, make fastcc functions tail-callable.
2710 const MachineFunction &MF = DAG.getMachineFunction();
2711 const Function *CallerF = DAG.getMachineFunction().getFunction();
2712 CallingConv::ID CallerCC = CallerF->getCallingConv();
2713 bool CCMatch = CallerCC == CalleeCC;
2715 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2716 if (IsTailCallConvention(CalleeCC) && CCMatch)
2721 // Look for obvious safe cases to perform tail call optimization that do not
2722 // require ABI changes. This is what gcc calls sibcall.
2724 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2725 // emit a special epilogue.
2726 if (RegInfo->needsStackRealignment(MF))
2729 // Also avoid sibcall optimization if either caller or callee uses struct
2730 // return semantics.
2731 if (isCalleeStructRet || isCallerStructRet)
2734 // An stdcall caller is expected to clean up its arguments; the callee
2735 // isn't going to do that.
2736 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2739 // Do not sibcall optimize vararg calls unless all arguments are passed via
2741 if (isVarArg && !Outs.empty()) {
2743 // Optimizing for varargs on Win64 is unlikely to be safe without
2744 // additional testing.
2745 if (Subtarget->isTargetWin64())
2748 SmallVector<CCValAssign, 16> ArgLocs;
2749 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2750 getTargetMachine(), ArgLocs, *DAG.getContext());
2752 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2754 if (!ArgLocs[i].isRegLoc())
2758 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2759 // stack. Therefore, if it's not used by the call it is not safe to optimize
2760 // this into a sibcall.
2761 bool Unused = false;
2762 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2769 SmallVector<CCValAssign, 16> RVLocs;
2770 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2771 getTargetMachine(), RVLocs, *DAG.getContext());
2772 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2773 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2774 CCValAssign &VA = RVLocs[i];
2775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2780 // If the calling conventions do not match, then we'd better make sure the
2781 // results are returned in the same way as what the caller expects.
2783 SmallVector<CCValAssign, 16> RVLocs1;
2784 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2785 getTargetMachine(), RVLocs1, *DAG.getContext());
2786 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2788 SmallVector<CCValAssign, 16> RVLocs2;
2789 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2790 getTargetMachine(), RVLocs2, *DAG.getContext());
2791 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2793 if (RVLocs1.size() != RVLocs2.size())
2795 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2796 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2798 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2800 if (RVLocs1[i].isRegLoc()) {
2801 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2804 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2810 // If the callee takes no arguments then go on to check the results of the
2812 if (!Outs.empty()) {
2813 // Check if stack adjustment is needed. For now, do not do this if any
2814 // argument is passed on the stack.
2815 SmallVector<CCValAssign, 16> ArgLocs;
2816 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2817 getTargetMachine(), ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2820 if (Subtarget->isTargetWin64()) {
2821 CCInfo.AllocateStack(32, 8);
2824 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 if (CCInfo.getNextStackOffset()) {
2826 MachineFunction &MF = DAG.getMachineFunction();
2827 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2830 // Check if the arguments are already laid out in the right way as
2831 // the caller's fixed stack objects.
2832 MachineFrameInfo *MFI = MF.getFrameInfo();
2833 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2834 const X86InstrInfo *TII =
2835 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2836 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2837 CCValAssign &VA = ArgLocs[i];
2838 SDValue Arg = OutVals[i];
2839 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2840 if (VA.getLocInfo() == CCValAssign::Indirect)
2842 if (!VA.isRegLoc()) {
2843 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2850 // If the tailcall address may be in a register, then make sure it's
2851 // possible to register allocate for it. In 32-bit, the call address can
2852 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2853 // callee-saved registers are restored. These happen to be the same
2854 // registers used to pass 'inreg' arguments so watch out for those.
2855 if (!Subtarget->is64Bit() &&
2856 !isa<GlobalAddressSDNode>(Callee) &&
2857 !isa<ExternalSymbolSDNode>(Callee)) {
2858 unsigned NumInRegs = 0;
2859 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2860 CCValAssign &VA = ArgLocs[i];
2863 unsigned Reg = VA.getLocReg();
2866 case X86::EAX: case X86::EDX: case X86::ECX:
2867 if (++NumInRegs == 3)
2879 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2880 const TargetLibraryInfo *libInfo) const {
2881 return X86::createFastISel(funcInfo, libInfo);
2885 //===----------------------------------------------------------------------===//
2886 // Other Lowering Hooks
2887 //===----------------------------------------------------------------------===//
2889 static bool MayFoldLoad(SDValue Op) {
2890 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2893 static bool MayFoldIntoStore(SDValue Op) {
2894 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2897 static bool isTargetShuffle(unsigned Opcode) {
2899 default: return false;
2900 case X86ISD::PSHUFD:
2901 case X86ISD::PSHUFHW:
2902 case X86ISD::PSHUFLW:
2904 case X86ISD::PALIGN:
2905 case X86ISD::MOVLHPS:
2906 case X86ISD::MOVLHPD:
2907 case X86ISD::MOVHLPS:
2908 case X86ISD::MOVLPS:
2909 case X86ISD::MOVLPD:
2910 case X86ISD::MOVSHDUP:
2911 case X86ISD::MOVSLDUP:
2912 case X86ISD::MOVDDUP:
2915 case X86ISD::UNPCKL:
2916 case X86ISD::UNPCKH:
2917 case X86ISD::VPERMILP:
2918 case X86ISD::VPERM2X128:
2919 case X86ISD::VPERMI:
2924 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2925 SDValue V1, SelectionDAG &DAG) {
2927 default: llvm_unreachable("Unknown x86 shuffle node");
2928 case X86ISD::MOVSHDUP:
2929 case X86ISD::MOVSLDUP:
2930 case X86ISD::MOVDDUP:
2931 return DAG.getNode(Opc, dl, VT, V1);
2935 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2936 SDValue V1, unsigned TargetMask,
2937 SelectionDAG &DAG) {
2939 default: llvm_unreachable("Unknown x86 shuffle node");
2940 case X86ISD::PSHUFD:
2941 case X86ISD::PSHUFHW:
2942 case X86ISD::PSHUFLW:
2943 case X86ISD::VPERMILP:
2944 case X86ISD::VPERMI:
2945 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2949 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2950 SDValue V1, SDValue V2, unsigned TargetMask,
2951 SelectionDAG &DAG) {
2953 default: llvm_unreachable("Unknown x86 shuffle node");
2954 case X86ISD::PALIGN:
2956 case X86ISD::VPERM2X128:
2957 return DAG.getNode(Opc, dl, VT, V1, V2,
2958 DAG.getConstant(TargetMask, MVT::i8));
2962 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2963 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2965 default: llvm_unreachable("Unknown x86 shuffle node");
2966 case X86ISD::MOVLHPS:
2967 case X86ISD::MOVLHPD:
2968 case X86ISD::MOVHLPS:
2969 case X86ISD::MOVLPS:
2970 case X86ISD::MOVLPD:
2973 case X86ISD::UNPCKL:
2974 case X86ISD::UNPCKH:
2975 return DAG.getNode(Opc, dl, VT, V1, V2);
2979 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2980 MachineFunction &MF = DAG.getMachineFunction();
2981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2982 int ReturnAddrIndex = FuncInfo->getRAIndex();
2984 if (ReturnAddrIndex == 0) {
2985 // Set up a frame object for the return address.
2986 uint64_t SlotSize = TD->getPointerSize();
2987 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2989 FuncInfo->setRAIndex(ReturnAddrIndex);
2992 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2996 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2997 bool hasSymbolicDisplacement) {
2998 // Offset should fit into 32 bit immediate field.
2999 if (!isInt<32>(Offset))
3002 // If we don't have a symbolic displacement - we don't have any extra
3004 if (!hasSymbolicDisplacement)
3007 // FIXME: Some tweaks might be needed for medium code model.
3008 if (M != CodeModel::Small && M != CodeModel::Kernel)
3011 // For small code model we assume that latest object is 16MB before end of 31
3012 // bits boundary. We may also accept pretty large negative constants knowing
3013 // that all objects are in the positive half of address space.
3014 if (M == CodeModel::Small && Offset < 16*1024*1024)
3017 // For kernel code model we know that all object resist in the negative half
3018 // of 32bits address space. We may not accept negative offsets, since they may
3019 // be just off and we may accept pretty large positive ones.
3020 if (M == CodeModel::Kernel && Offset > 0)
3026 /// isCalleePop - Determines whether the callee is required to pop its
3027 /// own arguments. Callee pop is necessary to support tail calls.
3028 bool X86::isCalleePop(CallingConv::ID CallingConv,
3029 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3033 switch (CallingConv) {
3036 case CallingConv::X86_StdCall:
3038 case CallingConv::X86_FastCall:
3040 case CallingConv::X86_ThisCall:
3042 case CallingConv::Fast:
3044 case CallingConv::GHC:
3049 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3050 /// specific condition code, returning the condition code and the LHS/RHS of the
3051 /// comparison to make.
3052 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3053 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3055 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3056 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3057 // X > -1 -> X == 0, jump !sign.
3058 RHS = DAG.getConstant(0, RHS.getValueType());
3059 return X86::COND_NS;
3061 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3062 // X < 0 -> X == 0, jump on sign.
3065 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3067 RHS = DAG.getConstant(0, RHS.getValueType());
3068 return X86::COND_LE;
3072 switch (SetCCOpcode) {
3073 default: llvm_unreachable("Invalid integer condition!");
3074 case ISD::SETEQ: return X86::COND_E;
3075 case ISD::SETGT: return X86::COND_G;
3076 case ISD::SETGE: return X86::COND_GE;
3077 case ISD::SETLT: return X86::COND_L;
3078 case ISD::SETLE: return X86::COND_LE;
3079 case ISD::SETNE: return X86::COND_NE;
3080 case ISD::SETULT: return X86::COND_B;
3081 case ISD::SETUGT: return X86::COND_A;
3082 case ISD::SETULE: return X86::COND_BE;
3083 case ISD::SETUGE: return X86::COND_AE;
3087 // First determine if it is required or is profitable to flip the operands.
3089 // If LHS is a foldable load, but RHS is not, flip the condition.
3090 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3091 !ISD::isNON_EXTLoad(RHS.getNode())) {
3092 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3093 std::swap(LHS, RHS);
3096 switch (SetCCOpcode) {
3102 std::swap(LHS, RHS);
3106 // On a floating point condition, the flags are set as follows:
3108 // 0 | 0 | 0 | X > Y
3109 // 0 | 0 | 1 | X < Y
3110 // 1 | 0 | 0 | X == Y
3111 // 1 | 1 | 1 | unordered
3112 switch (SetCCOpcode) {
3113 default: llvm_unreachable("Condcode should be pre-legalized away");
3115 case ISD::SETEQ: return X86::COND_E;
3116 case ISD::SETOLT: // flipped
3118 case ISD::SETGT: return X86::COND_A;
3119 case ISD::SETOLE: // flipped
3121 case ISD::SETGE: return X86::COND_AE;
3122 case ISD::SETUGT: // flipped
3124 case ISD::SETLT: return X86::COND_B;
3125 case ISD::SETUGE: // flipped
3127 case ISD::SETLE: return X86::COND_BE;
3129 case ISD::SETNE: return X86::COND_NE;
3130 case ISD::SETUO: return X86::COND_P;
3131 case ISD::SETO: return X86::COND_NP;
3133 case ISD::SETUNE: return X86::COND_INVALID;
3137 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3138 /// code. Current x86 isa includes the following FP cmov instructions:
3139 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3140 static bool hasFPCMov(unsigned X86CC) {
3156 /// isFPImmLegal - Returns true if the target can instruction select the
3157 /// specified FP immediate natively. If false, the legalizer will
3158 /// materialize the FP immediate as a load from a constant pool.
3159 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3160 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3161 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3167 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3168 /// the specified range (L, H].
3169 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3170 return (Val < 0) || (Val >= Low && Val < Hi);
3173 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3174 /// specified value.
3175 static bool isUndefOrEqual(int Val, int CmpVal) {
3176 if (Val < 0 || Val == CmpVal)
3181 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3182 /// from position Pos and ending in Pos+Size, falls within the specified
3183 /// sequential range (L, L+Pos]. or is undef.
3184 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3185 unsigned Pos, unsigned Size, int Low) {
3186 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3187 if (!isUndefOrEqual(Mask[i], Low))
3192 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3193 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3194 /// the second operand.
3195 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3196 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3197 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3198 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3199 return (Mask[0] < 2 && Mask[1] < 2);
3203 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3204 /// is suitable for input to PSHUFHW.
3205 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3206 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3209 // Lower quadword copied in order or undef.
3210 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3213 // Upper quadword shuffled.
3214 for (unsigned i = 4; i != 8; ++i)
3215 if (!isUndefOrInRange(Mask[i], 4, 8))
3218 if (VT == MVT::v16i16) {
3219 // Lower quadword copied in order or undef.
3220 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3223 // Upper quadword shuffled.
3224 for (unsigned i = 12; i != 16; ++i)
3225 if (!isUndefOrInRange(Mask[i], 12, 16))
3232 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3233 /// is suitable for input to PSHUFLW.
3234 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3235 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3238 // Upper quadword copied in order.
3239 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3242 // Lower quadword shuffled.
3243 for (unsigned i = 0; i != 4; ++i)
3244 if (!isUndefOrInRange(Mask[i], 0, 4))
3247 if (VT == MVT::v16i16) {
3248 // Upper quadword copied in order.
3249 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3252 // Lower quadword shuffled.
3253 for (unsigned i = 8; i != 12; ++i)
3254 if (!isUndefOrInRange(Mask[i], 8, 12))
3261 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3262 /// is suitable for input to PALIGNR.
3263 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3264 const X86Subtarget *Subtarget) {
3265 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3266 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3269 unsigned NumElts = VT.getVectorNumElements();
3270 unsigned NumLanes = VT.getSizeInBits()/128;
3271 unsigned NumLaneElts = NumElts/NumLanes;
3273 // Do not handle 64-bit element shuffles with palignr.
3274 if (NumLaneElts == 2)
3277 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3279 for (i = 0; i != NumLaneElts; ++i) {
3284 // Lane is all undef, go to next lane
3285 if (i == NumLaneElts)
3288 int Start = Mask[i+l];
3290 // Make sure its in this lane in one of the sources
3291 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3292 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3295 // If not lane 0, then we must match lane 0
3296 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3299 // Correct second source to be contiguous with first source
3300 if (Start >= (int)NumElts)
3301 Start -= NumElts - NumLaneElts;
3303 // Make sure we're shifting in the right direction.
3304 if (Start <= (int)(i+l))
3309 // Check the rest of the elements to see if they are consecutive.
3310 for (++i; i != NumLaneElts; ++i) {
3311 int Idx = Mask[i+l];
3313 // Make sure its in this lane
3314 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3315 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3318 // If not lane 0, then we must match lane 0
3319 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3322 if (Idx >= (int)NumElts)
3323 Idx -= NumElts - NumLaneElts;
3325 if (!isUndefOrEqual(Idx, Start+i))
3334 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3335 /// the two vector operands have swapped position.
3336 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3337 unsigned NumElems) {
3338 for (unsigned i = 0; i != NumElems; ++i) {
3342 else if (idx < (int)NumElems)
3343 Mask[i] = idx + NumElems;
3345 Mask[i] = idx - NumElems;
3349 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3350 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3351 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3352 /// reverse of what x86 shuffles want.
3353 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3354 bool Commuted = false) {
3355 if (!HasAVX && VT.getSizeInBits() == 256)
3358 unsigned NumElems = VT.getVectorNumElements();
3359 unsigned NumLanes = VT.getSizeInBits()/128;
3360 unsigned NumLaneElems = NumElems/NumLanes;
3362 if (NumLaneElems != 2 && NumLaneElems != 4)
3365 // VSHUFPSY divides the resulting vector into 4 chunks.
3366 // The sources are also splitted into 4 chunks, and each destination
3367 // chunk must come from a different source chunk.
3369 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3370 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3372 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3373 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3375 // VSHUFPDY divides the resulting vector into 4 chunks.
3376 // The sources are also splitted into 4 chunks, and each destination
3377 // chunk must come from a different source chunk.
3379 // SRC1 => X3 X2 X1 X0
3380 // SRC2 => Y3 Y2 Y1 Y0
3382 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3384 unsigned HalfLaneElems = NumLaneElems/2;
3385 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3386 for (unsigned i = 0; i != NumLaneElems; ++i) {
3387 int Idx = Mask[i+l];
3388 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3389 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3391 // For VSHUFPSY, the mask of the second half must be the same as the
3392 // first but with the appropriate offsets. This works in the same way as
3393 // VPERMILPS works with masks.
3394 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3396 if (!isUndefOrEqual(Idx, Mask[i]+l))
3404 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3405 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3406 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3407 if (!VT.is128BitVector())
3410 unsigned NumElems = VT.getVectorNumElements();
3415 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3416 return isUndefOrEqual(Mask[0], 6) &&
3417 isUndefOrEqual(Mask[1], 7) &&
3418 isUndefOrEqual(Mask[2], 2) &&
3419 isUndefOrEqual(Mask[3], 3);
3422 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3423 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3425 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3426 if (!VT.is128BitVector())
3429 unsigned NumElems = VT.getVectorNumElements();
3434 return isUndefOrEqual(Mask[0], 2) &&
3435 isUndefOrEqual(Mask[1], 3) &&
3436 isUndefOrEqual(Mask[2], 2) &&
3437 isUndefOrEqual(Mask[3], 3);
3440 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3441 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3442 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3443 if (!VT.is128BitVector())
3446 unsigned NumElems = VT.getVectorNumElements();
3448 if (NumElems != 2 && NumElems != 4)
3451 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3452 if (!isUndefOrEqual(Mask[i], i + NumElems))
3455 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3456 if (!isUndefOrEqual(Mask[i], i))
3462 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3463 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3464 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3465 if (!VT.is128BitVector())
3468 unsigned NumElems = VT.getVectorNumElements();
3470 if (NumElems != 2 && NumElems != 4)
3473 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3474 if (!isUndefOrEqual(Mask[i], i))
3477 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3478 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3485 // Some special combinations that can be optimized.
3488 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3489 SelectionDAG &DAG) {
3490 EVT VT = SVOp->getValueType(0);
3491 DebugLoc dl = SVOp->getDebugLoc();
3493 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3496 ArrayRef<int> Mask = SVOp->getMask();
3498 // These are the special masks that may be optimized.
3499 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3500 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3501 bool MatchEvenMask = true;
3502 bool MatchOddMask = true;
3503 for (int i=0; i<8; ++i) {
3504 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3505 MatchEvenMask = false;
3506 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3507 MatchOddMask = false;
3509 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3510 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3512 const int *CompactionMask;
3514 CompactionMask = CompactionMaskEven;
3515 else if (MatchOddMask)
3516 CompactionMask = CompactionMaskOdd;
3520 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3522 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3523 UndefNode, CompactionMask);
3524 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3525 UndefNode, CompactionMask);
3526 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3527 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3530 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3531 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3532 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3533 bool HasAVX2, bool V2IsSplat = false) {
3534 unsigned NumElts = VT.getVectorNumElements();
3536 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3537 "Unsupported vector type for unpckh");
3539 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3540 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3543 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3544 // independently on 128-bit lanes.
3545 unsigned NumLanes = VT.getSizeInBits()/128;
3546 unsigned NumLaneElts = NumElts/NumLanes;
3548 for (unsigned l = 0; l != NumLanes; ++l) {
3549 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3550 i != (l+1)*NumLaneElts;
3553 int BitI1 = Mask[i+1];
3554 if (!isUndefOrEqual(BitI, j))
3557 if (!isUndefOrEqual(BitI1, NumElts))
3560 if (!isUndefOrEqual(BitI1, j + NumElts))
3569 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3570 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3571 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3572 bool HasAVX2, bool V2IsSplat = false) {
3573 unsigned NumElts = VT.getVectorNumElements();
3575 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3576 "Unsupported vector type for unpckh");
3578 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3579 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3582 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3583 // independently on 128-bit lanes.
3584 unsigned NumLanes = VT.getSizeInBits()/128;
3585 unsigned NumLaneElts = NumElts/NumLanes;
3587 for (unsigned l = 0; l != NumLanes; ++l) {
3588 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3589 i != (l+1)*NumLaneElts; i += 2, ++j) {
3591 int BitI1 = Mask[i+1];
3592 if (!isUndefOrEqual(BitI, j))
3595 if (isUndefOrEqual(BitI1, NumElts))
3598 if (!isUndefOrEqual(BitI1, j+NumElts))
3606 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3607 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3609 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3611 unsigned NumElts = VT.getVectorNumElements();
3613 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3614 "Unsupported vector type for unpckh");
3616 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3617 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3620 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3621 // FIXME: Need a better way to get rid of this, there's no latency difference
3622 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3623 // the former later. We should also remove the "_undef" special mask.
3624 if (NumElts == 4 && VT.getSizeInBits() == 256)
3627 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3628 // independently on 128-bit lanes.
3629 unsigned NumLanes = VT.getSizeInBits()/128;
3630 unsigned NumLaneElts = NumElts/NumLanes;
3632 for (unsigned l = 0; l != NumLanes; ++l) {
3633 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3634 i != (l+1)*NumLaneElts;
3637 int BitI1 = Mask[i+1];
3639 if (!isUndefOrEqual(BitI, j))
3641 if (!isUndefOrEqual(BitI1, j))
3649 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3650 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3652 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3653 unsigned NumElts = VT.getVectorNumElements();
3655 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3656 "Unsupported vector type for unpckh");
3658 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3659 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3662 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3663 // independently on 128-bit lanes.
3664 unsigned NumLanes = VT.getSizeInBits()/128;
3665 unsigned NumLaneElts = NumElts/NumLanes;
3667 for (unsigned l = 0; l != NumLanes; ++l) {
3668 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3669 i != (l+1)*NumLaneElts; i += 2, ++j) {
3671 int BitI1 = Mask[i+1];
3672 if (!isUndefOrEqual(BitI, j))
3674 if (!isUndefOrEqual(BitI1, j))
3681 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3682 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3683 /// MOVSD, and MOVD, i.e. setting the lowest element.
3684 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3685 if (VT.getVectorElementType().getSizeInBits() < 32)
3687 if (!VT.is128BitVector())
3690 unsigned NumElts = VT.getVectorNumElements();
3692 if (!isUndefOrEqual(Mask[0], NumElts))
3695 for (unsigned i = 1; i != NumElts; ++i)
3696 if (!isUndefOrEqual(Mask[i], i))
3702 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3703 /// as permutations between 128-bit chunks or halves. As an example: this
3705 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3706 /// The first half comes from the second half of V1 and the second half from the
3707 /// the second half of V2.
3708 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3709 if (!HasAVX || !VT.is256BitVector())
3712 // The shuffle result is divided into half A and half B. In total the two
3713 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3714 // B must come from C, D, E or F.
3715 unsigned HalfSize = VT.getVectorNumElements()/2;
3716 bool MatchA = false, MatchB = false;
3718 // Check if A comes from one of C, D, E, F.
3719 for (unsigned Half = 0; Half != 4; ++Half) {
3720 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3726 // Check if B comes from one of C, D, E, F.
3727 for (unsigned Half = 0; Half != 4; ++Half) {
3728 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3734 return MatchA && MatchB;
3737 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3738 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3739 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3740 EVT VT = SVOp->getValueType(0);
3742 unsigned HalfSize = VT.getVectorNumElements()/2;
3744 unsigned FstHalf = 0, SndHalf = 0;
3745 for (unsigned i = 0; i < HalfSize; ++i) {
3746 if (SVOp->getMaskElt(i) > 0) {
3747 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3751 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3752 if (SVOp->getMaskElt(i) > 0) {
3753 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3758 return (FstHalf | (SndHalf << 4));
3761 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3762 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3763 /// Note that VPERMIL mask matching is different depending whether theunderlying
3764 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3765 /// to the same elements of the low, but to the higher half of the source.
3766 /// In VPERMILPD the two lanes could be shuffled independently of each other
3767 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3768 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3772 unsigned NumElts = VT.getVectorNumElements();
3773 // Only match 256-bit with 32/64-bit types
3774 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3777 unsigned NumLanes = VT.getSizeInBits()/128;
3778 unsigned LaneSize = NumElts/NumLanes;
3779 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3780 for (unsigned i = 0; i != LaneSize; ++i) {
3781 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3783 if (NumElts != 8 || l == 0)
3785 // VPERMILPS handling
3788 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3796 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3797 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3798 /// element of vector 2 and the other elements to come from vector 1 in order.
3799 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3800 bool V2IsSplat = false, bool V2IsUndef = false) {
3801 if (!VT.is128BitVector())
3804 unsigned NumOps = VT.getVectorNumElements();
3805 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3808 if (!isUndefOrEqual(Mask[0], 0))
3811 for (unsigned i = 1; i != NumOps; ++i)
3812 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3813 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3814 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3820 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3821 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3822 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3823 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3824 const X86Subtarget *Subtarget) {
3825 if (!Subtarget->hasSSE3())
3828 unsigned NumElems = VT.getVectorNumElements();
3830 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3831 (VT.getSizeInBits() == 256 && NumElems != 8))
3834 // "i+1" is the value the indexed mask element must have
3835 for (unsigned i = 0; i != NumElems; i += 2)
3836 if (!isUndefOrEqual(Mask[i], i+1) ||
3837 !isUndefOrEqual(Mask[i+1], i+1))
3843 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3844 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3845 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3846 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3847 const X86Subtarget *Subtarget) {
3848 if (!Subtarget->hasSSE3())
3851 unsigned NumElems = VT.getVectorNumElements();
3853 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3854 (VT.getSizeInBits() == 256 && NumElems != 8))
3857 // "i" is the value the indexed mask element must have
3858 for (unsigned i = 0; i != NumElems; i += 2)
3859 if (!isUndefOrEqual(Mask[i], i) ||
3860 !isUndefOrEqual(Mask[i+1], i))
3866 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3867 /// specifies a shuffle of elements that is suitable for input to 256-bit
3868 /// version of MOVDDUP.
3869 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3870 if (!HasAVX || !VT.is256BitVector())
3873 unsigned NumElts = VT.getVectorNumElements();
3877 for (unsigned i = 0; i != NumElts/2; ++i)
3878 if (!isUndefOrEqual(Mask[i], 0))
3880 for (unsigned i = NumElts/2; i != NumElts; ++i)
3881 if (!isUndefOrEqual(Mask[i], NumElts/2))
3886 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3887 /// specifies a shuffle of elements that is suitable for input to 128-bit
3888 /// version of MOVDDUP.
3889 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3890 if (!VT.is128BitVector())
3893 unsigned e = VT.getVectorNumElements() / 2;
3894 for (unsigned i = 0; i != e; ++i)
3895 if (!isUndefOrEqual(Mask[i], i))
3897 for (unsigned i = 0; i != e; ++i)
3898 if (!isUndefOrEqual(Mask[e+i], i))
3903 /// isVEXTRACTF128Index - Return true if the specified
3904 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3905 /// suitable for input to VEXTRACTF128.
3906 bool X86::isVEXTRACTF128Index(SDNode *N) {
3907 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3910 // The index should be aligned on a 128-bit boundary.
3912 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3914 unsigned VL = N->getValueType(0).getVectorNumElements();
3915 unsigned VBits = N->getValueType(0).getSizeInBits();
3916 unsigned ElSize = VBits / VL;
3917 bool Result = (Index * ElSize) % 128 == 0;
3922 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3923 /// operand specifies a subvector insert that is suitable for input to
3925 bool X86::isVINSERTF128Index(SDNode *N) {
3926 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3929 // The index should be aligned on a 128-bit boundary.
3931 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3933 unsigned VL = N->getValueType(0).getVectorNumElements();
3934 unsigned VBits = N->getValueType(0).getSizeInBits();
3935 unsigned ElSize = VBits / VL;
3936 bool Result = (Index * ElSize) % 128 == 0;
3941 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3942 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3943 /// Handles 128-bit and 256-bit.
3944 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3945 EVT VT = N->getValueType(0);
3947 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3948 "Unsupported vector type for PSHUF/SHUFP");
3950 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3951 // independently on 128-bit lanes.
3952 unsigned NumElts = VT.getVectorNumElements();
3953 unsigned NumLanes = VT.getSizeInBits()/128;
3954 unsigned NumLaneElts = NumElts/NumLanes;
3956 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3957 "Only supports 2 or 4 elements per lane");
3959 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3961 for (unsigned i = 0; i != NumElts; ++i) {
3962 int Elt = N->getMaskElt(i);
3963 if (Elt < 0) continue;
3964 Elt &= NumLaneElts - 1;
3965 unsigned ShAmt = (i << Shift) % 8;
3966 Mask |= Elt << ShAmt;
3972 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3973 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3974 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3975 EVT VT = N->getValueType(0);
3977 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3978 "Unsupported vector type for PSHUFHW");
3980 unsigned NumElts = VT.getVectorNumElements();
3983 for (unsigned l = 0; l != NumElts; l += 8) {
3984 // 8 nodes per lane, but we only care about the last 4.
3985 for (unsigned i = 0; i < 4; ++i) {
3986 int Elt = N->getMaskElt(l+i+4);
3987 if (Elt < 0) continue;
3988 Elt &= 0x3; // only 2-bits.
3989 Mask |= Elt << (i * 2);
3996 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3997 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3998 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3999 EVT VT = N->getValueType(0);
4001 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4002 "Unsupported vector type for PSHUFHW");
4004 unsigned NumElts = VT.getVectorNumElements();
4007 for (unsigned l = 0; l != NumElts; l += 8) {
4008 // 8 nodes per lane, but we only care about the first 4.
4009 for (unsigned i = 0; i < 4; ++i) {
4010 int Elt = N->getMaskElt(l+i);
4011 if (Elt < 0) continue;
4012 Elt &= 0x3; // only 2-bits
4013 Mask |= Elt << (i * 2);
4020 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4021 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4022 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4023 EVT VT = SVOp->getValueType(0);
4024 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4026 unsigned NumElts = VT.getVectorNumElements();
4027 unsigned NumLanes = VT.getSizeInBits()/128;
4028 unsigned NumLaneElts = NumElts/NumLanes;
4032 for (i = 0; i != NumElts; ++i) {
4033 Val = SVOp->getMaskElt(i);
4037 if (Val >= (int)NumElts)
4038 Val -= NumElts - NumLaneElts;
4040 assert(Val - i > 0 && "PALIGNR imm should be positive");
4041 return (Val - i) * EltSize;
4044 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4045 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4047 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4049 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4052 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4054 EVT VecVT = N->getOperand(0).getValueType();
4055 EVT ElVT = VecVT.getVectorElementType();
4057 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4058 return Index / NumElemsPerChunk;
4061 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4062 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4064 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4065 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4066 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4069 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4071 EVT VecVT = N->getValueType(0);
4072 EVT ElVT = VecVT.getVectorElementType();
4074 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4075 return Index / NumElemsPerChunk;
4078 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4079 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4080 /// Handles 256-bit.
4081 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4082 EVT VT = N->getValueType(0);
4084 unsigned NumElts = VT.getVectorNumElements();
4086 assert((VT.is256BitVector() && NumElts == 4) &&
4087 "Unsupported vector type for VPERMQ/VPERMPD");
4090 for (unsigned i = 0; i != NumElts; ++i) {
4091 int Elt = N->getMaskElt(i);
4094 Mask |= Elt << (i*2);
4099 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4101 bool X86::isZeroNode(SDValue Elt) {
4102 return ((isa<ConstantSDNode>(Elt) &&
4103 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4104 (isa<ConstantFPSDNode>(Elt) &&
4105 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4108 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4109 /// their permute mask.
4110 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4111 SelectionDAG &DAG) {
4112 EVT VT = SVOp->getValueType(0);
4113 unsigned NumElems = VT.getVectorNumElements();
4114 SmallVector<int, 8> MaskVec;
4116 for (unsigned i = 0; i != NumElems; ++i) {
4117 int Idx = SVOp->getMaskElt(i);
4119 if (Idx < (int)NumElems)
4124 MaskVec.push_back(Idx);
4126 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4127 SVOp->getOperand(0), &MaskVec[0]);
4130 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4131 /// match movhlps. The lower half elements should come from upper half of
4132 /// V1 (and in order), and the upper half elements should come from the upper
4133 /// half of V2 (and in order).
4134 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4135 if (!VT.is128BitVector())
4137 if (VT.getVectorNumElements() != 4)
4139 for (unsigned i = 0, e = 2; i != e; ++i)
4140 if (!isUndefOrEqual(Mask[i], i+2))
4142 for (unsigned i = 2; i != 4; ++i)
4143 if (!isUndefOrEqual(Mask[i], i+4))
4148 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4149 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4151 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4152 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4154 N = N->getOperand(0).getNode();
4155 if (!ISD::isNON_EXTLoad(N))
4158 *LD = cast<LoadSDNode>(N);
4162 // Test whether the given value is a vector value which will be legalized
4164 static bool WillBeConstantPoolLoad(SDNode *N) {
4165 if (N->getOpcode() != ISD::BUILD_VECTOR)
4168 // Check for any non-constant elements.
4169 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4170 switch (N->getOperand(i).getNode()->getOpcode()) {
4172 case ISD::ConstantFP:
4179 // Vectors of all-zeros and all-ones are materialized with special
4180 // instructions rather than being loaded.
4181 return !ISD::isBuildVectorAllZeros(N) &&
4182 !ISD::isBuildVectorAllOnes(N);
4185 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4186 /// match movlp{s|d}. The lower half elements should come from lower half of
4187 /// V1 (and in order), and the upper half elements should come from the upper
4188 /// half of V2 (and in order). And since V1 will become the source of the
4189 /// MOVLP, it must be either a vector load or a scalar load to vector.
4190 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4191 ArrayRef<int> Mask, EVT VT) {
4192 if (!VT.is128BitVector())
4195 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4197 // Is V2 is a vector load, don't do this transformation. We will try to use
4198 // load folding shufps op.
4199 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4202 unsigned NumElems = VT.getVectorNumElements();
4204 if (NumElems != 2 && NumElems != 4)
4206 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4207 if (!isUndefOrEqual(Mask[i], i))
4209 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4210 if (!isUndefOrEqual(Mask[i], i+NumElems))
4215 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4217 static bool isSplatVector(SDNode *N) {
4218 if (N->getOpcode() != ISD::BUILD_VECTOR)
4221 SDValue SplatValue = N->getOperand(0);
4222 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4223 if (N->getOperand(i) != SplatValue)
4228 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4229 /// to an zero vector.
4230 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4231 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4232 SDValue V1 = N->getOperand(0);
4233 SDValue V2 = N->getOperand(1);
4234 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4235 for (unsigned i = 0; i != NumElems; ++i) {
4236 int Idx = N->getMaskElt(i);
4237 if (Idx >= (int)NumElems) {
4238 unsigned Opc = V2.getOpcode();
4239 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4241 if (Opc != ISD::BUILD_VECTOR ||
4242 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4244 } else if (Idx >= 0) {
4245 unsigned Opc = V1.getOpcode();
4246 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4248 if (Opc != ISD::BUILD_VECTOR ||
4249 !X86::isZeroNode(V1.getOperand(Idx)))
4256 /// getZeroVector - Returns a vector of specified type with all zero elements.
4258 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4259 SelectionDAG &DAG, DebugLoc dl) {
4260 assert(VT.isVector() && "Expected a vector type");
4261 unsigned Size = VT.getSizeInBits();
4263 // Always build SSE zero vectors as <4 x i32> bitcasted
4264 // to their dest type. This ensures they get CSE'd.
4266 if (Size == 128) { // SSE
4267 if (Subtarget->hasSSE2()) { // SSE2
4268 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4271 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4272 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4274 } else if (Size == 256) { // AVX
4275 if (Subtarget->hasAVX2()) { // AVX2
4276 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4277 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4278 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4280 // 256-bit logic and arithmetic instructions in AVX are all
4281 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4282 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4283 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4284 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4287 llvm_unreachable("Unexpected vector type");
4289 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4292 /// getOnesVector - Returns a vector of specified type with all bits set.
4293 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4294 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4295 /// Then bitcast to their original type, ensuring they get CSE'd.
4296 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4298 assert(VT.isVector() && "Expected a vector type");
4299 unsigned Size = VT.getSizeInBits();
4301 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4304 if (HasAVX2) { // AVX2
4305 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4306 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4308 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4309 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4311 } else if (Size == 128) {
4312 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4314 llvm_unreachable("Unexpected vector type");
4316 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4319 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4320 /// that point to V2 points to its first element.
4321 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4322 for (unsigned i = 0; i != NumElems; ++i) {
4323 if (Mask[i] > (int)NumElems) {
4329 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4330 /// operation of specified width.
4331 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4333 unsigned NumElems = VT.getVectorNumElements();
4334 SmallVector<int, 8> Mask;
4335 Mask.push_back(NumElems);
4336 for (unsigned i = 1; i != NumElems; ++i)
4338 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4341 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4342 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4344 unsigned NumElems = VT.getVectorNumElements();
4345 SmallVector<int, 8> Mask;
4346 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4348 Mask.push_back(i + NumElems);
4350 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4353 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4354 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4356 unsigned NumElems = VT.getVectorNumElements();
4357 SmallVector<int, 8> Mask;
4358 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4359 Mask.push_back(i + Half);
4360 Mask.push_back(i + NumElems + Half);
4362 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4365 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4366 // a generic shuffle instruction because the target has no such instructions.
4367 // Generate shuffles which repeat i16 and i8 several times until they can be
4368 // represented by v4f32 and then be manipulated by target suported shuffles.
4369 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4370 EVT VT = V.getValueType();
4371 int NumElems = VT.getVectorNumElements();
4372 DebugLoc dl = V.getDebugLoc();
4374 while (NumElems > 4) {
4375 if (EltNo < NumElems/2) {
4376 V = getUnpackl(DAG, dl, VT, V, V);
4378 V = getUnpackh(DAG, dl, VT, V, V);
4379 EltNo -= NumElems/2;
4386 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4387 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4388 EVT VT = V.getValueType();
4389 DebugLoc dl = V.getDebugLoc();
4390 unsigned Size = VT.getSizeInBits();
4393 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4394 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4395 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4397 } else if (Size == 256) {
4398 // To use VPERMILPS to splat scalars, the second half of indicies must
4399 // refer to the higher part, which is a duplication of the lower one,
4400 // because VPERMILPS can only handle in-lane permutations.
4401 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4402 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4404 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4405 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4408 llvm_unreachable("Vector size not supported");
4410 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4413 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4414 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4415 EVT SrcVT = SV->getValueType(0);
4416 SDValue V1 = SV->getOperand(0);
4417 DebugLoc dl = SV->getDebugLoc();
4419 int EltNo = SV->getSplatIndex();
4420 int NumElems = SrcVT.getVectorNumElements();
4421 unsigned Size = SrcVT.getSizeInBits();
4423 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4424 "Unknown how to promote splat for type");
4426 // Extract the 128-bit part containing the splat element and update
4427 // the splat element index when it refers to the higher register.
4429 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4430 if (EltNo >= NumElems/2)
4431 EltNo -= NumElems/2;
4434 // All i16 and i8 vector types can't be used directly by a generic shuffle
4435 // instruction because the target has no such instruction. Generate shuffles
4436 // which repeat i16 and i8 several times until they fit in i32, and then can
4437 // be manipulated by target suported shuffles.
4438 EVT EltVT = SrcVT.getVectorElementType();
4439 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4440 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4442 // Recreate the 256-bit vector and place the same 128-bit vector
4443 // into the low and high part. This is necessary because we want
4444 // to use VPERM* to shuffle the vectors
4446 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4449 return getLegalSplat(DAG, V1, EltNo);
4452 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4453 /// vector of zero or undef vector. This produces a shuffle where the low
4454 /// element of V2 is swizzled into the zero/undef vector, landing at element
4455 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4456 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4458 const X86Subtarget *Subtarget,
4459 SelectionDAG &DAG) {
4460 EVT VT = V2.getValueType();
4462 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4463 unsigned NumElems = VT.getVectorNumElements();
4464 SmallVector<int, 16> MaskVec;
4465 for (unsigned i = 0; i != NumElems; ++i)
4466 // If this is the insertion idx, put the low elt of V2 here.
4467 MaskVec.push_back(i == Idx ? NumElems : i);
4468 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4471 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4472 /// target specific opcode. Returns true if the Mask could be calculated.
4473 /// Sets IsUnary to true if only uses one source.
4474 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4475 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4476 unsigned NumElems = VT.getVectorNumElements();
4480 switch(N->getOpcode()) {
4482 ImmN = N->getOperand(N->getNumOperands()-1);
4483 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4485 case X86ISD::UNPCKH:
4486 DecodeUNPCKHMask(VT, Mask);
4488 case X86ISD::UNPCKL:
4489 DecodeUNPCKLMask(VT, Mask);
4491 case X86ISD::MOVHLPS:
4492 DecodeMOVHLPSMask(NumElems, Mask);
4494 case X86ISD::MOVLHPS:
4495 DecodeMOVLHPSMask(NumElems, Mask);
4497 case X86ISD::PSHUFD:
4498 case X86ISD::VPERMILP:
4499 ImmN = N->getOperand(N->getNumOperands()-1);
4500 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4503 case X86ISD::PSHUFHW:
4504 ImmN = N->getOperand(N->getNumOperands()-1);
4505 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4508 case X86ISD::PSHUFLW:
4509 ImmN = N->getOperand(N->getNumOperands()-1);
4510 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4513 case X86ISD::VPERMI:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4519 case X86ISD::MOVSD: {
4520 // The index 0 always comes from the first element of the second source,
4521 // this is why MOVSS and MOVSD are used in the first place. The other
4522 // elements come from the other positions of the first source vector
4523 Mask.push_back(NumElems);
4524 for (unsigned i = 1; i != NumElems; ++i) {
4529 case X86ISD::VPERM2X128:
4530 ImmN = N->getOperand(N->getNumOperands()-1);
4531 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4532 if (Mask.empty()) return false;
4534 case X86ISD::MOVDDUP:
4535 case X86ISD::MOVLHPD:
4536 case X86ISD::MOVLPD:
4537 case X86ISD::MOVLPS:
4538 case X86ISD::MOVSHDUP:
4539 case X86ISD::MOVSLDUP:
4540 case X86ISD::PALIGN:
4541 // Not yet implemented
4543 default: llvm_unreachable("unknown target shuffle node");
4549 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4550 /// element of the result of the vector shuffle.
4551 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4554 return SDValue(); // Limit search depth.
4556 SDValue V = SDValue(N, 0);
4557 EVT VT = V.getValueType();
4558 unsigned Opcode = V.getOpcode();
4560 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4561 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4562 int Elt = SV->getMaskElt(Index);
4565 return DAG.getUNDEF(VT.getVectorElementType());
4567 unsigned NumElems = VT.getVectorNumElements();
4568 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4569 : SV->getOperand(1);
4570 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4573 // Recurse into target specific vector shuffles to find scalars.
4574 if (isTargetShuffle(Opcode)) {
4575 MVT ShufVT = V.getValueType().getSimpleVT();
4576 unsigned NumElems = ShufVT.getVectorNumElements();
4577 SmallVector<int, 16> ShuffleMask;
4581 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4584 int Elt = ShuffleMask[Index];
4586 return DAG.getUNDEF(ShufVT.getVectorElementType());
4588 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4590 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4594 // Actual nodes that may contain scalar elements
4595 if (Opcode == ISD::BITCAST) {
4596 V = V.getOperand(0);
4597 EVT SrcVT = V.getValueType();
4598 unsigned NumElems = VT.getVectorNumElements();
4600 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4604 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4605 return (Index == 0) ? V.getOperand(0)
4606 : DAG.getUNDEF(VT.getVectorElementType());
4608 if (V.getOpcode() == ISD::BUILD_VECTOR)
4609 return V.getOperand(Index);
4614 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4615 /// shuffle operation which come from a consecutively from a zero. The
4616 /// search can start in two different directions, from left or right.
4618 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4619 bool ZerosFromLeft, SelectionDAG &DAG) {
4621 for (i = 0; i != NumElems; ++i) {
4622 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4623 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4624 if (!(Elt.getNode() &&
4625 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4632 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4633 /// correspond consecutively to elements from one of the vector operands,
4634 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4636 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4637 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4638 unsigned NumElems, unsigned &OpNum) {
4639 bool SeenV1 = false;
4640 bool SeenV2 = false;
4642 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4643 int Idx = SVOp->getMaskElt(i);
4644 // Ignore undef indicies
4648 if (Idx < (int)NumElems)
4653 // Only accept consecutive elements from the same vector
4654 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4658 OpNum = SeenV1 ? 0 : 1;
4662 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4663 /// logical left shift of a vector.
4664 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4665 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4666 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4667 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4668 false /* check zeros from right */, DAG);
4674 // Considering the elements in the mask that are not consecutive zeros,
4675 // check if they consecutively come from only one of the source vectors.
4677 // V1 = {X, A, B, C} 0
4679 // vector_shuffle V1, V2 <1, 2, 3, X>
4681 if (!isShuffleMaskConsecutive(SVOp,
4682 0, // Mask Start Index
4683 NumElems-NumZeros, // Mask End Index(exclusive)
4684 NumZeros, // Where to start looking in the src vector
4685 NumElems, // Number of elements in vector
4686 OpSrc)) // Which source operand ?
4691 ShVal = SVOp->getOperand(OpSrc);
4695 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4696 /// logical left shift of a vector.
4697 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4698 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4699 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4700 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4701 true /* check zeros from left */, DAG);
4707 // Considering the elements in the mask that are not consecutive zeros,
4708 // check if they consecutively come from only one of the source vectors.
4710 // 0 { A, B, X, X } = V2
4712 // vector_shuffle V1, V2 <X, X, 4, 5>
4714 if (!isShuffleMaskConsecutive(SVOp,
4715 NumZeros, // Mask Start Index
4716 NumElems, // Mask End Index(exclusive)
4717 0, // Where to start looking in the src vector
4718 NumElems, // Number of elements in vector
4719 OpSrc)) // Which source operand ?
4724 ShVal = SVOp->getOperand(OpSrc);
4728 /// isVectorShift - Returns true if the shuffle can be implemented as a
4729 /// logical left or right shift of a vector.
4730 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4731 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4732 // Although the logic below support any bitwidth size, there are no
4733 // shift instructions which handle more than 128-bit vectors.
4734 if (!SVOp->getValueType(0).is128BitVector())
4737 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4738 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4744 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4746 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4747 unsigned NumNonZero, unsigned NumZero,
4749 const X86Subtarget* Subtarget,
4750 const TargetLowering &TLI) {
4754 DebugLoc dl = Op.getDebugLoc();
4757 for (unsigned i = 0; i < 16; ++i) {
4758 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4759 if (ThisIsNonZero && First) {
4761 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4763 V = DAG.getUNDEF(MVT::v8i16);
4768 SDValue ThisElt(0, 0), LastElt(0, 0);
4769 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4770 if (LastIsNonZero) {
4771 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4772 MVT::i16, Op.getOperand(i-1));
4774 if (ThisIsNonZero) {
4775 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4776 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4777 ThisElt, DAG.getConstant(8, MVT::i8));
4779 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4783 if (ThisElt.getNode())
4784 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4785 DAG.getIntPtrConstant(i/2));
4789 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4792 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4794 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4795 unsigned NumNonZero, unsigned NumZero,
4797 const X86Subtarget* Subtarget,
4798 const TargetLowering &TLI) {
4802 DebugLoc dl = Op.getDebugLoc();
4805 for (unsigned i = 0; i < 8; ++i) {
4806 bool isNonZero = (NonZeros & (1 << i)) != 0;
4810 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4812 V = DAG.getUNDEF(MVT::v8i16);
4815 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4816 MVT::v8i16, V, Op.getOperand(i),
4817 DAG.getIntPtrConstant(i));
4824 /// getVShift - Return a vector logical shift node.
4826 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4827 unsigned NumBits, SelectionDAG &DAG,
4828 const TargetLowering &TLI, DebugLoc dl) {
4829 assert(VT.is128BitVector() && "Unknown type for VShift");
4830 EVT ShVT = MVT::v2i64;
4831 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4832 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4833 return DAG.getNode(ISD::BITCAST, dl, VT,
4834 DAG.getNode(Opc, dl, ShVT, SrcOp,
4835 DAG.getConstant(NumBits,
4836 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4840 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4841 SelectionDAG &DAG) const {
4843 // Check if the scalar load can be widened into a vector load. And if
4844 // the address is "base + cst" see if the cst can be "absorbed" into
4845 // the shuffle mask.
4846 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4847 SDValue Ptr = LD->getBasePtr();
4848 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4850 EVT PVT = LD->getValueType(0);
4851 if (PVT != MVT::i32 && PVT != MVT::f32)
4856 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4857 FI = FINode->getIndex();
4859 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4860 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4861 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4862 Offset = Ptr.getConstantOperandVal(1);
4863 Ptr = Ptr.getOperand(0);
4868 // FIXME: 256-bit vector instructions don't require a strict alignment,
4869 // improve this code to support it better.
4870 unsigned RequiredAlign = VT.getSizeInBits()/8;
4871 SDValue Chain = LD->getChain();
4872 // Make sure the stack object alignment is at least 16 or 32.
4873 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4874 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4875 if (MFI->isFixedObjectIndex(FI)) {
4876 // Can't change the alignment. FIXME: It's possible to compute
4877 // the exact stack offset and reference FI + adjust offset instead.
4878 // If someone *really* cares about this. That's the way to implement it.
4881 MFI->setObjectAlignment(FI, RequiredAlign);
4885 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4886 // Ptr + (Offset & ~15).
4889 if ((Offset % RequiredAlign) & 3)
4891 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4893 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4894 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4896 int EltNo = (Offset - StartOffset) >> 2;
4897 unsigned NumElems = VT.getVectorNumElements();
4899 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4900 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4901 LD->getPointerInfo().getWithOffset(StartOffset),
4902 false, false, false, 0);
4904 SmallVector<int, 8> Mask;
4905 for (unsigned i = 0; i != NumElems; ++i)
4906 Mask.push_back(EltNo);
4908 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4914 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4915 /// vector of type 'VT', see if the elements can be replaced by a single large
4916 /// load which has the same value as a build_vector whose operands are 'elts'.
4918 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4920 /// FIXME: we'd also like to handle the case where the last elements are zero
4921 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4922 /// There's even a handy isZeroNode for that purpose.
4923 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4924 DebugLoc &DL, SelectionDAG &DAG) {
4925 EVT EltVT = VT.getVectorElementType();
4926 unsigned NumElems = Elts.size();
4928 LoadSDNode *LDBase = NULL;
4929 unsigned LastLoadedElt = -1U;
4931 // For each element in the initializer, see if we've found a load or an undef.
4932 // If we don't find an initial load element, or later load elements are
4933 // non-consecutive, bail out.
4934 for (unsigned i = 0; i < NumElems; ++i) {
4935 SDValue Elt = Elts[i];
4937 if (!Elt.getNode() ||
4938 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4941 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4943 LDBase = cast<LoadSDNode>(Elt.getNode());
4947 if (Elt.getOpcode() == ISD::UNDEF)
4950 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4951 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4956 // If we have found an entire vector of loads and undefs, then return a large
4957 // load of the entire vector width starting at the base pointer. If we found
4958 // consecutive loads for the low half, generate a vzext_load node.
4959 if (LastLoadedElt == NumElems - 1) {
4960 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4961 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4962 LDBase->getPointerInfo(),
4963 LDBase->isVolatile(), LDBase->isNonTemporal(),
4964 LDBase->isInvariant(), 0);
4965 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4966 LDBase->getPointerInfo(),
4967 LDBase->isVolatile(), LDBase->isNonTemporal(),
4968 LDBase->isInvariant(), LDBase->getAlignment());
4970 if (NumElems == 4 && LastLoadedElt == 1 &&
4971 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4972 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4973 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4975 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4976 LDBase->getPointerInfo(),
4977 LDBase->getAlignment(),
4978 false/*isVolatile*/, true/*ReadMem*/,
4980 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4985 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4986 /// to generate a splat value for the following cases:
4987 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4988 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4989 /// a scalar load, or a constant.
4990 /// The VBROADCAST node is returned when a pattern is found,
4991 /// or SDValue() otherwise.
4993 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4994 if (!Subtarget->hasAVX())
4997 EVT VT = Op.getValueType();
4998 DebugLoc dl = Op.getDebugLoc();
5000 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5001 "Unsupported vector type for broadcast.");
5006 switch (Op.getOpcode()) {
5008 // Unknown pattern found.
5011 case ISD::BUILD_VECTOR: {
5012 // The BUILD_VECTOR node must be a splat.
5013 if (!isSplatVector(Op.getNode()))
5016 Ld = Op.getOperand(0);
5017 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5018 Ld.getOpcode() == ISD::ConstantFP);
5020 // The suspected load node has several users. Make sure that all
5021 // of its users are from the BUILD_VECTOR node.
5022 // Constants may have multiple users.
5023 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5028 case ISD::VECTOR_SHUFFLE: {
5029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5031 // Shuffles must have a splat mask where the first element is
5033 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5036 SDValue Sc = Op.getOperand(0);
5037 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5038 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5040 if (!Subtarget->hasAVX2())
5043 // Use the register form of the broadcast instruction available on AVX2.
5044 if (VT.is256BitVector())
5045 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5046 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5049 Ld = Sc.getOperand(0);
5050 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5051 Ld.getOpcode() == ISD::ConstantFP);
5053 // The scalar_to_vector node and the suspected
5054 // load node must have exactly one user.
5055 // Constants may have multiple users.
5056 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5062 bool Is256 = VT.is256BitVector();
5064 // Handle the broadcasting a single constant scalar from the constant pool
5065 // into a vector. On Sandybridge it is still better to load a constant vector
5066 // from the constant pool and not to broadcast it from a scalar.
5067 if (ConstSplatVal && Subtarget->hasAVX2()) {
5068 EVT CVT = Ld.getValueType();
5069 assert(!CVT.isVector() && "Must not broadcast a vector type");
5070 unsigned ScalarSize = CVT.getSizeInBits();
5072 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5073 const Constant *C = 0;
5074 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5075 C = CI->getConstantIntValue();
5076 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5077 C = CF->getConstantFPValue();
5079 assert(C && "Invalid constant type");
5081 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5082 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5083 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5084 MachinePointerInfo::getConstantPool(),
5085 false, false, false, Alignment);
5087 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5091 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5092 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5094 // Handle AVX2 in-register broadcasts.
5095 if (!IsLoad && Subtarget->hasAVX2() &&
5096 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5097 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5099 // The scalar source must be a normal load.
5103 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5104 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5106 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5107 // double since there is no vbroadcastsd xmm
5108 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5109 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5110 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5113 // Unsupported broadcast.
5117 // LowerVectorFpExtend - Recognize the scalarized FP_EXTEND from v2f32 to v2f64
5118 // and convert it into X86ISD::VFPEXT due to the current ISD::FP_EXTEND has the
5119 // constraint of matching input/output vector elements.
5121 X86TargetLowering::LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const {
5122 DebugLoc DL = Op.getDebugLoc();
5123 SDNode *N = Op.getNode();
5124 EVT VT = Op.getValueType();
5125 unsigned NumElts = Op.getNumOperands();
5127 // Check supported types and sub-targets.
5129 // Only v2f32 -> v2f64 needs special handling.
5130 if (VT != MVT::v2f64 || !Subtarget->hasSSE2())
5135 SmallVector<int, 8> Mask;
5136 EVT SrcVT = MVT::Other;
5138 // Check the patterns could be translated into X86vfpext.
5139 for (unsigned i = 0; i < NumElts; ++i) {
5140 SDValue In = N->getOperand(i);
5141 unsigned Opcode = In.getOpcode();
5143 // Skip if the element is undefined.
5144 if (Opcode == ISD::UNDEF) {
5149 // Quit if one of the elements is not defined from 'fpext'.
5150 if (Opcode != ISD::FP_EXTEND)
5153 // Check how the source of 'fpext' is defined.
5154 SDValue L2In = In.getOperand(0);
5155 EVT L2InVT = L2In.getValueType();
5157 // Check the original type
5158 if (SrcVT == MVT::Other)
5160 else if (SrcVT != L2InVT) // Quit if non-homogenous typed.
5163 // Check whether the value being 'fpext'ed is extracted from the same
5165 Opcode = L2In.getOpcode();
5167 // Quit if it's not extracted with a constant index.
5168 if (Opcode != ISD::EXTRACT_VECTOR_ELT ||
5169 !isa<ConstantSDNode>(L2In.getOperand(1)))
5172 SDValue ExtractedFromVec = L2In.getOperand(0);
5174 if (VecIn.getNode() == 0) {
5175 VecIn = ExtractedFromVec;
5176 VecInVT = ExtractedFromVec.getValueType();
5177 } else if (VecIn != ExtractedFromVec) // Quit if built from more than 1 vec.
5180 Mask.push_back(cast<ConstantSDNode>(L2In.getOperand(1))->getZExtValue());
5183 // Fill the remaining mask as undef.
5184 for (unsigned i = NumElts; i < VecInVT.getVectorNumElements(); ++i)
5187 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
5188 DAG.getVectorShuffle(VecInVT, DL,
5189 VecIn, DAG.getUNDEF(VecInVT),
5194 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5195 DebugLoc dl = Op.getDebugLoc();
5197 EVT VT = Op.getValueType();
5198 EVT ExtVT = VT.getVectorElementType();
5199 unsigned NumElems = Op.getNumOperands();
5201 // Vectors containing all zeros can be matched by pxor and xorps later
5202 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5203 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5204 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5205 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5208 return getZeroVector(VT, Subtarget, DAG, dl);
5211 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5212 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5213 // vpcmpeqd on 256-bit vectors.
5214 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5215 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5218 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5221 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5222 if (Broadcast.getNode())
5225 SDValue FpExt = LowerVectorFpExtend(Op, DAG);
5226 if (FpExt.getNode())
5229 unsigned EVTBits = ExtVT.getSizeInBits();
5231 unsigned NumZero = 0;
5232 unsigned NumNonZero = 0;
5233 unsigned NonZeros = 0;
5234 bool IsAllConstants = true;
5235 SmallSet<SDValue, 8> Values;
5236 for (unsigned i = 0; i < NumElems; ++i) {
5237 SDValue Elt = Op.getOperand(i);
5238 if (Elt.getOpcode() == ISD::UNDEF)
5241 if (Elt.getOpcode() != ISD::Constant &&
5242 Elt.getOpcode() != ISD::ConstantFP)
5243 IsAllConstants = false;
5244 if (X86::isZeroNode(Elt))
5247 NonZeros |= (1 << i);
5252 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5253 if (NumNonZero == 0)
5254 return DAG.getUNDEF(VT);
5256 // Special case for single non-zero, non-undef, element.
5257 if (NumNonZero == 1) {
5258 unsigned Idx = CountTrailingZeros_32(NonZeros);
5259 SDValue Item = Op.getOperand(Idx);
5261 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5262 // the value are obviously zero, truncate the value to i32 and do the
5263 // insertion that way. Only do this if the value is non-constant or if the
5264 // value is a constant being inserted into element 0. It is cheaper to do
5265 // a constant pool load than it is to do a movd + shuffle.
5266 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5267 (!IsAllConstants || Idx == 0)) {
5268 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5270 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5271 EVT VecVT = MVT::v4i32;
5272 unsigned VecElts = 4;
5274 // Truncate the value (which may itself be a constant) to i32, and
5275 // convert it to a vector with movd (S2V+shuffle to zero extend).
5276 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5277 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5278 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5280 // Now we have our 32-bit value zero extended in the low element of
5281 // a vector. If Idx != 0, swizzle it into place.
5283 SmallVector<int, 4> Mask;
5284 Mask.push_back(Idx);
5285 for (unsigned i = 1; i != VecElts; ++i)
5287 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5290 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5294 // If we have a constant or non-constant insertion into the low element of
5295 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5296 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5297 // depending on what the source datatype is.
5300 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5302 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5303 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5304 if (VT.is256BitVector()) {
5305 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5306 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5307 Item, DAG.getIntPtrConstant(0));
5309 assert(VT.is128BitVector() && "Expected an SSE value type!");
5310 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5311 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5312 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5315 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5316 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5317 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5318 if (VT.is256BitVector()) {
5319 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5320 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5322 assert(VT.is128BitVector() && "Expected an SSE value type!");
5323 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5325 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5329 // Is it a vector logical left shift?
5330 if (NumElems == 2 && Idx == 1 &&
5331 X86::isZeroNode(Op.getOperand(0)) &&
5332 !X86::isZeroNode(Op.getOperand(1))) {
5333 unsigned NumBits = VT.getSizeInBits();
5334 return getVShift(true, VT,
5335 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5336 VT, Op.getOperand(1)),
5337 NumBits/2, DAG, *this, dl);
5340 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5343 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5344 // is a non-constant being inserted into an element other than the low one,
5345 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5346 // movd/movss) to move this into the low element, then shuffle it into
5348 if (EVTBits == 32) {
5349 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5351 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5352 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5353 SmallVector<int, 8> MaskVec;
5354 for (unsigned i = 0; i != NumElems; ++i)
5355 MaskVec.push_back(i == Idx ? 0 : 1);
5356 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5360 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5361 if (Values.size() == 1) {
5362 if (EVTBits == 32) {
5363 // Instead of a shuffle like this:
5364 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5365 // Check if it's possible to issue this instead.
5366 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5367 unsigned Idx = CountTrailingZeros_32(NonZeros);
5368 SDValue Item = Op.getOperand(Idx);
5369 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5370 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5375 // A vector full of immediates; various special cases are already
5376 // handled, so this is best done with a single constant-pool load.
5380 // For AVX-length vectors, build the individual 128-bit pieces and use
5381 // shuffles to put them in place.
5382 if (VT.is256BitVector()) {
5383 SmallVector<SDValue, 32> V;
5384 for (unsigned i = 0; i != NumElems; ++i)
5385 V.push_back(Op.getOperand(i));
5387 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5389 // Build both the lower and upper subvector.
5390 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5391 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5394 // Recreate the wider vector with the lower and upper part.
5395 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5398 // Let legalizer expand 2-wide build_vectors.
5399 if (EVTBits == 64) {
5400 if (NumNonZero == 1) {
5401 // One half is zero or undef.
5402 unsigned Idx = CountTrailingZeros_32(NonZeros);
5403 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5404 Op.getOperand(Idx));
5405 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5410 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5411 if (EVTBits == 8 && NumElems == 16) {
5412 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5414 if (V.getNode()) return V;
5417 if (EVTBits == 16 && NumElems == 8) {
5418 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5420 if (V.getNode()) return V;
5423 // If element VT is == 32 bits, turn it into a number of shuffles.
5424 SmallVector<SDValue, 8> V(NumElems);
5425 if (NumElems == 4 && NumZero > 0) {
5426 for (unsigned i = 0; i < 4; ++i) {
5427 bool isZero = !(NonZeros & (1 << i));
5429 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5431 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5434 for (unsigned i = 0; i < 2; ++i) {
5435 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5438 V[i] = V[i*2]; // Must be a zero vector.
5441 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5444 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5447 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5452 bool Reverse1 = (NonZeros & 0x3) == 2;
5453 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5457 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5458 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5460 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5463 if (Values.size() > 1 && VT.is128BitVector()) {
5464 // Check for a build vector of consecutive loads.
5465 for (unsigned i = 0; i < NumElems; ++i)
5466 V[i] = Op.getOperand(i);
5468 // Check for elements which are consecutive loads.
5469 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5473 // For SSE 4.1, use insertps to put the high elements into the low element.
5474 if (getSubtarget()->hasSSE41()) {
5476 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5477 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5479 Result = DAG.getUNDEF(VT);
5481 for (unsigned i = 1; i < NumElems; ++i) {
5482 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5483 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5484 Op.getOperand(i), DAG.getIntPtrConstant(i));
5489 // Otherwise, expand into a number of unpckl*, start by extending each of
5490 // our (non-undef) elements to the full vector width with the element in the
5491 // bottom slot of the vector (which generates no code for SSE).
5492 for (unsigned i = 0; i < NumElems; ++i) {
5493 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5494 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5496 V[i] = DAG.getUNDEF(VT);
5499 // Next, we iteratively mix elements, e.g. for v4f32:
5500 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5501 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5502 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5503 unsigned EltStride = NumElems >> 1;
5504 while (EltStride != 0) {
5505 for (unsigned i = 0; i < EltStride; ++i) {
5506 // If V[i+EltStride] is undef and this is the first round of mixing,
5507 // then it is safe to just drop this shuffle: V[i] is already in the
5508 // right place, the one element (since it's the first round) being
5509 // inserted as undef can be dropped. This isn't safe for successive
5510 // rounds because they will permute elements within both vectors.
5511 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5512 EltStride == NumElems/2)
5515 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5524 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5525 // to create 256-bit vectors from two other 128-bit ones.
5526 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5527 DebugLoc dl = Op.getDebugLoc();
5528 EVT ResVT = Op.getValueType();
5530 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5532 SDValue V1 = Op.getOperand(0);
5533 SDValue V2 = Op.getOperand(1);
5534 unsigned NumElems = ResVT.getVectorNumElements();
5536 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5540 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5541 assert(Op.getNumOperands() == 2);
5543 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5544 // from two other 128-bit ones.
5545 return LowerAVXCONCAT_VECTORS(Op, DAG);
5548 // Try to lower a shuffle node into a simple blend instruction.
5549 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5550 const X86Subtarget *Subtarget,
5551 SelectionDAG &DAG) {
5552 SDValue V1 = SVOp->getOperand(0);
5553 SDValue V2 = SVOp->getOperand(1);
5554 DebugLoc dl = SVOp->getDebugLoc();
5555 MVT VT = SVOp->getValueType(0).getSimpleVT();
5556 unsigned NumElems = VT.getVectorNumElements();
5558 if (!Subtarget->hasSSE41())
5564 switch (VT.SimpleTy) {
5565 default: return SDValue();
5567 ISDNo = X86ISD::BLENDPW;
5572 ISDNo = X86ISD::BLENDPS;
5577 ISDNo = X86ISD::BLENDPD;
5582 if (!Subtarget->hasAVX())
5584 ISDNo = X86ISD::BLENDPS;
5589 if (!Subtarget->hasAVX())
5591 ISDNo = X86ISD::BLENDPD;
5595 assert(ISDNo && "Invalid Op Number");
5597 unsigned MaskVals = 0;
5599 for (unsigned i = 0; i != NumElems; ++i) {
5600 int EltIdx = SVOp->getMaskElt(i);
5601 if (EltIdx == (int)i || EltIdx < 0)
5603 else if (EltIdx == (int)(i + NumElems))
5604 continue; // Bit is set to zero;
5609 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5610 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5611 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5612 DAG.getConstant(MaskVals, MVT::i32));
5613 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5616 // v8i16 shuffles - Prefer shuffles in the following order:
5617 // 1. [all] pshuflw, pshufhw, optional move
5618 // 2. [ssse3] 1 x pshufb
5619 // 3. [ssse3] 2 x pshufb + 1 x por
5620 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5622 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5623 SelectionDAG &DAG) const {
5624 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5625 SDValue V1 = SVOp->getOperand(0);
5626 SDValue V2 = SVOp->getOperand(1);
5627 DebugLoc dl = SVOp->getDebugLoc();
5628 SmallVector<int, 8> MaskVals;
5630 // Determine if more than 1 of the words in each of the low and high quadwords
5631 // of the result come from the same quadword of one of the two inputs. Undef
5632 // mask values count as coming from any quadword, for better codegen.
5633 unsigned LoQuad[] = { 0, 0, 0, 0 };
5634 unsigned HiQuad[] = { 0, 0, 0, 0 };
5635 std::bitset<4> InputQuads;
5636 for (unsigned i = 0; i < 8; ++i) {
5637 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5638 int EltIdx = SVOp->getMaskElt(i);
5639 MaskVals.push_back(EltIdx);
5648 InputQuads.set(EltIdx / 4);
5651 int BestLoQuad = -1;
5652 unsigned MaxQuad = 1;
5653 for (unsigned i = 0; i < 4; ++i) {
5654 if (LoQuad[i] > MaxQuad) {
5656 MaxQuad = LoQuad[i];
5660 int BestHiQuad = -1;
5662 for (unsigned i = 0; i < 4; ++i) {
5663 if (HiQuad[i] > MaxQuad) {
5665 MaxQuad = HiQuad[i];
5669 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5670 // of the two input vectors, shuffle them into one input vector so only a
5671 // single pshufb instruction is necessary. If There are more than 2 input
5672 // quads, disable the next transformation since it does not help SSSE3.
5673 bool V1Used = InputQuads[0] || InputQuads[1];
5674 bool V2Used = InputQuads[2] || InputQuads[3];
5675 if (Subtarget->hasSSSE3()) {
5676 if (InputQuads.count() == 2 && V1Used && V2Used) {
5677 BestLoQuad = InputQuads[0] ? 0 : 1;
5678 BestHiQuad = InputQuads[2] ? 2 : 3;
5680 if (InputQuads.count() > 2) {
5686 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5687 // the shuffle mask. If a quad is scored as -1, that means that it contains
5688 // words from all 4 input quadwords.
5690 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5692 BestLoQuad < 0 ? 0 : BestLoQuad,
5693 BestHiQuad < 0 ? 1 : BestHiQuad
5695 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5696 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5697 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5698 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5700 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5701 // source words for the shuffle, to aid later transformations.
5702 bool AllWordsInNewV = true;
5703 bool InOrder[2] = { true, true };
5704 for (unsigned i = 0; i != 8; ++i) {
5705 int idx = MaskVals[i];
5707 InOrder[i/4] = false;
5708 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5710 AllWordsInNewV = false;
5714 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5715 if (AllWordsInNewV) {
5716 for (int i = 0; i != 8; ++i) {
5717 int idx = MaskVals[i];
5720 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5721 if ((idx != i) && idx < 4)
5723 if ((idx != i) && idx > 3)
5732 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5733 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5734 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5735 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5736 unsigned TargetMask = 0;
5737 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5738 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5739 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5740 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5741 getShufflePSHUFLWImmediate(SVOp);
5742 V1 = NewV.getOperand(0);
5743 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5747 // If we have SSSE3, and all words of the result are from 1 input vector,
5748 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5749 // is present, fall back to case 4.
5750 if (Subtarget->hasSSSE3()) {
5751 SmallVector<SDValue,16> pshufbMask;
5753 // If we have elements from both input vectors, set the high bit of the
5754 // shuffle mask element to zero out elements that come from V2 in the V1
5755 // mask, and elements that come from V1 in the V2 mask, so that the two
5756 // results can be OR'd together.
5757 bool TwoInputs = V1Used && V2Used;
5758 for (unsigned i = 0; i != 8; ++i) {
5759 int EltIdx = MaskVals[i] * 2;
5760 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5761 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5762 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5763 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5765 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5766 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5767 DAG.getNode(ISD::BUILD_VECTOR, dl,
5768 MVT::v16i8, &pshufbMask[0], 16));
5770 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5772 // Calculate the shuffle mask for the second input, shuffle it, and
5773 // OR it with the first shuffled input.
5775 for (unsigned i = 0; i != 8; ++i) {
5776 int EltIdx = MaskVals[i] * 2;
5777 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5778 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5779 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5780 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5782 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5783 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5784 DAG.getNode(ISD::BUILD_VECTOR, dl,
5785 MVT::v16i8, &pshufbMask[0], 16));
5786 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5787 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5790 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5791 // and update MaskVals with new element order.
5792 std::bitset<8> InOrder;
5793 if (BestLoQuad >= 0) {
5794 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5795 for (int i = 0; i != 4; ++i) {
5796 int idx = MaskVals[i];
5799 } else if ((idx / 4) == BestLoQuad) {
5804 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5807 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5808 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5809 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5811 getShufflePSHUFLWImmediate(SVOp), DAG);
5815 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5816 // and update MaskVals with the new element order.
5817 if (BestHiQuad >= 0) {
5818 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5819 for (unsigned i = 4; i != 8; ++i) {
5820 int idx = MaskVals[i];
5823 } else if ((idx / 4) == BestHiQuad) {
5824 MaskV[i] = (idx & 3) + 4;
5828 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5831 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5833 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5835 getShufflePSHUFHWImmediate(SVOp), DAG);
5839 // In case BestHi & BestLo were both -1, which means each quadword has a word
5840 // from each of the four input quadwords, calculate the InOrder bitvector now
5841 // before falling through to the insert/extract cleanup.
5842 if (BestLoQuad == -1 && BestHiQuad == -1) {
5844 for (int i = 0; i != 8; ++i)
5845 if (MaskVals[i] < 0 || MaskVals[i] == i)
5849 // The other elements are put in the right place using pextrw and pinsrw.
5850 for (unsigned i = 0; i != 8; ++i) {
5853 int EltIdx = MaskVals[i];
5856 SDValue ExtOp = (EltIdx < 8) ?
5857 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5858 DAG.getIntPtrConstant(EltIdx)) :
5859 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5860 DAG.getIntPtrConstant(EltIdx - 8));
5861 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5862 DAG.getIntPtrConstant(i));
5867 // v16i8 shuffles - Prefer shuffles in the following order:
5868 // 1. [ssse3] 1 x pshufb
5869 // 2. [ssse3] 2 x pshufb + 1 x por
5870 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5872 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5874 const X86TargetLowering &TLI) {
5875 SDValue V1 = SVOp->getOperand(0);
5876 SDValue V2 = SVOp->getOperand(1);
5877 DebugLoc dl = SVOp->getDebugLoc();
5878 ArrayRef<int> MaskVals = SVOp->getMask();
5880 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5882 // If we have SSSE3, case 1 is generated when all result bytes come from
5883 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5884 // present, fall back to case 3.
5886 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5887 if (TLI.getSubtarget()->hasSSSE3()) {
5888 SmallVector<SDValue,16> pshufbMask;
5890 // If all result elements are from one input vector, then only translate
5891 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5893 // Otherwise, we have elements from both input vectors, and must zero out
5894 // elements that come from V2 in the first mask, and V1 in the second mask
5895 // so that we can OR them together.
5896 for (unsigned i = 0; i != 16; ++i) {
5897 int EltIdx = MaskVals[i];
5898 if (EltIdx < 0 || EltIdx >= 16)
5900 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5902 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5903 DAG.getNode(ISD::BUILD_VECTOR, dl,
5904 MVT::v16i8, &pshufbMask[0], 16));
5908 // Calculate the shuffle mask for the second input, shuffle it, and
5909 // OR it with the first shuffled input.
5911 for (unsigned i = 0; i != 16; ++i) {
5912 int EltIdx = MaskVals[i];
5913 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5914 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5916 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5917 DAG.getNode(ISD::BUILD_VECTOR, dl,
5918 MVT::v16i8, &pshufbMask[0], 16));
5919 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5922 // No SSSE3 - Calculate in place words and then fix all out of place words
5923 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5924 // the 16 different words that comprise the two doublequadword input vectors.
5925 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5926 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5928 for (int i = 0; i != 8; ++i) {
5929 int Elt0 = MaskVals[i*2];
5930 int Elt1 = MaskVals[i*2+1];
5932 // This word of the result is all undef, skip it.
5933 if (Elt0 < 0 && Elt1 < 0)
5936 // This word of the result is already in the correct place, skip it.
5937 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5940 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5941 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5944 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5945 // using a single extract together, load it and store it.
5946 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5947 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5948 DAG.getIntPtrConstant(Elt1 / 2));
5949 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5950 DAG.getIntPtrConstant(i));
5954 // If Elt1 is defined, extract it from the appropriate source. If the
5955 // source byte is not also odd, shift the extracted word left 8 bits
5956 // otherwise clear the bottom 8 bits if we need to do an or.
5958 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5959 DAG.getIntPtrConstant(Elt1 / 2));
5960 if ((Elt1 & 1) == 0)
5961 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5963 TLI.getShiftAmountTy(InsElt.getValueType())));
5965 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5966 DAG.getConstant(0xFF00, MVT::i16));
5968 // If Elt0 is defined, extract it from the appropriate source. If the
5969 // source byte is not also even, shift the extracted word right 8 bits. If
5970 // Elt1 was also defined, OR the extracted values together before
5971 // inserting them in the result.
5973 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5974 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5975 if ((Elt0 & 1) != 0)
5976 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5978 TLI.getShiftAmountTy(InsElt0.getValueType())));
5980 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5981 DAG.getConstant(0x00FF, MVT::i16));
5982 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5985 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5986 DAG.getIntPtrConstant(i));
5988 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5991 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5992 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5993 /// done when every pair / quad of shuffle mask elements point to elements in
5994 /// the right sequence. e.g.
5995 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5997 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5998 SelectionDAG &DAG, DebugLoc dl) {
5999 MVT VT = SVOp->getValueType(0).getSimpleVT();
6000 unsigned NumElems = VT.getVectorNumElements();
6003 switch (VT.SimpleTy) {
6004 default: llvm_unreachable("Unexpected!");
6005 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6006 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6007 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6008 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6009 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6010 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6013 SmallVector<int, 8> MaskVec;
6014 for (unsigned i = 0; i != NumElems; i += Scale) {
6016 for (unsigned j = 0; j != Scale; ++j) {
6017 int EltIdx = SVOp->getMaskElt(i+j);
6021 StartIdx = (EltIdx / Scale);
6022 if (EltIdx != (int)(StartIdx*Scale + j))
6025 MaskVec.push_back(StartIdx);
6028 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6029 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6030 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6033 /// getVZextMovL - Return a zero-extending vector move low node.
6035 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6036 SDValue SrcOp, SelectionDAG &DAG,
6037 const X86Subtarget *Subtarget, DebugLoc dl) {
6038 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6039 LoadSDNode *LD = NULL;
6040 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6041 LD = dyn_cast<LoadSDNode>(SrcOp);
6043 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6045 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6046 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6047 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6048 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6049 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6051 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6052 return DAG.getNode(ISD::BITCAST, dl, VT,
6053 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6054 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6062 return DAG.getNode(ISD::BITCAST, dl, VT,
6063 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6064 DAG.getNode(ISD::BITCAST, dl,
6068 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6069 /// which could not be matched by any known target speficic shuffle
6071 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6073 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6074 if (NewOp.getNode())
6077 EVT VT = SVOp->getValueType(0);
6079 unsigned NumElems = VT.getVectorNumElements();
6080 unsigned NumLaneElems = NumElems / 2;
6082 DebugLoc dl = SVOp->getDebugLoc();
6083 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6084 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6087 SmallVector<int, 16> Mask;
6088 for (unsigned l = 0; l < 2; ++l) {
6089 // Build a shuffle mask for the output, discovering on the fly which
6090 // input vectors to use as shuffle operands (recorded in InputUsed).
6091 // If building a suitable shuffle vector proves too hard, then bail
6092 // out with UseBuildVector set.
6093 bool UseBuildVector = false;
6094 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6095 unsigned LaneStart = l * NumLaneElems;
6096 for (unsigned i = 0; i != NumLaneElems; ++i) {
6097 // The mask element. This indexes into the input.
6098 int Idx = SVOp->getMaskElt(i+LaneStart);
6100 // the mask element does not index into any input vector.
6105 // The input vector this mask element indexes into.
6106 int Input = Idx / NumLaneElems;
6108 // Turn the index into an offset from the start of the input vector.
6109 Idx -= Input * NumLaneElems;
6111 // Find or create a shuffle vector operand to hold this input.
6113 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6114 if (InputUsed[OpNo] == Input)
6115 // This input vector is already an operand.
6117 if (InputUsed[OpNo] < 0) {
6118 // Create a new operand for this input vector.
6119 InputUsed[OpNo] = Input;
6124 if (OpNo >= array_lengthof(InputUsed)) {
6125 // More than two input vectors used! Give up on trying to create a
6126 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6127 UseBuildVector = true;
6131 // Add the mask index for the new shuffle vector.
6132 Mask.push_back(Idx + OpNo * NumLaneElems);
6135 if (UseBuildVector) {
6136 SmallVector<SDValue, 16> SVOps;
6137 for (unsigned i = 0; i != NumLaneElems; ++i) {
6138 // The mask element. This indexes into the input.
6139 int Idx = SVOp->getMaskElt(i+LaneStart);
6141 SVOps.push_back(DAG.getUNDEF(EltVT));
6145 // The input vector this mask element indexes into.
6146 int Input = Idx / NumElems;
6148 // Turn the index into an offset from the start of the input vector.
6149 Idx -= Input * NumElems;
6151 // Extract the vector element by hand.
6152 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6153 SVOp->getOperand(Input),
6154 DAG.getIntPtrConstant(Idx)));
6157 // Construct the output using a BUILD_VECTOR.
6158 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6160 } else if (InputUsed[0] < 0) {
6161 // No input vectors were used! The result is undefined.
6162 Output[l] = DAG.getUNDEF(NVT);
6164 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6165 (InputUsed[0] % 2) * NumLaneElems,
6167 // If only one input was used, use an undefined vector for the other.
6168 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6169 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6170 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6171 // At least one input vector was used. Create a new shuffle vector.
6172 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6178 // Concatenate the result back
6179 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6182 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6183 /// 4 elements, and match them with several different shuffle types.
6185 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6186 SDValue V1 = SVOp->getOperand(0);
6187 SDValue V2 = SVOp->getOperand(1);
6188 DebugLoc dl = SVOp->getDebugLoc();
6189 EVT VT = SVOp->getValueType(0);
6191 assert(VT.is128BitVector() && "Unsupported vector size");
6193 std::pair<int, int> Locs[4];
6194 int Mask1[] = { -1, -1, -1, -1 };
6195 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6199 for (unsigned i = 0; i != 4; ++i) {
6200 int Idx = PermMask[i];
6202 Locs[i] = std::make_pair(-1, -1);
6204 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6206 Locs[i] = std::make_pair(0, NumLo);
6210 Locs[i] = std::make_pair(1, NumHi);
6212 Mask1[2+NumHi] = Idx;
6218 if (NumLo <= 2 && NumHi <= 2) {
6219 // If no more than two elements come from either vector. This can be
6220 // implemented with two shuffles. First shuffle gather the elements.
6221 // The second shuffle, which takes the first shuffle as both of its
6222 // vector operands, put the elements into the right order.
6223 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6225 int Mask2[] = { -1, -1, -1, -1 };
6227 for (unsigned i = 0; i != 4; ++i)
6228 if (Locs[i].first != -1) {
6229 unsigned Idx = (i < 2) ? 0 : 4;
6230 Idx += Locs[i].first * 2 + Locs[i].second;
6234 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6237 if (NumLo == 3 || NumHi == 3) {
6238 // Otherwise, we must have three elements from one vector, call it X, and
6239 // one element from the other, call it Y. First, use a shufps to build an
6240 // intermediate vector with the one element from Y and the element from X
6241 // that will be in the same half in the final destination (the indexes don't
6242 // matter). Then, use a shufps to build the final vector, taking the half
6243 // containing the element from Y from the intermediate, and the other half
6246 // Normalize it so the 3 elements come from V1.
6247 CommuteVectorShuffleMask(PermMask, 4);
6251 // Find the element from V2.
6253 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6254 int Val = PermMask[HiIndex];
6261 Mask1[0] = PermMask[HiIndex];
6263 Mask1[2] = PermMask[HiIndex^1];
6265 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6268 Mask1[0] = PermMask[0];
6269 Mask1[1] = PermMask[1];
6270 Mask1[2] = HiIndex & 1 ? 6 : 4;
6271 Mask1[3] = HiIndex & 1 ? 4 : 6;
6272 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6275 Mask1[0] = HiIndex & 1 ? 2 : 0;
6276 Mask1[1] = HiIndex & 1 ? 0 : 2;
6277 Mask1[2] = PermMask[2];
6278 Mask1[3] = PermMask[3];
6283 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6286 // Break it into (shuffle shuffle_hi, shuffle_lo).
6287 int LoMask[] = { -1, -1, -1, -1 };
6288 int HiMask[] = { -1, -1, -1, -1 };
6290 int *MaskPtr = LoMask;
6291 unsigned MaskIdx = 0;
6294 for (unsigned i = 0; i != 4; ++i) {
6301 int Idx = PermMask[i];
6303 Locs[i] = std::make_pair(-1, -1);
6304 } else if (Idx < 4) {
6305 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6306 MaskPtr[LoIdx] = Idx;
6309 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6310 MaskPtr[HiIdx] = Idx;
6315 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6316 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6317 int MaskOps[] = { -1, -1, -1, -1 };
6318 for (unsigned i = 0; i != 4; ++i)
6319 if (Locs[i].first != -1)
6320 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6321 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6324 static bool MayFoldVectorLoad(SDValue V) {
6325 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6326 V = V.getOperand(0);
6327 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6328 V = V.getOperand(0);
6329 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6330 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6331 // BUILD_VECTOR (load), undef
6332 V = V.getOperand(0);
6338 // FIXME: the version above should always be used. Since there's
6339 // a bug where several vector shuffles can't be folded because the
6340 // DAG is not updated during lowering and a node claims to have two
6341 // uses while it only has one, use this version, and let isel match
6342 // another instruction if the load really happens to have more than
6343 // one use. Remove this version after this bug get fixed.
6344 // rdar://8434668, PR8156
6345 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6346 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6347 V = V.getOperand(0);
6348 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6349 V = V.getOperand(0);
6350 if (ISD::isNormalLoad(V.getNode()))
6356 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6357 EVT VT = Op.getValueType();
6359 // Canonizalize to v2f64.
6360 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6361 return DAG.getNode(ISD::BITCAST, dl, VT,
6362 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6367 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6369 SDValue V1 = Op.getOperand(0);
6370 SDValue V2 = Op.getOperand(1);
6371 EVT VT = Op.getValueType();
6373 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6375 if (HasSSE2 && VT == MVT::v2f64)
6376 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6378 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6379 return DAG.getNode(ISD::BITCAST, dl, VT,
6380 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6381 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6382 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6386 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6387 SDValue V1 = Op.getOperand(0);
6388 SDValue V2 = Op.getOperand(1);
6389 EVT VT = Op.getValueType();
6391 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6392 "unsupported shuffle type");
6394 if (V2.getOpcode() == ISD::UNDEF)
6398 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6402 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6403 SDValue V1 = Op.getOperand(0);
6404 SDValue V2 = Op.getOperand(1);
6405 EVT VT = Op.getValueType();
6406 unsigned NumElems = VT.getVectorNumElements();
6408 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6409 // operand of these instructions is only memory, so check if there's a
6410 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6412 bool CanFoldLoad = false;
6414 // Trivial case, when V2 comes from a load.
6415 if (MayFoldVectorLoad(V2))
6418 // When V1 is a load, it can be folded later into a store in isel, example:
6419 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6421 // (MOVLPSmr addr:$src1, VR128:$src2)
6422 // So, recognize this potential and also use MOVLPS or MOVLPD
6423 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6426 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6428 if (HasSSE2 && NumElems == 2)
6429 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6432 // If we don't care about the second element, proceed to use movss.
6433 if (SVOp->getMaskElt(1) != -1)
6434 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6437 // movl and movlp will both match v2i64, but v2i64 is never matched by
6438 // movl earlier because we make it strict to avoid messing with the movlp load
6439 // folding logic (see the code above getMOVLP call). Match it here then,
6440 // this is horrible, but will stay like this until we move all shuffle
6441 // matching to x86 specific nodes. Note that for the 1st condition all
6442 // types are matched with movsd.
6444 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6445 // as to remove this logic from here, as much as possible
6446 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6447 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6448 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6451 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6453 // Invert the operand order and use SHUFPS to match it.
6454 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6455 getShuffleSHUFImmediate(SVOp), DAG);
6459 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6460 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6461 EVT VT = Op.getValueType();
6462 DebugLoc dl = Op.getDebugLoc();
6463 SDValue V1 = Op.getOperand(0);
6464 SDValue V2 = Op.getOperand(1);
6466 if (isZeroShuffle(SVOp))
6467 return getZeroVector(VT, Subtarget, DAG, dl);
6469 // Handle splat operations
6470 if (SVOp->isSplat()) {
6471 unsigned NumElem = VT.getVectorNumElements();
6472 int Size = VT.getSizeInBits();
6474 // Use vbroadcast whenever the splat comes from a foldable load
6475 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6476 if (Broadcast.getNode())
6479 // Handle splats by matching through known shuffle masks
6480 if ((Size == 128 && NumElem <= 4) ||
6481 (Size == 256 && NumElem < 8))
6484 // All remaning splats are promoted to target supported vector shuffles.
6485 return PromoteSplat(SVOp, DAG);
6488 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6490 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6491 VT == MVT::v16i16 || VT == MVT::v32i8) {
6492 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6493 if (NewOp.getNode())
6494 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6495 } else if ((VT == MVT::v4i32 ||
6496 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6497 // FIXME: Figure out a cleaner way to do this.
6498 // Try to make use of movq to zero out the top part.
6499 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6500 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6501 if (NewOp.getNode()) {
6502 EVT NewVT = NewOp.getValueType();
6503 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6504 NewVT, true, false))
6505 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6506 DAG, Subtarget, dl);
6508 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6509 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6510 if (NewOp.getNode()) {
6511 EVT NewVT = NewOp.getValueType();
6512 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6513 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6514 DAG, Subtarget, dl);
6522 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6523 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6524 SDValue V1 = Op.getOperand(0);
6525 SDValue V2 = Op.getOperand(1);
6526 EVT VT = Op.getValueType();
6527 DebugLoc dl = Op.getDebugLoc();
6528 unsigned NumElems = VT.getVectorNumElements();
6529 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6530 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6531 bool V1IsSplat = false;
6532 bool V2IsSplat = false;
6533 bool HasSSE2 = Subtarget->hasSSE2();
6534 bool HasAVX = Subtarget->hasAVX();
6535 bool HasAVX2 = Subtarget->hasAVX2();
6536 MachineFunction &MF = DAG.getMachineFunction();
6537 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6539 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6541 if (V1IsUndef && V2IsUndef)
6542 return DAG.getUNDEF(VT);
6544 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6546 // Vector shuffle lowering takes 3 steps:
6548 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6549 // narrowing and commutation of operands should be handled.
6550 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6552 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6553 // so the shuffle can be broken into other shuffles and the legalizer can
6554 // try the lowering again.
6556 // The general idea is that no vector_shuffle operation should be left to
6557 // be matched during isel, all of them must be converted to a target specific
6560 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6561 // narrowing and commutation of operands should be handled. The actual code
6562 // doesn't include all of those, work in progress...
6563 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6564 if (NewOp.getNode())
6567 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6569 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6570 // unpckh_undef). Only use pshufd if speed is more important than size.
6571 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6572 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6573 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6574 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6576 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6577 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6578 return getMOVDDup(Op, dl, V1, DAG);
6580 if (isMOVHLPS_v_undef_Mask(M, VT))
6581 return getMOVHighToLow(Op, dl, DAG);
6583 // Use to match splats
6584 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6585 (VT == MVT::v2f64 || VT == MVT::v2i64))
6586 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6588 if (isPSHUFDMask(M, VT)) {
6589 // The actual implementation will match the mask in the if above and then
6590 // during isel it can match several different instructions, not only pshufd
6591 // as its name says, sad but true, emulate the behavior for now...
6592 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6593 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6595 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6597 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6598 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6600 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6601 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6603 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6607 // Check if this can be converted into a logical shift.
6608 bool isLeft = false;
6611 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6612 if (isShift && ShVal.hasOneUse()) {
6613 // If the shifted value has multiple uses, it may be cheaper to use
6614 // v_set0 + movlhps or movhlps, etc.
6615 EVT EltVT = VT.getVectorElementType();
6616 ShAmt *= EltVT.getSizeInBits();
6617 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6620 if (isMOVLMask(M, VT)) {
6621 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6622 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6623 if (!isMOVLPMask(M, VT)) {
6624 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6625 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6627 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6628 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6632 // FIXME: fold these into legal mask.
6633 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6634 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6636 if (isMOVHLPSMask(M, VT))
6637 return getMOVHighToLow(Op, dl, DAG);
6639 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6640 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6642 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6643 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6645 if (isMOVLPMask(M, VT))
6646 return getMOVLP(Op, dl, DAG, HasSSE2);
6648 if (ShouldXformToMOVHLPS(M, VT) ||
6649 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6650 return CommuteVectorShuffle(SVOp, DAG);
6653 // No better options. Use a vshldq / vsrldq.
6654 EVT EltVT = VT.getVectorElementType();
6655 ShAmt *= EltVT.getSizeInBits();
6656 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6659 bool Commuted = false;
6660 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6661 // 1,1,1,1 -> v8i16 though.
6662 V1IsSplat = isSplatVector(V1.getNode());
6663 V2IsSplat = isSplatVector(V2.getNode());
6665 // Canonicalize the splat or undef, if present, to be on the RHS.
6666 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6667 CommuteVectorShuffleMask(M, NumElems);
6669 std::swap(V1IsSplat, V2IsSplat);
6673 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6674 // Shuffling low element of v1 into undef, just return v1.
6677 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6678 // the instruction selector will not match, so get a canonical MOVL with
6679 // swapped operands to undo the commute.
6680 return getMOVL(DAG, dl, VT, V2, V1);
6683 if (isUNPCKLMask(M, VT, HasAVX2))
6684 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6686 if (isUNPCKHMask(M, VT, HasAVX2))
6687 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6690 // Normalize mask so all entries that point to V2 points to its first
6691 // element then try to match unpck{h|l} again. If match, return a
6692 // new vector_shuffle with the corrected mask.p
6693 SmallVector<int, 8> NewMask(M.begin(), M.end());
6694 NormalizeMask(NewMask, NumElems);
6695 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6696 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6697 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6698 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6702 // Commute is back and try unpck* again.
6703 // FIXME: this seems wrong.
6704 CommuteVectorShuffleMask(M, NumElems);
6706 std::swap(V1IsSplat, V2IsSplat);
6709 if (isUNPCKLMask(M, VT, HasAVX2))
6710 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6712 if (isUNPCKHMask(M, VT, HasAVX2))
6713 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6716 // Normalize the node to match x86 shuffle ops if needed
6717 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6718 return CommuteVectorShuffle(SVOp, DAG);
6720 // The checks below are all present in isShuffleMaskLegal, but they are
6721 // inlined here right now to enable us to directly emit target specific
6722 // nodes, and remove one by one until they don't return Op anymore.
6724 if (isPALIGNRMask(M, VT, Subtarget))
6725 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6726 getShufflePALIGNRImmediate(SVOp),
6729 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6730 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6731 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6732 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6735 if (isPSHUFHWMask(M, VT, HasAVX2))
6736 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6737 getShufflePSHUFHWImmediate(SVOp),
6740 if (isPSHUFLWMask(M, VT, HasAVX2))
6741 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6742 getShufflePSHUFLWImmediate(SVOp),
6745 if (isSHUFPMask(M, VT, HasAVX))
6746 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6747 getShuffleSHUFImmediate(SVOp), DAG);
6749 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6750 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6751 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6752 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6754 //===--------------------------------------------------------------------===//
6755 // Generate target specific nodes for 128 or 256-bit shuffles only
6756 // supported in the AVX instruction set.
6759 // Handle VMOVDDUPY permutations
6760 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6761 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6763 // Handle VPERMILPS/D* permutations
6764 if (isVPERMILPMask(M, VT, HasAVX)) {
6765 if (HasAVX2 && VT == MVT::v8i32)
6766 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6767 getShuffleSHUFImmediate(SVOp), DAG);
6768 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6769 getShuffleSHUFImmediate(SVOp), DAG);
6772 // Handle VPERM2F128/VPERM2I128 permutations
6773 if (isVPERM2X128Mask(M, VT, HasAVX))
6774 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6775 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6777 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6778 if (BlendOp.getNode())
6781 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6782 SmallVector<SDValue, 8> permclMask;
6783 for (unsigned i = 0; i != 8; ++i) {
6784 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6786 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6788 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6789 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6790 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6793 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6794 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6795 getShuffleCLImmediate(SVOp), DAG);
6798 //===--------------------------------------------------------------------===//
6799 // Since no target specific shuffle was selected for this generic one,
6800 // lower it into other known shuffles. FIXME: this isn't true yet, but
6801 // this is the plan.
6804 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6805 if (VT == MVT::v8i16) {
6806 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6807 if (NewOp.getNode())
6811 if (VT == MVT::v16i8) {
6812 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6813 if (NewOp.getNode())
6817 // Handle all 128-bit wide vectors with 4 elements, and match them with
6818 // several different shuffle types.
6819 if (NumElems == 4 && VT.is128BitVector())
6820 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6822 // Handle general 256-bit shuffles
6823 if (VT.is256BitVector())
6824 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6830 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6831 SelectionDAG &DAG) const {
6832 EVT VT = Op.getValueType();
6833 DebugLoc dl = Op.getDebugLoc();
6835 if (!Op.getOperand(0).getValueType().is128BitVector())
6838 if (VT.getSizeInBits() == 8) {
6839 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6840 Op.getOperand(0), Op.getOperand(1));
6841 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6842 DAG.getValueType(VT));
6843 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6846 if (VT.getSizeInBits() == 16) {
6847 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6848 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6850 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6851 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6852 DAG.getNode(ISD::BITCAST, dl,
6856 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6857 Op.getOperand(0), Op.getOperand(1));
6858 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6859 DAG.getValueType(VT));
6860 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6863 if (VT == MVT::f32) {
6864 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6865 // the result back to FR32 register. It's only worth matching if the
6866 // result has a single use which is a store or a bitcast to i32. And in
6867 // the case of a store, it's not worth it if the index is a constant 0,
6868 // because a MOVSSmr can be used instead, which is smaller and faster.
6869 if (!Op.hasOneUse())
6871 SDNode *User = *Op.getNode()->use_begin();
6872 if ((User->getOpcode() != ISD::STORE ||
6873 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6874 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6875 (User->getOpcode() != ISD::BITCAST ||
6876 User->getValueType(0) != MVT::i32))
6878 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6879 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6882 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6885 if (VT == MVT::i32 || VT == MVT::i64) {
6886 // ExtractPS/pextrq works with constant index.
6887 if (isa<ConstantSDNode>(Op.getOperand(1)))
6895 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6896 SelectionDAG &DAG) const {
6897 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6900 SDValue Vec = Op.getOperand(0);
6901 EVT VecVT = Vec.getValueType();
6903 // If this is a 256-bit vector result, first extract the 128-bit vector and
6904 // then extract the element from the 128-bit vector.
6905 if (VecVT.is256BitVector()) {
6906 DebugLoc dl = Op.getNode()->getDebugLoc();
6907 unsigned NumElems = VecVT.getVectorNumElements();
6908 SDValue Idx = Op.getOperand(1);
6909 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6911 // Get the 128-bit vector.
6912 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6914 if (IdxVal >= NumElems/2)
6915 IdxVal -= NumElems/2;
6916 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6917 DAG.getConstant(IdxVal, MVT::i32));
6920 assert(VecVT.is128BitVector() && "Unexpected vector length");
6922 if (Subtarget->hasSSE41()) {
6923 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6928 EVT VT = Op.getValueType();
6929 DebugLoc dl = Op.getDebugLoc();
6930 // TODO: handle v16i8.
6931 if (VT.getSizeInBits() == 16) {
6932 SDValue Vec = Op.getOperand(0);
6933 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6935 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6936 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6937 DAG.getNode(ISD::BITCAST, dl,
6940 // Transform it so it match pextrw which produces a 32-bit result.
6941 EVT EltVT = MVT::i32;
6942 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6943 Op.getOperand(0), Op.getOperand(1));
6944 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6945 DAG.getValueType(VT));
6946 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6949 if (VT.getSizeInBits() == 32) {
6950 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6954 // SHUFPS the element to the lowest double word, then movss.
6955 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6956 EVT VVT = Op.getOperand(0).getValueType();
6957 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6958 DAG.getUNDEF(VVT), Mask);
6959 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6960 DAG.getIntPtrConstant(0));
6963 if (VT.getSizeInBits() == 64) {
6964 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6965 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6966 // to match extract_elt for f64.
6967 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6971 // UNPCKHPD the element to the lowest double word, then movsd.
6972 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6973 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6974 int Mask[2] = { 1, -1 };
6975 EVT VVT = Op.getOperand(0).getValueType();
6976 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6977 DAG.getUNDEF(VVT), Mask);
6978 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6979 DAG.getIntPtrConstant(0));
6986 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6987 SelectionDAG &DAG) const {
6988 EVT VT = Op.getValueType();
6989 EVT EltVT = VT.getVectorElementType();
6990 DebugLoc dl = Op.getDebugLoc();
6992 SDValue N0 = Op.getOperand(0);
6993 SDValue N1 = Op.getOperand(1);
6994 SDValue N2 = Op.getOperand(2);
6996 if (!VT.is128BitVector())
6999 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7000 isa<ConstantSDNode>(N2)) {
7002 if (VT == MVT::v8i16)
7003 Opc = X86ISD::PINSRW;
7004 else if (VT == MVT::v16i8)
7005 Opc = X86ISD::PINSRB;
7007 Opc = X86ISD::PINSRB;
7009 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7011 if (N1.getValueType() != MVT::i32)
7012 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7013 if (N2.getValueType() != MVT::i32)
7014 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7015 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7018 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7019 // Bits [7:6] of the constant are the source select. This will always be
7020 // zero here. The DAG Combiner may combine an extract_elt index into these
7021 // bits. For example (insert (extract, 3), 2) could be matched by putting
7022 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7023 // Bits [5:4] of the constant are the destination select. This is the
7024 // value of the incoming immediate.
7025 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7026 // combine either bitwise AND or insert of float 0.0 to set these bits.
7027 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7028 // Create this as a scalar to vector..
7029 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7030 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7033 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7034 // PINSR* works with constant index.
7041 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7042 EVT VT = Op.getValueType();
7043 EVT EltVT = VT.getVectorElementType();
7045 DebugLoc dl = Op.getDebugLoc();
7046 SDValue N0 = Op.getOperand(0);
7047 SDValue N1 = Op.getOperand(1);
7048 SDValue N2 = Op.getOperand(2);
7050 // If this is a 256-bit vector result, first extract the 128-bit vector,
7051 // insert the element into the extracted half and then place it back.
7052 if (VT.is256BitVector()) {
7053 if (!isa<ConstantSDNode>(N2))
7056 // Get the desired 128-bit vector half.
7057 unsigned NumElems = VT.getVectorNumElements();
7058 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7059 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7061 // Insert the element into the desired half.
7062 bool Upper = IdxVal >= NumElems/2;
7063 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7064 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7066 // Insert the changed part back to the 256-bit vector
7067 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7070 if (Subtarget->hasSSE41())
7071 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7073 if (EltVT == MVT::i8)
7076 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7077 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7078 // as its second argument.
7079 if (N1.getValueType() != MVT::i32)
7080 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7081 if (N2.getValueType() != MVT::i32)
7082 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7083 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7089 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7090 LLVMContext *Context = DAG.getContext();
7091 DebugLoc dl = Op.getDebugLoc();
7092 EVT OpVT = Op.getValueType();
7094 // If this is a 256-bit vector result, first insert into a 128-bit
7095 // vector and then insert into the 256-bit vector.
7096 if (!OpVT.is128BitVector()) {
7097 // Insert into a 128-bit vector.
7098 EVT VT128 = EVT::getVectorVT(*Context,
7099 OpVT.getVectorElementType(),
7100 OpVT.getVectorNumElements() / 2);
7102 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7104 // Insert the 128-bit vector.
7105 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7108 if (OpVT == MVT::v1i64 &&
7109 Op.getOperand(0).getValueType() == MVT::i64)
7110 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7112 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7113 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7114 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7115 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7118 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7119 // a simple subregister reference or explicit instructions to grab
7120 // upper bits of a vector.
7122 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7123 if (Subtarget->hasAVX()) {
7124 DebugLoc dl = Op.getNode()->getDebugLoc();
7125 SDValue Vec = Op.getNode()->getOperand(0);
7126 SDValue Idx = Op.getNode()->getOperand(1);
7128 if (Op.getNode()->getValueType(0).is128BitVector() &&
7129 Vec.getNode()->getValueType(0).is256BitVector() &&
7130 isa<ConstantSDNode>(Idx)) {
7131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7132 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7138 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7139 // simple superregister reference or explicit instructions to insert
7140 // the upper bits of a vector.
7142 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7143 if (Subtarget->hasAVX()) {
7144 DebugLoc dl = Op.getNode()->getDebugLoc();
7145 SDValue Vec = Op.getNode()->getOperand(0);
7146 SDValue SubVec = Op.getNode()->getOperand(1);
7147 SDValue Idx = Op.getNode()->getOperand(2);
7149 if (Op.getNode()->getValueType(0).is256BitVector() &&
7150 SubVec.getNode()->getValueType(0).is128BitVector() &&
7151 isa<ConstantSDNode>(Idx)) {
7152 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7153 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7159 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7160 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7161 // one of the above mentioned nodes. It has to be wrapped because otherwise
7162 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7163 // be used to form addressing mode. These wrapped nodes will be selected
7166 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7167 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7169 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7171 unsigned char OpFlag = 0;
7172 unsigned WrapperKind = X86ISD::Wrapper;
7173 CodeModel::Model M = getTargetMachine().getCodeModel();
7175 if (Subtarget->isPICStyleRIPRel() &&
7176 (M == CodeModel::Small || M == CodeModel::Kernel))
7177 WrapperKind = X86ISD::WrapperRIP;
7178 else if (Subtarget->isPICStyleGOT())
7179 OpFlag = X86II::MO_GOTOFF;
7180 else if (Subtarget->isPICStyleStubPIC())
7181 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7183 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7185 CP->getOffset(), OpFlag);
7186 DebugLoc DL = CP->getDebugLoc();
7187 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7188 // With PIC, the address is actually $g + Offset.
7190 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7191 DAG.getNode(X86ISD::GlobalBaseReg,
7192 DebugLoc(), getPointerTy()),
7199 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7200 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7202 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7204 unsigned char OpFlag = 0;
7205 unsigned WrapperKind = X86ISD::Wrapper;
7206 CodeModel::Model M = getTargetMachine().getCodeModel();
7208 if (Subtarget->isPICStyleRIPRel() &&
7209 (M == CodeModel::Small || M == CodeModel::Kernel))
7210 WrapperKind = X86ISD::WrapperRIP;
7211 else if (Subtarget->isPICStyleGOT())
7212 OpFlag = X86II::MO_GOTOFF;
7213 else if (Subtarget->isPICStyleStubPIC())
7214 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7216 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7218 DebugLoc DL = JT->getDebugLoc();
7219 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7221 // With PIC, the address is actually $g + Offset.
7223 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7224 DAG.getNode(X86ISD::GlobalBaseReg,
7225 DebugLoc(), getPointerTy()),
7232 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7233 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7235 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7237 unsigned char OpFlag = 0;
7238 unsigned WrapperKind = X86ISD::Wrapper;
7239 CodeModel::Model M = getTargetMachine().getCodeModel();
7241 if (Subtarget->isPICStyleRIPRel() &&
7242 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7243 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7244 OpFlag = X86II::MO_GOTPCREL;
7245 WrapperKind = X86ISD::WrapperRIP;
7246 } else if (Subtarget->isPICStyleGOT()) {
7247 OpFlag = X86II::MO_GOT;
7248 } else if (Subtarget->isPICStyleStubPIC()) {
7249 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7250 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7251 OpFlag = X86II::MO_DARWIN_NONLAZY;
7254 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7256 DebugLoc DL = Op.getDebugLoc();
7257 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7260 // With PIC, the address is actually $g + Offset.
7261 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7262 !Subtarget->is64Bit()) {
7263 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7264 DAG.getNode(X86ISD::GlobalBaseReg,
7265 DebugLoc(), getPointerTy()),
7269 // For symbols that require a load from a stub to get the address, emit the
7271 if (isGlobalStubReference(OpFlag))
7272 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7273 MachinePointerInfo::getGOT(), false, false, false, 0);
7279 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7280 // Create the TargetBlockAddressAddress node.
7281 unsigned char OpFlags =
7282 Subtarget->ClassifyBlockAddressReference();
7283 CodeModel::Model M = getTargetMachine().getCodeModel();
7284 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7285 DebugLoc dl = Op.getDebugLoc();
7286 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7287 /*isTarget=*/true, OpFlags);
7289 if (Subtarget->isPICStyleRIPRel() &&
7290 (M == CodeModel::Small || M == CodeModel::Kernel))
7291 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7293 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7295 // With PIC, the address is actually $g + Offset.
7296 if (isGlobalRelativeToPICBase(OpFlags)) {
7297 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7298 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7306 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7308 SelectionDAG &DAG) const {
7309 // Create the TargetGlobalAddress node, folding in the constant
7310 // offset if it is legal.
7311 unsigned char OpFlags =
7312 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7313 CodeModel::Model M = getTargetMachine().getCodeModel();
7315 if (OpFlags == X86II::MO_NO_FLAG &&
7316 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7317 // A direct static reference to a global.
7318 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7321 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7324 if (Subtarget->isPICStyleRIPRel() &&
7325 (M == CodeModel::Small || M == CodeModel::Kernel))
7326 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7328 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7330 // With PIC, the address is actually $g + Offset.
7331 if (isGlobalRelativeToPICBase(OpFlags)) {
7332 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7333 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7337 // For globals that require a load from a stub to get the address, emit the
7339 if (isGlobalStubReference(OpFlags))
7340 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7341 MachinePointerInfo::getGOT(), false, false, false, 0);
7343 // If there was a non-zero offset that we didn't fold, create an explicit
7346 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7347 DAG.getConstant(Offset, getPointerTy()));
7353 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7354 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7355 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7356 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7360 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7361 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7362 unsigned char OperandFlags, bool LocalDynamic = false) {
7363 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7364 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7365 DebugLoc dl = GA->getDebugLoc();
7366 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7367 GA->getValueType(0),
7371 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7375 SDValue Ops[] = { Chain, TGA, *InFlag };
7376 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7378 SDValue Ops[] = { Chain, TGA };
7379 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7382 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7383 MFI->setAdjustsStack(true);
7385 SDValue Flag = Chain.getValue(1);
7386 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7389 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7391 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7394 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7395 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7396 DAG.getNode(X86ISD::GlobalBaseReg,
7397 DebugLoc(), PtrVT), InFlag);
7398 InFlag = Chain.getValue(1);
7400 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7403 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7405 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7407 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7408 X86::RAX, X86II::MO_TLSGD);
7411 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7415 DebugLoc dl = GA->getDebugLoc();
7417 // Get the start address of the TLS block for this module.
7418 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7419 .getInfo<X86MachineFunctionInfo>();
7420 MFI->incNumLocalDynamicTLSAccesses();
7424 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7425 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7428 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7429 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7430 InFlag = Chain.getValue(1);
7431 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7432 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7435 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7439 unsigned char OperandFlags = X86II::MO_DTPOFF;
7440 unsigned WrapperKind = X86ISD::Wrapper;
7441 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7442 GA->getValueType(0),
7443 GA->getOffset(), OperandFlags);
7444 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7446 // Add x@dtpoff with the base.
7447 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7450 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7451 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7452 const EVT PtrVT, TLSModel::Model model,
7453 bool is64Bit, bool isPIC) {
7454 DebugLoc dl = GA->getDebugLoc();
7456 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7457 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7458 is64Bit ? 257 : 256));
7460 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7461 DAG.getIntPtrConstant(0),
7462 MachinePointerInfo(Ptr),
7463 false, false, false, 0);
7465 unsigned char OperandFlags = 0;
7466 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7468 unsigned WrapperKind = X86ISD::Wrapper;
7469 if (model == TLSModel::LocalExec) {
7470 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7471 } else if (model == TLSModel::InitialExec) {
7473 OperandFlags = X86II::MO_GOTTPOFF;
7474 WrapperKind = X86ISD::WrapperRIP;
7476 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7479 llvm_unreachable("Unexpected model");
7482 // emit "addl x@ntpoff,%eax" (local exec)
7483 // or "addl x@indntpoff,%eax" (initial exec)
7484 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7485 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7486 GA->getValueType(0),
7487 GA->getOffset(), OperandFlags);
7488 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7490 if (model == TLSModel::InitialExec) {
7491 if (isPIC && !is64Bit) {
7492 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7493 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7497 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7498 MachinePointerInfo::getGOT(), false, false, false,
7502 // The address of the thread local variable is the add of the thread
7503 // pointer with the offset of the variable.
7504 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7508 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7510 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7511 const GlobalValue *GV = GA->getGlobal();
7513 if (Subtarget->isTargetELF()) {
7514 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7517 case TLSModel::GeneralDynamic:
7518 if (Subtarget->is64Bit())
7519 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7520 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7521 case TLSModel::LocalDynamic:
7522 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7523 Subtarget->is64Bit());
7524 case TLSModel::InitialExec:
7525 case TLSModel::LocalExec:
7526 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7527 Subtarget->is64Bit(),
7528 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7530 llvm_unreachable("Unknown TLS model.");
7533 if (Subtarget->isTargetDarwin()) {
7534 // Darwin only has one model of TLS. Lower to that.
7535 unsigned char OpFlag = 0;
7536 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7537 X86ISD::WrapperRIP : X86ISD::Wrapper;
7539 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7541 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7542 !Subtarget->is64Bit();
7544 OpFlag = X86II::MO_TLVP_PIC_BASE;
7546 OpFlag = X86II::MO_TLVP;
7547 DebugLoc DL = Op.getDebugLoc();
7548 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7549 GA->getValueType(0),
7550 GA->getOffset(), OpFlag);
7551 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7553 // With PIC32, the address is actually $g + Offset.
7555 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7556 DAG.getNode(X86ISD::GlobalBaseReg,
7557 DebugLoc(), getPointerTy()),
7560 // Lowering the machine isd will make sure everything is in the right
7562 SDValue Chain = DAG.getEntryNode();
7563 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7564 SDValue Args[] = { Chain, Offset };
7565 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7567 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7568 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7569 MFI->setAdjustsStack(true);
7571 // And our return value (tls address) is in the standard call return value
7573 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7574 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7578 if (Subtarget->isTargetWindows()) {
7579 // Just use the implicit TLS architecture
7580 // Need to generate someting similar to:
7581 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7583 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7584 // mov rcx, qword [rdx+rcx*8]
7585 // mov eax, .tls$:tlsvar
7586 // [rax+rcx] contains the address
7587 // Windows 64bit: gs:0x58
7588 // Windows 32bit: fs:__tls_array
7590 // If GV is an alias then use the aliasee for determining
7591 // thread-localness.
7592 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7593 GV = GA->resolveAliasedGlobal(false);
7594 DebugLoc dl = GA->getDebugLoc();
7595 SDValue Chain = DAG.getEntryNode();
7597 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7598 // %gs:0x58 (64-bit).
7599 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7600 ? Type::getInt8PtrTy(*DAG.getContext(),
7602 : Type::getInt32PtrTy(*DAG.getContext(),
7605 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7606 Subtarget->is64Bit()
7607 ? DAG.getIntPtrConstant(0x58)
7608 : DAG.getExternalSymbol("_tls_array",
7610 MachinePointerInfo(Ptr),
7611 false, false, false, 0);
7613 // Load the _tls_index variable
7614 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7615 if (Subtarget->is64Bit())
7616 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7617 IDX, MachinePointerInfo(), MVT::i32,
7620 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7621 false, false, false, 0);
7623 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7625 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7627 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7628 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7629 false, false, false, 0);
7631 // Get the offset of start of .tls section
7632 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7633 GA->getValueType(0),
7634 GA->getOffset(), X86II::MO_SECREL);
7635 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7637 // The address of the thread local variable is the add of the thread
7638 // pointer with the offset of the variable.
7639 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7642 llvm_unreachable("TLS not implemented for this target.");
7646 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7647 /// and take a 2 x i32 value to shift plus a shift amount.
7648 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7649 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7650 EVT VT = Op.getValueType();
7651 unsigned VTBits = VT.getSizeInBits();
7652 DebugLoc dl = Op.getDebugLoc();
7653 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7654 SDValue ShOpLo = Op.getOperand(0);
7655 SDValue ShOpHi = Op.getOperand(1);
7656 SDValue ShAmt = Op.getOperand(2);
7657 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7658 DAG.getConstant(VTBits - 1, MVT::i8))
7659 : DAG.getConstant(0, VT);
7662 if (Op.getOpcode() == ISD::SHL_PARTS) {
7663 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7664 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7666 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7667 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7670 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7671 DAG.getConstant(VTBits, MVT::i8));
7672 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7673 AndNode, DAG.getConstant(0, MVT::i8));
7676 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7677 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7678 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7680 if (Op.getOpcode() == ISD::SHL_PARTS) {
7681 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7682 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7684 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7685 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7688 SDValue Ops[2] = { Lo, Hi };
7689 return DAG.getMergeValues(Ops, 2, dl);
7692 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7693 SelectionDAG &DAG) const {
7694 EVT SrcVT = Op.getOperand(0).getValueType();
7696 if (SrcVT.isVector())
7699 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7700 "Unknown SINT_TO_FP to lower!");
7702 // These are really Legal; return the operand so the caller accepts it as
7704 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7706 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7707 Subtarget->is64Bit()) {
7711 DebugLoc dl = Op.getDebugLoc();
7712 unsigned Size = SrcVT.getSizeInBits()/8;
7713 MachineFunction &MF = DAG.getMachineFunction();
7714 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7715 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7716 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7718 MachinePointerInfo::getFixedStack(SSFI),
7720 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7723 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7725 SelectionDAG &DAG) const {
7727 DebugLoc DL = Op.getDebugLoc();
7729 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7731 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7733 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7735 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7737 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7738 MachineMemOperand *MMO;
7740 int SSFI = FI->getIndex();
7742 DAG.getMachineFunction()
7743 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7744 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7746 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7747 StackSlot = StackSlot.getOperand(1);
7749 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7750 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7752 Tys, Ops, array_lengthof(Ops),
7756 Chain = Result.getValue(1);
7757 SDValue InFlag = Result.getValue(2);
7759 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7760 // shouldn't be necessary except that RFP cannot be live across
7761 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7762 MachineFunction &MF = DAG.getMachineFunction();
7763 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7764 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7765 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7766 Tys = DAG.getVTList(MVT::Other);
7768 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7770 MachineMemOperand *MMO =
7771 DAG.getMachineFunction()
7772 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7773 MachineMemOperand::MOStore, SSFISize, SSFISize);
7775 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7776 Ops, array_lengthof(Ops),
7777 Op.getValueType(), MMO);
7778 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7779 MachinePointerInfo::getFixedStack(SSFI),
7780 false, false, false, 0);
7786 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7787 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7788 SelectionDAG &DAG) const {
7789 // This algorithm is not obvious. Here it is what we're trying to output:
7792 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7793 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7797 pshufd $0x4e, %xmm0, %xmm1
7802 DebugLoc dl = Op.getDebugLoc();
7803 LLVMContext *Context = DAG.getContext();
7805 // Build some magic constants.
7806 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7807 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7808 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7810 SmallVector<Constant*,2> CV1;
7812 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7814 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7815 Constant *C1 = ConstantVector::get(CV1);
7816 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7818 // Load the 64-bit value into an XMM register.
7819 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7821 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7822 MachinePointerInfo::getConstantPool(),
7823 false, false, false, 16);
7824 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7825 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7828 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7829 MachinePointerInfo::getConstantPool(),
7830 false, false, false, 16);
7831 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7832 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7835 if (Subtarget->hasSSE3()) {
7836 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7837 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7839 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7840 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7842 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7843 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7847 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7848 DAG.getIntPtrConstant(0));
7851 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7852 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7853 SelectionDAG &DAG) const {
7854 DebugLoc dl = Op.getDebugLoc();
7855 // FP constant to bias correct the final result.
7856 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7859 // Load the 32-bit value into an XMM register.
7860 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7863 // Zero out the upper parts of the register.
7864 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7866 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7867 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7868 DAG.getIntPtrConstant(0));
7870 // Or the load with the bias.
7871 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7872 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7873 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7875 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7876 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7877 MVT::v2f64, Bias)));
7878 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7879 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7880 DAG.getIntPtrConstant(0));
7882 // Subtract the bias.
7883 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7885 // Handle final rounding.
7886 EVT DestVT = Op.getValueType();
7888 if (DestVT.bitsLT(MVT::f64))
7889 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7890 DAG.getIntPtrConstant(0));
7891 if (DestVT.bitsGT(MVT::f64))
7892 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7894 // Handle final rounding.
7898 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7899 SelectionDAG &DAG) const {
7900 SDValue N0 = Op.getOperand(0);
7901 DebugLoc dl = Op.getDebugLoc();
7903 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7904 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7905 // the optimization here.
7906 if (DAG.SignBitIsZero(N0))
7907 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7909 EVT SrcVT = N0.getValueType();
7910 EVT DstVT = Op.getValueType();
7911 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7912 return LowerUINT_TO_FP_i64(Op, DAG);
7913 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7914 return LowerUINT_TO_FP_i32(Op, DAG);
7915 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7918 // Make a 64-bit buffer, and use it to build an FILD.
7919 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7920 if (SrcVT == MVT::i32) {
7921 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7922 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7923 getPointerTy(), StackSlot, WordOff);
7924 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7925 StackSlot, MachinePointerInfo(),
7927 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7928 OffsetSlot, MachinePointerInfo(),
7930 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7934 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7935 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7936 StackSlot, MachinePointerInfo(),
7938 // For i64 source, we need to add the appropriate power of 2 if the input
7939 // was negative. This is the same as the optimization in
7940 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7941 // we must be careful to do the computation in x87 extended precision, not
7942 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7943 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7944 MachineMemOperand *MMO =
7945 DAG.getMachineFunction()
7946 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7947 MachineMemOperand::MOLoad, 8, 8);
7949 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7950 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7951 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7954 APInt FF(32, 0x5F800000ULL);
7956 // Check whether the sign bit is set.
7957 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7958 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7961 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7962 SDValue FudgePtr = DAG.getConstantPool(
7963 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7966 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7967 SDValue Zero = DAG.getIntPtrConstant(0);
7968 SDValue Four = DAG.getIntPtrConstant(4);
7969 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7971 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7973 // Load the value out, extending it from f32 to f80.
7974 // FIXME: Avoid the extend by constructing the right constant pool?
7975 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7976 FudgePtr, MachinePointerInfo::getConstantPool(),
7977 MVT::f32, false, false, 4);
7978 // Extend everything to 80 bits to force it to be done on x87.
7979 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7980 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7983 std::pair<SDValue,SDValue> X86TargetLowering::
7984 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7985 DebugLoc DL = Op.getDebugLoc();
7987 EVT DstTy = Op.getValueType();
7989 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7990 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7994 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7995 DstTy.getSimpleVT() >= MVT::i16 &&
7996 "Unknown FP_TO_INT to lower!");
7998 // These are really Legal.
7999 if (DstTy == MVT::i32 &&
8000 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8001 return std::make_pair(SDValue(), SDValue());
8002 if (Subtarget->is64Bit() &&
8003 DstTy == MVT::i64 &&
8004 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8005 return std::make_pair(SDValue(), SDValue());
8007 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8008 // stack slot, or into the FTOL runtime function.
8009 MachineFunction &MF = DAG.getMachineFunction();
8010 unsigned MemSize = DstTy.getSizeInBits()/8;
8011 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8012 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8015 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8016 Opc = X86ISD::WIN_FTOL;
8018 switch (DstTy.getSimpleVT().SimpleTy) {
8019 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8020 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8021 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8022 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8025 SDValue Chain = DAG.getEntryNode();
8026 SDValue Value = Op.getOperand(0);
8027 EVT TheVT = Op.getOperand(0).getValueType();
8028 // FIXME This causes a redundant load/store if the SSE-class value is already
8029 // in memory, such as if it is on the callstack.
8030 if (isScalarFPTypeInSSEReg(TheVT)) {
8031 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8032 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8033 MachinePointerInfo::getFixedStack(SSFI),
8035 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8037 Chain, StackSlot, DAG.getValueType(TheVT)
8040 MachineMemOperand *MMO =
8041 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8042 MachineMemOperand::MOLoad, MemSize, MemSize);
8043 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8045 Chain = Value.getValue(1);
8046 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8047 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8050 MachineMemOperand *MMO =
8051 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8052 MachineMemOperand::MOStore, MemSize, MemSize);
8054 if (Opc != X86ISD::WIN_FTOL) {
8055 // Build the FP_TO_INT*_IN_MEM
8056 SDValue Ops[] = { Chain, Value, StackSlot };
8057 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8058 Ops, 3, DstTy, MMO);
8059 return std::make_pair(FIST, StackSlot);
8061 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8062 DAG.getVTList(MVT::Other, MVT::Glue),
8064 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8065 MVT::i32, ftol.getValue(1));
8066 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8067 MVT::i32, eax.getValue(2));
8068 SDValue Ops[] = { eax, edx };
8069 SDValue pair = IsReplace
8070 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8071 : DAG.getMergeValues(Ops, 2, DL);
8072 return std::make_pair(pair, SDValue());
8076 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8077 SelectionDAG &DAG) const {
8078 if (Op.getValueType().isVector())
8081 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8082 /*IsSigned=*/ true, /*IsReplace=*/ false);
8083 SDValue FIST = Vals.first, StackSlot = Vals.second;
8084 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8085 if (FIST.getNode() == 0) return Op;
8087 if (StackSlot.getNode())
8089 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8090 FIST, StackSlot, MachinePointerInfo(),
8091 false, false, false, 0);
8093 // The node is the result.
8097 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8098 SelectionDAG &DAG) const {
8099 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8100 /*IsSigned=*/ false, /*IsReplace=*/ false);
8101 SDValue FIST = Vals.first, StackSlot = Vals.second;
8102 assert(FIST.getNode() && "Unexpected failure");
8104 if (StackSlot.getNode())
8106 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8107 FIST, StackSlot, MachinePointerInfo(),
8108 false, false, false, 0);
8110 // The node is the result.
8114 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8115 SelectionDAG &DAG) const {
8116 LLVMContext *Context = DAG.getContext();
8117 DebugLoc dl = Op.getDebugLoc();
8118 EVT VT = Op.getValueType();
8121 EltVT = VT.getVectorElementType();
8123 if (EltVT == MVT::f64) {
8124 C = ConstantVector::getSplat(2,
8125 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8127 C = ConstantVector::getSplat(4,
8128 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8130 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8131 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8132 MachinePointerInfo::getConstantPool(),
8133 false, false, false, 16);
8134 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8137 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8138 LLVMContext *Context = DAG.getContext();
8139 DebugLoc dl = Op.getDebugLoc();
8140 EVT VT = Op.getValueType();
8142 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8143 if (VT.isVector()) {
8144 EltVT = VT.getVectorElementType();
8145 NumElts = VT.getVectorNumElements();
8148 if (EltVT == MVT::f64)
8149 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8151 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8152 C = ConstantVector::getSplat(NumElts, C);
8153 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8154 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8155 MachinePointerInfo::getConstantPool(),
8156 false, false, false, 16);
8157 if (VT.isVector()) {
8158 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8159 return DAG.getNode(ISD::BITCAST, dl, VT,
8160 DAG.getNode(ISD::XOR, dl, XORVT,
8161 DAG.getNode(ISD::BITCAST, dl, XORVT,
8163 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8166 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8169 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8170 LLVMContext *Context = DAG.getContext();
8171 SDValue Op0 = Op.getOperand(0);
8172 SDValue Op1 = Op.getOperand(1);
8173 DebugLoc dl = Op.getDebugLoc();
8174 EVT VT = Op.getValueType();
8175 EVT SrcVT = Op1.getValueType();
8177 // If second operand is smaller, extend it first.
8178 if (SrcVT.bitsLT(VT)) {
8179 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8182 // And if it is bigger, shrink it first.
8183 if (SrcVT.bitsGT(VT)) {
8184 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8188 // At this point the operands and the result should have the same
8189 // type, and that won't be f80 since that is not custom lowered.
8191 // First get the sign bit of second operand.
8192 SmallVector<Constant*,4> CV;
8193 if (SrcVT == MVT::f64) {
8194 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8195 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8197 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8198 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8199 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8200 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8202 Constant *C = ConstantVector::get(CV);
8203 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8204 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8205 MachinePointerInfo::getConstantPool(),
8206 false, false, false, 16);
8207 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8209 // Shift sign bit right or left if the two operands have different types.
8210 if (SrcVT.bitsGT(VT)) {
8211 // Op0 is MVT::f32, Op1 is MVT::f64.
8212 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8213 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8214 DAG.getConstant(32, MVT::i32));
8215 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8216 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8217 DAG.getIntPtrConstant(0));
8220 // Clear first operand sign bit.
8222 if (VT == MVT::f64) {
8223 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8224 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8226 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8227 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8228 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8229 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8231 C = ConstantVector::get(CV);
8232 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8233 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8234 MachinePointerInfo::getConstantPool(),
8235 false, false, false, 16);
8236 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8238 // Or the value with the sign bit.
8239 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8242 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8243 SDValue N0 = Op.getOperand(0);
8244 DebugLoc dl = Op.getDebugLoc();
8245 EVT VT = Op.getValueType();
8247 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8248 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8249 DAG.getConstant(1, VT));
8250 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8253 /// Emit nodes that will be selected as "test Op0,Op0", or something
8255 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8256 SelectionDAG &DAG) const {
8257 DebugLoc dl = Op.getDebugLoc();
8259 // CF and OF aren't always set the way we want. Determine which
8260 // of these we need.
8261 bool NeedCF = false;
8262 bool NeedOF = false;
8265 case X86::COND_A: case X86::COND_AE:
8266 case X86::COND_B: case X86::COND_BE:
8269 case X86::COND_G: case X86::COND_GE:
8270 case X86::COND_L: case X86::COND_LE:
8271 case X86::COND_O: case X86::COND_NO:
8276 // See if we can use the EFLAGS value from the operand instead of
8277 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8278 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8279 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8280 // Emit a CMP with 0, which is the TEST pattern.
8281 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8282 DAG.getConstant(0, Op.getValueType()));
8284 unsigned Opcode = 0;
8285 unsigned NumOperands = 0;
8287 // Truncate operations may prevent the merge of the SETCC instruction
8288 // and the arithmetic intruction before it. Attempt to truncate the operands
8289 // of the arithmetic instruction and use a reduced bit-width instruction.
8290 bool NeedTruncation = false;
8291 unsigned InOpcode = Op.getNode()->getOpcode();
8292 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8293 NeedTruncation = true;
8294 InOpcode = Op->getOperand(0)->getOpcode();
8299 // Due to an isel shortcoming, be conservative if this add is likely to be
8300 // selected as part of a load-modify-store instruction. When the root node
8301 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8302 // uses of other nodes in the match, such as the ADD in this case. This
8303 // leads to the ADD being left around and reselected, with the result being
8304 // two adds in the output. Alas, even if none our users are stores, that
8305 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8306 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8307 // climbing the DAG back to the root, and it doesn't seem to be worth the
8309 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8310 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8311 if (UI->getOpcode() != ISD::CopyToReg &&
8312 UI->getOpcode() != ISD::SETCC &&
8313 UI->getOpcode() != ISD::STORE)
8316 if (ConstantSDNode *C =
8317 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8318 // An add of one will be selected as an INC.
8319 if (C->getAPIntValue() == 1) {
8320 Opcode = X86ISD::INC;
8325 // An add of negative one (subtract of one) will be selected as a DEC.
8326 if (C->getAPIntValue().isAllOnesValue()) {
8327 Opcode = X86ISD::DEC;
8333 // Otherwise use a regular EFLAGS-setting add.
8334 Opcode = X86ISD::ADD;
8338 // If the primary and result isn't used, don't bother using X86ISD::AND,
8339 // because a TEST instruction will be better.
8340 bool NonFlagUse = false;
8341 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8342 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8344 unsigned UOpNo = UI.getOperandNo();
8345 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8346 // Look pass truncate.
8347 UOpNo = User->use_begin().getOperandNo();
8348 User = *User->use_begin();
8351 if (User->getOpcode() != ISD::BRCOND &&
8352 User->getOpcode() != ISD::SETCC &&
8353 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8366 // Due to the ISEL shortcoming noted above, be conservative if this op is
8367 // likely to be selected as part of a load-modify-store instruction.
8368 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8369 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8370 if (UI->getOpcode() == ISD::STORE)
8373 // Otherwise use a regular EFLAGS-setting instruction.
8375 default: llvm_unreachable("unexpected operator!");
8376 case ISD::SUB: Opcode = X86ISD::SUB; break;
8377 case ISD::OR: Opcode = X86ISD::OR; break;
8378 case ISD::XOR: Opcode = X86ISD::XOR; break;
8379 case ISD::AND: Opcode = X86ISD::AND; break;
8391 return SDValue(Op.getNode(), 1);
8397 if (NeedTruncation) {
8398 SDValue WideVal = Op->getOperand(0);
8399 EVT VT = Op.getValueType();
8400 EVT WideVT = WideVal.getValueType();
8401 unsigned ConvertedOp = 0;
8403 // Use a target machine opcode to prevent further DAGCombine
8404 // optimizations that may separate the arithmetic operations from the
8406 switch (WideVal.getOpcode()) {
8408 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
8409 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
8410 case ISD::AND: ConvertedOp = X86ISD::AND; break;
8411 case ISD::OR: ConvertedOp = X86ISD::OR; break;
8412 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
8415 if (ConvertedOp && WideVal.hasOneUse()) {
8416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8417 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
8418 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
8419 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
8420 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
8426 // Emit a CMP with 0, which is the TEST pattern.
8427 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8428 DAG.getConstant(0, Op.getValueType()));
8430 if (Opcode == X86ISD::CMP) {
8431 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8433 // We can't replace usage of SUB with CMP.
8434 // The SUB node will be removed later because there is no use of it.
8435 return SDValue(New.getNode(), 0);
8438 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8439 SmallVector<SDValue, 4> Ops;
8440 for (unsigned i = 0; i != NumOperands; ++i)
8441 Ops.push_back(Op.getOperand(i));
8443 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8444 DAG.ReplaceAllUsesWith(Op, New);
8445 return SDValue(New.getNode(), 1);
8448 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8450 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8451 SelectionDAG &DAG) const {
8452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8453 if (C->getAPIntValue() == 0)
8454 return EmitTest(Op0, X86CC, DAG);
8456 DebugLoc dl = Op0.getDebugLoc();
8457 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
8458 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
8459 // Use SUB instead of CMP to enable CSE between SUB and CMP.
8460 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
8461 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
8463 return SDValue(Sub.getNode(), 1);
8465 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8468 /// Convert a comparison if required by the subtarget.
8469 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8470 SelectionDAG &DAG) const {
8471 // If the subtarget does not support the FUCOMI instruction, floating-point
8472 // comparisons have to be converted.
8473 if (Subtarget->hasCMov() ||
8474 Cmp.getOpcode() != X86ISD::CMP ||
8475 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8476 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8479 // The instruction selector will select an FUCOM instruction instead of
8480 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8481 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8482 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8483 DebugLoc dl = Cmp.getDebugLoc();
8484 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8485 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8486 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8487 DAG.getConstant(8, MVT::i8));
8488 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8489 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8492 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8493 /// if it's possible.
8494 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8495 DebugLoc dl, SelectionDAG &DAG) const {
8496 SDValue Op0 = And.getOperand(0);
8497 SDValue Op1 = And.getOperand(1);
8498 if (Op0.getOpcode() == ISD::TRUNCATE)
8499 Op0 = Op0.getOperand(0);
8500 if (Op1.getOpcode() == ISD::TRUNCATE)
8501 Op1 = Op1.getOperand(0);
8504 if (Op1.getOpcode() == ISD::SHL)
8505 std::swap(Op0, Op1);
8506 if (Op0.getOpcode() == ISD::SHL) {
8507 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8508 if (And00C->getZExtValue() == 1) {
8509 // If we looked past a truncate, check that it's only truncating away
8511 unsigned BitWidth = Op0.getValueSizeInBits();
8512 unsigned AndBitWidth = And.getValueSizeInBits();
8513 if (BitWidth > AndBitWidth) {
8515 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8516 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8520 RHS = Op0.getOperand(1);
8522 } else if (Op1.getOpcode() == ISD::Constant) {
8523 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8524 uint64_t AndRHSVal = AndRHS->getZExtValue();
8525 SDValue AndLHS = Op0;
8527 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8528 LHS = AndLHS.getOperand(0);
8529 RHS = AndLHS.getOperand(1);
8532 // Use BT if the immediate can't be encoded in a TEST instruction.
8533 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8535 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8539 if (LHS.getNode()) {
8540 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8541 // instruction. Since the shift amount is in-range-or-undefined, we know
8542 // that doing a bittest on the i32 value is ok. We extend to i32 because
8543 // the encoding for the i16 version is larger than the i32 version.
8544 // Also promote i16 to i32 for performance / code size reason.
8545 if (LHS.getValueType() == MVT::i8 ||
8546 LHS.getValueType() == MVT::i16)
8547 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8549 // If the operand types disagree, extend the shift amount to match. Since
8550 // BT ignores high bits (like shifts) we can use anyextend.
8551 if (LHS.getValueType() != RHS.getValueType())
8552 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8554 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8555 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8556 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8557 DAG.getConstant(Cond, MVT::i8), BT);
8563 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8565 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8567 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8568 SDValue Op0 = Op.getOperand(0);
8569 SDValue Op1 = Op.getOperand(1);
8570 DebugLoc dl = Op.getDebugLoc();
8571 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8573 // Optimize to BT if possible.
8574 // Lower (X & (1 << N)) == 0 to BT(X, N).
8575 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8576 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8577 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8578 Op1.getOpcode() == ISD::Constant &&
8579 cast<ConstantSDNode>(Op1)->isNullValue() &&
8580 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8581 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8582 if (NewSetCC.getNode())
8586 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8588 if (Op1.getOpcode() == ISD::Constant &&
8589 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8590 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8591 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8593 // If the input is a setcc, then reuse the input setcc or use a new one with
8594 // the inverted condition.
8595 if (Op0.getOpcode() == X86ISD::SETCC) {
8596 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8597 bool Invert = (CC == ISD::SETNE) ^
8598 cast<ConstantSDNode>(Op1)->isNullValue();
8599 if (!Invert) return Op0;
8601 CCode = X86::GetOppositeBranchCondition(CCode);
8602 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8603 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8607 bool isFP = Op1.getValueType().isFloatingPoint();
8608 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8609 if (X86CC == X86::COND_INVALID)
8612 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8613 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8614 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8615 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8618 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8619 // ones, and then concatenate the result back.
8620 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8621 EVT VT = Op.getValueType();
8623 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
8624 "Unsupported value type for operation");
8626 unsigned NumElems = VT.getVectorNumElements();
8627 DebugLoc dl = Op.getDebugLoc();
8628 SDValue CC = Op.getOperand(2);
8630 // Extract the LHS vectors
8631 SDValue LHS = Op.getOperand(0);
8632 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8633 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8635 // Extract the RHS vectors
8636 SDValue RHS = Op.getOperand(1);
8637 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8638 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8640 // Issue the operation on the smaller types and concatenate the result back
8641 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8642 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8644 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8645 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8649 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8651 SDValue Op0 = Op.getOperand(0);
8652 SDValue Op1 = Op.getOperand(1);
8653 SDValue CC = Op.getOperand(2);
8654 EVT VT = Op.getValueType();
8655 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8656 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8657 DebugLoc dl = Op.getDebugLoc();
8661 EVT EltVT = Op0.getValueType().getVectorElementType();
8662 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8668 // SSE Condition code mapping:
8677 switch (SetCCOpcode) {
8678 default: llvm_unreachable("Unexpected SETCC condition");
8680 case ISD::SETEQ: SSECC = 0; break;
8682 case ISD::SETGT: Swap = true; // Fallthrough
8684 case ISD::SETOLT: SSECC = 1; break;
8686 case ISD::SETGE: Swap = true; // Fallthrough
8688 case ISD::SETOLE: SSECC = 2; break;
8689 case ISD::SETUO: SSECC = 3; break;
8691 case ISD::SETNE: SSECC = 4; break;
8692 case ISD::SETULE: Swap = true; // Fallthrough
8693 case ISD::SETUGE: SSECC = 5; break;
8694 case ISD::SETULT: Swap = true; // Fallthrough
8695 case ISD::SETUGT: SSECC = 6; break;
8696 case ISD::SETO: SSECC = 7; break;
8698 case ISD::SETONE: SSECC = 8; break;
8701 std::swap(Op0, Op1);
8703 // In the two special cases we can't handle, emit two comparisons.
8706 unsigned CombineOpc;
8707 if (SetCCOpcode == ISD::SETUEQ) {
8708 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
8710 assert(SetCCOpcode == ISD::SETONE);
8711 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
8714 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8715 DAG.getConstant(CC0, MVT::i8));
8716 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8717 DAG.getConstant(CC1, MVT::i8));
8718 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
8720 // Handle all other FP comparisons here.
8721 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8722 DAG.getConstant(SSECC, MVT::i8));
8725 // Break 256-bit integer vector compare into smaller ones.
8726 if (VT.is256BitVector() && !Subtarget->hasAVX2())
8727 return Lower256IntVSETCC(Op, DAG);
8729 // We are handling one of the integer comparisons here. Since SSE only has
8730 // GT and EQ comparisons for integer, swapping operands and multiple
8731 // operations may be required for some comparisons.
8733 bool Swap = false, Invert = false, FlipSigns = false;
8735 switch (SetCCOpcode) {
8736 default: llvm_unreachable("Unexpected SETCC condition");
8737 case ISD::SETNE: Invert = true;
8738 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8739 case ISD::SETLT: Swap = true;
8740 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8741 case ISD::SETGE: Swap = true;
8742 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8743 case ISD::SETULT: Swap = true;
8744 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8745 case ISD::SETUGE: Swap = true;
8746 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8749 std::swap(Op0, Op1);
8751 // Check that the operation in question is available (most are plain SSE2,
8752 // but PCMPGTQ and PCMPEQQ have different requirements).
8753 if (VT == MVT::v2i64) {
8754 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
8756 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41())
8760 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8761 // bits of the inputs before performing those operations.
8763 EVT EltVT = VT.getVectorElementType();
8764 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8766 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8767 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8769 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8770 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8773 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8775 // If the logical-not of the result is required, perform that now.
8777 Result = DAG.getNOT(dl, Result, VT);
8782 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8783 static bool isX86LogicalCmp(SDValue Op) {
8784 unsigned Opc = Op.getNode()->getOpcode();
8785 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8786 Opc == X86ISD::SAHF)
8788 if (Op.getResNo() == 1 &&
8789 (Opc == X86ISD::ADD ||
8790 Opc == X86ISD::SUB ||
8791 Opc == X86ISD::ADC ||
8792 Opc == X86ISD::SBB ||
8793 Opc == X86ISD::SMUL ||
8794 Opc == X86ISD::UMUL ||
8795 Opc == X86ISD::INC ||
8796 Opc == X86ISD::DEC ||
8797 Opc == X86ISD::OR ||
8798 Opc == X86ISD::XOR ||
8799 Opc == X86ISD::AND))
8802 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8808 static bool isZero(SDValue V) {
8809 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8810 return C && C->isNullValue();
8813 static bool isAllOnes(SDValue V) {
8814 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8815 return C && C->isAllOnesValue();
8818 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
8819 if (V.getOpcode() != ISD::TRUNCATE)
8822 SDValue VOp0 = V.getOperand(0);
8823 unsigned InBits = VOp0.getValueSizeInBits();
8824 unsigned Bits = V.getValueSizeInBits();
8825 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
8828 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8829 bool addTest = true;
8830 SDValue Cond = Op.getOperand(0);
8831 SDValue Op1 = Op.getOperand(1);
8832 SDValue Op2 = Op.getOperand(2);
8833 DebugLoc DL = Op.getDebugLoc();
8836 if (Cond.getOpcode() == ISD::SETCC) {
8837 SDValue NewCond = LowerSETCC(Cond, DAG);
8838 if (NewCond.getNode())
8842 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8843 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8844 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8845 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8846 if (Cond.getOpcode() == X86ISD::SETCC &&
8847 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8848 isZero(Cond.getOperand(1).getOperand(1))) {
8849 SDValue Cmp = Cond.getOperand(1);
8851 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8853 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8854 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8855 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8857 SDValue CmpOp0 = Cmp.getOperand(0);
8858 // Apply further optimizations for special cases
8859 // (select (x != 0), -1, 0) -> neg & sbb
8860 // (select (x == 0), 0, -1) -> neg & sbb
8861 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8862 if (YC->isNullValue() &&
8863 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8864 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8865 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8866 DAG.getConstant(0, CmpOp0.getValueType()),
8868 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8869 DAG.getConstant(X86::COND_B, MVT::i8),
8870 SDValue(Neg.getNode(), 1));
8874 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8875 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8876 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8878 SDValue Res = // Res = 0 or -1.
8879 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8880 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8882 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8883 Res = DAG.getNOT(DL, Res, Res.getValueType());
8885 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8886 if (N2C == 0 || !N2C->isNullValue())
8887 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8892 // Look past (and (setcc_carry (cmp ...)), 1).
8893 if (Cond.getOpcode() == ISD::AND &&
8894 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8895 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8896 if (C && C->getAPIntValue() == 1)
8897 Cond = Cond.getOperand(0);
8900 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8901 // setting operand in place of the X86ISD::SETCC.
8902 unsigned CondOpcode = Cond.getOpcode();
8903 if (CondOpcode == X86ISD::SETCC ||
8904 CondOpcode == X86ISD::SETCC_CARRY) {
8905 CC = Cond.getOperand(0);
8907 SDValue Cmp = Cond.getOperand(1);
8908 unsigned Opc = Cmp.getOpcode();
8909 EVT VT = Op.getValueType();
8911 bool IllegalFPCMov = false;
8912 if (VT.isFloatingPoint() && !VT.isVector() &&
8913 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8914 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8916 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8917 Opc == X86ISD::BT) { // FIXME
8921 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8922 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8923 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8924 Cond.getOperand(0).getValueType() != MVT::i8)) {
8925 SDValue LHS = Cond.getOperand(0);
8926 SDValue RHS = Cond.getOperand(1);
8930 switch (CondOpcode) {
8931 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8932 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8933 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8934 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8935 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8936 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8937 default: llvm_unreachable("unexpected overflowing operator");
8939 if (CondOpcode == ISD::UMULO)
8940 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8943 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8945 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8947 if (CondOpcode == ISD::UMULO)
8948 Cond = X86Op.getValue(2);
8950 Cond = X86Op.getValue(1);
8952 CC = DAG.getConstant(X86Cond, MVT::i8);
8957 // Look pass the truncate if the high bits are known zero.
8958 if (isTruncWithZeroHighBitsInput(Cond, DAG))
8959 Cond = Cond.getOperand(0);
8961 // We know the result of AND is compared against zero. Try to match
8963 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8964 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8965 if (NewSetCC.getNode()) {
8966 CC = NewSetCC.getOperand(0);
8967 Cond = NewSetCC.getOperand(1);
8974 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8975 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8978 // a < b ? -1 : 0 -> RES = ~setcc_carry
8979 // a < b ? 0 : -1 -> RES = setcc_carry
8980 // a >= b ? -1 : 0 -> RES = setcc_carry
8981 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8982 if (Cond.getOpcode() == X86ISD::SUB) {
8983 Cond = ConvertCmpIfNecessary(Cond, DAG);
8984 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8986 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8987 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8988 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8989 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8990 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8991 return DAG.getNOT(DL, Res, Res.getValueType());
8996 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8997 // condition is true.
8998 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8999 SDValue Ops[] = { Op2, Op1, CC, Cond };
9000 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9003 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9004 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9005 // from the AND / OR.
9006 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9007 Opc = Op.getOpcode();
9008 if (Opc != ISD::OR && Opc != ISD::AND)
9010 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9011 Op.getOperand(0).hasOneUse() &&
9012 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9013 Op.getOperand(1).hasOneUse());
9016 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9017 // 1 and that the SETCC node has a single use.
9018 static bool isXor1OfSetCC(SDValue Op) {
9019 if (Op.getOpcode() != ISD::XOR)
9021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9022 if (N1C && N1C->getAPIntValue() == 1) {
9023 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9024 Op.getOperand(0).hasOneUse();
9029 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9030 bool addTest = true;
9031 SDValue Chain = Op.getOperand(0);
9032 SDValue Cond = Op.getOperand(1);
9033 SDValue Dest = Op.getOperand(2);
9034 DebugLoc dl = Op.getDebugLoc();
9036 bool Inverted = false;
9038 if (Cond.getOpcode() == ISD::SETCC) {
9039 // Check for setcc([su]{add,sub,mul}o == 0).
9040 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9041 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9042 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9043 Cond.getOperand(0).getResNo() == 1 &&
9044 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9045 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9046 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9047 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9048 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9049 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9051 Cond = Cond.getOperand(0);
9053 SDValue NewCond = LowerSETCC(Cond, DAG);
9054 if (NewCond.getNode())
9059 // FIXME: LowerXALUO doesn't handle these!!
9060 else if (Cond.getOpcode() == X86ISD::ADD ||
9061 Cond.getOpcode() == X86ISD::SUB ||
9062 Cond.getOpcode() == X86ISD::SMUL ||
9063 Cond.getOpcode() == X86ISD::UMUL)
9064 Cond = LowerXALUO(Cond, DAG);
9067 // Look pass (and (setcc_carry (cmp ...)), 1).
9068 if (Cond.getOpcode() == ISD::AND &&
9069 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9070 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9071 if (C && C->getAPIntValue() == 1)
9072 Cond = Cond.getOperand(0);
9075 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9076 // setting operand in place of the X86ISD::SETCC.
9077 unsigned CondOpcode = Cond.getOpcode();
9078 if (CondOpcode == X86ISD::SETCC ||
9079 CondOpcode == X86ISD::SETCC_CARRY) {
9080 CC = Cond.getOperand(0);
9082 SDValue Cmp = Cond.getOperand(1);
9083 unsigned Opc = Cmp.getOpcode();
9084 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9085 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9089 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9093 // These can only come from an arithmetic instruction with overflow,
9094 // e.g. SADDO, UADDO.
9095 Cond = Cond.getNode()->getOperand(1);
9101 CondOpcode = Cond.getOpcode();
9102 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9103 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9104 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9105 Cond.getOperand(0).getValueType() != MVT::i8)) {
9106 SDValue LHS = Cond.getOperand(0);
9107 SDValue RHS = Cond.getOperand(1);
9111 switch (CondOpcode) {
9112 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9113 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9114 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9115 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9116 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9117 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9118 default: llvm_unreachable("unexpected overflowing operator");
9121 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9122 if (CondOpcode == ISD::UMULO)
9123 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9126 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9128 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9130 if (CondOpcode == ISD::UMULO)
9131 Cond = X86Op.getValue(2);
9133 Cond = X86Op.getValue(1);
9135 CC = DAG.getConstant(X86Cond, MVT::i8);
9139 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9140 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9141 if (CondOpc == ISD::OR) {
9142 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9143 // two branches instead of an explicit OR instruction with a
9145 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9146 isX86LogicalCmp(Cmp)) {
9147 CC = Cond.getOperand(0).getOperand(0);
9148 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9149 Chain, Dest, CC, Cmp);
9150 CC = Cond.getOperand(1).getOperand(0);
9154 } else { // ISD::AND
9155 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9156 // two branches instead of an explicit AND instruction with a
9157 // separate test. However, we only do this if this block doesn't
9158 // have a fall-through edge, because this requires an explicit
9159 // jmp when the condition is false.
9160 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9161 isX86LogicalCmp(Cmp) &&
9162 Op.getNode()->hasOneUse()) {
9163 X86::CondCode CCode =
9164 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9165 CCode = X86::GetOppositeBranchCondition(CCode);
9166 CC = DAG.getConstant(CCode, MVT::i8);
9167 SDNode *User = *Op.getNode()->use_begin();
9168 // Look for an unconditional branch following this conditional branch.
9169 // We need this because we need to reverse the successors in order
9170 // to implement FCMP_OEQ.
9171 if (User->getOpcode() == ISD::BR) {
9172 SDValue FalseBB = User->getOperand(1);
9174 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9175 assert(NewBR == User);
9179 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9180 Chain, Dest, CC, Cmp);
9181 X86::CondCode CCode =
9182 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9183 CCode = X86::GetOppositeBranchCondition(CCode);
9184 CC = DAG.getConstant(CCode, MVT::i8);
9190 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9191 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9192 // It should be transformed during dag combiner except when the condition
9193 // is set by a arithmetics with overflow node.
9194 X86::CondCode CCode =
9195 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9196 CCode = X86::GetOppositeBranchCondition(CCode);
9197 CC = DAG.getConstant(CCode, MVT::i8);
9198 Cond = Cond.getOperand(0).getOperand(1);
9200 } else if (Cond.getOpcode() == ISD::SETCC &&
9201 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9202 // For FCMP_OEQ, we can emit
9203 // two branches instead of an explicit AND instruction with a
9204 // separate test. However, we only do this if this block doesn't
9205 // have a fall-through edge, because this requires an explicit
9206 // jmp when the condition is false.
9207 if (Op.getNode()->hasOneUse()) {
9208 SDNode *User = *Op.getNode()->use_begin();
9209 // Look for an unconditional branch following this conditional branch.
9210 // We need this because we need to reverse the successors in order
9211 // to implement FCMP_OEQ.
9212 if (User->getOpcode() == ISD::BR) {
9213 SDValue FalseBB = User->getOperand(1);
9215 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9216 assert(NewBR == User);
9220 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9221 Cond.getOperand(0), Cond.getOperand(1));
9222 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9223 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9224 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9225 Chain, Dest, CC, Cmp);
9226 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9231 } else if (Cond.getOpcode() == ISD::SETCC &&
9232 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9233 // For FCMP_UNE, we can emit
9234 // two branches instead of an explicit AND instruction with a
9235 // separate test. However, we only do this if this block doesn't
9236 // have a fall-through edge, because this requires an explicit
9237 // jmp when the condition is false.
9238 if (Op.getNode()->hasOneUse()) {
9239 SDNode *User = *Op.getNode()->use_begin();
9240 // Look for an unconditional branch following this conditional branch.
9241 // We need this because we need to reverse the successors in order
9242 // to implement FCMP_UNE.
9243 if (User->getOpcode() == ISD::BR) {
9244 SDValue FalseBB = User->getOperand(1);
9246 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9247 assert(NewBR == User);
9250 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9251 Cond.getOperand(0), Cond.getOperand(1));
9252 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9253 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9254 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9255 Chain, Dest, CC, Cmp);
9256 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9266 // Look pass the truncate if the high bits are known zero.
9267 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9268 Cond = Cond.getOperand(0);
9270 // We know the result of AND is compared against zero. Try to match
9272 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9273 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9274 if (NewSetCC.getNode()) {
9275 CC = NewSetCC.getOperand(0);
9276 Cond = NewSetCC.getOperand(1);
9283 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9284 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9286 Cond = ConvertCmpIfNecessary(Cond, DAG);
9287 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9288 Chain, Dest, CC, Cond);
9292 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9293 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9294 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9295 // that the guard pages used by the OS virtual memory manager are allocated in
9296 // correct sequence.
9298 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9299 SelectionDAG &DAG) const {
9300 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9301 getTargetMachine().Options.EnableSegmentedStacks) &&
9302 "This should be used only on Windows targets or when segmented stacks "
9304 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9305 DebugLoc dl = Op.getDebugLoc();
9308 SDValue Chain = Op.getOperand(0);
9309 SDValue Size = Op.getOperand(1);
9310 // FIXME: Ensure alignment here
9312 bool Is64Bit = Subtarget->is64Bit();
9313 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9315 if (getTargetMachine().Options.EnableSegmentedStacks) {
9316 MachineFunction &MF = DAG.getMachineFunction();
9317 MachineRegisterInfo &MRI = MF.getRegInfo();
9320 // The 64 bit implementation of segmented stacks needs to clobber both r10
9321 // r11. This makes it impossible to use it along with nested parameters.
9322 const Function *F = MF.getFunction();
9324 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9326 if (I->hasNestAttr())
9327 report_fatal_error("Cannot use segmented stacks with functions that "
9328 "have nested arguments.");
9331 const TargetRegisterClass *AddrRegClass =
9332 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9333 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9334 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9335 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9336 DAG.getRegister(Vreg, SPTy));
9337 SDValue Ops1[2] = { Value, Chain };
9338 return DAG.getMergeValues(Ops1, 2, dl);
9341 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9343 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9344 Flag = Chain.getValue(1);
9345 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9347 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9348 Flag = Chain.getValue(1);
9350 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9352 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9353 return DAG.getMergeValues(Ops1, 2, dl);
9357 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9358 MachineFunction &MF = DAG.getMachineFunction();
9359 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9361 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9362 DebugLoc DL = Op.getDebugLoc();
9364 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9365 // vastart just stores the address of the VarArgsFrameIndex slot into the
9366 // memory location argument.
9367 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9369 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9370 MachinePointerInfo(SV), false, false, 0);
9374 // gp_offset (0 - 6 * 8)
9375 // fp_offset (48 - 48 + 8 * 16)
9376 // overflow_arg_area (point to parameters coming in memory).
9378 SmallVector<SDValue, 8> MemOps;
9379 SDValue FIN = Op.getOperand(1);
9381 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9382 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9384 FIN, MachinePointerInfo(SV), false, false, 0);
9385 MemOps.push_back(Store);
9388 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9389 FIN, DAG.getIntPtrConstant(4));
9390 Store = DAG.getStore(Op.getOperand(0), DL,
9391 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9393 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9394 MemOps.push_back(Store);
9396 // Store ptr to overflow_arg_area
9397 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9398 FIN, DAG.getIntPtrConstant(4));
9399 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9401 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9402 MachinePointerInfo(SV, 8),
9404 MemOps.push_back(Store);
9406 // Store ptr to reg_save_area.
9407 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9408 FIN, DAG.getIntPtrConstant(8));
9409 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9411 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9412 MachinePointerInfo(SV, 16), false, false, 0);
9413 MemOps.push_back(Store);
9414 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9415 &MemOps[0], MemOps.size());
9418 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9419 assert(Subtarget->is64Bit() &&
9420 "LowerVAARG only handles 64-bit va_arg!");
9421 assert((Subtarget->isTargetLinux() ||
9422 Subtarget->isTargetDarwin()) &&
9423 "Unhandled target in LowerVAARG");
9424 assert(Op.getNode()->getNumOperands() == 4);
9425 SDValue Chain = Op.getOperand(0);
9426 SDValue SrcPtr = Op.getOperand(1);
9427 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9428 unsigned Align = Op.getConstantOperandVal(3);
9429 DebugLoc dl = Op.getDebugLoc();
9431 EVT ArgVT = Op.getNode()->getValueType(0);
9432 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9433 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9436 // Decide which area this value should be read from.
9437 // TODO: Implement the AMD64 ABI in its entirety. This simple
9438 // selection mechanism works only for the basic types.
9439 if (ArgVT == MVT::f80) {
9440 llvm_unreachable("va_arg for f80 not yet implemented");
9441 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9442 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9443 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9444 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9446 llvm_unreachable("Unhandled argument type in LowerVAARG");
9450 // Sanity Check: Make sure using fp_offset makes sense.
9451 assert(!getTargetMachine().Options.UseSoftFloat &&
9452 !(DAG.getMachineFunction()
9453 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9454 Subtarget->hasSSE1());
9457 // Insert VAARG_64 node into the DAG
9458 // VAARG_64 returns two values: Variable Argument Address, Chain
9459 SmallVector<SDValue, 11> InstOps;
9460 InstOps.push_back(Chain);
9461 InstOps.push_back(SrcPtr);
9462 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9463 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9464 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9465 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9466 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9467 VTs, &InstOps[0], InstOps.size(),
9469 MachinePointerInfo(SV),
9474 Chain = VAARG.getValue(1);
9476 // Load the next argument and return it
9477 return DAG.getLoad(ArgVT, dl,
9480 MachinePointerInfo(),
9481 false, false, false, 0);
9484 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9485 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9486 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9487 SDValue Chain = Op.getOperand(0);
9488 SDValue DstPtr = Op.getOperand(1);
9489 SDValue SrcPtr = Op.getOperand(2);
9490 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9491 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9492 DebugLoc DL = Op.getDebugLoc();
9494 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9495 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9497 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9500 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9501 // may or may not be a constant. Takes immediate version of shift as input.
9502 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9503 SDValue SrcOp, SDValue ShAmt,
9504 SelectionDAG &DAG) {
9505 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9507 if (isa<ConstantSDNode>(ShAmt)) {
9508 // Constant may be a TargetConstant. Use a regular constant.
9509 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9511 default: llvm_unreachable("Unknown target vector shift node");
9515 return DAG.getNode(Opc, dl, VT, SrcOp,
9516 DAG.getConstant(ShiftAmt, MVT::i32));
9520 // Change opcode to non-immediate version
9522 default: llvm_unreachable("Unknown target vector shift node");
9523 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9524 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9525 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9528 // Need to build a vector containing shift amount
9529 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9532 ShOps[1] = DAG.getConstant(0, MVT::i32);
9533 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
9534 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9536 // The return type has to be a 128-bit type with the same element
9537 // type as the input type.
9538 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9539 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9541 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9542 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9546 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9547 DebugLoc dl = Op.getDebugLoc();
9548 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9550 default: return SDValue(); // Don't custom lower most intrinsics.
9551 // Comparison intrinsics.
9552 case Intrinsic::x86_sse_comieq_ss:
9553 case Intrinsic::x86_sse_comilt_ss:
9554 case Intrinsic::x86_sse_comile_ss:
9555 case Intrinsic::x86_sse_comigt_ss:
9556 case Intrinsic::x86_sse_comige_ss:
9557 case Intrinsic::x86_sse_comineq_ss:
9558 case Intrinsic::x86_sse_ucomieq_ss:
9559 case Intrinsic::x86_sse_ucomilt_ss:
9560 case Intrinsic::x86_sse_ucomile_ss:
9561 case Intrinsic::x86_sse_ucomigt_ss:
9562 case Intrinsic::x86_sse_ucomige_ss:
9563 case Intrinsic::x86_sse_ucomineq_ss:
9564 case Intrinsic::x86_sse2_comieq_sd:
9565 case Intrinsic::x86_sse2_comilt_sd:
9566 case Intrinsic::x86_sse2_comile_sd:
9567 case Intrinsic::x86_sse2_comigt_sd:
9568 case Intrinsic::x86_sse2_comige_sd:
9569 case Intrinsic::x86_sse2_comineq_sd:
9570 case Intrinsic::x86_sse2_ucomieq_sd:
9571 case Intrinsic::x86_sse2_ucomilt_sd:
9572 case Intrinsic::x86_sse2_ucomile_sd:
9573 case Intrinsic::x86_sse2_ucomigt_sd:
9574 case Intrinsic::x86_sse2_ucomige_sd:
9575 case Intrinsic::x86_sse2_ucomineq_sd: {
9579 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9580 case Intrinsic::x86_sse_comieq_ss:
9581 case Intrinsic::x86_sse2_comieq_sd:
9585 case Intrinsic::x86_sse_comilt_ss:
9586 case Intrinsic::x86_sse2_comilt_sd:
9590 case Intrinsic::x86_sse_comile_ss:
9591 case Intrinsic::x86_sse2_comile_sd:
9595 case Intrinsic::x86_sse_comigt_ss:
9596 case Intrinsic::x86_sse2_comigt_sd:
9600 case Intrinsic::x86_sse_comige_ss:
9601 case Intrinsic::x86_sse2_comige_sd:
9605 case Intrinsic::x86_sse_comineq_ss:
9606 case Intrinsic::x86_sse2_comineq_sd:
9610 case Intrinsic::x86_sse_ucomieq_ss:
9611 case Intrinsic::x86_sse2_ucomieq_sd:
9612 Opc = X86ISD::UCOMI;
9615 case Intrinsic::x86_sse_ucomilt_ss:
9616 case Intrinsic::x86_sse2_ucomilt_sd:
9617 Opc = X86ISD::UCOMI;
9620 case Intrinsic::x86_sse_ucomile_ss:
9621 case Intrinsic::x86_sse2_ucomile_sd:
9622 Opc = X86ISD::UCOMI;
9625 case Intrinsic::x86_sse_ucomigt_ss:
9626 case Intrinsic::x86_sse2_ucomigt_sd:
9627 Opc = X86ISD::UCOMI;
9630 case Intrinsic::x86_sse_ucomige_ss:
9631 case Intrinsic::x86_sse2_ucomige_sd:
9632 Opc = X86ISD::UCOMI;
9635 case Intrinsic::x86_sse_ucomineq_ss:
9636 case Intrinsic::x86_sse2_ucomineq_sd:
9637 Opc = X86ISD::UCOMI;
9642 SDValue LHS = Op.getOperand(1);
9643 SDValue RHS = Op.getOperand(2);
9644 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9645 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9646 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9647 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9648 DAG.getConstant(X86CC, MVT::i8), Cond);
9649 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9652 // Arithmetic intrinsics.
9653 case Intrinsic::x86_sse2_pmulu_dq:
9654 case Intrinsic::x86_avx2_pmulu_dq:
9655 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9656 Op.getOperand(1), Op.getOperand(2));
9658 // SSE3/AVX horizontal add/sub intrinsics
9659 case Intrinsic::x86_sse3_hadd_ps:
9660 case Intrinsic::x86_sse3_hadd_pd:
9661 case Intrinsic::x86_avx_hadd_ps_256:
9662 case Intrinsic::x86_avx_hadd_pd_256:
9663 case Intrinsic::x86_sse3_hsub_ps:
9664 case Intrinsic::x86_sse3_hsub_pd:
9665 case Intrinsic::x86_avx_hsub_ps_256:
9666 case Intrinsic::x86_avx_hsub_pd_256:
9667 case Intrinsic::x86_ssse3_phadd_w_128:
9668 case Intrinsic::x86_ssse3_phadd_d_128:
9669 case Intrinsic::x86_avx2_phadd_w:
9670 case Intrinsic::x86_avx2_phadd_d:
9671 case Intrinsic::x86_ssse3_phsub_w_128:
9672 case Intrinsic::x86_ssse3_phsub_d_128:
9673 case Intrinsic::x86_avx2_phsub_w:
9674 case Intrinsic::x86_avx2_phsub_d: {
9677 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9678 case Intrinsic::x86_sse3_hadd_ps:
9679 case Intrinsic::x86_sse3_hadd_pd:
9680 case Intrinsic::x86_avx_hadd_ps_256:
9681 case Intrinsic::x86_avx_hadd_pd_256:
9682 Opcode = X86ISD::FHADD;
9684 case Intrinsic::x86_sse3_hsub_ps:
9685 case Intrinsic::x86_sse3_hsub_pd:
9686 case Intrinsic::x86_avx_hsub_ps_256:
9687 case Intrinsic::x86_avx_hsub_pd_256:
9688 Opcode = X86ISD::FHSUB;
9690 case Intrinsic::x86_ssse3_phadd_w_128:
9691 case Intrinsic::x86_ssse3_phadd_d_128:
9692 case Intrinsic::x86_avx2_phadd_w:
9693 case Intrinsic::x86_avx2_phadd_d:
9694 Opcode = X86ISD::HADD;
9696 case Intrinsic::x86_ssse3_phsub_w_128:
9697 case Intrinsic::x86_ssse3_phsub_d_128:
9698 case Intrinsic::x86_avx2_phsub_w:
9699 case Intrinsic::x86_avx2_phsub_d:
9700 Opcode = X86ISD::HSUB;
9703 return DAG.getNode(Opcode, dl, Op.getValueType(),
9704 Op.getOperand(1), Op.getOperand(2));
9707 // AVX2 variable shift intrinsics
9708 case Intrinsic::x86_avx2_psllv_d:
9709 case Intrinsic::x86_avx2_psllv_q:
9710 case Intrinsic::x86_avx2_psllv_d_256:
9711 case Intrinsic::x86_avx2_psllv_q_256:
9712 case Intrinsic::x86_avx2_psrlv_d:
9713 case Intrinsic::x86_avx2_psrlv_q:
9714 case Intrinsic::x86_avx2_psrlv_d_256:
9715 case Intrinsic::x86_avx2_psrlv_q_256:
9716 case Intrinsic::x86_avx2_psrav_d:
9717 case Intrinsic::x86_avx2_psrav_d_256: {
9720 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9721 case Intrinsic::x86_avx2_psllv_d:
9722 case Intrinsic::x86_avx2_psllv_q:
9723 case Intrinsic::x86_avx2_psllv_d_256:
9724 case Intrinsic::x86_avx2_psllv_q_256:
9727 case Intrinsic::x86_avx2_psrlv_d:
9728 case Intrinsic::x86_avx2_psrlv_q:
9729 case Intrinsic::x86_avx2_psrlv_d_256:
9730 case Intrinsic::x86_avx2_psrlv_q_256:
9733 case Intrinsic::x86_avx2_psrav_d:
9734 case Intrinsic::x86_avx2_psrav_d_256:
9738 return DAG.getNode(Opcode, dl, Op.getValueType(),
9739 Op.getOperand(1), Op.getOperand(2));
9742 case Intrinsic::x86_ssse3_pshuf_b_128:
9743 case Intrinsic::x86_avx2_pshuf_b:
9744 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9745 Op.getOperand(1), Op.getOperand(2));
9747 case Intrinsic::x86_ssse3_psign_b_128:
9748 case Intrinsic::x86_ssse3_psign_w_128:
9749 case Intrinsic::x86_ssse3_psign_d_128:
9750 case Intrinsic::x86_avx2_psign_b:
9751 case Intrinsic::x86_avx2_psign_w:
9752 case Intrinsic::x86_avx2_psign_d:
9753 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9754 Op.getOperand(1), Op.getOperand(2));
9756 case Intrinsic::x86_sse41_insertps:
9757 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9758 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9760 case Intrinsic::x86_avx_vperm2f128_ps_256:
9761 case Intrinsic::x86_avx_vperm2f128_pd_256:
9762 case Intrinsic::x86_avx_vperm2f128_si_256:
9763 case Intrinsic::x86_avx2_vperm2i128:
9764 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9765 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9767 case Intrinsic::x86_avx2_permd:
9768 case Intrinsic::x86_avx2_permps:
9769 // Operands intentionally swapped. Mask is last operand to intrinsic,
9770 // but second operand for node/intruction.
9771 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9772 Op.getOperand(2), Op.getOperand(1));
9774 // ptest and testp intrinsics. The intrinsic these come from are designed to
9775 // return an integer value, not just an instruction so lower it to the ptest
9776 // or testp pattern and a setcc for the result.
9777 case Intrinsic::x86_sse41_ptestz:
9778 case Intrinsic::x86_sse41_ptestc:
9779 case Intrinsic::x86_sse41_ptestnzc:
9780 case Intrinsic::x86_avx_ptestz_256:
9781 case Intrinsic::x86_avx_ptestc_256:
9782 case Intrinsic::x86_avx_ptestnzc_256:
9783 case Intrinsic::x86_avx_vtestz_ps:
9784 case Intrinsic::x86_avx_vtestc_ps:
9785 case Intrinsic::x86_avx_vtestnzc_ps:
9786 case Intrinsic::x86_avx_vtestz_pd:
9787 case Intrinsic::x86_avx_vtestc_pd:
9788 case Intrinsic::x86_avx_vtestnzc_pd:
9789 case Intrinsic::x86_avx_vtestz_ps_256:
9790 case Intrinsic::x86_avx_vtestc_ps_256:
9791 case Intrinsic::x86_avx_vtestnzc_ps_256:
9792 case Intrinsic::x86_avx_vtestz_pd_256:
9793 case Intrinsic::x86_avx_vtestc_pd_256:
9794 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9795 bool IsTestPacked = false;
9798 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9799 case Intrinsic::x86_avx_vtestz_ps:
9800 case Intrinsic::x86_avx_vtestz_pd:
9801 case Intrinsic::x86_avx_vtestz_ps_256:
9802 case Intrinsic::x86_avx_vtestz_pd_256:
9803 IsTestPacked = true; // Fallthrough
9804 case Intrinsic::x86_sse41_ptestz:
9805 case Intrinsic::x86_avx_ptestz_256:
9807 X86CC = X86::COND_E;
9809 case Intrinsic::x86_avx_vtestc_ps:
9810 case Intrinsic::x86_avx_vtestc_pd:
9811 case Intrinsic::x86_avx_vtestc_ps_256:
9812 case Intrinsic::x86_avx_vtestc_pd_256:
9813 IsTestPacked = true; // Fallthrough
9814 case Intrinsic::x86_sse41_ptestc:
9815 case Intrinsic::x86_avx_ptestc_256:
9817 X86CC = X86::COND_B;
9819 case Intrinsic::x86_avx_vtestnzc_ps:
9820 case Intrinsic::x86_avx_vtestnzc_pd:
9821 case Intrinsic::x86_avx_vtestnzc_ps_256:
9822 case Intrinsic::x86_avx_vtestnzc_pd_256:
9823 IsTestPacked = true; // Fallthrough
9824 case Intrinsic::x86_sse41_ptestnzc:
9825 case Intrinsic::x86_avx_ptestnzc_256:
9827 X86CC = X86::COND_A;
9831 SDValue LHS = Op.getOperand(1);
9832 SDValue RHS = Op.getOperand(2);
9833 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9834 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9835 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9836 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9837 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9840 // SSE/AVX shift intrinsics
9841 case Intrinsic::x86_sse2_psll_w:
9842 case Intrinsic::x86_sse2_psll_d:
9843 case Intrinsic::x86_sse2_psll_q:
9844 case Intrinsic::x86_avx2_psll_w:
9845 case Intrinsic::x86_avx2_psll_d:
9846 case Intrinsic::x86_avx2_psll_q:
9847 case Intrinsic::x86_sse2_psrl_w:
9848 case Intrinsic::x86_sse2_psrl_d:
9849 case Intrinsic::x86_sse2_psrl_q:
9850 case Intrinsic::x86_avx2_psrl_w:
9851 case Intrinsic::x86_avx2_psrl_d:
9852 case Intrinsic::x86_avx2_psrl_q:
9853 case Intrinsic::x86_sse2_psra_w:
9854 case Intrinsic::x86_sse2_psra_d:
9855 case Intrinsic::x86_avx2_psra_w:
9856 case Intrinsic::x86_avx2_psra_d: {
9859 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9860 case Intrinsic::x86_sse2_psll_w:
9861 case Intrinsic::x86_sse2_psll_d:
9862 case Intrinsic::x86_sse2_psll_q:
9863 case Intrinsic::x86_avx2_psll_w:
9864 case Intrinsic::x86_avx2_psll_d:
9865 case Intrinsic::x86_avx2_psll_q:
9866 Opcode = X86ISD::VSHL;
9868 case Intrinsic::x86_sse2_psrl_w:
9869 case Intrinsic::x86_sse2_psrl_d:
9870 case Intrinsic::x86_sse2_psrl_q:
9871 case Intrinsic::x86_avx2_psrl_w:
9872 case Intrinsic::x86_avx2_psrl_d:
9873 case Intrinsic::x86_avx2_psrl_q:
9874 Opcode = X86ISD::VSRL;
9876 case Intrinsic::x86_sse2_psra_w:
9877 case Intrinsic::x86_sse2_psra_d:
9878 case Intrinsic::x86_avx2_psra_w:
9879 case Intrinsic::x86_avx2_psra_d:
9880 Opcode = X86ISD::VSRA;
9883 return DAG.getNode(Opcode, dl, Op.getValueType(),
9884 Op.getOperand(1), Op.getOperand(2));
9887 // SSE/AVX immediate shift intrinsics
9888 case Intrinsic::x86_sse2_pslli_w:
9889 case Intrinsic::x86_sse2_pslli_d:
9890 case Intrinsic::x86_sse2_pslli_q:
9891 case Intrinsic::x86_avx2_pslli_w:
9892 case Intrinsic::x86_avx2_pslli_d:
9893 case Intrinsic::x86_avx2_pslli_q:
9894 case Intrinsic::x86_sse2_psrli_w:
9895 case Intrinsic::x86_sse2_psrli_d:
9896 case Intrinsic::x86_sse2_psrli_q:
9897 case Intrinsic::x86_avx2_psrli_w:
9898 case Intrinsic::x86_avx2_psrli_d:
9899 case Intrinsic::x86_avx2_psrli_q:
9900 case Intrinsic::x86_sse2_psrai_w:
9901 case Intrinsic::x86_sse2_psrai_d:
9902 case Intrinsic::x86_avx2_psrai_w:
9903 case Intrinsic::x86_avx2_psrai_d: {
9906 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9907 case Intrinsic::x86_sse2_pslli_w:
9908 case Intrinsic::x86_sse2_pslli_d:
9909 case Intrinsic::x86_sse2_pslli_q:
9910 case Intrinsic::x86_avx2_pslli_w:
9911 case Intrinsic::x86_avx2_pslli_d:
9912 case Intrinsic::x86_avx2_pslli_q:
9913 Opcode = X86ISD::VSHLI;
9915 case Intrinsic::x86_sse2_psrli_w:
9916 case Intrinsic::x86_sse2_psrli_d:
9917 case Intrinsic::x86_sse2_psrli_q:
9918 case Intrinsic::x86_avx2_psrli_w:
9919 case Intrinsic::x86_avx2_psrli_d:
9920 case Intrinsic::x86_avx2_psrli_q:
9921 Opcode = X86ISD::VSRLI;
9923 case Intrinsic::x86_sse2_psrai_w:
9924 case Intrinsic::x86_sse2_psrai_d:
9925 case Intrinsic::x86_avx2_psrai_w:
9926 case Intrinsic::x86_avx2_psrai_d:
9927 Opcode = X86ISD::VSRAI;
9930 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
9931 Op.getOperand(1), Op.getOperand(2), DAG);
9934 // Fix vector shift instructions where the last operand is a non-immediate
9936 case Intrinsic::x86_mmx_pslli_w:
9937 case Intrinsic::x86_mmx_pslli_d:
9938 case Intrinsic::x86_mmx_pslli_q:
9939 case Intrinsic::x86_mmx_psrli_w:
9940 case Intrinsic::x86_mmx_psrli_d:
9941 case Intrinsic::x86_mmx_psrli_q:
9942 case Intrinsic::x86_mmx_psrai_w:
9943 case Intrinsic::x86_mmx_psrai_d: {
9944 SDValue ShAmt = Op.getOperand(2);
9945 if (isa<ConstantSDNode>(ShAmt))
9950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9951 case Intrinsic::x86_mmx_pslli_w:
9952 NewIntNo = Intrinsic::x86_mmx_psll_w;
9954 case Intrinsic::x86_mmx_pslli_d:
9955 NewIntNo = Intrinsic::x86_mmx_psll_d;
9957 case Intrinsic::x86_mmx_pslli_q:
9958 NewIntNo = Intrinsic::x86_mmx_psll_q;
9960 case Intrinsic::x86_mmx_psrli_w:
9961 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9963 case Intrinsic::x86_mmx_psrli_d:
9964 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9966 case Intrinsic::x86_mmx_psrli_q:
9967 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9969 case Intrinsic::x86_mmx_psrai_w:
9970 NewIntNo = Intrinsic::x86_mmx_psra_w;
9972 case Intrinsic::x86_mmx_psrai_d:
9973 NewIntNo = Intrinsic::x86_mmx_psra_d;
9977 // The vector shift intrinsics with scalars uses 32b shift amounts but
9978 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9980 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9981 DAG.getConstant(0, MVT::i32));
9982 // FIXME this must be lowered to get rid of the invalid type.
9984 EVT VT = Op.getValueType();
9985 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9986 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9987 DAG.getConstant(NewIntNo, MVT::i32),
9988 Op.getOperand(1), ShAmt);
9990 case Intrinsic::x86_sse42_pcmpistria128:
9991 case Intrinsic::x86_sse42_pcmpestria128:
9992 case Intrinsic::x86_sse42_pcmpistric128:
9993 case Intrinsic::x86_sse42_pcmpestric128:
9994 case Intrinsic::x86_sse42_pcmpistrio128:
9995 case Intrinsic::x86_sse42_pcmpestrio128:
9996 case Intrinsic::x86_sse42_pcmpistris128:
9997 case Intrinsic::x86_sse42_pcmpestris128:
9998 case Intrinsic::x86_sse42_pcmpistriz128:
9999 case Intrinsic::x86_sse42_pcmpestriz128: {
10003 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10004 case Intrinsic::x86_sse42_pcmpistria128:
10005 Opcode = X86ISD::PCMPISTRI;
10006 X86CC = X86::COND_A;
10008 case Intrinsic::x86_sse42_pcmpestria128:
10009 Opcode = X86ISD::PCMPESTRI;
10010 X86CC = X86::COND_A;
10012 case Intrinsic::x86_sse42_pcmpistric128:
10013 Opcode = X86ISD::PCMPISTRI;
10014 X86CC = X86::COND_B;
10016 case Intrinsic::x86_sse42_pcmpestric128:
10017 Opcode = X86ISD::PCMPESTRI;
10018 X86CC = X86::COND_B;
10020 case Intrinsic::x86_sse42_pcmpistrio128:
10021 Opcode = X86ISD::PCMPISTRI;
10022 X86CC = X86::COND_O;
10024 case Intrinsic::x86_sse42_pcmpestrio128:
10025 Opcode = X86ISD::PCMPESTRI;
10026 X86CC = X86::COND_O;
10028 case Intrinsic::x86_sse42_pcmpistris128:
10029 Opcode = X86ISD::PCMPISTRI;
10030 X86CC = X86::COND_S;
10032 case Intrinsic::x86_sse42_pcmpestris128:
10033 Opcode = X86ISD::PCMPESTRI;
10034 X86CC = X86::COND_S;
10036 case Intrinsic::x86_sse42_pcmpistriz128:
10037 Opcode = X86ISD::PCMPISTRI;
10038 X86CC = X86::COND_E;
10040 case Intrinsic::x86_sse42_pcmpestriz128:
10041 Opcode = X86ISD::PCMPESTRI;
10042 X86CC = X86::COND_E;
10045 SmallVector<SDValue, 5> NewOps;
10046 NewOps.append(Op->op_begin()+1, Op->op_end());
10047 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10048 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10049 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10050 DAG.getConstant(X86CC, MVT::i8),
10051 SDValue(PCMP.getNode(), 1));
10052 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10055 case Intrinsic::x86_sse42_pcmpistri128:
10056 case Intrinsic::x86_sse42_pcmpestri128: {
10058 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10059 Opcode = X86ISD::PCMPISTRI;
10061 Opcode = X86ISD::PCMPESTRI;
10063 SmallVector<SDValue, 5> NewOps;
10064 NewOps.append(Op->op_begin()+1, Op->op_end());
10065 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10066 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10072 X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
10073 DebugLoc dl = Op.getDebugLoc();
10074 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10076 default: return SDValue(); // Don't custom lower most intrinsics.
10078 // RDRAND intrinsics.
10079 case Intrinsic::x86_rdrand_16:
10080 case Intrinsic::x86_rdrand_32:
10081 case Intrinsic::x86_rdrand_64: {
10082 // Emit the node with the right value type.
10083 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10084 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10086 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10087 // return the value from Rand, which is always 0, casted to i32.
10088 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10089 DAG.getConstant(1, Op->getValueType(1)),
10090 DAG.getConstant(X86::COND_B, MVT::i32),
10091 SDValue(Result.getNode(), 1) };
10092 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10093 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10096 // Return { result, isValid, chain }.
10097 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10098 SDValue(Result.getNode(), 2));
10103 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10104 SelectionDAG &DAG) const {
10105 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10106 MFI->setReturnAddressIsTaken(true);
10108 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10109 DebugLoc dl = Op.getDebugLoc();
10112 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10114 DAG.getConstant(TD->getPointerSize(),
10115 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
10116 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10117 DAG.getNode(ISD::ADD, dl, getPointerTy(),
10118 FrameAddr, Offset),
10119 MachinePointerInfo(), false, false, false, 0);
10122 // Just load the return address.
10123 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10124 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10125 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10128 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10129 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10130 MFI->setFrameAddressIsTaken(true);
10132 EVT VT = Op.getValueType();
10133 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10134 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10135 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10136 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10138 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10139 MachinePointerInfo(),
10140 false, false, false, 0);
10144 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10145 SelectionDAG &DAG) const {
10146 return DAG.getIntPtrConstant(2*TD->getPointerSize());
10149 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10150 SDValue Chain = Op.getOperand(0);
10151 SDValue Offset = Op.getOperand(1);
10152 SDValue Handler = Op.getOperand(2);
10153 DebugLoc dl = Op.getDebugLoc();
10155 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10156 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10158 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10160 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10161 DAG.getIntPtrConstant(TD->getPointerSize()));
10162 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10163 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10165 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10167 return DAG.getNode(X86ISD::EH_RETURN, dl,
10169 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10172 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
10173 SelectionDAG &DAG) const {
10174 return Op.getOperand(0);
10177 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10178 SelectionDAG &DAG) const {
10179 SDValue Root = Op.getOperand(0);
10180 SDValue Trmp = Op.getOperand(1); // trampoline
10181 SDValue FPtr = Op.getOperand(2); // nested function
10182 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10183 DebugLoc dl = Op.getDebugLoc();
10185 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10187 if (Subtarget->is64Bit()) {
10188 SDValue OutChains[6];
10190 // Large code-model.
10191 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10192 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10194 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
10195 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
10197 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10199 // Load the pointer to the nested function into R11.
10200 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10201 SDValue Addr = Trmp;
10202 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10203 Addr, MachinePointerInfo(TrmpAddr),
10206 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10207 DAG.getConstant(2, MVT::i64));
10208 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10209 MachinePointerInfo(TrmpAddr, 2),
10212 // Load the 'nest' parameter value into R10.
10213 // R10 is specified in X86CallingConv.td
10214 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10215 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10216 DAG.getConstant(10, MVT::i64));
10217 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10218 Addr, MachinePointerInfo(TrmpAddr, 10),
10221 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10222 DAG.getConstant(12, MVT::i64));
10223 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10224 MachinePointerInfo(TrmpAddr, 12),
10227 // Jump to the nested function.
10228 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10229 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10230 DAG.getConstant(20, MVT::i64));
10231 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10232 Addr, MachinePointerInfo(TrmpAddr, 20),
10235 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10236 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10237 DAG.getConstant(22, MVT::i64));
10238 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10239 MachinePointerInfo(TrmpAddr, 22),
10242 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10244 const Function *Func =
10245 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10246 CallingConv::ID CC = Func->getCallingConv();
10251 llvm_unreachable("Unsupported calling convention");
10252 case CallingConv::C:
10253 case CallingConv::X86_StdCall: {
10254 // Pass 'nest' parameter in ECX.
10255 // Must be kept in sync with X86CallingConv.td
10256 NestReg = X86::ECX;
10258 // Check that ECX wasn't needed by an 'inreg' parameter.
10259 FunctionType *FTy = Func->getFunctionType();
10260 const AttrListPtr &Attrs = Func->getAttributes();
10262 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10263 unsigned InRegCount = 0;
10266 for (FunctionType::param_iterator I = FTy->param_begin(),
10267 E = FTy->param_end(); I != E; ++I, ++Idx)
10268 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10269 // FIXME: should only count parameters that are lowered to integers.
10270 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10272 if (InRegCount > 2) {
10273 report_fatal_error("Nest register in use - reduce number of inreg"
10279 case CallingConv::X86_FastCall:
10280 case CallingConv::X86_ThisCall:
10281 case CallingConv::Fast:
10282 // Pass 'nest' parameter in EAX.
10283 // Must be kept in sync with X86CallingConv.td
10284 NestReg = X86::EAX;
10288 SDValue OutChains[4];
10289 SDValue Addr, Disp;
10291 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10292 DAG.getConstant(10, MVT::i32));
10293 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10295 // This is storing the opcode for MOV32ri.
10296 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10297 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10298 OutChains[0] = DAG.getStore(Root, dl,
10299 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10300 Trmp, MachinePointerInfo(TrmpAddr),
10303 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10304 DAG.getConstant(1, MVT::i32));
10305 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10306 MachinePointerInfo(TrmpAddr, 1),
10309 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10310 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10311 DAG.getConstant(5, MVT::i32));
10312 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10313 MachinePointerInfo(TrmpAddr, 5),
10316 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10317 DAG.getConstant(6, MVT::i32));
10318 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10319 MachinePointerInfo(TrmpAddr, 6),
10322 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10326 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10327 SelectionDAG &DAG) const {
10329 The rounding mode is in bits 11:10 of FPSR, and has the following
10331 00 Round to nearest
10336 FLT_ROUNDS, on the other hand, expects the following:
10343 To perform the conversion, we do:
10344 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10347 MachineFunction &MF = DAG.getMachineFunction();
10348 const TargetMachine &TM = MF.getTarget();
10349 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10350 unsigned StackAlignment = TFI.getStackAlignment();
10351 EVT VT = Op.getValueType();
10352 DebugLoc DL = Op.getDebugLoc();
10354 // Save FP Control Word to stack slot
10355 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10356 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10359 MachineMemOperand *MMO =
10360 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10361 MachineMemOperand::MOStore, 2, 2);
10363 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10364 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10365 DAG.getVTList(MVT::Other),
10366 Ops, 2, MVT::i16, MMO);
10368 // Load FP Control Word from stack slot
10369 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10370 MachinePointerInfo(), false, false, false, 0);
10372 // Transform as necessary
10374 DAG.getNode(ISD::SRL, DL, MVT::i16,
10375 DAG.getNode(ISD::AND, DL, MVT::i16,
10376 CWD, DAG.getConstant(0x800, MVT::i16)),
10377 DAG.getConstant(11, MVT::i8));
10379 DAG.getNode(ISD::SRL, DL, MVT::i16,
10380 DAG.getNode(ISD::AND, DL, MVT::i16,
10381 CWD, DAG.getConstant(0x400, MVT::i16)),
10382 DAG.getConstant(9, MVT::i8));
10385 DAG.getNode(ISD::AND, DL, MVT::i16,
10386 DAG.getNode(ISD::ADD, DL, MVT::i16,
10387 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10388 DAG.getConstant(1, MVT::i16)),
10389 DAG.getConstant(3, MVT::i16));
10392 return DAG.getNode((VT.getSizeInBits() < 16 ?
10393 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10396 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10397 EVT VT = Op.getValueType();
10399 unsigned NumBits = VT.getSizeInBits();
10400 DebugLoc dl = Op.getDebugLoc();
10402 Op = Op.getOperand(0);
10403 if (VT == MVT::i8) {
10404 // Zero extend to i32 since there is not an i8 bsr.
10406 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10409 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10410 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10411 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10413 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10416 DAG.getConstant(NumBits+NumBits-1, OpVT),
10417 DAG.getConstant(X86::COND_E, MVT::i8),
10420 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10422 // Finally xor with NumBits-1.
10423 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10426 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10430 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10431 SelectionDAG &DAG) const {
10432 EVT VT = Op.getValueType();
10434 unsigned NumBits = VT.getSizeInBits();
10435 DebugLoc dl = Op.getDebugLoc();
10437 Op = Op.getOperand(0);
10438 if (VT == MVT::i8) {
10439 // Zero extend to i32 since there is not an i8 bsr.
10441 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10444 // Issue a bsr (scan bits in reverse).
10445 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10446 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10448 // And xor with NumBits-1.
10449 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10452 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10456 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10457 EVT VT = Op.getValueType();
10458 unsigned NumBits = VT.getSizeInBits();
10459 DebugLoc dl = Op.getDebugLoc();
10460 Op = Op.getOperand(0);
10462 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10463 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10464 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10466 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10469 DAG.getConstant(NumBits, VT),
10470 DAG.getConstant(X86::COND_E, MVT::i8),
10473 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10476 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10477 // ones, and then concatenate the result back.
10478 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10479 EVT VT = Op.getValueType();
10481 assert(VT.is256BitVector() && VT.isInteger() &&
10482 "Unsupported value type for operation");
10484 unsigned NumElems = VT.getVectorNumElements();
10485 DebugLoc dl = Op.getDebugLoc();
10487 // Extract the LHS vectors
10488 SDValue LHS = Op.getOperand(0);
10489 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10490 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10492 // Extract the RHS vectors
10493 SDValue RHS = Op.getOperand(1);
10494 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10495 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10497 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10498 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10500 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10501 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10502 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10505 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10506 assert(Op.getValueType().is256BitVector() &&
10507 Op.getValueType().isInteger() &&
10508 "Only handle AVX 256-bit vector integer operation");
10509 return Lower256IntArith(Op, DAG);
10512 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10513 assert(Op.getValueType().is256BitVector() &&
10514 Op.getValueType().isInteger() &&
10515 "Only handle AVX 256-bit vector integer operation");
10516 return Lower256IntArith(Op, DAG);
10519 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10520 EVT VT = Op.getValueType();
10522 // Decompose 256-bit ops into smaller 128-bit ops.
10523 if (VT.is256BitVector() && !Subtarget->hasAVX2())
10524 return Lower256IntArith(Op, DAG);
10526 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10527 "Only know how to lower V2I64/V4I64 multiply");
10529 DebugLoc dl = Op.getDebugLoc();
10531 // Ahi = psrlqi(a, 32);
10532 // Bhi = psrlqi(b, 32);
10534 // AloBlo = pmuludq(a, b);
10535 // AloBhi = pmuludq(a, Bhi);
10536 // AhiBlo = pmuludq(Ahi, b);
10538 // AloBhi = psllqi(AloBhi, 32);
10539 // AhiBlo = psllqi(AhiBlo, 32);
10540 // return AloBlo + AloBhi + AhiBlo;
10542 SDValue A = Op.getOperand(0);
10543 SDValue B = Op.getOperand(1);
10545 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10547 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10548 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10550 // Bit cast to 32-bit vectors for MULUDQ
10551 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10552 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10553 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10554 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10555 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10557 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10558 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10559 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10561 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10562 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10564 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10565 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10568 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10570 EVT VT = Op.getValueType();
10571 DebugLoc dl = Op.getDebugLoc();
10572 SDValue R = Op.getOperand(0);
10573 SDValue Amt = Op.getOperand(1);
10574 LLVMContext *Context = DAG.getContext();
10576 if (!Subtarget->hasSSE2())
10579 // Optimize shl/srl/sra with constant shift amount.
10580 if (isSplatVector(Amt.getNode())) {
10581 SDValue SclrAmt = Amt->getOperand(0);
10582 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10583 uint64_t ShiftAmt = C->getZExtValue();
10585 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10586 (Subtarget->hasAVX2() &&
10587 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10588 if (Op.getOpcode() == ISD::SHL)
10589 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10590 DAG.getConstant(ShiftAmt, MVT::i32));
10591 if (Op.getOpcode() == ISD::SRL)
10592 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10593 DAG.getConstant(ShiftAmt, MVT::i32));
10594 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10595 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10596 DAG.getConstant(ShiftAmt, MVT::i32));
10599 if (VT == MVT::v16i8) {
10600 if (Op.getOpcode() == ISD::SHL) {
10601 // Make a large shift.
10602 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10603 DAG.getConstant(ShiftAmt, MVT::i32));
10604 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10605 // Zero out the rightmost bits.
10606 SmallVector<SDValue, 16> V(16,
10607 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10609 return DAG.getNode(ISD::AND, dl, VT, SHL,
10610 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10612 if (Op.getOpcode() == ISD::SRL) {
10613 // Make a large shift.
10614 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10615 DAG.getConstant(ShiftAmt, MVT::i32));
10616 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10617 // Zero out the leftmost bits.
10618 SmallVector<SDValue, 16> V(16,
10619 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10621 return DAG.getNode(ISD::AND, dl, VT, SRL,
10622 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10624 if (Op.getOpcode() == ISD::SRA) {
10625 if (ShiftAmt == 7) {
10626 // R s>> 7 === R s< 0
10627 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10628 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10631 // R s>> a === ((R u>> a) ^ m) - m
10632 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10633 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10635 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10636 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10637 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10640 llvm_unreachable("Unknown shift opcode.");
10643 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10644 if (Op.getOpcode() == ISD::SHL) {
10645 // Make a large shift.
10646 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10647 DAG.getConstant(ShiftAmt, MVT::i32));
10648 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10649 // Zero out the rightmost bits.
10650 SmallVector<SDValue, 32> V(32,
10651 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10653 return DAG.getNode(ISD::AND, dl, VT, SHL,
10654 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10656 if (Op.getOpcode() == ISD::SRL) {
10657 // Make a large shift.
10658 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10659 DAG.getConstant(ShiftAmt, MVT::i32));
10660 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10661 // Zero out the leftmost bits.
10662 SmallVector<SDValue, 32> V(32,
10663 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10665 return DAG.getNode(ISD::AND, dl, VT, SRL,
10666 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10668 if (Op.getOpcode() == ISD::SRA) {
10669 if (ShiftAmt == 7) {
10670 // R s>> 7 === R s< 0
10671 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10672 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10675 // R s>> a === ((R u>> a) ^ m) - m
10676 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10677 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10679 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10680 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10681 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10684 llvm_unreachable("Unknown shift opcode.");
10689 // Lower SHL with variable shift amount.
10690 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10691 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10692 DAG.getConstant(23, MVT::i32));
10694 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10695 Constant *C = ConstantDataVector::get(*Context, CV);
10696 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10697 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10698 MachinePointerInfo::getConstantPool(),
10699 false, false, false, 16);
10701 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10702 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10703 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10704 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10706 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10707 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10710 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10711 DAG.getConstant(5, MVT::i32));
10712 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10714 // Turn 'a' into a mask suitable for VSELECT
10715 SDValue VSelM = DAG.getConstant(0x80, VT);
10716 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10717 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10719 SDValue CM1 = DAG.getConstant(0x0f, VT);
10720 SDValue CM2 = DAG.getConstant(0x3f, VT);
10722 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10723 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10724 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10725 DAG.getConstant(4, MVT::i32), DAG);
10726 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10727 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10730 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10731 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10732 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10734 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10735 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10736 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10737 DAG.getConstant(2, MVT::i32), DAG);
10738 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10739 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10742 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10743 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10744 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10746 // return VSELECT(r, r+r, a);
10747 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10748 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10752 // Decompose 256-bit shifts into smaller 128-bit shifts.
10753 if (VT.is256BitVector()) {
10754 unsigned NumElems = VT.getVectorNumElements();
10755 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10756 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10758 // Extract the two vectors
10759 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10760 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10762 // Recreate the shift amount vectors
10763 SDValue Amt1, Amt2;
10764 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10765 // Constant shift amount
10766 SmallVector<SDValue, 4> Amt1Csts;
10767 SmallVector<SDValue, 4> Amt2Csts;
10768 for (unsigned i = 0; i != NumElems/2; ++i)
10769 Amt1Csts.push_back(Amt->getOperand(i));
10770 for (unsigned i = NumElems/2; i != NumElems; ++i)
10771 Amt2Csts.push_back(Amt->getOperand(i));
10773 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10774 &Amt1Csts[0], NumElems/2);
10775 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10776 &Amt2Csts[0], NumElems/2);
10778 // Variable shift amount
10779 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10780 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10783 // Issue new vector shifts for the smaller types
10784 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10785 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10787 // Concatenate the result back
10788 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10794 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10795 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10796 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10797 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10798 // has only one use.
10799 SDNode *N = Op.getNode();
10800 SDValue LHS = N->getOperand(0);
10801 SDValue RHS = N->getOperand(1);
10802 unsigned BaseOp = 0;
10804 DebugLoc DL = Op.getDebugLoc();
10805 switch (Op.getOpcode()) {
10806 default: llvm_unreachable("Unknown ovf instruction!");
10808 // A subtract of one will be selected as a INC. Note that INC doesn't
10809 // set CF, so we can't do this for UADDO.
10810 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10812 BaseOp = X86ISD::INC;
10813 Cond = X86::COND_O;
10816 BaseOp = X86ISD::ADD;
10817 Cond = X86::COND_O;
10820 BaseOp = X86ISD::ADD;
10821 Cond = X86::COND_B;
10824 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10825 // set CF, so we can't do this for USUBO.
10826 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10828 BaseOp = X86ISD::DEC;
10829 Cond = X86::COND_O;
10832 BaseOp = X86ISD::SUB;
10833 Cond = X86::COND_O;
10836 BaseOp = X86ISD::SUB;
10837 Cond = X86::COND_B;
10840 BaseOp = X86ISD::SMUL;
10841 Cond = X86::COND_O;
10843 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10844 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10846 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10849 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10850 DAG.getConstant(X86::COND_O, MVT::i32),
10851 SDValue(Sum.getNode(), 2));
10853 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10857 // Also sets EFLAGS.
10858 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10859 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10862 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10863 DAG.getConstant(Cond, MVT::i32),
10864 SDValue(Sum.getNode(), 1));
10866 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10869 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10870 SelectionDAG &DAG) const {
10871 DebugLoc dl = Op.getDebugLoc();
10872 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10873 EVT VT = Op.getValueType();
10875 if (!Subtarget->hasSSE2() || !VT.isVector())
10878 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10879 ExtraVT.getScalarType().getSizeInBits();
10880 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10882 switch (VT.getSimpleVT().SimpleTy) {
10883 default: return SDValue();
10886 if (!Subtarget->hasAVX())
10888 if (!Subtarget->hasAVX2()) {
10889 // needs to be split
10890 unsigned NumElems = VT.getVectorNumElements();
10892 // Extract the LHS vectors
10893 SDValue LHS = Op.getOperand(0);
10894 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10895 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10897 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10898 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10900 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10901 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10902 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10904 SDValue Extra = DAG.getValueType(ExtraVT);
10906 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10907 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10909 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10914 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10915 Op.getOperand(0), ShAmt, DAG);
10916 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10922 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10923 DebugLoc dl = Op.getDebugLoc();
10925 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10926 // There isn't any reason to disable it if the target processor supports it.
10927 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10928 SDValue Chain = Op.getOperand(0);
10929 SDValue Zero = DAG.getConstant(0, MVT::i32);
10931 DAG.getRegister(X86::ESP, MVT::i32), // Base
10932 DAG.getTargetConstant(1, MVT::i8), // Scale
10933 DAG.getRegister(0, MVT::i32), // Index
10934 DAG.getTargetConstant(0, MVT::i32), // Disp
10935 DAG.getRegister(0, MVT::i32), // Segment.
10940 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10941 array_lengthof(Ops));
10942 return SDValue(Res, 0);
10945 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10947 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10949 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10950 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10951 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10952 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10954 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10955 if (!Op1 && !Op2 && !Op3 && Op4)
10956 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10958 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10959 if (Op1 && !Op2 && !Op3 && !Op4)
10960 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10962 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10964 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10967 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10968 SelectionDAG &DAG) const {
10969 DebugLoc dl = Op.getDebugLoc();
10970 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10971 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10972 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10973 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10975 // The only fence that needs an instruction is a sequentially-consistent
10976 // cross-thread fence.
10977 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10978 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10979 // no-sse2). There isn't any reason to disable it if the target processor
10981 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10982 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10984 SDValue Chain = Op.getOperand(0);
10985 SDValue Zero = DAG.getConstant(0, MVT::i32);
10987 DAG.getRegister(X86::ESP, MVT::i32), // Base
10988 DAG.getTargetConstant(1, MVT::i8), // Scale
10989 DAG.getRegister(0, MVT::i32), // Index
10990 DAG.getTargetConstant(0, MVT::i32), // Disp
10991 DAG.getRegister(0, MVT::i32), // Segment.
10996 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10997 array_lengthof(Ops));
10998 return SDValue(Res, 0);
11001 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11002 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11006 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
11007 EVT T = Op.getValueType();
11008 DebugLoc DL = Op.getDebugLoc();
11011 switch(T.getSimpleVT().SimpleTy) {
11012 default: llvm_unreachable("Invalid value type!");
11013 case MVT::i8: Reg = X86::AL; size = 1; break;
11014 case MVT::i16: Reg = X86::AX; size = 2; break;
11015 case MVT::i32: Reg = X86::EAX; size = 4; break;
11017 assert(Subtarget->is64Bit() && "Node not type legal!");
11018 Reg = X86::RAX; size = 8;
11021 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11022 Op.getOperand(2), SDValue());
11023 SDValue Ops[] = { cpIn.getValue(0),
11026 DAG.getTargetConstant(size, MVT::i8),
11027 cpIn.getValue(1) };
11028 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11029 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11030 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11033 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11037 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
11038 SelectionDAG &DAG) const {
11039 assert(Subtarget->is64Bit() && "Result not type legalized?");
11040 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11041 SDValue TheChain = Op.getOperand(0);
11042 DebugLoc dl = Op.getDebugLoc();
11043 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11044 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11045 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11047 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11048 DAG.getConstant(32, MVT::i8));
11050 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11053 return DAG.getMergeValues(Ops, 2, dl);
11056 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
11057 SelectionDAG &DAG) const {
11058 EVT SrcVT = Op.getOperand(0).getValueType();
11059 EVT DstVT = Op.getValueType();
11060 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11061 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11062 assert((DstVT == MVT::i64 ||
11063 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11064 "Unexpected custom BITCAST");
11065 // i64 <=> MMX conversions are Legal.
11066 if (SrcVT==MVT::i64 && DstVT.isVector())
11068 if (DstVT==MVT::i64 && SrcVT.isVector())
11070 // MMX <=> MMX conversions are Legal.
11071 if (SrcVT.isVector() && DstVT.isVector())
11073 // All other conversions need to be expanded.
11077 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
11078 SDNode *Node = Op.getNode();
11079 DebugLoc dl = Node->getDebugLoc();
11080 EVT T = Node->getValueType(0);
11081 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11082 DAG.getConstant(0, T), Node->getOperand(2));
11083 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11084 cast<AtomicSDNode>(Node)->getMemoryVT(),
11085 Node->getOperand(0),
11086 Node->getOperand(1), negOp,
11087 cast<AtomicSDNode>(Node)->getSrcValue(),
11088 cast<AtomicSDNode>(Node)->getAlignment(),
11089 cast<AtomicSDNode>(Node)->getOrdering(),
11090 cast<AtomicSDNode>(Node)->getSynchScope());
11093 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11094 SDNode *Node = Op.getNode();
11095 DebugLoc dl = Node->getDebugLoc();
11096 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11098 // Convert seq_cst store -> xchg
11099 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11100 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11101 // (The only way to get a 16-byte store is cmpxchg16b)
11102 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11103 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11104 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11105 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11106 cast<AtomicSDNode>(Node)->getMemoryVT(),
11107 Node->getOperand(0),
11108 Node->getOperand(1), Node->getOperand(2),
11109 cast<AtomicSDNode>(Node)->getMemOperand(),
11110 cast<AtomicSDNode>(Node)->getOrdering(),
11111 cast<AtomicSDNode>(Node)->getSynchScope());
11112 return Swap.getValue(1);
11114 // Other atomic stores have a simple pattern.
11118 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11119 EVT VT = Op.getNode()->getValueType(0);
11121 // Let legalize expand this if it isn't a legal type yet.
11122 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11125 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11128 bool ExtraOp = false;
11129 switch (Op.getOpcode()) {
11130 default: llvm_unreachable("Invalid code");
11131 case ISD::ADDC: Opc = X86ISD::ADD; break;
11132 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11133 case ISD::SUBC: Opc = X86ISD::SUB; break;
11134 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
11138 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11140 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11141 Op.getOperand(1), Op.getOperand(2));
11144 /// LowerOperation - Provide custom lowering hooks for some operations.
11146 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11147 switch (Op.getOpcode()) {
11148 default: llvm_unreachable("Should not custom lower this!");
11149 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
11150 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
11151 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
11152 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
11153 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
11154 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
11155 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
11156 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
11157 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
11158 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
11159 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
11160 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
11161 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
11162 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
11163 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
11164 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
11165 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
11166 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
11167 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
11168 case ISD::SHL_PARTS:
11169 case ISD::SRA_PARTS:
11170 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
11171 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
11172 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
11173 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
11174 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
11175 case ISD::FABS: return LowerFABS(Op, DAG);
11176 case ISD::FNEG: return LowerFNEG(Op, DAG);
11177 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
11178 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
11179 case ISD::SETCC: return LowerSETCC(Op, DAG);
11180 case ISD::SELECT: return LowerSELECT(Op, DAG);
11181 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
11182 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
11183 case ISD::VASTART: return LowerVASTART(Op, DAG);
11184 case ISD::VAARG: return LowerVAARG(Op, DAG);
11185 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
11186 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
11187 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
11188 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
11189 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
11190 case ISD::FRAME_TO_ARGS_OFFSET:
11191 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
11192 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
11193 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
11194 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
11195 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
11196 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
11197 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
11198 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
11199 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
11200 case ISD::MUL: return LowerMUL(Op, DAG);
11203 case ISD::SHL: return LowerShift(Op, DAG);
11209 case ISD::UMULO: return LowerXALUO(Op, DAG);
11210 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
11211 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11215 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11216 case ISD::ADD: return LowerADD(Op, DAG);
11217 case ISD::SUB: return LowerSUB(Op, DAG);
11221 static void ReplaceATOMIC_LOAD(SDNode *Node,
11222 SmallVectorImpl<SDValue> &Results,
11223 SelectionDAG &DAG) {
11224 DebugLoc dl = Node->getDebugLoc();
11225 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11227 // Convert wide load -> cmpxchg8b/cmpxchg16b
11228 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11229 // (The only way to get a 16-byte load is cmpxchg16b)
11230 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11231 SDValue Zero = DAG.getConstant(0, VT);
11232 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11233 Node->getOperand(0),
11234 Node->getOperand(1), Zero, Zero,
11235 cast<AtomicSDNode>(Node)->getMemOperand(),
11236 cast<AtomicSDNode>(Node)->getOrdering(),
11237 cast<AtomicSDNode>(Node)->getSynchScope());
11238 Results.push_back(Swap.getValue(0));
11239 Results.push_back(Swap.getValue(1));
11243 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11244 SelectionDAG &DAG, unsigned NewOp) {
11245 DebugLoc dl = Node->getDebugLoc();
11246 assert (Node->getValueType(0) == MVT::i64 &&
11247 "Only know how to expand i64 atomics");
11249 SDValue Chain = Node->getOperand(0);
11250 SDValue In1 = Node->getOperand(1);
11251 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11252 Node->getOperand(2), DAG.getIntPtrConstant(0));
11253 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11254 Node->getOperand(2), DAG.getIntPtrConstant(1));
11255 SDValue Ops[] = { Chain, In1, In2L, In2H };
11256 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11258 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11259 cast<MemSDNode>(Node)->getMemOperand());
11260 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11261 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11262 Results.push_back(Result.getValue(2));
11265 /// ReplaceNodeResults - Replace a node with an illegal result type
11266 /// with a new node built out of custom code.
11267 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11268 SmallVectorImpl<SDValue>&Results,
11269 SelectionDAG &DAG) const {
11270 DebugLoc dl = N->getDebugLoc();
11271 switch (N->getOpcode()) {
11273 llvm_unreachable("Do not know how to custom type legalize this operation!");
11274 case ISD::SIGN_EXTEND_INREG:
11279 // We don't want to expand or promote these.
11281 case ISD::FP_TO_SINT:
11282 case ISD::FP_TO_UINT: {
11283 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11285 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11288 std::pair<SDValue,SDValue> Vals =
11289 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11290 SDValue FIST = Vals.first, StackSlot = Vals.second;
11291 if (FIST.getNode() != 0) {
11292 EVT VT = N->getValueType(0);
11293 // Return a load from the stack slot.
11294 if (StackSlot.getNode() != 0)
11295 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11296 MachinePointerInfo(),
11297 false, false, false, 0));
11299 Results.push_back(FIST);
11303 case ISD::READCYCLECOUNTER: {
11304 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11305 SDValue TheChain = N->getOperand(0);
11306 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11307 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11309 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11311 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11312 SDValue Ops[] = { eax, edx };
11313 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11314 Results.push_back(edx.getValue(1));
11317 case ISD::ATOMIC_CMP_SWAP: {
11318 EVT T = N->getValueType(0);
11319 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11320 bool Regs64bit = T == MVT::i128;
11321 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11322 SDValue cpInL, cpInH;
11323 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11324 DAG.getConstant(0, HalfT));
11325 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11326 DAG.getConstant(1, HalfT));
11327 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11328 Regs64bit ? X86::RAX : X86::EAX,
11330 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11331 Regs64bit ? X86::RDX : X86::EDX,
11332 cpInH, cpInL.getValue(1));
11333 SDValue swapInL, swapInH;
11334 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11335 DAG.getConstant(0, HalfT));
11336 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11337 DAG.getConstant(1, HalfT));
11338 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11339 Regs64bit ? X86::RBX : X86::EBX,
11340 swapInL, cpInH.getValue(1));
11341 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11342 Regs64bit ? X86::RCX : X86::ECX,
11343 swapInH, swapInL.getValue(1));
11344 SDValue Ops[] = { swapInH.getValue(0),
11346 swapInH.getValue(1) };
11347 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11348 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11349 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11350 X86ISD::LCMPXCHG8_DAG;
11351 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11353 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11354 Regs64bit ? X86::RAX : X86::EAX,
11355 HalfT, Result.getValue(1));
11356 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11357 Regs64bit ? X86::RDX : X86::EDX,
11358 HalfT, cpOutL.getValue(2));
11359 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11360 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11361 Results.push_back(cpOutH.getValue(1));
11364 case ISD::ATOMIC_LOAD_ADD:
11365 case ISD::ATOMIC_LOAD_AND:
11366 case ISD::ATOMIC_LOAD_NAND:
11367 case ISD::ATOMIC_LOAD_OR:
11368 case ISD::ATOMIC_LOAD_SUB:
11369 case ISD::ATOMIC_LOAD_XOR:
11370 case ISD::ATOMIC_SWAP: {
11372 switch (N->getOpcode()) {
11373 default: llvm_unreachable("Unexpected opcode");
11374 case ISD::ATOMIC_LOAD_ADD:
11375 Opc = X86ISD::ATOMADD64_DAG;
11377 case ISD::ATOMIC_LOAD_AND:
11378 Opc = X86ISD::ATOMAND64_DAG;
11380 case ISD::ATOMIC_LOAD_NAND:
11381 Opc = X86ISD::ATOMNAND64_DAG;
11383 case ISD::ATOMIC_LOAD_OR:
11384 Opc = X86ISD::ATOMOR64_DAG;
11386 case ISD::ATOMIC_LOAD_SUB:
11387 Opc = X86ISD::ATOMSUB64_DAG;
11389 case ISD::ATOMIC_LOAD_XOR:
11390 Opc = X86ISD::ATOMXOR64_DAG;
11392 case ISD::ATOMIC_SWAP:
11393 Opc = X86ISD::ATOMSWAP64_DAG;
11396 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
11399 case ISD::ATOMIC_LOAD:
11400 ReplaceATOMIC_LOAD(N, Results, DAG);
11404 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11406 default: return NULL;
11407 case X86ISD::BSF: return "X86ISD::BSF";
11408 case X86ISD::BSR: return "X86ISD::BSR";
11409 case X86ISD::SHLD: return "X86ISD::SHLD";
11410 case X86ISD::SHRD: return "X86ISD::SHRD";
11411 case X86ISD::FAND: return "X86ISD::FAND";
11412 case X86ISD::FOR: return "X86ISD::FOR";
11413 case X86ISD::FXOR: return "X86ISD::FXOR";
11414 case X86ISD::FSRL: return "X86ISD::FSRL";
11415 case X86ISD::FILD: return "X86ISD::FILD";
11416 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11417 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11418 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11419 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11420 case X86ISD::FLD: return "X86ISD::FLD";
11421 case X86ISD::FST: return "X86ISD::FST";
11422 case X86ISD::CALL: return "X86ISD::CALL";
11423 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11424 case X86ISD::BT: return "X86ISD::BT";
11425 case X86ISD::CMP: return "X86ISD::CMP";
11426 case X86ISD::COMI: return "X86ISD::COMI";
11427 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11428 case X86ISD::SETCC: return "X86ISD::SETCC";
11429 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11430 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11431 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11432 case X86ISD::CMOV: return "X86ISD::CMOV";
11433 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11434 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11435 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11436 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11437 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11438 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11439 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11440 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11441 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11442 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11443 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11444 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11445 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11446 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11447 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11448 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11449 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11450 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11451 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11452 case X86ISD::HADD: return "X86ISD::HADD";
11453 case X86ISD::HSUB: return "X86ISD::HSUB";
11454 case X86ISD::FHADD: return "X86ISD::FHADD";
11455 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11456 case X86ISD::FMAX: return "X86ISD::FMAX";
11457 case X86ISD::FMIN: return "X86ISD::FMIN";
11458 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11459 case X86ISD::FRCP: return "X86ISD::FRCP";
11460 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11461 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11462 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11463 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11464 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11465 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11466 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11467 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11468 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11469 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11470 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11471 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11472 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11473 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11474 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11475 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11476 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
11477 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11478 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
11479 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11480 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11481 case X86ISD::VSHL: return "X86ISD::VSHL";
11482 case X86ISD::VSRL: return "X86ISD::VSRL";
11483 case X86ISD::VSRA: return "X86ISD::VSRA";
11484 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11485 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11486 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11487 case X86ISD::CMPP: return "X86ISD::CMPP";
11488 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11489 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11490 case X86ISD::ADD: return "X86ISD::ADD";
11491 case X86ISD::SUB: return "X86ISD::SUB";
11492 case X86ISD::ADC: return "X86ISD::ADC";
11493 case X86ISD::SBB: return "X86ISD::SBB";
11494 case X86ISD::SMUL: return "X86ISD::SMUL";
11495 case X86ISD::UMUL: return "X86ISD::UMUL";
11496 case X86ISD::INC: return "X86ISD::INC";
11497 case X86ISD::DEC: return "X86ISD::DEC";
11498 case X86ISD::OR: return "X86ISD::OR";
11499 case X86ISD::XOR: return "X86ISD::XOR";
11500 case X86ISD::AND: return "X86ISD::AND";
11501 case X86ISD::ANDN: return "X86ISD::ANDN";
11502 case X86ISD::BLSI: return "X86ISD::BLSI";
11503 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11504 case X86ISD::BLSR: return "X86ISD::BLSR";
11505 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11506 case X86ISD::PTEST: return "X86ISD::PTEST";
11507 case X86ISD::TESTP: return "X86ISD::TESTP";
11508 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11509 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11510 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11511 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11512 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11513 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11514 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11515 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11516 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11517 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11518 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11519 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11520 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11521 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11522 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11523 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11524 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11525 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11526 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11527 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11528 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11529 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11530 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11531 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11532 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11533 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11534 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11535 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11536 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11537 case X86ISD::SAHF: return "X86ISD::SAHF";
11538 case X86ISD::RDRAND: return "X86ISD::RDRAND";
11539 case X86ISD::FMADD: return "X86ISD::FMADD";
11540 case X86ISD::FMSUB: return "X86ISD::FMSUB";
11541 case X86ISD::FNMADD: return "X86ISD::FNMADD";
11542 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
11543 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
11544 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
11548 // isLegalAddressingMode - Return true if the addressing mode represented
11549 // by AM is legal for this target, for a load/store of the specified type.
11550 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11552 // X86 supports extremely general addressing modes.
11553 CodeModel::Model M = getTargetMachine().getCodeModel();
11554 Reloc::Model R = getTargetMachine().getRelocationModel();
11556 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11557 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11562 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11564 // If a reference to this global requires an extra load, we can't fold it.
11565 if (isGlobalStubReference(GVFlags))
11568 // If BaseGV requires a register for the PIC base, we cannot also have a
11569 // BaseReg specified.
11570 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11573 // If lower 4G is not available, then we must use rip-relative addressing.
11574 if ((M != CodeModel::Small || R != Reloc::Static) &&
11575 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11579 switch (AM.Scale) {
11585 // These scales always work.
11590 // These scales are formed with basereg+scalereg. Only accept if there is
11595 default: // Other stuff never works.
11603 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11604 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11606 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11607 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11608 if (NumBits1 <= NumBits2)
11613 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11614 return Imm == (int32_t)Imm;
11617 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
11618 // Can also use sub to handle negated immediates.
11619 return Imm == (int32_t)Imm;
11622 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11623 if (!VT1.isInteger() || !VT2.isInteger())
11625 unsigned NumBits1 = VT1.getSizeInBits();
11626 unsigned NumBits2 = VT2.getSizeInBits();
11627 if (NumBits1 <= NumBits2)
11632 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11633 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11634 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11637 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11638 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11639 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11642 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11643 // i16 instructions are longer (0x66 prefix) and potentially slower.
11644 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11647 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11648 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11649 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11650 /// are assumed to be legal.
11652 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11654 // Very little shuffling can be done for 64-bit vectors right now.
11655 if (VT.getSizeInBits() == 64)
11658 // FIXME: pshufb, blends, shifts.
11659 return (VT.getVectorNumElements() == 2 ||
11660 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11661 isMOVLMask(M, VT) ||
11662 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11663 isPSHUFDMask(M, VT) ||
11664 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11665 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11666 isPALIGNRMask(M, VT, Subtarget) ||
11667 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11668 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11669 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11670 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11674 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11676 unsigned NumElts = VT.getVectorNumElements();
11677 // FIXME: This collection of masks seems suspect.
11680 if (NumElts == 4 && VT.is128BitVector()) {
11681 return (isMOVLMask(Mask, VT) ||
11682 isCommutedMOVLMask(Mask, VT, true) ||
11683 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11684 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11689 //===----------------------------------------------------------------------===//
11690 // X86 Scheduler Hooks
11691 //===----------------------------------------------------------------------===//
11693 // private utility function
11694 MachineBasicBlock *
11695 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11696 MachineBasicBlock *MBB,
11703 const TargetRegisterClass *RC,
11704 bool Invert) const {
11705 // For the atomic bitwise operator, we generate
11708 // ld t1 = [bitinstr.addr]
11709 // op t2 = t1, [bitinstr.val]
11710 // not t3 = t2 (if Invert)
11712 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11714 // fallthrough -->nextMBB
11715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11716 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11717 MachineFunction::iterator MBBIter = MBB;
11720 /// First build the CFG
11721 MachineFunction *F = MBB->getParent();
11722 MachineBasicBlock *thisMBB = MBB;
11723 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11724 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11725 F->insert(MBBIter, newMBB);
11726 F->insert(MBBIter, nextMBB);
11728 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11729 nextMBB->splice(nextMBB->begin(), thisMBB,
11730 llvm::next(MachineBasicBlock::iterator(bInstr)),
11732 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11734 // Update thisMBB to fall through to newMBB
11735 thisMBB->addSuccessor(newMBB);
11737 // newMBB jumps to itself and fall through to nextMBB
11738 newMBB->addSuccessor(nextMBB);
11739 newMBB->addSuccessor(newMBB);
11741 // Insert instructions into newMBB based on incoming instruction
11742 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11743 "unexpected number of operands");
11744 DebugLoc dl = bInstr->getDebugLoc();
11745 MachineOperand& destOper = bInstr->getOperand(0);
11746 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11747 int numArgs = bInstr->getNumOperands() - 1;
11748 for (int i=0; i < numArgs; ++i)
11749 argOpers[i] = &bInstr->getOperand(i+1);
11751 // x86 address has 4 operands: base, index, scale, and displacement
11752 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11753 int valArgIndx = lastAddrIndx + 1;
11755 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11756 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11757 for (int i=0; i <= lastAddrIndx; ++i)
11758 (*MIB).addOperand(*argOpers[i]);
11760 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11761 assert((argOpers[valArgIndx]->isReg() ||
11762 argOpers[valArgIndx]->isImm()) &&
11763 "invalid operand");
11764 if (argOpers[valArgIndx]->isReg())
11765 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11767 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11769 (*MIB).addOperand(*argOpers[valArgIndx]);
11771 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11773 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11778 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11781 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11782 for (int i=0; i <= lastAddrIndx; ++i)
11783 (*MIB).addOperand(*argOpers[i]);
11785 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11786 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11787 bInstr->memoperands_end());
11789 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11790 MIB.addReg(EAXreg);
11793 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11795 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11799 // private utility function: 64 bit atomics on 32 bit host.
11800 MachineBasicBlock *
11801 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11802 MachineBasicBlock *MBB,
11807 bool Invert) const {
11808 // For the atomic bitwise operator, we generate
11809 // thisMBB (instructions are in pairs, except cmpxchg8b)
11810 // ld t1,t2 = [bitinstr.addr]
11812 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11813 // op t5, t6 <- out1, out2, [bitinstr.val]
11814 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11815 // neg t7, t8 < t5, t6 (if Invert)
11816 // mov ECX, EBX <- t5, t6
11817 // mov EAX, EDX <- t1, t2
11818 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11819 // mov t3, t4 <- EAX, EDX
11821 // result in out1, out2
11822 // fallthrough -->nextMBB
11824 const TargetRegisterClass *RC = &X86::GR32RegClass;
11825 const unsigned LoadOpc = X86::MOV32rm;
11826 const unsigned NotOpc = X86::NOT32r;
11827 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11828 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11829 MachineFunction::iterator MBBIter = MBB;
11832 /// First build the CFG
11833 MachineFunction *F = MBB->getParent();
11834 MachineBasicBlock *thisMBB = MBB;
11835 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11836 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11837 F->insert(MBBIter, newMBB);
11838 F->insert(MBBIter, nextMBB);
11840 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11841 nextMBB->splice(nextMBB->begin(), thisMBB,
11842 llvm::next(MachineBasicBlock::iterator(bInstr)),
11844 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11846 // Update thisMBB to fall through to newMBB
11847 thisMBB->addSuccessor(newMBB);
11849 // newMBB jumps to itself and fall through to nextMBB
11850 newMBB->addSuccessor(nextMBB);
11851 newMBB->addSuccessor(newMBB);
11853 DebugLoc dl = bInstr->getDebugLoc();
11854 // Insert instructions into newMBB based on incoming instruction
11855 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11856 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11857 "unexpected number of operands");
11858 MachineOperand& dest1Oper = bInstr->getOperand(0);
11859 MachineOperand& dest2Oper = bInstr->getOperand(1);
11860 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11861 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11862 argOpers[i] = &bInstr->getOperand(i+2);
11864 // We use some of the operands multiple times, so conservatively just
11865 // clear any kill flags that might be present.
11866 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11867 argOpers[i]->setIsKill(false);
11870 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11871 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11873 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11874 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11875 for (int i=0; i <= lastAddrIndx; ++i)
11876 (*MIB).addOperand(*argOpers[i]);
11877 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11878 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11879 // add 4 to displacement.
11880 for (int i=0; i <= lastAddrIndx-2; ++i)
11881 (*MIB).addOperand(*argOpers[i]);
11882 MachineOperand newOp3 = *(argOpers[3]);
11883 if (newOp3.isImm())
11884 newOp3.setImm(newOp3.getImm()+4);
11886 newOp3.setOffset(newOp3.getOffset()+4);
11887 (*MIB).addOperand(newOp3);
11888 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11890 // t3/4 are defined later, at the bottom of the loop
11891 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11892 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11893 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11894 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11895 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11896 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11898 // The subsequent operations should be using the destination registers of
11899 // the PHI instructions.
11900 t1 = dest1Oper.getReg();
11901 t2 = dest2Oper.getReg();
11903 int valArgIndx = lastAddrIndx + 1;
11904 assert((argOpers[valArgIndx]->isReg() ||
11905 argOpers[valArgIndx]->isImm()) &&
11906 "invalid operand");
11907 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11908 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11909 if (argOpers[valArgIndx]->isReg())
11910 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11912 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11913 if (regOpcL != X86::MOV32rr)
11915 (*MIB).addOperand(*argOpers[valArgIndx]);
11916 assert(argOpers[valArgIndx + 1]->isReg() ==
11917 argOpers[valArgIndx]->isReg());
11918 assert(argOpers[valArgIndx + 1]->isImm() ==
11919 argOpers[valArgIndx]->isImm());
11920 if (argOpers[valArgIndx + 1]->isReg())
11921 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11923 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11924 if (regOpcH != X86::MOV32rr)
11926 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11930 t7 = F->getRegInfo().createVirtualRegister(RC);
11931 t8 = F->getRegInfo().createVirtualRegister(RC);
11932 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11933 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11939 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11941 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11944 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11946 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11949 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11950 for (int i=0; i <= lastAddrIndx; ++i)
11951 (*MIB).addOperand(*argOpers[i]);
11953 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11954 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11955 bInstr->memoperands_end());
11957 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11958 MIB.addReg(X86::EAX);
11959 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11960 MIB.addReg(X86::EDX);
11963 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11965 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11969 // private utility function
11970 MachineBasicBlock *
11971 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11972 MachineBasicBlock *MBB,
11973 unsigned cmovOpc) const {
11974 // For the atomic min/max operator, we generate
11977 // ld t1 = [min/max.addr]
11978 // mov t2 = [min/max.val]
11980 // cmov[cond] t2 = t1
11982 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11984 // fallthrough -->nextMBB
11986 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11987 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11988 MachineFunction::iterator MBBIter = MBB;
11991 /// First build the CFG
11992 MachineFunction *F = MBB->getParent();
11993 MachineBasicBlock *thisMBB = MBB;
11994 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11995 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11996 F->insert(MBBIter, newMBB);
11997 F->insert(MBBIter, nextMBB);
11999 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
12000 nextMBB->splice(nextMBB->begin(), thisMBB,
12001 llvm::next(MachineBasicBlock::iterator(mInstr)),
12003 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12005 // Update thisMBB to fall through to newMBB
12006 thisMBB->addSuccessor(newMBB);
12008 // newMBB jumps to newMBB and fall through to nextMBB
12009 newMBB->addSuccessor(nextMBB);
12010 newMBB->addSuccessor(newMBB);
12012 DebugLoc dl = mInstr->getDebugLoc();
12013 // Insert instructions into newMBB based on incoming instruction
12014 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
12015 "unexpected number of operands");
12016 MachineOperand& destOper = mInstr->getOperand(0);
12017 MachineOperand* argOpers[2 + X86::AddrNumOperands];
12018 int numArgs = mInstr->getNumOperands() - 1;
12019 for (int i=0; i < numArgs; ++i)
12020 argOpers[i] = &mInstr->getOperand(i+1);
12022 // x86 address has 4 operands: base, index, scale, and displacement
12023 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
12024 int valArgIndx = lastAddrIndx + 1;
12026 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
12027 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
12028 for (int i=0; i <= lastAddrIndx; ++i)
12029 (*MIB).addOperand(*argOpers[i]);
12031 // We only support register and immediate values
12032 assert((argOpers[valArgIndx]->isReg() ||
12033 argOpers[valArgIndx]->isImm()) &&
12034 "invalid operand");
12036 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
12037 if (argOpers[valArgIndx]->isReg())
12038 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
12040 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
12041 (*MIB).addOperand(*argOpers[valArgIndx]);
12043 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
12046 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
12051 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
12052 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
12056 // Cmp and exchange if none has modified the memory location
12057 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
12058 for (int i=0; i <= lastAddrIndx; ++i)
12059 (*MIB).addOperand(*argOpers[i]);
12061 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
12062 (*MIB).setMemRefs(mInstr->memoperands_begin(),
12063 mInstr->memoperands_end());
12065 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
12066 MIB.addReg(X86::EAX);
12069 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
12071 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
12075 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
12076 // or XMM0_V32I8 in AVX all of this code can be replaced with that
12077 // in the .td file.
12078 MachineBasicBlock *
12079 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
12080 unsigned numArgs, bool memArg) const {
12081 assert(Subtarget->hasSSE42() &&
12082 "Target must have SSE4.2 or AVX features enabled");
12084 DebugLoc dl = MI->getDebugLoc();
12085 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12087 if (!Subtarget->hasAVX()) {
12089 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
12091 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
12094 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
12096 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
12099 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12100 for (unsigned i = 0; i < numArgs; ++i) {
12101 MachineOperand &Op = MI->getOperand(i+1);
12102 if (!(Op.isReg() && Op.isImplicit()))
12103 MIB.addOperand(Op);
12105 BuildMI(*BB, MI, dl,
12106 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12107 .addReg(X86::XMM0);
12109 MI->eraseFromParent();
12113 MachineBasicBlock *
12114 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
12115 DebugLoc dl = MI->getDebugLoc();
12116 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12118 // Address into RAX/EAX, other two args into ECX, EDX.
12119 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
12120 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12121 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
12122 for (int i = 0; i < X86::AddrNumOperands; ++i)
12123 MIB.addOperand(MI->getOperand(i));
12125 unsigned ValOps = X86::AddrNumOperands;
12126 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
12127 .addReg(MI->getOperand(ValOps).getReg());
12128 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
12129 .addReg(MI->getOperand(ValOps+1).getReg());
12131 // The instruction doesn't actually take any operands though.
12132 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
12134 MI->eraseFromParent(); // The pseudo is gone now.
12138 MachineBasicBlock *
12139 X86TargetLowering::EmitVAARG64WithCustomInserter(
12141 MachineBasicBlock *MBB) const {
12142 // Emit va_arg instruction on X86-64.
12144 // Operands to this pseudo-instruction:
12145 // 0 ) Output : destination address (reg)
12146 // 1-5) Input : va_list address (addr, i64mem)
12147 // 6 ) ArgSize : Size (in bytes) of vararg type
12148 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
12149 // 8 ) Align : Alignment of type
12150 // 9 ) EFLAGS (implicit-def)
12152 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
12153 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
12155 unsigned DestReg = MI->getOperand(0).getReg();
12156 MachineOperand &Base = MI->getOperand(1);
12157 MachineOperand &Scale = MI->getOperand(2);
12158 MachineOperand &Index = MI->getOperand(3);
12159 MachineOperand &Disp = MI->getOperand(4);
12160 MachineOperand &Segment = MI->getOperand(5);
12161 unsigned ArgSize = MI->getOperand(6).getImm();
12162 unsigned ArgMode = MI->getOperand(7).getImm();
12163 unsigned Align = MI->getOperand(8).getImm();
12165 // Memory Reference
12166 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
12167 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12168 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12170 // Machine Information
12171 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12172 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
12173 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
12174 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
12175 DebugLoc DL = MI->getDebugLoc();
12177 // struct va_list {
12180 // i64 overflow_area (address)
12181 // i64 reg_save_area (address)
12183 // sizeof(va_list) = 24
12184 // alignment(va_list) = 8
12186 unsigned TotalNumIntRegs = 6;
12187 unsigned TotalNumXMMRegs = 8;
12188 bool UseGPOffset = (ArgMode == 1);
12189 bool UseFPOffset = (ArgMode == 2);
12190 unsigned MaxOffset = TotalNumIntRegs * 8 +
12191 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
12193 /* Align ArgSize to a multiple of 8 */
12194 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
12195 bool NeedsAlign = (Align > 8);
12197 MachineBasicBlock *thisMBB = MBB;
12198 MachineBasicBlock *overflowMBB;
12199 MachineBasicBlock *offsetMBB;
12200 MachineBasicBlock *endMBB;
12202 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
12203 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
12204 unsigned OffsetReg = 0;
12206 if (!UseGPOffset && !UseFPOffset) {
12207 // If we only pull from the overflow region, we don't create a branch.
12208 // We don't need to alter control flow.
12209 OffsetDestReg = 0; // unused
12210 OverflowDestReg = DestReg;
12213 overflowMBB = thisMBB;
12216 // First emit code to check if gp_offset (or fp_offset) is below the bound.
12217 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
12218 // If not, pull from overflow_area. (branch to overflowMBB)
12223 // offsetMBB overflowMBB
12228 // Registers for the PHI in endMBB
12229 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
12230 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
12232 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12233 MachineFunction *MF = MBB->getParent();
12234 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12235 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12236 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12238 MachineFunction::iterator MBBIter = MBB;
12241 // Insert the new basic blocks
12242 MF->insert(MBBIter, offsetMBB);
12243 MF->insert(MBBIter, overflowMBB);
12244 MF->insert(MBBIter, endMBB);
12246 // Transfer the remainder of MBB and its successor edges to endMBB.
12247 endMBB->splice(endMBB->begin(), thisMBB,
12248 llvm::next(MachineBasicBlock::iterator(MI)),
12250 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12252 // Make offsetMBB and overflowMBB successors of thisMBB
12253 thisMBB->addSuccessor(offsetMBB);
12254 thisMBB->addSuccessor(overflowMBB);
12256 // endMBB is a successor of both offsetMBB and overflowMBB
12257 offsetMBB->addSuccessor(endMBB);
12258 overflowMBB->addSuccessor(endMBB);
12260 // Load the offset value into a register
12261 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12262 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12266 .addDisp(Disp, UseFPOffset ? 4 : 0)
12267 .addOperand(Segment)
12268 .setMemRefs(MMOBegin, MMOEnd);
12270 // Check if there is enough room left to pull this argument.
12271 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12273 .addImm(MaxOffset + 8 - ArgSizeA8);
12275 // Branch to "overflowMBB" if offset >= max
12276 // Fall through to "offsetMBB" otherwise
12277 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12278 .addMBB(overflowMBB);
12281 // In offsetMBB, emit code to use the reg_save_area.
12283 assert(OffsetReg != 0);
12285 // Read the reg_save_area address.
12286 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12287 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12292 .addOperand(Segment)
12293 .setMemRefs(MMOBegin, MMOEnd);
12295 // Zero-extend the offset
12296 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12297 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12300 .addImm(X86::sub_32bit);
12302 // Add the offset to the reg_save_area to get the final address.
12303 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12304 .addReg(OffsetReg64)
12305 .addReg(RegSaveReg);
12307 // Compute the offset for the next argument
12308 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12309 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12311 .addImm(UseFPOffset ? 16 : 8);
12313 // Store it back into the va_list.
12314 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12318 .addDisp(Disp, UseFPOffset ? 4 : 0)
12319 .addOperand(Segment)
12320 .addReg(NextOffsetReg)
12321 .setMemRefs(MMOBegin, MMOEnd);
12324 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12329 // Emit code to use overflow area
12332 // Load the overflow_area address into a register.
12333 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12334 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12339 .addOperand(Segment)
12340 .setMemRefs(MMOBegin, MMOEnd);
12342 // If we need to align it, do so. Otherwise, just copy the address
12343 // to OverflowDestReg.
12345 // Align the overflow address
12346 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12347 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12349 // aligned_addr = (addr + (align-1)) & ~(align-1)
12350 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12351 .addReg(OverflowAddrReg)
12354 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12356 .addImm(~(uint64_t)(Align-1));
12358 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12359 .addReg(OverflowAddrReg);
12362 // Compute the next overflow address after this argument.
12363 // (the overflow address should be kept 8-byte aligned)
12364 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12365 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12366 .addReg(OverflowDestReg)
12367 .addImm(ArgSizeA8);
12369 // Store the new overflow address.
12370 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12375 .addOperand(Segment)
12376 .addReg(NextAddrReg)
12377 .setMemRefs(MMOBegin, MMOEnd);
12379 // If we branched, emit the PHI to the front of endMBB.
12381 BuildMI(*endMBB, endMBB->begin(), DL,
12382 TII->get(X86::PHI), DestReg)
12383 .addReg(OffsetDestReg).addMBB(offsetMBB)
12384 .addReg(OverflowDestReg).addMBB(overflowMBB);
12387 // Erase the pseudo instruction
12388 MI->eraseFromParent();
12393 MachineBasicBlock *
12394 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12396 MachineBasicBlock *MBB) const {
12397 // Emit code to save XMM registers to the stack. The ABI says that the
12398 // number of registers to save is given in %al, so it's theoretically
12399 // possible to do an indirect jump trick to avoid saving all of them,
12400 // however this code takes a simpler approach and just executes all
12401 // of the stores if %al is non-zero. It's less code, and it's probably
12402 // easier on the hardware branch predictor, and stores aren't all that
12403 // expensive anyway.
12405 // Create the new basic blocks. One block contains all the XMM stores,
12406 // and one block is the final destination regardless of whether any
12407 // stores were performed.
12408 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12409 MachineFunction *F = MBB->getParent();
12410 MachineFunction::iterator MBBIter = MBB;
12412 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12413 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12414 F->insert(MBBIter, XMMSaveMBB);
12415 F->insert(MBBIter, EndMBB);
12417 // Transfer the remainder of MBB and its successor edges to EndMBB.
12418 EndMBB->splice(EndMBB->begin(), MBB,
12419 llvm::next(MachineBasicBlock::iterator(MI)),
12421 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12423 // The original block will now fall through to the XMM save block.
12424 MBB->addSuccessor(XMMSaveMBB);
12425 // The XMMSaveMBB will fall through to the end block.
12426 XMMSaveMBB->addSuccessor(EndMBB);
12428 // Now add the instructions.
12429 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12430 DebugLoc DL = MI->getDebugLoc();
12432 unsigned CountReg = MI->getOperand(0).getReg();
12433 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12434 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12436 if (!Subtarget->isTargetWin64()) {
12437 // If %al is 0, branch around the XMM save block.
12438 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12439 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12440 MBB->addSuccessor(EndMBB);
12443 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12444 // In the XMM save block, save all the XMM argument registers.
12445 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12446 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12447 MachineMemOperand *MMO =
12448 F->getMachineMemOperand(
12449 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12450 MachineMemOperand::MOStore,
12451 /*Size=*/16, /*Align=*/16);
12452 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12453 .addFrameIndex(RegSaveFrameIndex)
12454 .addImm(/*Scale=*/1)
12455 .addReg(/*IndexReg=*/0)
12456 .addImm(/*Disp=*/Offset)
12457 .addReg(/*Segment=*/0)
12458 .addReg(MI->getOperand(i).getReg())
12459 .addMemOperand(MMO);
12462 MI->eraseFromParent(); // The pseudo instruction is gone now.
12467 // The EFLAGS operand of SelectItr might be missing a kill marker
12468 // because there were multiple uses of EFLAGS, and ISel didn't know
12469 // which to mark. Figure out whether SelectItr should have had a
12470 // kill marker, and set it if it should. Returns the correct kill
12472 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12473 MachineBasicBlock* BB,
12474 const TargetRegisterInfo* TRI) {
12475 // Scan forward through BB for a use/def of EFLAGS.
12476 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12477 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12478 const MachineInstr& mi = *miI;
12479 if (mi.readsRegister(X86::EFLAGS))
12481 if (mi.definesRegister(X86::EFLAGS))
12482 break; // Should have kill-flag - update below.
12485 // If we hit the end of the block, check whether EFLAGS is live into a
12487 if (miI == BB->end()) {
12488 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12489 sEnd = BB->succ_end();
12490 sItr != sEnd; ++sItr) {
12491 MachineBasicBlock* succ = *sItr;
12492 if (succ->isLiveIn(X86::EFLAGS))
12497 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12498 // out. SelectMI should have a kill flag on EFLAGS.
12499 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12503 MachineBasicBlock *
12504 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12505 MachineBasicBlock *BB) const {
12506 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12507 DebugLoc DL = MI->getDebugLoc();
12509 // To "insert" a SELECT_CC instruction, we actually have to insert the
12510 // diamond control-flow pattern. The incoming instruction knows the
12511 // destination vreg to set, the condition code register to branch on, the
12512 // true/false values to select between, and a branch opcode to use.
12513 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12514 MachineFunction::iterator It = BB;
12520 // cmpTY ccX, r1, r2
12522 // fallthrough --> copy0MBB
12523 MachineBasicBlock *thisMBB = BB;
12524 MachineFunction *F = BB->getParent();
12525 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12526 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12527 F->insert(It, copy0MBB);
12528 F->insert(It, sinkMBB);
12530 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12531 // live into the sink and copy blocks.
12532 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12533 if (!MI->killsRegister(X86::EFLAGS) &&
12534 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12535 copy0MBB->addLiveIn(X86::EFLAGS);
12536 sinkMBB->addLiveIn(X86::EFLAGS);
12539 // Transfer the remainder of BB and its successor edges to sinkMBB.
12540 sinkMBB->splice(sinkMBB->begin(), BB,
12541 llvm::next(MachineBasicBlock::iterator(MI)),
12543 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12545 // Add the true and fallthrough blocks as its successors.
12546 BB->addSuccessor(copy0MBB);
12547 BB->addSuccessor(sinkMBB);
12549 // Create the conditional branch instruction.
12551 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12552 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12555 // %FalseValue = ...
12556 // # fallthrough to sinkMBB
12557 copy0MBB->addSuccessor(sinkMBB);
12560 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12562 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12563 TII->get(X86::PHI), MI->getOperand(0).getReg())
12564 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12565 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12567 MI->eraseFromParent(); // The pseudo instruction is gone now.
12571 MachineBasicBlock *
12572 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12573 bool Is64Bit) const {
12574 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12575 DebugLoc DL = MI->getDebugLoc();
12576 MachineFunction *MF = BB->getParent();
12577 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12579 assert(getTargetMachine().Options.EnableSegmentedStacks);
12581 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12582 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12585 // ... [Till the alloca]
12586 // If stacklet is not large enough, jump to mallocMBB
12589 // Allocate by subtracting from RSP
12590 // Jump to continueMBB
12593 // Allocate by call to runtime
12597 // [rest of original BB]
12600 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12601 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12602 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12604 MachineRegisterInfo &MRI = MF->getRegInfo();
12605 const TargetRegisterClass *AddrRegClass =
12606 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12608 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12609 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12610 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12611 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12612 sizeVReg = MI->getOperand(1).getReg(),
12613 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12615 MachineFunction::iterator MBBIter = BB;
12618 MF->insert(MBBIter, bumpMBB);
12619 MF->insert(MBBIter, mallocMBB);
12620 MF->insert(MBBIter, continueMBB);
12622 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12623 (MachineBasicBlock::iterator(MI)), BB->end());
12624 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12626 // Add code to the main basic block to check if the stack limit has been hit,
12627 // and if so, jump to mallocMBB otherwise to bumpMBB.
12628 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12629 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12630 .addReg(tmpSPVReg).addReg(sizeVReg);
12631 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12632 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12633 .addReg(SPLimitVReg);
12634 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12636 // bumpMBB simply decreases the stack pointer, since we know the current
12637 // stacklet has enough space.
12638 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12639 .addReg(SPLimitVReg);
12640 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12641 .addReg(SPLimitVReg);
12642 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12644 // Calls into a routine in libgcc to allocate more space from the heap.
12645 const uint32_t *RegMask =
12646 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12648 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12650 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12651 .addExternalSymbol("__morestack_allocate_stack_space")
12652 .addRegMask(RegMask)
12653 .addReg(X86::RDI, RegState::Implicit)
12654 .addReg(X86::RAX, RegState::ImplicitDefine);
12656 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12658 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12659 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12660 .addExternalSymbol("__morestack_allocate_stack_space")
12661 .addRegMask(RegMask)
12662 .addReg(X86::EAX, RegState::ImplicitDefine);
12666 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12669 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12670 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12671 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12673 // Set up the CFG correctly.
12674 BB->addSuccessor(bumpMBB);
12675 BB->addSuccessor(mallocMBB);
12676 mallocMBB->addSuccessor(continueMBB);
12677 bumpMBB->addSuccessor(continueMBB);
12679 // Take care of the PHI nodes.
12680 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12681 MI->getOperand(0).getReg())
12682 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12683 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12685 // Delete the original pseudo instruction.
12686 MI->eraseFromParent();
12689 return continueMBB;
12692 MachineBasicBlock *
12693 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12694 MachineBasicBlock *BB) const {
12695 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12696 DebugLoc DL = MI->getDebugLoc();
12698 assert(!Subtarget->isTargetEnvMacho());
12700 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12701 // non-trivial part is impdef of ESP.
12703 if (Subtarget->isTargetWin64()) {
12704 if (Subtarget->isTargetCygMing()) {
12705 // ___chkstk(Mingw64):
12706 // Clobbers R10, R11, RAX and EFLAGS.
12708 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12709 .addExternalSymbol("___chkstk")
12710 .addReg(X86::RAX, RegState::Implicit)
12711 .addReg(X86::RSP, RegState::Implicit)
12712 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12713 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12714 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12716 // __chkstk(MSVCRT): does not update stack pointer.
12717 // Clobbers R10, R11 and EFLAGS.
12718 // FIXME: RAX(allocated size) might be reused and not killed.
12719 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12720 .addExternalSymbol("__chkstk")
12721 .addReg(X86::RAX, RegState::Implicit)
12722 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12723 // RAX has the offset to subtracted from RSP.
12724 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12729 const char *StackProbeSymbol =
12730 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12732 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12733 .addExternalSymbol(StackProbeSymbol)
12734 .addReg(X86::EAX, RegState::Implicit)
12735 .addReg(X86::ESP, RegState::Implicit)
12736 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12737 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12738 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12741 MI->eraseFromParent(); // The pseudo instruction is gone now.
12745 MachineBasicBlock *
12746 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12747 MachineBasicBlock *BB) const {
12748 // This is pretty easy. We're taking the value that we received from
12749 // our load from the relocation, sticking it in either RDI (x86-64)
12750 // or EAX and doing an indirect call. The return value will then
12751 // be in the normal return register.
12752 const X86InstrInfo *TII
12753 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12754 DebugLoc DL = MI->getDebugLoc();
12755 MachineFunction *F = BB->getParent();
12757 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12758 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12760 // Get a register mask for the lowered call.
12761 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12762 // proper register mask.
12763 const uint32_t *RegMask =
12764 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12765 if (Subtarget->is64Bit()) {
12766 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12767 TII->get(X86::MOV64rm), X86::RDI)
12769 .addImm(0).addReg(0)
12770 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12771 MI->getOperand(3).getTargetFlags())
12773 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12774 addDirectMem(MIB, X86::RDI);
12775 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12776 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12777 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12778 TII->get(X86::MOV32rm), X86::EAX)
12780 .addImm(0).addReg(0)
12781 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12782 MI->getOperand(3).getTargetFlags())
12784 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12785 addDirectMem(MIB, X86::EAX);
12786 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12788 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12789 TII->get(X86::MOV32rm), X86::EAX)
12790 .addReg(TII->getGlobalBaseReg(F))
12791 .addImm(0).addReg(0)
12792 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12793 MI->getOperand(3).getTargetFlags())
12795 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12796 addDirectMem(MIB, X86::EAX);
12797 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12800 MI->eraseFromParent(); // The pseudo instruction is gone now.
12804 MachineBasicBlock *
12805 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12806 MachineBasicBlock *BB) const {
12807 switch (MI->getOpcode()) {
12808 default: llvm_unreachable("Unexpected instr type to insert");
12809 case X86::TAILJMPd64:
12810 case X86::TAILJMPr64:
12811 case X86::TAILJMPm64:
12812 llvm_unreachable("TAILJMP64 would not be touched here.");
12813 case X86::TCRETURNdi64:
12814 case X86::TCRETURNri64:
12815 case X86::TCRETURNmi64:
12817 case X86::WIN_ALLOCA:
12818 return EmitLoweredWinAlloca(MI, BB);
12819 case X86::SEG_ALLOCA_32:
12820 return EmitLoweredSegAlloca(MI, BB, false);
12821 case X86::SEG_ALLOCA_64:
12822 return EmitLoweredSegAlloca(MI, BB, true);
12823 case X86::TLSCall_32:
12824 case X86::TLSCall_64:
12825 return EmitLoweredTLSCall(MI, BB);
12826 case X86::CMOV_GR8:
12827 case X86::CMOV_FR32:
12828 case X86::CMOV_FR64:
12829 case X86::CMOV_V4F32:
12830 case X86::CMOV_V2F64:
12831 case X86::CMOV_V2I64:
12832 case X86::CMOV_V8F32:
12833 case X86::CMOV_V4F64:
12834 case X86::CMOV_V4I64:
12835 case X86::CMOV_GR16:
12836 case X86::CMOV_GR32:
12837 case X86::CMOV_RFP32:
12838 case X86::CMOV_RFP64:
12839 case X86::CMOV_RFP80:
12840 return EmitLoweredSelect(MI, BB);
12842 case X86::FP32_TO_INT16_IN_MEM:
12843 case X86::FP32_TO_INT32_IN_MEM:
12844 case X86::FP32_TO_INT64_IN_MEM:
12845 case X86::FP64_TO_INT16_IN_MEM:
12846 case X86::FP64_TO_INT32_IN_MEM:
12847 case X86::FP64_TO_INT64_IN_MEM:
12848 case X86::FP80_TO_INT16_IN_MEM:
12849 case X86::FP80_TO_INT32_IN_MEM:
12850 case X86::FP80_TO_INT64_IN_MEM: {
12851 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12852 DebugLoc DL = MI->getDebugLoc();
12854 // Change the floating point control register to use "round towards zero"
12855 // mode when truncating to an integer value.
12856 MachineFunction *F = BB->getParent();
12857 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12858 addFrameReference(BuildMI(*BB, MI, DL,
12859 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12861 // Load the old value of the high byte of the control word...
12863 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12864 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12867 // Set the high part to be round to zero...
12868 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12871 // Reload the modified control word now...
12872 addFrameReference(BuildMI(*BB, MI, DL,
12873 TII->get(X86::FLDCW16m)), CWFrameIdx);
12875 // Restore the memory image of control word to original value
12876 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12879 // Get the X86 opcode to use.
12881 switch (MI->getOpcode()) {
12882 default: llvm_unreachable("illegal opcode!");
12883 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12884 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12885 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12886 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12887 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12888 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12889 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12890 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12891 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12895 MachineOperand &Op = MI->getOperand(0);
12897 AM.BaseType = X86AddressMode::RegBase;
12898 AM.Base.Reg = Op.getReg();
12900 AM.BaseType = X86AddressMode::FrameIndexBase;
12901 AM.Base.FrameIndex = Op.getIndex();
12903 Op = MI->getOperand(1);
12905 AM.Scale = Op.getImm();
12906 Op = MI->getOperand(2);
12908 AM.IndexReg = Op.getImm();
12909 Op = MI->getOperand(3);
12910 if (Op.isGlobal()) {
12911 AM.GV = Op.getGlobal();
12913 AM.Disp = Op.getImm();
12915 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12916 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12918 // Reload the original control word now.
12919 addFrameReference(BuildMI(*BB, MI, DL,
12920 TII->get(X86::FLDCW16m)), CWFrameIdx);
12922 MI->eraseFromParent(); // The pseudo instruction is gone now.
12925 // String/text processing lowering.
12926 case X86::PCMPISTRM128REG:
12927 case X86::VPCMPISTRM128REG:
12928 case X86::PCMPISTRM128MEM:
12929 case X86::VPCMPISTRM128MEM:
12930 case X86::PCMPESTRM128REG:
12931 case X86::VPCMPESTRM128REG:
12932 case X86::PCMPESTRM128MEM:
12933 case X86::VPCMPESTRM128MEM: {
12936 switch (MI->getOpcode()) {
12937 default: llvm_unreachable("illegal opcode!");
12938 case X86::PCMPISTRM128REG:
12939 case X86::VPCMPISTRM128REG:
12940 NumArgs = 3; MemArg = false; break;
12941 case X86::PCMPISTRM128MEM:
12942 case X86::VPCMPISTRM128MEM:
12943 NumArgs = 3; MemArg = true; break;
12944 case X86::PCMPESTRM128REG:
12945 case X86::VPCMPESTRM128REG:
12946 NumArgs = 5; MemArg = false; break;
12947 case X86::PCMPESTRM128MEM:
12948 case X86::VPCMPESTRM128MEM:
12949 NumArgs = 5; MemArg = true; break;
12951 return EmitPCMP(MI, BB, NumArgs, MemArg);
12954 // Thread synchronization.
12956 return EmitMonitor(MI, BB);
12958 // Atomic Lowering.
12959 case X86::ATOMAND32:
12960 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12961 X86::AND32ri, X86::MOV32rm,
12963 X86::NOT32r, X86::EAX,
12964 &X86::GR32RegClass);
12965 case X86::ATOMOR32:
12966 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12967 X86::OR32ri, X86::MOV32rm,
12969 X86::NOT32r, X86::EAX,
12970 &X86::GR32RegClass);
12971 case X86::ATOMXOR32:
12972 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12973 X86::XOR32ri, X86::MOV32rm,
12975 X86::NOT32r, X86::EAX,
12976 &X86::GR32RegClass);
12977 case X86::ATOMNAND32:
12978 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12979 X86::AND32ri, X86::MOV32rm,
12981 X86::NOT32r, X86::EAX,
12982 &X86::GR32RegClass, true);
12983 case X86::ATOMMIN32:
12984 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12985 case X86::ATOMMAX32:
12986 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12987 case X86::ATOMUMIN32:
12988 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12989 case X86::ATOMUMAX32:
12990 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12992 case X86::ATOMAND16:
12993 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12994 X86::AND16ri, X86::MOV16rm,
12996 X86::NOT16r, X86::AX,
12997 &X86::GR16RegClass);
12998 case X86::ATOMOR16:
12999 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
13000 X86::OR16ri, X86::MOV16rm,
13002 X86::NOT16r, X86::AX,
13003 &X86::GR16RegClass);
13004 case X86::ATOMXOR16:
13005 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
13006 X86::XOR16ri, X86::MOV16rm,
13008 X86::NOT16r, X86::AX,
13009 &X86::GR16RegClass);
13010 case X86::ATOMNAND16:
13011 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
13012 X86::AND16ri, X86::MOV16rm,
13014 X86::NOT16r, X86::AX,
13015 &X86::GR16RegClass, true);
13016 case X86::ATOMMIN16:
13017 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
13018 case X86::ATOMMAX16:
13019 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
13020 case X86::ATOMUMIN16:
13021 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
13022 case X86::ATOMUMAX16:
13023 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
13025 case X86::ATOMAND8:
13026 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
13027 X86::AND8ri, X86::MOV8rm,
13029 X86::NOT8r, X86::AL,
13030 &X86::GR8RegClass);
13032 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
13033 X86::OR8ri, X86::MOV8rm,
13035 X86::NOT8r, X86::AL,
13036 &X86::GR8RegClass);
13037 case X86::ATOMXOR8:
13038 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
13039 X86::XOR8ri, X86::MOV8rm,
13041 X86::NOT8r, X86::AL,
13042 &X86::GR8RegClass);
13043 case X86::ATOMNAND8:
13044 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
13045 X86::AND8ri, X86::MOV8rm,
13047 X86::NOT8r, X86::AL,
13048 &X86::GR8RegClass, true);
13049 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
13050 // This group is for 64-bit host.
13051 case X86::ATOMAND64:
13052 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
13053 X86::AND64ri32, X86::MOV64rm,
13055 X86::NOT64r, X86::RAX,
13056 &X86::GR64RegClass);
13057 case X86::ATOMOR64:
13058 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
13059 X86::OR64ri32, X86::MOV64rm,
13061 X86::NOT64r, X86::RAX,
13062 &X86::GR64RegClass);
13063 case X86::ATOMXOR64:
13064 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
13065 X86::XOR64ri32, X86::MOV64rm,
13067 X86::NOT64r, X86::RAX,
13068 &X86::GR64RegClass);
13069 case X86::ATOMNAND64:
13070 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
13071 X86::AND64ri32, X86::MOV64rm,
13073 X86::NOT64r, X86::RAX,
13074 &X86::GR64RegClass, true);
13075 case X86::ATOMMIN64:
13076 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
13077 case X86::ATOMMAX64:
13078 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
13079 case X86::ATOMUMIN64:
13080 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
13081 case X86::ATOMUMAX64:
13082 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
13084 // This group does 64-bit operations on a 32-bit host.
13085 case X86::ATOMAND6432:
13086 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13087 X86::AND32rr, X86::AND32rr,
13088 X86::AND32ri, X86::AND32ri,
13090 case X86::ATOMOR6432:
13091 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13092 X86::OR32rr, X86::OR32rr,
13093 X86::OR32ri, X86::OR32ri,
13095 case X86::ATOMXOR6432:
13096 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13097 X86::XOR32rr, X86::XOR32rr,
13098 X86::XOR32ri, X86::XOR32ri,
13100 case X86::ATOMNAND6432:
13101 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13102 X86::AND32rr, X86::AND32rr,
13103 X86::AND32ri, X86::AND32ri,
13105 case X86::ATOMADD6432:
13106 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13107 X86::ADD32rr, X86::ADC32rr,
13108 X86::ADD32ri, X86::ADC32ri,
13110 case X86::ATOMSUB6432:
13111 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13112 X86::SUB32rr, X86::SBB32rr,
13113 X86::SUB32ri, X86::SBB32ri,
13115 case X86::ATOMSWAP6432:
13116 return EmitAtomicBit6432WithCustomInserter(MI, BB,
13117 X86::MOV32rr, X86::MOV32rr,
13118 X86::MOV32ri, X86::MOV32ri,
13120 case X86::VASTART_SAVE_XMM_REGS:
13121 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
13123 case X86::VAARG_64:
13124 return EmitVAARG64WithCustomInserter(MI, BB);
13128 //===----------------------------------------------------------------------===//
13129 // X86 Optimization Hooks
13130 //===----------------------------------------------------------------------===//
13132 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
13135 const SelectionDAG &DAG,
13136 unsigned Depth) const {
13137 unsigned BitWidth = KnownZero.getBitWidth();
13138 unsigned Opc = Op.getOpcode();
13139 assert((Opc >= ISD::BUILTIN_OP_END ||
13140 Opc == ISD::INTRINSIC_WO_CHAIN ||
13141 Opc == ISD::INTRINSIC_W_CHAIN ||
13142 Opc == ISD::INTRINSIC_VOID) &&
13143 "Should use MaskedValueIsZero if you don't know whether Op"
13144 " is a target node!");
13146 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
13160 // These nodes' second result is a boolean.
13161 if (Op.getResNo() == 0)
13164 case X86ISD::SETCC:
13165 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
13167 case ISD::INTRINSIC_WO_CHAIN: {
13168 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13169 unsigned NumLoBits = 0;
13172 case Intrinsic::x86_sse_movmsk_ps:
13173 case Intrinsic::x86_avx_movmsk_ps_256:
13174 case Intrinsic::x86_sse2_movmsk_pd:
13175 case Intrinsic::x86_avx_movmsk_pd_256:
13176 case Intrinsic::x86_mmx_pmovmskb:
13177 case Intrinsic::x86_sse2_pmovmskb_128:
13178 case Intrinsic::x86_avx2_pmovmskb: {
13179 // High bits of movmskp{s|d}, pmovmskb are known zero.
13181 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13182 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
13183 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
13184 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
13185 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
13186 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
13187 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
13188 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
13190 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
13199 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
13200 unsigned Depth) const {
13201 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
13202 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
13203 return Op.getValueType().getScalarType().getSizeInBits();
13209 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
13210 /// node is a GlobalAddress + offset.
13211 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
13212 const GlobalValue* &GA,
13213 int64_t &Offset) const {
13214 if (N->getOpcode() == X86ISD::Wrapper) {
13215 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
13216 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
13217 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
13221 return TargetLowering::isGAPlusOffset(N, GA, Offset);
13224 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
13225 /// same as extracting the high 128-bit part of 256-bit vector and then
13226 /// inserting the result into the low part of a new 256-bit vector
13227 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
13228 EVT VT = SVOp->getValueType(0);
13229 unsigned NumElems = VT.getVectorNumElements();
13231 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13232 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
13233 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13234 SVOp->getMaskElt(j) >= 0)
13240 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
13241 /// same as extracting the low 128-bit part of 256-bit vector and then
13242 /// inserting the result into the high part of a new 256-bit vector
13243 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
13244 EVT VT = SVOp->getValueType(0);
13245 unsigned NumElems = VT.getVectorNumElements();
13247 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13248 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
13249 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13250 SVOp->getMaskElt(j) >= 0)
13256 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
13257 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
13258 TargetLowering::DAGCombinerInfo &DCI,
13259 const X86Subtarget* Subtarget) {
13260 DebugLoc dl = N->getDebugLoc();
13261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
13262 SDValue V1 = SVOp->getOperand(0);
13263 SDValue V2 = SVOp->getOperand(1);
13264 EVT VT = SVOp->getValueType(0);
13265 unsigned NumElems = VT.getVectorNumElements();
13267 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
13268 V2.getOpcode() == ISD::CONCAT_VECTORS) {
13272 // V UNDEF BUILD_VECTOR UNDEF
13274 // CONCAT_VECTOR CONCAT_VECTOR
13277 // RESULT: V + zero extended
13279 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13280 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13281 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13284 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13287 // To match the shuffle mask, the first half of the mask should
13288 // be exactly the first vector, and all the rest a splat with the
13289 // first element of the second one.
13290 for (unsigned i = 0; i != NumElems/2; ++i)
13291 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13292 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13295 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13296 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13297 if (Ld->hasNUsesOfValue(1, 0)) {
13298 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13299 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13301 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13303 Ld->getPointerInfo(),
13304 Ld->getAlignment(),
13305 false/*isVolatile*/, true/*ReadMem*/,
13306 false/*WriteMem*/);
13307 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13311 // Emit a zeroed vector and insert the desired subvector on its
13313 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13314 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13315 return DCI.CombineTo(N, InsV);
13318 //===--------------------------------------------------------------------===//
13319 // Combine some shuffles into subvector extracts and inserts:
13322 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13323 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13324 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13325 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13326 return DCI.CombineTo(N, InsV);
13329 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13330 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13331 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13332 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13333 return DCI.CombineTo(N, InsV);
13339 /// PerformShuffleCombine - Performs several different shuffle combines.
13340 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13341 TargetLowering::DAGCombinerInfo &DCI,
13342 const X86Subtarget *Subtarget) {
13343 DebugLoc dl = N->getDebugLoc();
13344 EVT VT = N->getValueType(0);
13346 // Don't create instructions with illegal types after legalize types has run.
13347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13348 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13351 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13352 if (Subtarget->hasAVX() && VT.is256BitVector() &&
13353 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13354 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13356 // Only handle 128 wide vector from here on.
13357 if (!VT.is128BitVector())
13360 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13361 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13362 // consecutive, non-overlapping, and in the right order.
13363 SmallVector<SDValue, 16> Elts;
13364 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13365 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13367 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13371 /// DCI, PerformTruncateCombine - Converts truncate operation to
13372 /// a sequence of vector shuffle operations.
13373 /// It is possible when we truncate 256-bit vector to 128-bit vector
13375 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13376 DAGCombinerInfo &DCI) const {
13377 if (!DCI.isBeforeLegalizeOps())
13380 if (!Subtarget->hasAVX())
13383 EVT VT = N->getValueType(0);
13384 SDValue Op = N->getOperand(0);
13385 EVT OpVT = Op.getValueType();
13386 DebugLoc dl = N->getDebugLoc();
13388 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13390 if (Subtarget->hasAVX2()) {
13391 // AVX2: v4i64 -> v4i32
13394 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13396 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13397 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13400 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13401 DAG.getIntPtrConstant(0));
13404 // AVX: v4i64 -> v4i32
13405 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13406 DAG.getIntPtrConstant(0));
13408 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13409 DAG.getIntPtrConstant(2));
13411 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13412 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13415 static const int ShufMask1[] = {0, 2, 0, 0};
13417 SDValue Undef = DAG.getUNDEF(VT);
13418 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, Undef, ShufMask1);
13419 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, Undef, ShufMask1);
13422 static const int ShufMask2[] = {0, 1, 4, 5};
13424 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13427 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13429 if (Subtarget->hasAVX2()) {
13430 // AVX2: v8i32 -> v8i16
13432 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13435 SmallVector<SDValue,32> pshufbMask;
13436 for (unsigned i = 0; i < 2; ++i) {
13437 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13438 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13439 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13440 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13441 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13442 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13443 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13444 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13445 for (unsigned j = 0; j < 8; ++j)
13446 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13448 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13449 &pshufbMask[0], 32);
13450 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13452 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13454 static const int ShufMask[] = {0, 2, -1, -1};
13455 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13458 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13459 DAG.getIntPtrConstant(0));
13461 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13464 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13465 DAG.getIntPtrConstant(0));
13467 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13468 DAG.getIntPtrConstant(4));
13470 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13471 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13474 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13475 -1, -1, -1, -1, -1, -1, -1, -1};
13477 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13478 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, Undef, ShufMask1);
13479 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, Undef, ShufMask1);
13481 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13482 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13485 static const int ShufMask2[] = {0, 1, 4, 5};
13487 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13488 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13494 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13495 /// specific shuffle of a load can be folded into a single element load.
13496 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13497 /// shuffles have been customed lowered so we need to handle those here.
13498 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13499 TargetLowering::DAGCombinerInfo &DCI) {
13500 if (DCI.isBeforeLegalizeOps())
13503 SDValue InVec = N->getOperand(0);
13504 SDValue EltNo = N->getOperand(1);
13506 if (!isa<ConstantSDNode>(EltNo))
13509 EVT VT = InVec.getValueType();
13511 bool HasShuffleIntoBitcast = false;
13512 if (InVec.getOpcode() == ISD::BITCAST) {
13513 // Don't duplicate a load with other uses.
13514 if (!InVec.hasOneUse())
13516 EVT BCVT = InVec.getOperand(0).getValueType();
13517 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13519 InVec = InVec.getOperand(0);
13520 HasShuffleIntoBitcast = true;
13523 if (!isTargetShuffle(InVec.getOpcode()))
13526 // Don't duplicate a load with other uses.
13527 if (!InVec.hasOneUse())
13530 SmallVector<int, 16> ShuffleMask;
13532 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13536 // Select the input vector, guarding against out of range extract vector.
13537 unsigned NumElems = VT.getVectorNumElements();
13538 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13539 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13540 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13541 : InVec.getOperand(1);
13543 // If inputs to shuffle are the same for both ops, then allow 2 uses
13544 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13546 if (LdNode.getOpcode() == ISD::BITCAST) {
13547 // Don't duplicate a load with other uses.
13548 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13551 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13552 LdNode = LdNode.getOperand(0);
13555 if (!ISD::isNormalLoad(LdNode.getNode()))
13558 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13560 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13563 if (HasShuffleIntoBitcast) {
13564 // If there's a bitcast before the shuffle, check if the load type and
13565 // alignment is valid.
13566 unsigned Align = LN0->getAlignment();
13567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13568 unsigned NewAlign = TLI.getTargetData()->
13569 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13571 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13575 // All checks match so transform back to vector_shuffle so that DAG combiner
13576 // can finish the job
13577 DebugLoc dl = N->getDebugLoc();
13579 // Create shuffle node taking into account the case that its a unary shuffle
13580 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13581 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13582 InVec.getOperand(0), Shuffle,
13584 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13585 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13589 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13590 /// generation and convert it from being a bunch of shuffles and extracts
13591 /// to a simple store and scalar loads to extract the elements.
13592 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13593 TargetLowering::DAGCombinerInfo &DCI) {
13594 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13595 if (NewOp.getNode())
13598 SDValue InputVector = N->getOperand(0);
13600 // Only operate on vectors of 4 elements, where the alternative shuffling
13601 // gets to be more expensive.
13602 if (InputVector.getValueType() != MVT::v4i32)
13605 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13606 // single use which is a sign-extend or zero-extend, and all elements are
13608 SmallVector<SDNode *, 4> Uses;
13609 unsigned ExtractedElements = 0;
13610 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13611 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13612 if (UI.getUse().getResNo() != InputVector.getResNo())
13615 SDNode *Extract = *UI;
13616 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13619 if (Extract->getValueType(0) != MVT::i32)
13621 if (!Extract->hasOneUse())
13623 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13624 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13626 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13629 // Record which element was extracted.
13630 ExtractedElements |=
13631 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13633 Uses.push_back(Extract);
13636 // If not all the elements were used, this may not be worthwhile.
13637 if (ExtractedElements != 15)
13640 // Ok, we've now decided to do the transformation.
13641 DebugLoc dl = InputVector.getDebugLoc();
13643 // Store the value to a temporary stack slot.
13644 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13645 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13646 MachinePointerInfo(), false, false, 0);
13648 // Replace each use (extract) with a load of the appropriate element.
13649 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13650 UE = Uses.end(); UI != UE; ++UI) {
13651 SDNode *Extract = *UI;
13653 // cOMpute the element's address.
13654 SDValue Idx = Extract->getOperand(1);
13656 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13657 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13658 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13659 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13661 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13662 StackPtr, OffsetVal);
13664 // Load the scalar.
13665 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13666 ScalarAddr, MachinePointerInfo(),
13667 false, false, false, 0);
13669 // Replace the exact with the load.
13670 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13673 // The replacement was made in place; don't return anything.
13677 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13679 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13680 TargetLowering::DAGCombinerInfo &DCI,
13681 const X86Subtarget *Subtarget) {
13682 DebugLoc DL = N->getDebugLoc();
13683 SDValue Cond = N->getOperand(0);
13684 // Get the LHS/RHS of the select.
13685 SDValue LHS = N->getOperand(1);
13686 SDValue RHS = N->getOperand(2);
13687 EVT VT = LHS.getValueType();
13689 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13690 // instructions match the semantics of the common C idiom x<y?x:y but not
13691 // x<=y?x:y, because of how they handle negative zero (which can be
13692 // ignored in unsafe-math mode).
13693 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13694 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13695 (Subtarget->hasSSE2() ||
13696 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13697 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13699 unsigned Opcode = 0;
13700 // Check for x CC y ? x : y.
13701 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13702 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13706 // Converting this to a min would handle NaNs incorrectly, and swapping
13707 // the operands would cause it to handle comparisons between positive
13708 // and negative zero incorrectly.
13709 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13710 if (!DAG.getTarget().Options.UnsafeFPMath &&
13711 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13713 std::swap(LHS, RHS);
13715 Opcode = X86ISD::FMIN;
13718 // Converting this to a min would handle comparisons between positive
13719 // and negative zero incorrectly.
13720 if (!DAG.getTarget().Options.UnsafeFPMath &&
13721 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13723 Opcode = X86ISD::FMIN;
13726 // Converting this to a min would handle both negative zeros and NaNs
13727 // incorrectly, but we can swap the operands to fix both.
13728 std::swap(LHS, RHS);
13732 Opcode = X86ISD::FMIN;
13736 // Converting this to a max would handle comparisons between positive
13737 // and negative zero incorrectly.
13738 if (!DAG.getTarget().Options.UnsafeFPMath &&
13739 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13741 Opcode = X86ISD::FMAX;
13744 // Converting this to a max would handle NaNs incorrectly, and swapping
13745 // the operands would cause it to handle comparisons between positive
13746 // and negative zero incorrectly.
13747 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13748 if (!DAG.getTarget().Options.UnsafeFPMath &&
13749 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13751 std::swap(LHS, RHS);
13753 Opcode = X86ISD::FMAX;
13756 // Converting this to a max would handle both negative zeros and NaNs
13757 // incorrectly, but we can swap the operands to fix both.
13758 std::swap(LHS, RHS);
13762 Opcode = X86ISD::FMAX;
13765 // Check for x CC y ? y : x -- a min/max with reversed arms.
13766 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13767 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13771 // Converting this to a min would handle comparisons between positive
13772 // and negative zero incorrectly, and swapping the operands would
13773 // cause it to handle NaNs incorrectly.
13774 if (!DAG.getTarget().Options.UnsafeFPMath &&
13775 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13776 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13778 std::swap(LHS, RHS);
13780 Opcode = X86ISD::FMIN;
13783 // Converting this to a min would handle NaNs incorrectly.
13784 if (!DAG.getTarget().Options.UnsafeFPMath &&
13785 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13787 Opcode = X86ISD::FMIN;
13790 // Converting this to a min would handle both negative zeros and NaNs
13791 // incorrectly, but we can swap the operands to fix both.
13792 std::swap(LHS, RHS);
13796 Opcode = X86ISD::FMIN;
13800 // Converting this to a max would handle NaNs incorrectly.
13801 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13803 Opcode = X86ISD::FMAX;
13806 // Converting this to a max would handle comparisons between positive
13807 // and negative zero incorrectly, and swapping the operands would
13808 // cause it to handle NaNs incorrectly.
13809 if (!DAG.getTarget().Options.UnsafeFPMath &&
13810 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13811 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13813 std::swap(LHS, RHS);
13815 Opcode = X86ISD::FMAX;
13818 // Converting this to a max would handle both negative zeros and NaNs
13819 // incorrectly, but we can swap the operands to fix both.
13820 std::swap(LHS, RHS);
13824 Opcode = X86ISD::FMAX;
13830 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13833 // If this is a select between two integer constants, try to do some
13835 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13836 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13837 // Don't do this for crazy integer types.
13838 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13839 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13840 // so that TrueC (the true value) is larger than FalseC.
13841 bool NeedsCondInvert = false;
13843 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13844 // Efficiently invertible.
13845 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13846 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13847 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13848 NeedsCondInvert = true;
13849 std::swap(TrueC, FalseC);
13852 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13853 if (FalseC->getAPIntValue() == 0 &&
13854 TrueC->getAPIntValue().isPowerOf2()) {
13855 if (NeedsCondInvert) // Invert the condition if needed.
13856 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13857 DAG.getConstant(1, Cond.getValueType()));
13859 // Zero extend the condition if needed.
13860 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13862 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13863 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13864 DAG.getConstant(ShAmt, MVT::i8));
13867 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13868 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13869 if (NeedsCondInvert) // Invert the condition if needed.
13870 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13871 DAG.getConstant(1, Cond.getValueType()));
13873 // Zero extend the condition if needed.
13874 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13875 FalseC->getValueType(0), Cond);
13876 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13877 SDValue(FalseC, 0));
13880 // Optimize cases that will turn into an LEA instruction. This requires
13881 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13882 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13883 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13884 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13886 bool isFastMultiplier = false;
13888 switch ((unsigned char)Diff) {
13890 case 1: // result = add base, cond
13891 case 2: // result = lea base( , cond*2)
13892 case 3: // result = lea base(cond, cond*2)
13893 case 4: // result = lea base( , cond*4)
13894 case 5: // result = lea base(cond, cond*4)
13895 case 8: // result = lea base( , cond*8)
13896 case 9: // result = lea base(cond, cond*8)
13897 isFastMultiplier = true;
13902 if (isFastMultiplier) {
13903 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13904 if (NeedsCondInvert) // Invert the condition if needed.
13905 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13906 DAG.getConstant(1, Cond.getValueType()));
13908 // Zero extend the condition if needed.
13909 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13911 // Scale the condition by the difference.
13913 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13914 DAG.getConstant(Diff, Cond.getValueType()));
13916 // Add the base if non-zero.
13917 if (FalseC->getAPIntValue() != 0)
13918 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13919 SDValue(FalseC, 0));
13926 // Canonicalize max and min:
13927 // (x > y) ? x : y -> (x >= y) ? x : y
13928 // (x < y) ? x : y -> (x <= y) ? x : y
13929 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13930 // the need for an extra compare
13931 // against zero. e.g.
13932 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13934 // testl %edi, %edi
13936 // cmovgl %edi, %eax
13940 // cmovsl %eax, %edi
13941 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13942 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13943 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13944 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13949 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13950 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13951 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13952 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13957 // If we know that this node is legal then we know that it is going to be
13958 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13959 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13960 // to simplify previous instructions.
13961 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13962 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13963 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13964 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13966 // Don't optimize vector selects that map to mask-registers.
13970 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13971 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13973 APInt KnownZero, KnownOne;
13974 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13975 DCI.isBeforeLegalizeOps());
13976 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13977 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13978 DCI.CommitTargetLoweringOpt(TLO);
13984 // Check whether a boolean test is testing a boolean value generated by
13985 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
13988 // Simplify the following patterns:
13989 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
13990 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
13991 // to (Op EFLAGS Cond)
13993 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
13994 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
13995 // to (Op EFLAGS !Cond)
13997 // where Op could be BRCOND or CMOV.
13999 static SDValue BoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
14000 // Quit if not CMP and SUB with its value result used.
14001 if (Cmp.getOpcode() != X86ISD::CMP &&
14002 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
14005 // Quit if not used as a boolean value.
14006 if (CC != X86::COND_E && CC != X86::COND_NE)
14009 // Check CMP operands. One of them should be 0 or 1 and the other should be
14010 // an SetCC or extended from it.
14011 SDValue Op1 = Cmp.getOperand(0);
14012 SDValue Op2 = Cmp.getOperand(1);
14015 const ConstantSDNode* C = 0;
14016 bool needOppositeCond = (CC == X86::COND_E);
14018 if ((C = dyn_cast<ConstantSDNode>(Op1)))
14020 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
14022 else // Quit if all operands are not constants.
14025 if (C->getZExtValue() == 1)
14026 needOppositeCond = !needOppositeCond;
14027 else if (C->getZExtValue() != 0)
14028 // Quit if the constant is neither 0 or 1.
14031 // Skip 'zext' node.
14032 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
14033 SetCC = SetCC.getOperand(0);
14035 // Quit if not SETCC.
14036 // FIXME: So far we only handle the boolean value generated from SETCC. If
14037 // there is other ways to generate boolean values, we need handle them here
14039 if (SetCC.getOpcode() != X86ISD::SETCC)
14042 // Set the condition code or opposite one if necessary.
14043 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
14044 if (needOppositeCond)
14045 CC = X86::GetOppositeBranchCondition(CC);
14047 return SetCC.getOperand(1);
14050 static bool IsValidFCMOVCondition(X86::CondCode CC) {
14066 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
14067 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
14068 TargetLowering::DAGCombinerInfo &DCI) {
14069 DebugLoc DL = N->getDebugLoc();
14071 // If the flag operand isn't dead, don't touch this CMOV.
14072 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
14075 SDValue FalseOp = N->getOperand(0);
14076 SDValue TrueOp = N->getOperand(1);
14077 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
14078 SDValue Cond = N->getOperand(3);
14080 if (CC == X86::COND_E || CC == X86::COND_NE) {
14081 switch (Cond.getOpcode()) {
14085 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
14086 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
14087 return (CC == X86::COND_E) ? FalseOp : TrueOp;
14093 Flags = BoolTestSetCCCombine(Cond, CC);
14094 if (Flags.getNode() &&
14095 // Extra check as FCMOV only supports a subset of X86 cond.
14096 (FalseOp.getValueType() != MVT::f80 || IsValidFCMOVCondition(CC))) {
14097 SDValue Ops[] = { FalseOp, TrueOp,
14098 DAG.getConstant(CC, MVT::i8), Flags };
14099 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
14100 Ops, array_lengthof(Ops));
14103 // If this is a select between two integer constants, try to do some
14104 // optimizations. Note that the operands are ordered the opposite of SELECT
14106 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
14107 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
14108 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
14109 // larger than FalseC (the false value).
14110 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
14111 CC = X86::GetOppositeBranchCondition(CC);
14112 std::swap(TrueC, FalseC);
14115 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
14116 // This is efficient for any integer data type (including i8/i16) and
14118 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
14119 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14120 DAG.getConstant(CC, MVT::i8), Cond);
14122 // Zero extend the condition if needed.
14123 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
14125 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
14126 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
14127 DAG.getConstant(ShAmt, MVT::i8));
14128 if (N->getNumValues() == 2) // Dead flag value?
14129 return DCI.CombineTo(N, Cond, SDValue());
14133 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
14134 // for any integer data type, including i8/i16.
14135 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
14136 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14137 DAG.getConstant(CC, MVT::i8), Cond);
14139 // Zero extend the condition if needed.
14140 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
14141 FalseC->getValueType(0), Cond);
14142 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14143 SDValue(FalseC, 0));
14145 if (N->getNumValues() == 2) // Dead flag value?
14146 return DCI.CombineTo(N, Cond, SDValue());
14150 // Optimize cases that will turn into an LEA instruction. This requires
14151 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
14152 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
14153 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
14154 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
14156 bool isFastMultiplier = false;
14158 switch ((unsigned char)Diff) {
14160 case 1: // result = add base, cond
14161 case 2: // result = lea base( , cond*2)
14162 case 3: // result = lea base(cond, cond*2)
14163 case 4: // result = lea base( , cond*4)
14164 case 5: // result = lea base(cond, cond*4)
14165 case 8: // result = lea base( , cond*8)
14166 case 9: // result = lea base(cond, cond*8)
14167 isFastMultiplier = true;
14172 if (isFastMultiplier) {
14173 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
14174 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14175 DAG.getConstant(CC, MVT::i8), Cond);
14176 // Zero extend the condition if needed.
14177 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
14179 // Scale the condition by the difference.
14181 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
14182 DAG.getConstant(Diff, Cond.getValueType()));
14184 // Add the base if non-zero.
14185 if (FalseC->getAPIntValue() != 0)
14186 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14187 SDValue(FalseC, 0));
14188 if (N->getNumValues() == 2) // Dead flag value?
14189 return DCI.CombineTo(N, Cond, SDValue());
14199 /// PerformMulCombine - Optimize a single multiply with constant into two
14200 /// in order to implement it with two cheaper instructions, e.g.
14201 /// LEA + SHL, LEA + LEA.
14202 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
14203 TargetLowering::DAGCombinerInfo &DCI) {
14204 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14207 EVT VT = N->getValueType(0);
14208 if (VT != MVT::i64)
14211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
14214 uint64_t MulAmt = C->getZExtValue();
14215 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
14218 uint64_t MulAmt1 = 0;
14219 uint64_t MulAmt2 = 0;
14220 if ((MulAmt % 9) == 0) {
14222 MulAmt2 = MulAmt / 9;
14223 } else if ((MulAmt % 5) == 0) {
14225 MulAmt2 = MulAmt / 5;
14226 } else if ((MulAmt % 3) == 0) {
14228 MulAmt2 = MulAmt / 3;
14231 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
14232 DebugLoc DL = N->getDebugLoc();
14234 if (isPowerOf2_64(MulAmt2) &&
14235 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
14236 // If second multiplifer is pow2, issue it first. We want the multiply by
14237 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
14239 std::swap(MulAmt1, MulAmt2);
14242 if (isPowerOf2_64(MulAmt1))
14243 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
14244 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
14246 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
14247 DAG.getConstant(MulAmt1, VT));
14249 if (isPowerOf2_64(MulAmt2))
14250 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
14251 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
14253 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
14254 DAG.getConstant(MulAmt2, VT));
14256 // Do not add new nodes to DAG combiner worklist.
14257 DCI.CombineTo(N, NewMul, false);
14262 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
14263 SDValue N0 = N->getOperand(0);
14264 SDValue N1 = N->getOperand(1);
14265 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
14266 EVT VT = N0.getValueType();
14268 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
14269 // since the result of setcc_c is all zero's or all ones.
14270 if (VT.isInteger() && !VT.isVector() &&
14271 N1C && N0.getOpcode() == ISD::AND &&
14272 N0.getOperand(1).getOpcode() == ISD::Constant) {
14273 SDValue N00 = N0.getOperand(0);
14274 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
14275 ((N00.getOpcode() == ISD::ANY_EXTEND ||
14276 N00.getOpcode() == ISD::ZERO_EXTEND) &&
14277 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
14278 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
14279 APInt ShAmt = N1C->getAPIntValue();
14280 Mask = Mask.shl(ShAmt);
14282 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
14283 N00, DAG.getConstant(Mask, VT));
14288 // Hardware support for vector shifts is sparse which makes us scalarize the
14289 // vector operations in many cases. Also, on sandybridge ADD is faster than
14291 // (shl V, 1) -> add V,V
14292 if (isSplatVector(N1.getNode())) {
14293 assert(N0.getValueType().isVector() && "Invalid vector shift type");
14294 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
14295 // We shift all of the values by one. In many cases we do not have
14296 // hardware support for this operation. This is better expressed as an ADD
14298 if (N1C && (1 == N1C->getZExtValue())) {
14299 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
14306 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
14308 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
14309 TargetLowering::DAGCombinerInfo &DCI,
14310 const X86Subtarget *Subtarget) {
14311 EVT VT = N->getValueType(0);
14312 if (N->getOpcode() == ISD::SHL) {
14313 SDValue V = PerformSHLCombine(N, DAG);
14314 if (V.getNode()) return V;
14317 // On X86 with SSE2 support, we can transform this to a vector shift if
14318 // all elements are shifted by the same amount. We can't do this in legalize
14319 // because the a constant vector is typically transformed to a constant pool
14320 // so we have no knowledge of the shift amount.
14321 if (!Subtarget->hasSSE2())
14324 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
14325 (!Subtarget->hasAVX2() ||
14326 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
14329 SDValue ShAmtOp = N->getOperand(1);
14330 EVT EltVT = VT.getVectorElementType();
14331 DebugLoc DL = N->getDebugLoc();
14332 SDValue BaseShAmt = SDValue();
14333 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
14334 unsigned NumElts = VT.getVectorNumElements();
14336 for (; i != NumElts; ++i) {
14337 SDValue Arg = ShAmtOp.getOperand(i);
14338 if (Arg.getOpcode() == ISD::UNDEF) continue;
14342 // Handle the case where the build_vector is all undef
14343 // FIXME: Should DAG allow this?
14347 for (; i != NumElts; ++i) {
14348 SDValue Arg = ShAmtOp.getOperand(i);
14349 if (Arg.getOpcode() == ISD::UNDEF) continue;
14350 if (Arg != BaseShAmt) {
14354 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
14355 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
14356 SDValue InVec = ShAmtOp.getOperand(0);
14357 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
14358 unsigned NumElts = InVec.getValueType().getVectorNumElements();
14360 for (; i != NumElts; ++i) {
14361 SDValue Arg = InVec.getOperand(i);
14362 if (Arg.getOpcode() == ISD::UNDEF) continue;
14366 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
14367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
14368 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
14369 if (C->getZExtValue() == SplatIdx)
14370 BaseShAmt = InVec.getOperand(1);
14373 if (BaseShAmt.getNode() == 0) {
14374 // Don't create instructions with illegal types after legalize
14376 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14377 !DCI.isBeforeLegalize())
14380 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14381 DAG.getIntPtrConstant(0));
14386 // The shift amount is an i32.
14387 if (EltVT.bitsGT(MVT::i32))
14388 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14389 else if (EltVT.bitsLT(MVT::i32))
14390 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14392 // The shift amount is identical so we can do a vector shift.
14393 SDValue ValOp = N->getOperand(0);
14394 switch (N->getOpcode()) {
14396 llvm_unreachable("Unknown shift opcode!");
14398 switch (VT.getSimpleVT().SimpleTy) {
14399 default: return SDValue();
14406 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14409 switch (VT.getSimpleVT().SimpleTy) {
14410 default: return SDValue();
14415 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14418 switch (VT.getSimpleVT().SimpleTy) {
14419 default: return SDValue();
14426 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14432 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14433 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14434 // and friends. Likewise for OR -> CMPNEQSS.
14435 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14436 TargetLowering::DAGCombinerInfo &DCI,
14437 const X86Subtarget *Subtarget) {
14440 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14441 // we're requiring SSE2 for both.
14442 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14443 SDValue N0 = N->getOperand(0);
14444 SDValue N1 = N->getOperand(1);
14445 SDValue CMP0 = N0->getOperand(1);
14446 SDValue CMP1 = N1->getOperand(1);
14447 DebugLoc DL = N->getDebugLoc();
14449 // The SETCCs should both refer to the same CMP.
14450 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14453 SDValue CMP00 = CMP0->getOperand(0);
14454 SDValue CMP01 = CMP0->getOperand(1);
14455 EVT VT = CMP00.getValueType();
14457 if (VT == MVT::f32 || VT == MVT::f64) {
14458 bool ExpectingFlags = false;
14459 // Check for any users that want flags:
14460 for (SDNode::use_iterator UI = N->use_begin(),
14462 !ExpectingFlags && UI != UE; ++UI)
14463 switch (UI->getOpcode()) {
14468 ExpectingFlags = true;
14470 case ISD::CopyToReg:
14471 case ISD::SIGN_EXTEND:
14472 case ISD::ZERO_EXTEND:
14473 case ISD::ANY_EXTEND:
14477 if (!ExpectingFlags) {
14478 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14479 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14481 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14482 X86::CondCode tmp = cc0;
14487 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14488 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14489 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14490 X86ISD::NodeType NTOperator = is64BitFP ?
14491 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14492 // FIXME: need symbolic constants for these magic numbers.
14493 // See X86ATTInstPrinter.cpp:printSSECC().
14494 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14495 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14496 DAG.getConstant(x86cc, MVT::i8));
14497 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14499 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14500 DAG.getConstant(1, MVT::i32));
14501 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14502 return OneBitOfTruth;
14510 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14511 /// so it can be folded inside ANDNP.
14512 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14513 EVT VT = N->getValueType(0);
14515 // Match direct AllOnes for 128 and 256-bit vectors
14516 if (ISD::isBuildVectorAllOnes(N))
14519 // Look through a bit convert.
14520 if (N->getOpcode() == ISD::BITCAST)
14521 N = N->getOperand(0).getNode();
14523 // Sometimes the operand may come from a insert_subvector building a 256-bit
14525 if (VT.is256BitVector() &&
14526 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14527 SDValue V1 = N->getOperand(0);
14528 SDValue V2 = N->getOperand(1);
14530 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14531 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14532 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14533 ISD::isBuildVectorAllOnes(V2.getNode()))
14540 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14541 TargetLowering::DAGCombinerInfo &DCI,
14542 const X86Subtarget *Subtarget) {
14543 if (DCI.isBeforeLegalizeOps())
14546 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14550 EVT VT = N->getValueType(0);
14552 // Create ANDN, BLSI, and BLSR instructions
14553 // BLSI is X & (-X)
14554 // BLSR is X & (X-1)
14555 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14556 SDValue N0 = N->getOperand(0);
14557 SDValue N1 = N->getOperand(1);
14558 DebugLoc DL = N->getDebugLoc();
14560 // Check LHS for not
14561 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14562 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14563 // Check RHS for not
14564 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14565 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14567 // Check LHS for neg
14568 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14569 isZero(N0.getOperand(0)))
14570 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14572 // Check RHS for neg
14573 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14574 isZero(N1.getOperand(0)))
14575 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14577 // Check LHS for X-1
14578 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14579 isAllOnes(N0.getOperand(1)))
14580 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14582 // Check RHS for X-1
14583 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14584 isAllOnes(N1.getOperand(1)))
14585 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14590 // Want to form ANDNP nodes:
14591 // 1) In the hopes of then easily combining them with OR and AND nodes
14592 // to form PBLEND/PSIGN.
14593 // 2) To match ANDN packed intrinsics
14594 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14597 SDValue N0 = N->getOperand(0);
14598 SDValue N1 = N->getOperand(1);
14599 DebugLoc DL = N->getDebugLoc();
14601 // Check LHS for vnot
14602 if (N0.getOpcode() == ISD::XOR &&
14603 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14604 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14605 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14607 // Check RHS for vnot
14608 if (N1.getOpcode() == ISD::XOR &&
14609 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14610 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14611 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14616 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14617 TargetLowering::DAGCombinerInfo &DCI,
14618 const X86Subtarget *Subtarget) {
14619 if (DCI.isBeforeLegalizeOps())
14622 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14626 EVT VT = N->getValueType(0);
14628 SDValue N0 = N->getOperand(0);
14629 SDValue N1 = N->getOperand(1);
14631 // look for psign/blend
14632 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14633 if (!Subtarget->hasSSSE3() ||
14634 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14637 // Canonicalize pandn to RHS
14638 if (N0.getOpcode() == X86ISD::ANDNP)
14640 // or (and (m, y), (pandn m, x))
14641 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14642 SDValue Mask = N1.getOperand(0);
14643 SDValue X = N1.getOperand(1);
14645 if (N0.getOperand(0) == Mask)
14646 Y = N0.getOperand(1);
14647 if (N0.getOperand(1) == Mask)
14648 Y = N0.getOperand(0);
14650 // Check to see if the mask appeared in both the AND and ANDNP and
14654 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14655 // Look through mask bitcast.
14656 if (Mask.getOpcode() == ISD::BITCAST)
14657 Mask = Mask.getOperand(0);
14658 if (X.getOpcode() == ISD::BITCAST)
14659 X = X.getOperand(0);
14660 if (Y.getOpcode() == ISD::BITCAST)
14661 Y = Y.getOperand(0);
14663 EVT MaskVT = Mask.getValueType();
14665 // Validate that the Mask operand is a vector sra node.
14666 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14667 // there is no psrai.b
14668 if (Mask.getOpcode() != X86ISD::VSRAI)
14671 // Check that the SRA is all signbits.
14672 SDValue SraC = Mask.getOperand(1);
14673 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14674 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14675 if ((SraAmt + 1) != EltBits)
14678 DebugLoc DL = N->getDebugLoc();
14680 // Now we know we at least have a plendvb with the mask val. See if
14681 // we can form a psignb/w/d.
14682 // psign = x.type == y.type == mask.type && y = sub(0, x);
14683 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14684 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14685 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14686 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14687 "Unsupported VT for PSIGN");
14688 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14689 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14691 // PBLENDVB only available on SSE 4.1
14692 if (!Subtarget->hasSSE41())
14695 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14697 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14698 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14699 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14700 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14701 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14705 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14708 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14709 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14711 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14713 if (!N0.hasOneUse() || !N1.hasOneUse())
14716 SDValue ShAmt0 = N0.getOperand(1);
14717 if (ShAmt0.getValueType() != MVT::i8)
14719 SDValue ShAmt1 = N1.getOperand(1);
14720 if (ShAmt1.getValueType() != MVT::i8)
14722 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14723 ShAmt0 = ShAmt0.getOperand(0);
14724 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14725 ShAmt1 = ShAmt1.getOperand(0);
14727 DebugLoc DL = N->getDebugLoc();
14728 unsigned Opc = X86ISD::SHLD;
14729 SDValue Op0 = N0.getOperand(0);
14730 SDValue Op1 = N1.getOperand(0);
14731 if (ShAmt0.getOpcode() == ISD::SUB) {
14732 Opc = X86ISD::SHRD;
14733 std::swap(Op0, Op1);
14734 std::swap(ShAmt0, ShAmt1);
14737 unsigned Bits = VT.getSizeInBits();
14738 if (ShAmt1.getOpcode() == ISD::SUB) {
14739 SDValue Sum = ShAmt1.getOperand(0);
14740 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14741 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14742 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14743 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14744 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14745 return DAG.getNode(Opc, DL, VT,
14747 DAG.getNode(ISD::TRUNCATE, DL,
14750 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14751 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14753 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14754 return DAG.getNode(Opc, DL, VT,
14755 N0.getOperand(0), N1.getOperand(0),
14756 DAG.getNode(ISD::TRUNCATE, DL,
14763 // Generate NEG and CMOV for integer abs.
14764 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14765 EVT VT = N->getValueType(0);
14767 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14768 // 8-bit integer abs to NEG and CMOV.
14769 if (VT.isInteger() && VT.getSizeInBits() == 8)
14772 SDValue N0 = N->getOperand(0);
14773 SDValue N1 = N->getOperand(1);
14774 DebugLoc DL = N->getDebugLoc();
14776 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14777 // and change it to SUB and CMOV.
14778 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14779 N0.getOpcode() == ISD::ADD &&
14780 N0.getOperand(1) == N1 &&
14781 N1.getOpcode() == ISD::SRA &&
14782 N1.getOperand(0) == N0.getOperand(0))
14783 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14784 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14785 // Generate SUB & CMOV.
14786 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14787 DAG.getConstant(0, VT), N0.getOperand(0));
14789 SDValue Ops[] = { N0.getOperand(0), Neg,
14790 DAG.getConstant(X86::COND_GE, MVT::i8),
14791 SDValue(Neg.getNode(), 1) };
14792 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14793 Ops, array_lengthof(Ops));
14798 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14799 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14800 TargetLowering::DAGCombinerInfo &DCI,
14801 const X86Subtarget *Subtarget) {
14802 if (DCI.isBeforeLegalizeOps())
14805 if (Subtarget->hasCMov()) {
14806 SDValue RV = performIntegerAbsCombine(N, DAG);
14811 // Try forming BMI if it is available.
14812 if (!Subtarget->hasBMI())
14815 EVT VT = N->getValueType(0);
14817 if (VT != MVT::i32 && VT != MVT::i64)
14820 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14822 // Create BLSMSK instructions by finding X ^ (X-1)
14823 SDValue N0 = N->getOperand(0);
14824 SDValue N1 = N->getOperand(1);
14825 DebugLoc DL = N->getDebugLoc();
14827 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14828 isAllOnes(N0.getOperand(1)))
14829 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14831 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14832 isAllOnes(N1.getOperand(1)))
14833 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14838 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14839 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14840 TargetLowering::DAGCombinerInfo &DCI,
14841 const X86Subtarget *Subtarget) {
14842 LoadSDNode *Ld = cast<LoadSDNode>(N);
14843 EVT RegVT = Ld->getValueType(0);
14844 EVT MemVT = Ld->getMemoryVT();
14845 DebugLoc dl = Ld->getDebugLoc();
14846 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14848 ISD::LoadExtType Ext = Ld->getExtensionType();
14850 // If this is a vector EXT Load then attempt to optimize it using a
14851 // shuffle. We need SSE4 for the shuffles.
14852 // TODO: It is possible to support ZExt by zeroing the undef values
14853 // during the shuffle phase or after the shuffle.
14854 if (RegVT.isVector() && RegVT.isInteger() &&
14855 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14856 assert(MemVT != RegVT && "Cannot extend to the same type");
14857 assert(MemVT.isVector() && "Must load a vector from memory");
14859 unsigned NumElems = RegVT.getVectorNumElements();
14860 unsigned RegSz = RegVT.getSizeInBits();
14861 unsigned MemSz = MemVT.getSizeInBits();
14862 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14864 // All sizes must be a power of two.
14865 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
14868 // Attempt to load the original value using scalar loads.
14869 // Find the largest scalar type that divides the total loaded size.
14870 MVT SclrLoadTy = MVT::i8;
14871 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14872 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14873 MVT Tp = (MVT::SimpleValueType)tp;
14874 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14879 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14880 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14882 SclrLoadTy = MVT::f64;
14884 // Calculate the number of scalar loads that we need to perform
14885 // in order to load our vector from memory.
14886 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14888 // Represent our vector as a sequence of elements which are the
14889 // largest scalar that we can load.
14890 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14891 RegSz/SclrLoadTy.getSizeInBits());
14893 // Represent the data using the same element type that is stored in
14894 // memory. In practice, we ''widen'' MemVT.
14895 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14896 RegSz/MemVT.getScalarType().getSizeInBits());
14898 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14899 "Invalid vector type");
14901 // We can't shuffle using an illegal type.
14902 if (!TLI.isTypeLegal(WideVecVT))
14905 SmallVector<SDValue, 8> Chains;
14906 SDValue Ptr = Ld->getBasePtr();
14907 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
14908 TLI.getPointerTy());
14909 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14911 for (unsigned i = 0; i < NumLoads; ++i) {
14912 // Perform a single load.
14913 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14914 Ptr, Ld->getPointerInfo(),
14915 Ld->isVolatile(), Ld->isNonTemporal(),
14916 Ld->isInvariant(), Ld->getAlignment());
14917 Chains.push_back(ScalarLoad.getValue(1));
14918 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14919 // another round of DAGCombining.
14921 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14923 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14924 ScalarLoad, DAG.getIntPtrConstant(i));
14926 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14929 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14932 // Bitcast the loaded value to a vector of the original element type, in
14933 // the size of the target vector type.
14934 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14935 unsigned SizeRatio = RegSz/MemSz;
14937 // Redistribute the loaded elements into the different locations.
14938 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14939 for (unsigned i = 0; i != NumElems; ++i)
14940 ShuffleVec[i*SizeRatio] = i;
14942 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14943 DAG.getUNDEF(WideVecVT),
14946 // Bitcast to the requested type.
14947 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14948 // Replace the original load with the new sequence
14949 // and return the new chain.
14950 return DCI.CombineTo(N, Shuff, TF, true);
14956 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14957 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14958 const X86Subtarget *Subtarget) {
14959 StoreSDNode *St = cast<StoreSDNode>(N);
14960 EVT VT = St->getValue().getValueType();
14961 EVT StVT = St->getMemoryVT();
14962 DebugLoc dl = St->getDebugLoc();
14963 SDValue StoredVal = St->getOperand(1);
14964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14966 // If we are saving a concatenation of two XMM registers, perform two stores.
14967 // On Sandy Bridge, 256-bit memory operations are executed by two
14968 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14969 // memory operation.
14970 if (VT.is256BitVector() && !Subtarget->hasAVX2() &&
14971 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14972 StoredVal.getNumOperands() == 2) {
14973 SDValue Value0 = StoredVal.getOperand(0);
14974 SDValue Value1 = StoredVal.getOperand(1);
14976 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14977 SDValue Ptr0 = St->getBasePtr();
14978 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14980 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14981 St->getPointerInfo(), St->isVolatile(),
14982 St->isNonTemporal(), St->getAlignment());
14983 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14984 St->getPointerInfo(), St->isVolatile(),
14985 St->isNonTemporal(), St->getAlignment());
14986 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14989 // Optimize trunc store (of multiple scalars) to shuffle and store.
14990 // First, pack all of the elements in one place. Next, store to memory
14991 // in fewer chunks.
14992 if (St->isTruncatingStore() && VT.isVector()) {
14993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14994 unsigned NumElems = VT.getVectorNumElements();
14995 assert(StVT != VT && "Cannot truncate to the same type");
14996 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14997 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14999 // From, To sizes and ElemCount must be pow of two
15000 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
15001 // We are going to use the original vector elt for storing.
15002 // Accumulated smaller vector elements must be a multiple of the store size.
15003 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
15005 unsigned SizeRatio = FromSz / ToSz;
15007 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
15009 // Create a type on which we perform the shuffle
15010 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
15011 StVT.getScalarType(), NumElems*SizeRatio);
15013 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
15015 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
15016 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
15017 for (unsigned i = 0; i != NumElems; ++i)
15018 ShuffleVec[i] = i * SizeRatio;
15020 // Can't shuffle using an illegal type.
15021 if (!TLI.isTypeLegal(WideVecVT))
15024 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
15025 DAG.getUNDEF(WideVecVT),
15027 // At this point all of the data is stored at the bottom of the
15028 // register. We now need to save it to mem.
15030 // Find the largest store unit
15031 MVT StoreType = MVT::i8;
15032 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15033 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15034 MVT Tp = (MVT::SimpleValueType)tp;
15035 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
15039 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15040 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
15041 (64 <= NumElems * ToSz))
15042 StoreType = MVT::f64;
15044 // Bitcast the original vector into a vector of store-size units
15045 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
15046 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
15047 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
15048 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
15049 SmallVector<SDValue, 8> Chains;
15050 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
15051 TLI.getPointerTy());
15052 SDValue Ptr = St->getBasePtr();
15054 // Perform one or more big stores into memory.
15055 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
15056 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
15057 StoreType, ShuffWide,
15058 DAG.getIntPtrConstant(i));
15059 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
15060 St->getPointerInfo(), St->isVolatile(),
15061 St->isNonTemporal(), St->getAlignment());
15062 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15063 Chains.push_back(Ch);
15066 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
15071 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
15072 // the FP state in cases where an emms may be missing.
15073 // A preferable solution to the general problem is to figure out the right
15074 // places to insert EMMS. This qualifies as a quick hack.
15076 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
15077 if (VT.getSizeInBits() != 64)
15080 const Function *F = DAG.getMachineFunction().getFunction();
15081 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
15082 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
15083 && Subtarget->hasSSE2();
15084 if ((VT.isVector() ||
15085 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
15086 isa<LoadSDNode>(St->getValue()) &&
15087 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
15088 St->getChain().hasOneUse() && !St->isVolatile()) {
15089 SDNode* LdVal = St->getValue().getNode();
15090 LoadSDNode *Ld = 0;
15091 int TokenFactorIndex = -1;
15092 SmallVector<SDValue, 8> Ops;
15093 SDNode* ChainVal = St->getChain().getNode();
15094 // Must be a store of a load. We currently handle two cases: the load
15095 // is a direct child, and it's under an intervening TokenFactor. It is
15096 // possible to dig deeper under nested TokenFactors.
15097 if (ChainVal == LdVal)
15098 Ld = cast<LoadSDNode>(St->getChain());
15099 else if (St->getValue().hasOneUse() &&
15100 ChainVal->getOpcode() == ISD::TokenFactor) {
15101 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
15102 if (ChainVal->getOperand(i).getNode() == LdVal) {
15103 TokenFactorIndex = i;
15104 Ld = cast<LoadSDNode>(St->getValue());
15106 Ops.push_back(ChainVal->getOperand(i));
15110 if (!Ld || !ISD::isNormalLoad(Ld))
15113 // If this is not the MMX case, i.e. we are just turning i64 load/store
15114 // into f64 load/store, avoid the transformation if there are multiple
15115 // uses of the loaded value.
15116 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
15119 DebugLoc LdDL = Ld->getDebugLoc();
15120 DebugLoc StDL = N->getDebugLoc();
15121 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
15122 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
15124 if (Subtarget->is64Bit() || F64IsLegal) {
15125 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
15126 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
15127 Ld->getPointerInfo(), Ld->isVolatile(),
15128 Ld->isNonTemporal(), Ld->isInvariant(),
15129 Ld->getAlignment());
15130 SDValue NewChain = NewLd.getValue(1);
15131 if (TokenFactorIndex != -1) {
15132 Ops.push_back(NewChain);
15133 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
15136 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
15137 St->getPointerInfo(),
15138 St->isVolatile(), St->isNonTemporal(),
15139 St->getAlignment());
15142 // Otherwise, lower to two pairs of 32-bit loads / stores.
15143 SDValue LoAddr = Ld->getBasePtr();
15144 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
15145 DAG.getConstant(4, MVT::i32));
15147 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
15148 Ld->getPointerInfo(),
15149 Ld->isVolatile(), Ld->isNonTemporal(),
15150 Ld->isInvariant(), Ld->getAlignment());
15151 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
15152 Ld->getPointerInfo().getWithOffset(4),
15153 Ld->isVolatile(), Ld->isNonTemporal(),
15155 MinAlign(Ld->getAlignment(), 4));
15157 SDValue NewChain = LoLd.getValue(1);
15158 if (TokenFactorIndex != -1) {
15159 Ops.push_back(LoLd);
15160 Ops.push_back(HiLd);
15161 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
15165 LoAddr = St->getBasePtr();
15166 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
15167 DAG.getConstant(4, MVT::i32));
15169 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
15170 St->getPointerInfo(),
15171 St->isVolatile(), St->isNonTemporal(),
15172 St->getAlignment());
15173 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
15174 St->getPointerInfo().getWithOffset(4),
15176 St->isNonTemporal(),
15177 MinAlign(St->getAlignment(), 4));
15178 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
15183 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
15184 /// and return the operands for the horizontal operation in LHS and RHS. A
15185 /// horizontal operation performs the binary operation on successive elements
15186 /// of its first operand, then on successive elements of its second operand,
15187 /// returning the resulting values in a vector. For example, if
15188 /// A = < float a0, float a1, float a2, float a3 >
15190 /// B = < float b0, float b1, float b2, float b3 >
15191 /// then the result of doing a horizontal operation on A and B is
15192 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
15193 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
15194 /// A horizontal-op B, for some already available A and B, and if so then LHS is
15195 /// set to A, RHS to B, and the routine returns 'true'.
15196 /// Note that the binary operation should have the property that if one of the
15197 /// operands is UNDEF then the result is UNDEF.
15198 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
15199 // Look for the following pattern: if
15200 // A = < float a0, float a1, float a2, float a3 >
15201 // B = < float b0, float b1, float b2, float b3 >
15203 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
15204 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
15205 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
15206 // which is A horizontal-op B.
15208 // At least one of the operands should be a vector shuffle.
15209 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
15210 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
15213 EVT VT = LHS.getValueType();
15215 assert((VT.is128BitVector() || VT.is256BitVector()) &&
15216 "Unsupported vector type for horizontal add/sub");
15218 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
15219 // operate independently on 128-bit lanes.
15220 unsigned NumElts = VT.getVectorNumElements();
15221 unsigned NumLanes = VT.getSizeInBits()/128;
15222 unsigned NumLaneElts = NumElts / NumLanes;
15223 assert((NumLaneElts % 2 == 0) &&
15224 "Vector type should have an even number of elements in each lane");
15225 unsigned HalfLaneElts = NumLaneElts/2;
15227 // View LHS in the form
15228 // LHS = VECTOR_SHUFFLE A, B, LMask
15229 // If LHS is not a shuffle then pretend it is the shuffle
15230 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
15231 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
15234 SmallVector<int, 16> LMask(NumElts);
15235 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15236 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
15237 A = LHS.getOperand(0);
15238 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
15239 B = LHS.getOperand(1);
15240 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
15241 std::copy(Mask.begin(), Mask.end(), LMask.begin());
15243 if (LHS.getOpcode() != ISD::UNDEF)
15245 for (unsigned i = 0; i != NumElts; ++i)
15249 // Likewise, view RHS in the form
15250 // RHS = VECTOR_SHUFFLE C, D, RMask
15252 SmallVector<int, 16> RMask(NumElts);
15253 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15254 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
15255 C = RHS.getOperand(0);
15256 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
15257 D = RHS.getOperand(1);
15258 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
15259 std::copy(Mask.begin(), Mask.end(), RMask.begin());
15261 if (RHS.getOpcode() != ISD::UNDEF)
15263 for (unsigned i = 0; i != NumElts; ++i)
15267 // Check that the shuffles are both shuffling the same vectors.
15268 if (!(A == C && B == D) && !(A == D && B == C))
15271 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
15272 if (!A.getNode() && !B.getNode())
15275 // If A and B occur in reverse order in RHS, then "swap" them (which means
15276 // rewriting the mask).
15278 CommuteVectorShuffleMask(RMask, NumElts);
15280 // At this point LHS and RHS are equivalent to
15281 // LHS = VECTOR_SHUFFLE A, B, LMask
15282 // RHS = VECTOR_SHUFFLE A, B, RMask
15283 // Check that the masks correspond to performing a horizontal operation.
15284 for (unsigned i = 0; i != NumElts; ++i) {
15285 int LIdx = LMask[i], RIdx = RMask[i];
15287 // Ignore any UNDEF components.
15288 if (LIdx < 0 || RIdx < 0 ||
15289 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
15290 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
15293 // Check that successive elements are being operated on. If not, this is
15294 // not a horizontal operation.
15295 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
15296 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
15297 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
15298 if (!(LIdx == Index && RIdx == Index + 1) &&
15299 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
15303 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
15304 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
15308 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
15309 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
15310 const X86Subtarget *Subtarget) {
15311 EVT VT = N->getValueType(0);
15312 SDValue LHS = N->getOperand(0);
15313 SDValue RHS = N->getOperand(1);
15315 // Try to synthesize horizontal adds from adds of shuffles.
15316 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15317 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15318 isHorizontalBinOp(LHS, RHS, true))
15319 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
15323 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
15324 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
15325 const X86Subtarget *Subtarget) {
15326 EVT VT = N->getValueType(0);
15327 SDValue LHS = N->getOperand(0);
15328 SDValue RHS = N->getOperand(1);
15330 // Try to synthesize horizontal subs from subs of shuffles.
15331 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15332 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15333 isHorizontalBinOp(LHS, RHS, false))
15334 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
15338 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
15339 /// X86ISD::FXOR nodes.
15340 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
15341 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
15342 // F[X]OR(0.0, x) -> x
15343 // F[X]OR(x, 0.0) -> x
15344 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15345 if (C->getValueAPF().isPosZero())
15346 return N->getOperand(1);
15347 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15348 if (C->getValueAPF().isPosZero())
15349 return N->getOperand(0);
15353 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
15354 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
15355 // FAND(0.0, x) -> 0.0
15356 // FAND(x, 0.0) -> 0.0
15357 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15358 if (C->getValueAPF().isPosZero())
15359 return N->getOperand(0);
15360 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15361 if (C->getValueAPF().isPosZero())
15362 return N->getOperand(1);
15366 static SDValue PerformBTCombine(SDNode *N,
15368 TargetLowering::DAGCombinerInfo &DCI) {
15369 // BT ignores high bits in the bit index operand.
15370 SDValue Op1 = N->getOperand(1);
15371 if (Op1.hasOneUse()) {
15372 unsigned BitWidth = Op1.getValueSizeInBits();
15373 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
15374 APInt KnownZero, KnownOne;
15375 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15376 !DCI.isBeforeLegalizeOps());
15377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15378 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
15379 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
15380 DCI.CommitTargetLoweringOpt(TLO);
15385 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
15386 SDValue Op = N->getOperand(0);
15387 if (Op.getOpcode() == ISD::BITCAST)
15388 Op = Op.getOperand(0);
15389 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
15390 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
15391 VT.getVectorElementType().getSizeInBits() ==
15392 OpVT.getVectorElementType().getSizeInBits()) {
15393 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
15398 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
15399 TargetLowering::DAGCombinerInfo &DCI,
15400 const X86Subtarget *Subtarget) {
15401 if (!DCI.isBeforeLegalizeOps())
15404 if (!Subtarget->hasAVX())
15407 EVT VT = N->getValueType(0);
15408 SDValue Op = N->getOperand(0);
15409 EVT OpVT = Op.getValueType();
15410 DebugLoc dl = N->getDebugLoc();
15412 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15413 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15415 if (Subtarget->hasAVX2())
15416 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15418 // Optimize vectors in AVX mode
15419 // Sign extend v8i16 to v8i32 and
15422 // Divide input vector into two parts
15423 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15424 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15425 // concat the vectors to original VT
15427 unsigned NumElems = OpVT.getVectorNumElements();
15428 SDValue Undef = DAG.getUNDEF(OpVT);
15430 SmallVector<int,8> ShufMask1(NumElems, -1);
15431 for (unsigned i = 0; i != NumElems/2; ++i)
15434 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]);
15436 SmallVector<int,8> ShufMask2(NumElems, -1);
15437 for (unsigned i = 0; i != NumElems/2; ++i)
15438 ShufMask2[i] = i + NumElems/2;
15440 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]);
15442 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15443 VT.getVectorNumElements()/2);
15445 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15446 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15448 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15453 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
15454 const X86Subtarget* Subtarget) {
15455 DebugLoc dl = N->getDebugLoc();
15456 EVT VT = N->getValueType(0);
15458 EVT ScalarVT = VT.getScalarType();
15459 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasFMA())
15462 SDValue A = N->getOperand(0);
15463 SDValue B = N->getOperand(1);
15464 SDValue C = N->getOperand(2);
15466 bool NegA = (A.getOpcode() == ISD::FNEG);
15467 bool NegB = (B.getOpcode() == ISD::FNEG);
15468 bool NegC = (C.getOpcode() == ISD::FNEG);
15470 // Negative multiplication when NegA xor NegB
15471 bool NegMul = (NegA != NegB);
15473 A = A.getOperand(0);
15475 B = B.getOperand(0);
15477 C = C.getOperand(0);
15481 Opcode = (!NegC)? X86ISD::FMADD : X86ISD::FMSUB;
15483 Opcode = (!NegC)? X86ISD::FNMADD : X86ISD::FNMSUB;
15484 return DAG.getNode(Opcode, dl, VT, A, B, C);
15487 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15488 TargetLowering::DAGCombinerInfo &DCI,
15489 const X86Subtarget *Subtarget) {
15490 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15491 // (and (i32 x86isd::setcc_carry), 1)
15492 // This eliminates the zext. This transformation is necessary because
15493 // ISD::SETCC is always legalized to i8.
15494 DebugLoc dl = N->getDebugLoc();
15495 SDValue N0 = N->getOperand(0);
15496 EVT VT = N->getValueType(0);
15497 EVT OpVT = N0.getValueType();
15499 if (N0.getOpcode() == ISD::AND &&
15501 N0.getOperand(0).hasOneUse()) {
15502 SDValue N00 = N0.getOperand(0);
15503 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15505 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15506 if (!C || C->getZExtValue() != 1)
15508 return DAG.getNode(ISD::AND, dl, VT,
15509 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15510 N00.getOperand(0), N00.getOperand(1)),
15511 DAG.getConstant(1, VT));
15514 // Optimize vectors in AVX mode:
15517 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15518 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15519 // Concat upper and lower parts.
15522 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15523 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15524 // Concat upper and lower parts.
15526 if (!DCI.isBeforeLegalizeOps())
15529 if (!Subtarget->hasAVX())
15532 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15533 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15535 if (Subtarget->hasAVX2())
15536 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15538 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15539 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15540 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15542 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15543 VT.getVectorNumElements()/2);
15545 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15546 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15548 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15554 // Optimize x == -y --> x+y == 0
15555 // x != -y --> x+y != 0
15556 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15557 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15558 SDValue LHS = N->getOperand(0);
15559 SDValue RHS = N->getOperand(1);
15561 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15563 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15564 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15565 LHS.getValueType(), RHS, LHS.getOperand(1));
15566 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15567 addV, DAG.getConstant(0, addV.getValueType()), CC);
15569 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15570 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15571 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15572 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15573 RHS.getValueType(), LHS, RHS.getOperand(1));
15574 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15575 addV, DAG.getConstant(0, addV.getValueType()), CC);
15580 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15581 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15582 DebugLoc DL = N->getDebugLoc();
15583 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
15584 SDValue EFLAGS = N->getOperand(1);
15586 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15587 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15589 if (CC == X86::COND_B)
15590 return DAG.getNode(ISD::AND, DL, MVT::i8,
15591 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15592 DAG.getConstant(CC, MVT::i8), EFLAGS),
15593 DAG.getConstant(1, MVT::i8));
15597 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15598 if (Flags.getNode()) {
15599 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15600 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
15606 // Optimize branch condition evaluation.
15608 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
15609 TargetLowering::DAGCombinerInfo &DCI,
15610 const X86Subtarget *Subtarget) {
15611 DebugLoc DL = N->getDebugLoc();
15612 SDValue Chain = N->getOperand(0);
15613 SDValue Dest = N->getOperand(1);
15614 SDValue EFLAGS = N->getOperand(3);
15615 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
15619 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15620 if (Flags.getNode()) {
15621 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15622 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
15629 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15630 SDValue Op0 = N->getOperand(0);
15631 EVT InVT = Op0->getValueType(0);
15633 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15634 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15635 DebugLoc dl = N->getDebugLoc();
15636 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15637 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15638 // Notice that we use SINT_TO_FP because we know that the high bits
15639 // are zero and SINT_TO_FP is better supported by the hardware.
15640 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15646 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15647 const X86TargetLowering *XTLI) {
15648 SDValue Op0 = N->getOperand(0);
15649 EVT InVT = Op0->getValueType(0);
15651 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15652 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15653 DebugLoc dl = N->getDebugLoc();
15654 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15655 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15656 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15659 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15660 // a 32-bit target where SSE doesn't support i64->FP operations.
15661 if (Op0.getOpcode() == ISD::LOAD) {
15662 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15663 EVT VT = Ld->getValueType(0);
15664 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15665 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15666 !XTLI->getSubtarget()->is64Bit() &&
15667 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15668 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15669 Ld->getChain(), Op0, DAG);
15670 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15677 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15678 EVT VT = N->getValueType(0);
15680 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15681 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15682 DebugLoc dl = N->getDebugLoc();
15683 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15684 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15685 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15691 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15692 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15693 X86TargetLowering::DAGCombinerInfo &DCI) {
15694 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15695 // the result is either zero or one (depending on the input carry bit).
15696 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15697 if (X86::isZeroNode(N->getOperand(0)) &&
15698 X86::isZeroNode(N->getOperand(1)) &&
15699 // We don't have a good way to replace an EFLAGS use, so only do this when
15701 SDValue(N, 1).use_empty()) {
15702 DebugLoc DL = N->getDebugLoc();
15703 EVT VT = N->getValueType(0);
15704 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15705 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15706 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15707 DAG.getConstant(X86::COND_B,MVT::i8),
15709 DAG.getConstant(1, VT));
15710 return DCI.CombineTo(N, Res1, CarryOut);
15716 // fold (add Y, (sete X, 0)) -> adc 0, Y
15717 // (add Y, (setne X, 0)) -> sbb -1, Y
15718 // (sub (sete X, 0), Y) -> sbb 0, Y
15719 // (sub (setne X, 0), Y) -> adc -1, Y
15720 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15721 DebugLoc DL = N->getDebugLoc();
15723 // Look through ZExts.
15724 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15725 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15728 SDValue SetCC = Ext.getOperand(0);
15729 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15732 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15733 if (CC != X86::COND_E && CC != X86::COND_NE)
15736 SDValue Cmp = SetCC.getOperand(1);
15737 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15738 !X86::isZeroNode(Cmp.getOperand(1)) ||
15739 !Cmp.getOperand(0).getValueType().isInteger())
15742 SDValue CmpOp0 = Cmp.getOperand(0);
15743 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15744 DAG.getConstant(1, CmpOp0.getValueType()));
15746 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15747 if (CC == X86::COND_NE)
15748 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15749 DL, OtherVal.getValueType(), OtherVal,
15750 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15751 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15752 DL, OtherVal.getValueType(), OtherVal,
15753 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15756 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15757 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15758 const X86Subtarget *Subtarget) {
15759 EVT VT = N->getValueType(0);
15760 SDValue Op0 = N->getOperand(0);
15761 SDValue Op1 = N->getOperand(1);
15763 // Try to synthesize horizontal adds from adds of shuffles.
15764 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15765 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15766 isHorizontalBinOp(Op0, Op1, true))
15767 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15769 return OptimizeConditionalInDecrement(N, DAG);
15772 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15773 const X86Subtarget *Subtarget) {
15774 SDValue Op0 = N->getOperand(0);
15775 SDValue Op1 = N->getOperand(1);
15777 // X86 can't encode an immediate LHS of a sub. See if we can push the
15778 // negation into a preceding instruction.
15779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15780 // If the RHS of the sub is a XOR with one use and a constant, invert the
15781 // immediate. Then add one to the LHS of the sub so we can turn
15782 // X-Y -> X+~Y+1, saving one register.
15783 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15784 isa<ConstantSDNode>(Op1.getOperand(1))) {
15785 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15786 EVT VT = Op0.getValueType();
15787 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15789 DAG.getConstant(~XorC, VT));
15790 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15791 DAG.getConstant(C->getAPIntValue()+1, VT));
15795 // Try to synthesize horizontal adds from adds of shuffles.
15796 EVT VT = N->getValueType(0);
15797 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15798 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15799 isHorizontalBinOp(Op0, Op1, true))
15800 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15802 return OptimizeConditionalInDecrement(N, DAG);
15805 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15806 DAGCombinerInfo &DCI) const {
15807 SelectionDAG &DAG = DCI.DAG;
15808 switch (N->getOpcode()) {
15810 case ISD::EXTRACT_VECTOR_ELT:
15811 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15813 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15814 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15815 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15816 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15817 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15818 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15821 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15822 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15823 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15824 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15825 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
15826 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15827 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15828 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15829 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15830 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15831 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15833 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15834 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15835 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15836 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15837 case ISD::ANY_EXTEND:
15838 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15839 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15840 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15841 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15842 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15843 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
15844 case X86ISD::SHUFP: // Handle all target specific shuffles
15845 case X86ISD::PALIGN:
15846 case X86ISD::UNPCKH:
15847 case X86ISD::UNPCKL:
15848 case X86ISD::MOVHLPS:
15849 case X86ISD::MOVLHPS:
15850 case X86ISD::PSHUFD:
15851 case X86ISD::PSHUFHW:
15852 case X86ISD::PSHUFLW:
15853 case X86ISD::MOVSS:
15854 case X86ISD::MOVSD:
15855 case X86ISD::VPERMILP:
15856 case X86ISD::VPERM2X128:
15857 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15858 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
15864 /// isTypeDesirableForOp - Return true if the target has native support for
15865 /// the specified value type and it is 'desirable' to use the type for the
15866 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15867 /// instruction encodings are longer and some i16 instructions are slow.
15868 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15869 if (!isTypeLegal(VT))
15871 if (VT != MVT::i16)
15878 case ISD::SIGN_EXTEND:
15879 case ISD::ZERO_EXTEND:
15880 case ISD::ANY_EXTEND:
15893 /// IsDesirableToPromoteOp - This method query the target whether it is
15894 /// beneficial for dag combiner to promote the specified node. If true, it
15895 /// should return the desired promotion type by reference.
15896 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15897 EVT VT = Op.getValueType();
15898 if (VT != MVT::i16)
15901 bool Promote = false;
15902 bool Commute = false;
15903 switch (Op.getOpcode()) {
15906 LoadSDNode *LD = cast<LoadSDNode>(Op);
15907 // If the non-extending load has a single use and it's not live out, then it
15908 // might be folded.
15909 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15910 Op.hasOneUse()*/) {
15911 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15912 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15913 // The only case where we'd want to promote LOAD (rather then it being
15914 // promoted as an operand is when it's only use is liveout.
15915 if (UI->getOpcode() != ISD::CopyToReg)
15922 case ISD::SIGN_EXTEND:
15923 case ISD::ZERO_EXTEND:
15924 case ISD::ANY_EXTEND:
15929 SDValue N0 = Op.getOperand(0);
15930 // Look out for (store (shl (load), x)).
15931 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15944 SDValue N0 = Op.getOperand(0);
15945 SDValue N1 = Op.getOperand(1);
15946 if (!Commute && MayFoldLoad(N1))
15948 // Avoid disabling potential load folding opportunities.
15949 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15951 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15961 //===----------------------------------------------------------------------===//
15962 // X86 Inline Assembly Support
15963 //===----------------------------------------------------------------------===//
15966 // Helper to match a string separated by whitespace.
15967 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15968 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15970 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15971 StringRef piece(*args[i]);
15972 if (!s.startswith(piece)) // Check if the piece matches.
15975 s = s.substr(piece.size());
15976 StringRef::size_type pos = s.find_first_not_of(" \t");
15977 if (pos == 0) // We matched a prefix.
15985 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15988 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15989 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15991 std::string AsmStr = IA->getAsmString();
15993 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15994 if (!Ty || Ty->getBitWidth() % 16 != 0)
15997 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15998 SmallVector<StringRef, 4> AsmPieces;
15999 SplitString(AsmStr, AsmPieces, ";\n");
16001 switch (AsmPieces.size()) {
16002 default: return false;
16004 // FIXME: this should verify that we are targeting a 486 or better. If not,
16005 // we will turn this bswap into something that will be lowered to logical
16006 // ops instead of emitting the bswap asm. For now, we don't support 486 or
16007 // lower so don't worry about this.
16009 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
16010 matchAsm(AsmPieces[0], "bswapl", "$0") ||
16011 matchAsm(AsmPieces[0], "bswapq", "$0") ||
16012 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
16013 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
16014 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
16015 // No need to check constraints, nothing other than the equivalent of
16016 // "=r,0" would be valid here.
16017 return IntrinsicLowering::LowerToByteSwap(CI);
16020 // rorw $$8, ${0:w} --> llvm.bswap.i16
16021 if (CI->getType()->isIntegerTy(16) &&
16022 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
16023 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
16024 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
16026 const std::string &ConstraintsStr = IA->getConstraintString();
16027 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
16028 std::sort(AsmPieces.begin(), AsmPieces.end());
16029 if (AsmPieces.size() == 4 &&
16030 AsmPieces[0] == "~{cc}" &&
16031 AsmPieces[1] == "~{dirflag}" &&
16032 AsmPieces[2] == "~{flags}" &&
16033 AsmPieces[3] == "~{fpsr}")
16034 return IntrinsicLowering::LowerToByteSwap(CI);
16038 if (CI->getType()->isIntegerTy(32) &&
16039 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
16040 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
16041 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
16042 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
16044 const std::string &ConstraintsStr = IA->getConstraintString();
16045 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
16046 std::sort(AsmPieces.begin(), AsmPieces.end());
16047 if (AsmPieces.size() == 4 &&
16048 AsmPieces[0] == "~{cc}" &&
16049 AsmPieces[1] == "~{dirflag}" &&
16050 AsmPieces[2] == "~{flags}" &&
16051 AsmPieces[3] == "~{fpsr}")
16052 return IntrinsicLowering::LowerToByteSwap(CI);
16055 if (CI->getType()->isIntegerTy(64)) {
16056 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
16057 if (Constraints.size() >= 2 &&
16058 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
16059 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
16060 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
16061 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
16062 matchAsm(AsmPieces[1], "bswap", "%edx") &&
16063 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
16064 return IntrinsicLowering::LowerToByteSwap(CI);
16074 /// getConstraintType - Given a constraint letter, return the type of
16075 /// constraint it is for this target.
16076 X86TargetLowering::ConstraintType
16077 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
16078 if (Constraint.size() == 1) {
16079 switch (Constraint[0]) {
16090 return C_RegisterClass;
16114 return TargetLowering::getConstraintType(Constraint);
16117 /// Examine constraint type and operand type and determine a weight value.
16118 /// This object must already have been set up with the operand type
16119 /// and the current alternative constraint selected.
16120 TargetLowering::ConstraintWeight
16121 X86TargetLowering::getSingleConstraintMatchWeight(
16122 AsmOperandInfo &info, const char *constraint) const {
16123 ConstraintWeight weight = CW_Invalid;
16124 Value *CallOperandVal = info.CallOperandVal;
16125 // If we don't have a value, we can't do a match,
16126 // but allow it at the lowest weight.
16127 if (CallOperandVal == NULL)
16129 Type *type = CallOperandVal->getType();
16130 // Look at the constraint type.
16131 switch (*constraint) {
16133 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
16144 if (CallOperandVal->getType()->isIntegerTy())
16145 weight = CW_SpecificReg;
16150 if (type->isFloatingPointTy())
16151 weight = CW_SpecificReg;
16154 if (type->isX86_MMXTy() && Subtarget->hasMMX())
16155 weight = CW_SpecificReg;
16159 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
16160 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
16161 weight = CW_Register;
16164 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
16165 if (C->getZExtValue() <= 31)
16166 weight = CW_Constant;
16170 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16171 if (C->getZExtValue() <= 63)
16172 weight = CW_Constant;
16176 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16177 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
16178 weight = CW_Constant;
16182 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16183 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
16184 weight = CW_Constant;
16188 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16189 if (C->getZExtValue() <= 3)
16190 weight = CW_Constant;
16194 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16195 if (C->getZExtValue() <= 0xff)
16196 weight = CW_Constant;
16201 if (dyn_cast<ConstantFP>(CallOperandVal)) {
16202 weight = CW_Constant;
16206 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16207 if ((C->getSExtValue() >= -0x80000000LL) &&
16208 (C->getSExtValue() <= 0x7fffffffLL))
16209 weight = CW_Constant;
16213 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16214 if (C->getZExtValue() <= 0xffffffff)
16215 weight = CW_Constant;
16222 /// LowerXConstraint - try to replace an X constraint, which matches anything,
16223 /// with another that has more specific requirements based on the type of the
16224 /// corresponding operand.
16225 const char *X86TargetLowering::
16226 LowerXConstraint(EVT ConstraintVT) const {
16227 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
16228 // 'f' like normal targets.
16229 if (ConstraintVT.isFloatingPoint()) {
16230 if (Subtarget->hasSSE2())
16232 if (Subtarget->hasSSE1())
16236 return TargetLowering::LowerXConstraint(ConstraintVT);
16239 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
16240 /// vector. If it is invalid, don't add anything to Ops.
16241 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
16242 std::string &Constraint,
16243 std::vector<SDValue>&Ops,
16244 SelectionDAG &DAG) const {
16245 SDValue Result(0, 0);
16247 // Only support length 1 constraints for now.
16248 if (Constraint.length() > 1) return;
16250 char ConstraintLetter = Constraint[0];
16251 switch (ConstraintLetter) {
16254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16255 if (C->getZExtValue() <= 31) {
16256 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16263 if (C->getZExtValue() <= 63) {
16264 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16271 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
16272 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16279 if (C->getZExtValue() <= 255) {
16280 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16286 // 32-bit signed value
16287 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16288 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16289 C->getSExtValue())) {
16290 // Widen to 64 bits here to get it sign extended.
16291 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
16294 // FIXME gcc accepts some relocatable values here too, but only in certain
16295 // memory models; it's complicated.
16300 // 32-bit unsigned value
16301 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16302 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16303 C->getZExtValue())) {
16304 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16308 // FIXME gcc accepts some relocatable values here too, but only in certain
16309 // memory models; it's complicated.
16313 // Literal immediates are always ok.
16314 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
16315 // Widen to 64 bits here to get it sign extended.
16316 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
16320 // In any sort of PIC mode addresses need to be computed at runtime by
16321 // adding in a register or some sort of table lookup. These can't
16322 // be used as immediates.
16323 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
16326 // If we are in non-pic codegen mode, we allow the address of a global (with
16327 // an optional displacement) to be used with 'i'.
16328 GlobalAddressSDNode *GA = 0;
16329 int64_t Offset = 0;
16331 // Match either (GA), (GA+C), (GA+C1+C2), etc.
16333 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
16334 Offset += GA->getOffset();
16336 } else if (Op.getOpcode() == ISD::ADD) {
16337 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16338 Offset += C->getZExtValue();
16339 Op = Op.getOperand(0);
16342 } else if (Op.getOpcode() == ISD::SUB) {
16343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16344 Offset += -C->getZExtValue();
16345 Op = Op.getOperand(0);
16350 // Otherwise, this isn't something we can handle, reject it.
16354 const GlobalValue *GV = GA->getGlobal();
16355 // If we require an extra load to get this address, as in PIC mode, we
16356 // can't accept it.
16357 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
16358 getTargetMachine())))
16361 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
16362 GA->getValueType(0), Offset);
16367 if (Result.getNode()) {
16368 Ops.push_back(Result);
16371 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
16374 std::pair<unsigned, const TargetRegisterClass*>
16375 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
16377 // First, see if this is a constraint that directly corresponds to an LLVM
16379 if (Constraint.size() == 1) {
16380 // GCC Constraint Letters
16381 switch (Constraint[0]) {
16383 // TODO: Slight differences here in allocation order and leaving
16384 // RIP in the class. Do they matter any more here than they do
16385 // in the normal allocation?
16386 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
16387 if (Subtarget->is64Bit()) {
16388 if (VT == MVT::i32 || VT == MVT::f32)
16389 return std::make_pair(0U, &X86::GR32RegClass);
16390 if (VT == MVT::i16)
16391 return std::make_pair(0U, &X86::GR16RegClass);
16392 if (VT == MVT::i8 || VT == MVT::i1)
16393 return std::make_pair(0U, &X86::GR8RegClass);
16394 if (VT == MVT::i64 || VT == MVT::f64)
16395 return std::make_pair(0U, &X86::GR64RegClass);
16398 // 32-bit fallthrough
16399 case 'Q': // Q_REGS
16400 if (VT == MVT::i32 || VT == MVT::f32)
16401 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
16402 if (VT == MVT::i16)
16403 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
16404 if (VT == MVT::i8 || VT == MVT::i1)
16405 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
16406 if (VT == MVT::i64)
16407 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
16409 case 'r': // GENERAL_REGS
16410 case 'l': // INDEX_REGS
16411 if (VT == MVT::i8 || VT == MVT::i1)
16412 return std::make_pair(0U, &X86::GR8RegClass);
16413 if (VT == MVT::i16)
16414 return std::make_pair(0U, &X86::GR16RegClass);
16415 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
16416 return std::make_pair(0U, &X86::GR32RegClass);
16417 return std::make_pair(0U, &X86::GR64RegClass);
16418 case 'R': // LEGACY_REGS
16419 if (VT == MVT::i8 || VT == MVT::i1)
16420 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
16421 if (VT == MVT::i16)
16422 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
16423 if (VT == MVT::i32 || !Subtarget->is64Bit())
16424 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
16425 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
16426 case 'f': // FP Stack registers.
16427 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
16428 // value to the correct fpstack register class.
16429 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
16430 return std::make_pair(0U, &X86::RFP32RegClass);
16431 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
16432 return std::make_pair(0U, &X86::RFP64RegClass);
16433 return std::make_pair(0U, &X86::RFP80RegClass);
16434 case 'y': // MMX_REGS if MMX allowed.
16435 if (!Subtarget->hasMMX()) break;
16436 return std::make_pair(0U, &X86::VR64RegClass);
16437 case 'Y': // SSE_REGS if SSE2 allowed
16438 if (!Subtarget->hasSSE2()) break;
16440 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
16441 if (!Subtarget->hasSSE1()) break;
16443 switch (VT.getSimpleVT().SimpleTy) {
16445 // Scalar SSE types.
16448 return std::make_pair(0U, &X86::FR32RegClass);
16451 return std::make_pair(0U, &X86::FR64RegClass);
16459 return std::make_pair(0U, &X86::VR128RegClass);
16467 return std::make_pair(0U, &X86::VR256RegClass);
16473 // Use the default implementation in TargetLowering to convert the register
16474 // constraint into a member of a register class.
16475 std::pair<unsigned, const TargetRegisterClass*> Res;
16476 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16478 // Not found as a standard register?
16479 if (Res.second == 0) {
16480 // Map st(0) -> st(7) -> ST0
16481 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16482 tolower(Constraint[1]) == 's' &&
16483 tolower(Constraint[2]) == 't' &&
16484 Constraint[3] == '(' &&
16485 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16486 Constraint[5] == ')' &&
16487 Constraint[6] == '}') {
16489 Res.first = X86::ST0+Constraint[4]-'0';
16490 Res.second = &X86::RFP80RegClass;
16494 // GCC allows "st(0)" to be called just plain "st".
16495 if (StringRef("{st}").equals_lower(Constraint)) {
16496 Res.first = X86::ST0;
16497 Res.second = &X86::RFP80RegClass;
16502 if (StringRef("{flags}").equals_lower(Constraint)) {
16503 Res.first = X86::EFLAGS;
16504 Res.second = &X86::CCRRegClass;
16508 // 'A' means EAX + EDX.
16509 if (Constraint == "A") {
16510 Res.first = X86::EAX;
16511 Res.second = &X86::GR32_ADRegClass;
16517 // Otherwise, check to see if this is a register class of the wrong value
16518 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16519 // turn into {ax},{dx}.
16520 if (Res.second->hasType(VT))
16521 return Res; // Correct type already, nothing to do.
16523 // All of the single-register GCC register classes map their values onto
16524 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16525 // really want an 8-bit or 32-bit register, map to the appropriate register
16526 // class and return the appropriate register.
16527 if (Res.second == &X86::GR16RegClass) {
16528 if (VT == MVT::i8) {
16529 unsigned DestReg = 0;
16530 switch (Res.first) {
16532 case X86::AX: DestReg = X86::AL; break;
16533 case X86::DX: DestReg = X86::DL; break;
16534 case X86::CX: DestReg = X86::CL; break;
16535 case X86::BX: DestReg = X86::BL; break;
16538 Res.first = DestReg;
16539 Res.second = &X86::GR8RegClass;
16541 } else if (VT == MVT::i32) {
16542 unsigned DestReg = 0;
16543 switch (Res.first) {
16545 case X86::AX: DestReg = X86::EAX; break;
16546 case X86::DX: DestReg = X86::EDX; break;
16547 case X86::CX: DestReg = X86::ECX; break;
16548 case X86::BX: DestReg = X86::EBX; break;
16549 case X86::SI: DestReg = X86::ESI; break;
16550 case X86::DI: DestReg = X86::EDI; break;
16551 case X86::BP: DestReg = X86::EBP; break;
16552 case X86::SP: DestReg = X86::ESP; break;
16555 Res.first = DestReg;
16556 Res.second = &X86::GR32RegClass;
16558 } else if (VT == MVT::i64) {
16559 unsigned DestReg = 0;
16560 switch (Res.first) {
16562 case X86::AX: DestReg = X86::RAX; break;
16563 case X86::DX: DestReg = X86::RDX; break;
16564 case X86::CX: DestReg = X86::RCX; break;
16565 case X86::BX: DestReg = X86::RBX; break;
16566 case X86::SI: DestReg = X86::RSI; break;
16567 case X86::DI: DestReg = X86::RDI; break;
16568 case X86::BP: DestReg = X86::RBP; break;
16569 case X86::SP: DestReg = X86::RSP; break;
16572 Res.first = DestReg;
16573 Res.second = &X86::GR64RegClass;
16576 } else if (Res.second == &X86::FR32RegClass ||
16577 Res.second == &X86::FR64RegClass ||
16578 Res.second == &X86::VR128RegClass) {
16579 // Handle references to XMM physical registers that got mapped into the
16580 // wrong class. This can happen with constraints like {xmm0} where the
16581 // target independent register mapper will just pick the first match it can
16582 // find, ignoring the required type.
16584 if (VT == MVT::f32 || VT == MVT::i32)
16585 Res.second = &X86::FR32RegClass;
16586 else if (VT == MVT::f64 || VT == MVT::i64)
16587 Res.second = &X86::FR64RegClass;
16588 else if (X86::VR128RegClass.hasType(VT))
16589 Res.second = &X86::VR128RegClass;
16590 else if (X86::VR256RegClass.hasType(VT))
16591 Res.second = &X86::VR256RegClass;