1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1611 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1612 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1613 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1614 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1615 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1616 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1617 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1618 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1619 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1621 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1622 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1623 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1624 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1625 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1626 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1627 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1628 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1629 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1630 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1631 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1632 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1633 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1635 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1636 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1637 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1638 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1639 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1640 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1641 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1642 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1644 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1645 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1646 if (Subtarget->hasVLX())
1647 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1649 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1650 const MVT VT = (MVT::SimpleValueType)i;
1652 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1654 // Do not attempt to promote non-512-bit vectors.
1655 if (!VT.is512BitVector())
1659 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1660 setOperationAction(ISD::VSELECT, VT, Legal);
1665 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1666 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1667 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1669 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1671 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1672 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1673 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1674 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1675 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1676 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1680 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1682 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1683 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1684 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1685 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1686 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1687 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1688 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1689 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1691 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1692 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1693 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1694 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1695 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1701 // We want to custom lower some of our intrinsics.
1702 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1704 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1705 if (!Subtarget->is64Bit())
1706 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1708 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1709 // handle type legalization for these operations here.
1711 // FIXME: We really should do custom legalization for addition and
1712 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1713 // than generic legalization for 64-bit multiplication-with-overflow, though.
1714 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1715 // Add/Sub/Mul with overflow operations are custom lowered.
1717 setOperationAction(ISD::SADDO, VT, Custom);
1718 setOperationAction(ISD::UADDO, VT, Custom);
1719 setOperationAction(ISD::SSUBO, VT, Custom);
1720 setOperationAction(ISD::USUBO, VT, Custom);
1721 setOperationAction(ISD::SMULO, VT, Custom);
1722 setOperationAction(ISD::UMULO, VT, Custom);
1725 if (!Subtarget->is64Bit()) {
1726 // These libcalls are not available in 32-bit.
1727 setLibcallName(RTLIB::SHL_I128, nullptr);
1728 setLibcallName(RTLIB::SRL_I128, nullptr);
1729 setLibcallName(RTLIB::SRA_I128, nullptr);
1732 // Combine sin / cos into one node or libcall if possible.
1733 if (Subtarget->hasSinCos()) {
1734 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1735 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1736 if (Subtarget->isTargetDarwin()) {
1737 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1738 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1739 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1740 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1744 if (Subtarget->isTargetWin64()) {
1745 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1746 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1747 setOperationAction(ISD::SREM, MVT::i128, Custom);
1748 setOperationAction(ISD::UREM, MVT::i128, Custom);
1749 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1750 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1753 // We have target-specific dag combine patterns for the following nodes:
1754 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1755 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1756 setTargetDAGCombine(ISD::BITCAST);
1757 setTargetDAGCombine(ISD::VSELECT);
1758 setTargetDAGCombine(ISD::SELECT);
1759 setTargetDAGCombine(ISD::SHL);
1760 setTargetDAGCombine(ISD::SRA);
1761 setTargetDAGCombine(ISD::SRL);
1762 setTargetDAGCombine(ISD::OR);
1763 setTargetDAGCombine(ISD::AND);
1764 setTargetDAGCombine(ISD::ADD);
1765 setTargetDAGCombine(ISD::FADD);
1766 setTargetDAGCombine(ISD::FSUB);
1767 setTargetDAGCombine(ISD::FMA);
1768 setTargetDAGCombine(ISD::SUB);
1769 setTargetDAGCombine(ISD::LOAD);
1770 setTargetDAGCombine(ISD::MLOAD);
1771 setTargetDAGCombine(ISD::STORE);
1772 setTargetDAGCombine(ISD::MSTORE);
1773 setTargetDAGCombine(ISD::ZERO_EXTEND);
1774 setTargetDAGCombine(ISD::ANY_EXTEND);
1775 setTargetDAGCombine(ISD::SIGN_EXTEND);
1776 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1777 setTargetDAGCombine(ISD::SINT_TO_FP);
1778 setTargetDAGCombine(ISD::UINT_TO_FP);
1779 setTargetDAGCombine(ISD::SETCC);
1780 setTargetDAGCombine(ISD::BUILD_VECTOR);
1781 setTargetDAGCombine(ISD::MUL);
1782 setTargetDAGCombine(ISD::XOR);
1784 computeRegisterProperties(Subtarget->getRegisterInfo());
1786 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1787 MaxStoresPerMemsetOptSize = 8;
1788 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1789 MaxStoresPerMemcpyOptSize = 4;
1790 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1791 MaxStoresPerMemmoveOptSize = 4;
1792 setPrefLoopAlignment(4); // 2^4 bytes.
1794 // A predictable cmov does not hurt on an in-order CPU.
1795 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1796 PredictableSelectIsExpensive = !Subtarget->isAtom();
1797 EnableExtLdPromotion = true;
1798 setPrefFunctionAlignment(4); // 2^4 bytes.
1800 verifyIntrinsicTables();
1803 // This has so far only been implemented for 64-bit MachO.
1804 bool X86TargetLowering::useLoadStackGuardNode() const {
1805 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1808 TargetLoweringBase::LegalizeTypeAction
1809 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1810 if (ExperimentalVectorWideningLegalization &&
1811 VT.getVectorNumElements() != 1 &&
1812 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1813 return TypeWidenVector;
1815 return TargetLoweringBase::getPreferredVectorAction(VT);
1818 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1821 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1823 const unsigned NumElts = VT.getVectorNumElements();
1824 const EVT EltVT = VT.getVectorElementType();
1825 if (VT.is512BitVector()) {
1826 if (Subtarget->hasAVX512())
1827 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1828 EltVT == MVT::f32 || EltVT == MVT::f64)
1830 case 8: return MVT::v8i1;
1831 case 16: return MVT::v16i1;
1833 if (Subtarget->hasBWI())
1834 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1836 case 32: return MVT::v32i1;
1837 case 64: return MVT::v64i1;
1841 if (VT.is256BitVector() || VT.is128BitVector()) {
1842 if (Subtarget->hasVLX())
1843 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1844 EltVT == MVT::f32 || EltVT == MVT::f64)
1846 case 2: return MVT::v2i1;
1847 case 4: return MVT::v4i1;
1848 case 8: return MVT::v8i1;
1850 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1851 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1853 case 8: return MVT::v8i1;
1854 case 16: return MVT::v16i1;
1855 case 32: return MVT::v32i1;
1859 return VT.changeVectorElementTypeToInteger();
1862 /// Helper for getByValTypeAlignment to determine
1863 /// the desired ByVal argument alignment.
1864 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1867 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1868 if (VTy->getBitWidth() == 128)
1870 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1871 unsigned EltAlign = 0;
1872 getMaxByValAlign(ATy->getElementType(), EltAlign);
1873 if (EltAlign > MaxAlign)
1874 MaxAlign = EltAlign;
1875 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1876 for (auto *EltTy : STy->elements()) {
1877 unsigned EltAlign = 0;
1878 getMaxByValAlign(EltTy, EltAlign);
1879 if (EltAlign > MaxAlign)
1880 MaxAlign = EltAlign;
1887 /// Return the desired alignment for ByVal aggregate
1888 /// function arguments in the caller parameter area. For X86, aggregates
1889 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1890 /// are at 4-byte boundaries.
1891 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1892 const DataLayout &DL) const {
1893 if (Subtarget->is64Bit()) {
1894 // Max of 8 and alignment of type.
1895 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1902 if (Subtarget->hasSSE1())
1903 getMaxByValAlign(Ty, Align);
1907 /// Returns the target specific optimal type for load
1908 /// and store operations as a result of memset, memcpy, and memmove
1909 /// lowering. If DstAlign is zero that means it's safe to destination
1910 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1911 /// means there isn't a need to check it against alignment requirement,
1912 /// probably because the source does not need to be loaded. If 'IsMemset' is
1913 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1914 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1915 /// source is constant so it does not need to be loaded.
1916 /// It returns EVT::Other if the type should be determined using generic
1917 /// target-independent logic.
1919 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1920 unsigned DstAlign, unsigned SrcAlign,
1921 bool IsMemset, bool ZeroMemset,
1923 MachineFunction &MF) const {
1924 const Function *F = MF.getFunction();
1925 if ((!IsMemset || ZeroMemset) &&
1926 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1928 (!Subtarget->isUnalignedMem16Slow() ||
1929 ((DstAlign == 0 || DstAlign >= 16) &&
1930 (SrcAlign == 0 || SrcAlign >= 16)))) {
1932 // FIXME: Check if unaligned 32-byte accesses are slow.
1933 if (Subtarget->hasInt256())
1935 if (Subtarget->hasFp256())
1938 if (Subtarget->hasSSE2())
1940 if (Subtarget->hasSSE1())
1942 } else if (!MemcpyStrSrc && Size >= 8 &&
1943 !Subtarget->is64Bit() &&
1944 Subtarget->hasSSE2()) {
1945 // Do not use f64 to lower memcpy if source is string constant. It's
1946 // better to use i32 to avoid the loads.
1950 // This is a compromise. If we reach here, unaligned accesses may be slow on
1951 // this target. However, creating smaller, aligned accesses could be even
1952 // slower and would certainly be a lot more code.
1953 if (Subtarget->is64Bit() && Size >= 8)
1958 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1960 return X86ScalarSSEf32;
1961 else if (VT == MVT::f64)
1962 return X86ScalarSSEf64;
1967 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1972 switch (VT.getSizeInBits()) {
1974 // 8-byte and under are always assumed to be fast.
1978 *Fast = !Subtarget->isUnalignedMem16Slow();
1981 *Fast = !Subtarget->isUnalignedMem32Slow();
1983 // TODO: What about AVX-512 (512-bit) accesses?
1986 // Misaligned accesses of any size are always allowed.
1990 /// Return the entry encoding for a jump table in the
1991 /// current function. The returned value is a member of the
1992 /// MachineJumpTableInfo::JTEntryKind enum.
1993 unsigned X86TargetLowering::getJumpTableEncoding() const {
1994 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1996 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1997 Subtarget->isPICStyleGOT())
1998 return MachineJumpTableInfo::EK_Custom32;
2000 // Otherwise, use the normal jump table encoding heuristics.
2001 return TargetLowering::getJumpTableEncoding();
2004 bool X86TargetLowering::useSoftFloat() const {
2005 return Subtarget->useSoftFloat();
2009 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2010 const MachineBasicBlock *MBB,
2011 unsigned uid,MCContext &Ctx) const{
2012 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2013 Subtarget->isPICStyleGOT());
2014 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2016 return MCSymbolRefExpr::create(MBB->getSymbol(),
2017 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2020 /// Returns relocation base for the given PIC jumptable.
2021 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2022 SelectionDAG &DAG) const {
2023 if (!Subtarget->is64Bit())
2024 // This doesn't have SDLoc associated with it, but is not really the
2025 // same as a Register.
2026 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2027 getPointerTy(DAG.getDataLayout()));
2031 /// This returns the relocation base for the given PIC jumptable,
2032 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2033 const MCExpr *X86TargetLowering::
2034 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2035 MCContext &Ctx) const {
2036 // X86-64 uses RIP relative addressing based on the jump table label.
2037 if (Subtarget->isPICStyleRIPRel())
2038 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2040 // Otherwise, the reference is relative to the PIC base.
2041 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2044 std::pair<const TargetRegisterClass *, uint8_t>
2045 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2047 const TargetRegisterClass *RRC = nullptr;
2049 switch (VT.SimpleTy) {
2051 return TargetLowering::findRepresentativeClass(TRI, VT);
2052 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2053 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2056 RRC = &X86::VR64RegClass;
2058 case MVT::f32: case MVT::f64:
2059 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2060 case MVT::v4f32: case MVT::v2f64:
2061 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2063 RRC = &X86::VR128RegClass;
2066 return std::make_pair(RRC, Cost);
2069 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2070 unsigned &Offset) const {
2071 if (!Subtarget->isTargetLinux())
2074 if (Subtarget->is64Bit()) {
2075 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2077 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2089 /// Android provides a fixed TLS slot for the SafeStack pointer.
2090 /// See the definition of TLS_SLOT_SAFESTACK in
2091 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2092 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2093 unsigned &Offset) const {
2094 if (!Subtarget->isTargetAndroid())
2097 if (Subtarget->is64Bit()) {
2098 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2100 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2112 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2113 unsigned DestAS) const {
2114 assert(SrcAS != DestAS && "Expected different address spaces!");
2116 return SrcAS < 256 && DestAS < 256;
2119 //===----------------------------------------------------------------------===//
2120 // Return Value Calling Convention Implementation
2121 //===----------------------------------------------------------------------===//
2123 #include "X86GenCallingConv.inc"
2125 bool X86TargetLowering::CanLowerReturn(
2126 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2128 SmallVector<CCValAssign, 16> RVLocs;
2129 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2130 return CCInfo.CheckReturn(Outs, RetCC_X86);
2133 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2134 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2139 X86TargetLowering::LowerReturn(SDValue Chain,
2140 CallingConv::ID CallConv, bool isVarArg,
2141 const SmallVectorImpl<ISD::OutputArg> &Outs,
2142 const SmallVectorImpl<SDValue> &OutVals,
2143 SDLoc dl, SelectionDAG &DAG) const {
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2147 SmallVector<CCValAssign, 16> RVLocs;
2148 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2149 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2152 SmallVector<SDValue, 6> RetOps;
2153 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2154 // Operand #1 = Bytes To Pop
2155 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2158 // Copy the result values into the output registers.
2159 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2160 CCValAssign &VA = RVLocs[i];
2161 assert(VA.isRegLoc() && "Can only return in registers!");
2162 SDValue ValToCopy = OutVals[i];
2163 EVT ValVT = ValToCopy.getValueType();
2165 // Promote values to the appropriate types.
2166 if (VA.getLocInfo() == CCValAssign::SExt)
2167 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2168 else if (VA.getLocInfo() == CCValAssign::ZExt)
2169 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2170 else if (VA.getLocInfo() == CCValAssign::AExt) {
2171 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2172 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2174 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2176 else if (VA.getLocInfo() == CCValAssign::BCvt)
2177 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2179 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2180 "Unexpected FP-extend for return value.");
2182 // If this is x86-64, and we disabled SSE, we can't return FP values,
2183 // or SSE or MMX vectors.
2184 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2185 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2186 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2187 report_fatal_error("SSE register return with SSE disabled");
2189 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2190 // llvm-gcc has never done it right and no one has noticed, so this
2191 // should be OK for now.
2192 if (ValVT == MVT::f64 &&
2193 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2194 report_fatal_error("SSE2 register return with SSE2 disabled");
2196 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2197 // the RET instruction and handled by the FP Stackifier.
2198 if (VA.getLocReg() == X86::FP0 ||
2199 VA.getLocReg() == X86::FP1) {
2200 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2201 // change the value to the FP stack register class.
2202 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2203 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2204 RetOps.push_back(ValToCopy);
2205 // Don't emit a copytoreg.
2209 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2210 // which is returned in RAX / RDX.
2211 if (Subtarget->is64Bit()) {
2212 if (ValVT == MVT::x86mmx) {
2213 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2214 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2215 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2217 // If we don't have SSE2 available, convert to v4f32 so the generated
2218 // register is legal.
2219 if (!Subtarget->hasSSE2())
2220 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2225 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2226 Flag = Chain.getValue(1);
2227 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2230 // All x86 ABIs require that for returning structs by value we copy
2231 // the sret argument into %rax/%eax (depending on ABI) for the return.
2232 // We saved the argument into a virtual register in the entry block,
2233 // so now we copy the value out and into %rax/%eax.
2235 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2236 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2237 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2238 // either case FuncInfo->setSRetReturnReg() will have been called.
2239 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2240 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2241 getPointerTy(MF.getDataLayout()));
2244 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2245 X86::RAX : X86::EAX;
2246 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2247 Flag = Chain.getValue(1);
2249 // RAX/EAX now acts like a return value.
2251 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2254 RetOps[0] = Chain; // Update chain.
2256 // Add the flag if we have it.
2258 RetOps.push_back(Flag);
2260 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2263 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2264 if (N->getNumValues() != 1)
2266 if (!N->hasNUsesOfValue(1, 0))
2269 SDValue TCChain = Chain;
2270 SDNode *Copy = *N->use_begin();
2271 if (Copy->getOpcode() == ISD::CopyToReg) {
2272 // If the copy has a glue operand, we conservatively assume it isn't safe to
2273 // perform a tail call.
2274 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2276 TCChain = Copy->getOperand(0);
2277 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2280 bool HasRet = false;
2281 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2283 if (UI->getOpcode() != X86ISD::RET_FLAG)
2285 // If we are returning more than one value, we can definitely
2286 // not make a tail call see PR19530
2287 if (UI->getNumOperands() > 4)
2289 if (UI->getNumOperands() == 4 &&
2290 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2303 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2304 ISD::NodeType ExtendKind) const {
2306 // TODO: Is this also valid on 32-bit?
2307 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2308 ReturnMVT = MVT::i8;
2310 ReturnMVT = MVT::i32;
2312 EVT MinVT = getRegisterType(Context, ReturnMVT);
2313 return VT.bitsLT(MinVT) ? MinVT : VT;
2316 /// Lower the result values of a call into the
2317 /// appropriate copies out of appropriate physical registers.
2320 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2321 CallingConv::ID CallConv, bool isVarArg,
2322 const SmallVectorImpl<ISD::InputArg> &Ins,
2323 SDLoc dl, SelectionDAG &DAG,
2324 SmallVectorImpl<SDValue> &InVals) const {
2326 // Assign locations to each value returned by this call.
2327 SmallVector<CCValAssign, 16> RVLocs;
2328 bool Is64Bit = Subtarget->is64Bit();
2329 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2331 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2333 // Copy all of the result registers out of their specified physreg.
2334 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2335 CCValAssign &VA = RVLocs[i];
2336 EVT CopyVT = VA.getLocVT();
2338 // If this is x86-64, and we disabled SSE, we can't return FP values
2339 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2340 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2341 report_fatal_error("SSE register return with SSE disabled");
2344 // If we prefer to use the value in xmm registers, copy it out as f80 and
2345 // use a truncate to move it from fp stack reg to xmm reg.
2346 bool RoundAfterCopy = false;
2347 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2348 isScalarFPTypeInSSEReg(VA.getValVT())) {
2350 RoundAfterCopy = (CopyVT != VA.getLocVT());
2353 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2354 CopyVT, InFlag).getValue(1);
2355 SDValue Val = Chain.getValue(0);
2358 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2359 // This truncation won't change the value.
2360 DAG.getIntPtrConstant(1, dl));
2362 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2363 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2365 InFlag = Chain.getValue(2);
2366 InVals.push_back(Val);
2372 //===----------------------------------------------------------------------===//
2373 // C & StdCall & Fast Calling Convention implementation
2374 //===----------------------------------------------------------------------===//
2375 // StdCall calling convention seems to be standard for many Windows' API
2376 // routines and around. It differs from C calling convention just a little:
2377 // callee should clean up the stack, not caller. Symbols should be also
2378 // decorated in some fancy way :) It doesn't support any vector arguments.
2379 // For info on fast calling convention see Fast Calling Convention (tail call)
2380 // implementation LowerX86_32FastCCCallTo.
2382 /// CallIsStructReturn - Determines whether a call uses struct return
2384 enum StructReturnType {
2389 static StructReturnType
2390 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2392 return NotStructReturn;
2394 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2395 if (!Flags.isSRet())
2396 return NotStructReturn;
2397 if (Flags.isInReg())
2398 return RegStructReturn;
2399 return StackStructReturn;
2402 /// Determines whether a function uses struct return semantics.
2403 static StructReturnType
2404 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2406 return NotStructReturn;
2408 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2409 if (!Flags.isSRet())
2410 return NotStructReturn;
2411 if (Flags.isInReg())
2412 return RegStructReturn;
2413 return StackStructReturn;
2416 /// Make a copy of an aggregate at address specified by "Src" to address
2417 /// "Dst" with size and alignment information specified by the specific
2418 /// parameter attribute. The copy will be passed as a byval function parameter.
2420 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2421 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2423 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2425 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2426 /*isVolatile*/false, /*AlwaysInline=*/true,
2427 /*isTailCall*/false,
2428 MachinePointerInfo(), MachinePointerInfo());
2431 /// Return true if the calling convention is one that
2432 /// supports tail call optimization.
2433 static bool IsTailCallConvention(CallingConv::ID CC) {
2434 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2435 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2438 /// \brief Return true if the calling convention is a C calling convention.
2439 static bool IsCCallConvention(CallingConv::ID CC) {
2440 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2441 CC == CallingConv::X86_64_SysV);
2444 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2446 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2447 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2451 CallingConv::ID CalleeCC = CS.getCallingConv();
2452 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2458 /// Return true if the function is being made into
2459 /// a tailcall target by changing its ABI.
2460 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2461 bool GuaranteedTailCallOpt) {
2462 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2466 X86TargetLowering::LowerMemArgument(SDValue Chain,
2467 CallingConv::ID CallConv,
2468 const SmallVectorImpl<ISD::InputArg> &Ins,
2469 SDLoc dl, SelectionDAG &DAG,
2470 const CCValAssign &VA,
2471 MachineFrameInfo *MFI,
2473 // Create the nodes corresponding to a load from this parameter slot.
2474 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2475 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2476 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2477 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2480 // If value is passed by pointer we have address passed instead of the value
2482 bool ExtendedInMem = VA.isExtInLoc() &&
2483 VA.getValVT().getScalarType() == MVT::i1;
2485 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2486 ValVT = VA.getLocVT();
2488 ValVT = VA.getValVT();
2490 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2491 // changed with more analysis.
2492 // In case of tail call optimization mark all arguments mutable. Since they
2493 // could be overwritten by lowering of arguments in case of a tail call.
2494 if (Flags.isByVal()) {
2495 unsigned Bytes = Flags.getByValSize();
2496 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2497 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2498 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2500 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2501 VA.getLocMemOffset(), isImmutable);
2502 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2503 SDValue Val = DAG.getLoad(
2504 ValVT, dl, Chain, FIN,
2505 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2507 return ExtendedInMem ?
2508 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2512 // FIXME: Get this from tablegen.
2513 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2514 const X86Subtarget *Subtarget) {
2515 assert(Subtarget->is64Bit());
2517 if (Subtarget->isCallingConvWin64(CallConv)) {
2518 static const MCPhysReg GPR64ArgRegsWin64[] = {
2519 X86::RCX, X86::RDX, X86::R8, X86::R9
2521 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2524 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2525 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2527 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2530 // FIXME: Get this from tablegen.
2531 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2532 CallingConv::ID CallConv,
2533 const X86Subtarget *Subtarget) {
2534 assert(Subtarget->is64Bit());
2535 if (Subtarget->isCallingConvWin64(CallConv)) {
2536 // The XMM registers which might contain var arg parameters are shadowed
2537 // in their paired GPR. So we only need to save the GPR to their home
2539 // TODO: __vectorcall will change this.
2543 const Function *Fn = MF.getFunction();
2544 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2545 bool isSoftFloat = Subtarget->useSoftFloat();
2546 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2547 "SSE register cannot be used when SSE is disabled!");
2548 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2549 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2553 static const MCPhysReg XMMArgRegs64Bit[] = {
2554 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2555 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2557 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2560 SDValue X86TargetLowering::LowerFormalArguments(
2561 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2562 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2563 SmallVectorImpl<SDValue> &InVals) const {
2564 MachineFunction &MF = DAG.getMachineFunction();
2565 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2566 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2568 const Function* Fn = MF.getFunction();
2569 if (Fn->hasExternalLinkage() &&
2570 Subtarget->isTargetCygMing() &&
2571 Fn->getName() == "main")
2572 FuncInfo->setForceFramePointer(true);
2574 MachineFrameInfo *MFI = MF.getFrameInfo();
2575 bool Is64Bit = Subtarget->is64Bit();
2576 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2578 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2579 "Var args not supported with calling convention fastcc, ghc or hipe");
2581 // Assign locations to all of the incoming arguments.
2582 SmallVector<CCValAssign, 16> ArgLocs;
2583 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2585 // Allocate shadow area for Win64
2587 CCInfo.AllocateStack(32, 8);
2589 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2591 unsigned LastVal = ~0U;
2593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2594 CCValAssign &VA = ArgLocs[i];
2595 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2597 assert(VA.getValNo() != LastVal &&
2598 "Don't support value assigned to multiple locs yet");
2600 LastVal = VA.getValNo();
2602 if (VA.isRegLoc()) {
2603 EVT RegVT = VA.getLocVT();
2604 const TargetRegisterClass *RC;
2605 if (RegVT == MVT::i32)
2606 RC = &X86::GR32RegClass;
2607 else if (Is64Bit && RegVT == MVT::i64)
2608 RC = &X86::GR64RegClass;
2609 else if (RegVT == MVT::f32)
2610 RC = &X86::FR32RegClass;
2611 else if (RegVT == MVT::f64)
2612 RC = &X86::FR64RegClass;
2613 else if (RegVT.is512BitVector())
2614 RC = &X86::VR512RegClass;
2615 else if (RegVT.is256BitVector())
2616 RC = &X86::VR256RegClass;
2617 else if (RegVT.is128BitVector())
2618 RC = &X86::VR128RegClass;
2619 else if (RegVT == MVT::x86mmx)
2620 RC = &X86::VR64RegClass;
2621 else if (RegVT == MVT::i1)
2622 RC = &X86::VK1RegClass;
2623 else if (RegVT == MVT::v8i1)
2624 RC = &X86::VK8RegClass;
2625 else if (RegVT == MVT::v16i1)
2626 RC = &X86::VK16RegClass;
2627 else if (RegVT == MVT::v32i1)
2628 RC = &X86::VK32RegClass;
2629 else if (RegVT == MVT::v64i1)
2630 RC = &X86::VK64RegClass;
2632 llvm_unreachable("Unknown argument type!");
2634 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2635 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2637 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2638 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2640 if (VA.getLocInfo() == CCValAssign::SExt)
2641 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2642 DAG.getValueType(VA.getValVT()));
2643 else if (VA.getLocInfo() == CCValAssign::ZExt)
2644 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2645 DAG.getValueType(VA.getValVT()));
2646 else if (VA.getLocInfo() == CCValAssign::BCvt)
2647 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2649 if (VA.isExtInLoc()) {
2650 // Handle MMX values passed in XMM regs.
2651 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2652 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2654 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2657 assert(VA.isMemLoc());
2658 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2661 // If value is passed via pointer - do a load.
2662 if (VA.getLocInfo() == CCValAssign::Indirect)
2663 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2664 MachinePointerInfo(), false, false, false, 0);
2666 InVals.push_back(ArgValue);
2669 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2670 // All x86 ABIs require that for returning structs by value we copy the
2671 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2672 // the argument into a virtual register so that we can access it from the
2674 if (Ins[i].Flags.isSRet()) {
2675 unsigned Reg = FuncInfo->getSRetReturnReg();
2677 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2678 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2679 FuncInfo->setSRetReturnReg(Reg);
2681 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2682 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2687 unsigned StackSize = CCInfo.getNextStackOffset();
2688 // Align stack specially for tail calls.
2689 if (FuncIsMadeTailCallSafe(CallConv,
2690 MF.getTarget().Options.GuaranteedTailCallOpt))
2691 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2693 // If the function takes variable number of arguments, make a frame index for
2694 // the start of the first vararg value... for expansion of llvm.va_start. We
2695 // can skip this if there are no va_start calls.
2696 if (MFI->hasVAStart() &&
2697 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2698 CallConv != CallingConv::X86_ThisCall))) {
2699 FuncInfo->setVarArgsFrameIndex(
2700 MFI->CreateFixedObject(1, StackSize, true));
2703 MachineModuleInfo &MMI = MF.getMMI();
2705 // Figure out if XMM registers are in use.
2706 assert(!(Subtarget->useSoftFloat() &&
2707 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2708 "SSE register cannot be used when SSE is disabled!");
2710 // 64-bit calling conventions support varargs and register parameters, so we
2711 // have to do extra work to spill them in the prologue.
2712 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2713 // Find the first unallocated argument registers.
2714 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2715 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2716 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2717 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2718 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2719 "SSE register cannot be used when SSE is disabled!");
2721 // Gather all the live in physical registers.
2722 SmallVector<SDValue, 6> LiveGPRs;
2723 SmallVector<SDValue, 8> LiveXMMRegs;
2725 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2726 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2728 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2730 if (!ArgXMMs.empty()) {
2731 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2732 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2733 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2734 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2735 LiveXMMRegs.push_back(
2736 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2741 // Get to the caller-allocated home save location. Add 8 to account
2742 // for the return address.
2743 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2744 FuncInfo->setRegSaveFrameIndex(
2745 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2746 // Fixup to set vararg frame on shadow area (4 x i64).
2748 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2750 // For X86-64, if there are vararg parameters that are passed via
2751 // registers, then we must store them to their spots on the stack so
2752 // they may be loaded by deferencing the result of va_next.
2753 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2754 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2755 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2756 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2759 // Store the integer parameter registers.
2760 SmallVector<SDValue, 8> MemOps;
2761 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2762 getPointerTy(DAG.getDataLayout()));
2763 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2764 for (SDValue Val : LiveGPRs) {
2765 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2766 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2768 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2769 MachinePointerInfo::getFixedStack(
2770 DAG.getMachineFunction(),
2771 FuncInfo->getRegSaveFrameIndex(), Offset),
2773 MemOps.push_back(Store);
2777 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2778 // Now store the XMM (fp + vector) parameter registers.
2779 SmallVector<SDValue, 12> SaveXMMOps;
2780 SaveXMMOps.push_back(Chain);
2781 SaveXMMOps.push_back(ALVal);
2782 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2783 FuncInfo->getRegSaveFrameIndex(), dl));
2784 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2785 FuncInfo->getVarArgsFPOffset(), dl));
2786 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2788 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2789 MVT::Other, SaveXMMOps));
2792 if (!MemOps.empty())
2793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2796 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2797 // Find the largest legal vector type.
2798 MVT VecVT = MVT::Other;
2799 // FIXME: Only some x86_32 calling conventions support AVX512.
2800 if (Subtarget->hasAVX512() &&
2801 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2802 CallConv == CallingConv::Intel_OCL_BI)))
2803 VecVT = MVT::v16f32;
2804 else if (Subtarget->hasAVX())
2806 else if (Subtarget->hasSSE2())
2809 // We forward some GPRs and some vector types.
2810 SmallVector<MVT, 2> RegParmTypes;
2811 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2812 RegParmTypes.push_back(IntVT);
2813 if (VecVT != MVT::Other)
2814 RegParmTypes.push_back(VecVT);
2816 // Compute the set of forwarded registers. The rest are scratch.
2817 SmallVectorImpl<ForwardedRegister> &Forwards =
2818 FuncInfo->getForwardedMustTailRegParms();
2819 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2821 // Conservatively forward AL on x86_64, since it might be used for varargs.
2822 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2823 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2824 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2827 // Copy all forwards from physical to virtual registers.
2828 for (ForwardedRegister &F : Forwards) {
2829 // FIXME: Can we use a less constrained schedule?
2830 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2831 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2832 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2836 // Some CCs need callee pop.
2837 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2838 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2839 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2841 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2842 // If this is an sret function, the return should pop the hidden pointer.
2843 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2844 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2845 argsAreStructReturn(Ins) == StackStructReturn)
2846 FuncInfo->setBytesToPopOnReturn(4);
2850 // RegSaveFrameIndex is X86-64 only.
2851 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2852 if (CallConv == CallingConv::X86_FastCall ||
2853 CallConv == CallingConv::X86_ThisCall)
2854 // fastcc functions can't have varargs.
2855 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2858 FuncInfo->setArgumentStackSize(StackSize);
2860 if (MMI.hasWinEHFuncInfo(Fn)) {
2862 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2863 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2864 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2865 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2866 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2867 MachinePointerInfo::getFixedStack(
2868 DAG.getMachineFunction(), UnwindHelpFI),
2869 /*isVolatile=*/true,
2870 /*isNonTemporal=*/false, /*Alignment=*/0);
2872 // Functions using Win32 EH are considered to have opaque SP adjustments
2873 // to force local variables to be addressed from the frame or base
2875 MFI->setHasOpaqueSPAdjustment(true);
2883 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2884 SDValue StackPtr, SDValue Arg,
2885 SDLoc dl, SelectionDAG &DAG,
2886 const CCValAssign &VA,
2887 ISD::ArgFlagsTy Flags) const {
2888 unsigned LocMemOffset = VA.getLocMemOffset();
2889 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2890 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2892 if (Flags.isByVal())
2893 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2895 return DAG.getStore(
2896 Chain, dl, Arg, PtrOff,
2897 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2901 /// Emit a load of return address if tail call
2902 /// optimization is performed and it is required.
2904 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2905 SDValue &OutRetAddr, SDValue Chain,
2906 bool IsTailCall, bool Is64Bit,
2907 int FPDiff, SDLoc dl) const {
2908 // Adjust the Return address stack slot.
2909 EVT VT = getPointerTy(DAG.getDataLayout());
2910 OutRetAddr = getReturnAddressFrameIndex(DAG);
2912 // Load the "old" Return address.
2913 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2914 false, false, false, 0);
2915 return SDValue(OutRetAddr.getNode(), 1);
2918 /// Emit a store of the return address if tail call
2919 /// optimization is performed and it is required (FPDiff!=0).
2920 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2921 SDValue Chain, SDValue RetAddrFrIdx,
2922 EVT PtrVT, unsigned SlotSize,
2923 int FPDiff, SDLoc dl) {
2924 // Store the return address to the appropriate stack slot.
2925 if (!FPDiff) return Chain;
2926 // Calculate the new stack slot for the return address.
2927 int NewReturnAddrFI =
2928 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2930 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2931 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2932 MachinePointerInfo::getFixedStack(
2933 DAG.getMachineFunction(), NewReturnAddrFI),
2938 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2939 /// operation of specified width.
2940 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2942 unsigned NumElems = VT.getVectorNumElements();
2943 SmallVector<int, 8> Mask;
2944 Mask.push_back(NumElems);
2945 for (unsigned i = 1; i != NumElems; ++i)
2947 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2951 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2952 SmallVectorImpl<SDValue> &InVals) const {
2953 SelectionDAG &DAG = CLI.DAG;
2955 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2956 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2957 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2958 SDValue Chain = CLI.Chain;
2959 SDValue Callee = CLI.Callee;
2960 CallingConv::ID CallConv = CLI.CallConv;
2961 bool &isTailCall = CLI.IsTailCall;
2962 bool isVarArg = CLI.IsVarArg;
2964 MachineFunction &MF = DAG.getMachineFunction();
2965 bool Is64Bit = Subtarget->is64Bit();
2966 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2967 StructReturnType SR = callIsStructReturn(Outs);
2968 bool IsSibcall = false;
2969 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2970 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2972 if (Attr.getValueAsString() == "true")
2975 if (Subtarget->isPICStyleGOT() &&
2976 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2977 // If we are using a GOT, disable tail calls to external symbols with
2978 // default visibility. Tail calling such a symbol requires using a GOT
2979 // relocation, which forces early binding of the symbol. This breaks code
2980 // that require lazy function symbol resolution. Using musttail or
2981 // GuaranteedTailCallOpt will override this.
2982 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2983 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2984 G->getGlobal()->hasDefaultVisibility()))
2988 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2990 // Force this to be a tail call. The verifier rules are enough to ensure
2991 // that we can lower this successfully without moving the return address
2994 } else if (isTailCall) {
2995 // Check if it's really possible to do a tail call.
2996 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2997 isVarArg, SR != NotStructReturn,
2998 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2999 Outs, OutVals, Ins, DAG);
3001 // Sibcalls are automatically detected tailcalls which do not require
3003 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3010 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3011 "Var args not supported with calling convention fastcc, ghc or hipe");
3013 // Analyze operands of the call, assigning locations to each operand.
3014 SmallVector<CCValAssign, 16> ArgLocs;
3015 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3017 // Allocate shadow area for Win64
3019 CCInfo.AllocateStack(32, 8);
3021 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3023 // Get a count of how many bytes are to be pushed on the stack.
3024 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3026 // This is a sibcall. The memory operands are available in caller's
3027 // own caller's stack.
3029 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3030 IsTailCallConvention(CallConv))
3031 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3034 if (isTailCall && !IsSibcall && !IsMustTail) {
3035 // Lower arguments at fp - stackoffset + fpdiff.
3036 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3038 FPDiff = NumBytesCallerPushed - NumBytes;
3040 // Set the delta of movement of the returnaddr stackslot.
3041 // But only set if delta is greater than previous delta.
3042 if (FPDiff < X86Info->getTCReturnAddrDelta())
3043 X86Info->setTCReturnAddrDelta(FPDiff);
3046 unsigned NumBytesToPush = NumBytes;
3047 unsigned NumBytesToPop = NumBytes;
3049 // If we have an inalloca argument, all stack space has already been allocated
3050 // for us and be right at the top of the stack. We don't support multiple
3051 // arguments passed in memory when using inalloca.
3052 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3054 if (!ArgLocs.back().isMemLoc())
3055 report_fatal_error("cannot use inalloca attribute on a register "
3057 if (ArgLocs.back().getLocMemOffset() != 0)
3058 report_fatal_error("any parameter with the inalloca attribute must be "
3059 "the only memory argument");
3063 Chain = DAG.getCALLSEQ_START(
3064 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3066 SDValue RetAddrFrIdx;
3067 // Load return address for tail calls.
3068 if (isTailCall && FPDiff)
3069 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3070 Is64Bit, FPDiff, dl);
3072 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3073 SmallVector<SDValue, 8> MemOpChains;
3076 // Walk the register/memloc assignments, inserting copies/loads. In the case
3077 // of tail call optimization arguments are handle later.
3078 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3079 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3080 // Skip inalloca arguments, they have already been written.
3081 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3082 if (Flags.isInAlloca())
3085 CCValAssign &VA = ArgLocs[i];
3086 EVT RegVT = VA.getLocVT();
3087 SDValue Arg = OutVals[i];
3088 bool isByVal = Flags.isByVal();
3090 // Promote the value if needed.
3091 switch (VA.getLocInfo()) {
3092 default: llvm_unreachable("Unknown loc info!");
3093 case CCValAssign::Full: break;
3094 case CCValAssign::SExt:
3095 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3097 case CCValAssign::ZExt:
3098 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3100 case CCValAssign::AExt:
3101 if (Arg.getValueType().isVector() &&
3102 Arg.getValueType().getScalarType() == MVT::i1)
3103 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3104 else if (RegVT.is128BitVector()) {
3105 // Special case: passing MMX values in XMM registers.
3106 Arg = DAG.getBitcast(MVT::i64, Arg);
3107 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3108 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3110 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3112 case CCValAssign::BCvt:
3113 Arg = DAG.getBitcast(RegVT, Arg);
3115 case CCValAssign::Indirect: {
3116 // Store the argument.
3117 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3118 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3119 Chain = DAG.getStore(
3120 Chain, dl, Arg, SpillSlot,
3121 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3128 if (VA.isRegLoc()) {
3129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3130 if (isVarArg && IsWin64) {
3131 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3132 // shadow reg if callee is a varargs function.
3133 unsigned ShadowReg = 0;
3134 switch (VA.getLocReg()) {
3135 case X86::XMM0: ShadowReg = X86::RCX; break;
3136 case X86::XMM1: ShadowReg = X86::RDX; break;
3137 case X86::XMM2: ShadowReg = X86::R8; break;
3138 case X86::XMM3: ShadowReg = X86::R9; break;
3141 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3143 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3144 assert(VA.isMemLoc());
3145 if (!StackPtr.getNode())
3146 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3147 getPointerTy(DAG.getDataLayout()));
3148 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3149 dl, DAG, VA, Flags));
3153 if (!MemOpChains.empty())
3154 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3156 if (Subtarget->isPICStyleGOT()) {
3157 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3160 RegsToPass.push_back(std::make_pair(
3161 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3162 getPointerTy(DAG.getDataLayout()))));
3164 // If we are tail calling and generating PIC/GOT style code load the
3165 // address of the callee into ECX. The value in ecx is used as target of
3166 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3167 // for tail calls on PIC/GOT architectures. Normally we would just put the
3168 // address of GOT into ebx and then call target@PLT. But for tail calls
3169 // ebx would be restored (since ebx is callee saved) before jumping to the
3172 // Note: The actual moving to ECX is done further down.
3173 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3174 if (G && !G->getGlobal()->hasLocalLinkage() &&
3175 G->getGlobal()->hasDefaultVisibility())
3176 Callee = LowerGlobalAddress(Callee, DAG);
3177 else if (isa<ExternalSymbolSDNode>(Callee))
3178 Callee = LowerExternalSymbol(Callee, DAG);
3182 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3183 // From AMD64 ABI document:
3184 // For calls that may call functions that use varargs or stdargs
3185 // (prototype-less calls or calls to functions containing ellipsis (...) in
3186 // the declaration) %al is used as hidden argument to specify the number
3187 // of SSE registers used. The contents of %al do not need to match exactly
3188 // the number of registers, but must be an ubound on the number of SSE
3189 // registers used and is in the range 0 - 8 inclusive.
3191 // Count the number of XMM registers allocated.
3192 static const MCPhysReg XMMArgRegs[] = {
3193 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3194 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3196 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3197 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3198 && "SSE registers cannot be used when SSE is disabled");
3200 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3201 DAG.getConstant(NumXMMRegs, dl,
3205 if (isVarArg && IsMustTail) {
3206 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3207 for (const auto &F : Forwards) {
3208 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3209 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3213 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3214 // don't need this because the eligibility check rejects calls that require
3215 // shuffling arguments passed in memory.
3216 if (!IsSibcall && isTailCall) {
3217 // Force all the incoming stack arguments to be loaded from the stack
3218 // before any new outgoing arguments are stored to the stack, because the
3219 // outgoing stack slots may alias the incoming argument stack slots, and
3220 // the alias isn't otherwise explicit. This is slightly more conservative
3221 // than necessary, because it means that each store effectively depends
3222 // on every argument instead of just those arguments it would clobber.
3223 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3225 SmallVector<SDValue, 8> MemOpChains2;
3228 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3229 CCValAssign &VA = ArgLocs[i];
3232 assert(VA.isMemLoc());
3233 SDValue Arg = OutVals[i];
3234 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3235 // Skip inalloca arguments. They don't require any work.
3236 if (Flags.isInAlloca())
3238 // Create frame index.
3239 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3240 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3241 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3242 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3244 if (Flags.isByVal()) {
3245 // Copy relative to framepointer.
3246 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3247 if (!StackPtr.getNode())
3248 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3249 getPointerTy(DAG.getDataLayout()));
3250 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3253 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3257 // Store relative to framepointer.
3258 MemOpChains2.push_back(DAG.getStore(
3259 ArgChain, dl, Arg, FIN,
3260 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3265 if (!MemOpChains2.empty())
3266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3268 // Store the return address to the appropriate stack slot.
3269 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3270 getPointerTy(DAG.getDataLayout()),
3271 RegInfo->getSlotSize(), FPDiff, dl);
3274 // Build a sequence of copy-to-reg nodes chained together with token chain
3275 // and flag operands which copy the outgoing args into registers.
3277 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3278 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3279 RegsToPass[i].second, InFlag);
3280 InFlag = Chain.getValue(1);
3283 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3284 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3285 // In the 64-bit large code model, we have to make all calls
3286 // through a register, since the call instruction's 32-bit
3287 // pc-relative offset may not be large enough to hold the whole
3289 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3290 // If the callee is a GlobalAddress node (quite common, every direct call
3291 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3293 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3295 // We should use extra load for direct calls to dllimported functions in
3297 const GlobalValue *GV = G->getGlobal();
3298 if (!GV->hasDLLImportStorageClass()) {
3299 unsigned char OpFlags = 0;
3300 bool ExtraLoad = false;
3301 unsigned WrapperKind = ISD::DELETED_NODE;
3303 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3304 // external symbols most go through the PLT in PIC mode. If the symbol
3305 // has hidden or protected visibility, or if it is static or local, then
3306 // we don't need to use the PLT - we can directly call it.
3307 if (Subtarget->isTargetELF() &&
3308 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3309 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3310 OpFlags = X86II::MO_PLT;
3311 } else if (Subtarget->isPICStyleStubAny() &&
3312 !GV->isStrongDefinitionForLinker() &&
3313 (!Subtarget->getTargetTriple().isMacOSX() ||
3314 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3315 // PC-relative references to external symbols should go through $stub,
3316 // unless we're building with the leopard linker or later, which
3317 // automatically synthesizes these stubs.
3318 OpFlags = X86II::MO_DARWIN_STUB;
3319 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3320 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3321 // If the function is marked as non-lazy, generate an indirect call
3322 // which loads from the GOT directly. This avoids runtime overhead
3323 // at the cost of eager binding (and one extra byte of encoding).
3324 OpFlags = X86II::MO_GOTPCREL;
3325 WrapperKind = X86ISD::WrapperRIP;
3329 Callee = DAG.getTargetGlobalAddress(
3330 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3332 // Add a wrapper if needed.
3333 if (WrapperKind != ISD::DELETED_NODE)
3334 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3335 getPointerTy(DAG.getDataLayout()), Callee);
3336 // Add extra indirection if needed.
3338 Callee = DAG.getLoad(
3339 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3340 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3343 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3344 unsigned char OpFlags = 0;
3346 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3347 // external symbols should go through the PLT.
3348 if (Subtarget->isTargetELF() &&
3349 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3350 OpFlags = X86II::MO_PLT;
3351 } else if (Subtarget->isPICStyleStubAny() &&
3352 (!Subtarget->getTargetTriple().isMacOSX() ||
3353 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3354 // PC-relative references to external symbols should go through $stub,
3355 // unless we're building with the leopard linker or later, which
3356 // automatically synthesizes these stubs.
3357 OpFlags = X86II::MO_DARWIN_STUB;
3360 Callee = DAG.getTargetExternalSymbol(
3361 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3362 } else if (Subtarget->isTarget64BitILP32() &&
3363 Callee->getValueType(0) == MVT::i32) {
3364 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3365 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3368 // Returns a chain & a flag for retval copy to use.
3369 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3370 SmallVector<SDValue, 8> Ops;
3372 if (!IsSibcall && isTailCall) {
3373 Chain = DAG.getCALLSEQ_END(Chain,
3374 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3375 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3376 InFlag = Chain.getValue(1);
3379 Ops.push_back(Chain);
3380 Ops.push_back(Callee);
3383 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3385 // Add argument registers to the end of the list so that they are known live
3387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3388 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3389 RegsToPass[i].second.getValueType()));
3391 // Add a register mask operand representing the call-preserved registers.
3392 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3393 assert(Mask && "Missing call preserved mask for calling convention");
3395 // If this is an invoke in a 32-bit function using a funclet-based
3396 // personality, assume the function clobbers all registers. If an exception
3397 // is thrown, the runtime will not restore CSRs.
3398 // FIXME: Model this more precisely so that we can register allocate across
3399 // the normal edge and spill and fill across the exceptional edge.
3400 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3401 const Function *CallerFn = MF.getFunction();
3402 EHPersonality Pers =
3403 CallerFn->hasPersonalityFn()
3404 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3405 : EHPersonality::Unknown;
3406 if (isFuncletEHPersonality(Pers))
3407 Mask = RegInfo->getNoPreservedMask();
3410 Ops.push_back(DAG.getRegisterMask(Mask));
3412 if (InFlag.getNode())
3413 Ops.push_back(InFlag);
3417 //// If this is the first return lowered for this function, add the regs
3418 //// to the liveout set for the function.
3419 // This isn't right, although it's probably harmless on x86; liveouts
3420 // should be computed from returns not tail calls. Consider a void
3421 // function making a tail call to a function returning int.
3422 MF.getFrameInfo()->setHasTailCall();
3423 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3426 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3427 InFlag = Chain.getValue(1);
3429 // Create the CALLSEQ_END node.
3430 unsigned NumBytesForCalleeToPop;
3431 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3432 DAG.getTarget().Options.GuaranteedTailCallOpt))
3433 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3434 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3435 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3436 SR == StackStructReturn)
3437 // If this is a call to a struct-return function, the callee
3438 // pops the hidden struct pointer, so we have to push it back.
3439 // This is common for Darwin/X86, Linux & Mingw32 targets.
3440 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3441 NumBytesForCalleeToPop = 4;
3443 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3445 // Returns a flag for retval copy to use.
3447 Chain = DAG.getCALLSEQ_END(Chain,
3448 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3449 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3452 InFlag = Chain.getValue(1);
3455 // Handle result values, copying them out of physregs into vregs that we
3457 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3458 Ins, dl, DAG, InVals);
3461 //===----------------------------------------------------------------------===//
3462 // Fast Calling Convention (tail call) implementation
3463 //===----------------------------------------------------------------------===//
3465 // Like std call, callee cleans arguments, convention except that ECX is
3466 // reserved for storing the tail called function address. Only 2 registers are
3467 // free for argument passing (inreg). Tail call optimization is performed
3469 // * tailcallopt is enabled
3470 // * caller/callee are fastcc
3471 // On X86_64 architecture with GOT-style position independent code only local
3472 // (within module) calls are supported at the moment.
3473 // To keep the stack aligned according to platform abi the function
3474 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3475 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3476 // If a tail called function callee has more arguments than the caller the
3477 // caller needs to make sure that there is room to move the RETADDR to. This is
3478 // achieved by reserving an area the size of the argument delta right after the
3479 // original RETADDR, but before the saved framepointer or the spilled registers
3480 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3492 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3495 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3496 SelectionDAG& DAG) const {
3497 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3498 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3499 unsigned StackAlignment = TFI.getStackAlignment();
3500 uint64_t AlignMask = StackAlignment - 1;
3501 int64_t Offset = StackSize;
3502 unsigned SlotSize = RegInfo->getSlotSize();
3503 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3504 // Number smaller than 12 so just add the difference.
3505 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3507 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3508 Offset = ((~AlignMask) & Offset) + StackAlignment +
3509 (StackAlignment-SlotSize);
3514 /// Return true if the given stack call argument is already available in the
3515 /// same position (relatively) of the caller's incoming argument stack.
3517 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3518 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3519 const X86InstrInfo *TII) {
3520 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3522 if (Arg.getOpcode() == ISD::CopyFromReg) {
3523 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3524 if (!TargetRegisterInfo::isVirtualRegister(VR))
3526 MachineInstr *Def = MRI->getVRegDef(VR);
3529 if (!Flags.isByVal()) {
3530 if (!TII->isLoadFromStackSlot(Def, FI))
3533 unsigned Opcode = Def->getOpcode();
3534 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3535 Opcode == X86::LEA64_32r) &&
3536 Def->getOperand(1).isFI()) {
3537 FI = Def->getOperand(1).getIndex();
3538 Bytes = Flags.getByValSize();
3542 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3543 if (Flags.isByVal())
3544 // ByVal argument is passed in as a pointer but it's now being
3545 // dereferenced. e.g.
3546 // define @foo(%struct.X* %A) {
3547 // tail call @bar(%struct.X* byval %A)
3550 SDValue Ptr = Ld->getBasePtr();
3551 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3554 FI = FINode->getIndex();
3555 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3556 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3557 FI = FINode->getIndex();
3558 Bytes = Flags.getByValSize();
3562 assert(FI != INT_MAX);
3563 if (!MFI->isFixedObjectIndex(FI))
3565 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3568 /// Check whether the call is eligible for tail call optimization. Targets
3569 /// that want to do tail call optimization should implement this function.
3570 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3571 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3572 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3573 const SmallVectorImpl<ISD::OutputArg> &Outs,
3574 const SmallVectorImpl<SDValue> &OutVals,
3575 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3576 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3579 // If -tailcallopt is specified, make fastcc functions tail-callable.
3580 const MachineFunction &MF = DAG.getMachineFunction();
3581 const Function *CallerF = MF.getFunction();
3583 // If the function return type is x86_fp80 and the callee return type is not,
3584 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3585 // perform a tailcall optimization here.
3586 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3589 CallingConv::ID CallerCC = CallerF->getCallingConv();
3590 bool CCMatch = CallerCC == CalleeCC;
3591 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3592 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3594 // Win64 functions have extra shadow space for argument homing. Don't do the
3595 // sibcall if the caller and callee have mismatched expectations for this
3597 if (IsCalleeWin64 != IsCallerWin64)
3600 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3601 if (IsTailCallConvention(CalleeCC) && CCMatch)
3606 // Look for obvious safe cases to perform tail call optimization that do not
3607 // require ABI changes. This is what gcc calls sibcall.
3609 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3610 // emit a special epilogue.
3611 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3612 if (RegInfo->needsStackRealignment(MF))
3615 // Also avoid sibcall optimization if either caller or callee uses struct
3616 // return semantics.
3617 if (isCalleeStructRet || isCallerStructRet)
3620 // An stdcall/thiscall caller is expected to clean up its arguments; the
3621 // callee isn't going to do that.
3622 // FIXME: this is more restrictive than needed. We could produce a tailcall
3623 // when the stack adjustment matches. For example, with a thiscall that takes
3624 // only one argument.
3625 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3626 CallerCC == CallingConv::X86_ThisCall))
3629 // Do not sibcall optimize vararg calls unless all arguments are passed via
3631 if (isVarArg && !Outs.empty()) {
3633 // Optimizing for varargs on Win64 is unlikely to be safe without
3634 // additional testing.
3635 if (IsCalleeWin64 || IsCallerWin64)
3638 SmallVector<CCValAssign, 16> ArgLocs;
3639 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3642 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3643 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3644 if (!ArgLocs[i].isRegLoc())
3648 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3649 // stack. Therefore, if it's not used by the call it is not safe to optimize
3650 // this into a sibcall.
3651 bool Unused = false;
3652 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3659 SmallVector<CCValAssign, 16> RVLocs;
3660 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3662 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3663 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3664 CCValAssign &VA = RVLocs[i];
3665 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3670 // If the calling conventions do not match, then we'd better make sure the
3671 // results are returned in the same way as what the caller expects.
3673 SmallVector<CCValAssign, 16> RVLocs1;
3674 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3676 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3678 SmallVector<CCValAssign, 16> RVLocs2;
3679 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3681 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3683 if (RVLocs1.size() != RVLocs2.size())
3685 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3686 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3688 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3690 if (RVLocs1[i].isRegLoc()) {
3691 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3694 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3700 // If the callee takes no arguments then go on to check the results of the
3702 if (!Outs.empty()) {
3703 // Check if stack adjustment is needed. For now, do not do this if any
3704 // argument is passed on the stack.
3705 SmallVector<CCValAssign, 16> ArgLocs;
3706 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3709 // Allocate shadow area for Win64
3711 CCInfo.AllocateStack(32, 8);
3713 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3714 if (CCInfo.getNextStackOffset()) {
3715 MachineFunction &MF = DAG.getMachineFunction();
3716 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3719 // Check if the arguments are already laid out in the right way as
3720 // the caller's fixed stack objects.
3721 MachineFrameInfo *MFI = MF.getFrameInfo();
3722 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3723 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3724 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3725 CCValAssign &VA = ArgLocs[i];
3726 SDValue Arg = OutVals[i];
3727 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3728 if (VA.getLocInfo() == CCValAssign::Indirect)
3730 if (!VA.isRegLoc()) {
3731 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3738 // If the tailcall address may be in a register, then make sure it's
3739 // possible to register allocate for it. In 32-bit, the call address can
3740 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3741 // callee-saved registers are restored. These happen to be the same
3742 // registers used to pass 'inreg' arguments so watch out for those.
3743 if (!Subtarget->is64Bit() &&
3744 ((!isa<GlobalAddressSDNode>(Callee) &&
3745 !isa<ExternalSymbolSDNode>(Callee)) ||
3746 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3747 unsigned NumInRegs = 0;
3748 // In PIC we need an extra register to formulate the address computation
3750 unsigned MaxInRegs =
3751 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3754 CCValAssign &VA = ArgLocs[i];
3757 unsigned Reg = VA.getLocReg();
3760 case X86::EAX: case X86::EDX: case X86::ECX:
3761 if (++NumInRegs == MaxInRegs)
3773 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3774 const TargetLibraryInfo *libInfo) const {
3775 return X86::createFastISel(funcInfo, libInfo);
3778 //===----------------------------------------------------------------------===//
3779 // Other Lowering Hooks
3780 //===----------------------------------------------------------------------===//
3782 static bool MayFoldLoad(SDValue Op) {
3783 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3786 static bool MayFoldIntoStore(SDValue Op) {
3787 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3790 static bool isTargetShuffle(unsigned Opcode) {
3792 default: return false;
3793 case X86ISD::BLENDI:
3794 case X86ISD::PSHUFB:
3795 case X86ISD::PSHUFD:
3796 case X86ISD::PSHUFHW:
3797 case X86ISD::PSHUFLW:
3799 case X86ISD::PALIGNR:
3800 case X86ISD::MOVLHPS:
3801 case X86ISD::MOVLHPD:
3802 case X86ISD::MOVHLPS:
3803 case X86ISD::MOVLPS:
3804 case X86ISD::MOVLPD:
3805 case X86ISD::MOVSHDUP:
3806 case X86ISD::MOVSLDUP:
3807 case X86ISD::MOVDDUP:
3810 case X86ISD::UNPCKL:
3811 case X86ISD::UNPCKH:
3812 case X86ISD::VPERMILPI:
3813 case X86ISD::VPERM2X128:
3814 case X86ISD::VPERMI:
3815 case X86ISD::VPERMV:
3816 case X86ISD::VPERMV3:
3821 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3822 SDValue V1, unsigned TargetMask,
3823 SelectionDAG &DAG) {
3825 default: llvm_unreachable("Unknown x86 shuffle node");
3826 case X86ISD::PSHUFD:
3827 case X86ISD::PSHUFHW:
3828 case X86ISD::PSHUFLW:
3829 case X86ISD::VPERMILPI:
3830 case X86ISD::VPERMI:
3831 return DAG.getNode(Opc, dl, VT, V1,
3832 DAG.getConstant(TargetMask, dl, MVT::i8));
3836 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3837 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3839 default: llvm_unreachable("Unknown x86 shuffle node");
3840 case X86ISD::MOVLHPS:
3841 case X86ISD::MOVLHPD:
3842 case X86ISD::MOVHLPS:
3843 case X86ISD::MOVLPS:
3844 case X86ISD::MOVLPD:
3847 case X86ISD::UNPCKL:
3848 case X86ISD::UNPCKH:
3849 return DAG.getNode(Opc, dl, VT, V1, V2);
3853 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3854 MachineFunction &MF = DAG.getMachineFunction();
3855 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3856 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3857 int ReturnAddrIndex = FuncInfo->getRAIndex();
3859 if (ReturnAddrIndex == 0) {
3860 // Set up a frame object for the return address.
3861 unsigned SlotSize = RegInfo->getSlotSize();
3862 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3865 FuncInfo->setRAIndex(ReturnAddrIndex);
3868 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3871 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3872 bool hasSymbolicDisplacement) {
3873 // Offset should fit into 32 bit immediate field.
3874 if (!isInt<32>(Offset))
3877 // If we don't have a symbolic displacement - we don't have any extra
3879 if (!hasSymbolicDisplacement)
3882 // FIXME: Some tweaks might be needed for medium code model.
3883 if (M != CodeModel::Small && M != CodeModel::Kernel)
3886 // For small code model we assume that latest object is 16MB before end of 31
3887 // bits boundary. We may also accept pretty large negative constants knowing
3888 // that all objects are in the positive half of address space.
3889 if (M == CodeModel::Small && Offset < 16*1024*1024)
3892 // For kernel code model we know that all object resist in the negative half
3893 // of 32bits address space. We may not accept negative offsets, since they may
3894 // be just off and we may accept pretty large positive ones.
3895 if (M == CodeModel::Kernel && Offset >= 0)
3901 /// Determines whether the callee is required to pop its own arguments.
3902 /// Callee pop is necessary to support tail calls.
3903 bool X86::isCalleePop(CallingConv::ID CallingConv,
3904 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3906 if (IsTailCallConvention(CallingConv))
3907 return IsVarArg ? false : TailCallOpt;
3909 switch (CallingConv) {
3912 case CallingConv::X86_StdCall:
3913 case CallingConv::X86_FastCall:
3914 case CallingConv::X86_ThisCall:
3919 /// \brief Return true if the condition is an unsigned comparison operation.
3920 static bool isX86CCUnsigned(unsigned X86CC) {
3922 default: llvm_unreachable("Invalid integer condition!");
3923 case X86::COND_E: return true;
3924 case X86::COND_G: return false;
3925 case X86::COND_GE: return false;
3926 case X86::COND_L: return false;
3927 case X86::COND_LE: return false;
3928 case X86::COND_NE: return true;
3929 case X86::COND_B: return true;
3930 case X86::COND_A: return true;
3931 case X86::COND_BE: return true;
3932 case X86::COND_AE: return true;
3934 llvm_unreachable("covered switch fell through?!");
3937 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3938 /// condition code, returning the condition code and the LHS/RHS of the
3939 /// comparison to make.
3940 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3941 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3943 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3944 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3945 // X > -1 -> X == 0, jump !sign.
3946 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3947 return X86::COND_NS;
3949 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3950 // X < 0 -> X == 0, jump on sign.
3953 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3955 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3956 return X86::COND_LE;
3960 switch (SetCCOpcode) {
3961 default: llvm_unreachable("Invalid integer condition!");
3962 case ISD::SETEQ: return X86::COND_E;
3963 case ISD::SETGT: return X86::COND_G;
3964 case ISD::SETGE: return X86::COND_GE;
3965 case ISD::SETLT: return X86::COND_L;
3966 case ISD::SETLE: return X86::COND_LE;
3967 case ISD::SETNE: return X86::COND_NE;
3968 case ISD::SETULT: return X86::COND_B;
3969 case ISD::SETUGT: return X86::COND_A;
3970 case ISD::SETULE: return X86::COND_BE;
3971 case ISD::SETUGE: return X86::COND_AE;
3975 // First determine if it is required or is profitable to flip the operands.
3977 // If LHS is a foldable load, but RHS is not, flip the condition.
3978 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3979 !ISD::isNON_EXTLoad(RHS.getNode())) {
3980 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3981 std::swap(LHS, RHS);
3984 switch (SetCCOpcode) {
3990 std::swap(LHS, RHS);
3994 // On a floating point condition, the flags are set as follows:
3996 // 0 | 0 | 0 | X > Y
3997 // 0 | 0 | 1 | X < Y
3998 // 1 | 0 | 0 | X == Y
3999 // 1 | 1 | 1 | unordered
4000 switch (SetCCOpcode) {
4001 default: llvm_unreachable("Condcode should be pre-legalized away");
4003 case ISD::SETEQ: return X86::COND_E;
4004 case ISD::SETOLT: // flipped
4006 case ISD::SETGT: return X86::COND_A;
4007 case ISD::SETOLE: // flipped
4009 case ISD::SETGE: return X86::COND_AE;
4010 case ISD::SETUGT: // flipped
4012 case ISD::SETLT: return X86::COND_B;
4013 case ISD::SETUGE: // flipped
4015 case ISD::SETLE: return X86::COND_BE;
4017 case ISD::SETNE: return X86::COND_NE;
4018 case ISD::SETUO: return X86::COND_P;
4019 case ISD::SETO: return X86::COND_NP;
4021 case ISD::SETUNE: return X86::COND_INVALID;
4025 /// Is there a floating point cmov for the specific X86 condition code?
4026 /// Current x86 isa includes the following FP cmov instructions:
4027 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4028 static bool hasFPCMov(unsigned X86CC) {
4044 /// Returns true if the target can instruction select the
4045 /// specified FP immediate natively. If false, the legalizer will
4046 /// materialize the FP immediate as a load from a constant pool.
4047 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4048 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4049 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4055 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4056 ISD::LoadExtType ExtTy,
4058 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4059 // relocation target a movq or addq instruction: don't let the load shrink.
4060 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4061 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4062 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4063 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4067 /// \brief Returns true if it is beneficial to convert a load of a constant
4068 /// to just the constant itself.
4069 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4071 assert(Ty->isIntegerTy());
4073 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4074 if (BitSize == 0 || BitSize > 64)
4079 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4080 unsigned Index) const {
4081 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4084 return (Index == 0 || Index == ResVT.getVectorNumElements());
4087 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4088 // Speculate cttz only if we can directly use TZCNT.
4089 return Subtarget->hasBMI();
4092 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4093 // Speculate ctlz only if we can directly use LZCNT.
4094 return Subtarget->hasLZCNT();
4097 /// Return true if every element in Mask, beginning
4098 /// from position Pos and ending in Pos+Size is undef.
4099 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4100 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4106 /// Return true if Val is undef or if its value falls within the
4107 /// specified range (L, H].
4108 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4109 return (Val < 0) || (Val >= Low && Val < Hi);
4112 /// Val is either less than zero (undef) or equal to the specified value.
4113 static bool isUndefOrEqual(int Val, int CmpVal) {
4114 return (Val < 0 || Val == CmpVal);
4117 /// Return true if every element in Mask, beginning
4118 /// from position Pos and ending in Pos+Size, falls within the specified
4119 /// sequential range (Low, Low+Size]. or is undef.
4120 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4121 unsigned Pos, unsigned Size, int Low) {
4122 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4123 if (!isUndefOrEqual(Mask[i], Low))
4128 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4129 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4130 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4131 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4132 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4135 // The index should be aligned on a vecWidth-bit boundary.
4137 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4139 MVT VT = N->getSimpleValueType(0);
4140 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4141 bool Result = (Index * ElSize) % vecWidth == 0;
4146 /// Return true if the specified INSERT_SUBVECTOR
4147 /// operand specifies a subvector insert that is suitable for input to
4148 /// insertion of 128 or 256-bit subvectors
4149 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4150 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4151 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4153 // The index should be aligned on a vecWidth-bit boundary.
4155 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4157 MVT VT = N->getSimpleValueType(0);
4158 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4159 bool Result = (Index * ElSize) % vecWidth == 0;
4164 bool X86::isVINSERT128Index(SDNode *N) {
4165 return isVINSERTIndex(N, 128);
4168 bool X86::isVINSERT256Index(SDNode *N) {
4169 return isVINSERTIndex(N, 256);
4172 bool X86::isVEXTRACT128Index(SDNode *N) {
4173 return isVEXTRACTIndex(N, 128);
4176 bool X86::isVEXTRACT256Index(SDNode *N) {
4177 return isVEXTRACTIndex(N, 256);
4180 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4181 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4182 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4183 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4186 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4188 MVT VecVT = N->getOperand(0).getSimpleValueType();
4189 MVT ElVT = VecVT.getVectorElementType();
4191 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4192 return Index / NumElemsPerChunk;
4195 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4196 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4197 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4198 llvm_unreachable("Illegal insert subvector for VINSERT");
4201 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4203 MVT VecVT = N->getSimpleValueType(0);
4204 MVT ElVT = VecVT.getVectorElementType();
4206 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4207 return Index / NumElemsPerChunk;
4210 /// Return the appropriate immediate to extract the specified
4211 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4212 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4213 return getExtractVEXTRACTImmediate(N, 128);
4216 /// Return the appropriate immediate to extract the specified
4217 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4218 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4219 return getExtractVEXTRACTImmediate(N, 256);
4222 /// Return the appropriate immediate to insert at the specified
4223 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4224 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4225 return getInsertVINSERTImmediate(N, 128);
4228 /// Return the appropriate immediate to insert at the specified
4229 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4230 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4231 return getInsertVINSERTImmediate(N, 256);
4234 /// Returns true if V is a constant integer zero.
4235 static bool isZero(SDValue V) {
4236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4237 return C && C->isNullValue();
4240 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4241 bool X86::isZeroNode(SDValue Elt) {
4244 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4245 return CFP->getValueAPF().isPosZero();
4249 // Build a vector of constants
4250 // Use an UNDEF node if MaskElt == -1.
4251 // Spilt 64-bit constants in the 32-bit mode.
4252 static SDValue getConstVector(ArrayRef<int> Values, EVT VT,
4254 SDLoc dl, bool IsMask = false) {
4256 SmallVector<SDValue, 32> Ops;
4259 EVT ConstVecVT = VT;
4260 unsigned NumElts = VT.getVectorNumElements();
4261 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4262 if (!In64BitMode && VT.getScalarType() == MVT::i64) {
4263 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4267 EVT EltVT = ConstVecVT.getScalarType();
4268 for (unsigned i = 0; i < NumElts; ++i) {
4269 bool IsUndef = Values[i] < 0 && IsMask;
4270 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4271 DAG.getConstant(Values[i], dl, EltVT);
4272 Ops.push_back(OpNode);
4274 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4275 DAG.getConstant(0, dl, EltVT));
4277 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4279 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4283 /// Returns a vector of specified type with all zero elements.
4284 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4285 SelectionDAG &DAG, SDLoc dl) {
4286 assert(VT.isVector() && "Expected a vector type");
4288 // Always build SSE zero vectors as <4 x i32> bitcasted
4289 // to their dest type. This ensures they get CSE'd.
4291 if (VT.is128BitVector()) { // SSE
4292 if (Subtarget->hasSSE2()) { // SSE2
4293 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4294 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4296 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4297 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4299 } else if (VT.is256BitVector()) { // AVX
4300 if (Subtarget->hasInt256()) { // AVX2
4301 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4302 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4303 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4305 // 256-bit logic and arithmetic instructions in AVX are all
4306 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4307 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4308 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4309 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4311 } else if (VT.is512BitVector()) { // AVX-512
4312 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4313 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4314 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4315 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4316 } else if (VT.getScalarType() == MVT::i1) {
4318 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4319 && "Unexpected vector type");
4320 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4321 && "Unexpected vector type");
4322 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4323 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4324 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4326 llvm_unreachable("Unexpected vector type");
4328 return DAG.getBitcast(VT, Vec);
4331 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4332 SelectionDAG &DAG, SDLoc dl,
4333 unsigned vectorWidth) {
4334 assert((vectorWidth == 128 || vectorWidth == 256) &&
4335 "Unsupported vector width");
4336 EVT VT = Vec.getValueType();
4337 EVT ElVT = VT.getVectorElementType();
4338 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4339 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4340 VT.getVectorNumElements()/Factor);
4342 // Extract from UNDEF is UNDEF.
4343 if (Vec.getOpcode() == ISD::UNDEF)
4344 return DAG.getUNDEF(ResultVT);
4346 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4347 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4349 // This is the index of the first element of the vectorWidth-bit chunk
4351 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4354 // If the input is a buildvector just emit a smaller one.
4355 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4356 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4357 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4360 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4361 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4364 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4365 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4366 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4367 /// instructions or a simple subregister reference. Idx is an index in the
4368 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4369 /// lowering EXTRACT_VECTOR_ELT operations easier.
4370 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4371 SelectionDAG &DAG, SDLoc dl) {
4372 assert((Vec.getValueType().is256BitVector() ||
4373 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4374 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4377 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4378 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4379 SelectionDAG &DAG, SDLoc dl) {
4380 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4381 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4384 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4385 unsigned IdxVal, SelectionDAG &DAG,
4386 SDLoc dl, unsigned vectorWidth) {
4387 assert((vectorWidth == 128 || vectorWidth == 256) &&
4388 "Unsupported vector width");
4389 // Inserting UNDEF is Result
4390 if (Vec.getOpcode() == ISD::UNDEF)
4392 EVT VT = Vec.getValueType();
4393 EVT ElVT = VT.getVectorElementType();
4394 EVT ResultVT = Result.getValueType();
4396 // Insert the relevant vectorWidth bits.
4397 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4399 // This is the index of the first element of the vectorWidth-bit chunk
4401 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4404 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4405 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4408 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4409 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4410 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4411 /// simple superregister reference. Idx is an index in the 128 bits
4412 /// we want. It need not be aligned to a 128-bit boundary. That makes
4413 /// lowering INSERT_VECTOR_ELT operations easier.
4414 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4415 SelectionDAG &DAG, SDLoc dl) {
4416 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4418 // For insertion into the zero index (low half) of a 256-bit vector, it is
4419 // more efficient to generate a blend with immediate instead of an insert*128.
4420 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4421 // extend the subvector to the size of the result vector. Make sure that
4422 // we are not recursing on that node by checking for undef here.
4423 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4424 Result.getOpcode() != ISD::UNDEF) {
4425 EVT ResultVT = Result.getValueType();
4426 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4427 SDValue Undef = DAG.getUNDEF(ResultVT);
4428 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4431 // The blend instruction, and therefore its mask, depend on the data type.
4432 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4433 if (ScalarType.isFloatingPoint()) {
4434 // Choose either vblendps (float) or vblendpd (double).
4435 unsigned ScalarSize = ScalarType.getSizeInBits();
4436 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4437 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4438 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4439 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4442 const X86Subtarget &Subtarget =
4443 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4445 // AVX2 is needed for 256-bit integer blend support.
4446 // Integers must be cast to 32-bit because there is only vpblendd;
4447 // vpblendw can't be used for this because it has a handicapped mask.
4449 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4450 // is still more efficient than using the wrong domain vinsertf128 that
4451 // will be created by InsertSubVector().
4452 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4454 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4455 Vec256 = DAG.getBitcast(CastVT, Vec256);
4456 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4457 return DAG.getBitcast(ResultVT, Vec256);
4460 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4463 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4464 SelectionDAG &DAG, SDLoc dl) {
4465 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4466 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4469 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4470 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4471 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4472 /// large BUILD_VECTORS.
4473 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4474 unsigned NumElems, SelectionDAG &DAG,
4476 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4477 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4480 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4481 unsigned NumElems, SelectionDAG &DAG,
4483 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4484 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4487 /// Returns a vector of specified type with all bits set.
4488 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4489 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4490 /// Then bitcast to their original type, ensuring they get CSE'd.
4491 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4492 SelectionDAG &DAG, SDLoc dl) {
4493 assert(VT.isVector() && "Expected a vector type");
4495 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4497 if (VT.is512BitVector()) {
4498 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4499 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4500 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4501 } else if (VT.is256BitVector()) {
4502 if (Subtarget->hasInt256()) { // AVX2
4503 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4504 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4506 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4507 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4509 } else if (VT.is128BitVector()) {
4510 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4512 llvm_unreachable("Unexpected vector type");
4514 return DAG.getBitcast(VT, Vec);
4517 /// Returns a vector_shuffle node for an unpackl operation.
4518 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4520 unsigned NumElems = VT.getVectorNumElements();
4521 SmallVector<int, 8> Mask;
4522 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4524 Mask.push_back(i + NumElems);
4526 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4529 /// Returns a vector_shuffle node for an unpackh operation.
4530 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4532 unsigned NumElems = VT.getVectorNumElements();
4533 SmallVector<int, 8> Mask;
4534 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4535 Mask.push_back(i + Half);
4536 Mask.push_back(i + NumElems + Half);
4538 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4541 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4542 /// This produces a shuffle where the low element of V2 is swizzled into the
4543 /// zero/undef vector, landing at element Idx.
4544 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4545 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4547 const X86Subtarget *Subtarget,
4548 SelectionDAG &DAG) {
4549 MVT VT = V2.getSimpleValueType();
4551 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4552 unsigned NumElems = VT.getVectorNumElements();
4553 SmallVector<int, 16> MaskVec;
4554 for (unsigned i = 0; i != NumElems; ++i)
4555 // If this is the insertion idx, put the low elt of V2 here.
4556 MaskVec.push_back(i == Idx ? NumElems : i);
4557 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4560 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4561 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4562 /// uses one source. Note that this will set IsUnary for shuffles which use a
4563 /// single input multiple times, and in those cases it will
4564 /// adjust the mask to only have indices within that single input.
4565 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4566 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4567 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4568 unsigned NumElems = VT.getVectorNumElements();
4572 bool IsFakeUnary = false;
4573 switch(N->getOpcode()) {
4574 case X86ISD::BLENDI:
4575 ImmN = N->getOperand(N->getNumOperands()-1);
4576 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4579 ImmN = N->getOperand(N->getNumOperands()-1);
4580 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4581 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4583 case X86ISD::UNPCKH:
4584 DecodeUNPCKHMask(VT, Mask);
4585 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4587 case X86ISD::UNPCKL:
4588 DecodeUNPCKLMask(VT, Mask);
4589 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4591 case X86ISD::MOVHLPS:
4592 DecodeMOVHLPSMask(NumElems, Mask);
4593 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4595 case X86ISD::MOVLHPS:
4596 DecodeMOVLHPSMask(NumElems, Mask);
4597 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4599 case X86ISD::PALIGNR:
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4603 case X86ISD::PSHUFD:
4604 case X86ISD::VPERMILPI:
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4609 case X86ISD::PSHUFHW:
4610 ImmN = N->getOperand(N->getNumOperands()-1);
4611 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4614 case X86ISD::PSHUFLW:
4615 ImmN = N->getOperand(N->getNumOperands()-1);
4616 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4619 case X86ISD::PSHUFB: {
4621 SDValue MaskNode = N->getOperand(1);
4622 while (MaskNode->getOpcode() == ISD::BITCAST)
4623 MaskNode = MaskNode->getOperand(0);
4625 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4626 // If we have a build-vector, then things are easy.
4627 EVT VT = MaskNode.getValueType();
4628 assert(VT.isVector() &&
4629 "Can't produce a non-vector with a build_vector!");
4630 if (!VT.isInteger())
4633 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4635 SmallVector<uint64_t, 32> RawMask;
4636 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4637 SDValue Op = MaskNode->getOperand(i);
4638 if (Op->getOpcode() == ISD::UNDEF) {
4639 RawMask.push_back((uint64_t)SM_SentinelUndef);
4642 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4645 APInt MaskElement = CN->getAPIntValue();
4647 // We now have to decode the element which could be any integer size and
4648 // extract each byte of it.
4649 for (int j = 0; j < NumBytesPerElement; ++j) {
4650 // Note that this is x86 and so always little endian: the low byte is
4651 // the first byte of the mask.
4652 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4653 MaskElement = MaskElement.lshr(8);
4656 DecodePSHUFBMask(RawMask, Mask);
4660 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4664 SDValue Ptr = MaskLoad->getBasePtr();
4665 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4666 Ptr->getOpcode() == X86ISD::WrapperRIP)
4667 Ptr = Ptr->getOperand(0);
4669 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4670 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4673 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4674 DecodePSHUFBMask(C, Mask);
4682 case X86ISD::VPERMI:
4683 ImmN = N->getOperand(N->getNumOperands()-1);
4684 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4689 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4691 case X86ISD::VPERM2X128:
4692 ImmN = N->getOperand(N->getNumOperands()-1);
4693 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4694 if (Mask.empty()) return false;
4695 // Mask only contains negative index if an element is zero.
4696 if (std::any_of(Mask.begin(), Mask.end(),
4697 [](int M){ return M == SM_SentinelZero; }))
4700 case X86ISD::MOVSLDUP:
4701 DecodeMOVSLDUPMask(VT, Mask);
4704 case X86ISD::MOVSHDUP:
4705 DecodeMOVSHDUPMask(VT, Mask);
4708 case X86ISD::MOVDDUP:
4709 DecodeMOVDDUPMask(VT, Mask);
4712 case X86ISD::MOVLHPD:
4713 case X86ISD::MOVLPD:
4714 case X86ISD::MOVLPS:
4715 // Not yet implemented
4717 case X86ISD::VPERMV: {
4719 SDValue MaskNode = N->getOperand(0);
4720 while (MaskNode->getOpcode() == ISD::BITCAST)
4721 MaskNode = MaskNode->getOperand(0);
4723 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4724 SmallVector<uint64_t, 32> RawMask;
4725 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4726 // If we have a build-vector, then things are easy.
4727 assert(MaskNode.getValueType().isInteger() &&
4728 MaskNode.getValueType().getVectorNumElements() ==
4729 VT.getVectorNumElements());
4731 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4732 SDValue Op = MaskNode->getOperand(i);
4733 if (Op->getOpcode() == ISD::UNDEF)
4734 RawMask.push_back((uint64_t)SM_SentinelUndef);
4735 else if (isa<ConstantSDNode>(Op)) {
4736 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4737 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4741 DecodeVPERMVMask(RawMask, Mask);
4744 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4745 unsigned NumEltsInMask = MaskNode->getNumOperands();
4746 MaskNode = MaskNode->getOperand(0);
4747 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4749 APInt MaskEltValue = CN->getAPIntValue();
4750 for (unsigned i = 0; i < NumEltsInMask; ++i)
4751 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4752 DecodeVPERMVMask(RawMask, Mask);
4755 // It may be a scalar load
4758 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4762 SDValue Ptr = MaskLoad->getBasePtr();
4763 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4764 Ptr->getOpcode() == X86ISD::WrapperRIP)
4765 Ptr = Ptr->getOperand(0);
4767 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4768 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4771 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4773 DecodeVPERMVMask(C, VT, Mask);
4780 case X86ISD::VPERMV3: {
4782 SDValue MaskNode = N->getOperand(1);
4783 while (MaskNode->getOpcode() == ISD::BITCAST)
4784 MaskNode = MaskNode->getOperand(1);
4786 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4787 // If we have a build-vector, then things are easy.
4788 assert(MaskNode.getValueType().isInteger() &&
4789 MaskNode.getValueType().getVectorNumElements() ==
4790 VT.getVectorNumElements());
4792 SmallVector<uint64_t, 32> RawMask;
4793 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4795 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4796 SDValue Op = MaskNode->getOperand(i);
4797 if (Op->getOpcode() == ISD::UNDEF)
4798 RawMask.push_back((uint64_t)SM_SentinelUndef);
4800 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4803 APInt MaskElement = CN->getAPIntValue();
4804 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4807 DecodeVPERMV3Mask(RawMask, Mask);
4811 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4815 SDValue Ptr = MaskLoad->getBasePtr();
4816 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4817 Ptr->getOpcode() == X86ISD::WrapperRIP)
4818 Ptr = Ptr->getOperand(0);
4820 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4821 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4824 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4826 DecodeVPERMV3Mask(C, VT, Mask);
4833 default: llvm_unreachable("unknown target shuffle node");
4836 // If we have a fake unary shuffle, the shuffle mask is spread across two
4837 // inputs that are actually the same node. Re-map the mask to always point
4838 // into the first input.
4841 if (M >= (int)Mask.size())
4847 /// Returns the scalar element that will make up the ith
4848 /// element of the result of the vector shuffle.
4849 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4852 return SDValue(); // Limit search depth.
4854 SDValue V = SDValue(N, 0);
4855 EVT VT = V.getValueType();
4856 unsigned Opcode = V.getOpcode();
4858 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4859 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4860 int Elt = SV->getMaskElt(Index);
4863 return DAG.getUNDEF(VT.getVectorElementType());
4865 unsigned NumElems = VT.getVectorNumElements();
4866 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4867 : SV->getOperand(1);
4868 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4871 // Recurse into target specific vector shuffles to find scalars.
4872 if (isTargetShuffle(Opcode)) {
4873 MVT ShufVT = V.getSimpleValueType();
4874 unsigned NumElems = ShufVT.getVectorNumElements();
4875 SmallVector<int, 16> ShuffleMask;
4878 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4881 int Elt = ShuffleMask[Index];
4883 return DAG.getUNDEF(ShufVT.getVectorElementType());
4885 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4887 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4891 // Actual nodes that may contain scalar elements
4892 if (Opcode == ISD::BITCAST) {
4893 V = V.getOperand(0);
4894 EVT SrcVT = V.getValueType();
4895 unsigned NumElems = VT.getVectorNumElements();
4897 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4901 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4902 return (Index == 0) ? V.getOperand(0)
4903 : DAG.getUNDEF(VT.getVectorElementType());
4905 if (V.getOpcode() == ISD::BUILD_VECTOR)
4906 return V.getOperand(Index);
4911 /// Custom lower build_vector of v16i8.
4912 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4913 unsigned NumNonZero, unsigned NumZero,
4915 const X86Subtarget* Subtarget,
4916 const TargetLowering &TLI) {
4924 // SSE4.1 - use PINSRB to insert each byte directly.
4925 if (Subtarget->hasSSE41()) {
4926 for (unsigned i = 0; i < 16; ++i) {
4927 bool isNonZero = (NonZeros & (1 << i)) != 0;
4931 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4933 V = DAG.getUNDEF(MVT::v16i8);
4936 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4937 MVT::v16i8, V, Op.getOperand(i),
4938 DAG.getIntPtrConstant(i, dl));
4945 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4946 for (unsigned i = 0; i < 16; ++i) {
4947 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4948 if (ThisIsNonZero && First) {
4950 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4952 V = DAG.getUNDEF(MVT::v8i16);
4957 SDValue ThisElt, LastElt;
4958 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4959 if (LastIsNonZero) {
4960 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4961 MVT::i16, Op.getOperand(i-1));
4963 if (ThisIsNonZero) {
4964 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4965 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4966 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4968 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4972 if (ThisElt.getNode())
4973 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4974 DAG.getIntPtrConstant(i/2, dl));
4978 return DAG.getBitcast(MVT::v16i8, V);
4981 /// Custom lower build_vector of v8i16.
4982 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4983 unsigned NumNonZero, unsigned NumZero,
4985 const X86Subtarget* Subtarget,
4986 const TargetLowering &TLI) {
4993 for (unsigned i = 0; i < 8; ++i) {
4994 bool isNonZero = (NonZeros & (1 << i)) != 0;
4998 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5000 V = DAG.getUNDEF(MVT::v8i16);
5003 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5004 MVT::v8i16, V, Op.getOperand(i),
5005 DAG.getIntPtrConstant(i, dl));
5012 /// Custom lower build_vector of v4i32 or v4f32.
5013 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5014 const X86Subtarget *Subtarget,
5015 const TargetLowering &TLI) {
5016 // Find all zeroable elements.
5017 std::bitset<4> Zeroable;
5018 for (int i=0; i < 4; ++i) {
5019 SDValue Elt = Op->getOperand(i);
5020 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5022 assert(Zeroable.size() - Zeroable.count() > 1 &&
5023 "We expect at least two non-zero elements!");
5025 // We only know how to deal with build_vector nodes where elements are either
5026 // zeroable or extract_vector_elt with constant index.
5027 SDValue FirstNonZero;
5028 unsigned FirstNonZeroIdx;
5029 for (unsigned i=0; i < 4; ++i) {
5032 SDValue Elt = Op->getOperand(i);
5033 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5034 !isa<ConstantSDNode>(Elt.getOperand(1)))
5036 // Make sure that this node is extracting from a 128-bit vector.
5037 MVT VT = Elt.getOperand(0).getSimpleValueType();
5038 if (!VT.is128BitVector())
5040 if (!FirstNonZero.getNode()) {
5042 FirstNonZeroIdx = i;
5046 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5047 SDValue V1 = FirstNonZero.getOperand(0);
5048 MVT VT = V1.getSimpleValueType();
5050 // See if this build_vector can be lowered as a blend with zero.
5052 unsigned EltMaskIdx, EltIdx;
5054 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5055 if (Zeroable[EltIdx]) {
5056 // The zero vector will be on the right hand side.
5057 Mask[EltIdx] = EltIdx+4;
5061 Elt = Op->getOperand(EltIdx);
5062 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5063 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5064 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5066 Mask[EltIdx] = EltIdx;
5070 // Let the shuffle legalizer deal with blend operations.
5071 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5072 if (V1.getSimpleValueType() != VT)
5073 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5074 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5077 // See if we can lower this build_vector to a INSERTPS.
5078 if (!Subtarget->hasSSE41())
5081 SDValue V2 = Elt.getOperand(0);
5082 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5085 bool CanFold = true;
5086 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5090 SDValue Current = Op->getOperand(i);
5091 SDValue SrcVector = Current->getOperand(0);
5094 CanFold = SrcVector == V1 &&
5095 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5101 assert(V1.getNode() && "Expected at least two non-zero elements!");
5102 if (V1.getSimpleValueType() != MVT::v4f32)
5103 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5104 if (V2.getSimpleValueType() != MVT::v4f32)
5105 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5107 // Ok, we can emit an INSERTPS instruction.
5108 unsigned ZMask = Zeroable.to_ulong();
5110 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5111 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5113 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5114 DAG.getIntPtrConstant(InsertPSMask, DL));
5115 return DAG.getBitcast(VT, Result);
5118 /// Return a vector logical shift node.
5119 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5120 unsigned NumBits, SelectionDAG &DAG,
5121 const TargetLowering &TLI, SDLoc dl) {
5122 assert(VT.is128BitVector() && "Unknown type for VShift");
5123 MVT ShVT = MVT::v2i64;
5124 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5125 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5126 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5127 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5128 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5129 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5133 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5135 // Check if the scalar load can be widened into a vector load. And if
5136 // the address is "base + cst" see if the cst can be "absorbed" into
5137 // the shuffle mask.
5138 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5139 SDValue Ptr = LD->getBasePtr();
5140 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5142 EVT PVT = LD->getValueType(0);
5143 if (PVT != MVT::i32 && PVT != MVT::f32)
5148 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5149 FI = FINode->getIndex();
5151 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5152 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5153 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5154 Offset = Ptr.getConstantOperandVal(1);
5155 Ptr = Ptr.getOperand(0);
5160 // FIXME: 256-bit vector instructions don't require a strict alignment,
5161 // improve this code to support it better.
5162 unsigned RequiredAlign = VT.getSizeInBits()/8;
5163 SDValue Chain = LD->getChain();
5164 // Make sure the stack object alignment is at least 16 or 32.
5165 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5166 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5167 if (MFI->isFixedObjectIndex(FI)) {
5168 // Can't change the alignment. FIXME: It's possible to compute
5169 // the exact stack offset and reference FI + adjust offset instead.
5170 // If someone *really* cares about this. That's the way to implement it.
5173 MFI->setObjectAlignment(FI, RequiredAlign);
5177 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5178 // Ptr + (Offset & ~15).
5181 if ((Offset % RequiredAlign) & 3)
5183 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5186 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5187 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5190 int EltNo = (Offset - StartOffset) >> 2;
5191 unsigned NumElems = VT.getVectorNumElements();
5193 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5194 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5195 LD->getPointerInfo().getWithOffset(StartOffset),
5196 false, false, false, 0);
5198 SmallVector<int, 8> Mask(NumElems, EltNo);
5200 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5206 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5207 /// elements can be replaced by a single large load which has the same value as
5208 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5210 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5212 /// FIXME: we'd also like to handle the case where the last elements are zero
5213 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5214 /// There's even a handy isZeroNode for that purpose.
5215 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5216 SDLoc &DL, SelectionDAG &DAG,
5217 bool isAfterLegalize) {
5218 unsigned NumElems = Elts.size();
5220 LoadSDNode *LDBase = nullptr;
5221 unsigned LastLoadedElt = -1U;
5223 // For each element in the initializer, see if we've found a load or an undef.
5224 // If we don't find an initial load element, or later load elements are
5225 // non-consecutive, bail out.
5226 for (unsigned i = 0; i < NumElems; ++i) {
5227 SDValue Elt = Elts[i];
5228 // Look through a bitcast.
5229 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5230 Elt = Elt.getOperand(0);
5231 if (!Elt.getNode() ||
5232 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5235 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5237 LDBase = cast<LoadSDNode>(Elt.getNode());
5241 if (Elt.getOpcode() == ISD::UNDEF)
5244 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5245 EVT LdVT = Elt.getValueType();
5246 // Each loaded element must be the correct fractional portion of the
5247 // requested vector load.
5248 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5250 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5255 // If we have found an entire vector of loads and undefs, then return a large
5256 // load of the entire vector width starting at the base pointer. If we found
5257 // consecutive loads for the low half, generate a vzext_load node.
5258 if (LastLoadedElt == NumElems - 1) {
5259 assert(LDBase && "Did not find base load for merging consecutive loads");
5260 EVT EltVT = LDBase->getValueType(0);
5261 // Ensure that the input vector size for the merged loads matches the
5262 // cumulative size of the input elements.
5263 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5266 if (isAfterLegalize &&
5267 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5270 SDValue NewLd = SDValue();
5272 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5273 LDBase->getPointerInfo(), LDBase->isVolatile(),
5274 LDBase->isNonTemporal(), LDBase->isInvariant(),
5275 LDBase->getAlignment());
5277 if (LDBase->hasAnyUseOfValue(1)) {
5278 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5280 SDValue(NewLd.getNode(), 1));
5281 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5282 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5283 SDValue(NewLd.getNode(), 1));
5289 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5290 //of a v4i32 / v4f32. It's probably worth generalizing.
5291 EVT EltVT = VT.getVectorElementType();
5292 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5293 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5294 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5295 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5297 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5298 LDBase->getPointerInfo(),
5299 LDBase->getAlignment(),
5300 false/*isVolatile*/, true/*ReadMem*/,
5303 // Make sure the newly-created LOAD is in the same position as LDBase in
5304 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5305 // update uses of LDBase's output chain to use the TokenFactor.
5306 if (LDBase->hasAnyUseOfValue(1)) {
5307 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5308 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5309 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5310 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5311 SDValue(ResNode.getNode(), 1));
5314 return DAG.getBitcast(VT, ResNode);
5319 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5320 /// to generate a splat value for the following cases:
5321 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5322 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5323 /// a scalar load, or a constant.
5324 /// The VBROADCAST node is returned when a pattern is found,
5325 /// or SDValue() otherwise.
5326 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5327 SelectionDAG &DAG) {
5328 // VBROADCAST requires AVX.
5329 // TODO: Splats could be generated for non-AVX CPUs using SSE
5330 // instructions, but there's less potential gain for only 128-bit vectors.
5331 if (!Subtarget->hasAVX())
5334 MVT VT = Op.getSimpleValueType();
5337 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5338 "Unsupported vector type for broadcast.");
5343 switch (Op.getOpcode()) {
5345 // Unknown pattern found.
5348 case ISD::BUILD_VECTOR: {
5349 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5350 BitVector UndefElements;
5351 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5353 // We need a splat of a single value to use broadcast, and it doesn't
5354 // make any sense if the value is only in one element of the vector.
5355 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5359 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5360 Ld.getOpcode() == ISD::ConstantFP);
5362 // Make sure that all of the users of a non-constant load are from the
5363 // BUILD_VECTOR node.
5364 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5369 case ISD::VECTOR_SHUFFLE: {
5370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5372 // Shuffles must have a splat mask where the first element is
5374 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5377 SDValue Sc = Op.getOperand(0);
5378 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5379 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5381 if (!Subtarget->hasInt256())
5384 // Use the register form of the broadcast instruction available on AVX2.
5385 if (VT.getSizeInBits() >= 256)
5386 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5387 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5390 Ld = Sc.getOperand(0);
5391 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5392 Ld.getOpcode() == ISD::ConstantFP);
5394 // The scalar_to_vector node and the suspected
5395 // load node must have exactly one user.
5396 // Constants may have multiple users.
5398 // AVX-512 has register version of the broadcast
5399 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5400 Ld.getValueType().getSizeInBits() >= 32;
5401 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5408 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5409 bool IsGE256 = (VT.getSizeInBits() >= 256);
5411 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5412 // instruction to save 8 or more bytes of constant pool data.
5413 // TODO: If multiple splats are generated to load the same constant,
5414 // it may be detrimental to overall size. There needs to be a way to detect
5415 // that condition to know if this is truly a size win.
5416 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5418 // Handle broadcasting a single constant scalar from the constant pool
5420 // On Sandybridge (no AVX2), it is still better to load a constant vector
5421 // from the constant pool and not to broadcast it from a scalar.
5422 // But override that restriction when optimizing for size.
5423 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5424 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5425 EVT CVT = Ld.getValueType();
5426 assert(!CVT.isVector() && "Must not broadcast a vector type");
5428 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5429 // For size optimization, also splat v2f64 and v2i64, and for size opt
5430 // with AVX2, also splat i8 and i16.
5431 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5432 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5433 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5434 const Constant *C = nullptr;
5435 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5436 C = CI->getConstantIntValue();
5437 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5438 C = CF->getConstantFPValue();
5440 assert(C && "Invalid constant type");
5442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5444 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5445 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5447 CVT, dl, DAG.getEntryNode(), CP,
5448 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5449 false, false, Alignment);
5451 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5455 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5457 // Handle AVX2 in-register broadcasts.
5458 if (!IsLoad && Subtarget->hasInt256() &&
5459 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5460 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5462 // The scalar source must be a normal load.
5466 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5467 (Subtarget->hasVLX() && ScalarSize == 64))
5468 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5470 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5471 // double since there is no vbroadcastsd xmm
5472 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5473 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5474 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5477 // Unsupported broadcast.
5481 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5482 /// underlying vector and index.
5484 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5486 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5488 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5489 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5492 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5494 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5496 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5497 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5500 // In this case the vector is the extract_subvector expression and the index
5501 // is 2, as specified by the shuffle.
5502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5503 SDValue ShuffleVec = SVOp->getOperand(0);
5504 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5505 assert(ShuffleVecVT.getVectorElementType() ==
5506 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5508 int ShuffleIdx = SVOp->getMaskElt(Idx);
5509 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5510 ExtractedFromVec = ShuffleVec;
5516 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5517 MVT VT = Op.getSimpleValueType();
5519 // Skip if insert_vec_elt is not supported.
5520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5521 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5525 unsigned NumElems = Op.getNumOperands();
5529 SmallVector<unsigned, 4> InsertIndices;
5530 SmallVector<int, 8> Mask(NumElems, -1);
5532 for (unsigned i = 0; i != NumElems; ++i) {
5533 unsigned Opc = Op.getOperand(i).getOpcode();
5535 if (Opc == ISD::UNDEF)
5538 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5539 // Quit if more than 1 elements need inserting.
5540 if (InsertIndices.size() > 1)
5543 InsertIndices.push_back(i);
5547 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5548 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5549 // Quit if non-constant index.
5550 if (!isa<ConstantSDNode>(ExtIdx))
5552 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5554 // Quit if extracted from vector of different type.
5555 if (ExtractedFromVec.getValueType() != VT)
5558 if (!VecIn1.getNode())
5559 VecIn1 = ExtractedFromVec;
5560 else if (VecIn1 != ExtractedFromVec) {
5561 if (!VecIn2.getNode())
5562 VecIn2 = ExtractedFromVec;
5563 else if (VecIn2 != ExtractedFromVec)
5564 // Quit if more than 2 vectors to shuffle
5568 if (ExtractedFromVec == VecIn1)
5570 else if (ExtractedFromVec == VecIn2)
5571 Mask[i] = Idx + NumElems;
5574 if (!VecIn1.getNode())
5577 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5578 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5579 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5580 unsigned Idx = InsertIndices[i];
5581 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5582 DAG.getIntPtrConstant(Idx, DL));
5588 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5589 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5590 Op.getScalarValueSizeInBits() == 1 &&
5591 "Can not convert non-constant vector");
5592 uint64_t Immediate = 0;
5593 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5594 SDValue In = Op.getOperand(idx);
5595 if (In.getOpcode() != ISD::UNDEF)
5596 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5600 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5601 return DAG.getConstant(Immediate, dl, VT);
5603 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5605 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5607 MVT VT = Op.getSimpleValueType();
5608 assert((VT.getVectorElementType() == MVT::i1) &&
5609 "Unexpected type in LowerBUILD_VECTORvXi1!");
5612 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5613 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5614 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5615 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5618 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5619 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5620 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5621 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5624 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5625 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5626 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5627 return DAG.getBitcast(VT, Imm);
5628 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5629 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5630 DAG.getIntPtrConstant(0, dl));
5633 // Vector has one or more non-const elements
5634 uint64_t Immediate = 0;
5635 SmallVector<unsigned, 16> NonConstIdx;
5636 bool IsSplat = true;
5637 bool HasConstElts = false;
5639 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5640 SDValue In = Op.getOperand(idx);
5641 if (In.getOpcode() == ISD::UNDEF)
5643 if (!isa<ConstantSDNode>(In))
5644 NonConstIdx.push_back(idx);
5646 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5647 HasConstElts = true;
5651 else if (In != Op.getOperand(SplatIdx))
5655 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5657 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5658 DAG.getConstant(1, dl, VT),
5659 DAG.getConstant(0, dl, VT));
5661 // insert elements one by one
5665 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5666 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5668 else if (HasConstElts)
5669 Imm = DAG.getConstant(0, dl, VT);
5671 Imm = DAG.getUNDEF(VT);
5672 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5673 DstVec = DAG.getBitcast(VT, Imm);
5675 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5676 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5677 DAG.getIntPtrConstant(0, dl));
5680 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5681 unsigned InsertIdx = NonConstIdx[i];
5682 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5683 Op.getOperand(InsertIdx),
5684 DAG.getIntPtrConstant(InsertIdx, dl));
5689 /// \brief Return true if \p N implements a horizontal binop and return the
5690 /// operands for the horizontal binop into V0 and V1.
5692 /// This is a helper function of LowerToHorizontalOp().
5693 /// This function checks that the build_vector \p N in input implements a
5694 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5695 /// operation to match.
5696 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5697 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5698 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5701 /// This function only analyzes elements of \p N whose indices are
5702 /// in range [BaseIdx, LastIdx).
5703 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5705 unsigned BaseIdx, unsigned LastIdx,
5706 SDValue &V0, SDValue &V1) {
5707 EVT VT = N->getValueType(0);
5709 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5710 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5711 "Invalid Vector in input!");
5713 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5714 bool CanFold = true;
5715 unsigned ExpectedVExtractIdx = BaseIdx;
5716 unsigned NumElts = LastIdx - BaseIdx;
5717 V0 = DAG.getUNDEF(VT);
5718 V1 = DAG.getUNDEF(VT);
5720 // Check if N implements a horizontal binop.
5721 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5722 SDValue Op = N->getOperand(i + BaseIdx);
5725 if (Op->getOpcode() == ISD::UNDEF) {
5726 // Update the expected vector extract index.
5727 if (i * 2 == NumElts)
5728 ExpectedVExtractIdx = BaseIdx;
5729 ExpectedVExtractIdx += 2;
5733 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5738 SDValue Op0 = Op.getOperand(0);
5739 SDValue Op1 = Op.getOperand(1);
5741 // Try to match the following pattern:
5742 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5743 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5744 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5745 Op0.getOperand(0) == Op1.getOperand(0) &&
5746 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5747 isa<ConstantSDNode>(Op1.getOperand(1)));
5751 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5752 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5754 if (i * 2 < NumElts) {
5755 if (V0.getOpcode() == ISD::UNDEF) {
5756 V0 = Op0.getOperand(0);
5757 if (V0.getValueType() != VT)
5761 if (V1.getOpcode() == ISD::UNDEF) {
5762 V1 = Op0.getOperand(0);
5763 if (V1.getValueType() != VT)
5766 if (i * 2 == NumElts)
5767 ExpectedVExtractIdx = BaseIdx;
5770 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5771 if (I0 == ExpectedVExtractIdx)
5772 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5773 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5774 // Try to match the following dag sequence:
5775 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5776 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5780 ExpectedVExtractIdx += 2;
5786 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5787 /// a concat_vector.
5789 /// This is a helper function of LowerToHorizontalOp().
5790 /// This function expects two 256-bit vectors called V0 and V1.
5791 /// At first, each vector is split into two separate 128-bit vectors.
5792 /// Then, the resulting 128-bit vectors are used to implement two
5793 /// horizontal binary operations.
5795 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5797 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5798 /// the two new horizontal binop.
5799 /// When Mode is set, the first horizontal binop dag node would take as input
5800 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5801 /// horizontal binop dag node would take as input the lower 128-bit of V1
5802 /// and the upper 128-bit of V1.
5804 /// HADD V0_LO, V0_HI
5805 /// HADD V1_LO, V1_HI
5807 /// Otherwise, the first horizontal binop dag node takes as input the lower
5808 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5809 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5811 /// HADD V0_LO, V1_LO
5812 /// HADD V0_HI, V1_HI
5814 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5815 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5816 /// the upper 128-bits of the result.
5817 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5818 SDLoc DL, SelectionDAG &DAG,
5819 unsigned X86Opcode, bool Mode,
5820 bool isUndefLO, bool isUndefHI) {
5821 EVT VT = V0.getValueType();
5822 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5823 "Invalid nodes in input!");
5825 unsigned NumElts = VT.getVectorNumElements();
5826 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5827 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5828 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5829 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5830 EVT NewVT = V0_LO.getValueType();
5832 SDValue LO = DAG.getUNDEF(NewVT);
5833 SDValue HI = DAG.getUNDEF(NewVT);
5836 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5837 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5838 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5839 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5840 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5842 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5843 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5844 V1_LO->getOpcode() != ISD::UNDEF))
5845 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5847 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5848 V1_HI->getOpcode() != ISD::UNDEF))
5849 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5852 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5855 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5857 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5858 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5859 EVT VT = BV->getValueType(0);
5860 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5861 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5865 unsigned NumElts = VT.getVectorNumElements();
5866 SDValue InVec0 = DAG.getUNDEF(VT);
5867 SDValue InVec1 = DAG.getUNDEF(VT);
5869 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5870 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5872 // Odd-numbered elements in the input build vector are obtained from
5873 // adding two integer/float elements.
5874 // Even-numbered elements in the input build vector are obtained from
5875 // subtracting two integer/float elements.
5876 unsigned ExpectedOpcode = ISD::FSUB;
5877 unsigned NextExpectedOpcode = ISD::FADD;
5878 bool AddFound = false;
5879 bool SubFound = false;
5881 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5882 SDValue Op = BV->getOperand(i);
5884 // Skip 'undef' values.
5885 unsigned Opcode = Op.getOpcode();
5886 if (Opcode == ISD::UNDEF) {
5887 std::swap(ExpectedOpcode, NextExpectedOpcode);
5891 // Early exit if we found an unexpected opcode.
5892 if (Opcode != ExpectedOpcode)
5895 SDValue Op0 = Op.getOperand(0);
5896 SDValue Op1 = Op.getOperand(1);
5898 // Try to match the following pattern:
5899 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5900 // Early exit if we cannot match that sequence.
5901 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5902 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5903 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5904 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5905 Op0.getOperand(1) != Op1.getOperand(1))
5908 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5912 // We found a valid add/sub node. Update the information accordingly.
5918 // Update InVec0 and InVec1.
5919 if (InVec0.getOpcode() == ISD::UNDEF) {
5920 InVec0 = Op0.getOperand(0);
5921 if (InVec0.getValueType() != VT)
5924 if (InVec1.getOpcode() == ISD::UNDEF) {
5925 InVec1 = Op1.getOperand(0);
5926 if (InVec1.getValueType() != VT)
5930 // Make sure that operands in input to each add/sub node always
5931 // come from a same pair of vectors.
5932 if (InVec0 != Op0.getOperand(0)) {
5933 if (ExpectedOpcode == ISD::FSUB)
5936 // FADD is commutable. Try to commute the operands
5937 // and then test again.
5938 std::swap(Op0, Op1);
5939 if (InVec0 != Op0.getOperand(0))
5943 if (InVec1 != Op1.getOperand(0))
5946 // Update the pair of expected opcodes.
5947 std::swap(ExpectedOpcode, NextExpectedOpcode);
5950 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5951 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5952 InVec1.getOpcode() != ISD::UNDEF)
5953 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5958 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5959 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5960 const X86Subtarget *Subtarget,
5961 SelectionDAG &DAG) {
5962 EVT VT = BV->getValueType(0);
5963 unsigned NumElts = VT.getVectorNumElements();
5964 unsigned NumUndefsLO = 0;
5965 unsigned NumUndefsHI = 0;
5966 unsigned Half = NumElts/2;
5968 // Count the number of UNDEF operands in the build_vector in input.
5969 for (unsigned i = 0, e = Half; i != e; ++i)
5970 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5973 for (unsigned i = Half, e = NumElts; i != e; ++i)
5974 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5977 // Early exit if this is either a build_vector of all UNDEFs or all the
5978 // operands but one are UNDEF.
5979 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5983 SDValue InVec0, InVec1;
5984 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5985 // Try to match an SSE3 float HADD/HSUB.
5986 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5987 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5989 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5990 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5991 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5992 // Try to match an SSSE3 integer HADD/HSUB.
5993 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5994 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5996 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5997 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6000 if (!Subtarget->hasAVX())
6003 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6004 // Try to match an AVX horizontal add/sub of packed single/double
6005 // precision floating point values from 256-bit vectors.
6006 SDValue InVec2, InVec3;
6007 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6008 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6009 ((InVec0.getOpcode() == ISD::UNDEF ||
6010 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6011 ((InVec1.getOpcode() == ISD::UNDEF ||
6012 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6013 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6015 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6016 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6017 ((InVec0.getOpcode() == ISD::UNDEF ||
6018 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6019 ((InVec1.getOpcode() == ISD::UNDEF ||
6020 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6021 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6022 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6023 // Try to match an AVX2 horizontal add/sub of signed integers.
6024 SDValue InVec2, InVec3;
6026 bool CanFold = true;
6028 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6029 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6030 ((InVec0.getOpcode() == ISD::UNDEF ||
6031 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6032 ((InVec1.getOpcode() == ISD::UNDEF ||
6033 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6034 X86Opcode = X86ISD::HADD;
6035 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6036 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6037 ((InVec0.getOpcode() == ISD::UNDEF ||
6038 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6039 ((InVec1.getOpcode() == ISD::UNDEF ||
6040 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6041 X86Opcode = X86ISD::HSUB;
6046 // Fold this build_vector into a single horizontal add/sub.
6047 // Do this only if the target has AVX2.
6048 if (Subtarget->hasAVX2())
6049 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6051 // Do not try to expand this build_vector into a pair of horizontal
6052 // add/sub if we can emit a pair of scalar add/sub.
6053 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6056 // Convert this build_vector into a pair of horizontal binop followed by
6058 bool isUndefLO = NumUndefsLO == Half;
6059 bool isUndefHI = NumUndefsHI == Half;
6060 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6061 isUndefLO, isUndefHI);
6065 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6066 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6068 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6069 X86Opcode = X86ISD::HADD;
6070 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6071 X86Opcode = X86ISD::HSUB;
6072 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6073 X86Opcode = X86ISD::FHADD;
6074 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6075 X86Opcode = X86ISD::FHSUB;
6079 // Don't try to expand this build_vector into a pair of horizontal add/sub
6080 // if we can simply emit a pair of scalar add/sub.
6081 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6084 // Convert this build_vector into two horizontal add/sub followed by
6086 bool isUndefLO = NumUndefsLO == Half;
6087 bool isUndefHI = NumUndefsHI == Half;
6088 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6089 isUndefLO, isUndefHI);
6096 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6099 MVT VT = Op.getSimpleValueType();
6100 MVT ExtVT = VT.getVectorElementType();
6101 unsigned NumElems = Op.getNumOperands();
6103 // Generate vectors for predicate vectors.
6104 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6105 return LowerBUILD_VECTORvXi1(Op, DAG);
6107 // Vectors containing all zeros can be matched by pxor and xorps later
6108 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6109 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6110 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6111 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6114 return getZeroVector(VT, Subtarget, DAG, dl);
6117 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6118 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6119 // vpcmpeqd on 256-bit vectors.
6120 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6121 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6124 if (!VT.is512BitVector())
6125 return getOnesVector(VT, Subtarget, DAG, dl);
6128 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6129 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6131 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6132 return HorizontalOp;
6133 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6136 unsigned EVTBits = ExtVT.getSizeInBits();
6138 unsigned NumZero = 0;
6139 unsigned NumNonZero = 0;
6140 unsigned NonZeros = 0;
6141 bool IsAllConstants = true;
6142 SmallSet<SDValue, 8> Values;
6143 for (unsigned i = 0; i < NumElems; ++i) {
6144 SDValue Elt = Op.getOperand(i);
6145 if (Elt.getOpcode() == ISD::UNDEF)
6148 if (Elt.getOpcode() != ISD::Constant &&
6149 Elt.getOpcode() != ISD::ConstantFP)
6150 IsAllConstants = false;
6151 if (X86::isZeroNode(Elt))
6154 NonZeros |= (1 << i);
6159 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6160 if (NumNonZero == 0)
6161 return DAG.getUNDEF(VT);
6163 // Special case for single non-zero, non-undef, element.
6164 if (NumNonZero == 1) {
6165 unsigned Idx = countTrailingZeros(NonZeros);
6166 SDValue Item = Op.getOperand(Idx);
6168 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6169 // the value are obviously zero, truncate the value to i32 and do the
6170 // insertion that way. Only do this if the value is non-constant or if the
6171 // value is a constant being inserted into element 0. It is cheaper to do
6172 // a constant pool load than it is to do a movd + shuffle.
6173 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6174 (!IsAllConstants || Idx == 0)) {
6175 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6177 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6178 EVT VecVT = MVT::v4i32;
6180 // Truncate the value (which may itself be a constant) to i32, and
6181 // convert it to a vector with movd (S2V+shuffle to zero extend).
6182 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6183 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6184 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6185 Item, Idx * 2, true, Subtarget, DAG));
6189 // If we have a constant or non-constant insertion into the low element of
6190 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6191 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6192 // depending on what the source datatype is.
6195 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6197 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6198 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6199 if (VT.is512BitVector()) {
6200 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6201 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6202 Item, DAG.getIntPtrConstant(0, dl));
6204 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6205 "Expected an SSE value type!");
6206 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6207 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6208 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6211 // We can't directly insert an i8 or i16 into a vector, so zero extend
6213 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6214 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6215 if (VT.is256BitVector()) {
6216 if (Subtarget->hasAVX()) {
6217 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6218 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6220 // Without AVX, we need to extend to a 128-bit vector and then
6221 // insert into the 256-bit vector.
6222 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6223 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6224 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6227 assert(VT.is128BitVector() && "Expected an SSE value type!");
6228 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6229 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6231 return DAG.getBitcast(VT, Item);
6235 // Is it a vector logical left shift?
6236 if (NumElems == 2 && Idx == 1 &&
6237 X86::isZeroNode(Op.getOperand(0)) &&
6238 !X86::isZeroNode(Op.getOperand(1))) {
6239 unsigned NumBits = VT.getSizeInBits();
6240 return getVShift(true, VT,
6241 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6242 VT, Op.getOperand(1)),
6243 NumBits/2, DAG, *this, dl);
6246 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6249 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6250 // is a non-constant being inserted into an element other than the low one,
6251 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6252 // movd/movss) to move this into the low element, then shuffle it into
6254 if (EVTBits == 32) {
6255 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6256 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6260 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6261 if (Values.size() == 1) {
6262 if (EVTBits == 32) {
6263 // Instead of a shuffle like this:
6264 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6265 // Check if it's possible to issue this instead.
6266 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6267 unsigned Idx = countTrailingZeros(NonZeros);
6268 SDValue Item = Op.getOperand(Idx);
6269 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6270 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6275 // A vector full of immediates; various special cases are already
6276 // handled, so this is best done with a single constant-pool load.
6280 // For AVX-length vectors, see if we can use a vector load to get all of the
6281 // elements, otherwise build the individual 128-bit pieces and use
6282 // shuffles to put them in place.
6283 if (VT.is256BitVector() || VT.is512BitVector()) {
6284 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6286 // Check for a build vector of consecutive loads.
6287 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6290 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6292 // Build both the lower and upper subvector.
6293 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6294 makeArrayRef(&V[0], NumElems/2));
6295 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6296 makeArrayRef(&V[NumElems / 2], NumElems/2));
6298 // Recreate the wider vector with the lower and upper part.
6299 if (VT.is256BitVector())
6300 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6301 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6304 // Let legalizer expand 2-wide build_vectors.
6305 if (EVTBits == 64) {
6306 if (NumNonZero == 1) {
6307 // One half is zero or undef.
6308 unsigned Idx = countTrailingZeros(NonZeros);
6309 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6310 Op.getOperand(Idx));
6311 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6316 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6317 if (EVTBits == 8 && NumElems == 16)
6318 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6322 if (EVTBits == 16 && NumElems == 8)
6323 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6327 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6328 if (EVTBits == 32 && NumElems == 4)
6329 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6332 // If element VT is == 32 bits, turn it into a number of shuffles.
6333 SmallVector<SDValue, 8> V(NumElems);
6334 if (NumElems == 4 && NumZero > 0) {
6335 for (unsigned i = 0; i < 4; ++i) {
6336 bool isZero = !(NonZeros & (1 << i));
6338 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6340 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6343 for (unsigned i = 0; i < 2; ++i) {
6344 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6347 V[i] = V[i*2]; // Must be a zero vector.
6350 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6353 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6356 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6361 bool Reverse1 = (NonZeros & 0x3) == 2;
6362 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6366 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6367 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6369 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6372 if (Values.size() > 1 && VT.is128BitVector()) {
6373 // Check for a build vector of consecutive loads.
6374 for (unsigned i = 0; i < NumElems; ++i)
6375 V[i] = Op.getOperand(i);
6377 // Check for elements which are consecutive loads.
6378 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6381 // Check for a build vector from mostly shuffle plus few inserting.
6382 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6385 // For SSE 4.1, use insertps to put the high elements into the low element.
6386 if (Subtarget->hasSSE41()) {
6388 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6389 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6391 Result = DAG.getUNDEF(VT);
6393 for (unsigned i = 1; i < NumElems; ++i) {
6394 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6395 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6396 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6401 // Otherwise, expand into a number of unpckl*, start by extending each of
6402 // our (non-undef) elements to the full vector width with the element in the
6403 // bottom slot of the vector (which generates no code for SSE).
6404 for (unsigned i = 0; i < NumElems; ++i) {
6405 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6406 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6408 V[i] = DAG.getUNDEF(VT);
6411 // Next, we iteratively mix elements, e.g. for v4f32:
6412 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6413 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6414 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6415 unsigned EltStride = NumElems >> 1;
6416 while (EltStride != 0) {
6417 for (unsigned i = 0; i < EltStride; ++i) {
6418 // If V[i+EltStride] is undef and this is the first round of mixing,
6419 // then it is safe to just drop this shuffle: V[i] is already in the
6420 // right place, the one element (since it's the first round) being
6421 // inserted as undef can be dropped. This isn't safe for successive
6422 // rounds because they will permute elements within both vectors.
6423 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6424 EltStride == NumElems/2)
6427 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6436 // 256-bit AVX can use the vinsertf128 instruction
6437 // to create 256-bit vectors from two other 128-bit ones.
6438 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6440 MVT ResVT = Op.getSimpleValueType();
6442 assert((ResVT.is256BitVector() ||
6443 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6445 SDValue V1 = Op.getOperand(0);
6446 SDValue V2 = Op.getOperand(1);
6447 unsigned NumElems = ResVT.getVectorNumElements();
6448 if (ResVT.is256BitVector())
6449 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6451 if (Op.getNumOperands() == 4) {
6452 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6453 ResVT.getVectorNumElements()/2);
6454 SDValue V3 = Op.getOperand(2);
6455 SDValue V4 = Op.getOperand(3);
6456 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6457 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6459 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6462 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6463 const X86Subtarget *Subtarget,
6464 SelectionDAG & DAG) {
6466 MVT ResVT = Op.getSimpleValueType();
6467 unsigned NumOfOperands = Op.getNumOperands();
6469 assert(isPowerOf2_32(NumOfOperands) &&
6470 "Unexpected number of operands in CONCAT_VECTORS");
6472 if (NumOfOperands > 2) {
6473 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6474 ResVT.getVectorNumElements()/2);
6475 SmallVector<SDValue, 2> Ops;
6476 for (unsigned i = 0; i < NumOfOperands/2; i++)
6477 Ops.push_back(Op.getOperand(i));
6478 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6480 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6481 Ops.push_back(Op.getOperand(i));
6482 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6483 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6486 SDValue V1 = Op.getOperand(0);
6487 SDValue V2 = Op.getOperand(1);
6488 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6489 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6491 if (IsZeroV1 && IsZeroV2)
6492 return getZeroVector(ResVT, Subtarget, DAG, dl);
6494 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6495 SDValue Undef = DAG.getUNDEF(ResVT);
6496 unsigned NumElems = ResVT.getVectorNumElements();
6497 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6499 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6500 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6504 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6505 // Zero the upper bits of V1
6506 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6507 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6510 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6513 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6514 const X86Subtarget *Subtarget,
6515 SelectionDAG &DAG) {
6516 MVT VT = Op.getSimpleValueType();
6517 if (VT.getVectorElementType() == MVT::i1)
6518 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6520 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6521 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6522 Op.getNumOperands() == 4)));
6524 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6525 // from two other 128-bit ones.
6527 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6528 return LowerAVXCONCAT_VECTORS(Op, DAG);
6531 //===----------------------------------------------------------------------===//
6532 // Vector shuffle lowering
6534 // This is an experimental code path for lowering vector shuffles on x86. It is
6535 // designed to handle arbitrary vector shuffles and blends, gracefully
6536 // degrading performance as necessary. It works hard to recognize idiomatic
6537 // shuffles and lower them to optimal instruction patterns without leaving
6538 // a framework that allows reasonably efficient handling of all vector shuffle
6540 //===----------------------------------------------------------------------===//
6542 /// \brief Tiny helper function to identify a no-op mask.
6544 /// This is a somewhat boring predicate function. It checks whether the mask
6545 /// array input, which is assumed to be a single-input shuffle mask of the kind
6546 /// used by the X86 shuffle instructions (not a fully general
6547 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6548 /// in-place shuffle are 'no-op's.
6549 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6550 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6551 if (Mask[i] != -1 && Mask[i] != i)
6556 /// \brief Helper function to classify a mask as a single-input mask.
6558 /// This isn't a generic single-input test because in the vector shuffle
6559 /// lowering we canonicalize single inputs to be the first input operand. This
6560 /// means we can more quickly test for a single input by only checking whether
6561 /// an input from the second operand exists. We also assume that the size of
6562 /// mask corresponds to the size of the input vectors which isn't true in the
6563 /// fully general case.
6564 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6566 if (M >= (int)Mask.size())
6571 /// \brief Test whether there are elements crossing 128-bit lanes in this
6574 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6575 /// and we routinely test for these.
6576 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6577 int LaneSize = 128 / VT.getScalarSizeInBits();
6578 int Size = Mask.size();
6579 for (int i = 0; i < Size; ++i)
6580 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6585 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6587 /// This checks a shuffle mask to see if it is performing the same
6588 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6589 /// that it is also not lane-crossing. It may however involve a blend from the
6590 /// same lane of a second vector.
6592 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6593 /// non-trivial to compute in the face of undef lanes. The representation is
6594 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6595 /// entries from both V1 and V2 inputs to the wider mask.
6597 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6598 SmallVectorImpl<int> &RepeatedMask) {
6599 int LaneSize = 128 / VT.getScalarSizeInBits();
6600 RepeatedMask.resize(LaneSize, -1);
6601 int Size = Mask.size();
6602 for (int i = 0; i < Size; ++i) {
6605 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6606 // This entry crosses lanes, so there is no way to model this shuffle.
6609 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6610 if (RepeatedMask[i % LaneSize] == -1)
6611 // This is the first non-undef entry in this slot of a 128-bit lane.
6612 RepeatedMask[i % LaneSize] =
6613 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6614 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6615 // Found a mismatch with the repeated mask.
6621 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6624 /// This is a fast way to test a shuffle mask against a fixed pattern:
6626 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6628 /// It returns true if the mask is exactly as wide as the argument list, and
6629 /// each element of the mask is either -1 (signifying undef) or the value given
6630 /// in the argument.
6631 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6632 ArrayRef<int> ExpectedMask) {
6633 if (Mask.size() != ExpectedMask.size())
6636 int Size = Mask.size();
6638 // If the values are build vectors, we can look through them to find
6639 // equivalent inputs that make the shuffles equivalent.
6640 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6641 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6643 for (int i = 0; i < Size; ++i)
6644 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6645 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6646 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6647 if (!MaskBV || !ExpectedBV ||
6648 MaskBV->getOperand(Mask[i] % Size) !=
6649 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6656 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6658 /// This helper function produces an 8-bit shuffle immediate corresponding to
6659 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6660 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6663 /// NB: We rely heavily on "undef" masks preserving the input lane.
6664 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6665 SelectionDAG &DAG) {
6666 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6667 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6668 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6669 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6670 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6673 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6674 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6675 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6676 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6677 return DAG.getConstant(Imm, DL, MVT::i8);
6680 /// \brief Compute whether each element of a shuffle is zeroable.
6682 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6683 /// Either it is an undef element in the shuffle mask, the element of the input
6684 /// referenced is undef, or the element of the input referenced is known to be
6685 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6686 /// as many lanes with this technique as possible to simplify the remaining
6688 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6689 SDValue V1, SDValue V2) {
6690 SmallBitVector Zeroable(Mask.size(), false);
6692 while (V1.getOpcode() == ISD::BITCAST)
6693 V1 = V1->getOperand(0);
6694 while (V2.getOpcode() == ISD::BITCAST)
6695 V2 = V2->getOperand(0);
6697 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6698 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6700 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6702 // Handle the easy cases.
6703 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6708 // If this is an index into a build_vector node (which has the same number
6709 // of elements), dig out the input value and use it.
6710 SDValue V = M < Size ? V1 : V2;
6711 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6714 SDValue Input = V.getOperand(M % Size);
6715 // The UNDEF opcode check really should be dead code here, but not quite
6716 // worth asserting on (it isn't invalid, just unexpected).
6717 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6724 // X86 has dedicated unpack instructions that can handle specific blend
6725 // operations: UNPCKH and UNPCKL.
6726 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6727 SDValue V1, SDValue V2,
6728 SelectionDAG &DAG) {
6729 int NumElts = VT.getVectorNumElements();
6732 bool UnpcklSwapped = true;
6733 bool UnpckhSwapped = true;
6734 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6736 for (int i = 0; i < NumElts; ++i) {
6737 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6739 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6740 int HiPos = LoPos + NumEltsInLane / 2;
6741 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6742 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6746 if (Mask[i] != LoPos)
6748 if (Mask[i] != HiPos)
6750 if (Mask[i] != LoPosSwapped)
6751 UnpcklSwapped = false;
6752 if (Mask[i] != HiPosSwapped)
6753 UnpckhSwapped = false;
6754 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6758 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6760 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6762 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6764 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6766 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6770 /// \brief Try to emit a bitmask instruction for a shuffle.
6772 /// This handles cases where we can model a blend exactly as a bitmask due to
6773 /// one of the inputs being zeroable.
6774 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6775 SDValue V2, ArrayRef<int> Mask,
6776 SelectionDAG &DAG) {
6777 MVT EltVT = VT.getScalarType();
6778 int NumEltBits = EltVT.getSizeInBits();
6779 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6780 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6781 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6783 if (EltVT.isFloatingPoint()) {
6784 Zero = DAG.getBitcast(EltVT, Zero);
6785 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6787 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6788 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6790 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6793 if (Mask[i] % Size != i)
6794 return SDValue(); // Not a blend.
6796 V = Mask[i] < Size ? V1 : V2;
6797 else if (V != (Mask[i] < Size ? V1 : V2))
6798 return SDValue(); // Can only let one input through the mask.
6800 VMaskOps[i] = AllOnes;
6803 return SDValue(); // No non-zeroable elements!
6805 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6806 V = DAG.getNode(VT.isFloatingPoint()
6807 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6812 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6814 /// This is used as a fallback approach when first class blend instructions are
6815 /// unavailable. Currently it is only suitable for integer vectors, but could
6816 /// be generalized for floating point vectors if desirable.
6817 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6818 SDValue V2, ArrayRef<int> Mask,
6819 SelectionDAG &DAG) {
6820 assert(VT.isInteger() && "Only supports integer vector types!");
6821 MVT EltVT = VT.getScalarType();
6822 int NumEltBits = EltVT.getSizeInBits();
6823 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6824 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6826 SmallVector<SDValue, 16> MaskOps;
6827 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6828 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6829 return SDValue(); // Shuffled input!
6830 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6833 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6834 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6835 // We have to cast V2 around.
6836 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6837 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6838 DAG.getBitcast(MaskVT, V1Mask),
6839 DAG.getBitcast(MaskVT, V2)));
6840 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6843 /// \brief Try to emit a blend instruction for a shuffle.
6845 /// This doesn't do any checks for the availability of instructions for blending
6846 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6847 /// be matched in the backend with the type given. What it does check for is
6848 /// that the shuffle mask is in fact a blend.
6849 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6850 SDValue V2, ArrayRef<int> Mask,
6851 const X86Subtarget *Subtarget,
6852 SelectionDAG &DAG) {
6853 unsigned BlendMask = 0;
6854 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6855 if (Mask[i] >= Size) {
6856 if (Mask[i] != i + Size)
6857 return SDValue(); // Shuffled V2 input!
6858 BlendMask |= 1u << i;
6861 if (Mask[i] >= 0 && Mask[i] != i)
6862 return SDValue(); // Shuffled V1 input!
6864 switch (VT.SimpleTy) {
6869 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6870 DAG.getConstant(BlendMask, DL, MVT::i8));
6874 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6878 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6879 // that instruction.
6880 if (Subtarget->hasAVX2()) {
6881 // Scale the blend by the number of 32-bit dwords per element.
6882 int Scale = VT.getScalarSizeInBits() / 32;
6884 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6885 if (Mask[i] >= Size)
6886 for (int j = 0; j < Scale; ++j)
6887 BlendMask |= 1u << (i * Scale + j);
6889 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6890 V1 = DAG.getBitcast(BlendVT, V1);
6891 V2 = DAG.getBitcast(BlendVT, V2);
6892 return DAG.getBitcast(
6893 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6894 DAG.getConstant(BlendMask, DL, MVT::i8)));
6898 // For integer shuffles we need to expand the mask and cast the inputs to
6899 // v8i16s prior to blending.
6900 int Scale = 8 / VT.getVectorNumElements();
6902 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6903 if (Mask[i] >= Size)
6904 for (int j = 0; j < Scale; ++j)
6905 BlendMask |= 1u << (i * Scale + j);
6907 V1 = DAG.getBitcast(MVT::v8i16, V1);
6908 V2 = DAG.getBitcast(MVT::v8i16, V2);
6909 return DAG.getBitcast(VT,
6910 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6911 DAG.getConstant(BlendMask, DL, MVT::i8)));
6915 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6916 SmallVector<int, 8> RepeatedMask;
6917 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6918 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6919 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6921 for (int i = 0; i < 8; ++i)
6922 if (RepeatedMask[i] >= 16)
6923 BlendMask |= 1u << i;
6924 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6925 DAG.getConstant(BlendMask, DL, MVT::i8));
6931 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6932 "256-bit byte-blends require AVX2 support!");
6934 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6935 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6938 // Scale the blend by the number of bytes per element.
6939 int Scale = VT.getScalarSizeInBits() / 8;
6941 // This form of blend is always done on bytes. Compute the byte vector
6943 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6945 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6946 // mix of LLVM's code generator and the x86 backend. We tell the code
6947 // generator that boolean values in the elements of an x86 vector register
6948 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6949 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6950 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6951 // of the element (the remaining are ignored) and 0 in that high bit would
6952 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6953 // the LLVM model for boolean values in vector elements gets the relevant
6954 // bit set, it is set backwards and over constrained relative to x86's
6956 SmallVector<SDValue, 32> VSELECTMask;
6957 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6958 for (int j = 0; j < Scale; ++j)
6959 VSELECTMask.push_back(
6960 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6961 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6964 V1 = DAG.getBitcast(BlendVT, V1);
6965 V2 = DAG.getBitcast(BlendVT, V2);
6966 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6967 DAG.getNode(ISD::BUILD_VECTOR, DL,
6968 BlendVT, VSELECTMask),
6973 llvm_unreachable("Not a supported integer vector type!");
6977 /// \brief Try to lower as a blend of elements from two inputs followed by
6978 /// a single-input permutation.
6980 /// This matches the pattern where we can blend elements from two inputs and
6981 /// then reduce the shuffle to a single-input permutation.
6982 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6985 SelectionDAG &DAG) {
6986 // We build up the blend mask while checking whether a blend is a viable way
6987 // to reduce the shuffle.
6988 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6989 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6991 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6995 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6997 if (BlendMask[Mask[i] % Size] == -1)
6998 BlendMask[Mask[i] % Size] = Mask[i];
6999 else if (BlendMask[Mask[i] % Size] != Mask[i])
7000 return SDValue(); // Can't blend in the needed input!
7002 PermuteMask[i] = Mask[i] % Size;
7005 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7006 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7009 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7010 /// blends and permutes.
7012 /// This matches the extremely common pattern for handling combined
7013 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7014 /// operations. It will try to pick the best arrangement of shuffles and
7016 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7020 SelectionDAG &DAG) {
7021 // Shuffle the input elements into the desired positions in V1 and V2 and
7022 // blend them together.
7023 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7024 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7025 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7026 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7027 if (Mask[i] >= 0 && Mask[i] < Size) {
7028 V1Mask[i] = Mask[i];
7030 } else if (Mask[i] >= Size) {
7031 V2Mask[i] = Mask[i] - Size;
7032 BlendMask[i] = i + Size;
7035 // Try to lower with the simpler initial blend strategy unless one of the
7036 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7037 // shuffle may be able to fold with a load or other benefit. However, when
7038 // we'll have to do 2x as many shuffles in order to achieve this, blending
7039 // first is a better strategy.
7040 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7041 if (SDValue BlendPerm =
7042 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7045 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7046 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7047 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7050 /// \brief Try to lower a vector shuffle as a byte rotation.
7052 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7053 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7054 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7055 /// try to generically lower a vector shuffle through such an pattern. It
7056 /// does not check for the profitability of lowering either as PALIGNR or
7057 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7058 /// This matches shuffle vectors that look like:
7060 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7062 /// Essentially it concatenates V1 and V2, shifts right by some number of
7063 /// elements, and takes the low elements as the result. Note that while this is
7064 /// specified as a *right shift* because x86 is little-endian, it is a *left
7065 /// rotate* of the vector lanes.
7066 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7069 const X86Subtarget *Subtarget,
7070 SelectionDAG &DAG) {
7071 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7073 int NumElts = Mask.size();
7074 int NumLanes = VT.getSizeInBits() / 128;
7075 int NumLaneElts = NumElts / NumLanes;
7077 // We need to detect various ways of spelling a rotation:
7078 // [11, 12, 13, 14, 15, 0, 1, 2]
7079 // [-1, 12, 13, 14, -1, -1, 1, -1]
7080 // [-1, -1, -1, -1, -1, -1, 1, 2]
7081 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7082 // [-1, 4, 5, 6, -1, -1, 9, -1]
7083 // [-1, 4, 5, 6, -1, -1, -1, -1]
7086 for (int l = 0; l < NumElts; l += NumLaneElts) {
7087 for (int i = 0; i < NumLaneElts; ++i) {
7088 if (Mask[l + i] == -1)
7090 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7092 // Get the mod-Size index and lane correct it.
7093 int LaneIdx = (Mask[l + i] % NumElts) - l;
7094 // Make sure it was in this lane.
7095 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7098 // Determine where a rotated vector would have started.
7099 int StartIdx = i - LaneIdx;
7101 // The identity rotation isn't interesting, stop.
7104 // If we found the tail of a vector the rotation must be the missing
7105 // front. If we found the head of a vector, it must be how much of the
7107 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7110 Rotation = CandidateRotation;
7111 else if (Rotation != CandidateRotation)
7112 // The rotations don't match, so we can't match this mask.
7115 // Compute which value this mask is pointing at.
7116 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7118 // Compute which of the two target values this index should be assigned
7119 // to. This reflects whether the high elements are remaining or the low
7120 // elements are remaining.
7121 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7123 // Either set up this value if we've not encountered it before, or check
7124 // that it remains consistent.
7127 else if (TargetV != MaskV)
7128 // This may be a rotation, but it pulls from the inputs in some
7129 // unsupported interleaving.
7134 // Check that we successfully analyzed the mask, and normalize the results.
7135 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7136 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7142 // The actual rotate instruction rotates bytes, so we need to scale the
7143 // rotation based on how many bytes are in the vector lane.
7144 int Scale = 16 / NumLaneElts;
7146 // SSSE3 targets can use the palignr instruction.
7147 if (Subtarget->hasSSSE3()) {
7148 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7149 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7150 Lo = DAG.getBitcast(AlignVT, Lo);
7151 Hi = DAG.getBitcast(AlignVT, Hi);
7153 return DAG.getBitcast(
7154 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7155 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7158 assert(VT.getSizeInBits() == 128 &&
7159 "Rotate-based lowering only supports 128-bit lowering!");
7160 assert(Mask.size() <= 16 &&
7161 "Can shuffle at most 16 bytes in a 128-bit vector!");
7163 // Default SSE2 implementation
7164 int LoByteShift = 16 - Rotation * Scale;
7165 int HiByteShift = Rotation * Scale;
7167 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7168 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7169 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7171 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7172 DAG.getConstant(LoByteShift, DL, MVT::i8));
7173 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7174 DAG.getConstant(HiByteShift, DL, MVT::i8));
7175 return DAG.getBitcast(VT,
7176 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7179 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7181 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7182 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7183 /// matches elements from one of the input vectors shuffled to the left or
7184 /// right with zeroable elements 'shifted in'. It handles both the strictly
7185 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7188 /// PSHL : (little-endian) left bit shift.
7189 /// [ zz, 0, zz, 2 ]
7190 /// [ -1, 4, zz, -1 ]
7191 /// PSRL : (little-endian) right bit shift.
7193 /// [ -1, -1, 7, zz]
7194 /// PSLLDQ : (little-endian) left byte shift
7195 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7196 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7197 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7198 /// PSRLDQ : (little-endian) right byte shift
7199 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7200 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7201 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7202 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7203 SDValue V2, ArrayRef<int> Mask,
7204 SelectionDAG &DAG) {
7205 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7207 int Size = Mask.size();
7208 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7210 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7211 for (int i = 0; i < Size; i += Scale)
7212 for (int j = 0; j < Shift; ++j)
7213 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7219 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7220 for (int i = 0; i != Size; i += Scale) {
7221 unsigned Pos = Left ? i + Shift : i;
7222 unsigned Low = Left ? i : i + Shift;
7223 unsigned Len = Scale - Shift;
7224 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7225 Low + (V == V1 ? 0 : Size)))
7229 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7230 bool ByteShift = ShiftEltBits > 64;
7231 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7232 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7233 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7235 // Normalize the scale for byte shifts to still produce an i64 element
7237 Scale = ByteShift ? Scale / 2 : Scale;
7239 // We need to round trip through the appropriate type for the shift.
7240 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7241 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7242 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7243 "Illegal integer vector type");
7244 V = DAG.getBitcast(ShiftVT, V);
7246 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7247 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7248 return DAG.getBitcast(VT, V);
7251 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7252 // keep doubling the size of the integer elements up to that. We can
7253 // then shift the elements of the integer vector by whole multiples of
7254 // their width within the elements of the larger integer vector. Test each
7255 // multiple to see if we can find a match with the moved element indices
7256 // and that the shifted in elements are all zeroable.
7257 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7258 for (int Shift = 1; Shift != Scale; ++Shift)
7259 for (bool Left : {true, false})
7260 if (CheckZeros(Shift, Scale, Left))
7261 for (SDValue V : {V1, V2})
7262 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7269 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7270 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7271 SDValue V2, ArrayRef<int> Mask,
7272 SelectionDAG &DAG) {
7273 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7274 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7276 int Size = Mask.size();
7277 int HalfSize = Size / 2;
7278 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7280 // Upper half must be undefined.
7281 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7284 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7285 // Remainder of lower half result is zero and upper half is all undef.
7286 auto LowerAsEXTRQ = [&]() {
7287 // Determine the extraction length from the part of the
7288 // lower half that isn't zeroable.
7290 for (; Len >= 0; --Len)
7291 if (!Zeroable[Len - 1])
7293 assert(Len > 0 && "Zeroable shuffle mask");
7295 // Attempt to match first Len sequential elements from the lower half.
7298 for (int i = 0; i != Len; ++i) {
7302 SDValue &V = (M < Size ? V1 : V2);
7305 // All mask elements must be in the lower half.
7309 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7320 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7321 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7322 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7323 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7324 DAG.getConstant(BitLen, DL, MVT::i8),
7325 DAG.getConstant(BitIdx, DL, MVT::i8));
7328 if (SDValue ExtrQ = LowerAsEXTRQ())
7331 // INSERTQ: Extract lowest Len elements from lower half of second source and
7332 // insert over first source, starting at Idx.
7333 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7334 auto LowerAsInsertQ = [&]() {
7335 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7338 // Attempt to match first source from mask before insertion point.
7339 if (isUndefInRange(Mask, 0, Idx)) {
7341 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7343 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7349 // Extend the extraction length looking to match both the insertion of
7350 // the second source and the remaining elements of the first.
7351 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7356 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7358 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7364 // Match the remaining elements of the lower half.
7365 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7367 } else if ((!Base || (Base == V1)) &&
7368 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7370 } else if ((!Base || (Base == V2)) &&
7371 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7378 // We may not have a base (first source) - this can safely be undefined.
7380 Base = DAG.getUNDEF(VT);
7382 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7383 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7384 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7385 DAG.getConstant(BitLen, DL, MVT::i8),
7386 DAG.getConstant(BitIdx, DL, MVT::i8));
7393 if (SDValue InsertQ = LowerAsInsertQ())
7399 /// \brief Lower a vector shuffle as a zero or any extension.
7401 /// Given a specific number of elements, element bit width, and extension
7402 /// stride, produce either a zero or any extension based on the available
7403 /// features of the subtarget. The extended elements are consecutive and
7404 /// begin and can start from an offseted element index in the input; to
7405 /// avoid excess shuffling the offset must either being in the bottom lane
7406 /// or at the start of a higher lane. All extended elements must be from
7408 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7409 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7410 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7411 assert(Scale > 1 && "Need a scale to extend.");
7412 int EltBits = VT.getScalarSizeInBits();
7413 int NumElements = VT.getVectorNumElements();
7414 int NumEltsPerLane = 128 / EltBits;
7415 int OffsetLane = Offset / NumEltsPerLane;
7416 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7417 "Only 8, 16, and 32 bit elements can be extended.");
7418 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7419 assert(0 <= Offset && "Extension offset must be positive.");
7420 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7421 "Extension offset must be in the first lane or start an upper lane.");
7423 // Check that an index is in same lane as the base offset.
7424 auto SafeOffset = [&](int Idx) {
7425 return OffsetLane == (Idx / NumEltsPerLane);
7428 // Shift along an input so that the offset base moves to the first element.
7429 auto ShuffleOffset = [&](SDValue V) {
7433 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7434 for (int i = 0; i * Scale < NumElements; ++i) {
7435 int SrcIdx = i + Offset;
7436 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7438 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7441 // Found a valid zext mask! Try various lowering strategies based on the
7442 // input type and available ISA extensions.
7443 if (Subtarget->hasSSE41()) {
7444 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7445 // PUNPCK will catch this in a later shuffle match.
7446 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7448 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7449 NumElements / Scale);
7450 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7451 return DAG.getBitcast(VT, InputV);
7454 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7456 // For any extends we can cheat for larger element sizes and use shuffle
7457 // instructions that can fold with a load and/or copy.
7458 if (AnyExt && EltBits == 32) {
7459 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7461 return DAG.getBitcast(
7462 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7463 DAG.getBitcast(MVT::v4i32, InputV),
7464 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7466 if (AnyExt && EltBits == 16 && Scale > 2) {
7467 int PSHUFDMask[4] = {Offset / 2, -1,
7468 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7469 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7470 DAG.getBitcast(MVT::v4i32, InputV),
7471 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7472 int PSHUFWMask[4] = {1, -1, -1, -1};
7473 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7474 return DAG.getBitcast(
7475 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7476 DAG.getBitcast(MVT::v8i16, InputV),
7477 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7480 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7482 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7483 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7484 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7486 int LoIdx = Offset * EltBits;
7487 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7488 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7489 DAG.getConstant(EltBits, DL, MVT::i8),
7490 DAG.getConstant(LoIdx, DL, MVT::i8)));
7492 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7493 !SafeOffset(Offset + 1))
7494 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7496 int HiIdx = (Offset + 1) * EltBits;
7497 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7498 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7499 DAG.getConstant(EltBits, DL, MVT::i8),
7500 DAG.getConstant(HiIdx, DL, MVT::i8)));
7501 return DAG.getNode(ISD::BITCAST, DL, VT,
7502 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7505 // If this would require more than 2 unpack instructions to expand, use
7506 // pshufb when available. We can only use more than 2 unpack instructions
7507 // when zero extending i8 elements which also makes it easier to use pshufb.
7508 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7509 assert(NumElements == 16 && "Unexpected byte vector width!");
7510 SDValue PSHUFBMask[16];
7511 for (int i = 0; i < 16; ++i) {
7512 int Idx = Offset + (i / Scale);
7513 PSHUFBMask[i] = DAG.getConstant(
7514 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7516 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7517 return DAG.getBitcast(VT,
7518 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7519 DAG.getNode(ISD::BUILD_VECTOR, DL,
7520 MVT::v16i8, PSHUFBMask)));
7523 // If we are extending from an offset, ensure we start on a boundary that
7524 // we can unpack from.
7525 int AlignToUnpack = Offset % (NumElements / Scale);
7526 if (AlignToUnpack) {
7527 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7528 for (int i = AlignToUnpack; i < NumElements; ++i)
7529 ShMask[i - AlignToUnpack] = i;
7530 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7531 Offset -= AlignToUnpack;
7534 // Otherwise emit a sequence of unpacks.
7536 unsigned UnpackLoHi = X86ISD::UNPCKL;
7537 if (Offset >= (NumElements / 2)) {
7538 UnpackLoHi = X86ISD::UNPCKH;
7539 Offset -= (NumElements / 2);
7542 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7543 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7544 : getZeroVector(InputVT, Subtarget, DAG, DL);
7545 InputV = DAG.getBitcast(InputVT, InputV);
7546 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7550 } while (Scale > 1);
7551 return DAG.getBitcast(VT, InputV);
7554 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7556 /// This routine will try to do everything in its power to cleverly lower
7557 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7558 /// check for the profitability of this lowering, it tries to aggressively
7559 /// match this pattern. It will use all of the micro-architectural details it
7560 /// can to emit an efficient lowering. It handles both blends with all-zero
7561 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7562 /// masking out later).
7564 /// The reason we have dedicated lowering for zext-style shuffles is that they
7565 /// are both incredibly common and often quite performance sensitive.
7566 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7567 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7568 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7569 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7571 int Bits = VT.getSizeInBits();
7572 int NumLanes = Bits / 128;
7573 int NumElements = VT.getVectorNumElements();
7574 int NumEltsPerLane = NumElements / NumLanes;
7575 assert(VT.getScalarSizeInBits() <= 32 &&
7576 "Exceeds 32-bit integer zero extension limit");
7577 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7579 // Define a helper function to check a particular ext-scale and lower to it if
7581 auto Lower = [&](int Scale) -> SDValue {
7586 for (int i = 0; i < NumElements; ++i) {
7589 continue; // Valid anywhere but doesn't tell us anything.
7590 if (i % Scale != 0) {
7591 // Each of the extended elements need to be zeroable.
7595 // We no longer are in the anyext case.
7600 // Each of the base elements needs to be consecutive indices into the
7601 // same input vector.
7602 SDValue V = M < NumElements ? V1 : V2;
7603 M = M % NumElements;
7606 Offset = M - (i / Scale);
7607 } else if (InputV != V)
7608 return SDValue(); // Flip-flopping inputs.
7610 // Offset must start in the lowest 128-bit lane or at the start of an
7612 // FIXME: Is it ever worth allowing a negative base offset?
7613 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7614 (Offset % NumEltsPerLane) == 0))
7617 // If we are offsetting, all referenced entries must come from the same
7619 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7622 if ((M % NumElements) != (Offset + (i / Scale)))
7623 return SDValue(); // Non-consecutive strided elements.
7627 // If we fail to find an input, we have a zero-shuffle which should always
7628 // have already been handled.
7629 // FIXME: Maybe handle this here in case during blending we end up with one?
7633 // If we are offsetting, don't extend if we only match a single input, we
7634 // can always do better by using a basic PSHUF or PUNPCK.
7635 if (Offset != 0 && Matches < 2)
7638 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7639 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7642 // The widest scale possible for extending is to a 64-bit integer.
7643 assert(Bits % 64 == 0 &&
7644 "The number of bits in a vector must be divisible by 64 on x86!");
7645 int NumExtElements = Bits / 64;
7647 // Each iteration, try extending the elements half as much, but into twice as
7649 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7650 assert(NumElements % NumExtElements == 0 &&
7651 "The input vector size must be divisible by the extended size.");
7652 if (SDValue V = Lower(NumElements / NumExtElements))
7656 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7660 // Returns one of the source operands if the shuffle can be reduced to a
7661 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7662 auto CanZExtLowHalf = [&]() {
7663 for (int i = NumElements / 2; i != NumElements; ++i)
7666 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7668 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7673 if (SDValue V = CanZExtLowHalf()) {
7674 V = DAG.getBitcast(MVT::v2i64, V);
7675 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7676 return DAG.getBitcast(VT, V);
7679 // No viable ext lowering found.
7683 /// \brief Try to get a scalar value for a specific element of a vector.
7685 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7686 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7687 SelectionDAG &DAG) {
7688 MVT VT = V.getSimpleValueType();
7689 MVT EltVT = VT.getVectorElementType();
7690 while (V.getOpcode() == ISD::BITCAST)
7691 V = V.getOperand(0);
7692 // If the bitcasts shift the element size, we can't extract an equivalent
7694 MVT NewVT = V.getSimpleValueType();
7695 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7698 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7699 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7700 // Ensure the scalar operand is the same size as the destination.
7701 // FIXME: Add support for scalar truncation where possible.
7702 SDValue S = V.getOperand(Idx);
7703 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7704 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7710 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7712 /// This is particularly important because the set of instructions varies
7713 /// significantly based on whether the operand is a load or not.
7714 static bool isShuffleFoldableLoad(SDValue V) {
7715 while (V.getOpcode() == ISD::BITCAST)
7716 V = V.getOperand(0);
7718 return ISD::isNON_EXTLoad(V.getNode());
7721 /// \brief Try to lower insertion of a single element into a zero vector.
7723 /// This is a common pattern that we have especially efficient patterns to lower
7724 /// across all subtarget feature sets.
7725 static SDValue lowerVectorShuffleAsElementInsertion(
7726 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7727 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7728 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7730 MVT EltVT = VT.getVectorElementType();
7732 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7733 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7735 bool IsV1Zeroable = true;
7736 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7737 if (i != V2Index && !Zeroable[i]) {
7738 IsV1Zeroable = false;
7742 // Check for a single input from a SCALAR_TO_VECTOR node.
7743 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7744 // all the smarts here sunk into that routine. However, the current
7745 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7746 // vector shuffle lowering is dead.
7747 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7749 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7750 // We need to zext the scalar if it is smaller than an i32.
7751 V2S = DAG.getBitcast(EltVT, V2S);
7752 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7753 // Using zext to expand a narrow element won't work for non-zero
7758 // Zero-extend directly to i32.
7760 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7762 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7763 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7764 EltVT == MVT::i16) {
7765 // Either not inserting from the low element of the input or the input
7766 // element size is too small to use VZEXT_MOVL to clear the high bits.
7770 if (!IsV1Zeroable) {
7771 // If V1 can't be treated as a zero vector we have fewer options to lower
7772 // this. We can't support integer vectors or non-zero targets cheaply, and
7773 // the V1 elements can't be permuted in any way.
7774 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7775 if (!VT.isFloatingPoint() || V2Index != 0)
7777 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7778 V1Mask[V2Index] = -1;
7779 if (!isNoopShuffleMask(V1Mask))
7781 // This is essentially a special case blend operation, but if we have
7782 // general purpose blend operations, they are always faster. Bail and let
7783 // the rest of the lowering handle these as blends.
7784 if (Subtarget->hasSSE41())
7787 // Otherwise, use MOVSD or MOVSS.
7788 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7789 "Only two types of floating point element types to handle!");
7790 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7794 // This lowering only works for the low element with floating point vectors.
7795 if (VT.isFloatingPoint() && V2Index != 0)
7798 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7800 V2 = DAG.getBitcast(VT, V2);
7803 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7804 // the desired position. Otherwise it is more efficient to do a vector
7805 // shift left. We know that we can do a vector shift left because all
7806 // the inputs are zero.
7807 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7808 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7809 V2Shuffle[V2Index] = 0;
7810 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7812 V2 = DAG.getBitcast(MVT::v2i64, V2);
7814 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7815 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7816 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7817 DAG.getDataLayout(), VT)));
7818 V2 = DAG.getBitcast(VT, V2);
7824 /// \brief Try to lower broadcast of a single element.
7826 /// For convenience, this code also bundles all of the subtarget feature set
7827 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7828 /// a convenient way to factor it out.
7829 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7831 const X86Subtarget *Subtarget,
7832 SelectionDAG &DAG) {
7833 if (!Subtarget->hasAVX())
7835 if (VT.isInteger() && !Subtarget->hasAVX2())
7838 // Check that the mask is a broadcast.
7839 int BroadcastIdx = -1;
7841 if (M >= 0 && BroadcastIdx == -1)
7843 else if (M >= 0 && M != BroadcastIdx)
7846 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7847 "a sorted mask where the broadcast "
7850 // Go up the chain of (vector) values to find a scalar load that we can
7851 // combine with the broadcast.
7853 switch (V.getOpcode()) {
7854 case ISD::CONCAT_VECTORS: {
7855 int OperandSize = Mask.size() / V.getNumOperands();
7856 V = V.getOperand(BroadcastIdx / OperandSize);
7857 BroadcastIdx %= OperandSize;
7861 case ISD::INSERT_SUBVECTOR: {
7862 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7863 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7867 int BeginIdx = (int)ConstantIdx->getZExtValue();
7869 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7870 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7871 BroadcastIdx -= BeginIdx;
7882 // Check if this is a broadcast of a scalar. We special case lowering
7883 // for scalars so that we can more effectively fold with loads.
7884 // First, look through bitcast: if the original value has a larger element
7885 // type than the shuffle, the broadcast element is in essence truncated.
7886 // Make that explicit to ease folding.
7887 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7888 EVT EltVT = VT.getVectorElementType();
7889 SDValue V0 = V.getOperand(0);
7890 EVT V0VT = V0.getValueType();
7892 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7893 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7894 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7895 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7900 // Also check the simpler case, where we can directly reuse the scalar.
7901 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7902 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7903 V = V.getOperand(BroadcastIdx);
7905 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7906 // Only AVX2 has register broadcasts.
7907 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7909 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7910 // We can't broadcast from a vector register without AVX2, and we can only
7911 // broadcast from the zero-element of a vector register.
7915 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7918 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7919 // INSERTPS when the V1 elements are already in the correct locations
7920 // because otherwise we can just always use two SHUFPS instructions which
7921 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7922 // perform INSERTPS if a single V1 element is out of place and all V2
7923 // elements are zeroable.
7924 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7926 SelectionDAG &DAG) {
7927 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7928 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7929 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7930 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7932 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7935 int V1DstIndex = -1;
7936 int V2DstIndex = -1;
7937 bool V1UsedInPlace = false;
7939 for (int i = 0; i < 4; ++i) {
7940 // Synthesize a zero mask from the zeroable elements (includes undefs).
7946 // Flag if we use any V1 inputs in place.
7948 V1UsedInPlace = true;
7952 // We can only insert a single non-zeroable element.
7953 if (V1DstIndex != -1 || V2DstIndex != -1)
7957 // V1 input out of place for insertion.
7960 // V2 input for insertion.
7965 // Don't bother if we have no (non-zeroable) element for insertion.
7966 if (V1DstIndex == -1 && V2DstIndex == -1)
7969 // Determine element insertion src/dst indices. The src index is from the
7970 // start of the inserted vector, not the start of the concatenated vector.
7971 unsigned V2SrcIndex = 0;
7972 if (V1DstIndex != -1) {
7973 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7974 // and don't use the original V2 at all.
7975 V2SrcIndex = Mask[V1DstIndex];
7976 V2DstIndex = V1DstIndex;
7979 V2SrcIndex = Mask[V2DstIndex] - 4;
7982 // If no V1 inputs are used in place, then the result is created only from
7983 // the zero mask and the V2 insertion - so remove V1 dependency.
7985 V1 = DAG.getUNDEF(MVT::v4f32);
7987 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7988 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7990 // Insert the V2 element into the desired position.
7992 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7993 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7996 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7997 /// UNPCK instruction.
7999 /// This specifically targets cases where we end up with alternating between
8000 /// the two inputs, and so can permute them into something that feeds a single
8001 /// UNPCK instruction. Note that this routine only targets integer vectors
8002 /// because for floating point vectors we have a generalized SHUFPS lowering
8003 /// strategy that handles everything that doesn't *exactly* match an unpack,
8004 /// making this clever lowering unnecessary.
8005 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8006 SDValue V1, SDValue V2,
8008 SelectionDAG &DAG) {
8009 assert(!VT.isFloatingPoint() &&
8010 "This routine only supports integer vectors.");
8011 assert(!isSingleInputShuffleMask(Mask) &&
8012 "This routine should only be used when blending two inputs.");
8013 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8015 int Size = Mask.size();
8017 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8018 return M >= 0 && M % Size < Size / 2;
8020 int NumHiInputs = std::count_if(
8021 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8023 bool UnpackLo = NumLoInputs >= NumHiInputs;
8025 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8026 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8027 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8029 for (int i = 0; i < Size; ++i) {
8033 // Each element of the unpack contains Scale elements from this mask.
8034 int UnpackIdx = i / Scale;
8036 // We only handle the case where V1 feeds the first slots of the unpack.
8037 // We rely on canonicalization to ensure this is the case.
8038 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8041 // Setup the mask for this input. The indexing is tricky as we have to
8042 // handle the unpack stride.
8043 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8044 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8048 // If we will have to shuffle both inputs to use the unpack, check whether
8049 // we can just unpack first and shuffle the result. If so, skip this unpack.
8050 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8051 !isNoopShuffleMask(V2Mask))
8054 // Shuffle the inputs into place.
8055 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8056 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8058 // Cast the inputs to the type we will use to unpack them.
8059 V1 = DAG.getBitcast(UnpackVT, V1);
8060 V2 = DAG.getBitcast(UnpackVT, V2);
8062 // Unpack the inputs and cast the result back to the desired type.
8063 return DAG.getBitcast(
8064 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8068 // We try each unpack from the largest to the smallest to try and find one
8069 // that fits this mask.
8070 int OrigNumElements = VT.getVectorNumElements();
8071 int OrigScalarSize = VT.getScalarSizeInBits();
8072 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8073 int Scale = ScalarSize / OrigScalarSize;
8074 int NumElements = OrigNumElements / Scale;
8075 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8076 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8080 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8082 if (NumLoInputs == 0 || NumHiInputs == 0) {
8083 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8084 "We have to have *some* inputs!");
8085 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8087 // FIXME: We could consider the total complexity of the permute of each
8088 // possible unpacking. Or at the least we should consider how many
8089 // half-crossings are created.
8090 // FIXME: We could consider commuting the unpacks.
8092 SmallVector<int, 32> PermMask;
8093 PermMask.assign(Size, -1);
8094 for (int i = 0; i < Size; ++i) {
8098 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8101 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8103 return DAG.getVectorShuffle(
8104 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8106 DAG.getUNDEF(VT), PermMask);
8112 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8114 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8115 /// support for floating point shuffles but not integer shuffles. These
8116 /// instructions will incur a domain crossing penalty on some chips though so
8117 /// it is better to avoid lowering through this for integer vectors where
8119 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8120 const X86Subtarget *Subtarget,
8121 SelectionDAG &DAG) {
8123 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8124 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8125 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8126 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8127 ArrayRef<int> Mask = SVOp->getMask();
8128 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8130 if (isSingleInputShuffleMask(Mask)) {
8131 // Use low duplicate instructions for masks that match their pattern.
8132 if (Subtarget->hasSSE3())
8133 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8134 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8136 // Straight shuffle of a single input vector. Simulate this by using the
8137 // single input as both of the "inputs" to this instruction..
8138 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8140 if (Subtarget->hasAVX()) {
8141 // If we have AVX, we can use VPERMILPS which will allow folding a load
8142 // into the shuffle.
8143 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8144 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8147 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8148 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8150 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8151 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8153 // If we have a single input, insert that into V1 if we can do so cheaply.
8154 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8155 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8156 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8158 // Try inverting the insertion since for v2 masks it is easy to do and we
8159 // can't reliably sort the mask one way or the other.
8160 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8161 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8162 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8163 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8167 // Try to use one of the special instruction patterns to handle two common
8168 // blend patterns if a zero-blend above didn't work.
8169 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8170 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8171 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8172 // We can either use a special instruction to load over the low double or
8173 // to move just the low double.
8175 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8177 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8179 if (Subtarget->hasSSE41())
8180 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8184 // Use dedicated unpack instructions for masks that match their pattern.
8185 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8186 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8187 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8188 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8190 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8191 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8192 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8195 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8197 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8198 /// the integer unit to minimize domain crossing penalties. However, for blends
8199 /// it falls back to the floating point shuffle operation with appropriate bit
8201 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8202 const X86Subtarget *Subtarget,
8203 SelectionDAG &DAG) {
8205 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8206 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8207 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8209 ArrayRef<int> Mask = SVOp->getMask();
8210 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8212 if (isSingleInputShuffleMask(Mask)) {
8213 // Check for being able to broadcast a single element.
8214 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8215 Mask, Subtarget, DAG))
8218 // Straight shuffle of a single input vector. For everything from SSE2
8219 // onward this has a single fast instruction with no scary immediates.
8220 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8221 V1 = DAG.getBitcast(MVT::v4i32, V1);
8222 int WidenedMask[4] = {
8223 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8224 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8225 return DAG.getBitcast(
8227 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8228 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8230 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8231 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8232 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8233 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8235 // If we have a blend of two PACKUS operations an the blend aligns with the
8236 // low and half halves, we can just merge the PACKUS operations. This is
8237 // particularly important as it lets us merge shuffles that this routine itself
8239 auto GetPackNode = [](SDValue V) {
8240 while (V.getOpcode() == ISD::BITCAST)
8241 V = V.getOperand(0);
8243 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8245 if (SDValue V1Pack = GetPackNode(V1))
8246 if (SDValue V2Pack = GetPackNode(V2))
8247 return DAG.getBitcast(MVT::v2i64,
8248 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8249 Mask[0] == 0 ? V1Pack.getOperand(0)
8250 : V1Pack.getOperand(1),
8251 Mask[1] == 2 ? V2Pack.getOperand(0)
8252 : V2Pack.getOperand(1)));
8254 // Try to use shift instructions.
8256 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8259 // When loading a scalar and then shuffling it into a vector we can often do
8260 // the insertion cheaply.
8261 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8262 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8264 // Try inverting the insertion since for v2 masks it is easy to do and we
8265 // can't reliably sort the mask one way or the other.
8266 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8267 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8268 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8271 // We have different paths for blend lowering, but they all must use the
8272 // *exact* same predicate.
8273 bool IsBlendSupported = Subtarget->hasSSE41();
8274 if (IsBlendSupported)
8275 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8279 // Use dedicated unpack instructions for masks that match their pattern.
8280 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8281 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8282 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8283 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8285 // Try to use byte rotation instructions.
8286 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8287 if (Subtarget->hasSSSE3())
8288 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8289 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8292 // If we have direct support for blends, we should lower by decomposing into
8293 // a permute. That will be faster than the domain cross.
8294 if (IsBlendSupported)
8295 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8298 // We implement this with SHUFPD which is pretty lame because it will likely
8299 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8300 // However, all the alternatives are still more cycles and newer chips don't
8301 // have this problem. It would be really nice if x86 had better shuffles here.
8302 V1 = DAG.getBitcast(MVT::v2f64, V1);
8303 V2 = DAG.getBitcast(MVT::v2f64, V2);
8304 return DAG.getBitcast(MVT::v2i64,
8305 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8308 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8310 /// This is used to disable more specialized lowerings when the shufps lowering
8311 /// will happen to be efficient.
8312 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8313 // This routine only handles 128-bit shufps.
8314 assert(Mask.size() == 4 && "Unsupported mask size!");
8316 // To lower with a single SHUFPS we need to have the low half and high half
8317 // each requiring a single input.
8318 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8320 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8326 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8328 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8329 /// It makes no assumptions about whether this is the *best* lowering, it simply
8331 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8332 ArrayRef<int> Mask, SDValue V1,
8333 SDValue V2, SelectionDAG &DAG) {
8334 SDValue LowV = V1, HighV = V2;
8335 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8338 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8340 if (NumV2Elements == 1) {
8342 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8345 // Compute the index adjacent to V2Index and in the same half by toggling
8347 int V2AdjIndex = V2Index ^ 1;
8349 if (Mask[V2AdjIndex] == -1) {
8350 // Handles all the cases where we have a single V2 element and an undef.
8351 // This will only ever happen in the high lanes because we commute the
8352 // vector otherwise.
8354 std::swap(LowV, HighV);
8355 NewMask[V2Index] -= 4;
8357 // Handle the case where the V2 element ends up adjacent to a V1 element.
8358 // To make this work, blend them together as the first step.
8359 int V1Index = V2AdjIndex;
8360 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8361 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8362 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8364 // Now proceed to reconstruct the final blend as we have the necessary
8365 // high or low half formed.
8372 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8373 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8375 } else if (NumV2Elements == 2) {
8376 if (Mask[0] < 4 && Mask[1] < 4) {
8377 // Handle the easy case where we have V1 in the low lanes and V2 in the
8381 } else if (Mask[2] < 4 && Mask[3] < 4) {
8382 // We also handle the reversed case because this utility may get called
8383 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8384 // arrange things in the right direction.
8390 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8391 // trying to place elements directly, just blend them and set up the final
8392 // shuffle to place them.
8394 // The first two blend mask elements are for V1, the second two are for
8396 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8397 Mask[2] < 4 ? Mask[2] : Mask[3],
8398 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8399 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8400 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8401 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8403 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8406 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8407 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8408 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8409 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8412 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8413 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8416 /// \brief Lower 4-lane 32-bit floating point shuffles.
8418 /// Uses instructions exclusively from the floating point unit to minimize
8419 /// domain crossing penalties, as these are sufficient to implement all v4f32
8421 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8422 const X86Subtarget *Subtarget,
8423 SelectionDAG &DAG) {
8425 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8426 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8427 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8429 ArrayRef<int> Mask = SVOp->getMask();
8430 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8433 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8435 if (NumV2Elements == 0) {
8436 // Check for being able to broadcast a single element.
8437 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8438 Mask, Subtarget, DAG))
8441 // Use even/odd duplicate instructions for masks that match their pattern.
8442 if (Subtarget->hasSSE3()) {
8443 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8444 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8445 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8446 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8449 if (Subtarget->hasAVX()) {
8450 // If we have AVX, we can use VPERMILPS which will allow folding a load
8451 // into the shuffle.
8452 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8453 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8456 // Otherwise, use a straight shuffle of a single input vector. We pass the
8457 // input vector to both operands to simulate this with a SHUFPS.
8458 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8459 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8462 // There are special ways we can lower some single-element blends. However, we
8463 // have custom ways we can lower more complex single-element blends below that
8464 // we defer to if both this and BLENDPS fail to match, so restrict this to
8465 // when the V2 input is targeting element 0 of the mask -- that is the fast
8467 if (NumV2Elements == 1 && Mask[0] >= 4)
8468 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8469 Mask, Subtarget, DAG))
8472 if (Subtarget->hasSSE41()) {
8473 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8477 // Use INSERTPS if we can complete the shuffle efficiently.
8478 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8481 if (!isSingleSHUFPSMask(Mask))
8482 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8483 DL, MVT::v4f32, V1, V2, Mask, DAG))
8487 // Use dedicated unpack instructions for masks that match their pattern.
8488 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8489 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8490 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8491 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8492 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8493 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8494 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8495 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8497 // Otherwise fall back to a SHUFPS lowering strategy.
8498 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8501 /// \brief Lower 4-lane i32 vector shuffles.
8503 /// We try to handle these with integer-domain shuffles where we can, but for
8504 /// blends we use the floating point domain blend instructions.
8505 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8506 const X86Subtarget *Subtarget,
8507 SelectionDAG &DAG) {
8509 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8510 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8511 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8513 ArrayRef<int> Mask = SVOp->getMask();
8514 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8516 // Whenever we can lower this as a zext, that instruction is strictly faster
8517 // than any alternative. It also allows us to fold memory operands into the
8518 // shuffle in many cases.
8519 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8520 Mask, Subtarget, DAG))
8524 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8526 if (NumV2Elements == 0) {
8527 // Check for being able to broadcast a single element.
8528 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8529 Mask, Subtarget, DAG))
8532 // Straight shuffle of a single input vector. For everything from SSE2
8533 // onward this has a single fast instruction with no scary immediates.
8534 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8535 // but we aren't actually going to use the UNPCK instruction because doing
8536 // so prevents folding a load into this instruction or making a copy.
8537 const int UnpackLoMask[] = {0, 0, 1, 1};
8538 const int UnpackHiMask[] = {2, 2, 3, 3};
8539 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8540 Mask = UnpackLoMask;
8541 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8542 Mask = UnpackHiMask;
8544 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8545 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8548 // Try to use shift instructions.
8550 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8553 // There are special ways we can lower some single-element blends.
8554 if (NumV2Elements == 1)
8555 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8556 Mask, Subtarget, DAG))
8559 // We have different paths for blend lowering, but they all must use the
8560 // *exact* same predicate.
8561 bool IsBlendSupported = Subtarget->hasSSE41();
8562 if (IsBlendSupported)
8563 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8567 if (SDValue Masked =
8568 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8571 // Use dedicated unpack instructions for masks that match their pattern.
8572 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8573 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8574 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8575 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8576 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8577 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8578 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8579 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8581 // Try to use byte rotation instructions.
8582 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8583 if (Subtarget->hasSSSE3())
8584 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8585 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8588 // If we have direct support for blends, we should lower by decomposing into
8589 // a permute. That will be faster than the domain cross.
8590 if (IsBlendSupported)
8591 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8594 // Try to lower by permuting the inputs into an unpack instruction.
8595 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8599 // We implement this with SHUFPS because it can blend from two vectors.
8600 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8601 // up the inputs, bypassing domain shift penalties that we would encur if we
8602 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8604 return DAG.getBitcast(
8606 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8607 DAG.getBitcast(MVT::v4f32, V2), Mask));
8610 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8611 /// shuffle lowering, and the most complex part.
8613 /// The lowering strategy is to try to form pairs of input lanes which are
8614 /// targeted at the same half of the final vector, and then use a dword shuffle
8615 /// to place them onto the right half, and finally unpack the paired lanes into
8616 /// their final position.
8618 /// The exact breakdown of how to form these dword pairs and align them on the
8619 /// correct sides is really tricky. See the comments within the function for
8620 /// more of the details.
8622 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8623 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8624 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8625 /// vector, form the analogous 128-bit 8-element Mask.
8626 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8627 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8628 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8629 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8630 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8632 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8633 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8634 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8636 SmallVector<int, 4> LoInputs;
8637 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8638 [](int M) { return M >= 0; });
8639 std::sort(LoInputs.begin(), LoInputs.end());
8640 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8641 SmallVector<int, 4> HiInputs;
8642 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8643 [](int M) { return M >= 0; });
8644 std::sort(HiInputs.begin(), HiInputs.end());
8645 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8647 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8648 int NumHToL = LoInputs.size() - NumLToL;
8650 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8651 int NumHToH = HiInputs.size() - NumLToH;
8652 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8653 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8654 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8655 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8657 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8658 // such inputs we can swap two of the dwords across the half mark and end up
8659 // with <=2 inputs to each half in each half. Once there, we can fall through
8660 // to the generic code below. For example:
8662 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8663 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8665 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8666 // and an existing 2-into-2 on the other half. In this case we may have to
8667 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8668 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8669 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8670 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8671 // half than the one we target for fixing) will be fixed when we re-enter this
8672 // path. We will also combine away any sequence of PSHUFD instructions that
8673 // result into a single instruction. Here is an example of the tricky case:
8675 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8676 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8678 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8680 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8681 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8683 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8684 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8686 // The result is fine to be handled by the generic logic.
8687 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8688 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8689 int AOffset, int BOffset) {
8690 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8691 "Must call this with A having 3 or 1 inputs from the A half.");
8692 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8693 "Must call this with B having 1 or 3 inputs from the B half.");
8694 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8695 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8697 bool ThreeAInputs = AToAInputs.size() == 3;
8699 // Compute the index of dword with only one word among the three inputs in
8700 // a half by taking the sum of the half with three inputs and subtracting
8701 // the sum of the actual three inputs. The difference is the remaining
8704 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8705 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8706 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8707 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8708 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8709 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8710 int TripleNonInputIdx =
8711 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8712 TripleDWord = TripleNonInputIdx / 2;
8714 // We use xor with one to compute the adjacent DWord to whichever one the
8716 OneInputDWord = (OneInput / 2) ^ 1;
8718 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8719 // and BToA inputs. If there is also such a problem with the BToB and AToB
8720 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8721 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8722 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8723 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8724 // Compute how many inputs will be flipped by swapping these DWords. We
8726 // to balance this to ensure we don't form a 3-1 shuffle in the other
8728 int NumFlippedAToBInputs =
8729 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8730 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8731 int NumFlippedBToBInputs =
8732 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8733 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8734 if ((NumFlippedAToBInputs == 1 &&
8735 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8736 (NumFlippedBToBInputs == 1 &&
8737 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8738 // We choose whether to fix the A half or B half based on whether that
8739 // half has zero flipped inputs. At zero, we may not be able to fix it
8740 // with that half. We also bias towards fixing the B half because that
8741 // will more commonly be the high half, and we have to bias one way.
8742 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8743 ArrayRef<int> Inputs) {
8744 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8745 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8746 PinnedIdx ^ 1) != Inputs.end();
8747 // Determine whether the free index is in the flipped dword or the
8748 // unflipped dword based on where the pinned index is. We use this bit
8749 // in an xor to conditionally select the adjacent dword.
8750 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8751 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8752 FixFreeIdx) != Inputs.end();
8753 if (IsFixIdxInput == IsFixFreeIdxInput)
8755 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8756 FixFreeIdx) != Inputs.end();
8757 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8758 "We need to be changing the number of flipped inputs!");
8759 int PSHUFHalfMask[] = {0, 1, 2, 3};
8760 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8761 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8763 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8766 if (M != -1 && M == FixIdx)
8768 else if (M != -1 && M == FixFreeIdx)
8771 if (NumFlippedBToBInputs != 0) {
8773 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8774 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8776 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8777 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8778 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8783 int PSHUFDMask[] = {0, 1, 2, 3};
8784 PSHUFDMask[ADWord] = BDWord;
8785 PSHUFDMask[BDWord] = ADWord;
8788 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8789 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8791 // Adjust the mask to match the new locations of A and B.
8793 if (M != -1 && M/2 == ADWord)
8794 M = 2 * BDWord + M % 2;
8795 else if (M != -1 && M/2 == BDWord)
8796 M = 2 * ADWord + M % 2;
8798 // Recurse back into this routine to re-compute state now that this isn't
8799 // a 3 and 1 problem.
8800 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8803 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8804 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8805 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8806 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8808 // At this point there are at most two inputs to the low and high halves from
8809 // each half. That means the inputs can always be grouped into dwords and
8810 // those dwords can then be moved to the correct half with a dword shuffle.
8811 // We use at most one low and one high word shuffle to collect these paired
8812 // inputs into dwords, and finally a dword shuffle to place them.
8813 int PSHUFLMask[4] = {-1, -1, -1, -1};
8814 int PSHUFHMask[4] = {-1, -1, -1, -1};
8815 int PSHUFDMask[4] = {-1, -1, -1, -1};
8817 // First fix the masks for all the inputs that are staying in their
8818 // original halves. This will then dictate the targets of the cross-half
8820 auto fixInPlaceInputs =
8821 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8822 MutableArrayRef<int> SourceHalfMask,
8823 MutableArrayRef<int> HalfMask, int HalfOffset) {
8824 if (InPlaceInputs.empty())
8826 if (InPlaceInputs.size() == 1) {
8827 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8828 InPlaceInputs[0] - HalfOffset;
8829 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8832 if (IncomingInputs.empty()) {
8833 // Just fix all of the in place inputs.
8834 for (int Input : InPlaceInputs) {
8835 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8836 PSHUFDMask[Input / 2] = Input / 2;
8841 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8842 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8843 InPlaceInputs[0] - HalfOffset;
8844 // Put the second input next to the first so that they are packed into
8845 // a dword. We find the adjacent index by toggling the low bit.
8846 int AdjIndex = InPlaceInputs[0] ^ 1;
8847 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8848 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8849 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8851 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8852 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8854 // Now gather the cross-half inputs and place them into a free dword of
8855 // their target half.
8856 // FIXME: This operation could almost certainly be simplified dramatically to
8857 // look more like the 3-1 fixing operation.
8858 auto moveInputsToRightHalf = [&PSHUFDMask](
8859 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8860 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8861 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8863 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8864 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8866 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8868 int LowWord = Word & ~1;
8869 int HighWord = Word | 1;
8870 return isWordClobbered(SourceHalfMask, LowWord) ||
8871 isWordClobbered(SourceHalfMask, HighWord);
8874 if (IncomingInputs.empty())
8877 if (ExistingInputs.empty()) {
8878 // Map any dwords with inputs from them into the right half.
8879 for (int Input : IncomingInputs) {
8880 // If the source half mask maps over the inputs, turn those into
8881 // swaps and use the swapped lane.
8882 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8883 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8884 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8885 Input - SourceOffset;
8886 // We have to swap the uses in our half mask in one sweep.
8887 for (int &M : HalfMask)
8888 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8890 else if (M == Input)
8891 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8893 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8894 Input - SourceOffset &&
8895 "Previous placement doesn't match!");
8897 // Note that this correctly re-maps both when we do a swap and when
8898 // we observe the other side of the swap above. We rely on that to
8899 // avoid swapping the members of the input list directly.
8900 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8903 // Map the input's dword into the correct half.
8904 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8905 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8907 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8909 "Previous placement doesn't match!");
8912 // And just directly shift any other-half mask elements to be same-half
8913 // as we will have mirrored the dword containing the element into the
8914 // same position within that half.
8915 for (int &M : HalfMask)
8916 if (M >= SourceOffset && M < SourceOffset + 4) {
8917 M = M - SourceOffset + DestOffset;
8918 assert(M >= 0 && "This should never wrap below zero!");
8923 // Ensure we have the input in a viable dword of its current half. This
8924 // is particularly tricky because the original position may be clobbered
8925 // by inputs being moved and *staying* in that half.
8926 if (IncomingInputs.size() == 1) {
8927 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8928 int InputFixed = std::find(std::begin(SourceHalfMask),
8929 std::end(SourceHalfMask), -1) -
8930 std::begin(SourceHalfMask) + SourceOffset;
8931 SourceHalfMask[InputFixed - SourceOffset] =
8932 IncomingInputs[0] - SourceOffset;
8933 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8935 IncomingInputs[0] = InputFixed;
8937 } else if (IncomingInputs.size() == 2) {
8938 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8939 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8940 // We have two non-adjacent or clobbered inputs we need to extract from
8941 // the source half. To do this, we need to map them into some adjacent
8942 // dword slot in the source mask.
8943 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8944 IncomingInputs[1] - SourceOffset};
8946 // If there is a free slot in the source half mask adjacent to one of
8947 // the inputs, place the other input in it. We use (Index XOR 1) to
8948 // compute an adjacent index.
8949 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8950 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8951 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8952 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8953 InputsFixed[1] = InputsFixed[0] ^ 1;
8954 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8955 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8956 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8957 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8958 InputsFixed[0] = InputsFixed[1] ^ 1;
8959 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8960 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8961 // The two inputs are in the same DWord but it is clobbered and the
8962 // adjacent DWord isn't used at all. Move both inputs to the free
8964 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8965 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8966 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8967 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8969 // The only way we hit this point is if there is no clobbering
8970 // (because there are no off-half inputs to this half) and there is no
8971 // free slot adjacent to one of the inputs. In this case, we have to
8972 // swap an input with a non-input.
8973 for (int i = 0; i < 4; ++i)
8974 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8975 "We can't handle any clobbers here!");
8976 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8977 "Cannot have adjacent inputs here!");
8979 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8980 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8982 // We also have to update the final source mask in this case because
8983 // it may need to undo the above swap.
8984 for (int &M : FinalSourceHalfMask)
8985 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8986 M = InputsFixed[1] + SourceOffset;
8987 else if (M == InputsFixed[1] + SourceOffset)
8988 M = (InputsFixed[0] ^ 1) + SourceOffset;
8990 InputsFixed[1] = InputsFixed[0] ^ 1;
8993 // Point everything at the fixed inputs.
8994 for (int &M : HalfMask)
8995 if (M == IncomingInputs[0])
8996 M = InputsFixed[0] + SourceOffset;
8997 else if (M == IncomingInputs[1])
8998 M = InputsFixed[1] + SourceOffset;
9000 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9001 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9004 llvm_unreachable("Unhandled input size!");
9007 // Now hoist the DWord down to the right half.
9008 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9009 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9010 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9011 for (int &M : HalfMask)
9012 for (int Input : IncomingInputs)
9014 M = FreeDWord * 2 + Input % 2;
9016 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9017 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9018 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9019 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9021 // Now enact all the shuffles we've computed to move the inputs into their
9023 if (!isNoopShuffleMask(PSHUFLMask))
9024 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9025 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9026 if (!isNoopShuffleMask(PSHUFHMask))
9027 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9028 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9029 if (!isNoopShuffleMask(PSHUFDMask))
9032 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9033 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9035 // At this point, each half should contain all its inputs, and we can then
9036 // just shuffle them into their final position.
9037 assert(std::count_if(LoMask.begin(), LoMask.end(),
9038 [](int M) { return M >= 4; }) == 0 &&
9039 "Failed to lift all the high half inputs to the low mask!");
9040 assert(std::count_if(HiMask.begin(), HiMask.end(),
9041 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9042 "Failed to lift all the low half inputs to the high mask!");
9044 // Do a half shuffle for the low mask.
9045 if (!isNoopShuffleMask(LoMask))
9046 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9047 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9049 // Do a half shuffle with the high mask after shifting its values down.
9050 for (int &M : HiMask)
9053 if (!isNoopShuffleMask(HiMask))
9054 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9055 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9060 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9061 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9062 SDValue V2, ArrayRef<int> Mask,
9063 SelectionDAG &DAG, bool &V1InUse,
9065 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9071 int Size = Mask.size();
9072 int Scale = 16 / Size;
9073 for (int i = 0; i < 16; ++i) {
9074 if (Mask[i / Scale] == -1) {
9075 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9077 const int ZeroMask = 0x80;
9078 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9080 int V2Idx = Mask[i / Scale] < Size
9082 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9083 if (Zeroable[i / Scale])
9084 V1Idx = V2Idx = ZeroMask;
9085 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9086 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9087 V1InUse |= (ZeroMask != V1Idx);
9088 V2InUse |= (ZeroMask != V2Idx);
9093 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9094 DAG.getBitcast(MVT::v16i8, V1),
9095 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9097 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9098 DAG.getBitcast(MVT::v16i8, V2),
9099 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9101 // If we need shuffled inputs from both, blend the two.
9103 if (V1InUse && V2InUse)
9104 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9106 V = V1InUse ? V1 : V2;
9108 // Cast the result back to the correct type.
9109 return DAG.getBitcast(VT, V);
9112 /// \brief Generic lowering of 8-lane i16 shuffles.
9114 /// This handles both single-input shuffles and combined shuffle/blends with
9115 /// two inputs. The single input shuffles are immediately delegated to
9116 /// a dedicated lowering routine.
9118 /// The blends are lowered in one of three fundamental ways. If there are few
9119 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9120 /// of the input is significantly cheaper when lowered as an interleaving of
9121 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9122 /// halves of the inputs separately (making them have relatively few inputs)
9123 /// and then concatenate them.
9124 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9125 const X86Subtarget *Subtarget,
9126 SelectionDAG &DAG) {
9128 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9129 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9130 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9132 ArrayRef<int> OrigMask = SVOp->getMask();
9133 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9134 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9135 MutableArrayRef<int> Mask(MaskStorage);
9137 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9139 // Whenever we can lower this as a zext, that instruction is strictly faster
9140 // than any alternative.
9141 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9142 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9145 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9147 auto isV2 = [](int M) { return M >= 8; };
9149 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9151 if (NumV2Inputs == 0) {
9152 // Check for being able to broadcast a single element.
9153 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9154 Mask, Subtarget, DAG))
9157 // Try to use shift instructions.
9159 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9162 // Use dedicated unpack instructions for masks that match their pattern.
9163 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9164 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9165 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9166 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9168 // Try to use byte rotation instructions.
9169 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9170 Mask, Subtarget, DAG))
9173 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9177 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9178 "All single-input shuffles should be canonicalized to be V1-input "
9181 // Try to use shift instructions.
9183 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9186 // See if we can use SSE4A Extraction / Insertion.
9187 if (Subtarget->hasSSE4A())
9188 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9191 // There are special ways we can lower some single-element blends.
9192 if (NumV2Inputs == 1)
9193 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9194 Mask, Subtarget, DAG))
9197 // We have different paths for blend lowering, but they all must use the
9198 // *exact* same predicate.
9199 bool IsBlendSupported = Subtarget->hasSSE41();
9200 if (IsBlendSupported)
9201 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9205 if (SDValue Masked =
9206 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9209 // Use dedicated unpack instructions for masks that match their pattern.
9210 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9211 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9212 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9213 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9215 // Try to use byte rotation instructions.
9216 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9217 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9220 if (SDValue BitBlend =
9221 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9224 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9228 // If we can't directly blend but can use PSHUFB, that will be better as it
9229 // can both shuffle and set up the inefficient blend.
9230 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9231 bool V1InUse, V2InUse;
9232 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9236 // We can always bit-blend if we have to so the fallback strategy is to
9237 // decompose into single-input permutes and blends.
9238 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9242 /// \brief Check whether a compaction lowering can be done by dropping even
9243 /// elements and compute how many times even elements must be dropped.
9245 /// This handles shuffles which take every Nth element where N is a power of
9246 /// two. Example shuffle masks:
9248 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9249 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9250 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9251 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9252 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9253 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9255 /// Any of these lanes can of course be undef.
9257 /// This routine only supports N <= 3.
9258 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9261 /// \returns N above, or the number of times even elements must be dropped if
9262 /// there is such a number. Otherwise returns zero.
9263 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9264 // Figure out whether we're looping over two inputs or just one.
9265 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9267 // The modulus for the shuffle vector entries is based on whether this is
9268 // a single input or not.
9269 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9270 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9271 "We should only be called with masks with a power-of-2 size!");
9273 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9275 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9276 // and 2^3 simultaneously. This is because we may have ambiguity with
9277 // partially undef inputs.
9278 bool ViableForN[3] = {true, true, true};
9280 for (int i = 0, e = Mask.size(); i < e; ++i) {
9281 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9286 bool IsAnyViable = false;
9287 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9288 if (ViableForN[j]) {
9291 // The shuffle mask must be equal to (i * 2^N) % M.
9292 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9295 ViableForN[j] = false;
9297 // Early exit if we exhaust the possible powers of two.
9302 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9306 // Return 0 as there is no viable power of two.
9310 /// \brief Generic lowering of v16i8 shuffles.
9312 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9313 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9314 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9315 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9317 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9318 const X86Subtarget *Subtarget,
9319 SelectionDAG &DAG) {
9321 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9322 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9323 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9325 ArrayRef<int> Mask = SVOp->getMask();
9326 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9328 // Try to use shift instructions.
9330 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9333 // Try to use byte rotation instructions.
9334 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9335 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9338 // Try to use a zext lowering.
9339 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9340 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9343 // See if we can use SSE4A Extraction / Insertion.
9344 if (Subtarget->hasSSE4A())
9345 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9349 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9351 // For single-input shuffles, there are some nicer lowering tricks we can use.
9352 if (NumV2Elements == 0) {
9353 // Check for being able to broadcast a single element.
9354 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9355 Mask, Subtarget, DAG))
9358 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9359 // Notably, this handles splat and partial-splat shuffles more efficiently.
9360 // However, it only makes sense if the pre-duplication shuffle simplifies
9361 // things significantly. Currently, this means we need to be able to
9362 // express the pre-duplication shuffle as an i16 shuffle.
9364 // FIXME: We should check for other patterns which can be widened into an
9365 // i16 shuffle as well.
9366 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9367 for (int i = 0; i < 16; i += 2)
9368 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9373 auto tryToWidenViaDuplication = [&]() -> SDValue {
9374 if (!canWidenViaDuplication(Mask))
9376 SmallVector<int, 4> LoInputs;
9377 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9378 [](int M) { return M >= 0 && M < 8; });
9379 std::sort(LoInputs.begin(), LoInputs.end());
9380 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9382 SmallVector<int, 4> HiInputs;
9383 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9384 [](int M) { return M >= 8; });
9385 std::sort(HiInputs.begin(), HiInputs.end());
9386 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9389 bool TargetLo = LoInputs.size() >= HiInputs.size();
9390 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9391 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9393 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9394 SmallDenseMap<int, int, 8> LaneMap;
9395 for (int I : InPlaceInputs) {
9396 PreDupI16Shuffle[I/2] = I/2;
9399 int j = TargetLo ? 0 : 4, je = j + 4;
9400 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9401 // Check if j is already a shuffle of this input. This happens when
9402 // there are two adjacent bytes after we move the low one.
9403 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9404 // If we haven't yet mapped the input, search for a slot into which
9406 while (j < je && PreDupI16Shuffle[j] != -1)
9410 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9413 // Map this input with the i16 shuffle.
9414 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9417 // Update the lane map based on the mapping we ended up with.
9418 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9420 V1 = DAG.getBitcast(
9422 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9423 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9425 // Unpack the bytes to form the i16s that will be shuffled into place.
9426 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9427 MVT::v16i8, V1, V1);
9429 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9430 for (int i = 0; i < 16; ++i)
9431 if (Mask[i] != -1) {
9432 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9433 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9434 if (PostDupI16Shuffle[i / 2] == -1)
9435 PostDupI16Shuffle[i / 2] = MappedMask;
9437 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9438 "Conflicting entrties in the original shuffle!");
9440 return DAG.getBitcast(
9442 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9443 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9445 if (SDValue V = tryToWidenViaDuplication())
9449 if (SDValue Masked =
9450 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9453 // Use dedicated unpack instructions for masks that match their pattern.
9454 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9455 0, 16, 1, 17, 2, 18, 3, 19,
9457 4, 20, 5, 21, 6, 22, 7, 23}))
9458 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9459 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9460 8, 24, 9, 25, 10, 26, 11, 27,
9462 12, 28, 13, 29, 14, 30, 15, 31}))
9463 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9465 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9466 // with PSHUFB. It is important to do this before we attempt to generate any
9467 // blends but after all of the single-input lowerings. If the single input
9468 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9469 // want to preserve that and we can DAG combine any longer sequences into
9470 // a PSHUFB in the end. But once we start blending from multiple inputs,
9471 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9472 // and there are *very* few patterns that would actually be faster than the
9473 // PSHUFB approach because of its ability to zero lanes.
9475 // FIXME: The only exceptions to the above are blends which are exact
9476 // interleavings with direct instructions supporting them. We currently don't
9477 // handle those well here.
9478 if (Subtarget->hasSSSE3()) {
9479 bool V1InUse = false;
9480 bool V2InUse = false;
9482 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9483 DAG, V1InUse, V2InUse);
9485 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9486 // do so. This avoids using them to handle blends-with-zero which is
9487 // important as a single pshufb is significantly faster for that.
9488 if (V1InUse && V2InUse) {
9489 if (Subtarget->hasSSE41())
9490 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9491 Mask, Subtarget, DAG))
9494 // We can use an unpack to do the blending rather than an or in some
9495 // cases. Even though the or may be (very minorly) more efficient, we
9496 // preference this lowering because there are common cases where part of
9497 // the complexity of the shuffles goes away when we do the final blend as
9499 // FIXME: It might be worth trying to detect if the unpack-feeding
9500 // shuffles will both be pshufb, in which case we shouldn't bother with
9502 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9503 DL, MVT::v16i8, V1, V2, Mask, DAG))
9510 // There are special ways we can lower some single-element blends.
9511 if (NumV2Elements == 1)
9512 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9513 Mask, Subtarget, DAG))
9516 if (SDValue BitBlend =
9517 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9520 // Check whether a compaction lowering can be done. This handles shuffles
9521 // which take every Nth element for some even N. See the helper function for
9524 // We special case these as they can be particularly efficiently handled with
9525 // the PACKUSB instruction on x86 and they show up in common patterns of
9526 // rearranging bytes to truncate wide elements.
9527 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9528 // NumEvenDrops is the power of two stride of the elements. Another way of
9529 // thinking about it is that we need to drop the even elements this many
9530 // times to get the original input.
9531 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9533 // First we need to zero all the dropped bytes.
9534 assert(NumEvenDrops <= 3 &&
9535 "No support for dropping even elements more than 3 times.");
9536 // We use the mask type to pick which bytes are preserved based on how many
9537 // elements are dropped.
9538 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9539 SDValue ByteClearMask = DAG.getBitcast(
9540 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9541 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9543 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9545 // Now pack things back together.
9546 V1 = DAG.getBitcast(MVT::v8i16, V1);
9547 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9548 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9549 for (int i = 1; i < NumEvenDrops; ++i) {
9550 Result = DAG.getBitcast(MVT::v8i16, Result);
9551 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9557 // Handle multi-input cases by blending single-input shuffles.
9558 if (NumV2Elements > 0)
9559 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9562 // The fallback path for single-input shuffles widens this into two v8i16
9563 // vectors with unpacks, shuffles those, and then pulls them back together
9567 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9568 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9569 for (int i = 0; i < 16; ++i)
9571 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9573 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9575 SDValue VLoHalf, VHiHalf;
9576 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9577 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9579 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9580 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9581 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9582 [](int M) { return M >= 0 && M % 2 == 1; })) {
9583 // Use a mask to drop the high bytes.
9584 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9585 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9586 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9588 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9589 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9591 // Squash the masks to point directly into VLoHalf.
9592 for (int &M : LoBlendMask)
9595 for (int &M : HiBlendMask)
9599 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9600 // VHiHalf so that we can blend them as i16s.
9601 VLoHalf = DAG.getBitcast(
9602 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9603 VHiHalf = DAG.getBitcast(
9604 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9607 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9608 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9610 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9613 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9615 /// This routine breaks down the specific type of 128-bit shuffle and
9616 /// dispatches to the lowering routines accordingly.
9617 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9618 MVT VT, const X86Subtarget *Subtarget,
9619 SelectionDAG &DAG) {
9620 switch (VT.SimpleTy) {
9622 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9624 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9626 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9628 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9630 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9632 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9635 llvm_unreachable("Unimplemented!");
9639 /// \brief Helper function to test whether a shuffle mask could be
9640 /// simplified by widening the elements being shuffled.
9642 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9643 /// leaves it in an unspecified state.
9645 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9646 /// shuffle masks. The latter have the special property of a '-2' representing
9647 /// a zero-ed lane of a vector.
9648 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9649 SmallVectorImpl<int> &WidenedMask) {
9650 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9651 // If both elements are undef, its trivial.
9652 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9653 WidenedMask.push_back(SM_SentinelUndef);
9657 // Check for an undef mask and a mask value properly aligned to fit with
9658 // a pair of values. If we find such a case, use the non-undef mask's value.
9659 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9660 WidenedMask.push_back(Mask[i + 1] / 2);
9663 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9664 WidenedMask.push_back(Mask[i] / 2);
9668 // When zeroing, we need to spread the zeroing across both lanes to widen.
9669 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9670 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9671 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9672 WidenedMask.push_back(SM_SentinelZero);
9678 // Finally check if the two mask values are adjacent and aligned with
9680 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9681 WidenedMask.push_back(Mask[i] / 2);
9685 // Otherwise we can't safely widen the elements used in this shuffle.
9688 assert(WidenedMask.size() == Mask.size() / 2 &&
9689 "Incorrect size of mask after widening the elements!");
9694 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9696 /// This routine just extracts two subvectors, shuffles them independently, and
9697 /// then concatenates them back together. This should work effectively with all
9698 /// AVX vector shuffle types.
9699 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9700 SDValue V2, ArrayRef<int> Mask,
9701 SelectionDAG &DAG) {
9702 assert(VT.getSizeInBits() >= 256 &&
9703 "Only for 256-bit or wider vector shuffles!");
9704 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9705 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9707 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9708 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9710 int NumElements = VT.getVectorNumElements();
9711 int SplitNumElements = NumElements / 2;
9712 MVT ScalarVT = VT.getScalarType();
9713 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9715 // Rather than splitting build-vectors, just build two narrower build
9716 // vectors. This helps shuffling with splats and zeros.
9717 auto SplitVector = [&](SDValue V) {
9718 while (V.getOpcode() == ISD::BITCAST)
9719 V = V->getOperand(0);
9721 MVT OrigVT = V.getSimpleValueType();
9722 int OrigNumElements = OrigVT.getVectorNumElements();
9723 int OrigSplitNumElements = OrigNumElements / 2;
9724 MVT OrigScalarVT = OrigVT.getScalarType();
9725 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9729 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9731 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9732 DAG.getIntPtrConstant(0, DL));
9733 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9734 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9737 SmallVector<SDValue, 16> LoOps, HiOps;
9738 for (int i = 0; i < OrigSplitNumElements; ++i) {
9739 LoOps.push_back(BV->getOperand(i));
9740 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9742 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9743 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9745 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9746 DAG.getBitcast(SplitVT, HiV));
9749 SDValue LoV1, HiV1, LoV2, HiV2;
9750 std::tie(LoV1, HiV1) = SplitVector(V1);
9751 std::tie(LoV2, HiV2) = SplitVector(V2);
9753 // Now create two 4-way blends of these half-width vectors.
9754 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9755 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9756 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9757 for (int i = 0; i < SplitNumElements; ++i) {
9758 int M = HalfMask[i];
9759 if (M >= NumElements) {
9760 if (M >= NumElements + SplitNumElements)
9764 V2BlendMask.push_back(M - NumElements);
9765 V1BlendMask.push_back(-1);
9766 BlendMask.push_back(SplitNumElements + i);
9767 } else if (M >= 0) {
9768 if (M >= SplitNumElements)
9772 V2BlendMask.push_back(-1);
9773 V1BlendMask.push_back(M);
9774 BlendMask.push_back(i);
9776 V2BlendMask.push_back(-1);
9777 V1BlendMask.push_back(-1);
9778 BlendMask.push_back(-1);
9782 // Because the lowering happens after all combining takes place, we need to
9783 // manually combine these blend masks as much as possible so that we create
9784 // a minimal number of high-level vector shuffle nodes.
9786 // First try just blending the halves of V1 or V2.
9787 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9788 return DAG.getUNDEF(SplitVT);
9789 if (!UseLoV2 && !UseHiV2)
9790 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9791 if (!UseLoV1 && !UseHiV1)
9792 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9794 SDValue V1Blend, V2Blend;
9795 if (UseLoV1 && UseHiV1) {
9797 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9799 // We only use half of V1 so map the usage down into the final blend mask.
9800 V1Blend = UseLoV1 ? LoV1 : HiV1;
9801 for (int i = 0; i < SplitNumElements; ++i)
9802 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9803 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9805 if (UseLoV2 && UseHiV2) {
9807 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9809 // We only use half of V2 so map the usage down into the final blend mask.
9810 V2Blend = UseLoV2 ? LoV2 : HiV2;
9811 for (int i = 0; i < SplitNumElements; ++i)
9812 if (BlendMask[i] >= SplitNumElements)
9813 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9815 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9817 SDValue Lo = HalfBlend(LoMask);
9818 SDValue Hi = HalfBlend(HiMask);
9819 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9822 /// \brief Either split a vector in halves or decompose the shuffles and the
9825 /// This is provided as a good fallback for many lowerings of non-single-input
9826 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9827 /// between splitting the shuffle into 128-bit components and stitching those
9828 /// back together vs. extracting the single-input shuffles and blending those
9830 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9831 SDValue V2, ArrayRef<int> Mask,
9832 SelectionDAG &DAG) {
9833 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9834 "lower single-input shuffles as it "
9835 "could then recurse on itself.");
9836 int Size = Mask.size();
9838 // If this can be modeled as a broadcast of two elements followed by a blend,
9839 // prefer that lowering. This is especially important because broadcasts can
9840 // often fold with memory operands.
9841 auto DoBothBroadcast = [&] {
9842 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9845 if (V2BroadcastIdx == -1)
9846 V2BroadcastIdx = M - Size;
9847 else if (M - Size != V2BroadcastIdx)
9849 } else if (M >= 0) {
9850 if (V1BroadcastIdx == -1)
9852 else if (M != V1BroadcastIdx)
9857 if (DoBothBroadcast())
9858 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9861 // If the inputs all stem from a single 128-bit lane of each input, then we
9862 // split them rather than blending because the split will decompose to
9863 // unusually few instructions.
9864 int LaneCount = VT.getSizeInBits() / 128;
9865 int LaneSize = Size / LaneCount;
9866 SmallBitVector LaneInputs[2];
9867 LaneInputs[0].resize(LaneCount, false);
9868 LaneInputs[1].resize(LaneCount, false);
9869 for (int i = 0; i < Size; ++i)
9871 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9872 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9873 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9875 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9876 // that the decomposed single-input shuffles don't end up here.
9877 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9880 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9881 /// a permutation and blend of those lanes.
9883 /// This essentially blends the out-of-lane inputs to each lane into the lane
9884 /// from a permuted copy of the vector. This lowering strategy results in four
9885 /// instructions in the worst case for a single-input cross lane shuffle which
9886 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9887 /// of. Special cases for each particular shuffle pattern should be handled
9888 /// prior to trying this lowering.
9889 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9890 SDValue V1, SDValue V2,
9892 SelectionDAG &DAG) {
9893 // FIXME: This should probably be generalized for 512-bit vectors as well.
9894 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9895 int LaneSize = Mask.size() / 2;
9897 // If there are only inputs from one 128-bit lane, splitting will in fact be
9898 // less expensive. The flags track whether the given lane contains an element
9899 // that crosses to another lane.
9900 bool LaneCrossing[2] = {false, false};
9901 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9902 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9903 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9904 if (!LaneCrossing[0] || !LaneCrossing[1])
9905 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9907 if (isSingleInputShuffleMask(Mask)) {
9908 SmallVector<int, 32> FlippedBlendMask;
9909 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9910 FlippedBlendMask.push_back(
9911 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9913 : Mask[i] % LaneSize +
9914 (i / LaneSize) * LaneSize + Size));
9916 // Flip the vector, and blend the results which should now be in-lane. The
9917 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9918 // 5 for the high source. The value 3 selects the high half of source 2 and
9919 // the value 2 selects the low half of source 2. We only use source 2 to
9920 // allow folding it into a memory operand.
9921 unsigned PERMMask = 3 | 2 << 4;
9922 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9923 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9924 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9927 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9928 // will be handled by the above logic and a blend of the results, much like
9929 // other patterns in AVX.
9930 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9933 /// \brief Handle lowering 2-lane 128-bit shuffles.
9934 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9935 SDValue V2, ArrayRef<int> Mask,
9936 const X86Subtarget *Subtarget,
9937 SelectionDAG &DAG) {
9938 // TODO: If minimizing size and one of the inputs is a zero vector and the
9939 // the zero vector has only one use, we could use a VPERM2X128 to save the
9940 // instruction bytes needed to explicitly generate the zero vector.
9942 // Blends are faster and handle all the non-lane-crossing cases.
9943 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9947 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9948 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9950 // If either input operand is a zero vector, use VPERM2X128 because its mask
9951 // allows us to replace the zero input with an implicit zero.
9952 if (!IsV1Zero && !IsV2Zero) {
9953 // Check for patterns which can be matched with a single insert of a 128-bit
9955 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9956 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9957 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9958 VT.getVectorNumElements() / 2);
9959 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9960 DAG.getIntPtrConstant(0, DL));
9961 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9962 OnlyUsesV1 ? V1 : V2,
9963 DAG.getIntPtrConstant(0, DL));
9964 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9968 // Otherwise form a 128-bit permutation. After accounting for undefs,
9969 // convert the 64-bit shuffle mask selection values into 128-bit
9970 // selection bits by dividing the indexes by 2 and shifting into positions
9971 // defined by a vperm2*128 instruction's immediate control byte.
9973 // The immediate permute control byte looks like this:
9974 // [1:0] - select 128 bits from sources for low half of destination
9976 // [3] - zero low half of destination
9977 // [5:4] - select 128 bits from sources for high half of destination
9979 // [7] - zero high half of destination
9981 int MaskLO = Mask[0];
9982 if (MaskLO == SM_SentinelUndef)
9983 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9985 int MaskHI = Mask[2];
9986 if (MaskHI == SM_SentinelUndef)
9987 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9989 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9991 // If either input is a zero vector, replace it with an undef input.
9992 // Shuffle mask values < 4 are selecting elements of V1.
9993 // Shuffle mask values >= 4 are selecting elements of V2.
9994 // Adjust each half of the permute mask by clearing the half that was
9995 // selecting the zero vector and setting the zero mask bit.
9997 V1 = DAG.getUNDEF(VT);
9999 PermMask = (PermMask & 0xf0) | 0x08;
10001 PermMask = (PermMask & 0x0f) | 0x80;
10004 V2 = DAG.getUNDEF(VT);
10006 PermMask = (PermMask & 0xf0) | 0x08;
10008 PermMask = (PermMask & 0x0f) | 0x80;
10011 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10012 DAG.getConstant(PermMask, DL, MVT::i8));
10015 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10016 /// shuffling each lane.
10018 /// This will only succeed when the result of fixing the 128-bit lanes results
10019 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10020 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10021 /// the lane crosses early and then use simpler shuffles within each lane.
10023 /// FIXME: It might be worthwhile at some point to support this without
10024 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10025 /// in x86 only floating point has interesting non-repeating shuffles, and even
10026 /// those are still *marginally* more expensive.
10027 static SDValue lowerVectorShuffleByMerging128BitLanes(
10028 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10029 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10030 assert(!isSingleInputShuffleMask(Mask) &&
10031 "This is only useful with multiple inputs.");
10033 int Size = Mask.size();
10034 int LaneSize = 128 / VT.getScalarSizeInBits();
10035 int NumLanes = Size / LaneSize;
10036 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10038 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10039 // check whether the in-128-bit lane shuffles share a repeating pattern.
10040 SmallVector<int, 4> Lanes;
10041 Lanes.resize(NumLanes, -1);
10042 SmallVector<int, 4> InLaneMask;
10043 InLaneMask.resize(LaneSize, -1);
10044 for (int i = 0; i < Size; ++i) {
10048 int j = i / LaneSize;
10050 if (Lanes[j] < 0) {
10051 // First entry we've seen for this lane.
10052 Lanes[j] = Mask[i] / LaneSize;
10053 } else if (Lanes[j] != Mask[i] / LaneSize) {
10054 // This doesn't match the lane selected previously!
10058 // Check that within each lane we have a consistent shuffle mask.
10059 int k = i % LaneSize;
10060 if (InLaneMask[k] < 0) {
10061 InLaneMask[k] = Mask[i] % LaneSize;
10062 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10063 // This doesn't fit a repeating in-lane mask.
10068 // First shuffle the lanes into place.
10069 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10070 VT.getSizeInBits() / 64);
10071 SmallVector<int, 8> LaneMask;
10072 LaneMask.resize(NumLanes * 2, -1);
10073 for (int i = 0; i < NumLanes; ++i)
10074 if (Lanes[i] >= 0) {
10075 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10076 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10079 V1 = DAG.getBitcast(LaneVT, V1);
10080 V2 = DAG.getBitcast(LaneVT, V2);
10081 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10083 // Cast it back to the type we actually want.
10084 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10086 // Now do a simple shuffle that isn't lane crossing.
10087 SmallVector<int, 8> NewMask;
10088 NewMask.resize(Size, -1);
10089 for (int i = 0; i < Size; ++i)
10091 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10092 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10093 "Must not introduce lane crosses at this point!");
10095 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10098 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10101 /// This returns true if the elements from a particular input are already in the
10102 /// slot required by the given mask and require no permutation.
10103 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10104 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10105 int Size = Mask.size();
10106 for (int i = 0; i < Size; ++i)
10107 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10113 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10114 ArrayRef<int> Mask, SDValue V1,
10115 SDValue V2, SelectionDAG &DAG) {
10117 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10118 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10119 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10120 int NumElts = VT.getVectorNumElements();
10121 bool ShufpdMask = true;
10122 bool CommutableMask = true;
10123 unsigned Immediate = 0;
10124 for (int i = 0; i < NumElts; ++i) {
10127 int Val = (i & 6) + NumElts * (i & 1);
10128 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10129 if (Mask[i] < Val || Mask[i] > Val + 1)
10130 ShufpdMask = false;
10131 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10132 CommutableMask = false;
10133 Immediate |= (Mask[i] % 2) << i;
10136 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10137 DAG.getConstant(Immediate, DL, MVT::i8));
10138 if (CommutableMask)
10139 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10140 DAG.getConstant(Immediate, DL, MVT::i8));
10144 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10146 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10147 /// isn't available.
10148 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10149 const X86Subtarget *Subtarget,
10150 SelectionDAG &DAG) {
10152 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10153 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10154 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10155 ArrayRef<int> Mask = SVOp->getMask();
10156 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10158 SmallVector<int, 4> WidenedMask;
10159 if (canWidenShuffleElements(Mask, WidenedMask))
10160 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10163 if (isSingleInputShuffleMask(Mask)) {
10164 // Check for being able to broadcast a single element.
10165 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10166 Mask, Subtarget, DAG))
10169 // Use low duplicate instructions for masks that match their pattern.
10170 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10171 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10173 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10174 // Non-half-crossing single input shuffles can be lowerid with an
10175 // interleaved permutation.
10176 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10177 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10178 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10179 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10182 // With AVX2 we have direct support for this permutation.
10183 if (Subtarget->hasAVX2())
10184 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10185 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10187 // Otherwise, fall back.
10188 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10192 // X86 has dedicated unpack instructions that can handle specific blend
10193 // operations: UNPCKH and UNPCKL.
10194 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10195 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10196 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10197 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10198 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10199 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10200 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10201 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10203 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10207 // Check if the blend happens to exactly fit that of SHUFPD.
10209 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10212 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10213 // shuffle. However, if we have AVX2 and either inputs are already in place,
10214 // we will be able to shuffle even across lanes the other input in a single
10215 // instruction so skip this pattern.
10216 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10217 isShuffleMaskInputInPlace(1, Mask))))
10218 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10219 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10222 // If we have AVX2 then we always want to lower with a blend because an v4 we
10223 // can fully permute the elements.
10224 if (Subtarget->hasAVX2())
10225 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10228 // Otherwise fall back on generic lowering.
10229 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10232 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10234 /// This routine is only called when we have AVX2 and thus a reasonable
10235 /// instruction set for v4i64 shuffling..
10236 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10237 const X86Subtarget *Subtarget,
10238 SelectionDAG &DAG) {
10240 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10241 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10243 ArrayRef<int> Mask = SVOp->getMask();
10244 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10245 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10247 SmallVector<int, 4> WidenedMask;
10248 if (canWidenShuffleElements(Mask, WidenedMask))
10249 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10252 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10256 // Check for being able to broadcast a single element.
10257 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10258 Mask, Subtarget, DAG))
10261 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10262 // use lower latency instructions that will operate on both 128-bit lanes.
10263 SmallVector<int, 2> RepeatedMask;
10264 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10265 if (isSingleInputShuffleMask(Mask)) {
10266 int PSHUFDMask[] = {-1, -1, -1, -1};
10267 for (int i = 0; i < 2; ++i)
10268 if (RepeatedMask[i] >= 0) {
10269 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10270 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10272 return DAG.getBitcast(
10274 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10275 DAG.getBitcast(MVT::v8i32, V1),
10276 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10280 // AVX2 provides a direct instruction for permuting a single input across
10282 if (isSingleInputShuffleMask(Mask))
10283 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10284 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10286 // Try to use shift instructions.
10287 if (SDValue Shift =
10288 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10291 // Use dedicated unpack instructions for masks that match their pattern.
10292 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10293 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10294 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10295 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10296 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10297 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10298 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10299 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10301 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10302 // shuffle. However, if we have AVX2 and either inputs are already in place,
10303 // we will be able to shuffle even across lanes the other input in a single
10304 // instruction so skip this pattern.
10305 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10306 isShuffleMaskInputInPlace(1, Mask))))
10307 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10308 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10311 // Otherwise fall back on generic blend lowering.
10312 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10316 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10318 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10319 /// isn't available.
10320 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10321 const X86Subtarget *Subtarget,
10322 SelectionDAG &DAG) {
10324 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10325 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10327 ArrayRef<int> Mask = SVOp->getMask();
10328 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10330 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10334 // Check for being able to broadcast a single element.
10335 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10336 Mask, Subtarget, DAG))
10339 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10340 // options to efficiently lower the shuffle.
10341 SmallVector<int, 4> RepeatedMask;
10342 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10343 assert(RepeatedMask.size() == 4 &&
10344 "Repeated masks must be half the mask width!");
10346 // Use even/odd duplicate instructions for masks that match their pattern.
10347 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10348 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10349 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10350 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10352 if (isSingleInputShuffleMask(Mask))
10353 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10354 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10356 // Use dedicated unpack instructions for masks that match their pattern.
10357 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10358 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10359 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10360 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10361 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10362 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10363 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10364 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10366 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10367 // have already handled any direct blends. We also need to squash the
10368 // repeated mask into a simulated v4f32 mask.
10369 for (int i = 0; i < 4; ++i)
10370 if (RepeatedMask[i] >= 8)
10371 RepeatedMask[i] -= 4;
10372 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10375 // If we have a single input shuffle with different shuffle patterns in the
10376 // two 128-bit lanes use the variable mask to VPERMILPS.
10377 if (isSingleInputShuffleMask(Mask)) {
10378 SDValue VPermMask[8];
10379 for (int i = 0; i < 8; ++i)
10380 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10381 : DAG.getConstant(Mask[i], DL, MVT::i32);
10382 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10383 return DAG.getNode(
10384 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10385 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10387 if (Subtarget->hasAVX2())
10388 return DAG.getNode(
10389 X86ISD::VPERMV, DL, MVT::v8f32,
10390 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10391 MVT::v8i32, VPermMask)),
10394 // Otherwise, fall back.
10395 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10399 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10401 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10402 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10405 // If we have AVX2 then we always want to lower with a blend because at v8 we
10406 // can fully permute the elements.
10407 if (Subtarget->hasAVX2())
10408 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10411 // Otherwise fall back on generic lowering.
10412 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10415 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10417 /// This routine is only called when we have AVX2 and thus a reasonable
10418 /// instruction set for v8i32 shuffling..
10419 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10420 const X86Subtarget *Subtarget,
10421 SelectionDAG &DAG) {
10423 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10424 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10426 ArrayRef<int> Mask = SVOp->getMask();
10427 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10428 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10430 // Whenever we can lower this as a zext, that instruction is strictly faster
10431 // than any alternative. It also allows us to fold memory operands into the
10432 // shuffle in many cases.
10433 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10434 Mask, Subtarget, DAG))
10437 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10441 // Check for being able to broadcast a single element.
10442 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10443 Mask, Subtarget, DAG))
10446 // If the shuffle mask is repeated in each 128-bit lane we can use more
10447 // efficient instructions that mirror the shuffles across the two 128-bit
10449 SmallVector<int, 4> RepeatedMask;
10450 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10451 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10452 if (isSingleInputShuffleMask(Mask))
10453 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10454 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10456 // Use dedicated unpack instructions for masks that match their pattern.
10457 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10458 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10459 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10460 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10461 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10462 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10463 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10464 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10467 // Try to use shift instructions.
10468 if (SDValue Shift =
10469 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10472 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10473 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10476 // If the shuffle patterns aren't repeated but it is a single input, directly
10477 // generate a cross-lane VPERMD instruction.
10478 if (isSingleInputShuffleMask(Mask)) {
10479 SDValue VPermMask[8];
10480 for (int i = 0; i < 8; ++i)
10481 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10482 : DAG.getConstant(Mask[i], DL, MVT::i32);
10483 return DAG.getNode(
10484 X86ISD::VPERMV, DL, MVT::v8i32,
10485 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10488 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10490 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10491 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10494 // Otherwise fall back on generic blend lowering.
10495 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10499 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10501 /// This routine is only called when we have AVX2 and thus a reasonable
10502 /// instruction set for v16i16 shuffling..
10503 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10504 const X86Subtarget *Subtarget,
10505 SelectionDAG &DAG) {
10507 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10508 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10509 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10510 ArrayRef<int> Mask = SVOp->getMask();
10511 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10512 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10514 // Whenever we can lower this as a zext, that instruction is strictly faster
10515 // than any alternative. It also allows us to fold memory operands into the
10516 // shuffle in many cases.
10517 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10518 Mask, Subtarget, DAG))
10521 // Check for being able to broadcast a single element.
10522 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10523 Mask, Subtarget, DAG))
10526 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10530 // Use dedicated unpack instructions for masks that match their pattern.
10531 if (isShuffleEquivalent(V1, V2, Mask,
10532 {// First 128-bit lane:
10533 0, 16, 1, 17, 2, 18, 3, 19,
10534 // Second 128-bit lane:
10535 8, 24, 9, 25, 10, 26, 11, 27}))
10536 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10537 if (isShuffleEquivalent(V1, V2, Mask,
10538 {// First 128-bit lane:
10539 4, 20, 5, 21, 6, 22, 7, 23,
10540 // Second 128-bit lane:
10541 12, 28, 13, 29, 14, 30, 15, 31}))
10542 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10544 // Try to use shift instructions.
10545 if (SDValue Shift =
10546 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10549 // Try to use byte rotation instructions.
10550 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10551 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10554 if (isSingleInputShuffleMask(Mask)) {
10555 // There are no generalized cross-lane shuffle operations available on i16
10557 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10558 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10561 SmallVector<int, 8> RepeatedMask;
10562 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10563 // As this is a single-input shuffle, the repeated mask should be
10564 // a strictly valid v8i16 mask that we can pass through to the v8i16
10565 // lowering to handle even the v16 case.
10566 return lowerV8I16GeneralSingleInputVectorShuffle(
10567 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10570 SDValue PSHUFBMask[32];
10571 for (int i = 0; i < 16; ++i) {
10572 if (Mask[i] == -1) {
10573 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10577 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10578 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10579 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10580 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10582 return DAG.getBitcast(MVT::v16i16,
10583 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10584 DAG.getBitcast(MVT::v32i8, V1),
10585 DAG.getNode(ISD::BUILD_VECTOR, DL,
10586 MVT::v32i8, PSHUFBMask)));
10589 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10591 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10592 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10595 // Otherwise fall back on generic lowering.
10596 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10599 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10601 /// This routine is only called when we have AVX2 and thus a reasonable
10602 /// instruction set for v32i8 shuffling..
10603 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10604 const X86Subtarget *Subtarget,
10605 SelectionDAG &DAG) {
10607 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10608 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10610 ArrayRef<int> Mask = SVOp->getMask();
10611 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10612 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10614 // Whenever we can lower this as a zext, that instruction is strictly faster
10615 // than any alternative. It also allows us to fold memory operands into the
10616 // shuffle in many cases.
10617 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10618 Mask, Subtarget, DAG))
10621 // Check for being able to broadcast a single element.
10622 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10623 Mask, Subtarget, DAG))
10626 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10630 // Use dedicated unpack instructions for masks that match their pattern.
10631 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10633 if (isShuffleEquivalent(
10635 {// First 128-bit lane:
10636 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10637 // Second 128-bit lane:
10638 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10639 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10640 if (isShuffleEquivalent(
10642 {// First 128-bit lane:
10643 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10644 // Second 128-bit lane:
10645 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10646 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10648 // Try to use shift instructions.
10649 if (SDValue Shift =
10650 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10653 // Try to use byte rotation instructions.
10654 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10655 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10658 if (isSingleInputShuffleMask(Mask)) {
10659 // There are no generalized cross-lane shuffle operations available on i8
10661 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10662 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10665 SDValue PSHUFBMask[32];
10666 for (int i = 0; i < 32; ++i)
10669 ? DAG.getUNDEF(MVT::i8)
10670 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10673 return DAG.getNode(
10674 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10675 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10678 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10680 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10681 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10684 // Otherwise fall back on generic lowering.
10685 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10688 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10690 /// This routine either breaks down the specific type of a 256-bit x86 vector
10691 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10692 /// together based on the available instructions.
10693 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10694 MVT VT, const X86Subtarget *Subtarget,
10695 SelectionDAG &DAG) {
10697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10698 ArrayRef<int> Mask = SVOp->getMask();
10700 // If we have a single input to the zero element, insert that into V1 if we
10701 // can do so cheaply.
10702 int NumElts = VT.getVectorNumElements();
10703 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10704 return M >= NumElts;
10707 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10708 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10709 DL, VT, V1, V2, Mask, Subtarget, DAG))
10712 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10713 // can check for those subtargets here and avoid much of the subtarget
10714 // querying in the per-vector-type lowering routines. With AVX1 we have
10715 // essentially *zero* ability to manipulate a 256-bit vector with integer
10716 // types. Since we'll use floating point types there eventually, just
10717 // immediately cast everything to a float and operate entirely in that domain.
10718 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10719 int ElementBits = VT.getScalarSizeInBits();
10720 if (ElementBits < 32)
10721 // No floating point type available, decompose into 128-bit vectors.
10722 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10724 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10725 VT.getVectorNumElements());
10726 V1 = DAG.getBitcast(FpVT, V1);
10727 V2 = DAG.getBitcast(FpVT, V2);
10728 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10731 switch (VT.SimpleTy) {
10733 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10735 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10737 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10739 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10741 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10743 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10746 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10750 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10751 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10752 ArrayRef<int> Mask,
10753 SDValue V1, SDValue V2,
10754 SelectionDAG &DAG) {
10755 assert(VT.getScalarSizeInBits() == 64 &&
10756 "Unexpected element type size for 128bit shuffle.");
10758 // To handle 256 bit vector requires VLX and most probably
10759 // function lowerV2X128VectorShuffle() is better solution.
10760 assert(VT.getSizeInBits() == 512 &&
10761 "Unexpected vector size for 128bit shuffle.");
10763 SmallVector<int, 4> WidenedMask;
10764 if (!canWidenShuffleElements(Mask, WidenedMask))
10767 // Form a 128-bit permutation.
10768 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10769 // bits defined by a vshuf64x2 instruction's immediate control byte.
10770 unsigned PermMask = 0, Imm = 0;
10771 unsigned ControlBitsNum = WidenedMask.size() / 2;
10773 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10774 if (WidenedMask[i] == SM_SentinelZero)
10777 // Use first element in place of undef mask.
10778 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10779 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10782 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10783 DAG.getConstant(PermMask, DL, MVT::i8));
10786 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10787 ArrayRef<int> Mask, SDValue V1,
10788 SDValue V2, SelectionDAG &DAG) {
10790 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10792 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10793 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10795 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10796 if (isSingleInputShuffleMask(Mask))
10797 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10799 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10802 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10803 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10804 const X86Subtarget *Subtarget,
10805 SelectionDAG &DAG) {
10807 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10808 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10809 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10810 ArrayRef<int> Mask = SVOp->getMask();
10811 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10813 if (SDValue Shuf128 =
10814 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10817 if (SDValue Unpck =
10818 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10821 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10824 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10825 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10826 const X86Subtarget *Subtarget,
10827 SelectionDAG &DAG) {
10829 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10830 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10832 ArrayRef<int> Mask = SVOp->getMask();
10833 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10835 if (SDValue Unpck =
10836 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10839 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10842 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10843 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10844 const X86Subtarget *Subtarget,
10845 SelectionDAG &DAG) {
10847 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10848 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10850 ArrayRef<int> Mask = SVOp->getMask();
10851 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10853 if (SDValue Shuf128 =
10854 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10857 if (SDValue Unpck =
10858 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10861 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10864 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10865 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10866 const X86Subtarget *Subtarget,
10867 SelectionDAG &DAG) {
10869 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10870 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10871 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10872 ArrayRef<int> Mask = SVOp->getMask();
10873 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10875 if (SDValue Unpck =
10876 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10879 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10882 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10883 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10884 const X86Subtarget *Subtarget,
10885 SelectionDAG &DAG) {
10887 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10888 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10889 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10890 ArrayRef<int> Mask = SVOp->getMask();
10891 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10892 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10894 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10897 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10898 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10899 const X86Subtarget *Subtarget,
10900 SelectionDAG &DAG) {
10902 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10903 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10904 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10905 ArrayRef<int> Mask = SVOp->getMask();
10906 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10907 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10909 // FIXME: Implement direct support for this type!
10910 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10913 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10915 /// This routine either breaks down the specific type of a 512-bit x86 vector
10916 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10917 /// together based on the available instructions.
10918 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10919 MVT VT, const X86Subtarget *Subtarget,
10920 SelectionDAG &DAG) {
10922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10923 ArrayRef<int> Mask = SVOp->getMask();
10924 assert(Subtarget->hasAVX512() &&
10925 "Cannot lower 512-bit vectors w/ basic ISA!");
10927 // Check for being able to broadcast a single element.
10928 if (SDValue Broadcast =
10929 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10932 // Dispatch to each element type for lowering. If we don't have supprot for
10933 // specific element type shuffles at 512 bits, immediately split them and
10934 // lower them. Each lowering routine of a given type is allowed to assume that
10935 // the requisite ISA extensions for that element type are available.
10936 switch (VT.SimpleTy) {
10938 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10940 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10942 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10944 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10946 if (Subtarget->hasBWI())
10947 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10950 if (Subtarget->hasBWI())
10951 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10955 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10958 // Otherwise fall back on splitting.
10959 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10962 // Lower vXi1 vector shuffles.
10963 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10964 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10965 // vector, shuffle and then truncate it back.
10966 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10967 MVT VT, const X86Subtarget *Subtarget,
10968 SelectionDAG &DAG) {
10970 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10971 ArrayRef<int> Mask = SVOp->getMask();
10972 assert(Subtarget->hasAVX512() &&
10973 "Cannot lower 512-bit vectors w/o basic ISA!");
10975 switch (VT.SimpleTy) {
10977 assert(false && "Expected a vector of i1 elements");
10980 ExtVT = MVT::v2i64;
10983 ExtVT = MVT::v4i32;
10986 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10989 ExtVT = MVT::v16i32;
10992 ExtVT = MVT::v32i16;
10995 ExtVT = MVT::v64i8;
10999 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11000 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11001 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11002 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11004 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11007 V2 = DAG.getUNDEF(ExtVT);
11008 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11009 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11010 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11011 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11013 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11014 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11015 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11017 /// \brief Top-level lowering for x86 vector shuffles.
11019 /// This handles decomposition, canonicalization, and lowering of all x86
11020 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11021 /// above in helper routines. The canonicalization attempts to widen shuffles
11022 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11023 /// s.t. only one of the two inputs needs to be tested, etc.
11024 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11025 SelectionDAG &DAG) {
11026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11027 ArrayRef<int> Mask = SVOp->getMask();
11028 SDValue V1 = Op.getOperand(0);
11029 SDValue V2 = Op.getOperand(1);
11030 MVT VT = Op.getSimpleValueType();
11031 int NumElements = VT.getVectorNumElements();
11033 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
11035 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11036 "Can't lower MMX shuffles");
11038 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11039 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11040 if (V1IsUndef && V2IsUndef)
11041 return DAG.getUNDEF(VT);
11043 // When we create a shuffle node we put the UNDEF node to second operand,
11044 // but in some cases the first operand may be transformed to UNDEF.
11045 // In this case we should just commute the node.
11047 return DAG.getCommutedVectorShuffle(*SVOp);
11049 // Check for non-undef masks pointing at an undef vector and make the masks
11050 // undef as well. This makes it easier to match the shuffle based solely on
11054 if (M >= NumElements) {
11055 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11056 for (int &M : NewMask)
11057 if (M >= NumElements)
11059 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11062 // We actually see shuffles that are entirely re-arrangements of a set of
11063 // zero inputs. This mostly happens while decomposing complex shuffles into
11064 // simple ones. Directly lower these as a buildvector of zeros.
11065 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11066 if (Zeroable.all())
11067 return getZeroVector(VT, Subtarget, DAG, dl);
11069 // Try to collapse shuffles into using a vector type with fewer elements but
11070 // wider element types. We cap this to not form integers or floating point
11071 // elements wider than 64 bits, but it might be interesting to form i128
11072 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11073 SmallVector<int, 16> WidenedMask;
11074 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11075 canWidenShuffleElements(Mask, WidenedMask)) {
11076 MVT NewEltVT = VT.isFloatingPoint()
11077 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11078 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11079 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11080 // Make sure that the new vector type is legal. For example, v2f64 isn't
11082 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11083 V1 = DAG.getBitcast(NewVT, V1);
11084 V2 = DAG.getBitcast(NewVT, V2);
11085 return DAG.getBitcast(
11086 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11090 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11091 for (int M : SVOp->getMask())
11093 ++NumUndefElements;
11094 else if (M < NumElements)
11099 // Commute the shuffle as needed such that more elements come from V1 than
11100 // V2. This allows us to match the shuffle pattern strictly on how many
11101 // elements come from V1 without handling the symmetric cases.
11102 if (NumV2Elements > NumV1Elements)
11103 return DAG.getCommutedVectorShuffle(*SVOp);
11105 // When the number of V1 and V2 elements are the same, try to minimize the
11106 // number of uses of V2 in the low half of the vector. When that is tied,
11107 // ensure that the sum of indices for V1 is equal to or lower than the sum
11108 // indices for V2. When those are equal, try to ensure that the number of odd
11109 // indices for V1 is lower than the number of odd indices for V2.
11110 if (NumV1Elements == NumV2Elements) {
11111 int LowV1Elements = 0, LowV2Elements = 0;
11112 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11113 if (M >= NumElements)
11117 if (LowV2Elements > LowV1Elements) {
11118 return DAG.getCommutedVectorShuffle(*SVOp);
11119 } else if (LowV2Elements == LowV1Elements) {
11120 int SumV1Indices = 0, SumV2Indices = 0;
11121 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11122 if (SVOp->getMask()[i] >= NumElements)
11124 else if (SVOp->getMask()[i] >= 0)
11126 if (SumV2Indices < SumV1Indices) {
11127 return DAG.getCommutedVectorShuffle(*SVOp);
11128 } else if (SumV2Indices == SumV1Indices) {
11129 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11130 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11131 if (SVOp->getMask()[i] >= NumElements)
11132 NumV2OddIndices += i % 2;
11133 else if (SVOp->getMask()[i] >= 0)
11134 NumV1OddIndices += i % 2;
11135 if (NumV2OddIndices < NumV1OddIndices)
11136 return DAG.getCommutedVectorShuffle(*SVOp);
11141 // For each vector width, delegate to a specialized lowering routine.
11142 if (VT.getSizeInBits() == 128)
11143 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11145 if (VT.getSizeInBits() == 256)
11146 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11148 if (VT.getSizeInBits() == 512)
11149 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11152 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11153 llvm_unreachable("Unimplemented!");
11156 // This function assumes its argument is a BUILD_VECTOR of constants or
11157 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11159 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11160 unsigned &MaskValue) {
11162 unsigned NumElems = BuildVector->getNumOperands();
11164 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11165 // We don't handle the >2 lanes case right now.
11166 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11170 unsigned NumElemsInLane = NumElems / NumLanes;
11172 // Blend for v16i16 should be symmetric for the both lanes.
11173 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11174 SDValue EltCond = BuildVector->getOperand(i);
11175 SDValue SndLaneEltCond =
11176 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11178 int Lane1Cond = -1, Lane2Cond = -1;
11179 if (isa<ConstantSDNode>(EltCond))
11180 Lane1Cond = !isZero(EltCond);
11181 if (isa<ConstantSDNode>(SndLaneEltCond))
11182 Lane2Cond = !isZero(SndLaneEltCond);
11184 unsigned LaneMask = 0;
11185 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11186 // Lane1Cond != 0, means we want the first argument.
11187 // Lane1Cond == 0, means we want the second argument.
11188 // The encoding of this argument is 0 for the first argument, 1
11189 // for the second. Therefore, invert the condition.
11190 LaneMask = !Lane1Cond << i;
11191 else if (Lane1Cond < 0)
11192 LaneMask = !Lane2Cond << i;
11196 MaskValue |= LaneMask;
11198 MaskValue |= LaneMask << NumElemsInLane;
11203 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11204 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11205 const X86Subtarget *Subtarget,
11206 SelectionDAG &DAG) {
11207 SDValue Cond = Op.getOperand(0);
11208 SDValue LHS = Op.getOperand(1);
11209 SDValue RHS = Op.getOperand(2);
11211 MVT VT = Op.getSimpleValueType();
11213 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11215 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11217 // Only non-legal VSELECTs reach this lowering, convert those into generic
11218 // shuffles and re-use the shuffle lowering path for blends.
11219 SmallVector<int, 32> Mask;
11220 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11221 SDValue CondElt = CondBV->getOperand(i);
11223 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11225 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11228 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11229 // A vselect where all conditions and data are constants can be optimized into
11230 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11231 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11232 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11233 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11236 // Try to lower this to a blend-style vector shuffle. This can handle all
11237 // constant condition cases.
11238 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11241 // Variable blends are only legal from SSE4.1 onward.
11242 if (!Subtarget->hasSSE41())
11245 // Only some types will be legal on some subtargets. If we can emit a legal
11246 // VSELECT-matching blend, return Op, and but if we need to expand, return
11248 switch (Op.getSimpleValueType().SimpleTy) {
11250 // Most of the vector types have blends past SSE4.1.
11254 // The byte blends for AVX vectors were introduced only in AVX2.
11255 if (Subtarget->hasAVX2())
11262 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11263 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11266 // FIXME: We should custom lower this by fixing the condition and using i8
11272 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11273 MVT VT = Op.getSimpleValueType();
11276 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11279 if (VT.getSizeInBits() == 8) {
11280 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11281 Op.getOperand(0), Op.getOperand(1));
11282 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11283 DAG.getValueType(VT));
11284 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11287 if (VT.getSizeInBits() == 16) {
11288 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11289 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11291 return DAG.getNode(
11292 ISD::TRUNCATE, dl, MVT::i16,
11293 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11294 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11295 Op.getOperand(1)));
11296 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11297 Op.getOperand(0), Op.getOperand(1));
11298 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11299 DAG.getValueType(VT));
11300 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11303 if (VT == MVT::f32) {
11304 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11305 // the result back to FR32 register. It's only worth matching if the
11306 // result has a single use which is a store or a bitcast to i32. And in
11307 // the case of a store, it's not worth it if the index is a constant 0,
11308 // because a MOVSSmr can be used instead, which is smaller and faster.
11309 if (!Op.hasOneUse())
11311 SDNode *User = *Op.getNode()->use_begin();
11312 if ((User->getOpcode() != ISD::STORE ||
11313 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11314 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11315 (User->getOpcode() != ISD::BITCAST ||
11316 User->getValueType(0) != MVT::i32))
11318 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11319 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11321 return DAG.getBitcast(MVT::f32, Extract);
11324 if (VT == MVT::i32 || VT == MVT::i64) {
11325 // ExtractPS/pextrq works with constant index.
11326 if (isa<ConstantSDNode>(Op.getOperand(1)))
11332 /// Extract one bit from mask vector, like v16i1 or v8i1.
11333 /// AVX-512 feature.
11335 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11336 SDValue Vec = Op.getOperand(0);
11338 MVT VecVT = Vec.getSimpleValueType();
11339 SDValue Idx = Op.getOperand(1);
11340 MVT EltVT = Op.getSimpleValueType();
11342 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11343 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11344 "Unexpected vector type in ExtractBitFromMaskVector");
11346 // variable index can't be handled in mask registers,
11347 // extend vector to VR512
11348 if (!isa<ConstantSDNode>(Idx)) {
11349 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11350 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11351 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11352 ExtVT.getVectorElementType(), Ext, Idx);
11353 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11356 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11357 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11358 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11359 rc = getRegClassFor(MVT::v16i1);
11360 unsigned MaxSift = rc->getSize()*8 - 1;
11361 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11362 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11363 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11364 DAG.getConstant(MaxSift, dl, MVT::i8));
11365 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11366 DAG.getIntPtrConstant(0, dl));
11370 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11371 SelectionDAG &DAG) const {
11373 SDValue Vec = Op.getOperand(0);
11374 MVT VecVT = Vec.getSimpleValueType();
11375 SDValue Idx = Op.getOperand(1);
11377 if (Op.getSimpleValueType() == MVT::i1)
11378 return ExtractBitFromMaskVector(Op, DAG);
11380 if (!isa<ConstantSDNode>(Idx)) {
11381 if (VecVT.is512BitVector() ||
11382 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11383 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11386 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11387 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11388 MaskEltVT.getSizeInBits());
11390 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11391 auto PtrVT = getPointerTy(DAG.getDataLayout());
11392 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11393 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11394 DAG.getConstant(0, dl, PtrVT));
11395 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11396 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11397 DAG.getConstant(0, dl, PtrVT));
11402 // If this is a 256-bit vector result, first extract the 128-bit vector and
11403 // then extract the element from the 128-bit vector.
11404 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11406 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11407 // Get the 128-bit vector.
11408 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11409 MVT EltVT = VecVT.getVectorElementType();
11411 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11413 //if (IdxVal >= NumElems/2)
11414 // IdxVal -= NumElems/2;
11415 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11416 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11417 DAG.getConstant(IdxVal, dl, MVT::i32));
11420 assert(VecVT.is128BitVector() && "Unexpected vector length");
11422 if (Subtarget->hasSSE41())
11423 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11426 MVT VT = Op.getSimpleValueType();
11427 // TODO: handle v16i8.
11428 if (VT.getSizeInBits() == 16) {
11429 SDValue Vec = Op.getOperand(0);
11430 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11432 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11434 DAG.getBitcast(MVT::v4i32, Vec),
11435 Op.getOperand(1)));
11436 // Transform it so it match pextrw which produces a 32-bit result.
11437 MVT EltVT = MVT::i32;
11438 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11439 Op.getOperand(0), Op.getOperand(1));
11440 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11441 DAG.getValueType(VT));
11442 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11445 if (VT.getSizeInBits() == 32) {
11446 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11450 // SHUFPS the element to the lowest double word, then movss.
11451 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11452 MVT VVT = Op.getOperand(0).getSimpleValueType();
11453 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11454 DAG.getUNDEF(VVT), Mask);
11455 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11456 DAG.getIntPtrConstant(0, dl));
11459 if (VT.getSizeInBits() == 64) {
11460 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11461 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11462 // to match extract_elt for f64.
11463 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11467 // UNPCKHPD the element to the lowest double word, then movsd.
11468 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11469 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11470 int Mask[2] = { 1, -1 };
11471 MVT VVT = Op.getOperand(0).getSimpleValueType();
11472 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11473 DAG.getUNDEF(VVT), Mask);
11474 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11475 DAG.getIntPtrConstant(0, dl));
11481 /// Insert one bit to mask vector, like v16i1 or v8i1.
11482 /// AVX-512 feature.
11484 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11486 SDValue Vec = Op.getOperand(0);
11487 SDValue Elt = Op.getOperand(1);
11488 SDValue Idx = Op.getOperand(2);
11489 MVT VecVT = Vec.getSimpleValueType();
11491 if (!isa<ConstantSDNode>(Idx)) {
11492 // Non constant index. Extend source and destination,
11493 // insert element and then truncate the result.
11494 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11495 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11496 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11497 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11498 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11499 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11502 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11503 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11505 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11506 DAG.getConstant(IdxVal, dl, MVT::i8));
11507 if (Vec.getOpcode() == ISD::UNDEF)
11509 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11512 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11513 SelectionDAG &DAG) const {
11514 MVT VT = Op.getSimpleValueType();
11515 MVT EltVT = VT.getVectorElementType();
11517 if (EltVT == MVT::i1)
11518 return InsertBitToMaskVector(Op, DAG);
11521 SDValue N0 = Op.getOperand(0);
11522 SDValue N1 = Op.getOperand(1);
11523 SDValue N2 = Op.getOperand(2);
11524 if (!isa<ConstantSDNode>(N2))
11526 auto *N2C = cast<ConstantSDNode>(N2);
11527 unsigned IdxVal = N2C->getZExtValue();
11529 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11530 // into that, and then insert the subvector back into the result.
11531 if (VT.is256BitVector() || VT.is512BitVector()) {
11532 // With a 256-bit vector, we can insert into the zero element efficiently
11533 // using a blend if we have AVX or AVX2 and the right data type.
11534 if (VT.is256BitVector() && IdxVal == 0) {
11535 // TODO: It is worthwhile to cast integer to floating point and back
11536 // and incur a domain crossing penalty if that's what we'll end up
11537 // doing anyway after extracting to a 128-bit vector.
11538 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11539 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11540 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11541 N2 = DAG.getIntPtrConstant(1, dl);
11542 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11546 // Get the desired 128-bit vector chunk.
11547 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11549 // Insert the element into the desired chunk.
11550 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11551 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11553 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11554 DAG.getConstant(IdxIn128, dl, MVT::i32));
11556 // Insert the changed part back into the bigger vector
11557 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11559 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11561 if (Subtarget->hasSSE41()) {
11562 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11564 if (VT == MVT::v8i16) {
11565 Opc = X86ISD::PINSRW;
11567 assert(VT == MVT::v16i8);
11568 Opc = X86ISD::PINSRB;
11571 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11573 if (N1.getValueType() != MVT::i32)
11574 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11575 if (N2.getValueType() != MVT::i32)
11576 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11577 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11580 if (EltVT == MVT::f32) {
11581 // Bits [7:6] of the constant are the source select. This will always be
11582 // zero here. The DAG Combiner may combine an extract_elt index into
11583 // these bits. For example (insert (extract, 3), 2) could be matched by
11584 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11585 // Bits [5:4] of the constant are the destination select. This is the
11586 // value of the incoming immediate.
11587 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11588 // combine either bitwise AND or insert of float 0.0 to set these bits.
11590 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11591 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11592 // If this is an insertion of 32-bits into the low 32-bits of
11593 // a vector, we prefer to generate a blend with immediate rather
11594 // than an insertps. Blends are simpler operations in hardware and so
11595 // will always have equal or better performance than insertps.
11596 // But if optimizing for size and there's a load folding opportunity,
11597 // generate insertps because blendps does not have a 32-bit memory
11599 N2 = DAG.getIntPtrConstant(1, dl);
11600 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11601 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11603 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11604 // Create this as a scalar to vector..
11605 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11606 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11609 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11610 // PINSR* works with constant index.
11615 if (EltVT == MVT::i8)
11618 if (EltVT.getSizeInBits() == 16) {
11619 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11620 // as its second argument.
11621 if (N1.getValueType() != MVT::i32)
11622 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11623 if (N2.getValueType() != MVT::i32)
11624 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11625 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11630 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11632 MVT OpVT = Op.getSimpleValueType();
11634 // If this is a 256-bit vector result, first insert into a 128-bit
11635 // vector and then insert into the 256-bit vector.
11636 if (!OpVT.is128BitVector()) {
11637 // Insert into a 128-bit vector.
11638 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11639 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11640 OpVT.getVectorNumElements() / SizeFactor);
11642 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11644 // Insert the 128-bit vector.
11645 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11648 if (OpVT == MVT::v1i64 &&
11649 Op.getOperand(0).getValueType() == MVT::i64)
11650 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11652 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11653 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11654 return DAG.getBitcast(
11655 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11658 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11659 // a simple subregister reference or explicit instructions to grab
11660 // upper bits of a vector.
11661 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11662 SelectionDAG &DAG) {
11664 SDValue In = Op.getOperand(0);
11665 SDValue Idx = Op.getOperand(1);
11666 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11667 MVT ResVT = Op.getSimpleValueType();
11668 MVT InVT = In.getSimpleValueType();
11670 if (Subtarget->hasFp256()) {
11671 if (ResVT.is128BitVector() &&
11672 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11673 isa<ConstantSDNode>(Idx)) {
11674 return Extract128BitVector(In, IdxVal, DAG, dl);
11676 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11677 isa<ConstantSDNode>(Idx)) {
11678 return Extract256BitVector(In, IdxVal, DAG, dl);
11684 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11685 // simple superregister reference or explicit instructions to insert
11686 // the upper bits of a vector.
11687 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11688 SelectionDAG &DAG) {
11689 if (!Subtarget->hasAVX())
11693 SDValue Vec = Op.getOperand(0);
11694 SDValue SubVec = Op.getOperand(1);
11695 SDValue Idx = Op.getOperand(2);
11697 if (!isa<ConstantSDNode>(Idx))
11700 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11701 MVT OpVT = Op.getSimpleValueType();
11702 MVT SubVecVT = SubVec.getSimpleValueType();
11704 // Fold two 16-byte subvector loads into one 32-byte load:
11705 // (insert_subvector (insert_subvector undef, (load addr), 0),
11706 // (load addr + 16), Elts/2)
11708 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11709 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11710 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11711 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11712 if (Idx2 && Idx2->getZExtValue() == 0) {
11713 SDValue SubVec2 = Vec.getOperand(1);
11714 // If needed, look through a bitcast to get to the load.
11715 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11716 SubVec2 = SubVec2.getOperand(0);
11718 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11720 unsigned Alignment = FirstLd->getAlignment();
11721 unsigned AS = FirstLd->getAddressSpace();
11722 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11723 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11724 OpVT, AS, Alignment, &Fast) && Fast) {
11725 SDValue Ops[] = { SubVec2, SubVec };
11726 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11733 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11734 SubVecVT.is128BitVector())
11735 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11737 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11738 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11740 if (OpVT.getVectorElementType() == MVT::i1) {
11741 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11743 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11744 SDValue Undef = DAG.getUNDEF(OpVT);
11745 unsigned NumElems = OpVT.getVectorNumElements();
11746 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11748 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11749 // Zero upper bits of the Vec
11750 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11751 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11753 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11755 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11756 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11759 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11761 // Zero upper bits of the Vec2
11762 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11763 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11764 // Zero lower bits of the Vec
11765 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11766 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11767 // Merge them together
11768 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11774 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11775 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11776 // one of the above mentioned nodes. It has to be wrapped because otherwise
11777 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11778 // be used to form addressing mode. These wrapped nodes will be selected
11781 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11782 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11784 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11785 // global base reg.
11786 unsigned char OpFlag = 0;
11787 unsigned WrapperKind = X86ISD::Wrapper;
11788 CodeModel::Model M = DAG.getTarget().getCodeModel();
11790 if (Subtarget->isPICStyleRIPRel() &&
11791 (M == CodeModel::Small || M == CodeModel::Kernel))
11792 WrapperKind = X86ISD::WrapperRIP;
11793 else if (Subtarget->isPICStyleGOT())
11794 OpFlag = X86II::MO_GOTOFF;
11795 else if (Subtarget->isPICStyleStubPIC())
11796 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11798 auto PtrVT = getPointerTy(DAG.getDataLayout());
11799 SDValue Result = DAG.getTargetConstantPool(
11800 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11802 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11803 // With PIC, the address is actually $g + Offset.
11806 DAG.getNode(ISD::ADD, DL, PtrVT,
11807 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11813 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11814 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11816 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11817 // global base reg.
11818 unsigned char OpFlag = 0;
11819 unsigned WrapperKind = X86ISD::Wrapper;
11820 CodeModel::Model M = DAG.getTarget().getCodeModel();
11822 if (Subtarget->isPICStyleRIPRel() &&
11823 (M == CodeModel::Small || M == CodeModel::Kernel))
11824 WrapperKind = X86ISD::WrapperRIP;
11825 else if (Subtarget->isPICStyleGOT())
11826 OpFlag = X86II::MO_GOTOFF;
11827 else if (Subtarget->isPICStyleStubPIC())
11828 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11830 auto PtrVT = getPointerTy(DAG.getDataLayout());
11831 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11833 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11835 // With PIC, the address is actually $g + Offset.
11838 DAG.getNode(ISD::ADD, DL, PtrVT,
11839 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11845 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11846 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11848 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11849 // global base reg.
11850 unsigned char OpFlag = 0;
11851 unsigned WrapperKind = X86ISD::Wrapper;
11852 CodeModel::Model M = DAG.getTarget().getCodeModel();
11854 if (Subtarget->isPICStyleRIPRel() &&
11855 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11856 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11857 OpFlag = X86II::MO_GOTPCREL;
11858 WrapperKind = X86ISD::WrapperRIP;
11859 } else if (Subtarget->isPICStyleGOT()) {
11860 OpFlag = X86II::MO_GOT;
11861 } else if (Subtarget->isPICStyleStubPIC()) {
11862 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11863 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11864 OpFlag = X86II::MO_DARWIN_NONLAZY;
11867 auto PtrVT = getPointerTy(DAG.getDataLayout());
11868 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11871 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11873 // With PIC, the address is actually $g + Offset.
11874 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11875 !Subtarget->is64Bit()) {
11877 DAG.getNode(ISD::ADD, DL, PtrVT,
11878 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11881 // For symbols that require a load from a stub to get the address, emit the
11883 if (isGlobalStubReference(OpFlag))
11884 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11885 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11886 false, false, false, 0);
11892 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11893 // Create the TargetBlockAddressAddress node.
11894 unsigned char OpFlags =
11895 Subtarget->ClassifyBlockAddressReference();
11896 CodeModel::Model M = DAG.getTarget().getCodeModel();
11897 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11898 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11900 auto PtrVT = getPointerTy(DAG.getDataLayout());
11901 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11903 if (Subtarget->isPICStyleRIPRel() &&
11904 (M == CodeModel::Small || M == CodeModel::Kernel))
11905 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11907 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11909 // With PIC, the address is actually $g + Offset.
11910 if (isGlobalRelativeToPICBase(OpFlags)) {
11911 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11912 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11919 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11920 int64_t Offset, SelectionDAG &DAG) const {
11921 // Create the TargetGlobalAddress node, folding in the constant
11922 // offset if it is legal.
11923 unsigned char OpFlags =
11924 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11925 CodeModel::Model M = DAG.getTarget().getCodeModel();
11926 auto PtrVT = getPointerTy(DAG.getDataLayout());
11928 if (OpFlags == X86II::MO_NO_FLAG &&
11929 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11930 // A direct static reference to a global.
11931 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11934 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11937 if (Subtarget->isPICStyleRIPRel() &&
11938 (M == CodeModel::Small || M == CodeModel::Kernel))
11939 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11941 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11943 // With PIC, the address is actually $g + Offset.
11944 if (isGlobalRelativeToPICBase(OpFlags)) {
11945 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11946 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11949 // For globals that require a load from a stub to get the address, emit the
11951 if (isGlobalStubReference(OpFlags))
11952 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11953 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11954 false, false, false, 0);
11956 // If there was a non-zero offset that we didn't fold, create an explicit
11957 // addition for it.
11959 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11960 DAG.getConstant(Offset, dl, PtrVT));
11966 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11967 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11968 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11969 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11973 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11974 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11975 unsigned char OperandFlags, bool LocalDynamic = false) {
11976 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11977 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11979 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11980 GA->getValueType(0),
11984 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11988 SDValue Ops[] = { Chain, TGA, *InFlag };
11989 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11991 SDValue Ops[] = { Chain, TGA };
11992 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11995 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11996 MFI->setAdjustsStack(true);
11997 MFI->setHasCalls(true);
11999 SDValue Flag = Chain.getValue(1);
12000 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12003 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12005 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12008 SDLoc dl(GA); // ? function entry point might be better
12009 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12010 DAG.getNode(X86ISD::GlobalBaseReg,
12011 SDLoc(), PtrVT), InFlag);
12012 InFlag = Chain.getValue(1);
12014 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12017 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12019 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12021 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12022 X86::RAX, X86II::MO_TLSGD);
12025 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12031 // Get the start address of the TLS block for this module.
12032 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12033 .getInfo<X86MachineFunctionInfo>();
12034 MFI->incNumLocalDynamicTLSAccesses();
12038 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12039 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12042 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12043 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12044 InFlag = Chain.getValue(1);
12045 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12046 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12049 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12053 unsigned char OperandFlags = X86II::MO_DTPOFF;
12054 unsigned WrapperKind = X86ISD::Wrapper;
12055 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12056 GA->getValueType(0),
12057 GA->getOffset(), OperandFlags);
12058 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12060 // Add x@dtpoff with the base.
12061 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12064 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12065 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12066 const EVT PtrVT, TLSModel::Model model,
12067 bool is64Bit, bool isPIC) {
12070 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12071 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12072 is64Bit ? 257 : 256));
12074 SDValue ThreadPointer =
12075 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12076 MachinePointerInfo(Ptr), false, false, false, 0);
12078 unsigned char OperandFlags = 0;
12079 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12081 unsigned WrapperKind = X86ISD::Wrapper;
12082 if (model == TLSModel::LocalExec) {
12083 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12084 } else if (model == TLSModel::InitialExec) {
12086 OperandFlags = X86II::MO_GOTTPOFF;
12087 WrapperKind = X86ISD::WrapperRIP;
12089 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12092 llvm_unreachable("Unexpected model");
12095 // emit "addl x@ntpoff,%eax" (local exec)
12096 // or "addl x@indntpoff,%eax" (initial exec)
12097 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12099 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12100 GA->getOffset(), OperandFlags);
12101 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12103 if (model == TLSModel::InitialExec) {
12104 if (isPIC && !is64Bit) {
12105 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12106 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12110 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12111 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12112 false, false, false, 0);
12115 // The address of the thread local variable is the add of the thread
12116 // pointer with the offset of the variable.
12117 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12121 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12123 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12124 const GlobalValue *GV = GA->getGlobal();
12125 auto PtrVT = getPointerTy(DAG.getDataLayout());
12127 if (Subtarget->isTargetELF()) {
12128 if (DAG.getTarget().Options.EmulatedTLS)
12129 return LowerToTLSEmulatedModel(GA, DAG);
12130 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12132 case TLSModel::GeneralDynamic:
12133 if (Subtarget->is64Bit())
12134 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12135 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12136 case TLSModel::LocalDynamic:
12137 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12138 Subtarget->is64Bit());
12139 case TLSModel::InitialExec:
12140 case TLSModel::LocalExec:
12141 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12142 DAG.getTarget().getRelocationModel() ==
12145 llvm_unreachable("Unknown TLS model.");
12148 if (Subtarget->isTargetDarwin()) {
12149 // Darwin only has one model of TLS. Lower to that.
12150 unsigned char OpFlag = 0;
12151 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12152 X86ISD::WrapperRIP : X86ISD::Wrapper;
12154 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12155 // global base reg.
12156 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12157 !Subtarget->is64Bit();
12159 OpFlag = X86II::MO_TLVP_PIC_BASE;
12161 OpFlag = X86II::MO_TLVP;
12163 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12164 GA->getValueType(0),
12165 GA->getOffset(), OpFlag);
12166 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12168 // With PIC32, the address is actually $g + Offset.
12170 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12171 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12174 // Lowering the machine isd will make sure everything is in the right
12176 SDValue Chain = DAG.getEntryNode();
12177 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12178 SDValue Args[] = { Chain, Offset };
12179 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12181 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12182 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12183 MFI->setAdjustsStack(true);
12185 // And our return value (tls address) is in the standard call return value
12187 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12188 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12191 if (Subtarget->isTargetKnownWindowsMSVC() ||
12192 Subtarget->isTargetWindowsGNU()) {
12193 // Just use the implicit TLS architecture
12194 // Need to generate someting similar to:
12195 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12197 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12198 // mov rcx, qword [rdx+rcx*8]
12199 // mov eax, .tls$:tlsvar
12200 // [rax+rcx] contains the address
12201 // Windows 64bit: gs:0x58
12202 // Windows 32bit: fs:__tls_array
12205 SDValue Chain = DAG.getEntryNode();
12207 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12208 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12209 // use its literal value of 0x2C.
12210 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12211 ? Type::getInt8PtrTy(*DAG.getContext(),
12213 : Type::getInt32PtrTy(*DAG.getContext(),
12216 SDValue TlsArray = Subtarget->is64Bit()
12217 ? DAG.getIntPtrConstant(0x58, dl)
12218 : (Subtarget->isTargetWindowsGNU()
12219 ? DAG.getIntPtrConstant(0x2C, dl)
12220 : DAG.getExternalSymbol("_tls_array", PtrVT));
12222 SDValue ThreadPointer =
12223 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12227 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12228 res = ThreadPointer;
12230 // Load the _tls_index variable
12231 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12232 if (Subtarget->is64Bit())
12233 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12234 MachinePointerInfo(), MVT::i32, false, false,
12237 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12240 auto &DL = DAG.getDataLayout();
12242 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12243 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12245 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12248 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12251 // Get the offset of start of .tls section
12252 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12253 GA->getValueType(0),
12254 GA->getOffset(), X86II::MO_SECREL);
12255 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12257 // The address of the thread local variable is the add of the thread
12258 // pointer with the offset of the variable.
12259 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12262 llvm_unreachable("TLS not implemented for this target.");
12265 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12266 /// and take a 2 x i32 value to shift plus a shift amount.
12267 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12268 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12269 MVT VT = Op.getSimpleValueType();
12270 unsigned VTBits = VT.getSizeInBits();
12272 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12273 SDValue ShOpLo = Op.getOperand(0);
12274 SDValue ShOpHi = Op.getOperand(1);
12275 SDValue ShAmt = Op.getOperand(2);
12276 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12277 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12279 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12280 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12281 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12282 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12283 : DAG.getConstant(0, dl, VT);
12285 SDValue Tmp2, Tmp3;
12286 if (Op.getOpcode() == ISD::SHL_PARTS) {
12287 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12288 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12290 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12291 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12294 // If the shift amount is larger or equal than the width of a part we can't
12295 // rely on the results of shld/shrd. Insert a test and select the appropriate
12296 // values for large shift amounts.
12297 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12298 DAG.getConstant(VTBits, dl, MVT::i8));
12299 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12300 AndNode, DAG.getConstant(0, dl, MVT::i8));
12303 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12304 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12305 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12307 if (Op.getOpcode() == ISD::SHL_PARTS) {
12308 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12309 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12311 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12312 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12315 SDValue Ops[2] = { Lo, Hi };
12316 return DAG.getMergeValues(Ops, dl);
12319 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12320 SelectionDAG &DAG) const {
12321 SDValue Src = Op.getOperand(0);
12322 MVT SrcVT = Src.getSimpleValueType();
12323 MVT VT = Op.getSimpleValueType();
12326 if (SrcVT.isVector()) {
12327 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12328 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12329 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12330 DAG.getUNDEF(SrcVT)));
12332 if (SrcVT.getVectorElementType() == MVT::i1) {
12333 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12334 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12335 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12340 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12341 "Unknown SINT_TO_FP to lower!");
12343 // These are really Legal; return the operand so the caller accepts it as
12345 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12347 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12348 Subtarget->is64Bit()) {
12352 unsigned Size = SrcVT.getSizeInBits()/8;
12353 MachineFunction &MF = DAG.getMachineFunction();
12354 auto PtrVT = getPointerTy(MF.getDataLayout());
12355 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12356 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12357 SDValue Chain = DAG.getStore(
12358 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12359 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12361 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12364 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12366 SelectionDAG &DAG) const {
12370 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12372 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12374 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12376 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12378 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12379 MachineMemOperand *MMO;
12381 int SSFI = FI->getIndex();
12382 MMO = DAG.getMachineFunction().getMachineMemOperand(
12383 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12384 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12386 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12387 StackSlot = StackSlot.getOperand(1);
12389 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12390 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12392 Tys, Ops, SrcVT, MMO);
12395 Chain = Result.getValue(1);
12396 SDValue InFlag = Result.getValue(2);
12398 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12399 // shouldn't be necessary except that RFP cannot be live across
12400 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12401 MachineFunction &MF = DAG.getMachineFunction();
12402 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12403 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12404 auto PtrVT = getPointerTy(MF.getDataLayout());
12405 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12406 Tys = DAG.getVTList(MVT::Other);
12408 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12410 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12411 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12412 MachineMemOperand::MOStore, SSFISize, SSFISize);
12414 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12415 Ops, Op.getValueType(), MMO);
12416 Result = DAG.getLoad(
12417 Op.getValueType(), DL, Chain, StackSlot,
12418 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12419 false, false, false, 0);
12425 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12426 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12427 SelectionDAG &DAG) const {
12428 // This algorithm is not obvious. Here it is what we're trying to output:
12431 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12432 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12434 haddpd %xmm0, %xmm0
12436 pshufd $0x4e, %xmm0, %xmm1
12442 LLVMContext *Context = DAG.getContext();
12444 // Build some magic constants.
12445 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12446 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12447 auto PtrVT = getPointerTy(DAG.getDataLayout());
12448 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12450 SmallVector<Constant*,2> CV1;
12452 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12453 APInt(64, 0x4330000000000000ULL))));
12455 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12456 APInt(64, 0x4530000000000000ULL))));
12457 Constant *C1 = ConstantVector::get(CV1);
12458 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12460 // Load the 64-bit value into an XMM register.
12461 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12464 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12465 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12466 false, false, false, 16);
12468 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12471 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12472 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12473 false, false, false, 16);
12474 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12475 // TODO: Are there any fast-math-flags to propagate here?
12476 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12479 if (Subtarget->hasSSE3()) {
12480 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12481 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12483 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12484 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12486 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12487 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12490 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12491 DAG.getIntPtrConstant(0, dl));
12494 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12495 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12496 SelectionDAG &DAG) const {
12498 // FP constant to bias correct the final result.
12499 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12502 // Load the 32-bit value into an XMM register.
12503 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12506 // Zero out the upper parts of the register.
12507 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12509 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12510 DAG.getBitcast(MVT::v2f64, Load),
12511 DAG.getIntPtrConstant(0, dl));
12513 // Or the load with the bias.
12514 SDValue Or = DAG.getNode(
12515 ISD::OR, dl, MVT::v2i64,
12516 DAG.getBitcast(MVT::v2i64,
12517 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12518 DAG.getBitcast(MVT::v2i64,
12519 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12521 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12522 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12524 // Subtract the bias.
12525 // TODO: Are there any fast-math-flags to propagate here?
12526 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12528 // Handle final rounding.
12529 EVT DestVT = Op.getValueType();
12531 if (DestVT.bitsLT(MVT::f64))
12532 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12533 DAG.getIntPtrConstant(0, dl));
12534 if (DestVT.bitsGT(MVT::f64))
12535 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12537 // Handle final rounding.
12541 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12542 const X86Subtarget &Subtarget) {
12543 // The algorithm is the following:
12544 // #ifdef __SSE4_1__
12545 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12546 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12547 // (uint4) 0x53000000, 0xaa);
12549 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12550 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12552 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12553 // return (float4) lo + fhi;
12555 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12556 // reassociate the two FADDs, and if we do that, the algorithm fails
12557 // spectacularly (PR24512).
12558 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12559 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12560 // there's also the MachineCombiner reassociations happening on Machine IR.
12561 if (DAG.getTarget().Options.UnsafeFPMath)
12565 SDValue V = Op->getOperand(0);
12566 EVT VecIntVT = V.getValueType();
12567 bool Is128 = VecIntVT == MVT::v4i32;
12568 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12569 // If we convert to something else than the supported type, e.g., to v4f64,
12571 if (VecFloatVT != Op->getValueType(0))
12574 unsigned NumElts = VecIntVT.getVectorNumElements();
12575 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12576 "Unsupported custom type");
12577 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12579 // In the #idef/#else code, we have in common:
12580 // - The vector of constants:
12586 // Create the splat vector for 0x4b000000.
12587 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12588 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12589 CstLow, CstLow, CstLow, CstLow};
12590 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12591 makeArrayRef(&CstLowArray[0], NumElts));
12592 // Create the splat vector for 0x53000000.
12593 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12594 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12595 CstHigh, CstHigh, CstHigh, CstHigh};
12596 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12597 makeArrayRef(&CstHighArray[0], NumElts));
12599 // Create the right shift.
12600 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12601 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12602 CstShift, CstShift, CstShift, CstShift};
12603 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12604 makeArrayRef(&CstShiftArray[0], NumElts));
12605 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12608 if (Subtarget.hasSSE41()) {
12609 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12610 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12611 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12612 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12613 // Low will be bitcasted right away, so do not bother bitcasting back to its
12615 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12616 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12617 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12618 // (uint4) 0x53000000, 0xaa);
12619 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12620 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12621 // High will be bitcasted right away, so do not bother bitcasting back to
12622 // its original type.
12623 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12624 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12626 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12627 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12628 CstMask, CstMask, CstMask);
12629 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12630 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12631 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12633 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12634 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12637 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12638 SDValue CstFAdd = DAG.getConstantFP(
12639 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12640 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12641 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12642 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12643 makeArrayRef(&CstFAddArray[0], NumElts));
12645 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12646 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12647 // TODO: Are there any fast-math-flags to propagate here?
12649 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12650 // return (float4) lo + fhi;
12651 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12652 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12655 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12656 SelectionDAG &DAG) const {
12657 SDValue N0 = Op.getOperand(0);
12658 MVT SVT = N0.getSimpleValueType();
12661 switch (SVT.SimpleTy) {
12663 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12668 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12669 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12670 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12674 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12677 if (Subtarget->hasAVX512())
12678 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12679 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12681 llvm_unreachable(nullptr);
12684 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12685 SelectionDAG &DAG) const {
12686 SDValue N0 = Op.getOperand(0);
12688 auto PtrVT = getPointerTy(DAG.getDataLayout());
12690 if (Op.getValueType().isVector())
12691 return lowerUINT_TO_FP_vec(Op, DAG);
12693 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12694 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12695 // the optimization here.
12696 if (DAG.SignBitIsZero(N0))
12697 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12699 MVT SrcVT = N0.getSimpleValueType();
12700 MVT DstVT = Op.getSimpleValueType();
12702 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12703 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12704 // Conversions from unsigned i32 to f32/f64 are legal,
12705 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12709 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12710 return LowerUINT_TO_FP_i64(Op, DAG);
12711 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12712 return LowerUINT_TO_FP_i32(Op, DAG);
12713 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12716 // Make a 64-bit buffer, and use it to build an FILD.
12717 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12718 if (SrcVT == MVT::i32) {
12719 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12720 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12721 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12722 StackSlot, MachinePointerInfo(),
12724 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12725 OffsetSlot, MachinePointerInfo(),
12727 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12731 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12732 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12733 StackSlot, MachinePointerInfo(),
12735 // For i64 source, we need to add the appropriate power of 2 if the input
12736 // was negative. This is the same as the optimization in
12737 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12738 // we must be careful to do the computation in x87 extended precision, not
12739 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12740 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12741 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12742 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12743 MachineMemOperand::MOLoad, 8, 8);
12745 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12746 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12747 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12750 APInt FF(32, 0x5F800000ULL);
12752 // Check whether the sign bit is set.
12753 SDValue SignSet = DAG.getSetCC(
12754 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12755 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12757 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12758 SDValue FudgePtr = DAG.getConstantPool(
12759 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12761 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12762 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12763 SDValue Four = DAG.getIntPtrConstant(4, dl);
12764 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12766 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12768 // Load the value out, extending it from f32 to f80.
12769 // FIXME: Avoid the extend by constructing the right constant pool?
12770 SDValue Fudge = DAG.getExtLoad(
12771 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12772 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12773 false, false, false, 4);
12774 // Extend everything to 80 bits to force it to be done on x87.
12775 // TODO: Are there any fast-math-flags to propagate here?
12776 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12777 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12778 DAG.getIntPtrConstant(0, dl));
12781 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12782 // is legal, or has an f16 source (which needs to be promoted to f32),
12783 // just return an <SDValue(), SDValue()> pair.
12784 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12785 // to i16, i32 or i64, and we lower it to a legal sequence.
12786 // If lowered to the final integer result we return a <result, SDValue()> pair.
12787 // Otherwise we lower it to a sequence ending with a FIST, return a
12788 // <FIST, StackSlot> pair, and the caller is responsible for loading
12789 // the final integer result from StackSlot.
12790 std::pair<SDValue,SDValue>
12791 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12792 bool IsSigned, bool IsReplace) const {
12795 EVT DstTy = Op.getValueType();
12796 EVT TheVT = Op.getOperand(0).getValueType();
12797 auto PtrVT = getPointerTy(DAG.getDataLayout());
12799 if (TheVT == MVT::f16)
12800 // We need to promote the f16 to f32 before using the lowering
12801 // in this routine.
12802 return std::make_pair(SDValue(), SDValue());
12804 assert((TheVT == MVT::f32 ||
12805 TheVT == MVT::f64 ||
12806 TheVT == MVT::f80) &&
12807 "Unexpected FP operand type in FP_TO_INTHelper");
12809 // If using FIST to compute an unsigned i64, we'll need some fixup
12810 // to handle values above the maximum signed i64. A FIST is always
12811 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12812 bool UnsignedFixup = !IsSigned &&
12813 DstTy == MVT::i64 &&
12814 (!Subtarget->is64Bit() ||
12815 !isScalarFPTypeInSSEReg(TheVT));
12817 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12818 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12819 // The low 32 bits of the fist result will have the correct uint32 result.
12820 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12824 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12825 DstTy.getSimpleVT() >= MVT::i16 &&
12826 "Unknown FP_TO_INT to lower!");
12828 // These are really Legal.
12829 if (DstTy == MVT::i32 &&
12830 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12831 return std::make_pair(SDValue(), SDValue());
12832 if (Subtarget->is64Bit() &&
12833 DstTy == MVT::i64 &&
12834 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12835 return std::make_pair(SDValue(), SDValue());
12837 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12839 MachineFunction &MF = DAG.getMachineFunction();
12840 unsigned MemSize = DstTy.getSizeInBits()/8;
12841 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12842 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12845 switch (DstTy.getSimpleVT().SimpleTy) {
12846 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12847 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12848 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12849 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12852 SDValue Chain = DAG.getEntryNode();
12853 SDValue Value = Op.getOperand(0);
12854 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12856 if (UnsignedFixup) {
12858 // Conversion to unsigned i64 is implemented with a select,
12859 // depending on whether the source value fits in the range
12860 // of a signed i64. Let Thresh be the FP equivalent of
12861 // 0x8000000000000000ULL.
12863 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12864 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12865 // Fist-to-mem64 FistSrc
12866 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12867 // to XOR'ing the high 32 bits with Adjust.
12869 // Being a power of 2, Thresh is exactly representable in all FP formats.
12870 // For X87 we'd like to use the smallest FP type for this constant, but
12871 // for DAG type consistency we have to match the FP operand type.
12873 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12874 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12875 bool LosesInfo = false;
12876 if (TheVT == MVT::f64)
12877 // The rounding mode is irrelevant as the conversion should be exact.
12878 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12880 else if (TheVT == MVT::f80)
12881 Status = Thresh.convert(APFloat::x87DoubleExtended,
12882 APFloat::rmNearestTiesToEven, &LosesInfo);
12884 assert(Status == APFloat::opOK && !LosesInfo &&
12885 "FP conversion should have been exact");
12887 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12889 SDValue Cmp = DAG.getSetCC(DL,
12890 getSetCCResultType(DAG.getDataLayout(),
12891 *DAG.getContext(), TheVT),
12892 Value, ThreshVal, ISD::SETLT);
12893 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12894 DAG.getConstant(0, DL, MVT::i32),
12895 DAG.getConstant(0x80000000, DL, MVT::i32));
12896 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12897 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12898 *DAG.getContext(), TheVT),
12899 Value, ThreshVal, ISD::SETLT);
12900 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12903 // FIXME This causes a redundant load/store if the SSE-class value is already
12904 // in memory, such as if it is on the callstack.
12905 if (isScalarFPTypeInSSEReg(TheVT)) {
12906 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12907 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12908 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12910 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12912 Chain, StackSlot, DAG.getValueType(TheVT)
12915 MachineMemOperand *MMO =
12916 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12917 MachineMemOperand::MOLoad, MemSize, MemSize);
12918 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12919 Chain = Value.getValue(1);
12920 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12921 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12924 MachineMemOperand *MMO =
12925 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12926 MachineMemOperand::MOStore, MemSize, MemSize);
12928 if (UnsignedFixup) {
12930 // Insert the FIST, load its result as two i32's,
12931 // and XOR the high i32 with Adjust.
12933 SDValue FistOps[] = { Chain, Value, StackSlot };
12934 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12935 FistOps, DstTy, MMO);
12937 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12938 MachinePointerInfo(),
12939 false, false, false, 0);
12940 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12941 DAG.getConstant(4, DL, PtrVT));
12943 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12944 MachinePointerInfo(),
12945 false, false, false, 0);
12946 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12948 if (Subtarget->is64Bit()) {
12949 // Join High32 and Low32 into a 64-bit result.
12950 // (High32 << 32) | Low32
12951 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12952 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12953 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12954 DAG.getConstant(32, DL, MVT::i8));
12955 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12956 return std::make_pair(Result, SDValue());
12959 SDValue ResultOps[] = { Low32, High32 };
12961 SDValue pair = IsReplace
12962 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12963 : DAG.getMergeValues(ResultOps, DL);
12964 return std::make_pair(pair, SDValue());
12966 // Build the FP_TO_INT*_IN_MEM
12967 SDValue Ops[] = { Chain, Value, StackSlot };
12968 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12970 return std::make_pair(FIST, StackSlot);
12974 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12975 const X86Subtarget *Subtarget) {
12976 MVT VT = Op->getSimpleValueType(0);
12977 SDValue In = Op->getOperand(0);
12978 MVT InVT = In.getSimpleValueType();
12981 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12982 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12984 // Optimize vectors in AVX mode:
12987 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12988 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12989 // Concat upper and lower parts.
12992 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12993 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12994 // Concat upper and lower parts.
12997 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12998 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12999 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13002 if (Subtarget->hasInt256())
13003 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13005 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13006 SDValue Undef = DAG.getUNDEF(InVT);
13007 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13008 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13009 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13011 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13012 VT.getVectorNumElements()/2);
13014 OpLo = DAG.getBitcast(HVT, OpLo);
13015 OpHi = DAG.getBitcast(HVT, OpHi);
13017 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13020 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13021 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13022 MVT VT = Op->getSimpleValueType(0);
13023 SDValue In = Op->getOperand(0);
13024 MVT InVT = In.getSimpleValueType();
13026 unsigned int NumElts = VT.getVectorNumElements();
13027 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13030 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13031 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13033 assert(InVT.getVectorElementType() == MVT::i1);
13034 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13036 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13038 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13040 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13041 if (VT.is512BitVector())
13043 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13046 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13047 SelectionDAG &DAG) {
13048 if (Subtarget->hasFp256())
13049 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13055 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13056 SelectionDAG &DAG) {
13058 MVT VT = Op.getSimpleValueType();
13059 SDValue In = Op.getOperand(0);
13060 MVT SVT = In.getSimpleValueType();
13062 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13063 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13065 if (Subtarget->hasFp256())
13066 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13069 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13070 VT.getVectorNumElements() != SVT.getVectorNumElements());
13074 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13076 MVT VT = Op.getSimpleValueType();
13077 SDValue In = Op.getOperand(0);
13078 MVT InVT = In.getSimpleValueType();
13080 if (VT == MVT::i1) {
13081 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13082 "Invalid scalar TRUNCATE operation");
13083 if (InVT.getSizeInBits() >= 32)
13085 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13086 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13088 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13089 "Invalid TRUNCATE operation");
13091 // move vector to mask - truncate solution for SKX
13092 if (VT.getVectorElementType() == MVT::i1) {
13093 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13094 Subtarget->hasBWI())
13095 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13096 if ((InVT.is256BitVector() || InVT.is128BitVector())
13097 && InVT.getScalarSizeInBits() <= 16 &&
13098 Subtarget->hasBWI() && Subtarget->hasVLX())
13099 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13100 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13101 Subtarget->hasDQI())
13102 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13103 if ((InVT.is256BitVector() || InVT.is128BitVector())
13104 && InVT.getScalarSizeInBits() >= 32 &&
13105 Subtarget->hasDQI() && Subtarget->hasVLX())
13106 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13109 if (VT.getVectorElementType() == MVT::i1) {
13110 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13111 unsigned NumElts = InVT.getVectorNumElements();
13112 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13113 if (InVT.getSizeInBits() < 512) {
13114 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13115 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13120 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13121 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13122 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13125 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13126 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13127 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13128 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13130 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13131 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13132 if (Subtarget->hasInt256()) {
13133 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13134 In = DAG.getBitcast(MVT::v8i32, In);
13135 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13137 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13138 DAG.getIntPtrConstant(0, DL));
13141 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13142 DAG.getIntPtrConstant(0, DL));
13143 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13144 DAG.getIntPtrConstant(2, DL));
13145 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13146 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13147 static const int ShufMask[] = {0, 2, 4, 6};
13148 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13151 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13152 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13153 if (Subtarget->hasInt256()) {
13154 In = DAG.getBitcast(MVT::v32i8, In);
13156 SmallVector<SDValue,32> pshufbMask;
13157 for (unsigned i = 0; i < 2; ++i) {
13158 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13159 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13160 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13161 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13162 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13163 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13164 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13165 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13166 for (unsigned j = 0; j < 8; ++j)
13167 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13169 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13170 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13171 In = DAG.getBitcast(MVT::v4i64, In);
13173 static const int ShufMask[] = {0, 2, -1, -1};
13174 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13176 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13177 DAG.getIntPtrConstant(0, DL));
13178 return DAG.getBitcast(VT, In);
13181 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13182 DAG.getIntPtrConstant(0, DL));
13184 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13185 DAG.getIntPtrConstant(4, DL));
13187 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13188 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13190 // The PSHUFB mask:
13191 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13192 -1, -1, -1, -1, -1, -1, -1, -1};
13194 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13195 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13196 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13198 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13199 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13201 // The MOVLHPS Mask:
13202 static const int ShufMask2[] = {0, 1, 4, 5};
13203 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13204 return DAG.getBitcast(MVT::v8i16, res);
13207 // Handle truncation of V256 to V128 using shuffles.
13208 if (!VT.is128BitVector() || !InVT.is256BitVector())
13211 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13213 unsigned NumElems = VT.getVectorNumElements();
13214 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13216 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13217 // Prepare truncation shuffle mask
13218 for (unsigned i = 0; i != NumElems; ++i)
13219 MaskVec[i] = i * 2;
13220 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13221 DAG.getUNDEF(NVT), &MaskVec[0]);
13222 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13223 DAG.getIntPtrConstant(0, DL));
13226 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13227 SelectionDAG &DAG) const {
13228 assert(!Op.getSimpleValueType().isVector());
13230 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13231 /*IsSigned=*/ true, /*IsReplace=*/ false);
13232 SDValue FIST = Vals.first, StackSlot = Vals.second;
13233 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13234 if (!FIST.getNode())
13237 if (StackSlot.getNode())
13238 // Load the result.
13239 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13240 FIST, StackSlot, MachinePointerInfo(),
13241 false, false, false, 0);
13243 // The node is the result.
13247 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13248 SelectionDAG &DAG) const {
13249 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13250 /*IsSigned=*/ false, /*IsReplace=*/ false);
13251 SDValue FIST = Vals.first, StackSlot = Vals.second;
13252 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13253 if (!FIST.getNode())
13256 if (StackSlot.getNode())
13257 // Load the result.
13258 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13259 FIST, StackSlot, MachinePointerInfo(),
13260 false, false, false, 0);
13262 // The node is the result.
13266 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13268 MVT VT = Op.getSimpleValueType();
13269 SDValue In = Op.getOperand(0);
13270 MVT SVT = In.getSimpleValueType();
13272 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13274 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13275 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13276 In, DAG.getUNDEF(SVT)));
13279 /// The only differences between FABS and FNEG are the mask and the logic op.
13280 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13281 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13282 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13283 "Wrong opcode for lowering FABS or FNEG.");
13285 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13287 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13288 // into an FNABS. We'll lower the FABS after that if it is still in use.
13290 for (SDNode *User : Op->uses())
13291 if (User->getOpcode() == ISD::FNEG)
13295 MVT VT = Op.getSimpleValueType();
13297 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13298 // decide if we should generate a 16-byte constant mask when we only need 4 or
13299 // 8 bytes for the scalar case.
13305 if (VT.isVector()) {
13307 EltVT = VT.getVectorElementType();
13308 NumElts = VT.getVectorNumElements();
13310 // There are no scalar bitwise logical SSE/AVX instructions, so we
13311 // generate a 16-byte vector constant and logic op even for the scalar case.
13312 // Using a 16-byte mask allows folding the load of the mask with
13313 // the logic op, so it can save (~4 bytes) on code size.
13314 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13316 NumElts = (VT == MVT::f64) ? 2 : 4;
13319 unsigned EltBits = EltVT.getSizeInBits();
13320 LLVMContext *Context = DAG.getContext();
13321 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13323 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13324 Constant *C = ConstantInt::get(*Context, MaskElt);
13325 C = ConstantVector::getSplat(NumElts, C);
13326 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13327 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13328 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13330 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13331 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13332 false, false, false, Alignment);
13334 SDValue Op0 = Op.getOperand(0);
13335 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13337 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13338 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13341 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13343 // For the scalar case extend to a 128-bit vector, perform the logic op,
13344 // and extract the scalar result back out.
13345 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13346 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13348 DAG.getIntPtrConstant(0, dl));
13351 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13353 LLVMContext *Context = DAG.getContext();
13354 SDValue Op0 = Op.getOperand(0);
13355 SDValue Op1 = Op.getOperand(1);
13357 MVT VT = Op.getSimpleValueType();
13358 MVT SrcVT = Op1.getSimpleValueType();
13360 // If second operand is smaller, extend it first.
13361 if (SrcVT.bitsLT(VT)) {
13362 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13365 // And if it is bigger, shrink it first.
13366 if (SrcVT.bitsGT(VT)) {
13367 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13371 // At this point the operands and the result should have the same
13372 // type, and that won't be f80 since that is not custom lowered.
13374 const fltSemantics &Sem =
13375 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13376 const unsigned SizeInBits = VT.getSizeInBits();
13378 SmallVector<Constant *, 4> CV(
13379 VT == MVT::f64 ? 2 : 4,
13380 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13382 // First, clear all bits but the sign bit from the second operand (sign).
13383 CV[0] = ConstantFP::get(*Context,
13384 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13385 Constant *C = ConstantVector::get(CV);
13386 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13387 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13389 // Perform all logic operations as 16-byte vectors because there are no
13390 // scalar FP logic instructions in SSE. This allows load folding of the
13391 // constants into the logic instructions.
13392 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13394 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13395 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13396 false, false, false, 16);
13397 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13398 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13400 // Next, clear the sign bit from the first operand (magnitude).
13401 // If it's a constant, we can clear it here.
13402 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13403 APFloat APF = Op0CN->getValueAPF();
13404 // If the magnitude is a positive zero, the sign bit alone is enough.
13405 if (APF.isPosZero())
13406 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13407 DAG.getIntPtrConstant(0, dl));
13409 CV[0] = ConstantFP::get(*Context, APF);
13411 CV[0] = ConstantFP::get(
13413 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13415 C = ConstantVector::get(CV);
13416 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13418 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13419 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13420 false, false, false, 16);
13421 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13422 if (!isa<ConstantFPSDNode>(Op0)) {
13423 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13424 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13426 // OR the magnitude value with the sign bit.
13427 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13428 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13429 DAG.getIntPtrConstant(0, dl));
13432 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13433 SDValue N0 = Op.getOperand(0);
13435 MVT VT = Op.getSimpleValueType();
13437 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13438 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13439 DAG.getConstant(1, dl, VT));
13440 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13443 // Check whether an OR'd tree is PTEST-able.
13444 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13445 SelectionDAG &DAG) {
13446 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13448 if (!Subtarget->hasSSE41())
13451 if (!Op->hasOneUse())
13454 SDNode *N = Op.getNode();
13457 SmallVector<SDValue, 8> Opnds;
13458 DenseMap<SDValue, unsigned> VecInMap;
13459 SmallVector<SDValue, 8> VecIns;
13460 EVT VT = MVT::Other;
13462 // Recognize a special case where a vector is casted into wide integer to
13464 Opnds.push_back(N->getOperand(0));
13465 Opnds.push_back(N->getOperand(1));
13467 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13468 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13469 // BFS traverse all OR'd operands.
13470 if (I->getOpcode() == ISD::OR) {
13471 Opnds.push_back(I->getOperand(0));
13472 Opnds.push_back(I->getOperand(1));
13473 // Re-evaluate the number of nodes to be traversed.
13474 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13478 // Quit if a non-EXTRACT_VECTOR_ELT
13479 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13482 // Quit if without a constant index.
13483 SDValue Idx = I->getOperand(1);
13484 if (!isa<ConstantSDNode>(Idx))
13487 SDValue ExtractedFromVec = I->getOperand(0);
13488 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13489 if (M == VecInMap.end()) {
13490 VT = ExtractedFromVec.getValueType();
13491 // Quit if not 128/256-bit vector.
13492 if (!VT.is128BitVector() && !VT.is256BitVector())
13494 // Quit if not the same type.
13495 if (VecInMap.begin() != VecInMap.end() &&
13496 VT != VecInMap.begin()->first.getValueType())
13498 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13499 VecIns.push_back(ExtractedFromVec);
13501 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13504 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13505 "Not extracted from 128-/256-bit vector.");
13507 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13509 for (DenseMap<SDValue, unsigned>::const_iterator
13510 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13511 // Quit if not all elements are used.
13512 if (I->second != FullMask)
13516 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13518 // Cast all vectors into TestVT for PTEST.
13519 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13520 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13522 // If more than one full vectors are evaluated, OR them first before PTEST.
13523 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13524 // Each iteration will OR 2 nodes and append the result until there is only
13525 // 1 node left, i.e. the final OR'd value of all vectors.
13526 SDValue LHS = VecIns[Slot];
13527 SDValue RHS = VecIns[Slot + 1];
13528 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13531 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13532 VecIns.back(), VecIns.back());
13535 /// \brief return true if \c Op has a use that doesn't just read flags.
13536 static bool hasNonFlagsUse(SDValue Op) {
13537 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13539 SDNode *User = *UI;
13540 unsigned UOpNo = UI.getOperandNo();
13541 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13542 // Look pass truncate.
13543 UOpNo = User->use_begin().getOperandNo();
13544 User = *User->use_begin();
13547 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13548 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13554 /// Emit nodes that will be selected as "test Op0,Op0", or something
13556 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13557 SelectionDAG &DAG) const {
13558 if (Op.getValueType() == MVT::i1) {
13559 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13560 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13561 DAG.getConstant(0, dl, MVT::i8));
13563 // CF and OF aren't always set the way we want. Determine which
13564 // of these we need.
13565 bool NeedCF = false;
13566 bool NeedOF = false;
13569 case X86::COND_A: case X86::COND_AE:
13570 case X86::COND_B: case X86::COND_BE:
13573 case X86::COND_G: case X86::COND_GE:
13574 case X86::COND_L: case X86::COND_LE:
13575 case X86::COND_O: case X86::COND_NO: {
13576 // Check if we really need to set the
13577 // Overflow flag. If NoSignedWrap is present
13578 // that is not actually needed.
13579 switch (Op->getOpcode()) {
13584 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13585 if (BinNode->Flags.hasNoSignedWrap())
13595 // See if we can use the EFLAGS value from the operand instead of
13596 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13597 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13598 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13599 // Emit a CMP with 0, which is the TEST pattern.
13600 //if (Op.getValueType() == MVT::i1)
13601 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13602 // DAG.getConstant(0, MVT::i1));
13603 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13604 DAG.getConstant(0, dl, Op.getValueType()));
13606 unsigned Opcode = 0;
13607 unsigned NumOperands = 0;
13609 // Truncate operations may prevent the merge of the SETCC instruction
13610 // and the arithmetic instruction before it. Attempt to truncate the operands
13611 // of the arithmetic instruction and use a reduced bit-width instruction.
13612 bool NeedTruncation = false;
13613 SDValue ArithOp = Op;
13614 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13615 SDValue Arith = Op->getOperand(0);
13616 // Both the trunc and the arithmetic op need to have one user each.
13617 if (Arith->hasOneUse())
13618 switch (Arith.getOpcode()) {
13625 NeedTruncation = true;
13631 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13632 // which may be the result of a CAST. We use the variable 'Op', which is the
13633 // non-casted variable when we check for possible users.
13634 switch (ArithOp.getOpcode()) {
13636 // Due to an isel shortcoming, be conservative if this add is likely to be
13637 // selected as part of a load-modify-store instruction. When the root node
13638 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13639 // uses of other nodes in the match, such as the ADD in this case. This
13640 // leads to the ADD being left around and reselected, with the result being
13641 // two adds in the output. Alas, even if none our users are stores, that
13642 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13643 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13644 // climbing the DAG back to the root, and it doesn't seem to be worth the
13646 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13647 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13648 if (UI->getOpcode() != ISD::CopyToReg &&
13649 UI->getOpcode() != ISD::SETCC &&
13650 UI->getOpcode() != ISD::STORE)
13653 if (ConstantSDNode *C =
13654 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13655 // An add of one will be selected as an INC.
13656 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13657 Opcode = X86ISD::INC;
13662 // An add of negative one (subtract of one) will be selected as a DEC.
13663 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13664 Opcode = X86ISD::DEC;
13670 // Otherwise use a regular EFLAGS-setting add.
13671 Opcode = X86ISD::ADD;
13676 // If we have a constant logical shift that's only used in a comparison
13677 // against zero turn it into an equivalent AND. This allows turning it into
13678 // a TEST instruction later.
13679 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13680 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13681 EVT VT = Op.getValueType();
13682 unsigned BitWidth = VT.getSizeInBits();
13683 unsigned ShAmt = Op->getConstantOperandVal(1);
13684 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13686 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13687 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13688 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13689 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13691 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13692 DAG.getConstant(Mask, dl, VT));
13693 DAG.ReplaceAllUsesWith(Op, New);
13699 // If the primary and result isn't used, don't bother using X86ISD::AND,
13700 // because a TEST instruction will be better.
13701 if (!hasNonFlagsUse(Op))
13707 // Due to the ISEL shortcoming noted above, be conservative if this op is
13708 // likely to be selected as part of a load-modify-store instruction.
13709 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13710 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13711 if (UI->getOpcode() == ISD::STORE)
13714 // Otherwise use a regular EFLAGS-setting instruction.
13715 switch (ArithOp.getOpcode()) {
13716 default: llvm_unreachable("unexpected operator!");
13717 case ISD::SUB: Opcode = X86ISD::SUB; break;
13718 case ISD::XOR: Opcode = X86ISD::XOR; break;
13719 case ISD::AND: Opcode = X86ISD::AND; break;
13721 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13722 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13723 if (EFLAGS.getNode())
13726 Opcode = X86ISD::OR;
13740 return SDValue(Op.getNode(), 1);
13746 // If we found that truncation is beneficial, perform the truncation and
13748 if (NeedTruncation) {
13749 EVT VT = Op.getValueType();
13750 SDValue WideVal = Op->getOperand(0);
13751 EVT WideVT = WideVal.getValueType();
13752 unsigned ConvertedOp = 0;
13753 // Use a target machine opcode to prevent further DAGCombine
13754 // optimizations that may separate the arithmetic operations
13755 // from the setcc node.
13756 switch (WideVal.getOpcode()) {
13758 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13759 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13760 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13761 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13762 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13766 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13767 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13768 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13769 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13770 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13776 // Emit a CMP with 0, which is the TEST pattern.
13777 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13778 DAG.getConstant(0, dl, Op.getValueType()));
13780 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13781 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13783 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13784 DAG.ReplaceAllUsesWith(Op, New);
13785 return SDValue(New.getNode(), 1);
13788 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13790 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13791 SDLoc dl, SelectionDAG &DAG) const {
13792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13793 if (C->getAPIntValue() == 0)
13794 return EmitTest(Op0, X86CC, dl, DAG);
13796 if (Op0.getValueType() == MVT::i1)
13797 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13800 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13801 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13802 // Do the comparison at i32 if it's smaller, besides the Atom case.
13803 // This avoids subregister aliasing issues. Keep the smaller reference
13804 // if we're optimizing for size, however, as that'll allow better folding
13805 // of memory operations.
13806 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13807 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13808 !Subtarget->isAtom()) {
13809 unsigned ExtendOp =
13810 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13811 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13812 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13814 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13815 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13816 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13818 return SDValue(Sub.getNode(), 1);
13820 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13823 /// Convert a comparison if required by the subtarget.
13824 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13825 SelectionDAG &DAG) const {
13826 // If the subtarget does not support the FUCOMI instruction, floating-point
13827 // comparisons have to be converted.
13828 if (Subtarget->hasCMov() ||
13829 Cmp.getOpcode() != X86ISD::CMP ||
13830 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13831 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13834 // The instruction selector will select an FUCOM instruction instead of
13835 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13836 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13837 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13839 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13840 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13841 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13842 DAG.getConstant(8, dl, MVT::i8));
13843 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13844 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13847 /// The minimum architected relative accuracy is 2^-12. We need one
13848 /// Newton-Raphson step to have a good float result (24 bits of precision).
13849 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13850 DAGCombinerInfo &DCI,
13851 unsigned &RefinementSteps,
13852 bool &UseOneConstNR) const {
13853 EVT VT = Op.getValueType();
13854 const char *RecipOp;
13856 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13857 // TODO: Add support for AVX512 (v16f32).
13858 // It is likely not profitable to do this for f64 because a double-precision
13859 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13860 // instructions: convert to single, rsqrtss, convert back to double, refine
13861 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13862 // along with FMA, this could be a throughput win.
13863 if (VT == MVT::f32 && Subtarget->hasSSE1())
13865 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13866 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13867 RecipOp = "vec-sqrtf";
13871 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13872 if (!Recips.isEnabled(RecipOp))
13875 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13876 UseOneConstNR = false;
13877 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13880 /// The minimum architected relative accuracy is 2^-12. We need one
13881 /// Newton-Raphson step to have a good float result (24 bits of precision).
13882 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13883 DAGCombinerInfo &DCI,
13884 unsigned &RefinementSteps) const {
13885 EVT VT = Op.getValueType();
13886 const char *RecipOp;
13888 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13889 // TODO: Add support for AVX512 (v16f32).
13890 // It is likely not profitable to do this for f64 because a double-precision
13891 // reciprocal estimate with refinement on x86 prior to FMA requires
13892 // 15 instructions: convert to single, rcpss, convert back to double, refine
13893 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13894 // along with FMA, this could be a throughput win.
13895 if (VT == MVT::f32 && Subtarget->hasSSE1())
13897 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13898 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13899 RecipOp = "vec-divf";
13903 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13904 if (!Recips.isEnabled(RecipOp))
13907 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13908 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13911 /// If we have at least two divisions that use the same divisor, convert to
13912 /// multplication by a reciprocal. This may need to be adjusted for a given
13913 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13914 /// This is because we still need one division to calculate the reciprocal and
13915 /// then we need two multiplies by that reciprocal as replacements for the
13916 /// original divisions.
13917 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13921 static bool isAllOnes(SDValue V) {
13922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13923 return C && C->isAllOnesValue();
13926 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13927 /// if it's possible.
13928 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13929 SDLoc dl, SelectionDAG &DAG) const {
13930 SDValue Op0 = And.getOperand(0);
13931 SDValue Op1 = And.getOperand(1);
13932 if (Op0.getOpcode() == ISD::TRUNCATE)
13933 Op0 = Op0.getOperand(0);
13934 if (Op1.getOpcode() == ISD::TRUNCATE)
13935 Op1 = Op1.getOperand(0);
13938 if (Op1.getOpcode() == ISD::SHL)
13939 std::swap(Op0, Op1);
13940 if (Op0.getOpcode() == ISD::SHL) {
13941 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13942 if (And00C->getZExtValue() == 1) {
13943 // If we looked past a truncate, check that it's only truncating away
13945 unsigned BitWidth = Op0.getValueSizeInBits();
13946 unsigned AndBitWidth = And.getValueSizeInBits();
13947 if (BitWidth > AndBitWidth) {
13949 DAG.computeKnownBits(Op0, Zeros, Ones);
13950 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13954 RHS = Op0.getOperand(1);
13956 } else if (Op1.getOpcode() == ISD::Constant) {
13957 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13958 uint64_t AndRHSVal = AndRHS->getZExtValue();
13959 SDValue AndLHS = Op0;
13961 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13962 LHS = AndLHS.getOperand(0);
13963 RHS = AndLHS.getOperand(1);
13966 // Use BT if the immediate can't be encoded in a TEST instruction.
13967 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13969 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13973 if (LHS.getNode()) {
13974 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13975 // instruction. Since the shift amount is in-range-or-undefined, we know
13976 // that doing a bittest on the i32 value is ok. We extend to i32 because
13977 // the encoding for the i16 version is larger than the i32 version.
13978 // Also promote i16 to i32 for performance / code size reason.
13979 if (LHS.getValueType() == MVT::i8 ||
13980 LHS.getValueType() == MVT::i16)
13981 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13983 // If the operand types disagree, extend the shift amount to match. Since
13984 // BT ignores high bits (like shifts) we can use anyextend.
13985 if (LHS.getValueType() != RHS.getValueType())
13986 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13988 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13989 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13990 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13991 DAG.getConstant(Cond, dl, MVT::i8), BT);
13997 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13999 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14004 // SSE Condition code mapping:
14013 switch (SetCCOpcode) {
14014 default: llvm_unreachable("Unexpected SETCC condition");
14016 case ISD::SETEQ: SSECC = 0; break;
14018 case ISD::SETGT: Swap = true; // Fallthrough
14020 case ISD::SETOLT: SSECC = 1; break;
14022 case ISD::SETGE: Swap = true; // Fallthrough
14024 case ISD::SETOLE: SSECC = 2; break;
14025 case ISD::SETUO: SSECC = 3; break;
14027 case ISD::SETNE: SSECC = 4; break;
14028 case ISD::SETULE: Swap = true; // Fallthrough
14029 case ISD::SETUGE: SSECC = 5; break;
14030 case ISD::SETULT: Swap = true; // Fallthrough
14031 case ISD::SETUGT: SSECC = 6; break;
14032 case ISD::SETO: SSECC = 7; break;
14034 case ISD::SETONE: SSECC = 8; break;
14037 std::swap(Op0, Op1);
14042 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14043 // ones, and then concatenate the result back.
14044 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14045 MVT VT = Op.getSimpleValueType();
14047 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14048 "Unsupported value type for operation");
14050 unsigned NumElems = VT.getVectorNumElements();
14052 SDValue CC = Op.getOperand(2);
14054 // Extract the LHS vectors
14055 SDValue LHS = Op.getOperand(0);
14056 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14057 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14059 // Extract the RHS vectors
14060 SDValue RHS = Op.getOperand(1);
14061 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14062 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14064 // Issue the operation on the smaller types and concatenate the result back
14065 MVT EltVT = VT.getVectorElementType();
14066 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14067 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14068 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14069 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14072 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14073 SDValue Op0 = Op.getOperand(0);
14074 SDValue Op1 = Op.getOperand(1);
14075 SDValue CC = Op.getOperand(2);
14076 MVT VT = Op.getSimpleValueType();
14079 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14080 "Unexpected type for boolean compare operation");
14081 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14082 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14083 DAG.getConstant(-1, dl, VT));
14084 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14085 DAG.getConstant(-1, dl, VT));
14086 switch (SetCCOpcode) {
14087 default: llvm_unreachable("Unexpected SETCC condition");
14089 // (x == y) -> ~(x ^ y)
14090 return DAG.getNode(ISD::XOR, dl, VT,
14091 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14092 DAG.getConstant(-1, dl, VT));
14094 // (x != y) -> (x ^ y)
14095 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14098 // (x > y) -> (x & ~y)
14099 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14102 // (x < y) -> (~x & y)
14103 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14106 // (x <= y) -> (~x | y)
14107 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14110 // (x >=y) -> (x | ~y)
14111 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14115 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14116 const X86Subtarget *Subtarget) {
14117 SDValue Op0 = Op.getOperand(0);
14118 SDValue Op1 = Op.getOperand(1);
14119 SDValue CC = Op.getOperand(2);
14120 MVT VT = Op.getSimpleValueType();
14123 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14124 Op.getValueType().getScalarType() == MVT::i1 &&
14125 "Cannot set masked compare for this operation");
14127 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14129 bool Unsigned = false;
14132 switch (SetCCOpcode) {
14133 default: llvm_unreachable("Unexpected SETCC condition");
14134 case ISD::SETNE: SSECC = 4; break;
14135 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14136 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14137 case ISD::SETLT: Swap = true; //fall-through
14138 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14139 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14140 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14141 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14142 case ISD::SETULE: Unsigned = true; //fall-through
14143 case ISD::SETLE: SSECC = 2; break;
14147 std::swap(Op0, Op1);
14149 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14150 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14151 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14152 DAG.getConstant(SSECC, dl, MVT::i8));
14155 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14156 /// operand \p Op1. If non-trivial (for example because it's not constant)
14157 /// return an empty value.
14158 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14160 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14164 MVT VT = Op1.getSimpleValueType();
14165 MVT EVT = VT.getVectorElementType();
14166 unsigned n = VT.getVectorNumElements();
14167 SmallVector<SDValue, 8> ULTOp1;
14169 for (unsigned i = 0; i < n; ++i) {
14170 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14171 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14174 // Avoid underflow.
14175 APInt Val = Elt->getAPIntValue();
14179 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14182 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14185 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14186 SelectionDAG &DAG) {
14187 SDValue Op0 = Op.getOperand(0);
14188 SDValue Op1 = Op.getOperand(1);
14189 SDValue CC = Op.getOperand(2);
14190 MVT VT = Op.getSimpleValueType();
14191 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14192 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14197 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14198 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14201 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14202 unsigned Opc = X86ISD::CMPP;
14203 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14204 assert(VT.getVectorNumElements() <= 16);
14205 Opc = X86ISD::CMPM;
14207 // In the two special cases we can't handle, emit two comparisons.
14210 unsigned CombineOpc;
14211 if (SetCCOpcode == ISD::SETUEQ) {
14212 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14214 assert(SetCCOpcode == ISD::SETONE);
14215 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14218 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14219 DAG.getConstant(CC0, dl, MVT::i8));
14220 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14221 DAG.getConstant(CC1, dl, MVT::i8));
14222 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14224 // Handle all other FP comparisons here.
14225 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14226 DAG.getConstant(SSECC, dl, MVT::i8));
14229 MVT VTOp0 = Op0.getSimpleValueType();
14230 assert(VTOp0 == Op1.getSimpleValueType() &&
14231 "Expected operands with same type!");
14232 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14233 "Invalid number of packed elements for source and destination!");
14235 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14236 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14237 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14238 // legalizer firstly checks if the first operand in input to the setcc has
14239 // a legal type. If so, then it promotes the return type to that same type.
14240 // Otherwise, the return type is promoted to the 'next legal type' which,
14241 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14243 // We reach this code only if the following two conditions are met:
14244 // 1. Both return type and operand type have been promoted to wider types
14245 // by the type legalizer.
14246 // 2. The original operand type has been promoted to a 256-bit vector.
14248 // Note that condition 2. only applies for AVX targets.
14249 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14250 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14253 // The non-AVX512 code below works under the assumption that source and
14254 // destination types are the same.
14255 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14256 "Value types for source and destination must be the same!");
14258 // Break 256-bit integer vector compare into smaller ones.
14259 if (VT.is256BitVector() && !Subtarget->hasInt256())
14260 return Lower256IntVSETCC(Op, DAG);
14262 EVT OpVT = Op1.getValueType();
14263 if (OpVT.getVectorElementType() == MVT::i1)
14264 return LowerBoolVSETCC_AVX512(Op, DAG);
14266 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14267 if (Subtarget->hasAVX512()) {
14268 if (Op1.getValueType().is512BitVector() ||
14269 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14270 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14271 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14273 // In AVX-512 architecture setcc returns mask with i1 elements,
14274 // But there is no compare instruction for i8 and i16 elements in KNL.
14275 // We are not talking about 512-bit operands in this case, these
14276 // types are illegal.
14278 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14279 OpVT.getVectorElementType().getSizeInBits() >= 8))
14280 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14281 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14284 // Lower using XOP integer comparisons.
14285 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14286 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14287 // Translate compare code to XOP PCOM compare mode.
14288 unsigned CmpMode = 0;
14289 switch (SetCCOpcode) {
14290 default: llvm_unreachable("Unexpected SETCC condition");
14292 case ISD::SETLT: CmpMode = 0x00; break;
14294 case ISD::SETLE: CmpMode = 0x01; break;
14296 case ISD::SETGT: CmpMode = 0x02; break;
14298 case ISD::SETGE: CmpMode = 0x03; break;
14299 case ISD::SETEQ: CmpMode = 0x04; break;
14300 case ISD::SETNE: CmpMode = 0x05; break;
14303 // Are we comparing unsigned or signed integers?
14304 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14305 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14307 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14308 DAG.getConstant(CmpMode, dl, MVT::i8));
14311 // We are handling one of the integer comparisons here. Since SSE only has
14312 // GT and EQ comparisons for integer, swapping operands and multiple
14313 // operations may be required for some comparisons.
14315 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14316 bool Subus = false;
14318 switch (SetCCOpcode) {
14319 default: llvm_unreachable("Unexpected SETCC condition");
14320 case ISD::SETNE: Invert = true;
14321 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14322 case ISD::SETLT: Swap = true;
14323 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14324 case ISD::SETGE: Swap = true;
14325 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14326 Invert = true; break;
14327 case ISD::SETULT: Swap = true;
14328 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14329 FlipSigns = true; break;
14330 case ISD::SETUGE: Swap = true;
14331 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14332 FlipSigns = true; Invert = true; break;
14335 // Special case: Use min/max operations for SETULE/SETUGE
14336 MVT VET = VT.getVectorElementType();
14338 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14339 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14342 switch (SetCCOpcode) {
14344 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14345 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14348 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14351 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14352 if (!MinMax && hasSubus) {
14353 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14355 // t = psubus Op0, Op1
14356 // pcmpeq t, <0..0>
14357 switch (SetCCOpcode) {
14359 case ISD::SETULT: {
14360 // If the comparison is against a constant we can turn this into a
14361 // setule. With psubus, setule does not require a swap. This is
14362 // beneficial because the constant in the register is no longer
14363 // destructed as the destination so it can be hoisted out of a loop.
14364 // Only do this pre-AVX since vpcmp* is no longer destructive.
14365 if (Subtarget->hasAVX())
14367 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14368 if (ULEOp1.getNode()) {
14370 Subus = true; Invert = false; Swap = false;
14374 // Psubus is better than flip-sign because it requires no inversion.
14375 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14376 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14380 Opc = X86ISD::SUBUS;
14386 std::swap(Op0, Op1);
14388 // Check that the operation in question is available (most are plain SSE2,
14389 // but PCMPGTQ and PCMPEQQ have different requirements).
14390 if (VT == MVT::v2i64) {
14391 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14392 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14394 // First cast everything to the right type.
14395 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14396 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14398 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14399 // bits of the inputs before performing those operations. The lower
14400 // compare is always unsigned.
14403 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14405 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14406 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14407 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14408 Sign, Zero, Sign, Zero);
14410 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14411 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14413 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14414 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14415 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14417 // Create masks for only the low parts/high parts of the 64 bit integers.
14418 static const int MaskHi[] = { 1, 1, 3, 3 };
14419 static const int MaskLo[] = { 0, 0, 2, 2 };
14420 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14421 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14422 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14424 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14425 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14428 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14430 return DAG.getBitcast(VT, Result);
14433 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14434 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14435 // pcmpeqd + pshufd + pand.
14436 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14438 // First cast everything to the right type.
14439 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14440 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14443 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14445 // Make sure the lower and upper halves are both all-ones.
14446 static const int Mask[] = { 1, 0, 3, 2 };
14447 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14448 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14451 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14453 return DAG.getBitcast(VT, Result);
14457 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14458 // bits of the inputs before performing those operations.
14460 EVT EltVT = VT.getVectorElementType();
14461 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14463 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14464 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14467 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14469 // If the logical-not of the result is required, perform that now.
14471 Result = DAG.getNOT(dl, Result, VT);
14474 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14477 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14478 getZeroVector(VT, Subtarget, DAG, dl));
14483 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14485 MVT VT = Op.getSimpleValueType();
14487 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14489 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14490 && "SetCC type must be 8-bit or 1-bit integer");
14491 SDValue Op0 = Op.getOperand(0);
14492 SDValue Op1 = Op.getOperand(1);
14494 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14496 // Optimize to BT if possible.
14497 // Lower (X & (1 << N)) == 0 to BT(X, N).
14498 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14499 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14500 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14501 Op1.getOpcode() == ISD::Constant &&
14502 cast<ConstantSDNode>(Op1)->isNullValue() &&
14503 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14504 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14505 if (NewSetCC.getNode()) {
14507 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14512 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14514 if (Op1.getOpcode() == ISD::Constant &&
14515 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14516 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14517 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14519 // If the input is a setcc, then reuse the input setcc or use a new one with
14520 // the inverted condition.
14521 if (Op0.getOpcode() == X86ISD::SETCC) {
14522 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14523 bool Invert = (CC == ISD::SETNE) ^
14524 cast<ConstantSDNode>(Op1)->isNullValue();
14528 CCode = X86::GetOppositeBranchCondition(CCode);
14529 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14530 DAG.getConstant(CCode, dl, MVT::i8),
14531 Op0.getOperand(1));
14533 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14537 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14538 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14539 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14541 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14542 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14545 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14546 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14547 if (X86CC == X86::COND_INVALID)
14550 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14551 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14552 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14553 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14555 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14559 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14560 static bool isX86LogicalCmp(SDValue Op) {
14561 unsigned Opc = Op.getNode()->getOpcode();
14562 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14563 Opc == X86ISD::SAHF)
14565 if (Op.getResNo() == 1 &&
14566 (Opc == X86ISD::ADD ||
14567 Opc == X86ISD::SUB ||
14568 Opc == X86ISD::ADC ||
14569 Opc == X86ISD::SBB ||
14570 Opc == X86ISD::SMUL ||
14571 Opc == X86ISD::UMUL ||
14572 Opc == X86ISD::INC ||
14573 Opc == X86ISD::DEC ||
14574 Opc == X86ISD::OR ||
14575 Opc == X86ISD::XOR ||
14576 Opc == X86ISD::AND))
14579 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14585 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14586 if (V.getOpcode() != ISD::TRUNCATE)
14589 SDValue VOp0 = V.getOperand(0);
14590 unsigned InBits = VOp0.getValueSizeInBits();
14591 unsigned Bits = V.getValueSizeInBits();
14592 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14595 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14596 bool addTest = true;
14597 SDValue Cond = Op.getOperand(0);
14598 SDValue Op1 = Op.getOperand(1);
14599 SDValue Op2 = Op.getOperand(2);
14601 EVT VT = Op1.getValueType();
14604 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14605 // are available or VBLENDV if AVX is available.
14606 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14607 if (Cond.getOpcode() == ISD::SETCC &&
14608 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14609 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14610 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14611 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14612 int SSECC = translateX86FSETCC(
14613 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14616 if (Subtarget->hasAVX512()) {
14617 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14618 DAG.getConstant(SSECC, DL, MVT::i8));
14619 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14622 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14623 DAG.getConstant(SSECC, DL, MVT::i8));
14625 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14626 // of 3 logic instructions for size savings and potentially speed.
14627 // Unfortunately, there is no scalar form of VBLENDV.
14629 // If either operand is a constant, don't try this. We can expect to
14630 // optimize away at least one of the logic instructions later in that
14631 // case, so that sequence would be faster than a variable blend.
14633 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14634 // uses XMM0 as the selection register. That may need just as many
14635 // instructions as the AND/ANDN/OR sequence due to register moves, so
14638 if (Subtarget->hasAVX() &&
14639 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14641 // Convert to vectors, do a VSELECT, and convert back to scalar.
14642 // All of the conversions should be optimized away.
14644 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14645 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14646 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14647 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14649 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14650 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14652 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14654 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14655 VSel, DAG.getIntPtrConstant(0, DL));
14657 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14658 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14659 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14663 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14665 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14666 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14667 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14668 Op1Scalar = Op1.getOperand(0);
14670 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14671 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14672 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14673 Op2Scalar = Op2.getOperand(0);
14674 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14675 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14676 Op1Scalar.getValueType(),
14677 Cond, Op1Scalar, Op2Scalar);
14678 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14679 return DAG.getBitcast(VT, newSelect);
14680 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14681 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14682 DAG.getIntPtrConstant(0, DL));
14686 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14687 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14688 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14689 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14690 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14691 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14692 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14694 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14697 if (Cond.getOpcode() == ISD::SETCC) {
14698 SDValue NewCond = LowerSETCC(Cond, DAG);
14699 if (NewCond.getNode())
14703 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14704 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14705 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14706 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14707 if (Cond.getOpcode() == X86ISD::SETCC &&
14708 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14709 isZero(Cond.getOperand(1).getOperand(1))) {
14710 SDValue Cmp = Cond.getOperand(1);
14712 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14714 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14715 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14716 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14718 SDValue CmpOp0 = Cmp.getOperand(0);
14719 // Apply further optimizations for special cases
14720 // (select (x != 0), -1, 0) -> neg & sbb
14721 // (select (x == 0), 0, -1) -> neg & sbb
14722 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14723 if (YC->isNullValue() &&
14724 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14725 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14726 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14727 DAG.getConstant(0, DL,
14728 CmpOp0.getValueType()),
14730 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14731 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14732 SDValue(Neg.getNode(), 1));
14736 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14737 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14738 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14740 SDValue Res = // Res = 0 or -1.
14741 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14742 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14744 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14745 Res = DAG.getNOT(DL, Res, Res.getValueType());
14747 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14748 if (!N2C || !N2C->isNullValue())
14749 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14754 // Look past (and (setcc_carry (cmp ...)), 1).
14755 if (Cond.getOpcode() == ISD::AND &&
14756 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14758 if (C && C->getAPIntValue() == 1)
14759 Cond = Cond.getOperand(0);
14762 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14763 // setting operand in place of the X86ISD::SETCC.
14764 unsigned CondOpcode = Cond.getOpcode();
14765 if (CondOpcode == X86ISD::SETCC ||
14766 CondOpcode == X86ISD::SETCC_CARRY) {
14767 CC = Cond.getOperand(0);
14769 SDValue Cmp = Cond.getOperand(1);
14770 unsigned Opc = Cmp.getOpcode();
14771 MVT VT = Op.getSimpleValueType();
14773 bool IllegalFPCMov = false;
14774 if (VT.isFloatingPoint() && !VT.isVector() &&
14775 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14776 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14778 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14779 Opc == X86ISD::BT) { // FIXME
14783 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14784 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14785 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14786 Cond.getOperand(0).getValueType() != MVT::i8)) {
14787 SDValue LHS = Cond.getOperand(0);
14788 SDValue RHS = Cond.getOperand(1);
14789 unsigned X86Opcode;
14792 switch (CondOpcode) {
14793 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14794 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14795 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14796 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14797 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14798 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14799 default: llvm_unreachable("unexpected overflowing operator");
14801 if (CondOpcode == ISD::UMULO)
14802 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14805 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14807 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14809 if (CondOpcode == ISD::UMULO)
14810 Cond = X86Op.getValue(2);
14812 Cond = X86Op.getValue(1);
14814 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14819 // Look past the truncate if the high bits are known zero.
14820 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14821 Cond = Cond.getOperand(0);
14823 // We know the result of AND is compared against zero. Try to match
14825 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14826 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14827 if (NewSetCC.getNode()) {
14828 CC = NewSetCC.getOperand(0);
14829 Cond = NewSetCC.getOperand(1);
14836 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14837 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14840 // a < b ? -1 : 0 -> RES = ~setcc_carry
14841 // a < b ? 0 : -1 -> RES = setcc_carry
14842 // a >= b ? -1 : 0 -> RES = setcc_carry
14843 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14844 if (Cond.getOpcode() == X86ISD::SUB) {
14845 Cond = ConvertCmpIfNecessary(Cond, DAG);
14846 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14848 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14849 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14850 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14851 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14853 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14854 return DAG.getNOT(DL, Res, Res.getValueType());
14859 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14860 // widen the cmov and push the truncate through. This avoids introducing a new
14861 // branch during isel and doesn't add any extensions.
14862 if (Op.getValueType() == MVT::i8 &&
14863 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14864 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14865 if (T1.getValueType() == T2.getValueType() &&
14866 // Blacklist CopyFromReg to avoid partial register stalls.
14867 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14868 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14869 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14870 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14874 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14875 // condition is true.
14876 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14877 SDValue Ops[] = { Op2, Op1, CC, Cond };
14878 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14881 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14882 const X86Subtarget *Subtarget,
14883 SelectionDAG &DAG) {
14884 MVT VT = Op->getSimpleValueType(0);
14885 SDValue In = Op->getOperand(0);
14886 MVT InVT = In.getSimpleValueType();
14887 MVT VTElt = VT.getVectorElementType();
14888 MVT InVTElt = InVT.getVectorElementType();
14892 if ((InVTElt == MVT::i1) &&
14893 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14894 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14896 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14897 VTElt.getSizeInBits() <= 16)) ||
14899 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14900 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14902 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14903 VTElt.getSizeInBits() >= 32))))
14904 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14906 unsigned int NumElts = VT.getVectorNumElements();
14908 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14911 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14912 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14913 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14914 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14917 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14918 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14920 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14923 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14925 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14926 if (VT.is512BitVector())
14928 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14931 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14932 const X86Subtarget *Subtarget,
14933 SelectionDAG &DAG) {
14934 SDValue In = Op->getOperand(0);
14935 MVT VT = Op->getSimpleValueType(0);
14936 MVT InVT = In.getSimpleValueType();
14937 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14939 MVT InSVT = InVT.getScalarType();
14940 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14942 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14944 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14949 // SSE41 targets can use the pmovsx* instructions directly.
14950 if (Subtarget->hasSSE41())
14951 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14953 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14957 // As SRAI is only available on i16/i32 types, we expand only up to i32
14958 // and handle i64 separately.
14959 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14960 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14961 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14962 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14963 Curr = DAG.getBitcast(CurrVT, Curr);
14966 SDValue SignExt = Curr;
14967 if (CurrVT != InVT) {
14968 unsigned SignExtShift =
14969 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14970 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14971 DAG.getConstant(SignExtShift, dl, MVT::i8));
14977 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14978 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14979 DAG.getConstant(31, dl, MVT::i8));
14980 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14981 return DAG.getBitcast(VT, Ext);
14987 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14988 SelectionDAG &DAG) {
14989 MVT VT = Op->getSimpleValueType(0);
14990 SDValue In = Op->getOperand(0);
14991 MVT InVT = In.getSimpleValueType();
14994 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14995 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14997 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14998 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14999 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15002 if (Subtarget->hasInt256())
15003 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15005 // Optimize vectors in AVX mode
15006 // Sign extend v8i16 to v8i32 and
15009 // Divide input vector into two parts
15010 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15011 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15012 // concat the vectors to original VT
15014 unsigned NumElems = InVT.getVectorNumElements();
15015 SDValue Undef = DAG.getUNDEF(InVT);
15017 SmallVector<int,8> ShufMask1(NumElems, -1);
15018 for (unsigned i = 0; i != NumElems/2; ++i)
15021 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15023 SmallVector<int,8> ShufMask2(NumElems, -1);
15024 for (unsigned i = 0; i != NumElems/2; ++i)
15025 ShufMask2[i] = i + NumElems/2;
15027 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15029 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15030 VT.getVectorNumElements()/2);
15032 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15033 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15035 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15038 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15039 // may emit an illegal shuffle but the expansion is still better than scalar
15040 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15041 // we'll emit a shuffle and a arithmetic shift.
15042 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15043 // TODO: It is possible to support ZExt by zeroing the undef values during
15044 // the shuffle phase or after the shuffle.
15045 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15046 SelectionDAG &DAG) {
15047 MVT RegVT = Op.getSimpleValueType();
15048 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15049 assert(RegVT.isInteger() &&
15050 "We only custom lower integer vector sext loads.");
15052 // Nothing useful we can do without SSE2 shuffles.
15053 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15055 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15057 EVT MemVT = Ld->getMemoryVT();
15058 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15059 unsigned RegSz = RegVT.getSizeInBits();
15061 ISD::LoadExtType Ext = Ld->getExtensionType();
15063 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15064 && "Only anyext and sext are currently implemented.");
15065 assert(MemVT != RegVT && "Cannot extend to the same type");
15066 assert(MemVT.isVector() && "Must load a vector from memory");
15068 unsigned NumElems = RegVT.getVectorNumElements();
15069 unsigned MemSz = MemVT.getSizeInBits();
15070 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15072 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15073 // The only way in which we have a legal 256-bit vector result but not the
15074 // integer 256-bit operations needed to directly lower a sextload is if we
15075 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15076 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15077 // correctly legalized. We do this late to allow the canonical form of
15078 // sextload to persist throughout the rest of the DAG combiner -- it wants
15079 // to fold together any extensions it can, and so will fuse a sign_extend
15080 // of an sextload into a sextload targeting a wider value.
15082 if (MemSz == 128) {
15083 // Just switch this to a normal load.
15084 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15085 "it must be a legal 128-bit vector "
15087 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15088 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15089 Ld->isInvariant(), Ld->getAlignment());
15091 assert(MemSz < 128 &&
15092 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15093 // Do an sext load to a 128-bit vector type. We want to use the same
15094 // number of elements, but elements half as wide. This will end up being
15095 // recursively lowered by this routine, but will succeed as we definitely
15096 // have all the necessary features if we're using AVX1.
15098 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15099 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15101 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15102 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15103 Ld->isNonTemporal(), Ld->isInvariant(),
15104 Ld->getAlignment());
15107 // Replace chain users with the new chain.
15108 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15109 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15111 // Finally, do a normal sign-extend to the desired register.
15112 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15115 // All sizes must be a power of two.
15116 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15117 "Non-power-of-two elements are not custom lowered!");
15119 // Attempt to load the original value using scalar loads.
15120 // Find the largest scalar type that divides the total loaded size.
15121 MVT SclrLoadTy = MVT::i8;
15122 for (MVT Tp : MVT::integer_valuetypes()) {
15123 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15128 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15129 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15131 SclrLoadTy = MVT::f64;
15133 // Calculate the number of scalar loads that we need to perform
15134 // in order to load our vector from memory.
15135 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15137 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15138 "Can only lower sext loads with a single scalar load!");
15140 unsigned loadRegZize = RegSz;
15141 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15144 // Represent our vector as a sequence of elements which are the
15145 // largest scalar that we can load.
15146 EVT LoadUnitVecVT = EVT::getVectorVT(
15147 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15149 // Represent the data using the same element type that is stored in
15150 // memory. In practice, we ''widen'' MemVT.
15152 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15153 loadRegZize / MemVT.getScalarType().getSizeInBits());
15155 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15156 "Invalid vector type");
15158 // We can't shuffle using an illegal type.
15159 assert(TLI.isTypeLegal(WideVecVT) &&
15160 "We only lower types that form legal widened vector types");
15162 SmallVector<SDValue, 8> Chains;
15163 SDValue Ptr = Ld->getBasePtr();
15164 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15165 TLI.getPointerTy(DAG.getDataLayout()));
15166 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15168 for (unsigned i = 0; i < NumLoads; ++i) {
15169 // Perform a single load.
15170 SDValue ScalarLoad =
15171 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15172 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15173 Ld->getAlignment());
15174 Chains.push_back(ScalarLoad.getValue(1));
15175 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15176 // another round of DAGCombining.
15178 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15180 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15181 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15183 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15186 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15188 // Bitcast the loaded value to a vector of the original element type, in
15189 // the size of the target vector type.
15190 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15191 unsigned SizeRatio = RegSz / MemSz;
15193 if (Ext == ISD::SEXTLOAD) {
15194 // If we have SSE4.1, we can directly emit a VSEXT node.
15195 if (Subtarget->hasSSE41()) {
15196 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15197 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15201 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15203 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15204 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15206 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15207 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15211 // Redistribute the loaded elements into the different locations.
15212 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15213 for (unsigned i = 0; i != NumElems; ++i)
15214 ShuffleVec[i * SizeRatio] = i;
15216 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15217 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15219 // Bitcast to the requested type.
15220 Shuff = DAG.getBitcast(RegVT, Shuff);
15221 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15225 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15226 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15227 // from the AND / OR.
15228 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15229 Opc = Op.getOpcode();
15230 if (Opc != ISD::OR && Opc != ISD::AND)
15232 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15233 Op.getOperand(0).hasOneUse() &&
15234 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15235 Op.getOperand(1).hasOneUse());
15238 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15239 // 1 and that the SETCC node has a single use.
15240 static bool isXor1OfSetCC(SDValue Op) {
15241 if (Op.getOpcode() != ISD::XOR)
15243 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15244 if (N1C && N1C->getAPIntValue() == 1) {
15245 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15246 Op.getOperand(0).hasOneUse();
15251 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15252 bool addTest = true;
15253 SDValue Chain = Op.getOperand(0);
15254 SDValue Cond = Op.getOperand(1);
15255 SDValue Dest = Op.getOperand(2);
15258 bool Inverted = false;
15260 if (Cond.getOpcode() == ISD::SETCC) {
15261 // Check for setcc([su]{add,sub,mul}o == 0).
15262 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15263 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15264 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15265 Cond.getOperand(0).getResNo() == 1 &&
15266 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15267 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15268 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15269 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15270 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15271 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15273 Cond = Cond.getOperand(0);
15275 SDValue NewCond = LowerSETCC(Cond, DAG);
15276 if (NewCond.getNode())
15281 // FIXME: LowerXALUO doesn't handle these!!
15282 else if (Cond.getOpcode() == X86ISD::ADD ||
15283 Cond.getOpcode() == X86ISD::SUB ||
15284 Cond.getOpcode() == X86ISD::SMUL ||
15285 Cond.getOpcode() == X86ISD::UMUL)
15286 Cond = LowerXALUO(Cond, DAG);
15289 // Look pass (and (setcc_carry (cmp ...)), 1).
15290 if (Cond.getOpcode() == ISD::AND &&
15291 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15292 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15293 if (C && C->getAPIntValue() == 1)
15294 Cond = Cond.getOperand(0);
15297 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15298 // setting operand in place of the X86ISD::SETCC.
15299 unsigned CondOpcode = Cond.getOpcode();
15300 if (CondOpcode == X86ISD::SETCC ||
15301 CondOpcode == X86ISD::SETCC_CARRY) {
15302 CC = Cond.getOperand(0);
15304 SDValue Cmp = Cond.getOperand(1);
15305 unsigned Opc = Cmp.getOpcode();
15306 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15307 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15311 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15315 // These can only come from an arithmetic instruction with overflow,
15316 // e.g. SADDO, UADDO.
15317 Cond = Cond.getNode()->getOperand(1);
15323 CondOpcode = Cond.getOpcode();
15324 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15325 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15326 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15327 Cond.getOperand(0).getValueType() != MVT::i8)) {
15328 SDValue LHS = Cond.getOperand(0);
15329 SDValue RHS = Cond.getOperand(1);
15330 unsigned X86Opcode;
15333 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15334 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15336 switch (CondOpcode) {
15337 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15339 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15341 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15344 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15345 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15347 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15349 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15352 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15353 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15354 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15355 default: llvm_unreachable("unexpected overflowing operator");
15358 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15359 if (CondOpcode == ISD::UMULO)
15360 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15363 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15365 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15367 if (CondOpcode == ISD::UMULO)
15368 Cond = X86Op.getValue(2);
15370 Cond = X86Op.getValue(1);
15372 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15376 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15377 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15378 if (CondOpc == ISD::OR) {
15379 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15380 // two branches instead of an explicit OR instruction with a
15382 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15383 isX86LogicalCmp(Cmp)) {
15384 CC = Cond.getOperand(0).getOperand(0);
15385 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15386 Chain, Dest, CC, Cmp);
15387 CC = Cond.getOperand(1).getOperand(0);
15391 } else { // ISD::AND
15392 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15393 // two branches instead of an explicit AND instruction with a
15394 // separate test. However, we only do this if this block doesn't
15395 // have a fall-through edge, because this requires an explicit
15396 // jmp when the condition is false.
15397 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15398 isX86LogicalCmp(Cmp) &&
15399 Op.getNode()->hasOneUse()) {
15400 X86::CondCode CCode =
15401 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15402 CCode = X86::GetOppositeBranchCondition(CCode);
15403 CC = DAG.getConstant(CCode, dl, MVT::i8);
15404 SDNode *User = *Op.getNode()->use_begin();
15405 // Look for an unconditional branch following this conditional branch.
15406 // We need this because we need to reverse the successors in order
15407 // to implement FCMP_OEQ.
15408 if (User->getOpcode() == ISD::BR) {
15409 SDValue FalseBB = User->getOperand(1);
15411 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15412 assert(NewBR == User);
15416 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15417 Chain, Dest, CC, Cmp);
15418 X86::CondCode CCode =
15419 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15420 CCode = X86::GetOppositeBranchCondition(CCode);
15421 CC = DAG.getConstant(CCode, dl, MVT::i8);
15427 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15428 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15429 // It should be transformed during dag combiner except when the condition
15430 // is set by a arithmetics with overflow node.
15431 X86::CondCode CCode =
15432 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15433 CCode = X86::GetOppositeBranchCondition(CCode);
15434 CC = DAG.getConstant(CCode, dl, MVT::i8);
15435 Cond = Cond.getOperand(0).getOperand(1);
15437 } else if (Cond.getOpcode() == ISD::SETCC &&
15438 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15439 // For FCMP_OEQ, we can emit
15440 // two branches instead of an explicit AND instruction with a
15441 // separate test. However, we only do this if this block doesn't
15442 // have a fall-through edge, because this requires an explicit
15443 // jmp when the condition is false.
15444 if (Op.getNode()->hasOneUse()) {
15445 SDNode *User = *Op.getNode()->use_begin();
15446 // Look for an unconditional branch following this conditional branch.
15447 // We need this because we need to reverse the successors in order
15448 // to implement FCMP_OEQ.
15449 if (User->getOpcode() == ISD::BR) {
15450 SDValue FalseBB = User->getOperand(1);
15452 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15453 assert(NewBR == User);
15457 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15458 Cond.getOperand(0), Cond.getOperand(1));
15459 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15460 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15461 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15462 Chain, Dest, CC, Cmp);
15463 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15468 } else if (Cond.getOpcode() == ISD::SETCC &&
15469 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15470 // For FCMP_UNE, we can emit
15471 // two branches instead of an explicit AND instruction with a
15472 // separate test. However, we only do this if this block doesn't
15473 // have a fall-through edge, because this requires an explicit
15474 // jmp when the condition is false.
15475 if (Op.getNode()->hasOneUse()) {
15476 SDNode *User = *Op.getNode()->use_begin();
15477 // Look for an unconditional branch following this conditional branch.
15478 // We need this because we need to reverse the successors in order
15479 // to implement FCMP_UNE.
15480 if (User->getOpcode() == ISD::BR) {
15481 SDValue FalseBB = User->getOperand(1);
15483 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15484 assert(NewBR == User);
15487 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15488 Cond.getOperand(0), Cond.getOperand(1));
15489 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15490 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15491 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15492 Chain, Dest, CC, Cmp);
15493 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15503 // Look pass the truncate if the high bits are known zero.
15504 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15505 Cond = Cond.getOperand(0);
15507 // We know the result of AND is compared against zero. Try to match
15509 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15510 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15511 if (NewSetCC.getNode()) {
15512 CC = NewSetCC.getOperand(0);
15513 Cond = NewSetCC.getOperand(1);
15520 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15521 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15522 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15524 Cond = ConvertCmpIfNecessary(Cond, DAG);
15525 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15526 Chain, Dest, CC, Cond);
15529 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15530 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15531 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15532 // that the guard pages used by the OS virtual memory manager are allocated in
15533 // correct sequence.
15535 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15536 SelectionDAG &DAG) const {
15537 MachineFunction &MF = DAG.getMachineFunction();
15538 bool SplitStack = MF.shouldSplitStack();
15539 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15545 SDNode* Node = Op.getNode();
15547 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15548 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15549 " not tell us which reg is the stack pointer!");
15550 EVT VT = Node->getValueType(0);
15551 SDValue Tmp1 = SDValue(Node, 0);
15552 SDValue Tmp2 = SDValue(Node, 1);
15553 SDValue Tmp3 = Node->getOperand(2);
15554 SDValue Chain = Tmp1.getOperand(0);
15556 // Chain the dynamic stack allocation so that it doesn't modify the stack
15557 // pointer when other instructions are using the stack.
15558 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15561 SDValue Size = Tmp2.getOperand(1);
15562 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15563 Chain = SP.getValue(1);
15564 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15565 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15566 unsigned StackAlign = TFI.getStackAlignment();
15567 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15568 if (Align > StackAlign)
15569 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15570 DAG.getConstant(-(uint64_t)Align, dl, VT));
15571 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15573 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15574 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15577 SDValue Ops[2] = { Tmp1, Tmp2 };
15578 return DAG.getMergeValues(Ops, dl);
15582 SDValue Chain = Op.getOperand(0);
15583 SDValue Size = Op.getOperand(1);
15584 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15585 EVT VT = Op.getNode()->getValueType(0);
15587 bool Is64Bit = Subtarget->is64Bit();
15588 MVT SPTy = getPointerTy(DAG.getDataLayout());
15591 MachineRegisterInfo &MRI = MF.getRegInfo();
15594 // The 64 bit implementation of segmented stacks needs to clobber both r10
15595 // r11. This makes it impossible to use it along with nested parameters.
15596 const Function *F = MF.getFunction();
15598 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15600 if (I->hasNestAttr())
15601 report_fatal_error("Cannot use segmented stacks with functions that "
15602 "have nested arguments.");
15605 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15606 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15607 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15608 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15609 DAG.getRegister(Vreg, SPTy));
15610 SDValue Ops1[2] = { Value, Chain };
15611 return DAG.getMergeValues(Ops1, dl);
15614 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15616 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15617 Flag = Chain.getValue(1);
15618 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15620 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15622 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15623 unsigned SPReg = RegInfo->getStackRegister();
15624 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15625 Chain = SP.getValue(1);
15628 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15629 DAG.getConstant(-(uint64_t)Align, dl, VT));
15630 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15633 SDValue Ops1[2] = { SP, Chain };
15634 return DAG.getMergeValues(Ops1, dl);
15638 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15639 MachineFunction &MF = DAG.getMachineFunction();
15640 auto PtrVT = getPointerTy(MF.getDataLayout());
15641 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15643 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15646 if (!Subtarget->is64Bit() ||
15647 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15648 // vastart just stores the address of the VarArgsFrameIndex slot into the
15649 // memory location argument.
15650 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15651 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15652 MachinePointerInfo(SV), false, false, 0);
15656 // gp_offset (0 - 6 * 8)
15657 // fp_offset (48 - 48 + 8 * 16)
15658 // overflow_arg_area (point to parameters coming in memory).
15660 SmallVector<SDValue, 8> MemOps;
15661 SDValue FIN = Op.getOperand(1);
15663 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15664 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15666 FIN, MachinePointerInfo(SV), false, false, 0);
15667 MemOps.push_back(Store);
15670 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15671 Store = DAG.getStore(Op.getOperand(0), DL,
15672 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15674 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15675 MemOps.push_back(Store);
15677 // Store ptr to overflow_arg_area
15678 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15679 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15680 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15681 MachinePointerInfo(SV, 8),
15683 MemOps.push_back(Store);
15685 // Store ptr to reg_save_area.
15686 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15687 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15688 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15689 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15690 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15691 MemOps.push_back(Store);
15692 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15695 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15696 assert(Subtarget->is64Bit() &&
15697 "LowerVAARG only handles 64-bit va_arg!");
15698 assert(Op.getNode()->getNumOperands() == 4);
15700 MachineFunction &MF = DAG.getMachineFunction();
15701 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15702 // The Win64 ABI uses char* instead of a structure.
15703 return DAG.expandVAArg(Op.getNode());
15705 SDValue Chain = Op.getOperand(0);
15706 SDValue SrcPtr = Op.getOperand(1);
15707 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15708 unsigned Align = Op.getConstantOperandVal(3);
15711 EVT ArgVT = Op.getNode()->getValueType(0);
15712 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15713 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15716 // Decide which area this value should be read from.
15717 // TODO: Implement the AMD64 ABI in its entirety. This simple
15718 // selection mechanism works only for the basic types.
15719 if (ArgVT == MVT::f80) {
15720 llvm_unreachable("va_arg for f80 not yet implemented");
15721 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15722 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15723 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15724 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15726 llvm_unreachable("Unhandled argument type in LowerVAARG");
15729 if (ArgMode == 2) {
15730 // Sanity Check: Make sure using fp_offset makes sense.
15731 assert(!Subtarget->useSoftFloat() &&
15732 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15733 Subtarget->hasSSE1());
15736 // Insert VAARG_64 node into the DAG
15737 // VAARG_64 returns two values: Variable Argument Address, Chain
15738 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15739 DAG.getConstant(ArgMode, dl, MVT::i8),
15740 DAG.getConstant(Align, dl, MVT::i32)};
15741 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15742 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15743 VTs, InstOps, MVT::i64,
15744 MachinePointerInfo(SV),
15746 /*Volatile=*/false,
15748 /*WriteMem=*/true);
15749 Chain = VAARG.getValue(1);
15751 // Load the next argument and return it
15752 return DAG.getLoad(ArgVT, dl,
15755 MachinePointerInfo(),
15756 false, false, false, 0);
15759 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15760 SelectionDAG &DAG) {
15761 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15762 // where a va_list is still an i8*.
15763 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15764 if (Subtarget->isCallingConvWin64(
15765 DAG.getMachineFunction().getFunction()->getCallingConv()))
15766 // Probably a Win64 va_copy.
15767 return DAG.expandVACopy(Op.getNode());
15769 SDValue Chain = Op.getOperand(0);
15770 SDValue DstPtr = Op.getOperand(1);
15771 SDValue SrcPtr = Op.getOperand(2);
15772 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15773 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15776 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15777 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15779 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15782 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15783 // amount is a constant. Takes immediate version of shift as input.
15784 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15785 SDValue SrcOp, uint64_t ShiftAmt,
15786 SelectionDAG &DAG) {
15787 MVT ElementType = VT.getVectorElementType();
15789 // Fold this packed shift into its first operand if ShiftAmt is 0.
15793 // Check for ShiftAmt >= element width
15794 if (ShiftAmt >= ElementType.getSizeInBits()) {
15795 if (Opc == X86ISD::VSRAI)
15796 ShiftAmt = ElementType.getSizeInBits() - 1;
15798 return DAG.getConstant(0, dl, VT);
15801 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15802 && "Unknown target vector shift-by-constant node");
15804 // Fold this packed vector shift into a build vector if SrcOp is a
15805 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15806 if (VT == SrcOp.getSimpleValueType() &&
15807 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15808 SmallVector<SDValue, 8> Elts;
15809 unsigned NumElts = SrcOp->getNumOperands();
15810 ConstantSDNode *ND;
15813 default: llvm_unreachable(nullptr);
15814 case X86ISD::VSHLI:
15815 for (unsigned i=0; i!=NumElts; ++i) {
15816 SDValue CurrentOp = SrcOp->getOperand(i);
15817 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15818 Elts.push_back(CurrentOp);
15821 ND = cast<ConstantSDNode>(CurrentOp);
15822 const APInt &C = ND->getAPIntValue();
15823 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15826 case X86ISD::VSRLI:
15827 for (unsigned i=0; i!=NumElts; ++i) {
15828 SDValue CurrentOp = SrcOp->getOperand(i);
15829 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15830 Elts.push_back(CurrentOp);
15833 ND = cast<ConstantSDNode>(CurrentOp);
15834 const APInt &C = ND->getAPIntValue();
15835 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15838 case X86ISD::VSRAI:
15839 for (unsigned i=0; i!=NumElts; ++i) {
15840 SDValue CurrentOp = SrcOp->getOperand(i);
15841 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15842 Elts.push_back(CurrentOp);
15845 ND = cast<ConstantSDNode>(CurrentOp);
15846 const APInt &C = ND->getAPIntValue();
15847 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15852 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15855 return DAG.getNode(Opc, dl, VT, SrcOp,
15856 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15859 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15860 // may or may not be a constant. Takes immediate version of shift as input.
15861 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15862 SDValue SrcOp, SDValue ShAmt,
15863 SelectionDAG &DAG) {
15864 MVT SVT = ShAmt.getSimpleValueType();
15865 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15867 // Catch shift-by-constant.
15868 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15869 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15870 CShAmt->getZExtValue(), DAG);
15872 // Change opcode to non-immediate version
15874 default: llvm_unreachable("Unknown target vector shift node");
15875 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15876 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15877 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15880 const X86Subtarget &Subtarget =
15881 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15882 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15883 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15884 // Let the shuffle legalizer expand this shift amount node.
15885 SDValue Op0 = ShAmt.getOperand(0);
15886 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15887 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15889 // Need to build a vector containing shift amount.
15890 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15891 SmallVector<SDValue, 4> ShOps;
15892 ShOps.push_back(ShAmt);
15893 if (SVT == MVT::i32) {
15894 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15895 ShOps.push_back(DAG.getUNDEF(SVT));
15897 ShOps.push_back(DAG.getUNDEF(SVT));
15899 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15900 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15903 // The return type has to be a 128-bit type with the same element
15904 // type as the input type.
15905 MVT EltVT = VT.getVectorElementType();
15906 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15908 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15909 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15912 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15913 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15914 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15915 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15916 SDValue PreservedSrc,
15917 const X86Subtarget *Subtarget,
15918 SelectionDAG &DAG) {
15919 EVT VT = Op.getValueType();
15920 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15921 MVT::i1, VT.getVectorNumElements());
15922 SDValue VMask = SDValue();
15923 unsigned OpcodeSelect = ISD::VSELECT;
15926 assert(MaskVT.isSimple() && "invalid mask type");
15928 if (isAllOnes(Mask))
15931 if (MaskVT.bitsGT(Mask.getValueType())) {
15932 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15933 MaskVT.getSizeInBits());
15934 VMask = DAG.getBitcast(MaskVT,
15935 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15937 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15938 Mask.getValueType().getSizeInBits());
15939 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15940 // are extracted by EXTRACT_SUBVECTOR.
15941 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15942 DAG.getBitcast(BitcastVT, Mask),
15943 DAG.getIntPtrConstant(0, dl));
15946 switch (Op.getOpcode()) {
15948 case X86ISD::PCMPEQM:
15949 case X86ISD::PCMPGTM:
15951 case X86ISD::CMPMU:
15952 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15953 case X86ISD::VFPCLASS:
15954 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15955 case X86ISD::VTRUNC:
15956 case X86ISD::VTRUNCS:
15957 case X86ISD::VTRUNCUS:
15958 // We can't use ISD::VSELECT here because it is not always "Legal"
15959 // for the destination type. For example vpmovqb require only AVX512
15960 // and vselect that can operate on byte element type require BWI
15961 OpcodeSelect = X86ISD::SELECT;
15964 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15965 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15966 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15969 /// \brief Creates an SDNode for a predicated scalar operation.
15970 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15971 /// The mask is coming as MVT::i8 and it should be truncated
15972 /// to MVT::i1 while lowering masking intrinsics.
15973 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15974 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15975 /// for a scalar instruction.
15976 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15977 SDValue PreservedSrc,
15978 const X86Subtarget *Subtarget,
15979 SelectionDAG &DAG) {
15980 if (isAllOnes(Mask))
15983 EVT VT = Op.getValueType();
15985 // The mask should be of type MVT::i1
15986 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15988 if (Op.getOpcode() == X86ISD::FSETCC)
15989 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15991 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15992 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15993 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15996 static int getSEHRegistrationNodeSize(const Function *Fn) {
15997 if (!Fn->hasPersonalityFn())
15998 report_fatal_error(
15999 "querying registration node size for function without personality");
16000 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16001 // WinEHStatePass for the full struct definition.
16002 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16003 case EHPersonality::MSVC_X86SEH: return 24;
16004 case EHPersonality::MSVC_CXX: return 16;
16007 report_fatal_error("can only recover FP for MSVC EH personality functions");
16010 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16011 /// function or when returning to a parent frame after catching an exception, we
16012 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16013 /// Here's the math:
16014 /// RegNodeBase = EntryEBP - RegNodeSize
16015 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16016 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16017 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16018 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16019 SDValue EntryEBP) {
16020 MachineFunction &MF = DAG.getMachineFunction();
16023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16024 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16026 // It's possible that the parent function no longer has a personality function
16027 // if the exceptional code was optimized away, in which case we just return
16028 // the incoming EBP.
16029 if (!Fn->hasPersonalityFn())
16032 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16034 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16036 MCSymbol *OffsetSym =
16037 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16038 GlobalValue::getRealLinkageName(Fn->getName()));
16039 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16040 SDValue RegNodeFrameOffset =
16041 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16043 // RegNodeBase = EntryEBP - RegNodeSize
16044 // ParentFP = RegNodeBase - RegNodeFrameOffset
16045 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16046 DAG.getConstant(RegNodeSize, dl, PtrVT));
16047 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16050 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16051 SelectionDAG &DAG) {
16053 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16054 EVT VT = Op.getValueType();
16055 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16057 switch(IntrData->Type) {
16058 case INTR_TYPE_1OP:
16059 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16060 case INTR_TYPE_2OP:
16061 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16063 case INTR_TYPE_2OP_IMM8:
16064 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16065 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16066 case INTR_TYPE_3OP:
16067 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16068 Op.getOperand(2), Op.getOperand(3));
16069 case INTR_TYPE_4OP:
16070 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16071 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16072 case INTR_TYPE_1OP_MASK_RM: {
16073 SDValue Src = Op.getOperand(1);
16074 SDValue PassThru = Op.getOperand(2);
16075 SDValue Mask = Op.getOperand(3);
16076 SDValue RoundingMode;
16077 // We allways add rounding mode to the Node.
16078 // If the rounding mode is not specified, we add the
16079 // "current direction" mode.
16080 if (Op.getNumOperands() == 4)
16082 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16084 RoundingMode = Op.getOperand(4);
16085 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16086 if (IntrWithRoundingModeOpcode != 0)
16087 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16088 X86::STATIC_ROUNDING::CUR_DIRECTION)
16089 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16090 dl, Op.getValueType(), Src, RoundingMode),
16091 Mask, PassThru, Subtarget, DAG);
16092 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16094 Mask, PassThru, Subtarget, DAG);
16096 case INTR_TYPE_1OP_MASK: {
16097 SDValue Src = Op.getOperand(1);
16098 SDValue PassThru = Op.getOperand(2);
16099 SDValue Mask = Op.getOperand(3);
16100 // We add rounding mode to the Node when
16101 // - RM Opcode is specified and
16102 // - RM is not "current direction".
16103 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16104 if (IntrWithRoundingModeOpcode != 0) {
16105 SDValue Rnd = Op.getOperand(4);
16106 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16107 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16108 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16109 dl, Op.getValueType(),
16111 Mask, PassThru, Subtarget, DAG);
16114 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16115 Mask, PassThru, Subtarget, DAG);
16117 case INTR_TYPE_SCALAR_MASK: {
16118 SDValue Src1 = Op.getOperand(1);
16119 SDValue Src2 = Op.getOperand(2);
16120 SDValue passThru = Op.getOperand(3);
16121 SDValue Mask = Op.getOperand(4);
16122 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16123 Mask, passThru, Subtarget, DAG);
16125 case INTR_TYPE_SCALAR_MASK_RM: {
16126 SDValue Src1 = Op.getOperand(1);
16127 SDValue Src2 = Op.getOperand(2);
16128 SDValue Src0 = Op.getOperand(3);
16129 SDValue Mask = Op.getOperand(4);
16130 // There are 2 kinds of intrinsics in this group:
16131 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16132 // (2) With rounding mode and sae - 7 operands.
16133 if (Op.getNumOperands() == 6) {
16134 SDValue Sae = Op.getOperand(5);
16135 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16136 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16138 Mask, Src0, Subtarget, DAG);
16140 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16141 SDValue RoundingMode = Op.getOperand(5);
16142 SDValue Sae = Op.getOperand(6);
16143 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16144 RoundingMode, Sae),
16145 Mask, Src0, Subtarget, DAG);
16147 case INTR_TYPE_2OP_MASK:
16148 case INTR_TYPE_2OP_IMM8_MASK: {
16149 SDValue Src1 = Op.getOperand(1);
16150 SDValue Src2 = Op.getOperand(2);
16151 SDValue PassThru = Op.getOperand(3);
16152 SDValue Mask = Op.getOperand(4);
16154 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16155 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16157 // We specify 2 possible opcodes for intrinsics with rounding modes.
16158 // First, we check if the intrinsic may have non-default rounding mode,
16159 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16160 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16161 if (IntrWithRoundingModeOpcode != 0) {
16162 SDValue Rnd = Op.getOperand(5);
16163 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16164 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16165 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16166 dl, Op.getValueType(),
16168 Mask, PassThru, Subtarget, DAG);
16171 // TODO: Intrinsics should have fast-math-flags to propagate.
16172 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16173 Mask, PassThru, Subtarget, DAG);
16175 case INTR_TYPE_2OP_MASK_RM: {
16176 SDValue Src1 = Op.getOperand(1);
16177 SDValue Src2 = Op.getOperand(2);
16178 SDValue PassThru = Op.getOperand(3);
16179 SDValue Mask = Op.getOperand(4);
16180 // We specify 2 possible modes for intrinsics, with/without rounding
16182 // First, we check if the intrinsic have rounding mode (6 operands),
16183 // if not, we set rounding mode to "current".
16185 if (Op.getNumOperands() == 6)
16186 Rnd = Op.getOperand(5);
16188 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16189 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16191 Mask, PassThru, Subtarget, DAG);
16193 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16194 SDValue Src1 = Op.getOperand(1);
16195 SDValue Src2 = Op.getOperand(2);
16196 SDValue Src3 = Op.getOperand(3);
16197 SDValue PassThru = Op.getOperand(4);
16198 SDValue Mask = Op.getOperand(5);
16199 SDValue Sae = Op.getOperand(6);
16201 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16203 Mask, PassThru, Subtarget, DAG);
16205 case INTR_TYPE_3OP_MASK_RM: {
16206 SDValue Src1 = Op.getOperand(1);
16207 SDValue Src2 = Op.getOperand(2);
16208 SDValue Imm = Op.getOperand(3);
16209 SDValue PassThru = Op.getOperand(4);
16210 SDValue Mask = Op.getOperand(5);
16211 // We specify 2 possible modes for intrinsics, with/without rounding
16213 // First, we check if the intrinsic have rounding mode (7 operands),
16214 // if not, we set rounding mode to "current".
16216 if (Op.getNumOperands() == 7)
16217 Rnd = Op.getOperand(6);
16219 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16220 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16221 Src1, Src2, Imm, Rnd),
16222 Mask, PassThru, Subtarget, DAG);
16224 case INTR_TYPE_3OP_IMM8_MASK:
16225 case INTR_TYPE_3OP_MASK:
16226 case INSERT_SUBVEC: {
16227 SDValue Src1 = Op.getOperand(1);
16228 SDValue Src2 = Op.getOperand(2);
16229 SDValue Src3 = Op.getOperand(3);
16230 SDValue PassThru = Op.getOperand(4);
16231 SDValue Mask = Op.getOperand(5);
16233 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16234 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16235 else if (IntrData->Type == INSERT_SUBVEC) {
16236 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16237 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16238 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16239 Imm *= Src2.getValueType().getVectorNumElements();
16240 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16243 // We specify 2 possible opcodes for intrinsics with rounding modes.
16244 // First, we check if the intrinsic may have non-default rounding mode,
16245 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16246 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16247 if (IntrWithRoundingModeOpcode != 0) {
16248 SDValue Rnd = Op.getOperand(6);
16249 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16250 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16251 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16252 dl, Op.getValueType(),
16253 Src1, Src2, Src3, Rnd),
16254 Mask, PassThru, Subtarget, DAG);
16257 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16259 Mask, PassThru, Subtarget, DAG);
16261 case VPERM_3OP_MASKZ:
16262 case VPERM_3OP_MASK:
16265 case FMA_OP_MASK: {
16266 SDValue Src1 = Op.getOperand(1);
16267 SDValue Src2 = Op.getOperand(2);
16268 SDValue Src3 = Op.getOperand(3);
16269 SDValue Mask = Op.getOperand(4);
16270 EVT VT = Op.getValueType();
16271 SDValue PassThru = SDValue();
16273 // set PassThru element
16274 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16275 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16276 else if (IntrData->Type == FMA_OP_MASK3)
16281 // We specify 2 possible opcodes for intrinsics with rounding modes.
16282 // First, we check if the intrinsic may have non-default rounding mode,
16283 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16284 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16285 if (IntrWithRoundingModeOpcode != 0) {
16286 SDValue Rnd = Op.getOperand(5);
16287 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16288 X86::STATIC_ROUNDING::CUR_DIRECTION)
16289 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16290 dl, Op.getValueType(),
16291 Src1, Src2, Src3, Rnd),
16292 Mask, PassThru, Subtarget, DAG);
16294 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16295 dl, Op.getValueType(),
16297 Mask, PassThru, Subtarget, DAG);
16299 case TERLOG_OP_MASK:
16300 case TERLOG_OP_MASKZ: {
16301 SDValue Src1 = Op.getOperand(1);
16302 SDValue Src2 = Op.getOperand(2);
16303 SDValue Src3 = Op.getOperand(3);
16304 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16305 SDValue Mask = Op.getOperand(5);
16306 EVT VT = Op.getValueType();
16307 SDValue PassThru = Src1;
16308 // Set PassThru element.
16309 if (IntrData->Type == TERLOG_OP_MASKZ)
16310 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16312 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16313 Src1, Src2, Src3, Src4),
16314 Mask, PassThru, Subtarget, DAG);
16317 // FPclass intrinsics with mask
16318 SDValue Src1 = Op.getOperand(1);
16319 EVT VT = Src1.getValueType();
16320 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16321 VT.getVectorNumElements());
16322 SDValue Imm = Op.getOperand(2);
16323 SDValue Mask = Op.getOperand(3);
16324 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16325 Mask.getValueType().getSizeInBits());
16326 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16327 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16328 DAG.getTargetConstant(0, dl, MaskVT),
16330 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16331 DAG.getUNDEF(BitcastVT), FPclassMask,
16332 DAG.getIntPtrConstant(0, dl));
16333 return DAG.getBitcast(Op.getValueType(), Res);
16336 case CMP_MASK_CC: {
16337 // Comparison intrinsics with masks.
16338 // Example of transformation:
16339 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16340 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16342 // (v8i1 (insert_subvector undef,
16343 // (v2i1 (and (PCMPEQM %a, %b),
16344 // (extract_subvector
16345 // (v8i1 (bitcast %mask)), 0))), 0))))
16346 EVT VT = Op.getOperand(1).getValueType();
16347 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16348 VT.getVectorNumElements());
16349 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16350 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16351 Mask.getValueType().getSizeInBits());
16353 if (IntrData->Type == CMP_MASK_CC) {
16354 SDValue CC = Op.getOperand(3);
16355 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16356 // We specify 2 possible opcodes for intrinsics with rounding modes.
16357 // First, we check if the intrinsic may have non-default rounding mode,
16358 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16359 if (IntrData->Opc1 != 0) {
16360 SDValue Rnd = Op.getOperand(5);
16361 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16362 X86::STATIC_ROUNDING::CUR_DIRECTION)
16363 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16364 Op.getOperand(2), CC, Rnd);
16366 //default rounding mode
16368 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16369 Op.getOperand(2), CC);
16372 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16373 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16376 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16377 DAG.getTargetConstant(0, dl,
16380 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16381 DAG.getUNDEF(BitcastVT), CmpMask,
16382 DAG.getIntPtrConstant(0, dl));
16383 return DAG.getBitcast(Op.getValueType(), Res);
16385 case CMP_MASK_SCALAR_CC: {
16386 SDValue Src1 = Op.getOperand(1);
16387 SDValue Src2 = Op.getOperand(2);
16388 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16389 SDValue Mask = Op.getOperand(4);
16392 if (IntrData->Opc1 != 0) {
16393 SDValue Rnd = Op.getOperand(5);
16394 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16395 X86::STATIC_ROUNDING::CUR_DIRECTION)
16396 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16398 //default rounding mode
16400 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16402 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16403 DAG.getTargetConstant(0, dl,
16407 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16408 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16409 DAG.getValueType(MVT::i1));
16411 case COMI: { // Comparison intrinsics
16412 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16413 SDValue LHS = Op.getOperand(1);
16414 SDValue RHS = Op.getOperand(2);
16415 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16416 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16417 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16418 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16419 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16420 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16423 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16424 Op.getOperand(1), Op.getOperand(2), DAG);
16426 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16427 Op.getSimpleValueType(),
16429 Op.getOperand(2), DAG),
16430 Op.getOperand(4), Op.getOperand(3), Subtarget,
16432 case COMPRESS_EXPAND_IN_REG: {
16433 SDValue Mask = Op.getOperand(3);
16434 SDValue DataToCompress = Op.getOperand(1);
16435 SDValue PassThru = Op.getOperand(2);
16436 if (isAllOnes(Mask)) // return data as is
16437 return Op.getOperand(1);
16439 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16441 Mask, PassThru, Subtarget, DAG);
16444 SDValue Mask = Op.getOperand(3);
16445 EVT VT = Op.getValueType();
16446 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16447 VT.getVectorNumElements());
16448 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16449 Mask.getValueType().getSizeInBits());
16451 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16452 DAG.getBitcast(BitcastVT, Mask),
16453 DAG.getIntPtrConstant(0, dl));
16454 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16463 default: return SDValue(); // Don't custom lower most intrinsics.
16465 case Intrinsic::x86_avx2_permd:
16466 case Intrinsic::x86_avx2_permps:
16467 // Operands intentionally swapped. Mask is last operand to intrinsic,
16468 // but second operand for node/instruction.
16469 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16470 Op.getOperand(2), Op.getOperand(1));
16472 // ptest and testp intrinsics. The intrinsic these come from are designed to
16473 // return an integer value, not just an instruction so lower it to the ptest
16474 // or testp pattern and a setcc for the result.
16475 case Intrinsic::x86_sse41_ptestz:
16476 case Intrinsic::x86_sse41_ptestc:
16477 case Intrinsic::x86_sse41_ptestnzc:
16478 case Intrinsic::x86_avx_ptestz_256:
16479 case Intrinsic::x86_avx_ptestc_256:
16480 case Intrinsic::x86_avx_ptestnzc_256:
16481 case Intrinsic::x86_avx_vtestz_ps:
16482 case Intrinsic::x86_avx_vtestc_ps:
16483 case Intrinsic::x86_avx_vtestnzc_ps:
16484 case Intrinsic::x86_avx_vtestz_pd:
16485 case Intrinsic::x86_avx_vtestc_pd:
16486 case Intrinsic::x86_avx_vtestnzc_pd:
16487 case Intrinsic::x86_avx_vtestz_ps_256:
16488 case Intrinsic::x86_avx_vtestc_ps_256:
16489 case Intrinsic::x86_avx_vtestnzc_ps_256:
16490 case Intrinsic::x86_avx_vtestz_pd_256:
16491 case Intrinsic::x86_avx_vtestc_pd_256:
16492 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16493 bool IsTestPacked = false;
16496 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16497 case Intrinsic::x86_avx_vtestz_ps:
16498 case Intrinsic::x86_avx_vtestz_pd:
16499 case Intrinsic::x86_avx_vtestz_ps_256:
16500 case Intrinsic::x86_avx_vtestz_pd_256:
16501 IsTestPacked = true; // Fallthrough
16502 case Intrinsic::x86_sse41_ptestz:
16503 case Intrinsic::x86_avx_ptestz_256:
16505 X86CC = X86::COND_E;
16507 case Intrinsic::x86_avx_vtestc_ps:
16508 case Intrinsic::x86_avx_vtestc_pd:
16509 case Intrinsic::x86_avx_vtestc_ps_256:
16510 case Intrinsic::x86_avx_vtestc_pd_256:
16511 IsTestPacked = true; // Fallthrough
16512 case Intrinsic::x86_sse41_ptestc:
16513 case Intrinsic::x86_avx_ptestc_256:
16515 X86CC = X86::COND_B;
16517 case Intrinsic::x86_avx_vtestnzc_ps:
16518 case Intrinsic::x86_avx_vtestnzc_pd:
16519 case Intrinsic::x86_avx_vtestnzc_ps_256:
16520 case Intrinsic::x86_avx_vtestnzc_pd_256:
16521 IsTestPacked = true; // Fallthrough
16522 case Intrinsic::x86_sse41_ptestnzc:
16523 case Intrinsic::x86_avx_ptestnzc_256:
16525 X86CC = X86::COND_A;
16529 SDValue LHS = Op.getOperand(1);
16530 SDValue RHS = Op.getOperand(2);
16531 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16532 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16533 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16534 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16535 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16537 case Intrinsic::x86_avx512_kortestz_w:
16538 case Intrinsic::x86_avx512_kortestc_w: {
16539 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16540 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16541 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16542 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16543 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16544 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16545 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16548 case Intrinsic::x86_sse42_pcmpistria128:
16549 case Intrinsic::x86_sse42_pcmpestria128:
16550 case Intrinsic::x86_sse42_pcmpistric128:
16551 case Intrinsic::x86_sse42_pcmpestric128:
16552 case Intrinsic::x86_sse42_pcmpistrio128:
16553 case Intrinsic::x86_sse42_pcmpestrio128:
16554 case Intrinsic::x86_sse42_pcmpistris128:
16555 case Intrinsic::x86_sse42_pcmpestris128:
16556 case Intrinsic::x86_sse42_pcmpistriz128:
16557 case Intrinsic::x86_sse42_pcmpestriz128: {
16561 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16562 case Intrinsic::x86_sse42_pcmpistria128:
16563 Opcode = X86ISD::PCMPISTRI;
16564 X86CC = X86::COND_A;
16566 case Intrinsic::x86_sse42_pcmpestria128:
16567 Opcode = X86ISD::PCMPESTRI;
16568 X86CC = X86::COND_A;
16570 case Intrinsic::x86_sse42_pcmpistric128:
16571 Opcode = X86ISD::PCMPISTRI;
16572 X86CC = X86::COND_B;
16574 case Intrinsic::x86_sse42_pcmpestric128:
16575 Opcode = X86ISD::PCMPESTRI;
16576 X86CC = X86::COND_B;
16578 case Intrinsic::x86_sse42_pcmpistrio128:
16579 Opcode = X86ISD::PCMPISTRI;
16580 X86CC = X86::COND_O;
16582 case Intrinsic::x86_sse42_pcmpestrio128:
16583 Opcode = X86ISD::PCMPESTRI;
16584 X86CC = X86::COND_O;
16586 case Intrinsic::x86_sse42_pcmpistris128:
16587 Opcode = X86ISD::PCMPISTRI;
16588 X86CC = X86::COND_S;
16590 case Intrinsic::x86_sse42_pcmpestris128:
16591 Opcode = X86ISD::PCMPESTRI;
16592 X86CC = X86::COND_S;
16594 case Intrinsic::x86_sse42_pcmpistriz128:
16595 Opcode = X86ISD::PCMPISTRI;
16596 X86CC = X86::COND_E;
16598 case Intrinsic::x86_sse42_pcmpestriz128:
16599 Opcode = X86ISD::PCMPESTRI;
16600 X86CC = X86::COND_E;
16603 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16604 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16605 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16606 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16607 DAG.getConstant(X86CC, dl, MVT::i8),
16608 SDValue(PCMP.getNode(), 1));
16609 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16612 case Intrinsic::x86_sse42_pcmpistri128:
16613 case Intrinsic::x86_sse42_pcmpestri128: {
16615 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16616 Opcode = X86ISD::PCMPISTRI;
16618 Opcode = X86ISD::PCMPESTRI;
16620 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16621 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16622 return DAG.getNode(Opcode, dl, VTs, NewOps);
16625 case Intrinsic::x86_seh_lsda: {
16626 // Compute the symbol for the LSDA. We know it'll get emitted later.
16627 MachineFunction &MF = DAG.getMachineFunction();
16628 SDValue Op1 = Op.getOperand(1);
16629 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16630 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16631 GlobalValue::getRealLinkageName(Fn->getName()));
16633 // Generate a simple absolute symbol reference. This intrinsic is only
16634 // supported on 32-bit Windows, which isn't PIC.
16635 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16636 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16639 case Intrinsic::x86_seh_recoverfp: {
16640 SDValue FnOp = Op.getOperand(1);
16641 SDValue IncomingFPOp = Op.getOperand(2);
16642 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16643 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16645 report_fatal_error(
16646 "llvm.x86.seh.recoverfp must take a function as the first argument");
16647 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16650 case Intrinsic::localaddress: {
16651 // Returns one of the stack, base, or frame pointer registers, depending on
16652 // which is used to reference local variables.
16653 MachineFunction &MF = DAG.getMachineFunction();
16654 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16656 if (RegInfo->hasBasePointer(MF))
16657 Reg = RegInfo->getBaseRegister();
16658 else // This function handles the SP or FP case.
16659 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16660 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16665 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16666 SDValue Src, SDValue Mask, SDValue Base,
16667 SDValue Index, SDValue ScaleOp, SDValue Chain,
16668 const X86Subtarget * Subtarget) {
16670 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16672 llvm_unreachable("Invalid scale type");
16673 unsigned ScaleVal = C->getZExtValue();
16674 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16675 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16677 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16678 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16679 Index.getSimpleValueType().getVectorNumElements());
16681 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16683 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16685 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16686 Mask.getValueType().getSizeInBits());
16688 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16689 // are extracted by EXTRACT_SUBVECTOR.
16690 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16691 DAG.getBitcast(BitcastVT, Mask),
16692 DAG.getIntPtrConstant(0, dl));
16694 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16695 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16696 SDValue Segment = DAG.getRegister(0, MVT::i32);
16697 if (Src.getOpcode() == ISD::UNDEF)
16698 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16699 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16700 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16701 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16702 return DAG.getMergeValues(RetOps, dl);
16705 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16706 SDValue Src, SDValue Mask, SDValue Base,
16707 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16709 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16711 llvm_unreachable("Invalid scale type");
16712 unsigned ScaleVal = C->getZExtValue();
16713 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16714 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16716 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16717 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16718 SDValue Segment = DAG.getRegister(0, MVT::i32);
16719 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16720 Index.getSimpleValueType().getVectorNumElements());
16722 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16724 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16726 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16727 Mask.getValueType().getSizeInBits());
16729 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16730 // are extracted by EXTRACT_SUBVECTOR.
16731 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16732 DAG.getBitcast(BitcastVT, Mask),
16733 DAG.getIntPtrConstant(0, dl));
16735 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16736 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16737 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16738 return SDValue(Res, 1);
16741 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16742 SDValue Mask, SDValue Base, SDValue Index,
16743 SDValue ScaleOp, SDValue Chain) {
16745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16746 assert(C && "Invalid scale type");
16747 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16748 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16749 SDValue Segment = DAG.getRegister(0, MVT::i32);
16751 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16753 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16755 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16757 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16758 //SDVTList VTs = DAG.getVTList(MVT::Other);
16759 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16760 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16761 return SDValue(Res, 0);
16764 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16765 // read performance monitor counters (x86_rdpmc).
16766 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16767 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16768 SmallVectorImpl<SDValue> &Results) {
16769 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16770 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16773 // The ECX register is used to select the index of the performance counter
16775 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16777 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16779 // Reads the content of a 64-bit performance counter and returns it in the
16780 // registers EDX:EAX.
16781 if (Subtarget->is64Bit()) {
16782 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16783 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16786 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16787 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16790 Chain = HI.getValue(1);
16792 if (Subtarget->is64Bit()) {
16793 // The EAX register is loaded with the low-order 32 bits. The EDX register
16794 // is loaded with the supported high-order bits of the counter.
16795 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16796 DAG.getConstant(32, DL, MVT::i8));
16797 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16798 Results.push_back(Chain);
16802 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16803 SDValue Ops[] = { LO, HI };
16804 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16805 Results.push_back(Pair);
16806 Results.push_back(Chain);
16809 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16810 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16811 // also used to custom lower READCYCLECOUNTER nodes.
16812 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16813 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16814 SmallVectorImpl<SDValue> &Results) {
16815 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16816 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16819 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16820 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16821 // and the EAX register is loaded with the low-order 32 bits.
16822 if (Subtarget->is64Bit()) {
16823 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16824 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16827 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16828 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16831 SDValue Chain = HI.getValue(1);
16833 if (Opcode == X86ISD::RDTSCP_DAG) {
16834 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16836 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16837 // the ECX register. Add 'ecx' explicitly to the chain.
16838 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16840 // Explicitly store the content of ECX at the location passed in input
16841 // to the 'rdtscp' intrinsic.
16842 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16843 MachinePointerInfo(), false, false, 0);
16846 if (Subtarget->is64Bit()) {
16847 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16848 // the EAX register is loaded with the low-order 32 bits.
16849 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16850 DAG.getConstant(32, DL, MVT::i8));
16851 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16852 Results.push_back(Chain);
16856 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16857 SDValue Ops[] = { LO, HI };
16858 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16859 Results.push_back(Pair);
16860 Results.push_back(Chain);
16863 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16864 SelectionDAG &DAG) {
16865 SmallVector<SDValue, 2> Results;
16867 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16869 return DAG.getMergeValues(Results, DL);
16872 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16873 SelectionDAG &DAG) {
16874 MachineFunction &MF = DAG.getMachineFunction();
16875 const Function *Fn = MF.getFunction();
16877 SDValue Chain = Op.getOperand(0);
16879 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16880 "using llvm.x86.seh.restoreframe requires a frame pointer");
16882 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16883 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16885 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16886 unsigned FrameReg =
16887 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16888 unsigned SPReg = RegInfo->getStackRegister();
16889 unsigned SlotSize = RegInfo->getSlotSize();
16891 // Get incoming EBP.
16892 SDValue IncomingEBP =
16893 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16895 // SP is saved in the first field of every registration node, so load
16896 // [EBP-RegNodeSize] into SP.
16897 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16898 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16899 DAG.getConstant(-RegNodeSize, dl, VT));
16901 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16902 false, VT.getScalarSizeInBits() / 8);
16903 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16905 if (!RegInfo->needsStackRealignment(MF)) {
16906 // Adjust EBP to point back to the original frame position.
16907 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16908 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16910 assert(RegInfo->hasBasePointer(MF) &&
16911 "functions with Win32 EH must use frame or base pointer register");
16913 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16914 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16915 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16917 // Reload the spilled EBP value, now that the stack and base pointers are
16919 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16920 X86FI->setHasSEHFramePtrSave(true);
16921 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16922 X86FI->setSEHFramePtrSaveIndex(FI);
16923 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16924 MachinePointerInfo(), false, false, false,
16925 VT.getScalarSizeInBits() / 8);
16926 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16932 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16933 /// return truncate Store/MaskedStore Node
16934 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16938 SDValue Mask = Op.getOperand(4);
16939 SDValue DataToTruncate = Op.getOperand(3);
16940 SDValue Addr = Op.getOperand(2);
16941 SDValue Chain = Op.getOperand(0);
16943 EVT VT = DataToTruncate.getValueType();
16944 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16945 ElementType, VT.getVectorNumElements());
16947 if (isAllOnes(Mask)) // return just a truncate store
16948 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16949 MachinePointerInfo(), SVT, false, false,
16950 SVT.getScalarSizeInBits()/8);
16952 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16953 MVT::i1, VT.getVectorNumElements());
16954 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16955 Mask.getValueType().getSizeInBits());
16956 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16957 // are extracted by EXTRACT_SUBVECTOR.
16958 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16959 DAG.getBitcast(BitcastVT, Mask),
16960 DAG.getIntPtrConstant(0, dl));
16962 MachineMemOperand *MMO = DAG.getMachineFunction().
16963 getMachineMemOperand(MachinePointerInfo(),
16964 MachineMemOperand::MOStore, SVT.getStoreSize(),
16965 SVT.getScalarSizeInBits()/8);
16967 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16968 VMask, SVT, MMO, true);
16971 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16972 SelectionDAG &DAG) {
16973 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16975 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16977 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16978 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16983 switch(IntrData->Type) {
16985 llvm_unreachable("Unknown Intrinsic Type");
16989 // Emit the node with the right value type.
16990 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16991 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16993 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16994 // Otherwise return the value from Rand, which is always 0, casted to i32.
16995 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16996 DAG.getConstant(1, dl, Op->getValueType(1)),
16997 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16998 SDValue(Result.getNode(), 1) };
16999 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17000 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17003 // Return { result, isValid, chain }.
17004 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17005 SDValue(Result.getNode(), 2));
17008 //gather(v1, mask, index, base, scale);
17009 SDValue Chain = Op.getOperand(0);
17010 SDValue Src = Op.getOperand(2);
17011 SDValue Base = Op.getOperand(3);
17012 SDValue Index = Op.getOperand(4);
17013 SDValue Mask = Op.getOperand(5);
17014 SDValue Scale = Op.getOperand(6);
17015 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17019 //scatter(base, mask, index, v1, scale);
17020 SDValue Chain = Op.getOperand(0);
17021 SDValue Base = Op.getOperand(2);
17022 SDValue Mask = Op.getOperand(3);
17023 SDValue Index = Op.getOperand(4);
17024 SDValue Src = Op.getOperand(5);
17025 SDValue Scale = Op.getOperand(6);
17026 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17030 SDValue Hint = Op.getOperand(6);
17031 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17032 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17033 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17034 SDValue Chain = Op.getOperand(0);
17035 SDValue Mask = Op.getOperand(2);
17036 SDValue Index = Op.getOperand(3);
17037 SDValue Base = Op.getOperand(4);
17038 SDValue Scale = Op.getOperand(5);
17039 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17041 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17043 SmallVector<SDValue, 2> Results;
17044 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17046 return DAG.getMergeValues(Results, dl);
17048 // Read Performance Monitoring Counters.
17050 SmallVector<SDValue, 2> Results;
17051 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17052 return DAG.getMergeValues(Results, dl);
17054 // XTEST intrinsics.
17056 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17057 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17058 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17059 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17061 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17062 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17063 Ret, SDValue(InTrans.getNode(), 1));
17067 SmallVector<SDValue, 2> Results;
17068 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17069 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17070 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17071 DAG.getConstant(-1, dl, MVT::i8));
17072 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17073 Op.getOperand(4), GenCF.getValue(1));
17074 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17075 Op.getOperand(5), MachinePointerInfo(),
17077 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17078 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17080 Results.push_back(SetCC);
17081 Results.push_back(Store);
17082 return DAG.getMergeValues(Results, dl);
17084 case COMPRESS_TO_MEM: {
17086 SDValue Mask = Op.getOperand(4);
17087 SDValue DataToCompress = Op.getOperand(3);
17088 SDValue Addr = Op.getOperand(2);
17089 SDValue Chain = Op.getOperand(0);
17091 EVT VT = DataToCompress.getValueType();
17092 if (isAllOnes(Mask)) // return just a store
17093 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17094 MachinePointerInfo(), false, false,
17095 VT.getScalarSizeInBits()/8);
17097 SDValue Compressed =
17098 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17099 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17100 return DAG.getStore(Chain, dl, Compressed, Addr,
17101 MachinePointerInfo(), false, false,
17102 VT.getScalarSizeInBits()/8);
17104 case TRUNCATE_TO_MEM_VI8:
17105 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17106 case TRUNCATE_TO_MEM_VI16:
17107 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17108 case TRUNCATE_TO_MEM_VI32:
17109 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17110 case EXPAND_FROM_MEM: {
17112 SDValue Mask = Op.getOperand(4);
17113 SDValue PassThru = Op.getOperand(3);
17114 SDValue Addr = Op.getOperand(2);
17115 SDValue Chain = Op.getOperand(0);
17116 EVT VT = Op.getValueType();
17118 if (isAllOnes(Mask)) // return just a load
17119 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17120 false, VT.getScalarSizeInBits()/8);
17122 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17123 false, false, false,
17124 VT.getScalarSizeInBits()/8);
17126 SDValue Results[] = {
17127 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17128 Mask, PassThru, Subtarget, DAG), Chain};
17129 return DAG.getMergeValues(Results, dl);
17134 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17135 SelectionDAG &DAG) const {
17136 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17137 MFI->setReturnAddressIsTaken(true);
17139 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17142 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17144 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17147 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17148 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17149 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17150 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17151 DAG.getNode(ISD::ADD, dl, PtrVT,
17152 FrameAddr, Offset),
17153 MachinePointerInfo(), false, false, false, 0);
17156 // Just load the return address.
17157 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17158 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17159 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17162 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17163 MachineFunction &MF = DAG.getMachineFunction();
17164 MachineFrameInfo *MFI = MF.getFrameInfo();
17165 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17166 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17167 EVT VT = Op.getValueType();
17169 MFI->setFrameAddressIsTaken(true);
17171 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17172 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17173 // is not possible to crawl up the stack without looking at the unwind codes
17175 int FrameAddrIndex = FuncInfo->getFAIndex();
17176 if (!FrameAddrIndex) {
17177 // Set up a frame object for the return address.
17178 unsigned SlotSize = RegInfo->getSlotSize();
17179 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17180 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17181 FuncInfo->setFAIndex(FrameAddrIndex);
17183 return DAG.getFrameIndex(FrameAddrIndex, VT);
17186 unsigned FrameReg =
17187 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17188 SDLoc dl(Op); // FIXME probably not meaningful
17189 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17190 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17191 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17192 "Invalid Frame Register!");
17193 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17195 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17196 MachinePointerInfo(),
17197 false, false, false, 0);
17201 // FIXME? Maybe this could be a TableGen attribute on some registers and
17202 // this table could be generated automatically from RegInfo.
17203 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17204 SelectionDAG &DAG) const {
17205 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17206 const MachineFunction &MF = DAG.getMachineFunction();
17208 unsigned Reg = StringSwitch<unsigned>(RegName)
17209 .Case("esp", X86::ESP)
17210 .Case("rsp", X86::RSP)
17211 .Case("ebp", X86::EBP)
17212 .Case("rbp", X86::RBP)
17215 if (Reg == X86::EBP || Reg == X86::RBP) {
17216 if (!TFI.hasFP(MF))
17217 report_fatal_error("register " + StringRef(RegName) +
17218 " is allocatable: function has no frame pointer");
17221 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17222 unsigned FrameReg =
17223 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17224 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17225 "Invalid Frame Register!");
17233 report_fatal_error("Invalid register name global variable");
17236 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17237 SelectionDAG &DAG) const {
17238 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17239 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17242 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17243 SDValue Chain = Op.getOperand(0);
17244 SDValue Offset = Op.getOperand(1);
17245 SDValue Handler = Op.getOperand(2);
17248 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17249 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17250 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17251 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17252 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17253 "Invalid Frame Register!");
17254 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17255 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17257 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17258 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17260 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17261 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17263 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17265 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17266 DAG.getRegister(StoreAddrReg, PtrVT));
17269 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17270 SelectionDAG &DAG) const {
17272 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17273 DAG.getVTList(MVT::i32, MVT::Other),
17274 Op.getOperand(0), Op.getOperand(1));
17277 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17278 SelectionDAG &DAG) const {
17280 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17281 Op.getOperand(0), Op.getOperand(1));
17284 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17285 return Op.getOperand(0);
17288 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17289 SelectionDAG &DAG) const {
17290 SDValue Root = Op.getOperand(0);
17291 SDValue Trmp = Op.getOperand(1); // trampoline
17292 SDValue FPtr = Op.getOperand(2); // nested function
17293 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17296 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17297 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17299 if (Subtarget->is64Bit()) {
17300 SDValue OutChains[6];
17302 // Large code-model.
17303 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17304 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17306 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17307 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17309 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17311 // Load the pointer to the nested function into R11.
17312 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17313 SDValue Addr = Trmp;
17314 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17315 Addr, MachinePointerInfo(TrmpAddr),
17318 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17319 DAG.getConstant(2, dl, MVT::i64));
17320 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17321 MachinePointerInfo(TrmpAddr, 2),
17324 // Load the 'nest' parameter value into R10.
17325 // R10 is specified in X86CallingConv.td
17326 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17327 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17328 DAG.getConstant(10, dl, MVT::i64));
17329 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17330 Addr, MachinePointerInfo(TrmpAddr, 10),
17333 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17334 DAG.getConstant(12, dl, MVT::i64));
17335 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17336 MachinePointerInfo(TrmpAddr, 12),
17339 // Jump to the nested function.
17340 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17341 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17342 DAG.getConstant(20, dl, MVT::i64));
17343 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17344 Addr, MachinePointerInfo(TrmpAddr, 20),
17347 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17348 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17349 DAG.getConstant(22, dl, MVT::i64));
17350 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17351 Addr, MachinePointerInfo(TrmpAddr, 22),
17354 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17356 const Function *Func =
17357 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17358 CallingConv::ID CC = Func->getCallingConv();
17363 llvm_unreachable("Unsupported calling convention");
17364 case CallingConv::C:
17365 case CallingConv::X86_StdCall: {
17366 // Pass 'nest' parameter in ECX.
17367 // Must be kept in sync with X86CallingConv.td
17368 NestReg = X86::ECX;
17370 // Check that ECX wasn't needed by an 'inreg' parameter.
17371 FunctionType *FTy = Func->getFunctionType();
17372 const AttributeSet &Attrs = Func->getAttributes();
17374 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17375 unsigned InRegCount = 0;
17378 for (FunctionType::param_iterator I = FTy->param_begin(),
17379 E = FTy->param_end(); I != E; ++I, ++Idx)
17380 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17381 auto &DL = DAG.getDataLayout();
17382 // FIXME: should only count parameters that are lowered to integers.
17383 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17386 if (InRegCount > 2) {
17387 report_fatal_error("Nest register in use - reduce number of inreg"
17393 case CallingConv::X86_FastCall:
17394 case CallingConv::X86_ThisCall:
17395 case CallingConv::Fast:
17396 // Pass 'nest' parameter in EAX.
17397 // Must be kept in sync with X86CallingConv.td
17398 NestReg = X86::EAX;
17402 SDValue OutChains[4];
17403 SDValue Addr, Disp;
17405 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17406 DAG.getConstant(10, dl, MVT::i32));
17407 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17409 // This is storing the opcode for MOV32ri.
17410 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17411 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17412 OutChains[0] = DAG.getStore(Root, dl,
17413 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17414 Trmp, MachinePointerInfo(TrmpAddr),
17417 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17418 DAG.getConstant(1, dl, MVT::i32));
17419 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17420 MachinePointerInfo(TrmpAddr, 1),
17423 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17424 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17425 DAG.getConstant(5, dl, MVT::i32));
17426 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17427 Addr, MachinePointerInfo(TrmpAddr, 5),
17430 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17431 DAG.getConstant(6, dl, MVT::i32));
17432 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17433 MachinePointerInfo(TrmpAddr, 6),
17436 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17440 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17441 SelectionDAG &DAG) const {
17443 The rounding mode is in bits 11:10 of FPSR, and has the following
17445 00 Round to nearest
17450 FLT_ROUNDS, on the other hand, expects the following:
17457 To perform the conversion, we do:
17458 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17461 MachineFunction &MF = DAG.getMachineFunction();
17462 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17463 unsigned StackAlignment = TFI.getStackAlignment();
17464 MVT VT = Op.getSimpleValueType();
17467 // Save FP Control Word to stack slot
17468 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17469 SDValue StackSlot =
17470 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17472 MachineMemOperand *MMO =
17473 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17474 MachineMemOperand::MOStore, 2, 2);
17476 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17477 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17478 DAG.getVTList(MVT::Other),
17479 Ops, MVT::i16, MMO);
17481 // Load FP Control Word from stack slot
17482 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17483 MachinePointerInfo(), false, false, false, 0);
17485 // Transform as necessary
17487 DAG.getNode(ISD::SRL, DL, MVT::i16,
17488 DAG.getNode(ISD::AND, DL, MVT::i16,
17489 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17490 DAG.getConstant(11, DL, MVT::i8));
17492 DAG.getNode(ISD::SRL, DL, MVT::i16,
17493 DAG.getNode(ISD::AND, DL, MVT::i16,
17494 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17495 DAG.getConstant(9, DL, MVT::i8));
17498 DAG.getNode(ISD::AND, DL, MVT::i16,
17499 DAG.getNode(ISD::ADD, DL, MVT::i16,
17500 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17501 DAG.getConstant(1, DL, MVT::i16)),
17502 DAG.getConstant(3, DL, MVT::i16));
17504 return DAG.getNode((VT.getSizeInBits() < 16 ?
17505 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17508 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17509 MVT VT = Op.getSimpleValueType();
17511 unsigned NumBits = VT.getSizeInBits();
17514 Op = Op.getOperand(0);
17515 if (VT == MVT::i8) {
17516 // Zero extend to i32 since there is not an i8 bsr.
17518 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17521 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17522 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17523 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17525 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17528 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17529 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17532 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17534 // Finally xor with NumBits-1.
17535 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17536 DAG.getConstant(NumBits - 1, dl, OpVT));
17539 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17543 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17544 MVT VT = Op.getSimpleValueType();
17546 unsigned NumBits = VT.getSizeInBits();
17549 Op = Op.getOperand(0);
17550 if (VT == MVT::i8) {
17551 // Zero extend to i32 since there is not an i8 bsr.
17553 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17556 // Issue a bsr (scan bits in reverse).
17557 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17558 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17560 // And xor with NumBits-1.
17561 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17562 DAG.getConstant(NumBits - 1, dl, OpVT));
17565 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17569 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17570 MVT VT = Op.getSimpleValueType();
17571 unsigned NumBits = VT.getScalarSizeInBits();
17574 if (VT.isVector()) {
17575 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17577 SDValue N0 = Op.getOperand(0);
17578 SDValue Zero = DAG.getConstant(0, dl, VT);
17580 // lsb(x) = (x & -x)
17581 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17582 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17584 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17585 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17586 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17587 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17588 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17589 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17592 // cttz(x) = ctpop(lsb - 1)
17593 SDValue One = DAG.getConstant(1, dl, VT);
17594 return DAG.getNode(ISD::CTPOP, dl, VT,
17595 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17598 assert(Op.getOpcode() == ISD::CTTZ &&
17599 "Only scalar CTTZ requires custom lowering");
17601 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17602 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17603 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17605 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17608 DAG.getConstant(NumBits, dl, VT),
17609 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17612 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17615 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17616 // ones, and then concatenate the result back.
17617 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17618 MVT VT = Op.getSimpleValueType();
17620 assert(VT.is256BitVector() && VT.isInteger() &&
17621 "Unsupported value type for operation");
17623 unsigned NumElems = VT.getVectorNumElements();
17626 // Extract the LHS vectors
17627 SDValue LHS = Op.getOperand(0);
17628 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17629 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17631 // Extract the RHS vectors
17632 SDValue RHS = Op.getOperand(1);
17633 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17634 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17636 MVT EltVT = VT.getVectorElementType();
17637 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17639 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17640 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17641 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17644 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17645 if (Op.getValueType() == MVT::i1)
17646 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17647 Op.getOperand(0), Op.getOperand(1));
17648 assert(Op.getSimpleValueType().is256BitVector() &&
17649 Op.getSimpleValueType().isInteger() &&
17650 "Only handle AVX 256-bit vector integer operation");
17651 return Lower256IntArith(Op, DAG);
17654 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17655 if (Op.getValueType() == MVT::i1)
17656 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17657 Op.getOperand(0), Op.getOperand(1));
17658 assert(Op.getSimpleValueType().is256BitVector() &&
17659 Op.getSimpleValueType().isInteger() &&
17660 "Only handle AVX 256-bit vector integer operation");
17661 return Lower256IntArith(Op, DAG);
17664 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17665 assert(Op.getSimpleValueType().is256BitVector() &&
17666 Op.getSimpleValueType().isInteger() &&
17667 "Only handle AVX 256-bit vector integer operation");
17668 return Lower256IntArith(Op, DAG);
17671 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17672 SelectionDAG &DAG) {
17674 MVT VT = Op.getSimpleValueType();
17677 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17679 // Decompose 256-bit ops into smaller 128-bit ops.
17680 if (VT.is256BitVector() && !Subtarget->hasInt256())
17681 return Lower256IntArith(Op, DAG);
17683 SDValue A = Op.getOperand(0);
17684 SDValue B = Op.getOperand(1);
17686 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17687 // pairs, multiply and truncate.
17688 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17689 if (Subtarget->hasInt256()) {
17690 if (VT == MVT::v32i8) {
17691 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17692 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17693 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17694 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17695 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17696 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17697 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17698 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17699 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17700 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17703 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17704 return DAG.getNode(
17705 ISD::TRUNCATE, dl, VT,
17706 DAG.getNode(ISD::MUL, dl, ExVT,
17707 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17708 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17711 assert(VT == MVT::v16i8 &&
17712 "Pre-AVX2 support only supports v16i8 multiplication");
17713 MVT ExVT = MVT::v8i16;
17715 // Extract the lo parts and sign extend to i16
17717 if (Subtarget->hasSSE41()) {
17718 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17719 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17721 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17722 -1, 4, -1, 5, -1, 6, -1, 7};
17723 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17724 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17725 ALo = DAG.getBitcast(ExVT, ALo);
17726 BLo = DAG.getBitcast(ExVT, BLo);
17727 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17728 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17731 // Extract the hi parts and sign extend to i16
17733 if (Subtarget->hasSSE41()) {
17734 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17735 -1, -1, -1, -1, -1, -1, -1, -1};
17736 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17737 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17738 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17739 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17741 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17742 -1, 12, -1, 13, -1, 14, -1, 15};
17743 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17744 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17745 AHi = DAG.getBitcast(ExVT, AHi);
17746 BHi = DAG.getBitcast(ExVT, BHi);
17747 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17748 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17751 // Multiply, mask the lower 8bits of the lo/hi results and pack
17752 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17753 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17754 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17755 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17756 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17759 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17760 if (VT == MVT::v4i32) {
17761 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17762 "Should not custom lower when pmuldq is available!");
17764 // Extract the odd parts.
17765 static const int UnpackMask[] = { 1, -1, 3, -1 };
17766 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17767 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17769 // Multiply the even parts.
17770 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17771 // Now multiply odd parts.
17772 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17774 Evens = DAG.getBitcast(VT, Evens);
17775 Odds = DAG.getBitcast(VT, Odds);
17777 // Merge the two vectors back together with a shuffle. This expands into 2
17779 static const int ShufMask[] = { 0, 4, 2, 6 };
17780 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17783 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17784 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17786 // Ahi = psrlqi(a, 32);
17787 // Bhi = psrlqi(b, 32);
17789 // AloBlo = pmuludq(a, b);
17790 // AloBhi = pmuludq(a, Bhi);
17791 // AhiBlo = pmuludq(Ahi, b);
17793 // AloBhi = psllqi(AloBhi, 32);
17794 // AhiBlo = psllqi(AhiBlo, 32);
17795 // return AloBlo + AloBhi + AhiBlo;
17797 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17798 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17800 SDValue AhiBlo = Ahi;
17801 SDValue AloBhi = Bhi;
17802 // Bit cast to 32-bit vectors for MULUDQ
17803 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17804 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17805 A = DAG.getBitcast(MulVT, A);
17806 B = DAG.getBitcast(MulVT, B);
17807 Ahi = DAG.getBitcast(MulVT, Ahi);
17808 Bhi = DAG.getBitcast(MulVT, Bhi);
17810 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17811 // After shifting right const values the result may be all-zero.
17812 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17813 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17814 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17816 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17817 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17818 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17821 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17822 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17825 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17826 assert(Subtarget->isTargetWin64() && "Unexpected target");
17827 EVT VT = Op.getValueType();
17828 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17829 "Unexpected return type for lowering");
17833 switch (Op->getOpcode()) {
17834 default: llvm_unreachable("Unexpected request for libcall!");
17835 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17836 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17837 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17838 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17839 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17840 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17844 SDValue InChain = DAG.getEntryNode();
17846 TargetLowering::ArgListTy Args;
17847 TargetLowering::ArgListEntry Entry;
17848 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17849 EVT ArgVT = Op->getOperand(i).getValueType();
17850 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17851 "Unexpected argument type for lowering");
17852 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17853 Entry.Node = StackPtr;
17854 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17856 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17857 Entry.Ty = PointerType::get(ArgTy,0);
17858 Entry.isSExt = false;
17859 Entry.isZExt = false;
17860 Args.push_back(Entry);
17863 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17864 getPointerTy(DAG.getDataLayout()));
17866 TargetLowering::CallLoweringInfo CLI(DAG);
17867 CLI.setDebugLoc(dl).setChain(InChain)
17868 .setCallee(getLibcallCallingConv(LC),
17869 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17870 Callee, std::move(Args), 0)
17871 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17873 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17874 return DAG.getBitcast(VT, CallInfo.first);
17877 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17878 SelectionDAG &DAG) {
17879 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17880 EVT VT = Op0.getValueType();
17883 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17884 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17886 // PMULxD operations multiply each even value (starting at 0) of LHS with
17887 // the related value of RHS and produce a widen result.
17888 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17889 // => <2 x i64> <ae|cg>
17891 // In other word, to have all the results, we need to perform two PMULxD:
17892 // 1. one with the even values.
17893 // 2. one with the odd values.
17894 // To achieve #2, with need to place the odd values at an even position.
17896 // Place the odd value at an even position (basically, shift all values 1
17897 // step to the left):
17898 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17899 // <a|b|c|d> => <b|undef|d|undef>
17900 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17901 // <e|f|g|h> => <f|undef|h|undef>
17902 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17904 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17906 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17907 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17909 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17910 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17911 // => <2 x i64> <ae|cg>
17912 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17913 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17914 // => <2 x i64> <bf|dh>
17915 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17917 // Shuffle it back into the right order.
17918 SDValue Highs, Lows;
17919 if (VT == MVT::v8i32) {
17920 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17921 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17922 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17923 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17925 const int HighMask[] = {1, 5, 3, 7};
17926 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17927 const int LowMask[] = {0, 4, 2, 6};
17928 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17931 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17932 // unsigned multiply.
17933 if (IsSigned && !Subtarget->hasSSE41()) {
17934 SDValue ShAmt = DAG.getConstant(
17936 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17937 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17938 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17939 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17940 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17942 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17943 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17946 // The first result of MUL_LOHI is actually the low value, followed by the
17948 SDValue Ops[] = {Lows, Highs};
17949 return DAG.getMergeValues(Ops, dl);
17952 // Return true if the required (according to Opcode) shift-imm form is natively
17953 // supported by the Subtarget
17954 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17956 if (VT.getScalarSizeInBits() < 16)
17959 if (VT.is512BitVector() &&
17960 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17963 bool LShift = VT.is128BitVector() ||
17964 (VT.is256BitVector() && Subtarget->hasInt256());
17966 bool AShift = LShift && (Subtarget->hasVLX() ||
17967 (VT != MVT::v2i64 && VT != MVT::v4i64));
17968 return (Opcode == ISD::SRA) ? AShift : LShift;
17971 // The shift amount is a variable, but it is the same for all vector lanes.
17972 // These instructions are defined together with shift-immediate.
17974 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17976 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17979 // Return true if the required (according to Opcode) variable-shift form is
17980 // natively supported by the Subtarget
17981 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17984 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17987 // vXi16 supported only on AVX-512, BWI
17988 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17991 if (VT.is512BitVector() || Subtarget->hasVLX())
17994 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17995 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17996 return (Opcode == ISD::SRA) ? AShift : LShift;
17999 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18000 const X86Subtarget *Subtarget) {
18001 MVT VT = Op.getSimpleValueType();
18003 SDValue R = Op.getOperand(0);
18004 SDValue Amt = Op.getOperand(1);
18006 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18007 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18009 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18010 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18011 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18012 SDValue Ex = DAG.getBitcast(ExVT, R);
18014 if (ShiftAmt >= 32) {
18015 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18017 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18018 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18019 ShiftAmt - 32, DAG);
18020 if (VT == MVT::v2i64)
18021 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18022 if (VT == MVT::v4i64)
18023 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18024 {9, 1, 11, 3, 13, 5, 15, 7});
18026 // SRA upper i32, SHL whole i64 and select lower i32.
18027 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18030 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18031 Lower = DAG.getBitcast(ExVT, Lower);
18032 if (VT == MVT::v2i64)
18033 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18034 if (VT == MVT::v4i64)
18035 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18036 {8, 1, 10, 3, 12, 5, 14, 7});
18038 return DAG.getBitcast(VT, Ex);
18041 // Optimize shl/srl/sra with constant shift amount.
18042 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18043 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18044 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18046 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18047 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18049 // i64 SRA needs to be performed as partial shifts.
18050 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18051 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18052 return ArithmeticShiftRight64(ShiftAmt);
18054 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18055 unsigned NumElts = VT.getVectorNumElements();
18056 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18058 // Simple i8 add case
18059 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18060 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18062 // ashr(R, 7) === cmp_slt(R, 0)
18063 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18064 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18065 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18068 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18069 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18072 if (Op.getOpcode() == ISD::SHL) {
18073 // Make a large shift.
18074 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18076 SHL = DAG.getBitcast(VT, SHL);
18077 // Zero out the rightmost bits.
18078 SmallVector<SDValue, 32> V(
18079 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18080 return DAG.getNode(ISD::AND, dl, VT, SHL,
18081 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18083 if (Op.getOpcode() == ISD::SRL) {
18084 // Make a large shift.
18085 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18087 SRL = DAG.getBitcast(VT, SRL);
18088 // Zero out the leftmost bits.
18089 SmallVector<SDValue, 32> V(
18090 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18091 return DAG.getNode(ISD::AND, dl, VT, SRL,
18092 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18094 if (Op.getOpcode() == ISD::SRA) {
18095 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18096 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18097 SmallVector<SDValue, 32> V(NumElts,
18098 DAG.getConstant(128 >> ShiftAmt, dl,
18100 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18101 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18102 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18105 llvm_unreachable("Unknown shift opcode.");
18110 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18111 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18112 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18114 // Peek through any splat that was introduced for i64 shift vectorization.
18115 int SplatIndex = -1;
18116 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18117 if (SVN->isSplat()) {
18118 SplatIndex = SVN->getSplatIndex();
18119 Amt = Amt.getOperand(0);
18120 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18121 "Splat shuffle referencing second operand");
18124 if (Amt.getOpcode() != ISD::BITCAST ||
18125 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18128 Amt = Amt.getOperand(0);
18129 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18130 VT.getVectorNumElements();
18131 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18132 uint64_t ShiftAmt = 0;
18133 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18134 for (unsigned i = 0; i != Ratio; ++i) {
18135 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18139 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18142 // Check remaining shift amounts (if not a splat).
18143 if (SplatIndex < 0) {
18144 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18145 uint64_t ShAmt = 0;
18146 for (unsigned j = 0; j != Ratio; ++j) {
18147 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18151 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18153 if (ShAmt != ShiftAmt)
18158 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18159 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18161 if (Op.getOpcode() == ISD::SRA)
18162 return ArithmeticShiftRight64(ShiftAmt);
18168 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18169 const X86Subtarget* Subtarget) {
18170 MVT VT = Op.getSimpleValueType();
18172 SDValue R = Op.getOperand(0);
18173 SDValue Amt = Op.getOperand(1);
18175 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18176 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18178 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18179 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18181 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18183 EVT EltVT = VT.getVectorElementType();
18185 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18186 // Check if this build_vector node is doing a splat.
18187 // If so, then set BaseShAmt equal to the splat value.
18188 BaseShAmt = BV->getSplatValue();
18189 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18190 BaseShAmt = SDValue();
18192 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18193 Amt = Amt.getOperand(0);
18195 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18196 if (SVN && SVN->isSplat()) {
18197 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18198 SDValue InVec = Amt.getOperand(0);
18199 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18200 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18201 "Unexpected shuffle index found!");
18202 BaseShAmt = InVec.getOperand(SplatIdx);
18203 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18204 if (ConstantSDNode *C =
18205 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18206 if (C->getZExtValue() == SplatIdx)
18207 BaseShAmt = InVec.getOperand(1);
18212 // Avoid introducing an extract element from a shuffle.
18213 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18214 DAG.getIntPtrConstant(SplatIdx, dl));
18218 if (BaseShAmt.getNode()) {
18219 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18220 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18221 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18222 else if (EltVT.bitsLT(MVT::i32))
18223 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18225 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18229 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18230 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18231 Amt.getOpcode() == ISD::BITCAST &&
18232 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18233 Amt = Amt.getOperand(0);
18234 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18235 VT.getVectorNumElements();
18236 std::vector<SDValue> Vals(Ratio);
18237 for (unsigned i = 0; i != Ratio; ++i)
18238 Vals[i] = Amt.getOperand(i);
18239 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18240 for (unsigned j = 0; j != Ratio; ++j)
18241 if (Vals[j] != Amt.getOperand(i + j))
18245 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18246 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18251 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18252 SelectionDAG &DAG) {
18253 MVT VT = Op.getSimpleValueType();
18255 SDValue R = Op.getOperand(0);
18256 SDValue Amt = Op.getOperand(1);
18258 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18259 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18261 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18264 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18267 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18270 // XOP has 128-bit variable logical/arithmetic shifts.
18271 // +ve/-ve Amt = shift left/right.
18272 if (Subtarget->hasXOP() &&
18273 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18274 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18275 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18276 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18277 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18279 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18280 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18281 if (Op.getOpcode() == ISD::SRA)
18282 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18285 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18286 // shifts per-lane and then shuffle the partial results back together.
18287 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18288 // Splat the shift amounts so the scalar shifts above will catch it.
18289 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18290 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18291 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18292 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18293 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18296 // i64 vector arithmetic shift can be emulated with the transform:
18297 // M = lshr(SIGN_BIT, Amt)
18298 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18299 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18300 Op.getOpcode() == ISD::SRA) {
18301 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18302 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18303 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18304 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18305 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18309 // If possible, lower this packed shift into a vector multiply instead of
18310 // expanding it into a sequence of scalar shifts.
18311 // Do this only if the vector shift count is a constant build_vector.
18312 if (Op.getOpcode() == ISD::SHL &&
18313 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18314 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18315 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18316 SmallVector<SDValue, 8> Elts;
18317 EVT SVT = VT.getScalarType();
18318 unsigned SVTBits = SVT.getSizeInBits();
18319 const APInt &One = APInt(SVTBits, 1);
18320 unsigned NumElems = VT.getVectorNumElements();
18322 for (unsigned i=0; i !=NumElems; ++i) {
18323 SDValue Op = Amt->getOperand(i);
18324 if (Op->getOpcode() == ISD::UNDEF) {
18325 Elts.push_back(Op);
18329 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18330 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18331 uint64_t ShAmt = C.getZExtValue();
18332 if (ShAmt >= SVTBits) {
18333 Elts.push_back(DAG.getUNDEF(SVT));
18336 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18338 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18339 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18342 // Lower SHL with variable shift amount.
18343 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18344 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18346 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18347 DAG.getConstant(0x3f800000U, dl, VT));
18348 Op = DAG.getBitcast(MVT::v4f32, Op);
18349 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18350 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18353 // If possible, lower this shift as a sequence of two shifts by
18354 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18356 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18358 // Could be rewritten as:
18359 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18361 // The advantage is that the two shifts from the example would be
18362 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18363 // the vector shift into four scalar shifts plus four pairs of vector
18365 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18366 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18367 unsigned TargetOpcode = X86ISD::MOVSS;
18368 bool CanBeSimplified;
18369 // The splat value for the first packed shift (the 'X' from the example).
18370 SDValue Amt1 = Amt->getOperand(0);
18371 // The splat value for the second packed shift (the 'Y' from the example).
18372 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18373 Amt->getOperand(2);
18375 // See if it is possible to replace this node with a sequence of
18376 // two shifts followed by a MOVSS/MOVSD
18377 if (VT == MVT::v4i32) {
18378 // Check if it is legal to use a MOVSS.
18379 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18380 Amt2 == Amt->getOperand(3);
18381 if (!CanBeSimplified) {
18382 // Otherwise, check if we can still simplify this node using a MOVSD.
18383 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18384 Amt->getOperand(2) == Amt->getOperand(3);
18385 TargetOpcode = X86ISD::MOVSD;
18386 Amt2 = Amt->getOperand(2);
18389 // Do similar checks for the case where the machine value type
18391 CanBeSimplified = Amt1 == Amt->getOperand(1);
18392 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18393 CanBeSimplified = Amt2 == Amt->getOperand(i);
18395 if (!CanBeSimplified) {
18396 TargetOpcode = X86ISD::MOVSD;
18397 CanBeSimplified = true;
18398 Amt2 = Amt->getOperand(4);
18399 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18400 CanBeSimplified = Amt1 == Amt->getOperand(i);
18401 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18402 CanBeSimplified = Amt2 == Amt->getOperand(j);
18406 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18407 isa<ConstantSDNode>(Amt2)) {
18408 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18409 EVT CastVT = MVT::v4i32;
18411 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18412 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18414 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18415 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18416 if (TargetOpcode == X86ISD::MOVSD)
18417 CastVT = MVT::v2i64;
18418 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18419 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18420 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18422 return DAG.getBitcast(VT, Result);
18426 // v4i32 Non Uniform Shifts.
18427 // If the shift amount is constant we can shift each lane using the SSE2
18428 // immediate shifts, else we need to zero-extend each lane to the lower i64
18429 // and shift using the SSE2 variable shifts.
18430 // The separate results can then be blended together.
18431 if (VT == MVT::v4i32) {
18432 unsigned Opc = Op.getOpcode();
18433 SDValue Amt0, Amt1, Amt2, Amt3;
18434 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18435 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18436 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18437 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18438 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18440 // ISD::SHL is handled above but we include it here for completeness.
18443 llvm_unreachable("Unknown target vector shift node");
18445 Opc = X86ISD::VSHL;
18448 Opc = X86ISD::VSRL;
18451 Opc = X86ISD::VSRA;
18454 // The SSE2 shifts use the lower i64 as the same shift amount for
18455 // all lanes and the upper i64 is ignored. These shuffle masks
18456 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18457 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18458 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18459 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18460 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18461 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18464 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18465 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18466 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18467 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18468 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18469 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18470 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18473 if (VT == MVT::v16i8 ||
18474 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18475 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18476 unsigned ShiftOpcode = Op->getOpcode();
18478 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18479 // On SSE41 targets we make use of the fact that VSELECT lowers
18480 // to PBLENDVB which selects bytes based just on the sign bit.
18481 if (Subtarget->hasSSE41()) {
18482 V0 = DAG.getBitcast(VT, V0);
18483 V1 = DAG.getBitcast(VT, V1);
18484 Sel = DAG.getBitcast(VT, Sel);
18485 return DAG.getBitcast(SelVT,
18486 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18488 // On pre-SSE41 targets we test for the sign bit by comparing to
18489 // zero - a negative value will set all bits of the lanes to true
18490 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18491 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18492 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18493 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18496 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18497 // We can safely do this using i16 shifts as we're only interested in
18498 // the 3 lower bits of each byte.
18499 Amt = DAG.getBitcast(ExtVT, Amt);
18500 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18501 Amt = DAG.getBitcast(VT, Amt);
18503 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18504 // r = VSELECT(r, shift(r, 4), a);
18506 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18507 R = SignBitSelect(VT, Amt, M, R);
18510 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18512 // r = VSELECT(r, shift(r, 2), a);
18513 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18514 R = SignBitSelect(VT, Amt, M, R);
18517 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18519 // return VSELECT(r, shift(r, 1), a);
18520 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18521 R = SignBitSelect(VT, Amt, M, R);
18525 if (Op->getOpcode() == ISD::SRA) {
18526 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18527 // so we can correctly sign extend. We don't care what happens to the
18529 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18530 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18531 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18532 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18533 ALo = DAG.getBitcast(ExtVT, ALo);
18534 AHi = DAG.getBitcast(ExtVT, AHi);
18535 RLo = DAG.getBitcast(ExtVT, RLo);
18536 RHi = DAG.getBitcast(ExtVT, RHi);
18538 // r = VSELECT(r, shift(r, 4), a);
18539 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18540 DAG.getConstant(4, dl, ExtVT));
18541 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18542 DAG.getConstant(4, dl, ExtVT));
18543 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18544 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18547 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18548 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18550 // r = VSELECT(r, shift(r, 2), a);
18551 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18552 DAG.getConstant(2, dl, ExtVT));
18553 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18554 DAG.getConstant(2, dl, ExtVT));
18555 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18556 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18559 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18560 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18562 // r = VSELECT(r, shift(r, 1), a);
18563 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18564 DAG.getConstant(1, dl, ExtVT));
18565 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18566 DAG.getConstant(1, dl, ExtVT));
18567 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18568 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18570 // Logical shift the result back to the lower byte, leaving a zero upper
18572 // meaning that we can safely pack with PACKUSWB.
18574 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18576 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18577 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18581 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18582 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18583 // solution better.
18584 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18585 MVT ExtVT = MVT::v8i32;
18587 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18588 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18589 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18590 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18591 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18594 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18595 MVT ExtVT = MVT::v8i32;
18596 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18597 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18598 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18599 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18600 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18601 ALo = DAG.getBitcast(ExtVT, ALo);
18602 AHi = DAG.getBitcast(ExtVT, AHi);
18603 RLo = DAG.getBitcast(ExtVT, RLo);
18604 RHi = DAG.getBitcast(ExtVT, RHi);
18605 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18606 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18607 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18608 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18609 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18612 if (VT == MVT::v8i16) {
18613 unsigned ShiftOpcode = Op->getOpcode();
18615 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18616 // On SSE41 targets we make use of the fact that VSELECT lowers
18617 // to PBLENDVB which selects bytes based just on the sign bit.
18618 if (Subtarget->hasSSE41()) {
18619 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18620 V0 = DAG.getBitcast(ExtVT, V0);
18621 V1 = DAG.getBitcast(ExtVT, V1);
18622 Sel = DAG.getBitcast(ExtVT, Sel);
18623 return DAG.getBitcast(
18624 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18626 // On pre-SSE41 targets we splat the sign bit - a negative value will
18627 // set all bits of the lanes to true and VSELECT uses that in
18628 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18630 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18631 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18634 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18635 if (Subtarget->hasSSE41()) {
18636 // On SSE41 targets we need to replicate the shift mask in both
18637 // bytes for PBLENDVB.
18640 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18641 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18643 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18646 // r = VSELECT(r, shift(r, 8), a);
18647 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18648 R = SignBitSelect(Amt, M, R);
18651 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18653 // r = VSELECT(r, shift(r, 4), a);
18654 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18655 R = SignBitSelect(Amt, M, R);
18658 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18660 // r = VSELECT(r, shift(r, 2), a);
18661 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18662 R = SignBitSelect(Amt, M, R);
18665 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18667 // return VSELECT(r, shift(r, 1), a);
18668 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18669 R = SignBitSelect(Amt, M, R);
18673 // Decompose 256-bit shifts into smaller 128-bit shifts.
18674 if (VT.is256BitVector()) {
18675 unsigned NumElems = VT.getVectorNumElements();
18676 MVT EltVT = VT.getVectorElementType();
18677 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18679 // Extract the two vectors
18680 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18681 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18683 // Recreate the shift amount vectors
18684 SDValue Amt1, Amt2;
18685 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18686 // Constant shift amount
18687 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18688 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18689 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18691 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18692 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18694 // Variable shift amount
18695 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18696 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18699 // Issue new vector shifts for the smaller types
18700 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18701 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18703 // Concatenate the result back
18704 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18710 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18711 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18712 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18713 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18714 // has only one use.
18715 SDNode *N = Op.getNode();
18716 SDValue LHS = N->getOperand(0);
18717 SDValue RHS = N->getOperand(1);
18718 unsigned BaseOp = 0;
18721 switch (Op.getOpcode()) {
18722 default: llvm_unreachable("Unknown ovf instruction!");
18724 // A subtract of one will be selected as a INC. Note that INC doesn't
18725 // set CF, so we can't do this for UADDO.
18726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18728 BaseOp = X86ISD::INC;
18729 Cond = X86::COND_O;
18732 BaseOp = X86ISD::ADD;
18733 Cond = X86::COND_O;
18736 BaseOp = X86ISD::ADD;
18737 Cond = X86::COND_B;
18740 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18741 // set CF, so we can't do this for USUBO.
18742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18744 BaseOp = X86ISD::DEC;
18745 Cond = X86::COND_O;
18748 BaseOp = X86ISD::SUB;
18749 Cond = X86::COND_O;
18752 BaseOp = X86ISD::SUB;
18753 Cond = X86::COND_B;
18756 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18757 Cond = X86::COND_O;
18759 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18760 if (N->getValueType(0) == MVT::i8) {
18761 BaseOp = X86ISD::UMUL8;
18762 Cond = X86::COND_O;
18765 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18767 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18770 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18771 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18772 SDValue(Sum.getNode(), 2));
18774 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18778 // Also sets EFLAGS.
18779 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18780 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18783 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18784 DAG.getConstant(Cond, DL, MVT::i32),
18785 SDValue(Sum.getNode(), 1));
18787 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18790 /// Returns true if the operand type is exactly twice the native width, and
18791 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18792 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18793 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18794 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18795 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18798 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18799 else if (OpWidth == 128)
18800 return Subtarget->hasCmpxchg16b();
18805 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18806 return needsCmpXchgNb(SI->getValueOperand()->getType());
18809 // Note: this turns large loads into lock cmpxchg8b/16b.
18810 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18811 TargetLowering::AtomicExpansionKind
18812 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18813 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18814 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18815 : AtomicExpansionKind::None;
18818 TargetLowering::AtomicExpansionKind
18819 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18820 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18821 Type *MemType = AI->getType();
18823 // If the operand is too big, we must see if cmpxchg8/16b is available
18824 // and default to library calls otherwise.
18825 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18826 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18827 : AtomicExpansionKind::None;
18830 AtomicRMWInst::BinOp Op = AI->getOperation();
18833 llvm_unreachable("Unknown atomic operation");
18834 case AtomicRMWInst::Xchg:
18835 case AtomicRMWInst::Add:
18836 case AtomicRMWInst::Sub:
18837 // It's better to use xadd, xsub or xchg for these in all cases.
18838 return AtomicExpansionKind::None;
18839 case AtomicRMWInst::Or:
18840 case AtomicRMWInst::And:
18841 case AtomicRMWInst::Xor:
18842 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18843 // prefix to a normal instruction for these operations.
18844 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18845 : AtomicExpansionKind::None;
18846 case AtomicRMWInst::Nand:
18847 case AtomicRMWInst::Max:
18848 case AtomicRMWInst::Min:
18849 case AtomicRMWInst::UMax:
18850 case AtomicRMWInst::UMin:
18851 // These always require a non-trivial set of data operations on x86. We must
18852 // use a cmpxchg loop.
18853 return AtomicExpansionKind::CmpXChg;
18857 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18858 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18859 // no-sse2). There isn't any reason to disable it if the target processor
18861 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18865 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18866 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18867 Type *MemType = AI->getType();
18868 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18869 // there is no benefit in turning such RMWs into loads, and it is actually
18870 // harmful as it introduces a mfence.
18871 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18874 auto Builder = IRBuilder<>(AI);
18875 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18876 auto SynchScope = AI->getSynchScope();
18877 // We must restrict the ordering to avoid generating loads with Release or
18878 // ReleaseAcquire orderings.
18879 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18880 auto Ptr = AI->getPointerOperand();
18882 // Before the load we need a fence. Here is an example lifted from
18883 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18886 // x.store(1, relaxed);
18887 // r1 = y.fetch_add(0, release);
18889 // y.fetch_add(42, acquire);
18890 // r2 = x.load(relaxed);
18891 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18892 // lowered to just a load without a fence. A mfence flushes the store buffer,
18893 // making the optimization clearly correct.
18894 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18895 // otherwise, we might be able to be more aggressive on relaxed idempotent
18896 // rmw. In practice, they do not look useful, so we don't try to be
18897 // especially clever.
18898 if (SynchScope == SingleThread)
18899 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18900 // the IR level, so we must wrap it in an intrinsic.
18903 if (!hasMFENCE(*Subtarget))
18904 // FIXME: it might make sense to use a locked operation here but on a
18905 // different cache-line to prevent cache-line bouncing. In practice it
18906 // is probably a small win, and x86 processors without mfence are rare
18907 // enough that we do not bother.
18911 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18912 Builder.CreateCall(MFence, {});
18914 // Finally we can emit the atomic load.
18915 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18916 AI->getType()->getPrimitiveSizeInBits());
18917 Loaded->setAtomic(Order, SynchScope);
18918 AI->replaceAllUsesWith(Loaded);
18919 AI->eraseFromParent();
18923 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18924 SelectionDAG &DAG) {
18926 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18927 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18928 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18929 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18931 // The only fence that needs an instruction is a sequentially-consistent
18932 // cross-thread fence.
18933 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18934 if (hasMFENCE(*Subtarget))
18935 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18937 SDValue Chain = Op.getOperand(0);
18938 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18940 DAG.getRegister(X86::ESP, MVT::i32), // Base
18941 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18942 DAG.getRegister(0, MVT::i32), // Index
18943 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18944 DAG.getRegister(0, MVT::i32), // Segment.
18948 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18949 return SDValue(Res, 0);
18952 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18953 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18956 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18957 SelectionDAG &DAG) {
18958 MVT T = Op.getSimpleValueType();
18962 switch(T.SimpleTy) {
18963 default: llvm_unreachable("Invalid value type!");
18964 case MVT::i8: Reg = X86::AL; size = 1; break;
18965 case MVT::i16: Reg = X86::AX; size = 2; break;
18966 case MVT::i32: Reg = X86::EAX; size = 4; break;
18968 assert(Subtarget->is64Bit() && "Node not type legal!");
18969 Reg = X86::RAX; size = 8;
18972 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18973 Op.getOperand(2), SDValue());
18974 SDValue Ops[] = { cpIn.getValue(0),
18977 DAG.getTargetConstant(size, DL, MVT::i8),
18978 cpIn.getValue(1) };
18979 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18980 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18981 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18985 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18986 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18987 MVT::i32, cpOut.getValue(2));
18988 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18989 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18992 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18993 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18994 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18998 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18999 SelectionDAG &DAG) {
19000 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19001 MVT DstVT = Op.getSimpleValueType();
19003 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19004 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19005 if (DstVT != MVT::f64)
19006 // This conversion needs to be expanded.
19009 SDValue InVec = Op->getOperand(0);
19011 unsigned NumElts = SrcVT.getVectorNumElements();
19012 EVT SVT = SrcVT.getVectorElementType();
19014 // Widen the vector in input in the case of MVT::v2i32.
19015 // Example: from MVT::v2i32 to MVT::v4i32.
19016 SmallVector<SDValue, 16> Elts;
19017 for (unsigned i = 0, e = NumElts; i != e; ++i)
19018 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19019 DAG.getIntPtrConstant(i, dl)));
19021 // Explicitly mark the extra elements as Undef.
19022 Elts.append(NumElts, DAG.getUNDEF(SVT));
19024 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19025 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19026 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19027 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19028 DAG.getIntPtrConstant(0, dl));
19031 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19032 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19033 assert((DstVT == MVT::i64 ||
19034 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19035 "Unexpected custom BITCAST");
19036 // i64 <=> MMX conversions are Legal.
19037 if (SrcVT==MVT::i64 && DstVT.isVector())
19039 if (DstVT==MVT::i64 && SrcVT.isVector())
19041 // MMX <=> MMX conversions are Legal.
19042 if (SrcVT.isVector() && DstVT.isVector())
19044 // All other conversions need to be expanded.
19048 /// Compute the horizontal sum of bytes in V for the elements of VT.
19050 /// Requires V to be a byte vector and VT to be an integer vector type with
19051 /// wider elements than V's type. The width of the elements of VT determines
19052 /// how many bytes of V are summed horizontally to produce each element of the
19054 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19055 const X86Subtarget *Subtarget,
19056 SelectionDAG &DAG) {
19058 MVT ByteVecVT = V.getSimpleValueType();
19059 MVT EltVT = VT.getVectorElementType();
19060 int NumElts = VT.getVectorNumElements();
19061 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19062 "Expected value to have byte element type.");
19063 assert(EltVT != MVT::i8 &&
19064 "Horizontal byte sum only makes sense for wider elements!");
19065 unsigned VecSize = VT.getSizeInBits();
19066 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19068 // PSADBW instruction horizontally add all bytes and leave the result in i64
19069 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19070 if (EltVT == MVT::i64) {
19071 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19072 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19073 return DAG.getBitcast(VT, V);
19076 if (EltVT == MVT::i32) {
19077 // We unpack the low half and high half into i32s interleaved with zeros so
19078 // that we can use PSADBW to horizontally sum them. The most useful part of
19079 // this is that it lines up the results of two PSADBW instructions to be
19080 // two v2i64 vectors which concatenated are the 4 population counts. We can
19081 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19082 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19083 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19084 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19086 // Do the horizontal sums into two v2i64s.
19087 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19088 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19089 DAG.getBitcast(ByteVecVT, Low), Zeros);
19090 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19091 DAG.getBitcast(ByteVecVT, High), Zeros);
19093 // Merge them together.
19094 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19095 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19096 DAG.getBitcast(ShortVecVT, Low),
19097 DAG.getBitcast(ShortVecVT, High));
19099 return DAG.getBitcast(VT, V);
19102 // The only element type left is i16.
19103 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19105 // To obtain pop count for each i16 element starting from the pop count for
19106 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19107 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19108 // directly supported.
19109 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19110 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19111 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19112 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19113 DAG.getBitcast(ByteVecVT, V));
19114 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19117 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19118 const X86Subtarget *Subtarget,
19119 SelectionDAG &DAG) {
19120 MVT VT = Op.getSimpleValueType();
19121 MVT EltVT = VT.getVectorElementType();
19122 unsigned VecSize = VT.getSizeInBits();
19124 // Implement a lookup table in register by using an algorithm based on:
19125 // http://wm.ite.pl/articles/sse-popcount.html
19127 // The general idea is that every lower byte nibble in the input vector is an
19128 // index into a in-register pre-computed pop count table. We then split up the
19129 // input vector in two new ones: (1) a vector with only the shifted-right
19130 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19131 // masked out higher ones) for each byte. PSHUB is used separately with both
19132 // to index the in-register table. Next, both are added and the result is a
19133 // i8 vector where each element contains the pop count for input byte.
19135 // To obtain the pop count for elements != i8, we follow up with the same
19136 // approach and use additional tricks as described below.
19138 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19139 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19140 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19141 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19143 int NumByteElts = VecSize / 8;
19144 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19145 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19146 SmallVector<SDValue, 16> LUTVec;
19147 for (int i = 0; i < NumByteElts; ++i)
19148 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19149 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19150 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19151 DAG.getConstant(0x0F, DL, MVT::i8));
19152 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19155 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19156 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19157 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19160 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19162 // The input vector is used as the shuffle mask that index elements into the
19163 // LUT. After counting low and high nibbles, add the vector to obtain the
19164 // final pop count per i8 element.
19165 SDValue HighPopCnt =
19166 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19167 SDValue LowPopCnt =
19168 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19169 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19171 if (EltVT == MVT::i8)
19174 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19177 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19178 const X86Subtarget *Subtarget,
19179 SelectionDAG &DAG) {
19180 MVT VT = Op.getSimpleValueType();
19181 assert(VT.is128BitVector() &&
19182 "Only 128-bit vector bitmath lowering supported.");
19184 int VecSize = VT.getSizeInBits();
19185 MVT EltVT = VT.getVectorElementType();
19186 int Len = EltVT.getSizeInBits();
19188 // This is the vectorized version of the "best" algorithm from
19189 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19190 // with a minor tweak to use a series of adds + shifts instead of vector
19191 // multiplications. Implemented for all integer vector types. We only use
19192 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19193 // much faster, even faster than using native popcnt instructions.
19195 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19196 MVT VT = V.getSimpleValueType();
19197 SmallVector<SDValue, 32> Shifters(
19198 VT.getVectorNumElements(),
19199 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19200 return DAG.getNode(OpCode, DL, VT, V,
19201 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19203 auto GetMask = [&](SDValue V, APInt Mask) {
19204 MVT VT = V.getSimpleValueType();
19205 SmallVector<SDValue, 32> Masks(
19206 VT.getVectorNumElements(),
19207 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19208 return DAG.getNode(ISD::AND, DL, VT, V,
19209 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19212 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19213 // x86, so set the SRL type to have elements at least i16 wide. This is
19214 // correct because all of our SRLs are followed immediately by a mask anyways
19215 // that handles any bits that sneak into the high bits of the byte elements.
19216 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19220 // v = v - ((v >> 1) & 0x55555555...)
19222 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19223 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19224 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19226 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19227 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19228 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19229 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19230 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19232 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19233 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19234 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19235 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19237 // At this point, V contains the byte-wise population count, and we are
19238 // merely doing a horizontal sum if necessary to get the wider element
19240 if (EltVT == MVT::i8)
19243 return LowerHorizontalByteSum(
19244 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19248 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19249 SelectionDAG &DAG) {
19250 MVT VT = Op.getSimpleValueType();
19251 // FIXME: Need to add AVX-512 support here!
19252 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19253 "Unknown CTPOP type to handle");
19254 SDLoc DL(Op.getNode());
19255 SDValue Op0 = Op.getOperand(0);
19257 if (!Subtarget->hasSSSE3()) {
19258 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19259 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19260 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19263 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19264 unsigned NumElems = VT.getVectorNumElements();
19266 // Extract each 128-bit vector, compute pop count and concat the result.
19267 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19268 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19270 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19271 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19272 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19275 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19278 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19279 SelectionDAG &DAG) {
19280 assert(Op.getValueType().isVector() &&
19281 "We only do custom lowering for vector population count.");
19282 return LowerVectorCTPOP(Op, Subtarget, DAG);
19285 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19286 SDNode *Node = Op.getNode();
19288 EVT T = Node->getValueType(0);
19289 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19290 DAG.getConstant(0, dl, T), Node->getOperand(2));
19291 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19292 cast<AtomicSDNode>(Node)->getMemoryVT(),
19293 Node->getOperand(0),
19294 Node->getOperand(1), negOp,
19295 cast<AtomicSDNode>(Node)->getMemOperand(),
19296 cast<AtomicSDNode>(Node)->getOrdering(),
19297 cast<AtomicSDNode>(Node)->getSynchScope());
19300 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19301 SDNode *Node = Op.getNode();
19303 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19305 // Convert seq_cst store -> xchg
19306 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19307 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19308 // (The only way to get a 16-byte store is cmpxchg16b)
19309 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19310 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19311 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19312 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19313 cast<AtomicSDNode>(Node)->getMemoryVT(),
19314 Node->getOperand(0),
19315 Node->getOperand(1), Node->getOperand(2),
19316 cast<AtomicSDNode>(Node)->getMemOperand(),
19317 cast<AtomicSDNode>(Node)->getOrdering(),
19318 cast<AtomicSDNode>(Node)->getSynchScope());
19319 return Swap.getValue(1);
19321 // Other atomic stores have a simple pattern.
19325 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19326 EVT VT = Op.getNode()->getSimpleValueType(0);
19328 // Let legalize expand this if it isn't a legal type yet.
19329 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19332 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19335 bool ExtraOp = false;
19336 switch (Op.getOpcode()) {
19337 default: llvm_unreachable("Invalid code");
19338 case ISD::ADDC: Opc = X86ISD::ADD; break;
19339 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19340 case ISD::SUBC: Opc = X86ISD::SUB; break;
19341 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19345 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19347 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19348 Op.getOperand(1), Op.getOperand(2));
19351 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19352 SelectionDAG &DAG) {
19353 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19355 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19356 // which returns the values as { float, float } (in XMM0) or
19357 // { double, double } (which is returned in XMM0, XMM1).
19359 SDValue Arg = Op.getOperand(0);
19360 EVT ArgVT = Arg.getValueType();
19361 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19363 TargetLowering::ArgListTy Args;
19364 TargetLowering::ArgListEntry Entry;
19368 Entry.isSExt = false;
19369 Entry.isZExt = false;
19370 Args.push_back(Entry);
19372 bool isF64 = ArgVT == MVT::f64;
19373 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19374 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19375 // the results are returned via SRet in memory.
19376 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19379 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19381 Type *RetTy = isF64
19382 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19383 : (Type*)VectorType::get(ArgTy, 4);
19385 TargetLowering::CallLoweringInfo CLI(DAG);
19386 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19387 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19389 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19392 // Returned in xmm0 and xmm1.
19393 return CallResult.first;
19395 // Returned in bits 0:31 and 32:64 xmm0.
19396 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19397 CallResult.first, DAG.getIntPtrConstant(0, dl));
19398 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19399 CallResult.first, DAG.getIntPtrConstant(1, dl));
19400 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19401 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19404 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19405 SelectionDAG &DAG) {
19406 assert(Subtarget->hasAVX512() &&
19407 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19409 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19410 EVT VT = N->getValue().getValueType();
19411 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19414 // X86 scatter kills mask register, so its type should be added to
19415 // the list of return values
19416 if (N->getNumValues() == 1) {
19417 SDValue Index = N->getIndex();
19418 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19419 !Index.getValueType().is512BitVector())
19420 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19422 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19423 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19424 N->getOperand(3), Index };
19426 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19427 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19428 return SDValue(NewScatter.getNode(), 0);
19433 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19434 SelectionDAG &DAG) {
19435 assert(Subtarget->hasAVX512() &&
19436 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19438 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19439 EVT VT = Op.getValueType();
19440 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19443 SDValue Index = N->getIndex();
19444 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19445 !Index.getValueType().is512BitVector()) {
19446 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19447 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19448 N->getOperand(3), Index };
19449 DAG.UpdateNodeOperands(N, Ops);
19454 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19455 SelectionDAG &DAG) const {
19456 // TODO: Eventually, the lowering of these nodes should be informed by or
19457 // deferred to the GC strategy for the function in which they appear. For
19458 // now, however, they must be lowered to something. Since they are logically
19459 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19460 // require special handling for these nodes), lower them as literal NOOPs for
19462 SmallVector<SDValue, 2> Ops;
19464 Ops.push_back(Op.getOperand(0));
19465 if (Op->getGluedNode())
19466 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19469 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19470 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19475 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19476 SelectionDAG &DAG) const {
19477 // TODO: Eventually, the lowering of these nodes should be informed by or
19478 // deferred to the GC strategy for the function in which they appear. For
19479 // now, however, they must be lowered to something. Since they are logically
19480 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19481 // require special handling for these nodes), lower them as literal NOOPs for
19483 SmallVector<SDValue, 2> Ops;
19485 Ops.push_back(Op.getOperand(0));
19486 if (Op->getGluedNode())
19487 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19490 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19491 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19496 /// LowerOperation - Provide custom lowering hooks for some operations.
19498 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19499 switch (Op.getOpcode()) {
19500 default: llvm_unreachable("Should not custom lower this!");
19501 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19502 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19503 return LowerCMP_SWAP(Op, Subtarget, DAG);
19504 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19505 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19506 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19507 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19508 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19509 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19510 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19511 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19512 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19513 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19514 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19515 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19516 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19517 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19518 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19519 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19520 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19521 case ISD::SHL_PARTS:
19522 case ISD::SRA_PARTS:
19523 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19524 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19525 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19526 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19527 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19528 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19529 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19530 case ISD::SIGN_EXTEND_VECTOR_INREG:
19531 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19532 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19533 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19534 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19535 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19537 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19538 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19539 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19540 case ISD::SETCC: return LowerSETCC(Op, DAG);
19541 case ISD::SELECT: return LowerSELECT(Op, DAG);
19542 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19543 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19544 case ISD::VASTART: return LowerVASTART(Op, DAG);
19545 case ISD::VAARG: return LowerVAARG(Op, DAG);
19546 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19547 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19548 case ISD::INTRINSIC_VOID:
19549 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19550 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19551 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19552 case ISD::FRAME_TO_ARGS_OFFSET:
19553 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19554 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19555 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19556 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19557 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19558 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19559 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19560 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19561 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19562 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19564 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19565 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19566 case ISD::UMUL_LOHI:
19567 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19570 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19576 case ISD::UMULO: return LowerXALUO(Op, DAG);
19577 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19578 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19582 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19583 case ISD::ADD: return LowerADD(Op, DAG);
19584 case ISD::SUB: return LowerSUB(Op, DAG);
19588 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19589 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19590 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19591 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19592 case ISD::GC_TRANSITION_START:
19593 return LowerGC_TRANSITION_START(Op, DAG);
19594 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19598 /// ReplaceNodeResults - Replace a node with an illegal result type
19599 /// with a new node built out of custom code.
19600 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19601 SmallVectorImpl<SDValue>&Results,
19602 SelectionDAG &DAG) const {
19604 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19605 switch (N->getOpcode()) {
19607 llvm_unreachable("Do not know how to custom type legalize this operation!");
19608 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19609 case X86ISD::FMINC:
19611 case X86ISD::FMAXC:
19612 case X86ISD::FMAX: {
19613 EVT VT = N->getValueType(0);
19614 if (VT != MVT::v2f32)
19615 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19616 SDValue UNDEF = DAG.getUNDEF(VT);
19617 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19618 N->getOperand(0), UNDEF);
19619 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19620 N->getOperand(1), UNDEF);
19621 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19624 case ISD::SIGN_EXTEND_INREG:
19629 // We don't want to expand or promote these.
19636 case ISD::UDIVREM: {
19637 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19638 Results.push_back(V);
19641 case ISD::FP_TO_SINT:
19642 case ISD::FP_TO_UINT: {
19643 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19645 std::pair<SDValue,SDValue> Vals =
19646 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19647 SDValue FIST = Vals.first, StackSlot = Vals.second;
19648 if (FIST.getNode()) {
19649 EVT VT = N->getValueType(0);
19650 // Return a load from the stack slot.
19651 if (StackSlot.getNode())
19652 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19653 MachinePointerInfo(),
19654 false, false, false, 0));
19656 Results.push_back(FIST);
19660 case ISD::UINT_TO_FP: {
19661 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19662 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19663 N->getValueType(0) != MVT::v2f32)
19665 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19667 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19669 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19670 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19671 DAG.getBitcast(MVT::v2i64, VBias));
19672 Or = DAG.getBitcast(MVT::v2f64, Or);
19673 // TODO: Are there any fast-math-flags to propagate here?
19674 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19675 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19678 case ISD::FP_ROUND: {
19679 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19681 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19682 Results.push_back(V);
19685 case ISD::FP_EXTEND: {
19686 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19687 // No other ValueType for FP_EXTEND should reach this point.
19688 assert(N->getValueType(0) == MVT::v2f32 &&
19689 "Do not know how to legalize this Node");
19692 case ISD::INTRINSIC_W_CHAIN: {
19693 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19695 default : llvm_unreachable("Do not know how to custom type "
19696 "legalize this intrinsic operation!");
19697 case Intrinsic::x86_rdtsc:
19698 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19700 case Intrinsic::x86_rdtscp:
19701 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19703 case Intrinsic::x86_rdpmc:
19704 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19707 case ISD::READCYCLECOUNTER: {
19708 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19711 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19712 EVT T = N->getValueType(0);
19713 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19714 bool Regs64bit = T == MVT::i128;
19715 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19716 SDValue cpInL, cpInH;
19717 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19718 DAG.getConstant(0, dl, HalfT));
19719 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19720 DAG.getConstant(1, dl, HalfT));
19721 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19722 Regs64bit ? X86::RAX : X86::EAX,
19724 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19725 Regs64bit ? X86::RDX : X86::EDX,
19726 cpInH, cpInL.getValue(1));
19727 SDValue swapInL, swapInH;
19728 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19729 DAG.getConstant(0, dl, HalfT));
19730 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19731 DAG.getConstant(1, dl, HalfT));
19732 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19733 Regs64bit ? X86::RBX : X86::EBX,
19734 swapInL, cpInH.getValue(1));
19735 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19736 Regs64bit ? X86::RCX : X86::ECX,
19737 swapInH, swapInL.getValue(1));
19738 SDValue Ops[] = { swapInH.getValue(0),
19740 swapInH.getValue(1) };
19741 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19742 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19743 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19744 X86ISD::LCMPXCHG8_DAG;
19745 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19746 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19747 Regs64bit ? X86::RAX : X86::EAX,
19748 HalfT, Result.getValue(1));
19749 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19750 Regs64bit ? X86::RDX : X86::EDX,
19751 HalfT, cpOutL.getValue(2));
19752 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19754 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19755 MVT::i32, cpOutH.getValue(2));
19757 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19758 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19759 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19761 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19762 Results.push_back(Success);
19763 Results.push_back(EFLAGS.getValue(1));
19766 case ISD::ATOMIC_SWAP:
19767 case ISD::ATOMIC_LOAD_ADD:
19768 case ISD::ATOMIC_LOAD_SUB:
19769 case ISD::ATOMIC_LOAD_AND:
19770 case ISD::ATOMIC_LOAD_OR:
19771 case ISD::ATOMIC_LOAD_XOR:
19772 case ISD::ATOMIC_LOAD_NAND:
19773 case ISD::ATOMIC_LOAD_MIN:
19774 case ISD::ATOMIC_LOAD_MAX:
19775 case ISD::ATOMIC_LOAD_UMIN:
19776 case ISD::ATOMIC_LOAD_UMAX:
19777 case ISD::ATOMIC_LOAD: {
19778 // Delegate to generic TypeLegalization. Situations we can really handle
19779 // should have already been dealt with by AtomicExpandPass.cpp.
19782 case ISD::BITCAST: {
19783 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19784 EVT DstVT = N->getValueType(0);
19785 EVT SrcVT = N->getOperand(0)->getValueType(0);
19787 if (SrcVT != MVT::f64 ||
19788 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19791 unsigned NumElts = DstVT.getVectorNumElements();
19792 EVT SVT = DstVT.getVectorElementType();
19793 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19794 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19795 MVT::v2f64, N->getOperand(0));
19796 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19798 if (ExperimentalVectorWideningLegalization) {
19799 // If we are legalizing vectors by widening, we already have the desired
19800 // legal vector type, just return it.
19801 Results.push_back(ToVecInt);
19805 SmallVector<SDValue, 8> Elts;
19806 for (unsigned i = 0, e = NumElts; i != e; ++i)
19807 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19808 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19810 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19815 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19816 switch ((X86ISD::NodeType)Opcode) {
19817 case X86ISD::FIRST_NUMBER: break;
19818 case X86ISD::BSF: return "X86ISD::BSF";
19819 case X86ISD::BSR: return "X86ISD::BSR";
19820 case X86ISD::SHLD: return "X86ISD::SHLD";
19821 case X86ISD::SHRD: return "X86ISD::SHRD";
19822 case X86ISD::FAND: return "X86ISD::FAND";
19823 case X86ISD::FANDN: return "X86ISD::FANDN";
19824 case X86ISD::FOR: return "X86ISD::FOR";
19825 case X86ISD::FXOR: return "X86ISD::FXOR";
19826 case X86ISD::FILD: return "X86ISD::FILD";
19827 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19828 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19829 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19830 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19831 case X86ISD::FLD: return "X86ISD::FLD";
19832 case X86ISD::FST: return "X86ISD::FST";
19833 case X86ISD::CALL: return "X86ISD::CALL";
19834 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19835 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19836 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19837 case X86ISD::BT: return "X86ISD::BT";
19838 case X86ISD::CMP: return "X86ISD::CMP";
19839 case X86ISD::COMI: return "X86ISD::COMI";
19840 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19841 case X86ISD::CMPM: return "X86ISD::CMPM";
19842 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19843 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19844 case X86ISD::SETCC: return "X86ISD::SETCC";
19845 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19846 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19847 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19848 case X86ISD::CMOV: return "X86ISD::CMOV";
19849 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19850 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19851 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19852 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19853 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19854 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19855 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19856 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19857 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19858 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19859 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19860 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19861 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19862 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19863 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19864 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19865 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19866 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19867 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19868 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19869 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19870 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19871 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19872 case X86ISD::HADD: return "X86ISD::HADD";
19873 case X86ISD::HSUB: return "X86ISD::HSUB";
19874 case X86ISD::FHADD: return "X86ISD::FHADD";
19875 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19876 case X86ISD::ABS: return "X86ISD::ABS";
19877 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19878 case X86ISD::FMAX: return "X86ISD::FMAX";
19879 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19880 case X86ISD::FMIN: return "X86ISD::FMIN";
19881 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19882 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19883 case X86ISD::FMINC: return "X86ISD::FMINC";
19884 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19885 case X86ISD::FRCP: return "X86ISD::FRCP";
19886 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19887 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19888 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19889 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19890 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19891 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19892 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19893 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19894 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19895 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19896 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19897 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19898 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19899 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19900 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19901 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19902 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19903 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19904 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19905 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19906 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19907 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19908 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19909 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19910 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19911 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19912 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19913 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19914 case X86ISD::VSHL: return "X86ISD::VSHL";
19915 case X86ISD::VSRL: return "X86ISD::VSRL";
19916 case X86ISD::VSRA: return "X86ISD::VSRA";
19917 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19918 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19919 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19920 case X86ISD::CMPP: return "X86ISD::CMPP";
19921 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19922 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19923 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19924 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19925 case X86ISD::ADD: return "X86ISD::ADD";
19926 case X86ISD::SUB: return "X86ISD::SUB";
19927 case X86ISD::ADC: return "X86ISD::ADC";
19928 case X86ISD::SBB: return "X86ISD::SBB";
19929 case X86ISD::SMUL: return "X86ISD::SMUL";
19930 case X86ISD::UMUL: return "X86ISD::UMUL";
19931 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19932 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19933 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19934 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19935 case X86ISD::INC: return "X86ISD::INC";
19936 case X86ISD::DEC: return "X86ISD::DEC";
19937 case X86ISD::OR: return "X86ISD::OR";
19938 case X86ISD::XOR: return "X86ISD::XOR";
19939 case X86ISD::AND: return "X86ISD::AND";
19940 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19941 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19942 case X86ISD::PTEST: return "X86ISD::PTEST";
19943 case X86ISD::TESTP: return "X86ISD::TESTP";
19944 case X86ISD::TESTM: return "X86ISD::TESTM";
19945 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19946 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19947 case X86ISD::KTEST: return "X86ISD::KTEST";
19948 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19949 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19950 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19951 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19952 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19953 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19954 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19955 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19956 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19957 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19958 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19959 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19960 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19961 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19962 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19963 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19964 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19965 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19966 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19967 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19968 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19969 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19970 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19971 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19972 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19973 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19974 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19975 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19976 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19977 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19978 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19979 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
19980 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19981 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19982 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19983 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19984 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19985 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19986 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19987 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19988 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19989 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19990 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19991 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19992 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19993 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19994 case X86ISD::SAHF: return "X86ISD::SAHF";
19995 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19996 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19997 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19998 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19999 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20000 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20001 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20002 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20003 case X86ISD::FMADD: return "X86ISD::FMADD";
20004 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20005 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20006 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20007 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20008 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20009 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20010 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20011 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20012 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20013 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20014 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20015 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20016 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20017 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20018 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20019 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20020 case X86ISD::XTEST: return "X86ISD::XTEST";
20021 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20022 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20023 case X86ISD::SELECT: return "X86ISD::SELECT";
20024 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20025 case X86ISD::RCP28: return "X86ISD::RCP28";
20026 case X86ISD::EXP2: return "X86ISD::EXP2";
20027 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20028 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20029 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20030 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20031 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20032 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20033 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20034 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20035 case X86ISD::ADDS: return "X86ISD::ADDS";
20036 case X86ISD::SUBS: return "X86ISD::SUBS";
20037 case X86ISD::AVG: return "X86ISD::AVG";
20038 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20039 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20040 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20041 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20042 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20043 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20048 // isLegalAddressingMode - Return true if the addressing mode represented
20049 // by AM is legal for this target, for a load/store of the specified type.
20050 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20051 const AddrMode &AM, Type *Ty,
20052 unsigned AS) const {
20053 // X86 supports extremely general addressing modes.
20054 CodeModel::Model M = getTargetMachine().getCodeModel();
20055 Reloc::Model R = getTargetMachine().getRelocationModel();
20057 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20058 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20063 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20065 // If a reference to this global requires an extra load, we can't fold it.
20066 if (isGlobalStubReference(GVFlags))
20069 // If BaseGV requires a register for the PIC base, we cannot also have a
20070 // BaseReg specified.
20071 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20074 // If lower 4G is not available, then we must use rip-relative addressing.
20075 if ((M != CodeModel::Small || R != Reloc::Static) &&
20076 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20080 switch (AM.Scale) {
20086 // These scales always work.
20091 // These scales are formed with basereg+scalereg. Only accept if there is
20096 default: // Other stuff never works.
20103 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20104 unsigned Bits = Ty->getScalarSizeInBits();
20106 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20107 // particularly cheaper than those without.
20111 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20112 // variable shifts just as cheap as scalar ones.
20113 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20116 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20117 // fully general vector.
20121 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20122 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20124 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20125 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20126 return NumBits1 > NumBits2;
20129 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20130 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20133 if (!isTypeLegal(EVT::getEVT(Ty1)))
20136 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20138 // Assuming the caller doesn't have a zeroext or signext return parameter,
20139 // truncation all the way down to i1 is valid.
20143 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20144 return isInt<32>(Imm);
20147 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20148 // Can also use sub to handle negated immediates.
20149 return isInt<32>(Imm);
20152 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20153 if (!VT1.isInteger() || !VT2.isInteger())
20155 unsigned NumBits1 = VT1.getSizeInBits();
20156 unsigned NumBits2 = VT2.getSizeInBits();
20157 return NumBits1 > NumBits2;
20160 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20161 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20162 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20165 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20166 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20167 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20170 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20171 EVT VT1 = Val.getValueType();
20172 if (isZExtFree(VT1, VT2))
20175 if (Val.getOpcode() != ISD::LOAD)
20178 if (!VT1.isSimple() || !VT1.isInteger() ||
20179 !VT2.isSimple() || !VT2.isInteger())
20182 switch (VT1.getSimpleVT().SimpleTy) {
20187 // X86 has 8, 16, and 32-bit zero-extending loads.
20194 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20197 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20198 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20201 VT = VT.getScalarType();
20203 if (!VT.isSimple())
20206 switch (VT.getSimpleVT().SimpleTy) {
20217 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20218 // i16 instructions are longer (0x66 prefix) and potentially slower.
20219 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20222 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20223 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20224 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20225 /// are assumed to be legal.
20227 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20229 if (!VT.isSimple())
20232 // Not for i1 vectors
20233 if (VT.getScalarType() == MVT::i1)
20236 // Very little shuffling can be done for 64-bit vectors right now.
20237 if (VT.getSizeInBits() == 64)
20240 // We only care that the types being shuffled are legal. The lowering can
20241 // handle any possible shuffle mask that results.
20242 return isTypeLegal(VT.getSimpleVT());
20246 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20248 // Just delegate to the generic legality, clear masks aren't special.
20249 return isShuffleMaskLegal(Mask, VT);
20252 //===----------------------------------------------------------------------===//
20253 // X86 Scheduler Hooks
20254 //===----------------------------------------------------------------------===//
20256 /// Utility function to emit xbegin specifying the start of an RTM region.
20257 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20258 const TargetInstrInfo *TII) {
20259 DebugLoc DL = MI->getDebugLoc();
20261 const BasicBlock *BB = MBB->getBasicBlock();
20262 MachineFunction::iterator I = MBB;
20265 // For the v = xbegin(), we generate
20276 MachineBasicBlock *thisMBB = MBB;
20277 MachineFunction *MF = MBB->getParent();
20278 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20279 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20280 MF->insert(I, mainMBB);
20281 MF->insert(I, sinkMBB);
20283 // Transfer the remainder of BB and its successor edges to sinkMBB.
20284 sinkMBB->splice(sinkMBB->begin(), MBB,
20285 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20286 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20290 // # fallthrough to mainMBB
20291 // # abortion to sinkMBB
20292 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20293 thisMBB->addSuccessor(mainMBB);
20294 thisMBB->addSuccessor(sinkMBB);
20298 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20299 mainMBB->addSuccessor(sinkMBB);
20302 // EAX is live into the sinkMBB
20303 sinkMBB->addLiveIn(X86::EAX);
20304 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20305 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20308 MI->eraseFromParent();
20312 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20313 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20314 // in the .td file.
20315 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20316 const TargetInstrInfo *TII) {
20318 switch (MI->getOpcode()) {
20319 default: llvm_unreachable("illegal opcode!");
20320 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20321 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20322 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20323 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20324 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20325 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20326 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20327 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20330 DebugLoc dl = MI->getDebugLoc();
20331 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20333 unsigned NumArgs = MI->getNumOperands();
20334 for (unsigned i = 1; i < NumArgs; ++i) {
20335 MachineOperand &Op = MI->getOperand(i);
20336 if (!(Op.isReg() && Op.isImplicit()))
20337 MIB.addOperand(Op);
20339 if (MI->hasOneMemOperand())
20340 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20342 BuildMI(*BB, MI, dl,
20343 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20344 .addReg(X86::XMM0);
20346 MI->eraseFromParent();
20350 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20351 // defs in an instruction pattern
20352 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20353 const TargetInstrInfo *TII) {
20355 switch (MI->getOpcode()) {
20356 default: llvm_unreachable("illegal opcode!");
20357 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20358 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20359 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20360 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20361 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20362 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20363 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20364 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20367 DebugLoc dl = MI->getDebugLoc();
20368 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20370 unsigned NumArgs = MI->getNumOperands(); // remove the results
20371 for (unsigned i = 1; i < NumArgs; ++i) {
20372 MachineOperand &Op = MI->getOperand(i);
20373 if (!(Op.isReg() && Op.isImplicit()))
20374 MIB.addOperand(Op);
20376 if (MI->hasOneMemOperand())
20377 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20379 BuildMI(*BB, MI, dl,
20380 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20383 MI->eraseFromParent();
20387 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20388 const X86Subtarget *Subtarget) {
20389 DebugLoc dl = MI->getDebugLoc();
20390 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20391 // Address into RAX/EAX, other two args into ECX, EDX.
20392 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20393 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20394 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20395 for (int i = 0; i < X86::AddrNumOperands; ++i)
20396 MIB.addOperand(MI->getOperand(i));
20398 unsigned ValOps = X86::AddrNumOperands;
20399 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20400 .addReg(MI->getOperand(ValOps).getReg());
20401 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20402 .addReg(MI->getOperand(ValOps+1).getReg());
20404 // The instruction doesn't actually take any operands though.
20405 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20407 MI->eraseFromParent(); // The pseudo is gone now.
20411 MachineBasicBlock *
20412 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20413 MachineBasicBlock *MBB) const {
20414 // Emit va_arg instruction on X86-64.
20416 // Operands to this pseudo-instruction:
20417 // 0 ) Output : destination address (reg)
20418 // 1-5) Input : va_list address (addr, i64mem)
20419 // 6 ) ArgSize : Size (in bytes) of vararg type
20420 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20421 // 8 ) Align : Alignment of type
20422 // 9 ) EFLAGS (implicit-def)
20424 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20425 static_assert(X86::AddrNumOperands == 5,
20426 "VAARG_64 assumes 5 address operands");
20428 unsigned DestReg = MI->getOperand(0).getReg();
20429 MachineOperand &Base = MI->getOperand(1);
20430 MachineOperand &Scale = MI->getOperand(2);
20431 MachineOperand &Index = MI->getOperand(3);
20432 MachineOperand &Disp = MI->getOperand(4);
20433 MachineOperand &Segment = MI->getOperand(5);
20434 unsigned ArgSize = MI->getOperand(6).getImm();
20435 unsigned ArgMode = MI->getOperand(7).getImm();
20436 unsigned Align = MI->getOperand(8).getImm();
20438 // Memory Reference
20439 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20440 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20441 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20443 // Machine Information
20444 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20445 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20446 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20447 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20448 DebugLoc DL = MI->getDebugLoc();
20450 // struct va_list {
20453 // i64 overflow_area (address)
20454 // i64 reg_save_area (address)
20456 // sizeof(va_list) = 24
20457 // alignment(va_list) = 8
20459 unsigned TotalNumIntRegs = 6;
20460 unsigned TotalNumXMMRegs = 8;
20461 bool UseGPOffset = (ArgMode == 1);
20462 bool UseFPOffset = (ArgMode == 2);
20463 unsigned MaxOffset = TotalNumIntRegs * 8 +
20464 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20466 /* Align ArgSize to a multiple of 8 */
20467 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20468 bool NeedsAlign = (Align > 8);
20470 MachineBasicBlock *thisMBB = MBB;
20471 MachineBasicBlock *overflowMBB;
20472 MachineBasicBlock *offsetMBB;
20473 MachineBasicBlock *endMBB;
20475 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20476 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20477 unsigned OffsetReg = 0;
20479 if (!UseGPOffset && !UseFPOffset) {
20480 // If we only pull from the overflow region, we don't create a branch.
20481 // We don't need to alter control flow.
20482 OffsetDestReg = 0; // unused
20483 OverflowDestReg = DestReg;
20485 offsetMBB = nullptr;
20486 overflowMBB = thisMBB;
20489 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20490 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20491 // If not, pull from overflow_area. (branch to overflowMBB)
20496 // offsetMBB overflowMBB
20501 // Registers for the PHI in endMBB
20502 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20503 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20505 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20506 MachineFunction *MF = MBB->getParent();
20507 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20508 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20509 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20511 MachineFunction::iterator MBBIter = MBB;
20514 // Insert the new basic blocks
20515 MF->insert(MBBIter, offsetMBB);
20516 MF->insert(MBBIter, overflowMBB);
20517 MF->insert(MBBIter, endMBB);
20519 // Transfer the remainder of MBB and its successor edges to endMBB.
20520 endMBB->splice(endMBB->begin(), thisMBB,
20521 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20522 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20524 // Make offsetMBB and overflowMBB successors of thisMBB
20525 thisMBB->addSuccessor(offsetMBB);
20526 thisMBB->addSuccessor(overflowMBB);
20528 // endMBB is a successor of both offsetMBB and overflowMBB
20529 offsetMBB->addSuccessor(endMBB);
20530 overflowMBB->addSuccessor(endMBB);
20532 // Load the offset value into a register
20533 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20534 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20538 .addDisp(Disp, UseFPOffset ? 4 : 0)
20539 .addOperand(Segment)
20540 .setMemRefs(MMOBegin, MMOEnd);
20542 // Check if there is enough room left to pull this argument.
20543 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20545 .addImm(MaxOffset + 8 - ArgSizeA8);
20547 // Branch to "overflowMBB" if offset >= max
20548 // Fall through to "offsetMBB" otherwise
20549 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20550 .addMBB(overflowMBB);
20553 // In offsetMBB, emit code to use the reg_save_area.
20555 assert(OffsetReg != 0);
20557 // Read the reg_save_area address.
20558 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20559 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20564 .addOperand(Segment)
20565 .setMemRefs(MMOBegin, MMOEnd);
20567 // Zero-extend the offset
20568 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20569 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20572 .addImm(X86::sub_32bit);
20574 // Add the offset to the reg_save_area to get the final address.
20575 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20576 .addReg(OffsetReg64)
20577 .addReg(RegSaveReg);
20579 // Compute the offset for the next argument
20580 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20581 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20583 .addImm(UseFPOffset ? 16 : 8);
20585 // Store it back into the va_list.
20586 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20590 .addDisp(Disp, UseFPOffset ? 4 : 0)
20591 .addOperand(Segment)
20592 .addReg(NextOffsetReg)
20593 .setMemRefs(MMOBegin, MMOEnd);
20596 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20601 // Emit code to use overflow area
20604 // Load the overflow_area address into a register.
20605 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20606 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20611 .addOperand(Segment)
20612 .setMemRefs(MMOBegin, MMOEnd);
20614 // If we need to align it, do so. Otherwise, just copy the address
20615 // to OverflowDestReg.
20617 // Align the overflow address
20618 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20619 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20621 // aligned_addr = (addr + (align-1)) & ~(align-1)
20622 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20623 .addReg(OverflowAddrReg)
20626 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20628 .addImm(~(uint64_t)(Align-1));
20630 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20631 .addReg(OverflowAddrReg);
20634 // Compute the next overflow address after this argument.
20635 // (the overflow address should be kept 8-byte aligned)
20636 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20637 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20638 .addReg(OverflowDestReg)
20639 .addImm(ArgSizeA8);
20641 // Store the new overflow address.
20642 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20647 .addOperand(Segment)
20648 .addReg(NextAddrReg)
20649 .setMemRefs(MMOBegin, MMOEnd);
20651 // If we branched, emit the PHI to the front of endMBB.
20653 BuildMI(*endMBB, endMBB->begin(), DL,
20654 TII->get(X86::PHI), DestReg)
20655 .addReg(OffsetDestReg).addMBB(offsetMBB)
20656 .addReg(OverflowDestReg).addMBB(overflowMBB);
20659 // Erase the pseudo instruction
20660 MI->eraseFromParent();
20665 MachineBasicBlock *
20666 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20668 MachineBasicBlock *MBB) const {
20669 // Emit code to save XMM registers to the stack. The ABI says that the
20670 // number of registers to save is given in %al, so it's theoretically
20671 // possible to do an indirect jump trick to avoid saving all of them,
20672 // however this code takes a simpler approach and just executes all
20673 // of the stores if %al is non-zero. It's less code, and it's probably
20674 // easier on the hardware branch predictor, and stores aren't all that
20675 // expensive anyway.
20677 // Create the new basic blocks. One block contains all the XMM stores,
20678 // and one block is the final destination regardless of whether any
20679 // stores were performed.
20680 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20681 MachineFunction *F = MBB->getParent();
20682 MachineFunction::iterator MBBIter = MBB;
20684 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20685 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20686 F->insert(MBBIter, XMMSaveMBB);
20687 F->insert(MBBIter, EndMBB);
20689 // Transfer the remainder of MBB and its successor edges to EndMBB.
20690 EndMBB->splice(EndMBB->begin(), MBB,
20691 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20692 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20694 // The original block will now fall through to the XMM save block.
20695 MBB->addSuccessor(XMMSaveMBB);
20696 // The XMMSaveMBB will fall through to the end block.
20697 XMMSaveMBB->addSuccessor(EndMBB);
20699 // Now add the instructions.
20700 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20701 DebugLoc DL = MI->getDebugLoc();
20703 unsigned CountReg = MI->getOperand(0).getReg();
20704 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20705 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20707 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20708 // If %al is 0, branch around the XMM save block.
20709 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20710 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20711 MBB->addSuccessor(EndMBB);
20714 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20715 // that was just emitted, but clearly shouldn't be "saved".
20716 assert((MI->getNumOperands() <= 3 ||
20717 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20718 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20719 && "Expected last argument to be EFLAGS");
20720 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20721 // In the XMM save block, save all the XMM argument registers.
20722 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20723 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20724 MachineMemOperand *MMO = F->getMachineMemOperand(
20725 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20726 MachineMemOperand::MOStore,
20727 /*Size=*/16, /*Align=*/16);
20728 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20729 .addFrameIndex(RegSaveFrameIndex)
20730 .addImm(/*Scale=*/1)
20731 .addReg(/*IndexReg=*/0)
20732 .addImm(/*Disp=*/Offset)
20733 .addReg(/*Segment=*/0)
20734 .addReg(MI->getOperand(i).getReg())
20735 .addMemOperand(MMO);
20738 MI->eraseFromParent(); // The pseudo instruction is gone now.
20743 // The EFLAGS operand of SelectItr might be missing a kill marker
20744 // because there were multiple uses of EFLAGS, and ISel didn't know
20745 // which to mark. Figure out whether SelectItr should have had a
20746 // kill marker, and set it if it should. Returns the correct kill
20748 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20749 MachineBasicBlock* BB,
20750 const TargetRegisterInfo* TRI) {
20751 // Scan forward through BB for a use/def of EFLAGS.
20752 MachineBasicBlock::iterator miI(std::next(SelectItr));
20753 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20754 const MachineInstr& mi = *miI;
20755 if (mi.readsRegister(X86::EFLAGS))
20757 if (mi.definesRegister(X86::EFLAGS))
20758 break; // Should have kill-flag - update below.
20761 // If we hit the end of the block, check whether EFLAGS is live into a
20763 if (miI == BB->end()) {
20764 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20765 sEnd = BB->succ_end();
20766 sItr != sEnd; ++sItr) {
20767 MachineBasicBlock* succ = *sItr;
20768 if (succ->isLiveIn(X86::EFLAGS))
20773 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20774 // out. SelectMI should have a kill flag on EFLAGS.
20775 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20779 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20780 // together with other CMOV pseudo-opcodes into a single basic-block with
20781 // conditional jump around it.
20782 static bool isCMOVPseudo(MachineInstr *MI) {
20783 switch (MI->getOpcode()) {
20784 case X86::CMOV_FR32:
20785 case X86::CMOV_FR64:
20786 case X86::CMOV_GR8:
20787 case X86::CMOV_GR16:
20788 case X86::CMOV_GR32:
20789 case X86::CMOV_RFP32:
20790 case X86::CMOV_RFP64:
20791 case X86::CMOV_RFP80:
20792 case X86::CMOV_V2F64:
20793 case X86::CMOV_V2I64:
20794 case X86::CMOV_V4F32:
20795 case X86::CMOV_V4F64:
20796 case X86::CMOV_V4I64:
20797 case X86::CMOV_V16F32:
20798 case X86::CMOV_V8F32:
20799 case X86::CMOV_V8F64:
20800 case X86::CMOV_V8I64:
20801 case X86::CMOV_V8I1:
20802 case X86::CMOV_V16I1:
20803 case X86::CMOV_V32I1:
20804 case X86::CMOV_V64I1:
20812 MachineBasicBlock *
20813 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20814 MachineBasicBlock *BB) const {
20815 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20816 DebugLoc DL = MI->getDebugLoc();
20818 // To "insert" a SELECT_CC instruction, we actually have to insert the
20819 // diamond control-flow pattern. The incoming instruction knows the
20820 // destination vreg to set, the condition code register to branch on, the
20821 // true/false values to select between, and a branch opcode to use.
20822 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20823 MachineFunction::iterator It = BB;
20829 // cmpTY ccX, r1, r2
20831 // fallthrough --> copy0MBB
20832 MachineBasicBlock *thisMBB = BB;
20833 MachineFunction *F = BB->getParent();
20835 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20836 // as described above, by inserting a BB, and then making a PHI at the join
20837 // point to select the true and false operands of the CMOV in the PHI.
20839 // The code also handles two different cases of multiple CMOV opcodes
20843 // In this case, there are multiple CMOVs in a row, all which are based on
20844 // the same condition setting (or the exact opposite condition setting).
20845 // In this case we can lower all the CMOVs using a single inserted BB, and
20846 // then make a number of PHIs at the join point to model the CMOVs. The only
20847 // trickiness here, is that in a case like:
20849 // t2 = CMOV cond1 t1, f1
20850 // t3 = CMOV cond1 t2, f2
20852 // when rewriting this into PHIs, we have to perform some renaming on the
20853 // temps since you cannot have a PHI operand refer to a PHI result earlier
20854 // in the same block. The "simple" but wrong lowering would be:
20856 // t2 = PHI t1(BB1), f1(BB2)
20857 // t3 = PHI t2(BB1), f2(BB2)
20859 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20860 // renaming is to note that on the path through BB1, t2 is really just a
20861 // copy of t1, and do that renaming, properly generating:
20863 // t2 = PHI t1(BB1), f1(BB2)
20864 // t3 = PHI t1(BB1), f2(BB2)
20866 // Case 2, we lower cascaded CMOVs such as
20868 // (CMOV (CMOV F, T, cc1), T, cc2)
20870 // to two successives branches. For that, we look for another CMOV as the
20871 // following instruction.
20873 // Without this, we would add a PHI between the two jumps, which ends up
20874 // creating a few copies all around. For instance, for
20876 // (sitofp (zext (fcmp une)))
20878 // we would generate:
20880 // ucomiss %xmm1, %xmm0
20881 // movss <1.0f>, %xmm0
20882 // movaps %xmm0, %xmm1
20884 // xorps %xmm1, %xmm1
20887 // movaps %xmm1, %xmm0
20891 // because this custom-inserter would have generated:
20903 // A: X = ...; Y = ...
20905 // C: Z = PHI [X, A], [Y, B]
20907 // E: PHI [X, C], [Z, D]
20909 // If we lower both CMOVs in a single step, we can instead generate:
20921 // A: X = ...; Y = ...
20923 // E: PHI [X, A], [X, C], [Y, D]
20925 // Which, in our sitofp/fcmp example, gives us something like:
20927 // ucomiss %xmm1, %xmm0
20928 // movss <1.0f>, %xmm0
20931 // xorps %xmm0, %xmm0
20935 MachineInstr *CascadedCMOV = nullptr;
20936 MachineInstr *LastCMOV = MI;
20937 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20938 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20939 MachineBasicBlock::iterator NextMIIt =
20940 std::next(MachineBasicBlock::iterator(MI));
20942 // Check for case 1, where there are multiple CMOVs with the same condition
20943 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20944 // number of jumps the most.
20946 if (isCMOVPseudo(MI)) {
20947 // See if we have a string of CMOVS with the same condition.
20948 while (NextMIIt != BB->end() &&
20949 isCMOVPseudo(NextMIIt) &&
20950 (NextMIIt->getOperand(3).getImm() == CC ||
20951 NextMIIt->getOperand(3).getImm() == OppCC)) {
20952 LastCMOV = &*NextMIIt;
20957 // This checks for case 2, but only do this if we didn't already find
20958 // case 1, as indicated by LastCMOV == MI.
20959 if (LastCMOV == MI &&
20960 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20961 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20962 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20963 CascadedCMOV = &*NextMIIt;
20966 MachineBasicBlock *jcc1MBB = nullptr;
20968 // If we have a cascaded CMOV, we lower it to two successive branches to
20969 // the same block. EFLAGS is used by both, so mark it as live in the second.
20970 if (CascadedCMOV) {
20971 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20972 F->insert(It, jcc1MBB);
20973 jcc1MBB->addLiveIn(X86::EFLAGS);
20976 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20977 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20978 F->insert(It, copy0MBB);
20979 F->insert(It, sinkMBB);
20981 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20982 // live into the sink and copy blocks.
20983 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20985 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20986 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20987 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20988 copy0MBB->addLiveIn(X86::EFLAGS);
20989 sinkMBB->addLiveIn(X86::EFLAGS);
20992 // Transfer the remainder of BB and its successor edges to sinkMBB.
20993 sinkMBB->splice(sinkMBB->begin(), BB,
20994 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20995 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20997 // Add the true and fallthrough blocks as its successors.
20998 if (CascadedCMOV) {
20999 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21000 BB->addSuccessor(jcc1MBB);
21002 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21003 // jump to the sinkMBB.
21004 jcc1MBB->addSuccessor(copy0MBB);
21005 jcc1MBB->addSuccessor(sinkMBB);
21007 BB->addSuccessor(copy0MBB);
21010 // The true block target of the first (or only) branch is always sinkMBB.
21011 BB->addSuccessor(sinkMBB);
21013 // Create the conditional branch instruction.
21014 unsigned Opc = X86::GetCondBranchFromCond(CC);
21015 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21017 if (CascadedCMOV) {
21018 unsigned Opc2 = X86::GetCondBranchFromCond(
21019 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21020 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21024 // %FalseValue = ...
21025 // # fallthrough to sinkMBB
21026 copy0MBB->addSuccessor(sinkMBB);
21029 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21031 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21032 MachineBasicBlock::iterator MIItEnd =
21033 std::next(MachineBasicBlock::iterator(LastCMOV));
21034 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21035 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21036 MachineInstrBuilder MIB;
21038 // As we are creating the PHIs, we have to be careful if there is more than
21039 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21040 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21041 // That also means that PHI construction must work forward from earlier to
21042 // later, and that the code must maintain a mapping from earlier PHI's
21043 // destination registers, and the registers that went into the PHI.
21045 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21046 unsigned DestReg = MIIt->getOperand(0).getReg();
21047 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21048 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21050 // If this CMOV we are generating is the opposite condition from
21051 // the jump we generated, then we have to swap the operands for the
21052 // PHI that is going to be generated.
21053 if (MIIt->getOperand(3).getImm() == OppCC)
21054 std::swap(Op1Reg, Op2Reg);
21056 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21057 Op1Reg = RegRewriteTable[Op1Reg].first;
21059 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21060 Op2Reg = RegRewriteTable[Op2Reg].second;
21062 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21063 TII->get(X86::PHI), DestReg)
21064 .addReg(Op1Reg).addMBB(copy0MBB)
21065 .addReg(Op2Reg).addMBB(thisMBB);
21067 // Add this PHI to the rewrite table.
21068 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21071 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21072 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21073 if (CascadedCMOV) {
21074 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21075 // Copy the PHI result to the register defined by the second CMOV.
21076 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21077 DL, TII->get(TargetOpcode::COPY),
21078 CascadedCMOV->getOperand(0).getReg())
21079 .addReg(MI->getOperand(0).getReg());
21080 CascadedCMOV->eraseFromParent();
21083 // Now remove the CMOV(s).
21084 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21085 (MIIt++)->eraseFromParent();
21090 MachineBasicBlock *
21091 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21092 MachineBasicBlock *BB) const {
21093 // Combine the following atomic floating-point modification pattern:
21094 // a.store(reg OP a.load(acquire), release)
21095 // Transform them into:
21096 // OPss (%gpr), %xmm
21097 // movss %xmm, (%gpr)
21098 // Or sd equivalent for 64-bit operations.
21100 switch (MI->getOpcode()) {
21101 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21102 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21103 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21105 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21106 DebugLoc DL = MI->getDebugLoc();
21107 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21108 MachineOperand MSrc = MI->getOperand(0);
21109 unsigned VSrc = MI->getOperand(5).getReg();
21110 const MachineOperand &Disp = MI->getOperand(3);
21111 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21112 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21113 if (hasDisp && MSrc.isReg())
21114 MSrc.setIsKill(false);
21115 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21116 .addOperand(/*Base=*/MSrc)
21117 .addImm(/*Scale=*/1)
21118 .addReg(/*Index=*/0)
21119 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21121 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21122 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21124 .addOperand(/*Base=*/MSrc)
21125 .addImm(/*Scale=*/1)
21126 .addReg(/*Index=*/0)
21127 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21128 .addReg(/*Segment=*/0);
21129 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21130 MI->eraseFromParent(); // The pseudo instruction is gone now.
21134 MachineBasicBlock *
21135 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21136 MachineBasicBlock *BB) const {
21137 MachineFunction *MF = BB->getParent();
21138 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21139 DebugLoc DL = MI->getDebugLoc();
21140 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21142 assert(MF->shouldSplitStack());
21144 const bool Is64Bit = Subtarget->is64Bit();
21145 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21147 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21148 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21151 // ... [Till the alloca]
21152 // If stacklet is not large enough, jump to mallocMBB
21155 // Allocate by subtracting from RSP
21156 // Jump to continueMBB
21159 // Allocate by call to runtime
21163 // [rest of original BB]
21166 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21167 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21168 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21170 MachineRegisterInfo &MRI = MF->getRegInfo();
21171 const TargetRegisterClass *AddrRegClass =
21172 getRegClassFor(getPointerTy(MF->getDataLayout()));
21174 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21175 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21176 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21177 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21178 sizeVReg = MI->getOperand(1).getReg(),
21179 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21181 MachineFunction::iterator MBBIter = BB;
21184 MF->insert(MBBIter, bumpMBB);
21185 MF->insert(MBBIter, mallocMBB);
21186 MF->insert(MBBIter, continueMBB);
21188 continueMBB->splice(continueMBB->begin(), BB,
21189 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21190 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21192 // Add code to the main basic block to check if the stack limit has been hit,
21193 // and if so, jump to mallocMBB otherwise to bumpMBB.
21194 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21195 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21196 .addReg(tmpSPVReg).addReg(sizeVReg);
21197 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21198 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21199 .addReg(SPLimitVReg);
21200 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21202 // bumpMBB simply decreases the stack pointer, since we know the current
21203 // stacklet has enough space.
21204 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21205 .addReg(SPLimitVReg);
21206 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21207 .addReg(SPLimitVReg);
21208 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21210 // Calls into a routine in libgcc to allocate more space from the heap.
21211 const uint32_t *RegMask =
21212 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21214 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21216 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21217 .addExternalSymbol("__morestack_allocate_stack_space")
21218 .addRegMask(RegMask)
21219 .addReg(X86::RDI, RegState::Implicit)
21220 .addReg(X86::RAX, RegState::ImplicitDefine);
21221 } else if (Is64Bit) {
21222 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21224 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21225 .addExternalSymbol("__morestack_allocate_stack_space")
21226 .addRegMask(RegMask)
21227 .addReg(X86::EDI, RegState::Implicit)
21228 .addReg(X86::EAX, RegState::ImplicitDefine);
21230 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21232 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21233 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21234 .addExternalSymbol("__morestack_allocate_stack_space")
21235 .addRegMask(RegMask)
21236 .addReg(X86::EAX, RegState::ImplicitDefine);
21240 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21243 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21244 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21245 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21247 // Set up the CFG correctly.
21248 BB->addSuccessor(bumpMBB);
21249 BB->addSuccessor(mallocMBB);
21250 mallocMBB->addSuccessor(continueMBB);
21251 bumpMBB->addSuccessor(continueMBB);
21253 // Take care of the PHI nodes.
21254 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21255 MI->getOperand(0).getReg())
21256 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21257 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21259 // Delete the original pseudo instruction.
21260 MI->eraseFromParent();
21263 return continueMBB;
21266 MachineBasicBlock *
21267 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21268 MachineBasicBlock *BB) const {
21269 DebugLoc DL = MI->getDebugLoc();
21271 assert(!Subtarget->isTargetMachO());
21273 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21276 MI->eraseFromParent(); // The pseudo instruction is gone now.
21280 MachineBasicBlock *
21281 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21282 MachineBasicBlock *BB) const {
21283 // This is pretty easy. We're taking the value that we received from
21284 // our load from the relocation, sticking it in either RDI (x86-64)
21285 // or EAX and doing an indirect call. The return value will then
21286 // be in the normal return register.
21287 MachineFunction *F = BB->getParent();
21288 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21289 DebugLoc DL = MI->getDebugLoc();
21291 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21292 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21294 // Get a register mask for the lowered call.
21295 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21296 // proper register mask.
21297 const uint32_t *RegMask =
21298 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21299 if (Subtarget->is64Bit()) {
21300 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21301 TII->get(X86::MOV64rm), X86::RDI)
21303 .addImm(0).addReg(0)
21304 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21305 MI->getOperand(3).getTargetFlags())
21307 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21308 addDirectMem(MIB, X86::RDI);
21309 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21310 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21311 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21312 TII->get(X86::MOV32rm), X86::EAX)
21314 .addImm(0).addReg(0)
21315 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21316 MI->getOperand(3).getTargetFlags())
21318 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21319 addDirectMem(MIB, X86::EAX);
21320 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21322 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21323 TII->get(X86::MOV32rm), X86::EAX)
21324 .addReg(TII->getGlobalBaseReg(F))
21325 .addImm(0).addReg(0)
21326 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21327 MI->getOperand(3).getTargetFlags())
21329 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21330 addDirectMem(MIB, X86::EAX);
21331 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21334 MI->eraseFromParent(); // The pseudo instruction is gone now.
21338 MachineBasicBlock *
21339 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21340 MachineBasicBlock *MBB) const {
21341 DebugLoc DL = MI->getDebugLoc();
21342 MachineFunction *MF = MBB->getParent();
21343 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21344 MachineRegisterInfo &MRI = MF->getRegInfo();
21346 const BasicBlock *BB = MBB->getBasicBlock();
21347 MachineFunction::iterator I = MBB;
21350 // Memory Reference
21351 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21352 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21355 unsigned MemOpndSlot = 0;
21357 unsigned CurOp = 0;
21359 DstReg = MI->getOperand(CurOp++).getReg();
21360 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21361 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21362 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21363 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21365 MemOpndSlot = CurOp;
21367 MVT PVT = getPointerTy(MF->getDataLayout());
21368 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21369 "Invalid Pointer Size!");
21371 // For v = setjmp(buf), we generate
21374 // buf[LabelOffset] = restoreMBB
21375 // SjLjSetup restoreMBB
21381 // v = phi(main, restore)
21384 // if base pointer being used, load it from frame
21387 MachineBasicBlock *thisMBB = MBB;
21388 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21389 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21390 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21391 MF->insert(I, mainMBB);
21392 MF->insert(I, sinkMBB);
21393 MF->push_back(restoreMBB);
21395 MachineInstrBuilder MIB;
21397 // Transfer the remainder of BB and its successor edges to sinkMBB.
21398 sinkMBB->splice(sinkMBB->begin(), MBB,
21399 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21400 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21403 unsigned PtrStoreOpc = 0;
21404 unsigned LabelReg = 0;
21405 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21406 Reloc::Model RM = MF->getTarget().getRelocationModel();
21407 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21408 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21410 // Prepare IP either in reg or imm.
21411 if (!UseImmLabel) {
21412 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21413 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21414 LabelReg = MRI.createVirtualRegister(PtrRC);
21415 if (Subtarget->is64Bit()) {
21416 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21420 .addMBB(restoreMBB)
21423 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21424 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21425 .addReg(XII->getGlobalBaseReg(MF))
21428 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21432 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21434 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21435 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21436 if (i == X86::AddrDisp)
21437 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21439 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21442 MIB.addReg(LabelReg);
21444 MIB.addMBB(restoreMBB);
21445 MIB.setMemRefs(MMOBegin, MMOEnd);
21447 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21448 .addMBB(restoreMBB);
21450 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21451 MIB.addRegMask(RegInfo->getNoPreservedMask());
21452 thisMBB->addSuccessor(mainMBB);
21453 thisMBB->addSuccessor(restoreMBB);
21457 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21458 mainMBB->addSuccessor(sinkMBB);
21461 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21462 TII->get(X86::PHI), DstReg)
21463 .addReg(mainDstReg).addMBB(mainMBB)
21464 .addReg(restoreDstReg).addMBB(restoreMBB);
21467 if (RegInfo->hasBasePointer(*MF)) {
21468 const bool Uses64BitFramePtr =
21469 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21470 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21471 X86FI->setRestoreBasePointer(MF);
21472 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21473 unsigned BasePtr = RegInfo->getBaseRegister();
21474 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21475 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21476 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21477 .setMIFlag(MachineInstr::FrameSetup);
21479 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21480 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21481 restoreMBB->addSuccessor(sinkMBB);
21483 MI->eraseFromParent();
21487 MachineBasicBlock *
21488 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21489 MachineBasicBlock *MBB) const {
21490 DebugLoc DL = MI->getDebugLoc();
21491 MachineFunction *MF = MBB->getParent();
21492 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21493 MachineRegisterInfo &MRI = MF->getRegInfo();
21495 // Memory Reference
21496 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21497 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21499 MVT PVT = getPointerTy(MF->getDataLayout());
21500 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21501 "Invalid Pointer Size!");
21503 const TargetRegisterClass *RC =
21504 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21505 unsigned Tmp = MRI.createVirtualRegister(RC);
21506 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21507 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21508 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21509 unsigned SP = RegInfo->getStackRegister();
21511 MachineInstrBuilder MIB;
21513 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21514 const int64_t SPOffset = 2 * PVT.getStoreSize();
21516 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21517 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21520 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21521 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21522 MIB.addOperand(MI->getOperand(i));
21523 MIB.setMemRefs(MMOBegin, MMOEnd);
21525 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21526 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21527 if (i == X86::AddrDisp)
21528 MIB.addDisp(MI->getOperand(i), LabelOffset);
21530 MIB.addOperand(MI->getOperand(i));
21532 MIB.setMemRefs(MMOBegin, MMOEnd);
21534 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21535 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21536 if (i == X86::AddrDisp)
21537 MIB.addDisp(MI->getOperand(i), SPOffset);
21539 MIB.addOperand(MI->getOperand(i));
21541 MIB.setMemRefs(MMOBegin, MMOEnd);
21543 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21545 MI->eraseFromParent();
21549 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21550 // accumulator loops. Writing back to the accumulator allows the coalescer
21551 // to remove extra copies in the loop.
21552 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21553 MachineBasicBlock *
21554 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21555 MachineBasicBlock *MBB) const {
21556 MachineOperand &AddendOp = MI->getOperand(3);
21558 // Bail out early if the addend isn't a register - we can't switch these.
21559 if (!AddendOp.isReg())
21562 MachineFunction &MF = *MBB->getParent();
21563 MachineRegisterInfo &MRI = MF.getRegInfo();
21565 // Check whether the addend is defined by a PHI:
21566 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21567 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21568 if (!AddendDef.isPHI())
21571 // Look for the following pattern:
21573 // %addend = phi [%entry, 0], [%loop, %result]
21575 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21579 // %addend = phi [%entry, 0], [%loop, %result]
21581 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21583 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21584 assert(AddendDef.getOperand(i).isReg());
21585 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21586 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21587 if (&PHISrcInst == MI) {
21588 // Found a matching instruction.
21589 unsigned NewFMAOpc = 0;
21590 switch (MI->getOpcode()) {
21591 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21592 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21593 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21594 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21595 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21596 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21597 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21598 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21599 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21600 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21601 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21602 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21603 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21604 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21605 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21606 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21607 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21608 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21609 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21610 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21612 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21613 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21614 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21615 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21616 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21617 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21618 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21619 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21620 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21621 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21622 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21623 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21624 default: llvm_unreachable("Unrecognized FMA variant.");
21627 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21628 MachineInstrBuilder MIB =
21629 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21630 .addOperand(MI->getOperand(0))
21631 .addOperand(MI->getOperand(3))
21632 .addOperand(MI->getOperand(2))
21633 .addOperand(MI->getOperand(1));
21634 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21635 MI->eraseFromParent();
21642 MachineBasicBlock *
21643 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21644 MachineBasicBlock *BB) const {
21645 switch (MI->getOpcode()) {
21646 default: llvm_unreachable("Unexpected instr type to insert");
21647 case X86::TAILJMPd64:
21648 case X86::TAILJMPr64:
21649 case X86::TAILJMPm64:
21650 case X86::TAILJMPd64_REX:
21651 case X86::TAILJMPr64_REX:
21652 case X86::TAILJMPm64_REX:
21653 llvm_unreachable("TAILJMP64 would not be touched here.");
21654 case X86::TCRETURNdi64:
21655 case X86::TCRETURNri64:
21656 case X86::TCRETURNmi64:
21658 case X86::WIN_ALLOCA:
21659 return EmitLoweredWinAlloca(MI, BB);
21660 case X86::SEG_ALLOCA_32:
21661 case X86::SEG_ALLOCA_64:
21662 return EmitLoweredSegAlloca(MI, BB);
21663 case X86::TLSCall_32:
21664 case X86::TLSCall_64:
21665 return EmitLoweredTLSCall(MI, BB);
21666 case X86::CMOV_FR32:
21667 case X86::CMOV_FR64:
21668 case X86::CMOV_GR8:
21669 case X86::CMOV_GR16:
21670 case X86::CMOV_GR32:
21671 case X86::CMOV_RFP32:
21672 case X86::CMOV_RFP64:
21673 case X86::CMOV_RFP80:
21674 case X86::CMOV_V2F64:
21675 case X86::CMOV_V2I64:
21676 case X86::CMOV_V4F32:
21677 case X86::CMOV_V4F64:
21678 case X86::CMOV_V4I64:
21679 case X86::CMOV_V16F32:
21680 case X86::CMOV_V8F32:
21681 case X86::CMOV_V8F64:
21682 case X86::CMOV_V8I64:
21683 case X86::CMOV_V8I1:
21684 case X86::CMOV_V16I1:
21685 case X86::CMOV_V32I1:
21686 case X86::CMOV_V64I1:
21687 return EmitLoweredSelect(MI, BB);
21689 case X86::RELEASE_FADD32mr:
21690 case X86::RELEASE_FADD64mr:
21691 return EmitLoweredAtomicFP(MI, BB);
21693 case X86::FP32_TO_INT16_IN_MEM:
21694 case X86::FP32_TO_INT32_IN_MEM:
21695 case X86::FP32_TO_INT64_IN_MEM:
21696 case X86::FP64_TO_INT16_IN_MEM:
21697 case X86::FP64_TO_INT32_IN_MEM:
21698 case X86::FP64_TO_INT64_IN_MEM:
21699 case X86::FP80_TO_INT16_IN_MEM:
21700 case X86::FP80_TO_INT32_IN_MEM:
21701 case X86::FP80_TO_INT64_IN_MEM: {
21702 MachineFunction *F = BB->getParent();
21703 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21704 DebugLoc DL = MI->getDebugLoc();
21706 // Change the floating point control register to use "round towards zero"
21707 // mode when truncating to an integer value.
21708 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21709 addFrameReference(BuildMI(*BB, MI, DL,
21710 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21712 // Load the old value of the high byte of the control word...
21714 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21715 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21718 // Set the high part to be round to zero...
21719 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21722 // Reload the modified control word now...
21723 addFrameReference(BuildMI(*BB, MI, DL,
21724 TII->get(X86::FLDCW16m)), CWFrameIdx);
21726 // Restore the memory image of control word to original value
21727 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21730 // Get the X86 opcode to use.
21732 switch (MI->getOpcode()) {
21733 default: llvm_unreachable("illegal opcode!");
21734 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21735 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21736 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21737 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21738 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21739 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21740 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21741 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21742 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21746 MachineOperand &Op = MI->getOperand(0);
21748 AM.BaseType = X86AddressMode::RegBase;
21749 AM.Base.Reg = Op.getReg();
21751 AM.BaseType = X86AddressMode::FrameIndexBase;
21752 AM.Base.FrameIndex = Op.getIndex();
21754 Op = MI->getOperand(1);
21756 AM.Scale = Op.getImm();
21757 Op = MI->getOperand(2);
21759 AM.IndexReg = Op.getImm();
21760 Op = MI->getOperand(3);
21761 if (Op.isGlobal()) {
21762 AM.GV = Op.getGlobal();
21764 AM.Disp = Op.getImm();
21766 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21767 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21769 // Reload the original control word now.
21770 addFrameReference(BuildMI(*BB, MI, DL,
21771 TII->get(X86::FLDCW16m)), CWFrameIdx);
21773 MI->eraseFromParent(); // The pseudo instruction is gone now.
21776 // String/text processing lowering.
21777 case X86::PCMPISTRM128REG:
21778 case X86::VPCMPISTRM128REG:
21779 case X86::PCMPISTRM128MEM:
21780 case X86::VPCMPISTRM128MEM:
21781 case X86::PCMPESTRM128REG:
21782 case X86::VPCMPESTRM128REG:
21783 case X86::PCMPESTRM128MEM:
21784 case X86::VPCMPESTRM128MEM:
21785 assert(Subtarget->hasSSE42() &&
21786 "Target must have SSE4.2 or AVX features enabled");
21787 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21789 // String/text processing lowering.
21790 case X86::PCMPISTRIREG:
21791 case X86::VPCMPISTRIREG:
21792 case X86::PCMPISTRIMEM:
21793 case X86::VPCMPISTRIMEM:
21794 case X86::PCMPESTRIREG:
21795 case X86::VPCMPESTRIREG:
21796 case X86::PCMPESTRIMEM:
21797 case X86::VPCMPESTRIMEM:
21798 assert(Subtarget->hasSSE42() &&
21799 "Target must have SSE4.2 or AVX features enabled");
21800 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21802 // Thread synchronization.
21804 return EmitMonitor(MI, BB, Subtarget);
21808 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21810 case X86::VASTART_SAVE_XMM_REGS:
21811 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21813 case X86::VAARG_64:
21814 return EmitVAARG64WithCustomInserter(MI, BB);
21816 case X86::EH_SjLj_SetJmp32:
21817 case X86::EH_SjLj_SetJmp64:
21818 return emitEHSjLjSetJmp(MI, BB);
21820 case X86::EH_SjLj_LongJmp32:
21821 case X86::EH_SjLj_LongJmp64:
21822 return emitEHSjLjLongJmp(MI, BB);
21824 case TargetOpcode::STATEPOINT:
21825 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21826 // this point in the process. We diverge later.
21827 return emitPatchPoint(MI, BB);
21829 case TargetOpcode::STACKMAP:
21830 case TargetOpcode::PATCHPOINT:
21831 return emitPatchPoint(MI, BB);
21833 case X86::VFMADDPDr213r:
21834 case X86::VFMADDPSr213r:
21835 case X86::VFMADDSDr213r:
21836 case X86::VFMADDSSr213r:
21837 case X86::VFMSUBPDr213r:
21838 case X86::VFMSUBPSr213r:
21839 case X86::VFMSUBSDr213r:
21840 case X86::VFMSUBSSr213r:
21841 case X86::VFNMADDPDr213r:
21842 case X86::VFNMADDPSr213r:
21843 case X86::VFNMADDSDr213r:
21844 case X86::VFNMADDSSr213r:
21845 case X86::VFNMSUBPDr213r:
21846 case X86::VFNMSUBPSr213r:
21847 case X86::VFNMSUBSDr213r:
21848 case X86::VFNMSUBSSr213r:
21849 case X86::VFMADDSUBPDr213r:
21850 case X86::VFMADDSUBPSr213r:
21851 case X86::VFMSUBADDPDr213r:
21852 case X86::VFMSUBADDPSr213r:
21853 case X86::VFMADDPDr213rY:
21854 case X86::VFMADDPSr213rY:
21855 case X86::VFMSUBPDr213rY:
21856 case X86::VFMSUBPSr213rY:
21857 case X86::VFNMADDPDr213rY:
21858 case X86::VFNMADDPSr213rY:
21859 case X86::VFNMSUBPDr213rY:
21860 case X86::VFNMSUBPSr213rY:
21861 case X86::VFMADDSUBPDr213rY:
21862 case X86::VFMADDSUBPSr213rY:
21863 case X86::VFMSUBADDPDr213rY:
21864 case X86::VFMSUBADDPSr213rY:
21865 return emitFMA3Instr(MI, BB);
21869 //===----------------------------------------------------------------------===//
21870 // X86 Optimization Hooks
21871 //===----------------------------------------------------------------------===//
21873 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21876 const SelectionDAG &DAG,
21877 unsigned Depth) const {
21878 unsigned BitWidth = KnownZero.getBitWidth();
21879 unsigned Opc = Op.getOpcode();
21880 assert((Opc >= ISD::BUILTIN_OP_END ||
21881 Opc == ISD::INTRINSIC_WO_CHAIN ||
21882 Opc == ISD::INTRINSIC_W_CHAIN ||
21883 Opc == ISD::INTRINSIC_VOID) &&
21884 "Should use MaskedValueIsZero if you don't know whether Op"
21885 " is a target node!");
21887 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21901 // These nodes' second result is a boolean.
21902 if (Op.getResNo() == 0)
21905 case X86ISD::SETCC:
21906 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21908 case ISD::INTRINSIC_WO_CHAIN: {
21909 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21910 unsigned NumLoBits = 0;
21913 case Intrinsic::x86_sse_movmsk_ps:
21914 case Intrinsic::x86_avx_movmsk_ps_256:
21915 case Intrinsic::x86_sse2_movmsk_pd:
21916 case Intrinsic::x86_avx_movmsk_pd_256:
21917 case Intrinsic::x86_mmx_pmovmskb:
21918 case Intrinsic::x86_sse2_pmovmskb_128:
21919 case Intrinsic::x86_avx2_pmovmskb: {
21920 // High bits of movmskp{s|d}, pmovmskb are known zero.
21922 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21923 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21924 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21925 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21926 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21927 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21928 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21929 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21931 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21940 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21942 const SelectionDAG &,
21943 unsigned Depth) const {
21944 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21945 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21946 return Op.getValueType().getScalarType().getSizeInBits();
21952 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21953 /// node is a GlobalAddress + offset.
21954 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21955 const GlobalValue* &GA,
21956 int64_t &Offset) const {
21957 if (N->getOpcode() == X86ISD::Wrapper) {
21958 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21959 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21960 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21964 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21967 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21968 /// same as extracting the high 128-bit part of 256-bit vector and then
21969 /// inserting the result into the low part of a new 256-bit vector
21970 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21971 EVT VT = SVOp->getValueType(0);
21972 unsigned NumElems = VT.getVectorNumElements();
21974 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21975 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21976 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21977 SVOp->getMaskElt(j) >= 0)
21983 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21984 /// same as extracting the low 128-bit part of 256-bit vector and then
21985 /// inserting the result into the high part of a new 256-bit vector
21986 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21987 EVT VT = SVOp->getValueType(0);
21988 unsigned NumElems = VT.getVectorNumElements();
21990 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21991 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21992 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21993 SVOp->getMaskElt(j) >= 0)
21999 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22000 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22001 TargetLowering::DAGCombinerInfo &DCI,
22002 const X86Subtarget* Subtarget) {
22004 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22005 SDValue V1 = SVOp->getOperand(0);
22006 SDValue V2 = SVOp->getOperand(1);
22007 EVT VT = SVOp->getValueType(0);
22008 unsigned NumElems = VT.getVectorNumElements();
22010 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22011 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22015 // V UNDEF BUILD_VECTOR UNDEF
22017 // CONCAT_VECTOR CONCAT_VECTOR
22020 // RESULT: V + zero extended
22022 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22023 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22024 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22027 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22030 // To match the shuffle mask, the first half of the mask should
22031 // be exactly the first vector, and all the rest a splat with the
22032 // first element of the second one.
22033 for (unsigned i = 0; i != NumElems/2; ++i)
22034 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22035 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22038 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22039 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22040 if (Ld->hasNUsesOfValue(1, 0)) {
22041 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22042 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22044 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22046 Ld->getPointerInfo(),
22047 Ld->getAlignment(),
22048 false/*isVolatile*/, true/*ReadMem*/,
22049 false/*WriteMem*/);
22051 // Make sure the newly-created LOAD is in the same position as Ld in
22052 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22053 // and update uses of Ld's output chain to use the TokenFactor.
22054 if (Ld->hasAnyUseOfValue(1)) {
22055 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22056 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22057 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22058 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22059 SDValue(ResNode.getNode(), 1));
22062 return DAG.getBitcast(VT, ResNode);
22066 // Emit a zeroed vector and insert the desired subvector on its
22068 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22069 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22070 return DCI.CombineTo(N, InsV);
22073 //===--------------------------------------------------------------------===//
22074 // Combine some shuffles into subvector extracts and inserts:
22077 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22078 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22079 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22080 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22081 return DCI.CombineTo(N, InsV);
22084 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22085 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22086 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22087 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22088 return DCI.CombineTo(N, InsV);
22094 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22097 /// This is the leaf of the recursive combinine below. When we have found some
22098 /// chain of single-use x86 shuffle instructions and accumulated the combined
22099 /// shuffle mask represented by them, this will try to pattern match that mask
22100 /// into either a single instruction if there is a special purpose instruction
22101 /// for this operation, or into a PSHUFB instruction which is a fully general
22102 /// instruction but should only be used to replace chains over a certain depth.
22103 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22104 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22105 TargetLowering::DAGCombinerInfo &DCI,
22106 const X86Subtarget *Subtarget) {
22107 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22109 // Find the operand that enters the chain. Note that multiple uses are OK
22110 // here, we're not going to remove the operand we find.
22111 SDValue Input = Op.getOperand(0);
22112 while (Input.getOpcode() == ISD::BITCAST)
22113 Input = Input.getOperand(0);
22115 MVT VT = Input.getSimpleValueType();
22116 MVT RootVT = Root.getSimpleValueType();
22119 if (Mask.size() == 1) {
22120 int Index = Mask[0];
22121 assert((Index >= 0 || Index == SM_SentinelUndef ||
22122 Index == SM_SentinelZero) &&
22123 "Invalid shuffle index found!");
22125 // We may end up with an accumulated mask of size 1 as a result of
22126 // widening of shuffle operands (see function canWidenShuffleElements).
22127 // If the only shuffle index is equal to SM_SentinelZero then propagate
22128 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22129 // mask, and therefore the entire chain of shuffles can be folded away.
22130 if (Index == SM_SentinelZero)
22131 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22133 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22138 // Use the float domain if the operand type is a floating point type.
22139 bool FloatDomain = VT.isFloatingPoint();
22141 // For floating point shuffles, we don't have free copies in the shuffle
22142 // instructions or the ability to load as part of the instruction, so
22143 // canonicalize their shuffles to UNPCK or MOV variants.
22145 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22146 // vectors because it can have a load folded into it that UNPCK cannot. This
22147 // doesn't preclude something switching to the shorter encoding post-RA.
22149 // FIXME: Should teach these routines about AVX vector widths.
22150 if (FloatDomain && VT.getSizeInBits() == 128) {
22151 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22152 bool Lo = Mask.equals({0, 0});
22155 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22156 // is no slower than UNPCKLPD but has the option to fold the input operand
22157 // into even an unaligned memory load.
22158 if (Lo && Subtarget->hasSSE3()) {
22159 Shuffle = X86ISD::MOVDDUP;
22160 ShuffleVT = MVT::v2f64;
22162 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22163 // than the UNPCK variants.
22164 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22165 ShuffleVT = MVT::v4f32;
22167 if (Depth == 1 && Root->getOpcode() == Shuffle)
22168 return false; // Nothing to do!
22169 Op = DAG.getBitcast(ShuffleVT, Input);
22170 DCI.AddToWorklist(Op.getNode());
22171 if (Shuffle == X86ISD::MOVDDUP)
22172 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22174 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22175 DCI.AddToWorklist(Op.getNode());
22176 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22180 if (Subtarget->hasSSE3() &&
22181 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22182 bool Lo = Mask.equals({0, 0, 2, 2});
22183 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22184 MVT ShuffleVT = MVT::v4f32;
22185 if (Depth == 1 && Root->getOpcode() == Shuffle)
22186 return false; // Nothing to do!
22187 Op = DAG.getBitcast(ShuffleVT, Input);
22188 DCI.AddToWorklist(Op.getNode());
22189 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22190 DCI.AddToWorklist(Op.getNode());
22191 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22195 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22196 bool Lo = Mask.equals({0, 0, 1, 1});
22197 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22198 MVT ShuffleVT = MVT::v4f32;
22199 if (Depth == 1 && Root->getOpcode() == Shuffle)
22200 return false; // Nothing to do!
22201 Op = DAG.getBitcast(ShuffleVT, Input);
22202 DCI.AddToWorklist(Op.getNode());
22203 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22204 DCI.AddToWorklist(Op.getNode());
22205 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22211 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22212 // variants as none of these have single-instruction variants that are
22213 // superior to the UNPCK formulation.
22214 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22215 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22216 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22217 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22219 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22220 bool Lo = Mask[0] == 0;
22221 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22222 if (Depth == 1 && Root->getOpcode() == Shuffle)
22223 return false; // Nothing to do!
22225 switch (Mask.size()) {
22227 ShuffleVT = MVT::v8i16;
22230 ShuffleVT = MVT::v16i8;
22233 llvm_unreachable("Impossible mask size!");
22235 Op = DAG.getBitcast(ShuffleVT, Input);
22236 DCI.AddToWorklist(Op.getNode());
22237 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22238 DCI.AddToWorklist(Op.getNode());
22239 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22244 // Don't try to re-form single instruction chains under any circumstances now
22245 // that we've done encoding canonicalization for them.
22249 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22250 // can replace them with a single PSHUFB instruction profitably. Intel's
22251 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22252 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22253 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22254 SmallVector<SDValue, 16> PSHUFBMask;
22255 int NumBytes = VT.getSizeInBits() / 8;
22256 int Ratio = NumBytes / Mask.size();
22257 for (int i = 0; i < NumBytes; ++i) {
22258 if (Mask[i / Ratio] == SM_SentinelUndef) {
22259 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22262 int M = Mask[i / Ratio] != SM_SentinelZero
22263 ? Ratio * Mask[i / Ratio] + i % Ratio
22265 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22267 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22268 Op = DAG.getBitcast(ByteVT, Input);
22269 DCI.AddToWorklist(Op.getNode());
22270 SDValue PSHUFBMaskOp =
22271 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22272 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22273 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22274 DCI.AddToWorklist(Op.getNode());
22275 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22280 // Failed to find any combines.
22284 /// \brief Fully generic combining of x86 shuffle instructions.
22286 /// This should be the last combine run over the x86 shuffle instructions. Once
22287 /// they have been fully optimized, this will recursively consider all chains
22288 /// of single-use shuffle instructions, build a generic model of the cumulative
22289 /// shuffle operation, and check for simpler instructions which implement this
22290 /// operation. We use this primarily for two purposes:
22292 /// 1) Collapse generic shuffles to specialized single instructions when
22293 /// equivalent. In most cases, this is just an encoding size win, but
22294 /// sometimes we will collapse multiple generic shuffles into a single
22295 /// special-purpose shuffle.
22296 /// 2) Look for sequences of shuffle instructions with 3 or more total
22297 /// instructions, and replace them with the slightly more expensive SSSE3
22298 /// PSHUFB instruction if available. We do this as the last combining step
22299 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22300 /// a suitable short sequence of other instructions. The PHUFB will either
22301 /// use a register or have to read from memory and so is slightly (but only
22302 /// slightly) more expensive than the other shuffle instructions.
22304 /// Because this is inherently a quadratic operation (for each shuffle in
22305 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22306 /// This should never be an issue in practice as the shuffle lowering doesn't
22307 /// produce sequences of more than 8 instructions.
22309 /// FIXME: We will currently miss some cases where the redundant shuffling
22310 /// would simplify under the threshold for PSHUFB formation because of
22311 /// combine-ordering. To fix this, we should do the redundant instruction
22312 /// combining in this recursive walk.
22313 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22314 ArrayRef<int> RootMask,
22315 int Depth, bool HasPSHUFB,
22317 TargetLowering::DAGCombinerInfo &DCI,
22318 const X86Subtarget *Subtarget) {
22319 // Bound the depth of our recursive combine because this is ultimately
22320 // quadratic in nature.
22324 // Directly rip through bitcasts to find the underlying operand.
22325 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22326 Op = Op.getOperand(0);
22328 MVT VT = Op.getSimpleValueType();
22329 if (!VT.isVector())
22330 return false; // Bail if we hit a non-vector.
22332 assert(Root.getSimpleValueType().isVector() &&
22333 "Shuffles operate on vector types!");
22334 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22335 "Can only combine shuffles of the same vector register size.");
22337 if (!isTargetShuffle(Op.getOpcode()))
22339 SmallVector<int, 16> OpMask;
22341 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22342 // We only can combine unary shuffles which we can decode the mask for.
22343 if (!HaveMask || !IsUnary)
22346 assert(VT.getVectorNumElements() == OpMask.size() &&
22347 "Different mask size from vector size!");
22348 assert(((RootMask.size() > OpMask.size() &&
22349 RootMask.size() % OpMask.size() == 0) ||
22350 (OpMask.size() > RootMask.size() &&
22351 OpMask.size() % RootMask.size() == 0) ||
22352 OpMask.size() == RootMask.size()) &&
22353 "The smaller number of elements must divide the larger.");
22354 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22355 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22356 assert(((RootRatio == 1 && OpRatio == 1) ||
22357 (RootRatio == 1) != (OpRatio == 1)) &&
22358 "Must not have a ratio for both incoming and op masks!");
22360 SmallVector<int, 16> Mask;
22361 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22363 // Merge this shuffle operation's mask into our accumulated mask. Note that
22364 // this shuffle's mask will be the first applied to the input, followed by the
22365 // root mask to get us all the way to the root value arrangement. The reason
22366 // for this order is that we are recursing up the operation chain.
22367 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22368 int RootIdx = i / RootRatio;
22369 if (RootMask[RootIdx] < 0) {
22370 // This is a zero or undef lane, we're done.
22371 Mask.push_back(RootMask[RootIdx]);
22375 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22376 int OpIdx = RootMaskedIdx / OpRatio;
22377 if (OpMask[OpIdx] < 0) {
22378 // The incoming lanes are zero or undef, it doesn't matter which ones we
22380 Mask.push_back(OpMask[OpIdx]);
22384 // Ok, we have non-zero lanes, map them through.
22385 Mask.push_back(OpMask[OpIdx] * OpRatio +
22386 RootMaskedIdx % OpRatio);
22389 // See if we can recurse into the operand to combine more things.
22390 switch (Op.getOpcode()) {
22391 case X86ISD::PSHUFB:
22393 case X86ISD::PSHUFD:
22394 case X86ISD::PSHUFHW:
22395 case X86ISD::PSHUFLW:
22396 if (Op.getOperand(0).hasOneUse() &&
22397 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22398 HasPSHUFB, DAG, DCI, Subtarget))
22402 case X86ISD::UNPCKL:
22403 case X86ISD::UNPCKH:
22404 assert(Op.getOperand(0) == Op.getOperand(1) &&
22405 "We only combine unary shuffles!");
22406 // We can't check for single use, we have to check that this shuffle is the
22408 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22409 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22410 HasPSHUFB, DAG, DCI, Subtarget))
22415 // Minor canonicalization of the accumulated shuffle mask to make it easier
22416 // to match below. All this does is detect masks with squential pairs of
22417 // elements, and shrink them to the half-width mask. It does this in a loop
22418 // so it will reduce the size of the mask to the minimal width mask which
22419 // performs an equivalent shuffle.
22420 SmallVector<int, 16> WidenedMask;
22421 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22422 Mask = std::move(WidenedMask);
22423 WidenedMask.clear();
22426 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22430 /// \brief Get the PSHUF-style mask from PSHUF node.
22432 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22433 /// PSHUF-style masks that can be reused with such instructions.
22434 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22435 MVT VT = N.getSimpleValueType();
22436 SmallVector<int, 4> Mask;
22438 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22442 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22443 // matter. Check that the upper masks are repeats and remove them.
22444 if (VT.getSizeInBits() > 128) {
22445 int LaneElts = 128 / VT.getScalarSizeInBits();
22447 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22448 for (int j = 0; j < LaneElts; ++j)
22449 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22450 "Mask doesn't repeat in high 128-bit lanes!");
22452 Mask.resize(LaneElts);
22455 switch (N.getOpcode()) {
22456 case X86ISD::PSHUFD:
22458 case X86ISD::PSHUFLW:
22461 case X86ISD::PSHUFHW:
22462 Mask.erase(Mask.begin(), Mask.begin() + 4);
22463 for (int &M : Mask)
22467 llvm_unreachable("No valid shuffle instruction found!");
22471 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22473 /// We walk up the chain and look for a combinable shuffle, skipping over
22474 /// shuffles that we could hoist this shuffle's transformation past without
22475 /// altering anything.
22477 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22479 TargetLowering::DAGCombinerInfo &DCI) {
22480 assert(N.getOpcode() == X86ISD::PSHUFD &&
22481 "Called with something other than an x86 128-bit half shuffle!");
22484 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22485 // of the shuffles in the chain so that we can form a fresh chain to replace
22487 SmallVector<SDValue, 8> Chain;
22488 SDValue V = N.getOperand(0);
22489 for (; V.hasOneUse(); V = V.getOperand(0)) {
22490 switch (V.getOpcode()) {
22492 return SDValue(); // Nothing combined!
22495 // Skip bitcasts as we always know the type for the target specific
22499 case X86ISD::PSHUFD:
22500 // Found another dword shuffle.
22503 case X86ISD::PSHUFLW:
22504 // Check that the low words (being shuffled) are the identity in the
22505 // dword shuffle, and the high words are self-contained.
22506 if (Mask[0] != 0 || Mask[1] != 1 ||
22507 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22510 Chain.push_back(V);
22513 case X86ISD::PSHUFHW:
22514 // Check that the high words (being shuffled) are the identity in the
22515 // dword shuffle, and the low words are self-contained.
22516 if (Mask[2] != 2 || Mask[3] != 3 ||
22517 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22520 Chain.push_back(V);
22523 case X86ISD::UNPCKL:
22524 case X86ISD::UNPCKH:
22525 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22526 // shuffle into a preceding word shuffle.
22527 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22528 V.getSimpleValueType().getScalarType() != MVT::i16)
22531 // Search for a half-shuffle which we can combine with.
22532 unsigned CombineOp =
22533 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22534 if (V.getOperand(0) != V.getOperand(1) ||
22535 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22537 Chain.push_back(V);
22538 V = V.getOperand(0);
22540 switch (V.getOpcode()) {
22542 return SDValue(); // Nothing to combine.
22544 case X86ISD::PSHUFLW:
22545 case X86ISD::PSHUFHW:
22546 if (V.getOpcode() == CombineOp)
22549 Chain.push_back(V);
22553 V = V.getOperand(0);
22557 } while (V.hasOneUse());
22560 // Break out of the loop if we break out of the switch.
22564 if (!V.hasOneUse())
22565 // We fell out of the loop without finding a viable combining instruction.
22568 // Merge this node's mask and our incoming mask.
22569 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22570 for (int &M : Mask)
22572 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22573 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22575 // Rebuild the chain around this new shuffle.
22576 while (!Chain.empty()) {
22577 SDValue W = Chain.pop_back_val();
22579 if (V.getValueType() != W.getOperand(0).getValueType())
22580 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22582 switch (W.getOpcode()) {
22584 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22586 case X86ISD::UNPCKL:
22587 case X86ISD::UNPCKH:
22588 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22591 case X86ISD::PSHUFD:
22592 case X86ISD::PSHUFLW:
22593 case X86ISD::PSHUFHW:
22594 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22598 if (V.getValueType() != N.getValueType())
22599 V = DAG.getBitcast(N.getValueType(), V);
22601 // Return the new chain to replace N.
22605 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22608 /// We walk up the chain, skipping shuffles of the other half and looking
22609 /// through shuffles which switch halves trying to find a shuffle of the same
22610 /// pair of dwords.
22611 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22613 TargetLowering::DAGCombinerInfo &DCI) {
22615 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22616 "Called with something other than an x86 128-bit half shuffle!");
22618 unsigned CombineOpcode = N.getOpcode();
22620 // Walk up a single-use chain looking for a combinable shuffle.
22621 SDValue V = N.getOperand(0);
22622 for (; V.hasOneUse(); V = V.getOperand(0)) {
22623 switch (V.getOpcode()) {
22625 return false; // Nothing combined!
22628 // Skip bitcasts as we always know the type for the target specific
22632 case X86ISD::PSHUFLW:
22633 case X86ISD::PSHUFHW:
22634 if (V.getOpcode() == CombineOpcode)
22637 // Other-half shuffles are no-ops.
22640 // Break out of the loop if we break out of the switch.
22644 if (!V.hasOneUse())
22645 // We fell out of the loop without finding a viable combining instruction.
22648 // Combine away the bottom node as its shuffle will be accumulated into
22649 // a preceding shuffle.
22650 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22652 // Record the old value.
22655 // Merge this node's mask and our incoming mask (adjusted to account for all
22656 // the pshufd instructions encountered).
22657 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22658 for (int &M : Mask)
22660 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22661 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22663 // Check that the shuffles didn't cancel each other out. If not, we need to
22664 // combine to the new one.
22666 // Replace the combinable shuffle with the combined one, updating all users
22667 // so that we re-evaluate the chain here.
22668 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22673 /// \brief Try to combine x86 target specific shuffles.
22674 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22675 TargetLowering::DAGCombinerInfo &DCI,
22676 const X86Subtarget *Subtarget) {
22678 MVT VT = N.getSimpleValueType();
22679 SmallVector<int, 4> Mask;
22681 switch (N.getOpcode()) {
22682 case X86ISD::PSHUFD:
22683 case X86ISD::PSHUFLW:
22684 case X86ISD::PSHUFHW:
22685 Mask = getPSHUFShuffleMask(N);
22686 assert(Mask.size() == 4);
22692 // Nuke no-op shuffles that show up after combining.
22693 if (isNoopShuffleMask(Mask))
22694 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22696 // Look for simplifications involving one or two shuffle instructions.
22697 SDValue V = N.getOperand(0);
22698 switch (N.getOpcode()) {
22701 case X86ISD::PSHUFLW:
22702 case X86ISD::PSHUFHW:
22703 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22705 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22706 return SDValue(); // We combined away this shuffle, so we're done.
22708 // See if this reduces to a PSHUFD which is no more expensive and can
22709 // combine with more operations. Note that it has to at least flip the
22710 // dwords as otherwise it would have been removed as a no-op.
22711 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22712 int DMask[] = {0, 1, 2, 3};
22713 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22714 DMask[DOffset + 0] = DOffset + 1;
22715 DMask[DOffset + 1] = DOffset + 0;
22716 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22717 V = DAG.getBitcast(DVT, V);
22718 DCI.AddToWorklist(V.getNode());
22719 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22720 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22721 DCI.AddToWorklist(V.getNode());
22722 return DAG.getBitcast(VT, V);
22725 // Look for shuffle patterns which can be implemented as a single unpack.
22726 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22727 // only works when we have a PSHUFD followed by two half-shuffles.
22728 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22729 (V.getOpcode() == X86ISD::PSHUFLW ||
22730 V.getOpcode() == X86ISD::PSHUFHW) &&
22731 V.getOpcode() != N.getOpcode() &&
22733 SDValue D = V.getOperand(0);
22734 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22735 D = D.getOperand(0);
22736 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22737 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22738 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22739 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22740 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22742 for (int i = 0; i < 4; ++i) {
22743 WordMask[i + NOffset] = Mask[i] + NOffset;
22744 WordMask[i + VOffset] = VMask[i] + VOffset;
22746 // Map the word mask through the DWord mask.
22748 for (int i = 0; i < 8; ++i)
22749 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22750 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22751 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22752 // We can replace all three shuffles with an unpack.
22753 V = DAG.getBitcast(VT, D.getOperand(0));
22754 DCI.AddToWorklist(V.getNode());
22755 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22764 case X86ISD::PSHUFD:
22765 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22774 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22776 /// We combine this directly on the abstract vector shuffle nodes so it is
22777 /// easier to generically match. We also insert dummy vector shuffle nodes for
22778 /// the operands which explicitly discard the lanes which are unused by this
22779 /// operation to try to flow through the rest of the combiner the fact that
22780 /// they're unused.
22781 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22783 EVT VT = N->getValueType(0);
22785 // We only handle target-independent shuffles.
22786 // FIXME: It would be easy and harmless to use the target shuffle mask
22787 // extraction tool to support more.
22788 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22791 auto *SVN = cast<ShuffleVectorSDNode>(N);
22792 ArrayRef<int> Mask = SVN->getMask();
22793 SDValue V1 = N->getOperand(0);
22794 SDValue V2 = N->getOperand(1);
22796 // We require the first shuffle operand to be the SUB node, and the second to
22797 // be the ADD node.
22798 // FIXME: We should support the commuted patterns.
22799 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22802 // If there are other uses of these operations we can't fold them.
22803 if (!V1->hasOneUse() || !V2->hasOneUse())
22806 // Ensure that both operations have the same operands. Note that we can
22807 // commute the FADD operands.
22808 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22809 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22810 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22813 // We're looking for blends between FADD and FSUB nodes. We insist on these
22814 // nodes being lined up in a specific expected pattern.
22815 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22816 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22817 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22820 // Only specific types are legal at this point, assert so we notice if and
22821 // when these change.
22822 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22823 VT == MVT::v4f64) &&
22824 "Unknown vector type encountered!");
22826 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22829 /// PerformShuffleCombine - Performs several different shuffle combines.
22830 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22831 TargetLowering::DAGCombinerInfo &DCI,
22832 const X86Subtarget *Subtarget) {
22834 SDValue N0 = N->getOperand(0);
22835 SDValue N1 = N->getOperand(1);
22836 EVT VT = N->getValueType(0);
22838 // Don't create instructions with illegal types after legalize types has run.
22839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22840 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22843 // If we have legalized the vector types, look for blends of FADD and FSUB
22844 // nodes that we can fuse into an ADDSUB node.
22845 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22846 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22849 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22850 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22851 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22852 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22854 // During Type Legalization, when promoting illegal vector types,
22855 // the backend might introduce new shuffle dag nodes and bitcasts.
22857 // This code performs the following transformation:
22858 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22859 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22861 // We do this only if both the bitcast and the BINOP dag nodes have
22862 // one use. Also, perform this transformation only if the new binary
22863 // operation is legal. This is to avoid introducing dag nodes that
22864 // potentially need to be further expanded (or custom lowered) into a
22865 // less optimal sequence of dag nodes.
22866 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22867 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22868 N0.getOpcode() == ISD::BITCAST) {
22869 SDValue BC0 = N0.getOperand(0);
22870 EVT SVT = BC0.getValueType();
22871 unsigned Opcode = BC0.getOpcode();
22872 unsigned NumElts = VT.getVectorNumElements();
22874 if (BC0.hasOneUse() && SVT.isVector() &&
22875 SVT.getVectorNumElements() * 2 == NumElts &&
22876 TLI.isOperationLegal(Opcode, VT)) {
22877 bool CanFold = false;
22889 unsigned SVTNumElts = SVT.getVectorNumElements();
22890 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22891 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22892 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22893 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22894 CanFold = SVOp->getMaskElt(i) < 0;
22897 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22898 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22899 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22900 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22905 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22906 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22907 // consecutive, non-overlapping, and in the right order.
22908 SmallVector<SDValue, 16> Elts;
22909 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22910 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22912 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22915 if (isTargetShuffle(N->getOpcode())) {
22917 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22918 if (Shuffle.getNode())
22921 // Try recursively combining arbitrary sequences of x86 shuffle
22922 // instructions into higher-order shuffles. We do this after combining
22923 // specific PSHUF instruction sequences into their minimal form so that we
22924 // can evaluate how many specialized shuffle instructions are involved in
22925 // a particular chain.
22926 SmallVector<int, 1> NonceMask; // Just a placeholder.
22927 NonceMask.push_back(0);
22928 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22929 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22931 return SDValue(); // This routine will use CombineTo to replace N.
22937 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22938 /// specific shuffle of a load can be folded into a single element load.
22939 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22940 /// shuffles have been custom lowered so we need to handle those here.
22941 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22942 TargetLowering::DAGCombinerInfo &DCI) {
22943 if (DCI.isBeforeLegalizeOps())
22946 SDValue InVec = N->getOperand(0);
22947 SDValue EltNo = N->getOperand(1);
22949 if (!isa<ConstantSDNode>(EltNo))
22952 EVT OriginalVT = InVec.getValueType();
22954 if (InVec.getOpcode() == ISD::BITCAST) {
22955 // Don't duplicate a load with other uses.
22956 if (!InVec.hasOneUse())
22958 EVT BCVT = InVec.getOperand(0).getValueType();
22959 if (!BCVT.isVector() ||
22960 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22962 InVec = InVec.getOperand(0);
22965 EVT CurrentVT = InVec.getValueType();
22967 if (!isTargetShuffle(InVec.getOpcode()))
22970 // Don't duplicate a load with other uses.
22971 if (!InVec.hasOneUse())
22974 SmallVector<int, 16> ShuffleMask;
22976 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22977 ShuffleMask, UnaryShuffle))
22980 // Select the input vector, guarding against out of range extract vector.
22981 unsigned NumElems = CurrentVT.getVectorNumElements();
22982 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22983 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22984 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22985 : InVec.getOperand(1);
22987 // If inputs to shuffle are the same for both ops, then allow 2 uses
22988 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22989 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22991 if (LdNode.getOpcode() == ISD::BITCAST) {
22992 // Don't duplicate a load with other uses.
22993 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22996 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22997 LdNode = LdNode.getOperand(0);
23000 if (!ISD::isNormalLoad(LdNode.getNode()))
23003 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23005 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23008 EVT EltVT = N->getValueType(0);
23009 // If there's a bitcast before the shuffle, check if the load type and
23010 // alignment is valid.
23011 unsigned Align = LN0->getAlignment();
23012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23013 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23014 EltVT.getTypeForEVT(*DAG.getContext()));
23016 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23019 // All checks match so transform back to vector_shuffle so that DAG combiner
23020 // can finish the job
23023 // Create shuffle node taking into account the case that its a unary shuffle
23024 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23025 : InVec.getOperand(1);
23026 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23027 InVec.getOperand(0), Shuffle,
23029 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23030 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23034 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23035 /// special and don't usually play with other vector types, it's better to
23036 /// handle them early to be sure we emit efficient code by avoiding
23037 /// store-load conversions.
23038 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
23039 if (N->getValueType(0) != MVT::x86mmx ||
23040 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
23041 N->getOperand(0)->getValueType(0) != MVT::v2i32)
23044 SDValue V = N->getOperand(0);
23045 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
23046 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
23047 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
23048 N->getValueType(0), V.getOperand(0));
23053 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23054 /// generation and convert it from being a bunch of shuffles and extracts
23055 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23056 /// storing the value and loading scalars back, while for x64 we should
23057 /// use 64-bit extracts and shifts.
23058 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23059 TargetLowering::DAGCombinerInfo &DCI) {
23060 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23063 SDValue InputVector = N->getOperand(0);
23064 SDLoc dl(InputVector);
23065 // Detect mmx to i32 conversion through a v2i32 elt extract.
23066 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23067 N->getValueType(0) == MVT::i32 &&
23068 InputVector.getValueType() == MVT::v2i32) {
23070 // The bitcast source is a direct mmx result.
23071 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23072 if (MMXSrc.getValueType() == MVT::x86mmx)
23073 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23074 N->getValueType(0),
23075 InputVector.getNode()->getOperand(0));
23077 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23078 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23079 MMXSrc.getValueType() == MVT::i64) {
23080 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23081 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23082 MMXSrcOp.getValueType() == MVT::v1i64 &&
23083 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23084 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23085 N->getValueType(0), MMXSrcOp.getOperand(0));
23089 EVT VT = N->getValueType(0);
23091 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
23092 InputVector.getOpcode() == ISD::BITCAST &&
23093 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
23094 uint64_t ExtractedElt =
23095 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23096 uint64_t InputValue =
23097 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23098 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23099 return DAG.getConstant(Res, dl, MVT::i1);
23101 // Only operate on vectors of 4 elements, where the alternative shuffling
23102 // gets to be more expensive.
23103 if (InputVector.getValueType() != MVT::v4i32)
23106 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23107 // single use which is a sign-extend or zero-extend, and all elements are
23109 SmallVector<SDNode *, 4> Uses;
23110 unsigned ExtractedElements = 0;
23111 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23112 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23113 if (UI.getUse().getResNo() != InputVector.getResNo())
23116 SDNode *Extract = *UI;
23117 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23120 if (Extract->getValueType(0) != MVT::i32)
23122 if (!Extract->hasOneUse())
23124 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23125 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23127 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23130 // Record which element was extracted.
23131 ExtractedElements |=
23132 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23134 Uses.push_back(Extract);
23137 // If not all the elements were used, this may not be worthwhile.
23138 if (ExtractedElements != 15)
23141 // Ok, we've now decided to do the transformation.
23142 // If 64-bit shifts are legal, use the extract-shift sequence,
23143 // otherwise bounce the vector off the cache.
23144 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23147 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23148 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23149 auto &DL = DAG.getDataLayout();
23150 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23151 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23152 DAG.getConstant(0, dl, VecIdxTy));
23153 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23154 DAG.getConstant(1, dl, VecIdxTy));
23156 SDValue ShAmt = DAG.getConstant(
23157 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23158 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23159 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23160 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23161 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23162 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23163 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23165 // Store the value to a temporary stack slot.
23166 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23167 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23168 MachinePointerInfo(), false, false, 0);
23170 EVT ElementType = InputVector.getValueType().getVectorElementType();
23171 unsigned EltSize = ElementType.getSizeInBits() / 8;
23173 // Replace each use (extract) with a load of the appropriate element.
23174 for (unsigned i = 0; i < 4; ++i) {
23175 uint64_t Offset = EltSize * i;
23176 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23177 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23179 SDValue ScalarAddr =
23180 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23182 // Load the scalar.
23183 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23184 ScalarAddr, MachinePointerInfo(),
23185 false, false, false, 0);
23190 // Replace the extracts
23191 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23192 UE = Uses.end(); UI != UE; ++UI) {
23193 SDNode *Extract = *UI;
23195 SDValue Idx = Extract->getOperand(1);
23196 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23197 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23200 // The replacement was made in place; don't return anything.
23205 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23206 const X86Subtarget *Subtarget) {
23208 SDValue Cond = N->getOperand(0);
23209 SDValue LHS = N->getOperand(1);
23210 SDValue RHS = N->getOperand(2);
23212 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23213 SDValue CondSrc = Cond->getOperand(0);
23214 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23215 Cond = CondSrc->getOperand(0);
23218 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23221 // A vselect where all conditions and data are constants can be optimized into
23222 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23223 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23224 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23227 unsigned MaskValue = 0;
23228 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23231 MVT VT = N->getSimpleValueType(0);
23232 unsigned NumElems = VT.getVectorNumElements();
23233 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23234 for (unsigned i = 0; i < NumElems; ++i) {
23235 // Be sure we emit undef where we can.
23236 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23237 ShuffleMask[i] = -1;
23239 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23243 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23245 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23248 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23250 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23251 TargetLowering::DAGCombinerInfo &DCI,
23252 const X86Subtarget *Subtarget) {
23254 SDValue Cond = N->getOperand(0);
23255 // Get the LHS/RHS of the select.
23256 SDValue LHS = N->getOperand(1);
23257 SDValue RHS = N->getOperand(2);
23258 EVT VT = LHS.getValueType();
23259 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23261 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23262 // instructions match the semantics of the common C idiom x<y?x:y but not
23263 // x<=y?x:y, because of how they handle negative zero (which can be
23264 // ignored in unsafe-math mode).
23265 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23266 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23267 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23268 (Subtarget->hasSSE2() ||
23269 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23270 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23272 unsigned Opcode = 0;
23273 // Check for x CC y ? x : y.
23274 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23275 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23279 // Converting this to a min would handle NaNs incorrectly, and swapping
23280 // the operands would cause it to handle comparisons between positive
23281 // and negative zero incorrectly.
23282 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23283 if (!DAG.getTarget().Options.UnsafeFPMath &&
23284 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23286 std::swap(LHS, RHS);
23288 Opcode = X86ISD::FMIN;
23291 // Converting this to a min would handle comparisons between positive
23292 // and negative zero incorrectly.
23293 if (!DAG.getTarget().Options.UnsafeFPMath &&
23294 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23296 Opcode = X86ISD::FMIN;
23299 // Converting this to a min would handle both negative zeros and NaNs
23300 // incorrectly, but we can swap the operands to fix both.
23301 std::swap(LHS, RHS);
23305 Opcode = X86ISD::FMIN;
23309 // Converting this to a max would handle comparisons between positive
23310 // and negative zero incorrectly.
23311 if (!DAG.getTarget().Options.UnsafeFPMath &&
23312 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23314 Opcode = X86ISD::FMAX;
23317 // Converting this to a max would handle NaNs incorrectly, and swapping
23318 // the operands would cause it to handle comparisons between positive
23319 // and negative zero incorrectly.
23320 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23321 if (!DAG.getTarget().Options.UnsafeFPMath &&
23322 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23324 std::swap(LHS, RHS);
23326 Opcode = X86ISD::FMAX;
23329 // Converting this to a max would handle both negative zeros and NaNs
23330 // incorrectly, but we can swap the operands to fix both.
23331 std::swap(LHS, RHS);
23335 Opcode = X86ISD::FMAX;
23338 // Check for x CC y ? y : x -- a min/max with reversed arms.
23339 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23340 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23344 // Converting this to a min would handle comparisons between positive
23345 // and negative zero incorrectly, and swapping the operands would
23346 // cause it to handle NaNs incorrectly.
23347 if (!DAG.getTarget().Options.UnsafeFPMath &&
23348 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23349 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23351 std::swap(LHS, RHS);
23353 Opcode = X86ISD::FMIN;
23356 // Converting this to a min would handle NaNs incorrectly.
23357 if (!DAG.getTarget().Options.UnsafeFPMath &&
23358 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23360 Opcode = X86ISD::FMIN;
23363 // Converting this to a min would handle both negative zeros and NaNs
23364 // incorrectly, but we can swap the operands to fix both.
23365 std::swap(LHS, RHS);
23369 Opcode = X86ISD::FMIN;
23373 // Converting this to a max would handle NaNs incorrectly.
23374 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23376 Opcode = X86ISD::FMAX;
23379 // Converting this to a max would handle comparisons between positive
23380 // and negative zero incorrectly, and swapping the operands would
23381 // cause it to handle NaNs incorrectly.
23382 if (!DAG.getTarget().Options.UnsafeFPMath &&
23383 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23384 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23386 std::swap(LHS, RHS);
23388 Opcode = X86ISD::FMAX;
23391 // Converting this to a max would handle both negative zeros and NaNs
23392 // incorrectly, but we can swap the operands to fix both.
23393 std::swap(LHS, RHS);
23397 Opcode = X86ISD::FMAX;
23403 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23406 EVT CondVT = Cond.getValueType();
23407 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23408 CondVT.getVectorElementType() == MVT::i1) {
23409 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23410 // lowering on KNL. In this case we convert it to
23411 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23412 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23413 // Since SKX these selects have a proper lowering.
23414 EVT OpVT = LHS.getValueType();
23415 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23416 (OpVT.getVectorElementType() == MVT::i8 ||
23417 OpVT.getVectorElementType() == MVT::i16) &&
23418 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23419 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23420 DCI.AddToWorklist(Cond.getNode());
23421 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23424 // If this is a select between two integer constants, try to do some
23426 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23427 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23428 // Don't do this for crazy integer types.
23429 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23430 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23431 // so that TrueC (the true value) is larger than FalseC.
23432 bool NeedsCondInvert = false;
23434 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23435 // Efficiently invertible.
23436 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23437 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23438 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23439 NeedsCondInvert = true;
23440 std::swap(TrueC, FalseC);
23443 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23444 if (FalseC->getAPIntValue() == 0 &&
23445 TrueC->getAPIntValue().isPowerOf2()) {
23446 if (NeedsCondInvert) // Invert the condition if needed.
23447 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23448 DAG.getConstant(1, DL, Cond.getValueType()));
23450 // Zero extend the condition if needed.
23451 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23453 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23454 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23455 DAG.getConstant(ShAmt, DL, MVT::i8));
23458 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23459 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23460 if (NeedsCondInvert) // Invert the condition if needed.
23461 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23462 DAG.getConstant(1, DL, Cond.getValueType()));
23464 // Zero extend the condition if needed.
23465 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23466 FalseC->getValueType(0), Cond);
23467 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23468 SDValue(FalseC, 0));
23471 // Optimize cases that will turn into an LEA instruction. This requires
23472 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23473 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23474 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23475 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23477 bool isFastMultiplier = false;
23479 switch ((unsigned char)Diff) {
23481 case 1: // result = add base, cond
23482 case 2: // result = lea base( , cond*2)
23483 case 3: // result = lea base(cond, cond*2)
23484 case 4: // result = lea base( , cond*4)
23485 case 5: // result = lea base(cond, cond*4)
23486 case 8: // result = lea base( , cond*8)
23487 case 9: // result = lea base(cond, cond*8)
23488 isFastMultiplier = true;
23493 if (isFastMultiplier) {
23494 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23495 if (NeedsCondInvert) // Invert the condition if needed.
23496 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23497 DAG.getConstant(1, DL, Cond.getValueType()));
23499 // Zero extend the condition if needed.
23500 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23502 // Scale the condition by the difference.
23504 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23505 DAG.getConstant(Diff, DL,
23506 Cond.getValueType()));
23508 // Add the base if non-zero.
23509 if (FalseC->getAPIntValue() != 0)
23510 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23511 SDValue(FalseC, 0));
23518 // Canonicalize max and min:
23519 // (x > y) ? x : y -> (x >= y) ? x : y
23520 // (x < y) ? x : y -> (x <= y) ? x : y
23521 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23522 // the need for an extra compare
23523 // against zero. e.g.
23524 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23526 // testl %edi, %edi
23528 // cmovgl %edi, %eax
23532 // cmovsl %eax, %edi
23533 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23534 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23535 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23536 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23541 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23542 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23543 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23544 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23549 // Early exit check
23550 if (!TLI.isTypeLegal(VT))
23553 // Match VSELECTs into subs with unsigned saturation.
23554 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23555 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23556 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23557 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23558 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23560 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23561 // left side invert the predicate to simplify logic below.
23563 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23565 CC = ISD::getSetCCInverse(CC, true);
23566 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23570 if (Other.getNode() && Other->getNumOperands() == 2 &&
23571 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23572 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23573 SDValue CondRHS = Cond->getOperand(1);
23575 // Look for a general sub with unsigned saturation first.
23576 // x >= y ? x-y : 0 --> subus x, y
23577 // x > y ? x-y : 0 --> subus x, y
23578 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23579 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23580 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23582 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23583 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23584 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23585 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23586 // If the RHS is a constant we have to reverse the const
23587 // canonicalization.
23588 // x > C-1 ? x+-C : 0 --> subus x, C
23589 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23590 CondRHSConst->getAPIntValue() ==
23591 (-OpRHSConst->getAPIntValue() - 1))
23592 return DAG.getNode(
23593 X86ISD::SUBUS, DL, VT, OpLHS,
23594 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23596 // Another special case: If C was a sign bit, the sub has been
23597 // canonicalized into a xor.
23598 // FIXME: Would it be better to use computeKnownBits to determine
23599 // whether it's safe to decanonicalize the xor?
23600 // x s< 0 ? x^C : 0 --> subus x, C
23601 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23602 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23603 OpRHSConst->getAPIntValue().isSignBit())
23604 // Note that we have to rebuild the RHS constant here to ensure we
23605 // don't rely on particular values of undef lanes.
23606 return DAG.getNode(
23607 X86ISD::SUBUS, DL, VT, OpLHS,
23608 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23613 // Simplify vector selection if condition value type matches vselect
23615 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23616 assert(Cond.getValueType().isVector() &&
23617 "vector select expects a vector selector!");
23619 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23620 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23622 // Try invert the condition if true value is not all 1s and false value
23624 if (!TValIsAllOnes && !FValIsAllZeros &&
23625 // Check if the selector will be produced by CMPP*/PCMP*
23626 Cond.getOpcode() == ISD::SETCC &&
23627 // Check if SETCC has already been promoted
23628 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23630 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23631 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23633 if (TValIsAllZeros || FValIsAllOnes) {
23634 SDValue CC = Cond.getOperand(2);
23635 ISD::CondCode NewCC =
23636 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23637 Cond.getOperand(0).getValueType().isInteger());
23638 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23639 std::swap(LHS, RHS);
23640 TValIsAllOnes = FValIsAllOnes;
23641 FValIsAllZeros = TValIsAllZeros;
23645 if (TValIsAllOnes || FValIsAllZeros) {
23648 if (TValIsAllOnes && FValIsAllZeros)
23650 else if (TValIsAllOnes)
23652 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23653 else if (FValIsAllZeros)
23654 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23655 DAG.getBitcast(CondVT, LHS));
23657 return DAG.getBitcast(VT, Ret);
23661 // We should generate an X86ISD::BLENDI from a vselect if its argument
23662 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23663 // constants. This specific pattern gets generated when we split a
23664 // selector for a 512 bit vector in a machine without AVX512 (but with
23665 // 256-bit vectors), during legalization:
23667 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23669 // Iff we find this pattern and the build_vectors are built from
23670 // constants, we translate the vselect into a shuffle_vector that we
23671 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23672 if ((N->getOpcode() == ISD::VSELECT ||
23673 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23674 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23675 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23676 if (Shuffle.getNode())
23680 // If this is a *dynamic* select (non-constant condition) and we can match
23681 // this node with one of the variable blend instructions, restructure the
23682 // condition so that the blends can use the high bit of each element and use
23683 // SimplifyDemandedBits to simplify the condition operand.
23684 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23685 !DCI.isBeforeLegalize() &&
23686 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23687 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23689 // Don't optimize vector selects that map to mask-registers.
23693 // We can only handle the cases where VSELECT is directly legal on the
23694 // subtarget. We custom lower VSELECT nodes with constant conditions and
23695 // this makes it hard to see whether a dynamic VSELECT will correctly
23696 // lower, so we both check the operation's status and explicitly handle the
23697 // cases where a *dynamic* blend will fail even though a constant-condition
23698 // blend could be custom lowered.
23699 // FIXME: We should find a better way to handle this class of problems.
23700 // Potentially, we should combine constant-condition vselect nodes
23701 // pre-legalization into shuffles and not mark as many types as custom
23703 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23705 // FIXME: We don't support i16-element blends currently. We could and
23706 // should support them by making *all* the bits in the condition be set
23707 // rather than just the high bit and using an i8-element blend.
23708 if (VT.getScalarType() == MVT::i16)
23710 // Dynamic blending was only available from SSE4.1 onward.
23711 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23713 // Byte blends are only available in AVX2
23714 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23715 !Subtarget->hasAVX2())
23718 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23719 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23721 APInt KnownZero, KnownOne;
23722 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23723 DCI.isBeforeLegalizeOps());
23724 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23725 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23727 // If we changed the computation somewhere in the DAG, this change
23728 // will affect all users of Cond.
23729 // Make sure it is fine and update all the nodes so that we do not
23730 // use the generic VSELECT anymore. Otherwise, we may perform
23731 // wrong optimizations as we messed up with the actual expectation
23732 // for the vector boolean values.
23733 if (Cond != TLO.Old) {
23734 // Check all uses of that condition operand to check whether it will be
23735 // consumed by non-BLEND instructions, which may depend on all bits are
23737 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23739 if (I->getOpcode() != ISD::VSELECT)
23740 // TODO: Add other opcodes eventually lowered into BLEND.
23743 // Update all the users of the condition, before committing the change,
23744 // so that the VSELECT optimizations that expect the correct vector
23745 // boolean value will not be triggered.
23746 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23748 DAG.ReplaceAllUsesOfValueWith(
23750 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23751 Cond, I->getOperand(1), I->getOperand(2)));
23752 DCI.CommitTargetLoweringOpt(TLO);
23755 // At this point, only Cond is changed. Change the condition
23756 // just for N to keep the opportunity to optimize all other
23757 // users their own way.
23758 DAG.ReplaceAllUsesOfValueWith(
23760 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23761 TLO.New, N->getOperand(1), N->getOperand(2)));
23769 // Check whether a boolean test is testing a boolean value generated by
23770 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23773 // Simplify the following patterns:
23774 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23775 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23776 // to (Op EFLAGS Cond)
23778 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23779 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23780 // to (Op EFLAGS !Cond)
23782 // where Op could be BRCOND or CMOV.
23784 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23785 // Quit if not CMP and SUB with its value result used.
23786 if (Cmp.getOpcode() != X86ISD::CMP &&
23787 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23790 // Quit if not used as a boolean value.
23791 if (CC != X86::COND_E && CC != X86::COND_NE)
23794 // Check CMP operands. One of them should be 0 or 1 and the other should be
23795 // an SetCC or extended from it.
23796 SDValue Op1 = Cmp.getOperand(0);
23797 SDValue Op2 = Cmp.getOperand(1);
23800 const ConstantSDNode* C = nullptr;
23801 bool needOppositeCond = (CC == X86::COND_E);
23802 bool checkAgainstTrue = false; // Is it a comparison against 1?
23804 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23806 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23808 else // Quit if all operands are not constants.
23811 if (C->getZExtValue() == 1) {
23812 needOppositeCond = !needOppositeCond;
23813 checkAgainstTrue = true;
23814 } else if (C->getZExtValue() != 0)
23815 // Quit if the constant is neither 0 or 1.
23818 bool truncatedToBoolWithAnd = false;
23819 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23820 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23821 SetCC.getOpcode() == ISD::TRUNCATE ||
23822 SetCC.getOpcode() == ISD::AND) {
23823 if (SetCC.getOpcode() == ISD::AND) {
23825 ConstantSDNode *CS;
23826 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23827 CS->getZExtValue() == 1)
23829 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23830 CS->getZExtValue() == 1)
23834 SetCC = SetCC.getOperand(OpIdx);
23835 truncatedToBoolWithAnd = true;
23837 SetCC = SetCC.getOperand(0);
23840 switch (SetCC.getOpcode()) {
23841 case X86ISD::SETCC_CARRY:
23842 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23843 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23844 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23845 // truncated to i1 using 'and'.
23846 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23848 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23849 "Invalid use of SETCC_CARRY!");
23851 case X86ISD::SETCC:
23852 // Set the condition code or opposite one if necessary.
23853 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23854 if (needOppositeCond)
23855 CC = X86::GetOppositeBranchCondition(CC);
23856 return SetCC.getOperand(1);
23857 case X86ISD::CMOV: {
23858 // Check whether false/true value has canonical one, i.e. 0 or 1.
23859 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23860 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23861 // Quit if true value is not a constant.
23864 // Quit if false value is not a constant.
23866 SDValue Op = SetCC.getOperand(0);
23867 // Skip 'zext' or 'trunc' node.
23868 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23869 Op.getOpcode() == ISD::TRUNCATE)
23870 Op = Op.getOperand(0);
23871 // A special case for rdrand/rdseed, where 0 is set if false cond is
23873 if ((Op.getOpcode() != X86ISD::RDRAND &&
23874 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23877 // Quit if false value is not the constant 0 or 1.
23878 bool FValIsFalse = true;
23879 if (FVal && FVal->getZExtValue() != 0) {
23880 if (FVal->getZExtValue() != 1)
23882 // If FVal is 1, opposite cond is needed.
23883 needOppositeCond = !needOppositeCond;
23884 FValIsFalse = false;
23886 // Quit if TVal is not the constant opposite of FVal.
23887 if (FValIsFalse && TVal->getZExtValue() != 1)
23889 if (!FValIsFalse && TVal->getZExtValue() != 0)
23891 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23892 if (needOppositeCond)
23893 CC = X86::GetOppositeBranchCondition(CC);
23894 return SetCC.getOperand(3);
23901 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23903 /// (X86or (X86setcc) (X86setcc))
23904 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23905 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23906 X86::CondCode &CC1, SDValue &Flags,
23908 if (Cond->getOpcode() == X86ISD::CMP) {
23909 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23910 if (!CondOp1C || !CondOp1C->isNullValue())
23913 Cond = Cond->getOperand(0);
23918 SDValue SetCC0, SetCC1;
23919 switch (Cond->getOpcode()) {
23920 default: return false;
23927 SetCC0 = Cond->getOperand(0);
23928 SetCC1 = Cond->getOperand(1);
23932 // Make sure we have SETCC nodes, using the same flags value.
23933 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23934 SetCC1.getOpcode() != X86ISD::SETCC ||
23935 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23938 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23939 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23940 Flags = SetCC0->getOperand(1);
23944 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23945 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23946 TargetLowering::DAGCombinerInfo &DCI,
23947 const X86Subtarget *Subtarget) {
23950 // If the flag operand isn't dead, don't touch this CMOV.
23951 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23954 SDValue FalseOp = N->getOperand(0);
23955 SDValue TrueOp = N->getOperand(1);
23956 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23957 SDValue Cond = N->getOperand(3);
23959 if (CC == X86::COND_E || CC == X86::COND_NE) {
23960 switch (Cond.getOpcode()) {
23964 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23965 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23966 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23972 Flags = checkBoolTestSetCCCombine(Cond, CC);
23973 if (Flags.getNode() &&
23974 // Extra check as FCMOV only supports a subset of X86 cond.
23975 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23976 SDValue Ops[] = { FalseOp, TrueOp,
23977 DAG.getConstant(CC, DL, MVT::i8), Flags };
23978 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23981 // If this is a select between two integer constants, try to do some
23982 // optimizations. Note that the operands are ordered the opposite of SELECT
23984 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23985 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23986 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23987 // larger than FalseC (the false value).
23988 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23989 CC = X86::GetOppositeBranchCondition(CC);
23990 std::swap(TrueC, FalseC);
23991 std::swap(TrueOp, FalseOp);
23994 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23995 // This is efficient for any integer data type (including i8/i16) and
23997 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23998 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23999 DAG.getConstant(CC, DL, MVT::i8), Cond);
24001 // Zero extend the condition if needed.
24002 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24004 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24005 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24006 DAG.getConstant(ShAmt, DL, MVT::i8));
24007 if (N->getNumValues() == 2) // Dead flag value?
24008 return DCI.CombineTo(N, Cond, SDValue());
24012 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24013 // for any integer data type, including i8/i16.
24014 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24015 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24016 DAG.getConstant(CC, DL, MVT::i8), Cond);
24018 // Zero extend the condition if needed.
24019 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24020 FalseC->getValueType(0), Cond);
24021 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24022 SDValue(FalseC, 0));
24024 if (N->getNumValues() == 2) // Dead flag value?
24025 return DCI.CombineTo(N, Cond, SDValue());
24029 // Optimize cases that will turn into an LEA instruction. This requires
24030 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24031 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24032 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24033 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24035 bool isFastMultiplier = false;
24037 switch ((unsigned char)Diff) {
24039 case 1: // result = add base, cond
24040 case 2: // result = lea base( , cond*2)
24041 case 3: // result = lea base(cond, cond*2)
24042 case 4: // result = lea base( , cond*4)
24043 case 5: // result = lea base(cond, cond*4)
24044 case 8: // result = lea base( , cond*8)
24045 case 9: // result = lea base(cond, cond*8)
24046 isFastMultiplier = true;
24051 if (isFastMultiplier) {
24052 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24053 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24054 DAG.getConstant(CC, DL, MVT::i8), Cond);
24055 // Zero extend the condition if needed.
24056 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24058 // Scale the condition by the difference.
24060 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24061 DAG.getConstant(Diff, DL, Cond.getValueType()));
24063 // Add the base if non-zero.
24064 if (FalseC->getAPIntValue() != 0)
24065 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24066 SDValue(FalseC, 0));
24067 if (N->getNumValues() == 2) // Dead flag value?
24068 return DCI.CombineTo(N, Cond, SDValue());
24075 // Handle these cases:
24076 // (select (x != c), e, c) -> select (x != c), e, x),
24077 // (select (x == c), c, e) -> select (x == c), x, e)
24078 // where the c is an integer constant, and the "select" is the combination
24079 // of CMOV and CMP.
24081 // The rationale for this change is that the conditional-move from a constant
24082 // needs two instructions, however, conditional-move from a register needs
24083 // only one instruction.
24085 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24086 // some instruction-combining opportunities. This opt needs to be
24087 // postponed as late as possible.
24089 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24090 // the DCI.xxxx conditions are provided to postpone the optimization as
24091 // late as possible.
24093 ConstantSDNode *CmpAgainst = nullptr;
24094 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24095 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24096 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24098 if (CC == X86::COND_NE &&
24099 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24100 CC = X86::GetOppositeBranchCondition(CC);
24101 std::swap(TrueOp, FalseOp);
24104 if (CC == X86::COND_E &&
24105 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24106 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24107 DAG.getConstant(CC, DL, MVT::i8), Cond };
24108 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24113 // Fold and/or of setcc's to double CMOV:
24114 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24115 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24117 // This combine lets us generate:
24118 // cmovcc1 (jcc1 if we don't have CMOV)
24124 // cmovne (jne if we don't have CMOV)
24125 // When we can't use the CMOV instruction, it might increase branch
24127 // When we can use CMOV, or when there is no mispredict, this improves
24128 // throughput and reduces register pressure.
24130 if (CC == X86::COND_NE) {
24132 X86::CondCode CC0, CC1;
24134 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24136 std::swap(FalseOp, TrueOp);
24137 CC0 = X86::GetOppositeBranchCondition(CC0);
24138 CC1 = X86::GetOppositeBranchCondition(CC1);
24141 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24143 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24144 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24145 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24146 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24154 /// PerformMulCombine - Optimize a single multiply with constant into two
24155 /// in order to implement it with two cheaper instructions, e.g.
24156 /// LEA + SHL, LEA + LEA.
24157 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24158 TargetLowering::DAGCombinerInfo &DCI) {
24159 // An imul is usually smaller than the alternative sequence.
24160 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24163 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24166 EVT VT = N->getValueType(0);
24167 if (VT != MVT::i64 && VT != MVT::i32)
24170 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24173 uint64_t MulAmt = C->getZExtValue();
24174 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24177 uint64_t MulAmt1 = 0;
24178 uint64_t MulAmt2 = 0;
24179 if ((MulAmt % 9) == 0) {
24181 MulAmt2 = MulAmt / 9;
24182 } else if ((MulAmt % 5) == 0) {
24184 MulAmt2 = MulAmt / 5;
24185 } else if ((MulAmt % 3) == 0) {
24187 MulAmt2 = MulAmt / 3;
24190 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24193 if (isPowerOf2_64(MulAmt2) &&
24194 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24195 // If second multiplifer is pow2, issue it first. We want the multiply by
24196 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24198 std::swap(MulAmt1, MulAmt2);
24201 if (isPowerOf2_64(MulAmt1))
24202 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24203 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24205 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24206 DAG.getConstant(MulAmt1, DL, VT));
24208 if (isPowerOf2_64(MulAmt2))
24209 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24210 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24212 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24213 DAG.getConstant(MulAmt2, DL, VT));
24215 // Do not add new nodes to DAG combiner worklist.
24216 DCI.CombineTo(N, NewMul, false);
24221 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24222 SDValue N0 = N->getOperand(0);
24223 SDValue N1 = N->getOperand(1);
24224 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24225 EVT VT = N0.getValueType();
24227 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24228 // since the result of setcc_c is all zero's or all ones.
24229 if (VT.isInteger() && !VT.isVector() &&
24230 N1C && N0.getOpcode() == ISD::AND &&
24231 N0.getOperand(1).getOpcode() == ISD::Constant) {
24232 SDValue N00 = N0.getOperand(0);
24233 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24234 APInt ShAmt = N1C->getAPIntValue();
24235 Mask = Mask.shl(ShAmt);
24236 bool MaskOK = false;
24237 // We can handle cases concerning bit-widening nodes containing setcc_c if
24238 // we carefully interrogate the mask to make sure we are semantics
24240 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24241 // of the underlying setcc_c operation if the setcc_c was zero extended.
24242 // Consider the following example:
24243 // zext(setcc_c) -> i32 0x0000FFFF
24244 // c1 -> i32 0x0000FFFF
24245 // c2 -> i32 0x00000001
24246 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24247 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24248 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24250 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24251 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24253 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24254 N00.getOpcode() == ISD::ANY_EXTEND) &&
24255 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24256 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24258 if (MaskOK && Mask != 0) {
24260 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24264 // Hardware support for vector shifts is sparse which makes us scalarize the
24265 // vector operations in many cases. Also, on sandybridge ADD is faster than
24267 // (shl V, 1) -> add V,V
24268 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24269 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24270 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24271 // We shift all of the values by one. In many cases we do not have
24272 // hardware support for this operation. This is better expressed as an ADD
24274 if (N1SplatC->getAPIntValue() == 1)
24275 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24281 /// \brief Returns a vector of 0s if the node in input is a vector logical
24282 /// shift by a constant amount which is known to be bigger than or equal
24283 /// to the vector element size in bits.
24284 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24285 const X86Subtarget *Subtarget) {
24286 EVT VT = N->getValueType(0);
24288 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24289 (!Subtarget->hasInt256() ||
24290 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24293 SDValue Amt = N->getOperand(1);
24295 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24296 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24297 APInt ShiftAmt = AmtSplat->getAPIntValue();
24298 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24300 // SSE2/AVX2 logical shifts always return a vector of 0s
24301 // if the shift amount is bigger than or equal to
24302 // the element size. The constant shift amount will be
24303 // encoded as a 8-bit immediate.
24304 if (ShiftAmt.trunc(8).uge(MaxAmount))
24305 return getZeroVector(VT, Subtarget, DAG, DL);
24311 /// PerformShiftCombine - Combine shifts.
24312 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24313 TargetLowering::DAGCombinerInfo &DCI,
24314 const X86Subtarget *Subtarget) {
24315 if (N->getOpcode() == ISD::SHL)
24316 if (SDValue V = PerformSHLCombine(N, DAG))
24319 // Try to fold this logical shift into a zero vector.
24320 if (N->getOpcode() != ISD::SRA)
24321 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24327 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24328 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24329 // and friends. Likewise for OR -> CMPNEQSS.
24330 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24331 TargetLowering::DAGCombinerInfo &DCI,
24332 const X86Subtarget *Subtarget) {
24335 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24336 // we're requiring SSE2 for both.
24337 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24338 SDValue N0 = N->getOperand(0);
24339 SDValue N1 = N->getOperand(1);
24340 SDValue CMP0 = N0->getOperand(1);
24341 SDValue CMP1 = N1->getOperand(1);
24344 // The SETCCs should both refer to the same CMP.
24345 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24348 SDValue CMP00 = CMP0->getOperand(0);
24349 SDValue CMP01 = CMP0->getOperand(1);
24350 EVT VT = CMP00.getValueType();
24352 if (VT == MVT::f32 || VT == MVT::f64) {
24353 bool ExpectingFlags = false;
24354 // Check for any users that want flags:
24355 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24356 !ExpectingFlags && UI != UE; ++UI)
24357 switch (UI->getOpcode()) {
24362 ExpectingFlags = true;
24364 case ISD::CopyToReg:
24365 case ISD::SIGN_EXTEND:
24366 case ISD::ZERO_EXTEND:
24367 case ISD::ANY_EXTEND:
24371 if (!ExpectingFlags) {
24372 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24373 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24375 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24376 X86::CondCode tmp = cc0;
24381 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24382 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24383 // FIXME: need symbolic constants for these magic numbers.
24384 // See X86ATTInstPrinter.cpp:printSSECC().
24385 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24386 if (Subtarget->hasAVX512()) {
24387 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24389 DAG.getConstant(x86cc, DL, MVT::i8));
24390 if (N->getValueType(0) != MVT::i1)
24391 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24395 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24396 CMP00.getValueType(), CMP00, CMP01,
24397 DAG.getConstant(x86cc, DL,
24400 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24401 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24403 if (is64BitFP && !Subtarget->is64Bit()) {
24404 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24405 // 64-bit integer, since that's not a legal type. Since
24406 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24407 // bits, but can do this little dance to extract the lowest 32 bits
24408 // and work with those going forward.
24409 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24411 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24412 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24413 Vector32, DAG.getIntPtrConstant(0, DL));
24417 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24418 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24419 DAG.getConstant(1, DL, IntVT));
24420 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24422 return OneBitOfTruth;
24430 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24431 /// so it can be folded inside ANDNP.
24432 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24433 EVT VT = N->getValueType(0);
24435 // Match direct AllOnes for 128 and 256-bit vectors
24436 if (ISD::isBuildVectorAllOnes(N))
24439 // Look through a bit convert.
24440 if (N->getOpcode() == ISD::BITCAST)
24441 N = N->getOperand(0).getNode();
24443 // Sometimes the operand may come from a insert_subvector building a 256-bit
24445 if (VT.is256BitVector() &&
24446 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24447 SDValue V1 = N->getOperand(0);
24448 SDValue V2 = N->getOperand(1);
24450 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24451 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24452 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24453 ISD::isBuildVectorAllOnes(V2.getNode()))
24460 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24461 // register. In most cases we actually compare or select YMM-sized registers
24462 // and mixing the two types creates horrible code. This method optimizes
24463 // some of the transition sequences.
24464 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24465 TargetLowering::DAGCombinerInfo &DCI,
24466 const X86Subtarget *Subtarget) {
24467 EVT VT = N->getValueType(0);
24468 if (!VT.is256BitVector())
24471 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24472 N->getOpcode() == ISD::ZERO_EXTEND ||
24473 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24475 SDValue Narrow = N->getOperand(0);
24476 EVT NarrowVT = Narrow->getValueType(0);
24477 if (!NarrowVT.is128BitVector())
24480 if (Narrow->getOpcode() != ISD::XOR &&
24481 Narrow->getOpcode() != ISD::AND &&
24482 Narrow->getOpcode() != ISD::OR)
24485 SDValue N0 = Narrow->getOperand(0);
24486 SDValue N1 = Narrow->getOperand(1);
24489 // The Left side has to be a trunc.
24490 if (N0.getOpcode() != ISD::TRUNCATE)
24493 // The type of the truncated inputs.
24494 EVT WideVT = N0->getOperand(0)->getValueType(0);
24498 // The right side has to be a 'trunc' or a constant vector.
24499 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24500 ConstantSDNode *RHSConstSplat = nullptr;
24501 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24502 RHSConstSplat = RHSBV->getConstantSplatNode();
24503 if (!RHSTrunc && !RHSConstSplat)
24506 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24508 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24511 // Set N0 and N1 to hold the inputs to the new wide operation.
24512 N0 = N0->getOperand(0);
24513 if (RHSConstSplat) {
24514 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24515 SDValue(RHSConstSplat, 0));
24516 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24517 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24518 } else if (RHSTrunc) {
24519 N1 = N1->getOperand(0);
24522 // Generate the wide operation.
24523 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24524 unsigned Opcode = N->getOpcode();
24526 case ISD::ANY_EXTEND:
24528 case ISD::ZERO_EXTEND: {
24529 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24530 APInt Mask = APInt::getAllOnesValue(InBits);
24531 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24532 return DAG.getNode(ISD::AND, DL, VT,
24533 Op, DAG.getConstant(Mask, DL, VT));
24535 case ISD::SIGN_EXTEND:
24536 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24537 Op, DAG.getValueType(NarrowVT));
24539 llvm_unreachable("Unexpected opcode");
24543 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24544 TargetLowering::DAGCombinerInfo &DCI,
24545 const X86Subtarget *Subtarget) {
24546 SDValue N0 = N->getOperand(0);
24547 SDValue N1 = N->getOperand(1);
24550 // A vector zext_in_reg may be represented as a shuffle,
24551 // feeding into a bitcast (this represents anyext) feeding into
24552 // an and with a mask.
24553 // We'd like to try to combine that into a shuffle with zero
24554 // plus a bitcast, removing the and.
24555 if (N0.getOpcode() != ISD::BITCAST ||
24556 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24559 // The other side of the AND should be a splat of 2^C, where C
24560 // is the number of bits in the source type.
24561 if (N1.getOpcode() == ISD::BITCAST)
24562 N1 = N1.getOperand(0);
24563 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24565 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24567 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24568 EVT SrcType = Shuffle->getValueType(0);
24570 // We expect a single-source shuffle
24571 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24574 unsigned SrcSize = SrcType.getScalarSizeInBits();
24576 APInt SplatValue, SplatUndef;
24577 unsigned SplatBitSize;
24579 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24580 SplatBitSize, HasAnyUndefs))
24583 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24584 // Make sure the splat matches the mask we expect
24585 if (SplatBitSize > ResSize ||
24586 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24589 // Make sure the input and output size make sense
24590 if (SrcSize >= ResSize || ResSize % SrcSize)
24593 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24594 // The number of u's between each two values depends on the ratio between
24595 // the source and dest type.
24596 unsigned ZextRatio = ResSize / SrcSize;
24597 bool IsZext = true;
24598 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24599 if (i % ZextRatio) {
24600 if (Shuffle->getMaskElt(i) > 0) {
24606 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24607 // Expected element number
24617 // Ok, perform the transformation - replace the shuffle with
24618 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24619 // (instead of undef) where the k elements come from the zero vector.
24620 SmallVector<int, 8> Mask;
24621 unsigned NumElems = SrcType.getVectorNumElements();
24622 for (unsigned i = 0; i < NumElems; ++i)
24624 Mask.push_back(NumElems);
24626 Mask.push_back(i / ZextRatio);
24628 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24629 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24630 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24633 /// If both input operands of a logic op are being cast from floating point
24634 /// types, try to convert this into a floating point logic node to avoid
24635 /// unnecessary moves from SSE to integer registers.
24636 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24637 const X86Subtarget *Subtarget) {
24638 unsigned FPOpcode = ISD::DELETED_NODE;
24639 if (N->getOpcode() == ISD::AND)
24640 FPOpcode = X86ISD::FAND;
24641 else if (N->getOpcode() == ISD::OR)
24642 FPOpcode = X86ISD::FOR;
24643 else if (N->getOpcode() == ISD::XOR)
24644 FPOpcode = X86ISD::FXOR;
24646 assert(FPOpcode != ISD::DELETED_NODE &&
24647 "Unexpected input node for FP logic conversion");
24649 EVT VT = N->getValueType(0);
24650 SDValue N0 = N->getOperand(0);
24651 SDValue N1 = N->getOperand(1);
24653 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24654 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24655 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24656 SDValue N00 = N0.getOperand(0);
24657 SDValue N10 = N1.getOperand(0);
24658 EVT N00Type = N00.getValueType();
24659 EVT N10Type = N10.getValueType();
24660 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24661 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24662 return DAG.getBitcast(VT, FPLogic);
24668 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24669 TargetLowering::DAGCombinerInfo &DCI,
24670 const X86Subtarget *Subtarget) {
24671 if (DCI.isBeforeLegalizeOps())
24674 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24677 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24680 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24683 EVT VT = N->getValueType(0);
24684 SDValue N0 = N->getOperand(0);
24685 SDValue N1 = N->getOperand(1);
24688 // Create BEXTR instructions
24689 // BEXTR is ((X >> imm) & (2**size-1))
24690 if (VT == MVT::i32 || VT == MVT::i64) {
24691 // Check for BEXTR.
24692 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24693 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24694 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24695 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24696 if (MaskNode && ShiftNode) {
24697 uint64_t Mask = MaskNode->getZExtValue();
24698 uint64_t Shift = ShiftNode->getZExtValue();
24699 if (isMask_64(Mask)) {
24700 uint64_t MaskSize = countPopulation(Mask);
24701 if (Shift + MaskSize <= VT.getSizeInBits())
24702 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24703 DAG.getConstant(Shift | (MaskSize << 8), DL,
24712 // Want to form ANDNP nodes:
24713 // 1) In the hopes of then easily combining them with OR and AND nodes
24714 // to form PBLEND/PSIGN.
24715 // 2) To match ANDN packed intrinsics
24716 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24719 // Check LHS for vnot
24720 if (N0.getOpcode() == ISD::XOR &&
24721 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24722 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24723 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24725 // Check RHS for vnot
24726 if (N1.getOpcode() == ISD::XOR &&
24727 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24728 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24729 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24734 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24735 TargetLowering::DAGCombinerInfo &DCI,
24736 const X86Subtarget *Subtarget) {
24737 if (DCI.isBeforeLegalizeOps())
24740 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24743 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24746 SDValue N0 = N->getOperand(0);
24747 SDValue N1 = N->getOperand(1);
24748 EVT VT = N->getValueType(0);
24750 // look for psign/blend
24751 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24752 if (!Subtarget->hasSSSE3() ||
24753 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24756 // Canonicalize pandn to RHS
24757 if (N0.getOpcode() == X86ISD::ANDNP)
24759 // or (and (m, y), (pandn m, x))
24760 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24761 SDValue Mask = N1.getOperand(0);
24762 SDValue X = N1.getOperand(1);
24764 if (N0.getOperand(0) == Mask)
24765 Y = N0.getOperand(1);
24766 if (N0.getOperand(1) == Mask)
24767 Y = N0.getOperand(0);
24769 // Check to see if the mask appeared in both the AND and ANDNP and
24773 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24774 // Look through mask bitcast.
24775 if (Mask.getOpcode() == ISD::BITCAST)
24776 Mask = Mask.getOperand(0);
24777 if (X.getOpcode() == ISD::BITCAST)
24778 X = X.getOperand(0);
24779 if (Y.getOpcode() == ISD::BITCAST)
24780 Y = Y.getOperand(0);
24782 EVT MaskVT = Mask.getValueType();
24784 // Validate that the Mask operand is a vector sra node.
24785 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24786 // there is no psrai.b
24787 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24788 unsigned SraAmt = ~0;
24789 if (Mask.getOpcode() == ISD::SRA) {
24790 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24791 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24792 SraAmt = AmtConst->getZExtValue();
24793 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24794 SDValue SraC = Mask.getOperand(1);
24795 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24797 if ((SraAmt + 1) != EltBits)
24802 // Now we know we at least have a plendvb with the mask val. See if
24803 // we can form a psignb/w/d.
24804 // psign = x.type == y.type == mask.type && y = sub(0, x);
24805 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24806 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24807 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24808 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24809 "Unsupported VT for PSIGN");
24810 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24811 return DAG.getBitcast(VT, Mask);
24813 // PBLENDVB only available on SSE 4.1
24814 if (!Subtarget->hasSSE41())
24817 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24819 X = DAG.getBitcast(BlendVT, X);
24820 Y = DAG.getBitcast(BlendVT, Y);
24821 Mask = DAG.getBitcast(BlendVT, Mask);
24822 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24823 return DAG.getBitcast(VT, Mask);
24827 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24830 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24831 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24833 // SHLD/SHRD instructions have lower register pressure, but on some
24834 // platforms they have higher latency than the equivalent
24835 // series of shifts/or that would otherwise be generated.
24836 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24837 // have higher latencies and we are not optimizing for size.
24838 if (!OptForSize && Subtarget->isSHLDSlow())
24841 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24843 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24845 if (!N0.hasOneUse() || !N1.hasOneUse())
24848 SDValue ShAmt0 = N0.getOperand(1);
24849 if (ShAmt0.getValueType() != MVT::i8)
24851 SDValue ShAmt1 = N1.getOperand(1);
24852 if (ShAmt1.getValueType() != MVT::i8)
24854 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24855 ShAmt0 = ShAmt0.getOperand(0);
24856 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24857 ShAmt1 = ShAmt1.getOperand(0);
24860 unsigned Opc = X86ISD::SHLD;
24861 SDValue Op0 = N0.getOperand(0);
24862 SDValue Op1 = N1.getOperand(0);
24863 if (ShAmt0.getOpcode() == ISD::SUB) {
24864 Opc = X86ISD::SHRD;
24865 std::swap(Op0, Op1);
24866 std::swap(ShAmt0, ShAmt1);
24869 unsigned Bits = VT.getSizeInBits();
24870 if (ShAmt1.getOpcode() == ISD::SUB) {
24871 SDValue Sum = ShAmt1.getOperand(0);
24872 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24873 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24874 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24875 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24876 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24877 return DAG.getNode(Opc, DL, VT,
24879 DAG.getNode(ISD::TRUNCATE, DL,
24882 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24883 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24885 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24886 return DAG.getNode(Opc, DL, VT,
24887 N0.getOperand(0), N1.getOperand(0),
24888 DAG.getNode(ISD::TRUNCATE, DL,
24895 // Generate NEG and CMOV for integer abs.
24896 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24897 EVT VT = N->getValueType(0);
24899 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24900 // 8-bit integer abs to NEG and CMOV.
24901 if (VT.isInteger() && VT.getSizeInBits() == 8)
24904 SDValue N0 = N->getOperand(0);
24905 SDValue N1 = N->getOperand(1);
24908 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24909 // and change it to SUB and CMOV.
24910 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24911 N0.getOpcode() == ISD::ADD &&
24912 N0.getOperand(1) == N1 &&
24913 N1.getOpcode() == ISD::SRA &&
24914 N1.getOperand(0) == N0.getOperand(0))
24915 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24916 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24917 // Generate SUB & CMOV.
24918 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24919 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24921 SDValue Ops[] = { N0.getOperand(0), Neg,
24922 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24923 SDValue(Neg.getNode(), 1) };
24924 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24929 // Try to turn tests against the signbit in the form of:
24930 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24933 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24934 // This is only worth doing if the output type is i8.
24935 if (N->getValueType(0) != MVT::i8)
24938 SDValue N0 = N->getOperand(0);
24939 SDValue N1 = N->getOperand(1);
24941 // We should be performing an xor against a truncated shift.
24942 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24945 // Make sure we are performing an xor against one.
24946 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24949 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24950 SDValue Shift = N0.getOperand(0);
24951 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24954 // Make sure we are truncating from one of i16, i32 or i64.
24955 EVT ShiftTy = Shift.getValueType();
24956 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24959 // Make sure the shift amount extracts the sign bit.
24960 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24961 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24964 // Create a greater-than comparison against -1.
24965 // N.B. Using SETGE against 0 works but we want a canonical looking
24966 // comparison, using SETGT matches up with what TranslateX86CC.
24968 SDValue ShiftOp = Shift.getOperand(0);
24969 EVT ShiftOpTy = ShiftOp.getValueType();
24970 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24971 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24975 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24976 TargetLowering::DAGCombinerInfo &DCI,
24977 const X86Subtarget *Subtarget) {
24978 if (DCI.isBeforeLegalizeOps())
24981 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24984 if (Subtarget->hasCMov())
24985 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24988 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24994 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24995 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24996 TargetLowering::DAGCombinerInfo &DCI,
24997 const X86Subtarget *Subtarget) {
24998 LoadSDNode *Ld = cast<LoadSDNode>(N);
24999 EVT RegVT = Ld->getValueType(0);
25000 EVT MemVT = Ld->getMemoryVT();
25002 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25004 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25005 // into two 16-byte operations.
25006 ISD::LoadExtType Ext = Ld->getExtensionType();
25008 unsigned AddressSpace = Ld->getAddressSpace();
25009 unsigned Alignment = Ld->getAlignment();
25010 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25011 Ext == ISD::NON_EXTLOAD &&
25012 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25013 AddressSpace, Alignment, &Fast) && !Fast) {
25014 unsigned NumElems = RegVT.getVectorNumElements();
25018 SDValue Ptr = Ld->getBasePtr();
25019 SDValue Increment =
25020 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25022 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25024 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25025 Ld->getPointerInfo(), Ld->isVolatile(),
25026 Ld->isNonTemporal(), Ld->isInvariant(),
25028 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25029 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25030 Ld->getPointerInfo(), Ld->isVolatile(),
25031 Ld->isNonTemporal(), Ld->isInvariant(),
25032 std::min(16U, Alignment));
25033 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25035 Load2.getValue(1));
25037 SDValue NewVec = DAG.getUNDEF(RegVT);
25038 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25039 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25040 return DCI.CombineTo(N, NewVec, TF, true);
25046 /// PerformMLOADCombine - Resolve extending loads
25047 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25048 TargetLowering::DAGCombinerInfo &DCI,
25049 const X86Subtarget *Subtarget) {
25050 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25051 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25054 EVT VT = Mld->getValueType(0);
25055 unsigned NumElems = VT.getVectorNumElements();
25056 EVT LdVT = Mld->getMemoryVT();
25059 assert(LdVT != VT && "Cannot extend to the same type");
25060 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25061 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25062 // From, To sizes and ElemCount must be pow of two
25063 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25064 "Unexpected size for extending masked load");
25066 unsigned SizeRatio = ToSz / FromSz;
25067 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25069 // Create a type on which we perform the shuffle
25070 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25071 LdVT.getScalarType(), NumElems*SizeRatio);
25072 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25074 // Convert Src0 value
25075 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25076 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25077 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25078 for (unsigned i = 0; i != NumElems; ++i)
25079 ShuffleVec[i] = i * SizeRatio;
25081 // Can't shuffle using an illegal type.
25082 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25083 "WideVecVT should be legal");
25084 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25085 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25087 // Prepare the new mask
25089 SDValue Mask = Mld->getMask();
25090 if (Mask.getValueType() == VT) {
25091 // Mask and original value have the same type
25092 NewMask = DAG.getBitcast(WideVecVT, Mask);
25093 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25094 for (unsigned i = 0; i != NumElems; ++i)
25095 ShuffleVec[i] = i * SizeRatio;
25096 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25097 ShuffleVec[i] = NumElems*SizeRatio;
25098 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25099 DAG.getConstant(0, dl, WideVecVT),
25103 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25104 unsigned WidenNumElts = NumElems*SizeRatio;
25105 unsigned MaskNumElts = VT.getVectorNumElements();
25106 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25109 unsigned NumConcat = WidenNumElts / MaskNumElts;
25110 SmallVector<SDValue, 16> Ops(NumConcat);
25111 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25113 for (unsigned i = 1; i != NumConcat; ++i)
25116 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25119 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25120 Mld->getBasePtr(), NewMask, WideSrc0,
25121 Mld->getMemoryVT(), Mld->getMemOperand(),
25123 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25124 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25126 /// PerformMSTORECombine - Resolve truncating stores
25127 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25128 const X86Subtarget *Subtarget) {
25129 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25130 if (!Mst->isTruncatingStore())
25133 EVT VT = Mst->getValue().getValueType();
25134 unsigned NumElems = VT.getVectorNumElements();
25135 EVT StVT = Mst->getMemoryVT();
25138 assert(StVT != VT && "Cannot truncate to the same type");
25139 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25140 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25142 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25144 // The truncating store is legal in some cases. For example
25145 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25146 // are designated for truncate store.
25147 // In this case we don't need any further transformations.
25148 if (TLI.isTruncStoreLegal(VT, StVT))
25151 // From, To sizes and ElemCount must be pow of two
25152 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25153 "Unexpected size for truncating masked store");
25154 // We are going to use the original vector elt for storing.
25155 // Accumulated smaller vector elements must be a multiple of the store size.
25156 assert (((NumElems * FromSz) % ToSz) == 0 &&
25157 "Unexpected ratio for truncating masked store");
25159 unsigned SizeRatio = FromSz / ToSz;
25160 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25162 // Create a type on which we perform the shuffle
25163 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25164 StVT.getScalarType(), NumElems*SizeRatio);
25166 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25168 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25169 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25170 for (unsigned i = 0; i != NumElems; ++i)
25171 ShuffleVec[i] = i * SizeRatio;
25173 // Can't shuffle using an illegal type.
25174 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25175 "WideVecVT should be legal");
25177 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25178 DAG.getUNDEF(WideVecVT),
25182 SDValue Mask = Mst->getMask();
25183 if (Mask.getValueType() == VT) {
25184 // Mask and original value have the same type
25185 NewMask = DAG.getBitcast(WideVecVT, Mask);
25186 for (unsigned i = 0; i != NumElems; ++i)
25187 ShuffleVec[i] = i * SizeRatio;
25188 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25189 ShuffleVec[i] = NumElems*SizeRatio;
25190 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25191 DAG.getConstant(0, dl, WideVecVT),
25195 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25196 unsigned WidenNumElts = NumElems*SizeRatio;
25197 unsigned MaskNumElts = VT.getVectorNumElements();
25198 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25201 unsigned NumConcat = WidenNumElts / MaskNumElts;
25202 SmallVector<SDValue, 16> Ops(NumConcat);
25203 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25205 for (unsigned i = 1; i != NumConcat; ++i)
25208 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25211 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25212 NewMask, StVT, Mst->getMemOperand(), false);
25214 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25215 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25216 const X86Subtarget *Subtarget) {
25217 StoreSDNode *St = cast<StoreSDNode>(N);
25218 EVT VT = St->getValue().getValueType();
25219 EVT StVT = St->getMemoryVT();
25221 SDValue StoredVal = St->getOperand(1);
25222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25224 // If we are saving a concatenation of two XMM registers and 32-byte stores
25225 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25227 unsigned AddressSpace = St->getAddressSpace();
25228 unsigned Alignment = St->getAlignment();
25229 if (VT.is256BitVector() && StVT == VT &&
25230 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25231 AddressSpace, Alignment, &Fast) && !Fast) {
25232 unsigned NumElems = VT.getVectorNumElements();
25236 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25237 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25240 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25241 SDValue Ptr0 = St->getBasePtr();
25242 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25244 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25245 St->getPointerInfo(), St->isVolatile(),
25246 St->isNonTemporal(), Alignment);
25247 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25248 St->getPointerInfo(), St->isVolatile(),
25249 St->isNonTemporal(),
25250 std::min(16U, Alignment));
25251 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25254 // Optimize trunc store (of multiple scalars) to shuffle and store.
25255 // First, pack all of the elements in one place. Next, store to memory
25256 // in fewer chunks.
25257 if (St->isTruncatingStore() && VT.isVector()) {
25258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25259 unsigned NumElems = VT.getVectorNumElements();
25260 assert(StVT != VT && "Cannot truncate to the same type");
25261 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25262 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25264 // The truncating store is legal in some cases. For example
25265 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25266 // are designated for truncate store.
25267 // In this case we don't need any further transformations.
25268 if (TLI.isTruncStoreLegal(VT, StVT))
25271 // From, To sizes and ElemCount must be pow of two
25272 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25273 // We are going to use the original vector elt for storing.
25274 // Accumulated smaller vector elements must be a multiple of the store size.
25275 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25277 unsigned SizeRatio = FromSz / ToSz;
25279 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25281 // Create a type on which we perform the shuffle
25282 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25283 StVT.getScalarType(), NumElems*SizeRatio);
25285 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25287 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25288 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25289 for (unsigned i = 0; i != NumElems; ++i)
25290 ShuffleVec[i] = i * SizeRatio;
25292 // Can't shuffle using an illegal type.
25293 if (!TLI.isTypeLegal(WideVecVT))
25296 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25297 DAG.getUNDEF(WideVecVT),
25299 // At this point all of the data is stored at the bottom of the
25300 // register. We now need to save it to mem.
25302 // Find the largest store unit
25303 MVT StoreType = MVT::i8;
25304 for (MVT Tp : MVT::integer_valuetypes()) {
25305 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25309 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25310 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25311 (64 <= NumElems * ToSz))
25312 StoreType = MVT::f64;
25314 // Bitcast the original vector into a vector of store-size units
25315 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25316 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25317 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25318 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25319 SmallVector<SDValue, 8> Chains;
25320 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25321 TLI.getPointerTy(DAG.getDataLayout()));
25322 SDValue Ptr = St->getBasePtr();
25324 // Perform one or more big stores into memory.
25325 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25326 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25327 StoreType, ShuffWide,
25328 DAG.getIntPtrConstant(i, dl));
25329 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25330 St->getPointerInfo(), St->isVolatile(),
25331 St->isNonTemporal(), St->getAlignment());
25332 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25333 Chains.push_back(Ch);
25336 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25339 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25340 // the FP state in cases where an emms may be missing.
25341 // A preferable solution to the general problem is to figure out the right
25342 // places to insert EMMS. This qualifies as a quick hack.
25344 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25345 if (VT.getSizeInBits() != 64)
25348 const Function *F = DAG.getMachineFunction().getFunction();
25349 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25351 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25352 if ((VT.isVector() ||
25353 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25354 isa<LoadSDNode>(St->getValue()) &&
25355 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25356 St->getChain().hasOneUse() && !St->isVolatile()) {
25357 SDNode* LdVal = St->getValue().getNode();
25358 LoadSDNode *Ld = nullptr;
25359 int TokenFactorIndex = -1;
25360 SmallVector<SDValue, 8> Ops;
25361 SDNode* ChainVal = St->getChain().getNode();
25362 // Must be a store of a load. We currently handle two cases: the load
25363 // is a direct child, and it's under an intervening TokenFactor. It is
25364 // possible to dig deeper under nested TokenFactors.
25365 if (ChainVal == LdVal)
25366 Ld = cast<LoadSDNode>(St->getChain());
25367 else if (St->getValue().hasOneUse() &&
25368 ChainVal->getOpcode() == ISD::TokenFactor) {
25369 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25370 if (ChainVal->getOperand(i).getNode() == LdVal) {
25371 TokenFactorIndex = i;
25372 Ld = cast<LoadSDNode>(St->getValue());
25374 Ops.push_back(ChainVal->getOperand(i));
25378 if (!Ld || !ISD::isNormalLoad(Ld))
25381 // If this is not the MMX case, i.e. we are just turning i64 load/store
25382 // into f64 load/store, avoid the transformation if there are multiple
25383 // uses of the loaded value.
25384 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25389 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25390 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25392 if (Subtarget->is64Bit() || F64IsLegal) {
25393 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25394 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25395 Ld->getPointerInfo(), Ld->isVolatile(),
25396 Ld->isNonTemporal(), Ld->isInvariant(),
25397 Ld->getAlignment());
25398 SDValue NewChain = NewLd.getValue(1);
25399 if (TokenFactorIndex != -1) {
25400 Ops.push_back(NewChain);
25401 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25403 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25404 St->getPointerInfo(),
25405 St->isVolatile(), St->isNonTemporal(),
25406 St->getAlignment());
25409 // Otherwise, lower to two pairs of 32-bit loads / stores.
25410 SDValue LoAddr = Ld->getBasePtr();
25411 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25412 DAG.getConstant(4, LdDL, MVT::i32));
25414 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25415 Ld->getPointerInfo(),
25416 Ld->isVolatile(), Ld->isNonTemporal(),
25417 Ld->isInvariant(), Ld->getAlignment());
25418 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25419 Ld->getPointerInfo().getWithOffset(4),
25420 Ld->isVolatile(), Ld->isNonTemporal(),
25422 MinAlign(Ld->getAlignment(), 4));
25424 SDValue NewChain = LoLd.getValue(1);
25425 if (TokenFactorIndex != -1) {
25426 Ops.push_back(LoLd);
25427 Ops.push_back(HiLd);
25428 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25431 LoAddr = St->getBasePtr();
25432 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25433 DAG.getConstant(4, StDL, MVT::i32));
25435 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25436 St->getPointerInfo(),
25437 St->isVolatile(), St->isNonTemporal(),
25438 St->getAlignment());
25439 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25440 St->getPointerInfo().getWithOffset(4),
25442 St->isNonTemporal(),
25443 MinAlign(St->getAlignment(), 4));
25444 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25447 // This is similar to the above case, but here we handle a scalar 64-bit
25448 // integer store that is extracted from a vector on a 32-bit target.
25449 // If we have SSE2, then we can treat it like a floating-point double
25450 // to get past legalization. The execution dependencies fixup pass will
25451 // choose the optimal machine instruction for the store if this really is
25452 // an integer or v2f32 rather than an f64.
25453 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25454 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25455 SDValue OldExtract = St->getOperand(1);
25456 SDValue ExtOp0 = OldExtract.getOperand(0);
25457 unsigned VecSize = ExtOp0.getValueSizeInBits();
25458 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25459 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25460 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25461 BitCast, OldExtract.getOperand(1));
25462 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25463 St->getPointerInfo(), St->isVolatile(),
25464 St->isNonTemporal(), St->getAlignment());
25470 /// Return 'true' if this vector operation is "horizontal"
25471 /// and return the operands for the horizontal operation in LHS and RHS. A
25472 /// horizontal operation performs the binary operation on successive elements
25473 /// of its first operand, then on successive elements of its second operand,
25474 /// returning the resulting values in a vector. For example, if
25475 /// A = < float a0, float a1, float a2, float a3 >
25477 /// B = < float b0, float b1, float b2, float b3 >
25478 /// then the result of doing a horizontal operation on A and B is
25479 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25480 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25481 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25482 /// set to A, RHS to B, and the routine returns 'true'.
25483 /// Note that the binary operation should have the property that if one of the
25484 /// operands is UNDEF then the result is UNDEF.
25485 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25486 // Look for the following pattern: if
25487 // A = < float a0, float a1, float a2, float a3 >
25488 // B = < float b0, float b1, float b2, float b3 >
25490 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25491 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25492 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25493 // which is A horizontal-op B.
25495 // At least one of the operands should be a vector shuffle.
25496 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25497 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25500 MVT VT = LHS.getSimpleValueType();
25502 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25503 "Unsupported vector type for horizontal add/sub");
25505 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25506 // operate independently on 128-bit lanes.
25507 unsigned NumElts = VT.getVectorNumElements();
25508 unsigned NumLanes = VT.getSizeInBits()/128;
25509 unsigned NumLaneElts = NumElts / NumLanes;
25510 assert((NumLaneElts % 2 == 0) &&
25511 "Vector type should have an even number of elements in each lane");
25512 unsigned HalfLaneElts = NumLaneElts/2;
25514 // View LHS in the form
25515 // LHS = VECTOR_SHUFFLE A, B, LMask
25516 // If LHS is not a shuffle then pretend it is the shuffle
25517 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25518 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25521 SmallVector<int, 16> LMask(NumElts);
25522 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25523 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25524 A = LHS.getOperand(0);
25525 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25526 B = LHS.getOperand(1);
25527 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25528 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25530 if (LHS.getOpcode() != ISD::UNDEF)
25532 for (unsigned i = 0; i != NumElts; ++i)
25536 // Likewise, view RHS in the form
25537 // RHS = VECTOR_SHUFFLE C, D, RMask
25539 SmallVector<int, 16> RMask(NumElts);
25540 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25541 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25542 C = RHS.getOperand(0);
25543 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25544 D = RHS.getOperand(1);
25545 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25546 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25548 if (RHS.getOpcode() != ISD::UNDEF)
25550 for (unsigned i = 0; i != NumElts; ++i)
25554 // Check that the shuffles are both shuffling the same vectors.
25555 if (!(A == C && B == D) && !(A == D && B == C))
25558 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25559 if (!A.getNode() && !B.getNode())
25562 // If A and B occur in reverse order in RHS, then "swap" them (which means
25563 // rewriting the mask).
25565 ShuffleVectorSDNode::commuteMask(RMask);
25567 // At this point LHS and RHS are equivalent to
25568 // LHS = VECTOR_SHUFFLE A, B, LMask
25569 // RHS = VECTOR_SHUFFLE A, B, RMask
25570 // Check that the masks correspond to performing a horizontal operation.
25571 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25572 for (unsigned i = 0; i != NumLaneElts; ++i) {
25573 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25575 // Ignore any UNDEF components.
25576 if (LIdx < 0 || RIdx < 0 ||
25577 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25578 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25581 // Check that successive elements are being operated on. If not, this is
25582 // not a horizontal operation.
25583 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25584 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25585 if (!(LIdx == Index && RIdx == Index + 1) &&
25586 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25591 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25592 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25596 /// Do target-specific dag combines on floating point adds.
25597 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25598 const X86Subtarget *Subtarget) {
25599 EVT VT = N->getValueType(0);
25600 SDValue LHS = N->getOperand(0);
25601 SDValue RHS = N->getOperand(1);
25603 // Try to synthesize horizontal adds from adds of shuffles.
25604 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25605 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25606 isHorizontalBinOp(LHS, RHS, true))
25607 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25611 /// Do target-specific dag combines on floating point subs.
25612 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25613 const X86Subtarget *Subtarget) {
25614 EVT VT = N->getValueType(0);
25615 SDValue LHS = N->getOperand(0);
25616 SDValue RHS = N->getOperand(1);
25618 // Try to synthesize horizontal subs from subs of shuffles.
25619 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25620 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25621 isHorizontalBinOp(LHS, RHS, false))
25622 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25626 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25627 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25628 const X86Subtarget *Subtarget) {
25629 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25631 // F[X]OR(0.0, x) -> x
25632 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25633 if (C->getValueAPF().isPosZero())
25634 return N->getOperand(1);
25636 // F[X]OR(x, 0.0) -> x
25637 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25638 if (C->getValueAPF().isPosZero())
25639 return N->getOperand(0);
25641 EVT VT = N->getValueType(0);
25642 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25644 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25645 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25647 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25648 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25649 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25650 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25651 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25656 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25657 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25658 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25660 // Only perform optimizations if UnsafeMath is used.
25661 if (!DAG.getTarget().Options.UnsafeFPMath)
25664 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25665 // into FMINC and FMAXC, which are Commutative operations.
25666 unsigned NewOp = 0;
25667 switch (N->getOpcode()) {
25668 default: llvm_unreachable("unknown opcode");
25669 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25670 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25673 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25674 N->getOperand(0), N->getOperand(1));
25677 /// Do target-specific dag combines on X86ISD::FAND nodes.
25678 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25679 // FAND(0.0, x) -> 0.0
25680 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25681 if (C->getValueAPF().isPosZero())
25682 return N->getOperand(0);
25684 // FAND(x, 0.0) -> 0.0
25685 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25686 if (C->getValueAPF().isPosZero())
25687 return N->getOperand(1);
25692 /// Do target-specific dag combines on X86ISD::FANDN nodes
25693 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25694 // FANDN(0.0, x) -> x
25695 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25696 if (C->getValueAPF().isPosZero())
25697 return N->getOperand(1);
25699 // FANDN(x, 0.0) -> 0.0
25700 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25701 if (C->getValueAPF().isPosZero())
25702 return N->getOperand(1);
25707 static SDValue PerformBTCombine(SDNode *N,
25709 TargetLowering::DAGCombinerInfo &DCI) {
25710 // BT ignores high bits in the bit index operand.
25711 SDValue Op1 = N->getOperand(1);
25712 if (Op1.hasOneUse()) {
25713 unsigned BitWidth = Op1.getValueSizeInBits();
25714 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25715 APInt KnownZero, KnownOne;
25716 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25717 !DCI.isBeforeLegalizeOps());
25718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25719 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25720 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25721 DCI.CommitTargetLoweringOpt(TLO);
25726 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25727 SDValue Op = N->getOperand(0);
25728 if (Op.getOpcode() == ISD::BITCAST)
25729 Op = Op.getOperand(0);
25730 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25731 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25732 VT.getVectorElementType().getSizeInBits() ==
25733 OpVT.getVectorElementType().getSizeInBits()) {
25734 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25739 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25740 const X86Subtarget *Subtarget) {
25741 EVT VT = N->getValueType(0);
25742 if (!VT.isVector())
25745 SDValue N0 = N->getOperand(0);
25746 SDValue N1 = N->getOperand(1);
25747 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25750 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25751 // both SSE and AVX2 since there is no sign-extended shift right
25752 // operation on a vector with 64-bit elements.
25753 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25754 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25755 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25756 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25757 SDValue N00 = N0.getOperand(0);
25759 // EXTLOAD has a better solution on AVX2,
25760 // it may be replaced with X86ISD::VSEXT node.
25761 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25762 if (!ISD::isNormalLoad(N00.getNode()))
25765 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25766 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25768 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25774 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25775 TargetLowering::DAGCombinerInfo &DCI,
25776 const X86Subtarget *Subtarget) {
25777 SDValue N0 = N->getOperand(0);
25778 EVT VT = N->getValueType(0);
25779 EVT SVT = VT.getScalarType();
25780 EVT InVT = N0.getValueType();
25781 EVT InSVT = InVT.getScalarType();
25784 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25785 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25786 // This exposes the sext to the sdivrem lowering, so that it directly extends
25787 // from AH (which we otherwise need to do contortions to access).
25788 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25789 InVT == MVT::i8 && VT == MVT::i32) {
25790 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25791 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25792 N0.getOperand(0), N0.getOperand(1));
25793 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25794 return R.getValue(1);
25797 if (!DCI.isBeforeLegalizeOps()) {
25798 if (InVT == MVT::i1) {
25799 SDValue Zero = DAG.getConstant(0, DL, VT);
25801 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25802 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25807 if (VT.isVector() && Subtarget->hasSSE2()) {
25808 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25809 EVT InVT = N.getValueType();
25810 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25811 Size / InVT.getScalarSizeInBits());
25812 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25813 DAG.getUNDEF(InVT));
25815 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25818 // If target-size is less than 128-bits, extend to a type that would extend
25819 // to 128 bits, extend that and extract the original target vector.
25820 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25821 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25822 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25823 unsigned Scale = 128 / VT.getSizeInBits();
25825 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25826 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25827 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25828 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25829 DAG.getIntPtrConstant(0, DL));
25832 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25833 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25834 if (VT.getSizeInBits() == 128 &&
25835 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25836 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25837 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25838 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25841 // On pre-AVX2 targets, split into 128-bit nodes of
25842 // ISD::SIGN_EXTEND_VECTOR_INREG.
25843 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25844 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25845 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25846 unsigned NumVecs = VT.getSizeInBits() / 128;
25847 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25848 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25849 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25851 SmallVector<SDValue, 8> Opnds;
25852 for (unsigned i = 0, Offset = 0; i != NumVecs;
25853 ++i, Offset += NumSubElts) {
25854 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25855 DAG.getIntPtrConstant(Offset, DL));
25856 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25857 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25858 Opnds.push_back(SrcVec);
25860 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25864 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
25865 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25871 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25872 const X86Subtarget* Subtarget) {
25874 EVT VT = N->getValueType(0);
25876 // Let legalize expand this if it isn't a legal type yet.
25877 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25880 EVT ScalarVT = VT.getScalarType();
25881 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25882 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25883 !Subtarget->hasAVX512()))
25886 SDValue A = N->getOperand(0);
25887 SDValue B = N->getOperand(1);
25888 SDValue C = N->getOperand(2);
25890 bool NegA = (A.getOpcode() == ISD::FNEG);
25891 bool NegB = (B.getOpcode() == ISD::FNEG);
25892 bool NegC = (C.getOpcode() == ISD::FNEG);
25894 // Negative multiplication when NegA xor NegB
25895 bool NegMul = (NegA != NegB);
25897 A = A.getOperand(0);
25899 B = B.getOperand(0);
25901 C = C.getOperand(0);
25905 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25907 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25909 return DAG.getNode(Opcode, dl, VT, A, B, C);
25912 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25913 TargetLowering::DAGCombinerInfo &DCI,
25914 const X86Subtarget *Subtarget) {
25915 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25916 // (and (i32 x86isd::setcc_carry), 1)
25917 // This eliminates the zext. This transformation is necessary because
25918 // ISD::SETCC is always legalized to i8.
25920 SDValue N0 = N->getOperand(0);
25921 EVT VT = N->getValueType(0);
25923 if (N0.getOpcode() == ISD::AND &&
25925 N0.getOperand(0).hasOneUse()) {
25926 SDValue N00 = N0.getOperand(0);
25927 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25928 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25929 if (!C || C->getZExtValue() != 1)
25931 return DAG.getNode(ISD::AND, dl, VT,
25932 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25933 N00.getOperand(0), N00.getOperand(1)),
25934 DAG.getConstant(1, dl, VT));
25938 if (N0.getOpcode() == ISD::TRUNCATE &&
25940 N0.getOperand(0).hasOneUse()) {
25941 SDValue N00 = N0.getOperand(0);
25942 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25943 return DAG.getNode(ISD::AND, dl, VT,
25944 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25945 N00.getOperand(0), N00.getOperand(1)),
25946 DAG.getConstant(1, dl, VT));
25950 if (VT.is256BitVector())
25951 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25954 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25955 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25956 // This exposes the zext to the udivrem lowering, so that it directly extends
25957 // from AH (which we otherwise need to do contortions to access).
25958 if (N0.getOpcode() == ISD::UDIVREM &&
25959 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25960 (VT == MVT::i32 || VT == MVT::i64)) {
25961 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25962 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25963 N0.getOperand(0), N0.getOperand(1));
25964 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25965 return R.getValue(1);
25971 // Optimize x == -y --> x+y == 0
25972 // x != -y --> x+y != 0
25973 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25974 const X86Subtarget* Subtarget) {
25975 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25976 SDValue LHS = N->getOperand(0);
25977 SDValue RHS = N->getOperand(1);
25978 EVT VT = N->getValueType(0);
25981 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25982 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25983 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25984 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25985 LHS.getOperand(1));
25986 return DAG.getSetCC(DL, N->getValueType(0), addV,
25987 DAG.getConstant(0, DL, addV.getValueType()), CC);
25989 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25991 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25992 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25993 RHS.getOperand(1));
25994 return DAG.getSetCC(DL, N->getValueType(0), addV,
25995 DAG.getConstant(0, DL, addV.getValueType()), CC);
25998 if (VT.getScalarType() == MVT::i1 &&
25999 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26001 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26002 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26003 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26005 if (!IsSEXT0 || !IsVZero1) {
26006 // Swap the operands and update the condition code.
26007 std::swap(LHS, RHS);
26008 CC = ISD::getSetCCSwappedOperands(CC);
26010 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26011 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26012 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26015 if (IsSEXT0 && IsVZero1) {
26016 assert(VT == LHS.getOperand(0).getValueType() &&
26017 "Uexpected operand type");
26018 if (CC == ISD::SETGT)
26019 return DAG.getConstant(0, DL, VT);
26020 if (CC == ISD::SETLE)
26021 return DAG.getConstant(1, DL, VT);
26022 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26023 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26025 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26026 "Unexpected condition code!");
26027 return LHS.getOperand(0);
26034 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
26035 SelectionDAG &DAG) {
26037 MVT VT = Load->getSimpleValueType(0);
26038 MVT EVT = VT.getVectorElementType();
26039 SDValue Addr = Load->getOperand(1);
26040 SDValue NewAddr = DAG.getNode(
26041 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
26042 DAG.getConstant(Index * EVT.getStoreSize(), dl,
26043 Addr.getSimpleValueType()));
26046 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
26047 DAG.getMachineFunction().getMachineMemOperand(
26048 Load->getMemOperand(), 0, EVT.getStoreSize()));
26052 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26053 const X86Subtarget *Subtarget) {
26055 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26056 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26057 "X86insertps is only defined for v4x32");
26059 SDValue Ld = N->getOperand(1);
26060 if (MayFoldLoad(Ld)) {
26061 // Extract the countS bits from the immediate so we can get the proper
26062 // address when narrowing the vector load to a specific element.
26063 // When the second source op is a memory address, insertps doesn't use
26064 // countS and just gets an f32 from that address.
26065 unsigned DestIndex =
26066 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26068 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26070 // Create this as a scalar to vector to match the instruction pattern.
26071 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26072 // countS bits are ignored when loading from memory on insertps, which
26073 // means we don't need to explicitly set them to 0.
26074 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26075 LoadScalarToVector, N->getOperand(2));
26080 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26081 SDValue V0 = N->getOperand(0);
26082 SDValue V1 = N->getOperand(1);
26084 EVT VT = N->getValueType(0);
26086 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26087 // operands and changing the mask to 1. This saves us a bunch of
26088 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26089 // x86InstrInfo knows how to commute this back after instruction selection
26090 // if it would help register allocation.
26092 // TODO: If optimizing for size or a processor that doesn't suffer from
26093 // partial register update stalls, this should be transformed into a MOVSD
26094 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26096 if (VT == MVT::v2f64)
26097 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26098 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26099 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26100 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26106 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26107 // as "sbb reg,reg", since it can be extended without zext and produces
26108 // an all-ones bit which is more useful than 0/1 in some cases.
26109 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26112 return DAG.getNode(ISD::AND, DL, VT,
26113 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26114 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26116 DAG.getConstant(1, DL, VT));
26117 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26118 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26119 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26120 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26124 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26125 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26126 TargetLowering::DAGCombinerInfo &DCI,
26127 const X86Subtarget *Subtarget) {
26129 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26130 SDValue EFLAGS = N->getOperand(1);
26132 if (CC == X86::COND_A) {
26133 // Try to convert COND_A into COND_B in an attempt to facilitate
26134 // materializing "setb reg".
26136 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26137 // cannot take an immediate as its first operand.
26139 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26140 EFLAGS.getValueType().isInteger() &&
26141 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26142 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26143 EFLAGS.getNode()->getVTList(),
26144 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26145 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26146 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26150 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26151 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26153 if (CC == X86::COND_B)
26154 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26156 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26157 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26158 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26164 // Optimize branch condition evaluation.
26166 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26167 TargetLowering::DAGCombinerInfo &DCI,
26168 const X86Subtarget *Subtarget) {
26170 SDValue Chain = N->getOperand(0);
26171 SDValue Dest = N->getOperand(1);
26172 SDValue EFLAGS = N->getOperand(3);
26173 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26175 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26176 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26177 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26184 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26185 SelectionDAG &DAG) {
26186 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26187 // optimize away operation when it's from a constant.
26189 // The general transformation is:
26190 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26191 // AND(VECTOR_CMP(x,y), constant2)
26192 // constant2 = UNARYOP(constant)
26194 // Early exit if this isn't a vector operation, the operand of the
26195 // unary operation isn't a bitwise AND, or if the sizes of the operations
26196 // aren't the same.
26197 EVT VT = N->getValueType(0);
26198 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26199 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26200 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26203 // Now check that the other operand of the AND is a constant. We could
26204 // make the transformation for non-constant splats as well, but it's unclear
26205 // that would be a benefit as it would not eliminate any operations, just
26206 // perform one more step in scalar code before moving to the vector unit.
26207 if (BuildVectorSDNode *BV =
26208 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26209 // Bail out if the vector isn't a constant.
26210 if (!BV->isConstant())
26213 // Everything checks out. Build up the new and improved node.
26215 EVT IntVT = BV->getValueType(0);
26216 // Create a new constant of the appropriate type for the transformed
26218 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26219 // The AND node needs bitcasts to/from an integer vector type around it.
26220 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26221 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26222 N->getOperand(0)->getOperand(0), MaskConst);
26223 SDValue Res = DAG.getBitcast(VT, NewAnd);
26230 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26231 const X86Subtarget *Subtarget) {
26232 SDValue Op0 = N->getOperand(0);
26233 EVT VT = N->getValueType(0);
26234 EVT InVT = Op0.getValueType();
26235 EVT InSVT = InVT.getScalarType();
26236 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26238 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26239 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26240 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26242 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26243 InVT.getVectorNumElements());
26244 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26246 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26247 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26249 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26255 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26256 const X86Subtarget *Subtarget) {
26257 // First try to optimize away the conversion entirely when it's
26258 // conditionally from a constant. Vectors only.
26259 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26262 // Now move on to more general possibilities.
26263 SDValue Op0 = N->getOperand(0);
26264 EVT VT = N->getValueType(0);
26265 EVT InVT = Op0.getValueType();
26266 EVT InSVT = InVT.getScalarType();
26268 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26269 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26270 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26272 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26273 InVT.getVectorNumElements());
26274 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26275 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26278 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26279 // a 32-bit target where SSE doesn't support i64->FP operations.
26280 if (Op0.getOpcode() == ISD::LOAD) {
26281 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26282 EVT LdVT = Ld->getValueType(0);
26284 // This transformation is not supported if the result type is f16
26285 if (VT == MVT::f16)
26288 if (!Ld->isVolatile() && !VT.isVector() &&
26289 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26290 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26291 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26292 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26293 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26300 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26301 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26302 X86TargetLowering::DAGCombinerInfo &DCI) {
26303 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26304 // the result is either zero or one (depending on the input carry bit).
26305 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26306 if (X86::isZeroNode(N->getOperand(0)) &&
26307 X86::isZeroNode(N->getOperand(1)) &&
26308 // We don't have a good way to replace an EFLAGS use, so only do this when
26310 SDValue(N, 1).use_empty()) {
26312 EVT VT = N->getValueType(0);
26313 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26314 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26315 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26316 DAG.getConstant(X86::COND_B, DL,
26319 DAG.getConstant(1, DL, VT));
26320 return DCI.CombineTo(N, Res1, CarryOut);
26326 // fold (add Y, (sete X, 0)) -> adc 0, Y
26327 // (add Y, (setne X, 0)) -> sbb -1, Y
26328 // (sub (sete X, 0), Y) -> sbb 0, Y
26329 // (sub (setne X, 0), Y) -> adc -1, Y
26330 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26333 // Look through ZExts.
26334 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26335 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26338 SDValue SetCC = Ext.getOperand(0);
26339 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26342 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26343 if (CC != X86::COND_E && CC != X86::COND_NE)
26346 SDValue Cmp = SetCC.getOperand(1);
26347 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26348 !X86::isZeroNode(Cmp.getOperand(1)) ||
26349 !Cmp.getOperand(0).getValueType().isInteger())
26352 SDValue CmpOp0 = Cmp.getOperand(0);
26353 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26354 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26356 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26357 if (CC == X86::COND_NE)
26358 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26359 DL, OtherVal.getValueType(), OtherVal,
26360 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26362 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26363 DL, OtherVal.getValueType(), OtherVal,
26364 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26367 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26368 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26369 const X86Subtarget *Subtarget) {
26370 EVT VT = N->getValueType(0);
26371 SDValue Op0 = N->getOperand(0);
26372 SDValue Op1 = N->getOperand(1);
26374 // Try to synthesize horizontal adds from adds of shuffles.
26375 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26376 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26377 isHorizontalBinOp(Op0, Op1, true))
26378 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26380 return OptimizeConditionalInDecrement(N, DAG);
26383 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26384 const X86Subtarget *Subtarget) {
26385 SDValue Op0 = N->getOperand(0);
26386 SDValue Op1 = N->getOperand(1);
26388 // X86 can't encode an immediate LHS of a sub. See if we can push the
26389 // negation into a preceding instruction.
26390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26391 // If the RHS of the sub is a XOR with one use and a constant, invert the
26392 // immediate. Then add one to the LHS of the sub so we can turn
26393 // X-Y -> X+~Y+1, saving one register.
26394 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26395 isa<ConstantSDNode>(Op1.getOperand(1))) {
26396 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26397 EVT VT = Op0.getValueType();
26398 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26400 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26401 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26402 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26406 // Try to synthesize horizontal adds from adds of shuffles.
26407 EVT VT = N->getValueType(0);
26408 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26409 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26410 isHorizontalBinOp(Op0, Op1, true))
26411 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26413 return OptimizeConditionalInDecrement(N, DAG);
26416 /// performVZEXTCombine - Performs build vector combines
26417 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26418 TargetLowering::DAGCombinerInfo &DCI,
26419 const X86Subtarget *Subtarget) {
26421 MVT VT = N->getSimpleValueType(0);
26422 SDValue Op = N->getOperand(0);
26423 MVT OpVT = Op.getSimpleValueType();
26424 MVT OpEltVT = OpVT.getVectorElementType();
26425 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26427 // (vzext (bitcast (vzext (x)) -> (vzext x)
26429 while (V.getOpcode() == ISD::BITCAST)
26430 V = V.getOperand(0);
26432 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26433 MVT InnerVT = V.getSimpleValueType();
26434 MVT InnerEltVT = InnerVT.getVectorElementType();
26436 // If the element sizes match exactly, we can just do one larger vzext. This
26437 // is always an exact type match as vzext operates on integer types.
26438 if (OpEltVT == InnerEltVT) {
26439 assert(OpVT == InnerVT && "Types must match for vzext!");
26440 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26443 // The only other way we can combine them is if only a single element of the
26444 // inner vzext is used in the input to the outer vzext.
26445 if (InnerEltVT.getSizeInBits() < InputBits)
26448 // In this case, the inner vzext is completely dead because we're going to
26449 // only look at bits inside of the low element. Just do the outer vzext on
26450 // a bitcast of the input to the inner.
26451 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26454 // Check if we can bypass extracting and re-inserting an element of an input
26455 // vector. Essentially:
26456 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26457 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26458 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26459 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26460 SDValue ExtractedV = V.getOperand(0);
26461 SDValue OrigV = ExtractedV.getOperand(0);
26462 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26463 if (ExtractIdx->getZExtValue() == 0) {
26464 MVT OrigVT = OrigV.getSimpleValueType();
26465 // Extract a subvector if necessary...
26466 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26467 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26468 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26469 OrigVT.getVectorNumElements() / Ratio);
26470 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26471 DAG.getIntPtrConstant(0, DL));
26473 Op = DAG.getBitcast(OpVT, OrigV);
26474 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26481 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26482 DAGCombinerInfo &DCI) const {
26483 SelectionDAG &DAG = DCI.DAG;
26484 switch (N->getOpcode()) {
26486 case ISD::EXTRACT_VECTOR_ELT:
26487 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26490 case X86ISD::SHRUNKBLEND:
26491 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26492 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26493 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26494 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26495 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26496 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26497 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26500 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26501 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26502 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26503 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26504 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26505 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26506 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26507 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26508 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26509 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26510 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26511 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26513 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26515 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26516 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26517 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26518 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26519 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26520 case ISD::ANY_EXTEND:
26521 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26522 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26523 case ISD::SIGN_EXTEND_INREG:
26524 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26525 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26526 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26527 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26528 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26529 case X86ISD::SHUFP: // Handle all target specific shuffles
26530 case X86ISD::PALIGNR:
26531 case X86ISD::UNPCKH:
26532 case X86ISD::UNPCKL:
26533 case X86ISD::MOVHLPS:
26534 case X86ISD::MOVLHPS:
26535 case X86ISD::PSHUFB:
26536 case X86ISD::PSHUFD:
26537 case X86ISD::PSHUFHW:
26538 case X86ISD::PSHUFLW:
26539 case X86ISD::MOVSS:
26540 case X86ISD::MOVSD:
26541 case X86ISD::VPERMILPI:
26542 case X86ISD::VPERM2X128:
26543 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26544 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26545 case X86ISD::INSERTPS: {
26546 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26547 return PerformINSERTPSCombine(N, DAG, Subtarget);
26550 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26556 /// isTypeDesirableForOp - Return true if the target has native support for
26557 /// the specified value type and it is 'desirable' to use the type for the
26558 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26559 /// instruction encodings are longer and some i16 instructions are slow.
26560 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26561 if (!isTypeLegal(VT))
26563 if (VT != MVT::i16)
26570 case ISD::SIGN_EXTEND:
26571 case ISD::ZERO_EXTEND:
26572 case ISD::ANY_EXTEND:
26585 /// IsDesirableToPromoteOp - This method query the target whether it is
26586 /// beneficial for dag combiner to promote the specified node. If true, it
26587 /// should return the desired promotion type by reference.
26588 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26589 EVT VT = Op.getValueType();
26590 if (VT != MVT::i16)
26593 bool Promote = false;
26594 bool Commute = false;
26595 switch (Op.getOpcode()) {
26598 LoadSDNode *LD = cast<LoadSDNode>(Op);
26599 // If the non-extending load has a single use and it's not live out, then it
26600 // might be folded.
26601 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26602 Op.hasOneUse()*/) {
26603 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26604 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26605 // The only case where we'd want to promote LOAD (rather then it being
26606 // promoted as an operand is when it's only use is liveout.
26607 if (UI->getOpcode() != ISD::CopyToReg)
26614 case ISD::SIGN_EXTEND:
26615 case ISD::ZERO_EXTEND:
26616 case ISD::ANY_EXTEND:
26621 SDValue N0 = Op.getOperand(0);
26622 // Look out for (store (shl (load), x)).
26623 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26636 SDValue N0 = Op.getOperand(0);
26637 SDValue N1 = Op.getOperand(1);
26638 if (!Commute && MayFoldLoad(N1))
26640 // Avoid disabling potential load folding opportunities.
26641 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26643 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26653 //===----------------------------------------------------------------------===//
26654 // X86 Inline Assembly Support
26655 //===----------------------------------------------------------------------===//
26657 // Helper to match a string separated by whitespace.
26658 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26659 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26661 for (StringRef Piece : Pieces) {
26662 if (!S.startswith(Piece)) // Check if the piece matches.
26665 S = S.substr(Piece.size());
26666 StringRef::size_type Pos = S.find_first_not_of(" \t");
26667 if (Pos == 0) // We matched a prefix.
26676 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26678 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26679 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26680 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26681 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26683 if (AsmPieces.size() == 3)
26685 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26692 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26693 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26695 std::string AsmStr = IA->getAsmString();
26697 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26698 if (!Ty || Ty->getBitWidth() % 16 != 0)
26701 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26702 SmallVector<StringRef, 4> AsmPieces;
26703 SplitString(AsmStr, AsmPieces, ";\n");
26705 switch (AsmPieces.size()) {
26706 default: return false;
26708 // FIXME: this should verify that we are targeting a 486 or better. If not,
26709 // we will turn this bswap into something that will be lowered to logical
26710 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26711 // lower so don't worry about this.
26713 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26714 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26715 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26716 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26717 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26718 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26719 // No need to check constraints, nothing other than the equivalent of
26720 // "=r,0" would be valid here.
26721 return IntrinsicLowering::LowerToByteSwap(CI);
26724 // rorw $$8, ${0:w} --> llvm.bswap.i16
26725 if (CI->getType()->isIntegerTy(16) &&
26726 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26727 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26728 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26730 StringRef ConstraintsStr = IA->getConstraintString();
26731 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26732 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26733 if (clobbersFlagRegisters(AsmPieces))
26734 return IntrinsicLowering::LowerToByteSwap(CI);
26738 if (CI->getType()->isIntegerTy(32) &&
26739 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26740 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26741 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26742 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26744 StringRef ConstraintsStr = IA->getConstraintString();
26745 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26746 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26747 if (clobbersFlagRegisters(AsmPieces))
26748 return IntrinsicLowering::LowerToByteSwap(CI);
26751 if (CI->getType()->isIntegerTy(64)) {
26752 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26753 if (Constraints.size() >= 2 &&
26754 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26755 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26756 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26757 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26758 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26759 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26760 return IntrinsicLowering::LowerToByteSwap(CI);
26768 /// getConstraintType - Given a constraint letter, return the type of
26769 /// constraint it is for this target.
26770 X86TargetLowering::ConstraintType
26771 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26772 if (Constraint.size() == 1) {
26773 switch (Constraint[0]) {
26784 return C_RegisterClass;
26808 return TargetLowering::getConstraintType(Constraint);
26811 /// Examine constraint type and operand type and determine a weight value.
26812 /// This object must already have been set up with the operand type
26813 /// and the current alternative constraint selected.
26814 TargetLowering::ConstraintWeight
26815 X86TargetLowering::getSingleConstraintMatchWeight(
26816 AsmOperandInfo &info, const char *constraint) const {
26817 ConstraintWeight weight = CW_Invalid;
26818 Value *CallOperandVal = info.CallOperandVal;
26819 // If we don't have a value, we can't do a match,
26820 // but allow it at the lowest weight.
26821 if (!CallOperandVal)
26823 Type *type = CallOperandVal->getType();
26824 // Look at the constraint type.
26825 switch (*constraint) {
26827 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26838 if (CallOperandVal->getType()->isIntegerTy())
26839 weight = CW_SpecificReg;
26844 if (type->isFloatingPointTy())
26845 weight = CW_SpecificReg;
26848 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26849 weight = CW_SpecificReg;
26853 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26854 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26855 weight = CW_Register;
26858 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26859 if (C->getZExtValue() <= 31)
26860 weight = CW_Constant;
26864 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26865 if (C->getZExtValue() <= 63)
26866 weight = CW_Constant;
26870 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26871 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26872 weight = CW_Constant;
26876 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26877 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26878 weight = CW_Constant;
26882 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26883 if (C->getZExtValue() <= 3)
26884 weight = CW_Constant;
26888 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26889 if (C->getZExtValue() <= 0xff)
26890 weight = CW_Constant;
26895 if (isa<ConstantFP>(CallOperandVal)) {
26896 weight = CW_Constant;
26900 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26901 if ((C->getSExtValue() >= -0x80000000LL) &&
26902 (C->getSExtValue() <= 0x7fffffffLL))
26903 weight = CW_Constant;
26907 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26908 if (C->getZExtValue() <= 0xffffffff)
26909 weight = CW_Constant;
26916 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26917 /// with another that has more specific requirements based on the type of the
26918 /// corresponding operand.
26919 const char *X86TargetLowering::
26920 LowerXConstraint(EVT ConstraintVT) const {
26921 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26922 // 'f' like normal targets.
26923 if (ConstraintVT.isFloatingPoint()) {
26924 if (Subtarget->hasSSE2())
26926 if (Subtarget->hasSSE1())
26930 return TargetLowering::LowerXConstraint(ConstraintVT);
26933 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26934 /// vector. If it is invalid, don't add anything to Ops.
26935 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26936 std::string &Constraint,
26937 std::vector<SDValue>&Ops,
26938 SelectionDAG &DAG) const {
26941 // Only support length 1 constraints for now.
26942 if (Constraint.length() > 1) return;
26944 char ConstraintLetter = Constraint[0];
26945 switch (ConstraintLetter) {
26948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26949 if (C->getZExtValue() <= 31) {
26950 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26951 Op.getValueType());
26957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26958 if (C->getZExtValue() <= 63) {
26959 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26960 Op.getValueType());
26966 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26967 if (isInt<8>(C->getSExtValue())) {
26968 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26969 Op.getValueType());
26975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26976 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26977 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26978 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26979 Op.getValueType());
26985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26986 if (C->getZExtValue() <= 3) {
26987 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26988 Op.getValueType());
26994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26995 if (C->getZExtValue() <= 255) {
26996 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26997 Op.getValueType());
27003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27004 if (C->getZExtValue() <= 127) {
27005 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27006 Op.getValueType());
27012 // 32-bit signed value
27013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27014 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27015 C->getSExtValue())) {
27016 // Widen to 64 bits here to get it sign extended.
27017 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27020 // FIXME gcc accepts some relocatable values here too, but only in certain
27021 // memory models; it's complicated.
27026 // 32-bit unsigned value
27027 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27028 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27029 C->getZExtValue())) {
27030 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27031 Op.getValueType());
27035 // FIXME gcc accepts some relocatable values here too, but only in certain
27036 // memory models; it's complicated.
27040 // Literal immediates are always ok.
27041 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27042 // Widen to 64 bits here to get it sign extended.
27043 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27047 // In any sort of PIC mode addresses need to be computed at runtime by
27048 // adding in a register or some sort of table lookup. These can't
27049 // be used as immediates.
27050 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27053 // If we are in non-pic codegen mode, we allow the address of a global (with
27054 // an optional displacement) to be used with 'i'.
27055 GlobalAddressSDNode *GA = nullptr;
27056 int64_t Offset = 0;
27058 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27060 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27061 Offset += GA->getOffset();
27063 } else if (Op.getOpcode() == ISD::ADD) {
27064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27065 Offset += C->getZExtValue();
27066 Op = Op.getOperand(0);
27069 } else if (Op.getOpcode() == ISD::SUB) {
27070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27071 Offset += -C->getZExtValue();
27072 Op = Op.getOperand(0);
27077 // Otherwise, this isn't something we can handle, reject it.
27081 const GlobalValue *GV = GA->getGlobal();
27082 // If we require an extra load to get this address, as in PIC mode, we
27083 // can't accept it.
27084 if (isGlobalStubReference(
27085 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27088 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27089 GA->getValueType(0), Offset);
27094 if (Result.getNode()) {
27095 Ops.push_back(Result);
27098 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27101 std::pair<unsigned, const TargetRegisterClass *>
27102 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27103 StringRef Constraint,
27105 // First, see if this is a constraint that directly corresponds to an LLVM
27107 if (Constraint.size() == 1) {
27108 // GCC Constraint Letters
27109 switch (Constraint[0]) {
27111 // TODO: Slight differences here in allocation order and leaving
27112 // RIP in the class. Do they matter any more here than they do
27113 // in the normal allocation?
27114 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27115 if (Subtarget->is64Bit()) {
27116 if (VT == MVT::i32 || VT == MVT::f32)
27117 return std::make_pair(0U, &X86::GR32RegClass);
27118 if (VT == MVT::i16)
27119 return std::make_pair(0U, &X86::GR16RegClass);
27120 if (VT == MVT::i8 || VT == MVT::i1)
27121 return std::make_pair(0U, &X86::GR8RegClass);
27122 if (VT == MVT::i64 || VT == MVT::f64)
27123 return std::make_pair(0U, &X86::GR64RegClass);
27126 // 32-bit fallthrough
27127 case 'Q': // Q_REGS
27128 if (VT == MVT::i32 || VT == MVT::f32)
27129 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27130 if (VT == MVT::i16)
27131 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27132 if (VT == MVT::i8 || VT == MVT::i1)
27133 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27134 if (VT == MVT::i64)
27135 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27137 case 'r': // GENERAL_REGS
27138 case 'l': // INDEX_REGS
27139 if (VT == MVT::i8 || VT == MVT::i1)
27140 return std::make_pair(0U, &X86::GR8RegClass);
27141 if (VT == MVT::i16)
27142 return std::make_pair(0U, &X86::GR16RegClass);
27143 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27144 return std::make_pair(0U, &X86::GR32RegClass);
27145 return std::make_pair(0U, &X86::GR64RegClass);
27146 case 'R': // LEGACY_REGS
27147 if (VT == MVT::i8 || VT == MVT::i1)
27148 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27149 if (VT == MVT::i16)
27150 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27151 if (VT == MVT::i32 || !Subtarget->is64Bit())
27152 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27153 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27154 case 'f': // FP Stack registers.
27155 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27156 // value to the correct fpstack register class.
27157 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27158 return std::make_pair(0U, &X86::RFP32RegClass);
27159 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27160 return std::make_pair(0U, &X86::RFP64RegClass);
27161 return std::make_pair(0U, &X86::RFP80RegClass);
27162 case 'y': // MMX_REGS if MMX allowed.
27163 if (!Subtarget->hasMMX()) break;
27164 return std::make_pair(0U, &X86::VR64RegClass);
27165 case 'Y': // SSE_REGS if SSE2 allowed
27166 if (!Subtarget->hasSSE2()) break;
27168 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27169 if (!Subtarget->hasSSE1()) break;
27171 switch (VT.SimpleTy) {
27173 // Scalar SSE types.
27176 return std::make_pair(0U, &X86::FR32RegClass);
27179 return std::make_pair(0U, &X86::FR64RegClass);
27187 return std::make_pair(0U, &X86::VR128RegClass);
27195 return std::make_pair(0U, &X86::VR256RegClass);
27200 return std::make_pair(0U, &X86::VR512RegClass);
27206 // Use the default implementation in TargetLowering to convert the register
27207 // constraint into a member of a register class.
27208 std::pair<unsigned, const TargetRegisterClass*> Res;
27209 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27211 // Not found as a standard register?
27213 // Map st(0) -> st(7) -> ST0
27214 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27215 tolower(Constraint[1]) == 's' &&
27216 tolower(Constraint[2]) == 't' &&
27217 Constraint[3] == '(' &&
27218 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27219 Constraint[5] == ')' &&
27220 Constraint[6] == '}') {
27222 Res.first = X86::FP0+Constraint[4]-'0';
27223 Res.second = &X86::RFP80RegClass;
27227 // GCC allows "st(0)" to be called just plain "st".
27228 if (StringRef("{st}").equals_lower(Constraint)) {
27229 Res.first = X86::FP0;
27230 Res.second = &X86::RFP80RegClass;
27235 if (StringRef("{flags}").equals_lower(Constraint)) {
27236 Res.first = X86::EFLAGS;
27237 Res.second = &X86::CCRRegClass;
27241 // 'A' means EAX + EDX.
27242 if (Constraint == "A") {
27243 Res.first = X86::EAX;
27244 Res.second = &X86::GR32_ADRegClass;
27250 // Otherwise, check to see if this is a register class of the wrong value
27251 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27252 // turn into {ax},{dx}.
27253 // MVT::Other is used to specify clobber names.
27254 if (Res.second->hasType(VT) || VT == MVT::Other)
27255 return Res; // Correct type already, nothing to do.
27257 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27258 // return "eax". This should even work for things like getting 64bit integer
27259 // registers when given an f64 type.
27260 const TargetRegisterClass *Class = Res.second;
27261 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27262 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27263 unsigned Size = VT.getSizeInBits();
27264 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27265 : Size == 16 ? MVT::i16
27266 : Size == 32 ? MVT::i32
27267 : Size == 64 ? MVT::i64
27269 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27271 Res.first = DestReg;
27272 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27273 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27274 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27275 : &X86::GR64RegClass;
27276 assert(Res.second->contains(Res.first) && "Register in register class");
27278 // No register found/type mismatch.
27280 Res.second = nullptr;
27282 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27283 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27284 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27285 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27286 Class == &X86::VR512RegClass) {
27287 // Handle references to XMM physical registers that got mapped into the
27288 // wrong class. This can happen with constraints like {xmm0} where the
27289 // target independent register mapper will just pick the first match it can
27290 // find, ignoring the required type.
27292 if (VT == MVT::f32 || VT == MVT::i32)
27293 Res.second = &X86::FR32RegClass;
27294 else if (VT == MVT::f64 || VT == MVT::i64)
27295 Res.second = &X86::FR64RegClass;
27296 else if (X86::VR128RegClass.hasType(VT))
27297 Res.second = &X86::VR128RegClass;
27298 else if (X86::VR256RegClass.hasType(VT))
27299 Res.second = &X86::VR256RegClass;
27300 else if (X86::VR512RegClass.hasType(VT))
27301 Res.second = &X86::VR512RegClass;
27303 // Type mismatch and not a clobber: Return an error;
27305 Res.second = nullptr;
27312 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27313 const AddrMode &AM, Type *Ty,
27314 unsigned AS) const {
27315 // Scaling factors are not free at all.
27316 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27317 // will take 2 allocations in the out of order engine instead of 1
27318 // for plain addressing mode, i.e. inst (reg1).
27320 // vaddps (%rsi,%drx), %ymm0, %ymm1
27321 // Requires two allocations (one for the load, one for the computation)
27323 // vaddps (%rsi), %ymm0, %ymm1
27324 // Requires just 1 allocation, i.e., freeing allocations for other operations
27325 // and having less micro operations to execute.
27327 // For some X86 architectures, this is even worse because for instance for
27328 // stores, the complex addressing mode forces the instruction to use the
27329 // "load" ports instead of the dedicated "store" port.
27330 // E.g., on Haswell:
27331 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27332 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27333 if (isLegalAddressingMode(DL, AM, Ty, AS))
27334 // Scale represents reg2 * scale, thus account for 1
27335 // as soon as we use a second register.
27336 return AM.Scale != 0;
27340 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27341 // Integer division on x86 is expensive. However, when aggressively optimizing
27342 // for code size, we prefer to use a div instruction, as it is usually smaller
27343 // than the alternative sequence.
27344 // The exception to this is vector division. Since x86 doesn't have vector
27345 // integer division, leaving the division as-is is a loss even in terms of
27346 // size, because it will have to be scalarized, while the alternative code
27347 // sequence can be performed in vector form.
27348 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27349 Attribute::MinSize);
27350 return OptSize && !VT.isVector();