1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (TM.getOptLevel() >= CodeGenOpt::Default) {
253 if (Subtarget->hasSlowDivide32())
254 addBypassSlowDiv(32, 8);
255 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
256 addBypassSlowDiv(64, 16);
259 if (Subtarget->isTargetKnownWindowsMSVC()) {
260 // Setup Windows compiler runtime calls.
261 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
262 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
263 setLibcallName(RTLIB::SREM_I64, "_allrem");
264 setLibcallName(RTLIB::UREM_I64, "_aullrem");
265 setLibcallName(RTLIB::MUL_I64, "_allmul");
266 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
272 // The _ftol2 runtime function has an unusual calling conv, which
273 // is modeled by a special pseudo-instruction.
274 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
280 if (Subtarget->isTargetDarwin()) {
281 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
282 setUseUnderscoreSetJmp(false);
283 setUseUnderscoreLongJmp(false);
284 } else if (Subtarget->isTargetWindowsGNU()) {
285 // MS runtime is weird: it exports _setjmp, but longjmp!
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(false);
289 setUseUnderscoreSetJmp(true);
290 setUseUnderscoreLongJmp(true);
293 // Set up the register classes.
294 addRegisterClass(MVT::i8, &X86::GR8RegClass);
295 addRegisterClass(MVT::i16, &X86::GR16RegClass);
296 addRegisterClass(MVT::i32, &X86::GR32RegClass);
297 if (Subtarget->is64Bit())
298 addRegisterClass(MVT::i64, &X86::GR64RegClass);
300 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
302 // We don't accept any truncstore of integer registers.
303 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
307 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
308 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
310 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
312 // SETOEQ and SETUNE require checking two conditions.
313 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
315 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
320 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
322 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 } else if (!TM.Options.UseSoftFloat) {
330 // We have an algorithm for SSE2->double, and we turn this into a
331 // 64-bit FILD followed by conditional FADD for other targets.
332 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
333 // We have an algorithm for SSE2, and we turn this into a 64-bit
334 // FILD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
338 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
340 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
343 if (!TM.Options.UseSoftFloat) {
344 // SSE has no i16 to fp conversion, only i32
345 if (X86ScalarSSEf32) {
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 // f32 and f64 cases are Legal, f80 case is not
348 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
358 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
359 // are Legal, f80 is custom lowered.
360 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
363 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
365 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
368 if (X86ScalarSSEf32) {
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
370 // f32 and f64 cases are Legal, f80 case is not
371 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
377 // Handle FP_TO_UINT by promoting the destination to a larger signed
379 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
383 if (Subtarget->is64Bit()) {
384 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
385 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
386 } else if (!TM.Options.UseSoftFloat) {
387 // Since AVX is a superset of SSE3, only check for SSE here.
388 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
389 // Expand FP_TO_UINT into a select.
390 // FIXME: We would like to use a Custom expander here eventually to do
391 // the optimal thing for SSE vs. the default expansion in the legalizer.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
394 // With SSE3 we can use fisttpll to convert to a signed i64; without
395 // SSE, we're stuck with a fistpll.
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
399 if (isTargetFTOL()) {
400 // Use the _ftol2 runtime function, which has a pseudo-instruction
401 // to handle its weird calling convention.
402 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
405 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
406 if (!X86ScalarSSEf64) {
407 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
408 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
409 if (Subtarget->is64Bit()) {
410 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
411 // Without SSE, i64->f64 goes through memory.
412 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
416 // Scalar integer divide and remainder are lowered to use operations that
417 // produce two results, to match the available instructions. This exposes
418 // the two-result form to trivial CSE, which is able to combine x/y and x%y
419 // into a single instruction.
421 // Scalar integer multiply-high is also lowered to use two-result
422 // operations, to match the available instructions. However, plain multiply
423 // (low) operations are left as Legal, as there are single-result
424 // instructions for this in x86. Using the two-result multiply instructions
425 // when both high and low results are needed must be arranged by dagcombine.
426 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
428 setOperationAction(ISD::MULHS, VT, Expand);
429 setOperationAction(ISD::MULHU, VT, Expand);
430 setOperationAction(ISD::SDIV, VT, Expand);
431 setOperationAction(ISD::UDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UREM, VT, Expand);
435 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
436 setOperationAction(ISD::ADDC, VT, Custom);
437 setOperationAction(ISD::ADDE, VT, Custom);
438 setOperationAction(ISD::SUBC, VT, Custom);
439 setOperationAction(ISD::SUBE, VT, Custom);
442 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
443 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
444 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
446 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
458 if (Subtarget->is64Bit())
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
463 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f32 , Expand);
465 setOperationAction(ISD::FREM , MVT::f64 , Expand);
466 setOperationAction(ISD::FREM , MVT::f80 , Expand);
467 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
469 // Promote the i8 variants and force them on up to i32 which has a shorter
471 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
474 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
475 if (Subtarget->hasBMI()) {
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
481 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
482 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
483 if (Subtarget->is64Bit())
484 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
487 if (Subtarget->hasLZCNT()) {
488 // When promoting the i8 variants, force them to i32 for a shorter
490 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
493 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
496 if (Subtarget->is64Bit())
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
499 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
501 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
505 if (Subtarget->is64Bit()) {
506 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
511 // Special handling for half-precision floating point conversions.
512 // If we don't have F16C support, then lower half float conversions
513 // into library calls.
514 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
515 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
516 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
519 // There's never any support for operations beyond MVT::f32.
520 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
521 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
525 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
528 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
530 if (Subtarget->hasPOPCNT()) {
531 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
533 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
535 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
536 if (Subtarget->is64Bit())
537 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
540 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
542 if (!Subtarget->hasMOVBE())
543 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
545 // These should be promoted to a larger select which is supported.
546 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
547 // X86 wants to expand cmov itself.
548 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
550 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
553 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
556 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
559 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
560 if (Subtarget->is64Bit()) {
561 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
564 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
565 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
566 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
567 // support continuation, user-level threading, and etc.. As a result, no
568 // other SjLj exception interfaces are implemented and please don't build
569 // your own exception handling based on them.
570 // LLVM/Clang supports zero-cost DWARF exception handling.
571 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
572 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
575 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
576 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
579 if (Subtarget->is64Bit())
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
581 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
582 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
583 if (Subtarget->is64Bit()) {
584 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
585 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
586 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
587 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
588 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
590 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
591 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
597 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
600 if (Subtarget->hasSSE1())
601 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
603 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
605 // Expand certain atomics
606 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
608 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
609 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
610 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
613 if (Subtarget->hasCmpxchg16b()) {
614 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
617 // FIXME - use subtarget debug flags
618 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
619 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
620 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
623 if (Subtarget->is64Bit()) {
624 setExceptionPointerRegister(X86::RAX);
625 setExceptionSelectorRegister(X86::RDX);
627 setExceptionPointerRegister(X86::EAX);
628 setExceptionSelectorRegister(X86::EDX);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
631 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
633 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
636 setOperationAction(ISD::TRAP, MVT::Other, Legal);
637 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
639 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
640 setOperationAction(ISD::VASTART , MVT::Other, Custom);
641 setOperationAction(ISD::VAEND , MVT::Other, Expand);
642 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
643 // TargetInfo::X86_64ABIBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Custom);
645 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
647 // TargetInfo::CharPtrBuiltinVaList
648 setOperationAction(ISD::VAARG , MVT::Other, Expand);
649 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
652 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
653 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
655 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
657 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
658 // f32 and f64 use SSE.
659 // Set up the FP register classes.
660 addRegisterClass(MVT::f32, &X86::FR32RegClass);
661 addRegisterClass(MVT::f64, &X86::FR64RegClass);
663 // Use ANDPD to simulate FABS.
664 setOperationAction(ISD::FABS , MVT::f64, Custom);
665 setOperationAction(ISD::FABS , MVT::f32, Custom);
667 // Use XORP to simulate FNEG.
668 setOperationAction(ISD::FNEG , MVT::f64, Custom);
669 setOperationAction(ISD::FNEG , MVT::f32, Custom);
671 // Use ANDPD and ORPD to simulate FCOPYSIGN.
672 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
675 // Lower this to FGETSIGNx86 plus an AND.
676 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
677 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
679 // We don't support sin/cos/fmod
680 setOperationAction(ISD::FSIN , MVT::f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::f64, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
683 setOperationAction(ISD::FSIN , MVT::f32, Expand);
684 setOperationAction(ISD::FCOS , MVT::f32, Expand);
685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
687 // Expand FP immediates into loads from the stack, except for the special
689 addLegalFPImmediate(APFloat(+0.0)); // xorpd
690 addLegalFPImmediate(APFloat(+0.0f)); // xorps
691 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
692 // Use SSE for f32, x87 for f64.
693 // Set up the FP register classes.
694 addRegisterClass(MVT::f32, &X86::FR32RegClass);
695 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
697 // Use ANDPS to simulate FABS.
698 setOperationAction(ISD::FABS , MVT::f32, Custom);
700 // Use XORP to simulate FNEG.
701 setOperationAction(ISD::FNEG , MVT::f32, Custom);
703 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 // Use ANDPS and ORPS to simulate FCOPYSIGN.
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
709 // We don't support sin/cos/fmod
710 setOperationAction(ISD::FSIN , MVT::f32, Expand);
711 setOperationAction(ISD::FCOS , MVT::f32, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
714 // Special cases we handle for FP constants.
715 addLegalFPImmediate(APFloat(+0.0f)); // xorps
716 addLegalFPImmediate(APFloat(+0.0)); // FLD0
717 addLegalFPImmediate(APFloat(+1.0)); // FLD1
718 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
719 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 if (!TM.Options.UnsafeFPMath) {
722 setOperationAction(ISD::FSIN , MVT::f64, Expand);
723 setOperationAction(ISD::FCOS , MVT::f64, Expand);
724 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
726 } else if (!TM.Options.UseSoftFloat) {
727 // f32 and f64 in x87.
728 // Set up the FP register classes.
729 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
730 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
732 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
733 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
737 if (!TM.Options.UnsafeFPMath) {
738 setOperationAction(ISD::FSIN , MVT::f64, Expand);
739 setOperationAction(ISD::FSIN , MVT::f32, Expand);
740 setOperationAction(ISD::FCOS , MVT::f64, Expand);
741 setOperationAction(ISD::FCOS , MVT::f32, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
743 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
745 addLegalFPImmediate(APFloat(+0.0)); // FLD0
746 addLegalFPImmediate(APFloat(+1.0)); // FLD1
747 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
748 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
749 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
750 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
751 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
752 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
755 // We don't support FMA.
756 setOperationAction(ISD::FMA, MVT::f64, Expand);
757 setOperationAction(ISD::FMA, MVT::f32, Expand);
759 // Long double always uses X87.
760 if (!TM.Options.UseSoftFloat) {
761 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
762 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
763 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
765 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
766 addLegalFPImmediate(TmpFlt); // FLD0
768 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
771 APFloat TmpFlt2(+1.0);
772 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
774 addLegalFPImmediate(TmpFlt2); // FLD1
775 TmpFlt2.changeSign();
776 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
779 if (!TM.Options.UnsafeFPMath) {
780 setOperationAction(ISD::FSIN , MVT::f80, Expand);
781 setOperationAction(ISD::FCOS , MVT::f80, Expand);
782 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
785 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
786 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
787 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
788 setOperationAction(ISD::FRINT, MVT::f80, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
790 setOperationAction(ISD::FMA, MVT::f80, Expand);
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
798 setOperationAction(ISD::FLOG, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
803 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
804 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806 // First set operation action for all vector types to either promote
807 // (for widening) or expand (for scalarization). Then we will selectively
808 // turn on ones that can be effectively codegen'd.
809 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
810 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
811 MVT VT = (MVT::SimpleValueType)i;
812 setOperationAction(ISD::ADD , VT, Expand);
813 setOperationAction(ISD::SUB , VT, Expand);
814 setOperationAction(ISD::FADD, VT, Expand);
815 setOperationAction(ISD::FNEG, VT, Expand);
816 setOperationAction(ISD::FSUB, VT, Expand);
817 setOperationAction(ISD::MUL , VT, Expand);
818 setOperationAction(ISD::FMUL, VT, Expand);
819 setOperationAction(ISD::SDIV, VT, Expand);
820 setOperationAction(ISD::UDIV, VT, Expand);
821 setOperationAction(ISD::FDIV, VT, Expand);
822 setOperationAction(ISD::SREM, VT, Expand);
823 setOperationAction(ISD::UREM, VT, Expand);
824 setOperationAction(ISD::LOAD, VT, Expand);
825 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
828 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
830 setOperationAction(ISD::FABS, VT, Expand);
831 setOperationAction(ISD::FSIN, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FCOS, VT, Expand);
834 setOperationAction(ISD::FSINCOS, VT, Expand);
835 setOperationAction(ISD::FREM, VT, Expand);
836 setOperationAction(ISD::FMA, VT, Expand);
837 setOperationAction(ISD::FPOWI, VT, Expand);
838 setOperationAction(ISD::FSQRT, VT, Expand);
839 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
840 setOperationAction(ISD::FFLOOR, VT, Expand);
841 setOperationAction(ISD::FCEIL, VT, Expand);
842 setOperationAction(ISD::FTRUNC, VT, Expand);
843 setOperationAction(ISD::FRINT, VT, Expand);
844 setOperationAction(ISD::FNEARBYINT, VT, Expand);
845 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHS, VT, Expand);
847 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
848 setOperationAction(ISD::MULHU, VT, Expand);
849 setOperationAction(ISD::SDIVREM, VT, Expand);
850 setOperationAction(ISD::UDIVREM, VT, Expand);
851 setOperationAction(ISD::FPOW, VT, Expand);
852 setOperationAction(ISD::CTPOP, VT, Expand);
853 setOperationAction(ISD::CTTZ, VT, Expand);
854 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::CTLZ, VT, Expand);
856 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
857 setOperationAction(ISD::SHL, VT, Expand);
858 setOperationAction(ISD::SRA, VT, Expand);
859 setOperationAction(ISD::SRL, VT, Expand);
860 setOperationAction(ISD::ROTL, VT, Expand);
861 setOperationAction(ISD::ROTR, VT, Expand);
862 setOperationAction(ISD::BSWAP, VT, Expand);
863 setOperationAction(ISD::SETCC, VT, Expand);
864 setOperationAction(ISD::FLOG, VT, Expand);
865 setOperationAction(ISD::FLOG2, VT, Expand);
866 setOperationAction(ISD::FLOG10, VT, Expand);
867 setOperationAction(ISD::FEXP, VT, Expand);
868 setOperationAction(ISD::FEXP2, VT, Expand);
869 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
870 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
871 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
874 setOperationAction(ISD::TRUNCATE, VT, Expand);
875 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
876 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
877 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
878 setOperationAction(ISD::VSELECT, VT, Expand);
879 setOperationAction(ISD::SELECT_CC, VT, Expand);
880 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
881 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
882 setTruncStoreAction(VT,
883 (MVT::SimpleValueType)InnerVT, Expand);
884 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
885 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
887 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
888 // we have to deal with them whether we ask for Expansion or not. Setting
889 // Expand causes its own optimisation problems though, so leave them legal.
890 if (VT.getVectorElementType() == MVT::i1)
891 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
894 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
895 // with -msoft-float, disable use of MMX as well.
896 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
897 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
898 // No operations on x86mmx supported, everything uses intrinsics.
901 // MMX-sized vectors (other than x86mmx) are expected to be expanded
902 // into smaller operations.
903 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
904 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
905 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
906 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
907 setOperationAction(ISD::AND, MVT::v8i8, Expand);
908 setOperationAction(ISD::AND, MVT::v4i16, Expand);
909 setOperationAction(ISD::AND, MVT::v2i32, Expand);
910 setOperationAction(ISD::AND, MVT::v1i64, Expand);
911 setOperationAction(ISD::OR, MVT::v8i8, Expand);
912 setOperationAction(ISD::OR, MVT::v4i16, Expand);
913 setOperationAction(ISD::OR, MVT::v2i32, Expand);
914 setOperationAction(ISD::OR, MVT::v1i64, Expand);
915 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
924 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
925 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
926 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
927 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
931 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
933 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
934 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
936 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
938 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
939 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
940 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
941 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
942 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
943 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
944 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
945 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
947 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
948 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
951 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
952 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
954 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
955 // registers cannot be used even for integer operations.
956 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
957 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
958 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
959 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
961 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
962 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
963 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
964 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
965 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
966 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
967 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
969 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
970 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
972 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
973 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
974 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
976 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
977 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
978 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
979 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
981 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
982 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
985 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
986 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
987 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
990 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
995 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to custom lower non-power-of-2 vectors
999 if (!isPowerOf2_32(VT.getVectorNumElements()))
1001 // Do not attempt to custom lower non-128-bit vectors
1002 if (!VT.is128BitVector())
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1009 // We support custom legalizing of sext and anyext loads for specific
1010 // memory vector types which we can load as a scalar (or sequence of
1011 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1012 // loads these must work with a single scalar load.
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1015 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1024 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1026 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1030 if (Subtarget->is64Bit()) {
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1032 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1035 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1036 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1037 MVT VT = (MVT::SimpleValueType)i;
1039 // Do not attempt to promote non-128-bit vectors
1040 if (!VT.is128BitVector())
1043 setOperationAction(ISD::AND, VT, Promote);
1044 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1045 setOperationAction(ISD::OR, VT, Promote);
1046 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1047 setOperationAction(ISD::XOR, VT, Promote);
1048 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1049 setOperationAction(ISD::LOAD, VT, Promote);
1050 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1051 setOperationAction(ISD::SELECT, VT, Promote);
1052 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1055 // Custom lower v2i64 and v2f64 selects.
1056 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1058 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1059 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1066 // As there is no 64-bit GPR available, we need build a special custom
1067 // sequence to convert from v2i32 to v2f32.
1068 if (!Subtarget->is64Bit())
1069 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1072 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1074 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1076 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1078 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1081 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1082 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1087 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1088 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1089 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1090 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1104 // FIXME: Do we need to handle scalar-to-vector here?
1105 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1107 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1112 // There is no BLENDI for byte vectors. We don't need to custom lower
1113 // some vselects for now.
1114 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1116 // SSE41 brings specific instructions for doing vector sign extend even in
1117 // cases where we don't have SRA.
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1120 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1122 // i8 and i16 vectors are custom because the source register and source
1123 // source memory operand types are not the same width. f32 vectors are
1124 // custom since the immediate controlling the insert encodes additional
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1136 // FIXME: these should be Legal, but that's only for the case where
1137 // the index is constant. For now custom expand to deal with that.
1138 if (Subtarget->is64Bit()) {
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1144 if (Subtarget->hasSSE2()) {
1145 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1146 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1148 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1154 // In the customized shift lowering, the legal cases in AVX2 will be
1156 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1157 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1159 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1165 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1166 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1173 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1175 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1190 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1201 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1203 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1204 // even though v8i16 is a legal type.
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1207 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1210 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1211 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1214 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1218 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1219 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1221 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1234 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1252 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1254 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1255 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1259 setOperationAction(ISD::FMA, MVT::f32, Legal);
1260 setOperationAction(ISD::FMA, MVT::f64, Legal);
1263 if (Subtarget->hasInt256()) {
1264 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1265 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1266 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1267 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1269 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1270 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1271 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1272 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1274 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1275 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1276 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1277 // Don't lower v32i8 because there is no 128-bit byte mul
1279 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1281 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1282 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1284 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1285 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1287 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1288 // when we have a 256bit-wide blend with immediate.
1289 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1292 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1293 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1294 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1296 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1297 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1299 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1301 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1302 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1303 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1304 // Don't lower v32i8 because there is no 128-bit byte mul
1307 // In the customized shift lowering, the legal cases in AVX2 will be
1309 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1312 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1317 // Custom lower several nodes for 256-bit types.
1318 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1319 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1320 MVT VT = (MVT::SimpleValueType)i;
1322 // Extract subvector is special because the value type
1323 // (result) is 128-bit but the source is 256-bit wide.
1324 if (VT.is128BitVector())
1325 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1327 // Do not attempt to custom lower other non-256-bit vectors
1328 if (!VT.is256BitVector())
1331 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1332 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1335 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1336 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1337 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1340 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1341 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1342 MVT VT = (MVT::SimpleValueType)i;
1344 // Do not attempt to promote non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::AND, VT, Promote);
1349 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1350 setOperationAction(ISD::OR, VT, Promote);
1351 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1352 setOperationAction(ISD::XOR, VT, Promote);
1353 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1354 setOperationAction(ISD::LOAD, VT, Promote);
1355 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1356 setOperationAction(ISD::SELECT, VT, Promote);
1357 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1361 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1362 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1365 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1367 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1368 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1369 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1371 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1372 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1373 setOperationAction(ISD::XOR, MVT::i1, Legal);
1374 setOperationAction(ISD::OR, MVT::i1, Legal);
1375 setOperationAction(ISD::AND, MVT::i1, Legal);
1376 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1383 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1390 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1396 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1401 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1402 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1403 if (Subtarget->is64Bit()) {
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1406 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1599 if (!Subtarget->is64Bit()) {
1600 // These libcalls are not available in 32-bit.
1601 setLibcallName(RTLIB::SHL_I128, nullptr);
1602 setLibcallName(RTLIB::SRL_I128, nullptr);
1603 setLibcallName(RTLIB::SRA_I128, nullptr);
1606 // Combine sin / cos into one node or libcall if possible.
1607 if (Subtarget->hasSinCos()) {
1608 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1609 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1610 if (Subtarget->isTargetDarwin()) {
1611 // For MacOSX, we don't want to the normal expansion of a libcall to
1612 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1614 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1615 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1619 if (Subtarget->isTargetWin64()) {
1620 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1622 setOperationAction(ISD::SREM, MVT::i128, Custom);
1623 setOperationAction(ISD::UREM, MVT::i128, Custom);
1624 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1628 // We have target-specific dag combine patterns for the following nodes:
1629 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1630 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1631 setTargetDAGCombine(ISD::VSELECT);
1632 setTargetDAGCombine(ISD::SELECT);
1633 setTargetDAGCombine(ISD::SHL);
1634 setTargetDAGCombine(ISD::SRA);
1635 setTargetDAGCombine(ISD::SRL);
1636 setTargetDAGCombine(ISD::OR);
1637 setTargetDAGCombine(ISD::AND);
1638 setTargetDAGCombine(ISD::ADD);
1639 setTargetDAGCombine(ISD::FADD);
1640 setTargetDAGCombine(ISD::FSUB);
1641 setTargetDAGCombine(ISD::FMA);
1642 setTargetDAGCombine(ISD::SUB);
1643 setTargetDAGCombine(ISD::LOAD);
1644 setTargetDAGCombine(ISD::STORE);
1645 setTargetDAGCombine(ISD::ZERO_EXTEND);
1646 setTargetDAGCombine(ISD::ANY_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND);
1648 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1649 setTargetDAGCombine(ISD::TRUNCATE);
1650 setTargetDAGCombine(ISD::SINT_TO_FP);
1651 setTargetDAGCombine(ISD::SETCC);
1652 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1653 setTargetDAGCombine(ISD::BUILD_VECTOR);
1654 if (Subtarget->is64Bit())
1655 setTargetDAGCombine(ISD::MUL);
1656 setTargetDAGCombine(ISD::XOR);
1658 computeRegisterProperties();
1660 // On Darwin, -Os means optimize for size without hurting performance,
1661 // do not reduce the limit.
1662 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1663 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1664 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1665 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1666 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1667 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 setPrefLoopAlignment(4); // 2^4 bytes.
1670 // Predictable cmov don't hurt on atom because it's in-order.
1671 PredictableSelectIsExpensive = !Subtarget->isAtom();
1673 setPrefFunctionAlignment(4); // 2^4 bytes.
1675 verifyIntrinsicTables();
1678 // This has so far only been implemented for 64-bit MachO.
1679 bool X86TargetLowering::useLoadStackGuardNode() const {
1680 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1681 Subtarget->is64Bit();
1684 TargetLoweringBase::LegalizeTypeAction
1685 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1686 if (ExperimentalVectorWideningLegalization &&
1687 VT.getVectorNumElements() != 1 &&
1688 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1689 return TypeWidenVector;
1691 return TargetLoweringBase::getPreferredVectorAction(VT);
1694 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1696 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1698 const unsigned NumElts = VT.getVectorNumElements();
1699 const EVT EltVT = VT.getVectorElementType();
1700 if (VT.is512BitVector()) {
1701 if (Subtarget->hasAVX512())
1702 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1703 EltVT == MVT::f32 || EltVT == MVT::f64)
1705 case 8: return MVT::v8i1;
1706 case 16: return MVT::v16i1;
1708 if (Subtarget->hasBWI())
1709 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1711 case 32: return MVT::v32i1;
1712 case 64: return MVT::v64i1;
1716 if (VT.is256BitVector() || VT.is128BitVector()) {
1717 if (Subtarget->hasVLX())
1718 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1719 EltVT == MVT::f32 || EltVT == MVT::f64)
1721 case 2: return MVT::v2i1;
1722 case 4: return MVT::v4i1;
1723 case 8: return MVT::v8i1;
1725 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1726 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1728 case 8: return MVT::v8i1;
1729 case 16: return MVT::v16i1;
1730 case 32: return MVT::v32i1;
1734 return VT.changeVectorElementTypeToInteger();
1737 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1738 /// the desired ByVal argument alignment.
1739 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1742 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1743 if (VTy->getBitWidth() == 128)
1745 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1746 unsigned EltAlign = 0;
1747 getMaxByValAlign(ATy->getElementType(), EltAlign);
1748 if (EltAlign > MaxAlign)
1749 MaxAlign = EltAlign;
1750 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1751 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1752 unsigned EltAlign = 0;
1753 getMaxByValAlign(STy->getElementType(i), EltAlign);
1754 if (EltAlign > MaxAlign)
1755 MaxAlign = EltAlign;
1762 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1763 /// function arguments in the caller parameter area. For X86, aggregates
1764 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1765 /// are at 4-byte boundaries.
1766 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1767 if (Subtarget->is64Bit()) {
1768 // Max of 8 and alignment of type.
1769 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1776 if (Subtarget->hasSSE1())
1777 getMaxByValAlign(Ty, Align);
1781 /// getOptimalMemOpType - Returns the target specific optimal type for load
1782 /// and store operations as a result of memset, memcpy, and memmove
1783 /// lowering. If DstAlign is zero that means it's safe to destination
1784 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1785 /// means there isn't a need to check it against alignment requirement,
1786 /// probably because the source does not need to be loaded. If 'IsMemset' is
1787 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1788 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1789 /// source is constant so it does not need to be loaded.
1790 /// It returns EVT::Other if the type should be determined using generic
1791 /// target-independent logic.
1793 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1794 unsigned DstAlign, unsigned SrcAlign,
1795 bool IsMemset, bool ZeroMemset,
1797 MachineFunction &MF) const {
1798 const Function *F = MF.getFunction();
1799 if ((!IsMemset || ZeroMemset) &&
1800 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1801 Attribute::NoImplicitFloat)) {
1803 (Subtarget->isUnalignedMemAccessFast() ||
1804 ((DstAlign == 0 || DstAlign >= 16) &&
1805 (SrcAlign == 0 || SrcAlign >= 16)))) {
1807 if (Subtarget->hasInt256())
1809 if (Subtarget->hasFp256())
1812 if (Subtarget->hasSSE2())
1814 if (Subtarget->hasSSE1())
1816 } else if (!MemcpyStrSrc && Size >= 8 &&
1817 !Subtarget->is64Bit() &&
1818 Subtarget->hasSSE2()) {
1819 // Do not use f64 to lower memcpy if source is string constant. It's
1820 // better to use i32 to avoid the loads.
1824 if (Subtarget->is64Bit() && Size >= 8)
1829 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1831 return X86ScalarSSEf32;
1832 else if (VT == MVT::f64)
1833 return X86ScalarSSEf64;
1838 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1843 *Fast = Subtarget->isUnalignedMemAccessFast();
1847 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1848 /// current function. The returned value is a member of the
1849 /// MachineJumpTableInfo::JTEntryKind enum.
1850 unsigned X86TargetLowering::getJumpTableEncoding() const {
1851 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1853 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1854 Subtarget->isPICStyleGOT())
1855 return MachineJumpTableInfo::EK_Custom32;
1857 // Otherwise, use the normal jump table encoding heuristics.
1858 return TargetLowering::getJumpTableEncoding();
1862 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1863 const MachineBasicBlock *MBB,
1864 unsigned uid,MCContext &Ctx) const{
1865 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1866 Subtarget->isPICStyleGOT());
1867 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1869 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1870 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1873 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1875 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1876 SelectionDAG &DAG) const {
1877 if (!Subtarget->is64Bit())
1878 // This doesn't have SDLoc associated with it, but is not really the
1879 // same as a Register.
1880 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1884 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1885 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1887 const MCExpr *X86TargetLowering::
1888 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1889 MCContext &Ctx) const {
1890 // X86-64 uses RIP relative addressing based on the jump table label.
1891 if (Subtarget->isPICStyleRIPRel())
1892 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1894 // Otherwise, the reference is relative to the PIC base.
1895 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1898 // FIXME: Why this routine is here? Move to RegInfo!
1899 std::pair<const TargetRegisterClass*, uint8_t>
1900 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1901 const TargetRegisterClass *RRC = nullptr;
1903 switch (VT.SimpleTy) {
1905 return TargetLowering::findRepresentativeClass(VT);
1906 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1907 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1910 RRC = &X86::VR64RegClass;
1912 case MVT::f32: case MVT::f64:
1913 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1914 case MVT::v4f32: case MVT::v2f64:
1915 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1917 RRC = &X86::VR128RegClass;
1920 return std::make_pair(RRC, Cost);
1923 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1924 unsigned &Offset) const {
1925 if (!Subtarget->isTargetLinux())
1928 if (Subtarget->is64Bit()) {
1929 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1931 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1943 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1944 unsigned DestAS) const {
1945 assert(SrcAS != DestAS && "Expected different address spaces!");
1947 return SrcAS < 256 && DestAS < 256;
1950 //===----------------------------------------------------------------------===//
1951 // Return Value Calling Convention Implementation
1952 //===----------------------------------------------------------------------===//
1954 #include "X86GenCallingConv.inc"
1957 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1958 MachineFunction &MF, bool isVarArg,
1959 const SmallVectorImpl<ISD::OutputArg> &Outs,
1960 LLVMContext &Context) const {
1961 SmallVector<CCValAssign, 16> RVLocs;
1962 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1963 return CCInfo.CheckReturn(Outs, RetCC_X86);
1966 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1967 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1972 X86TargetLowering::LowerReturn(SDValue Chain,
1973 CallingConv::ID CallConv, bool isVarArg,
1974 const SmallVectorImpl<ISD::OutputArg> &Outs,
1975 const SmallVectorImpl<SDValue> &OutVals,
1976 SDLoc dl, SelectionDAG &DAG) const {
1977 MachineFunction &MF = DAG.getMachineFunction();
1978 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1980 SmallVector<CCValAssign, 16> RVLocs;
1981 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1982 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1985 SmallVector<SDValue, 6> RetOps;
1986 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1987 // Operand #1 = Bytes To Pop
1988 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1991 // Copy the result values into the output registers.
1992 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1993 CCValAssign &VA = RVLocs[i];
1994 assert(VA.isRegLoc() && "Can only return in registers!");
1995 SDValue ValToCopy = OutVals[i];
1996 EVT ValVT = ValToCopy.getValueType();
1998 // Promote values to the appropriate types
1999 if (VA.getLocInfo() == CCValAssign::SExt)
2000 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2001 else if (VA.getLocInfo() == CCValAssign::ZExt)
2002 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::AExt)
2004 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::BCvt)
2006 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2008 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2009 "Unexpected FP-extend for return value.");
2011 // If this is x86-64, and we disabled SSE, we can't return FP values,
2012 // or SSE or MMX vectors.
2013 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2014 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2015 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2016 report_fatal_error("SSE register return with SSE disabled");
2018 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2019 // llvm-gcc has never done it right and no one has noticed, so this
2020 // should be OK for now.
2021 if (ValVT == MVT::f64 &&
2022 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2023 report_fatal_error("SSE2 register return with SSE2 disabled");
2025 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2026 // the RET instruction and handled by the FP Stackifier.
2027 if (VA.getLocReg() == X86::FP0 ||
2028 VA.getLocReg() == X86::FP1) {
2029 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2030 // change the value to the FP stack register class.
2031 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2032 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2033 RetOps.push_back(ValToCopy);
2034 // Don't emit a copytoreg.
2038 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2039 // which is returned in RAX / RDX.
2040 if (Subtarget->is64Bit()) {
2041 if (ValVT == MVT::x86mmx) {
2042 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2043 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2044 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2046 // If we don't have SSE2 available, convert to v4f32 so the generated
2047 // register is legal.
2048 if (!Subtarget->hasSSE2())
2049 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2054 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2055 Flag = Chain.getValue(1);
2056 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2059 // The x86-64 ABIs require that for returning structs by value we copy
2060 // the sret argument into %rax/%eax (depending on ABI) for the return.
2061 // Win32 requires us to put the sret argument to %eax as well.
2062 // We saved the argument into a virtual register in the entry block,
2063 // so now we copy the value out and into %rax/%eax.
2064 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2065 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2066 MachineFunction &MF = DAG.getMachineFunction();
2067 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2068 unsigned Reg = FuncInfo->getSRetReturnReg();
2070 "SRetReturnReg should have been set in LowerFormalArguments().");
2071 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2074 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2075 X86::RAX : X86::EAX;
2076 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2077 Flag = Chain.getValue(1);
2079 // RAX/EAX now acts like a return value.
2080 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2083 RetOps[0] = Chain; // Update chain.
2085 // Add the flag if we have it.
2087 RetOps.push_back(Flag);
2089 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2092 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2093 if (N->getNumValues() != 1)
2095 if (!N->hasNUsesOfValue(1, 0))
2098 SDValue TCChain = Chain;
2099 SDNode *Copy = *N->use_begin();
2100 if (Copy->getOpcode() == ISD::CopyToReg) {
2101 // If the copy has a glue operand, we conservatively assume it isn't safe to
2102 // perform a tail call.
2103 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2105 TCChain = Copy->getOperand(0);
2106 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2109 bool HasRet = false;
2110 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2112 if (UI->getOpcode() != X86ISD::RET_FLAG)
2114 // If we are returning more than one value, we can definitely
2115 // not make a tail call see PR19530
2116 if (UI->getNumOperands() > 4)
2118 if (UI->getNumOperands() == 4 &&
2119 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2132 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2133 ISD::NodeType ExtendKind) const {
2135 // TODO: Is this also valid on 32-bit?
2136 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2137 ReturnMVT = MVT::i8;
2139 ReturnMVT = MVT::i32;
2141 EVT MinVT = getRegisterType(Context, ReturnMVT);
2142 return VT.bitsLT(MinVT) ? MinVT : VT;
2145 /// LowerCallResult - Lower the result values of a call into the
2146 /// appropriate copies out of appropriate physical registers.
2149 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2150 CallingConv::ID CallConv, bool isVarArg,
2151 const SmallVectorImpl<ISD::InputArg> &Ins,
2152 SDLoc dl, SelectionDAG &DAG,
2153 SmallVectorImpl<SDValue> &InVals) const {
2155 // Assign locations to each value returned by this call.
2156 SmallVector<CCValAssign, 16> RVLocs;
2157 bool Is64Bit = Subtarget->is64Bit();
2158 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2160 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2162 // Copy all of the result registers out of their specified physreg.
2163 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2164 CCValAssign &VA = RVLocs[i];
2165 EVT CopyVT = VA.getValVT();
2167 // If this is x86-64, and we disabled SSE, we can't return FP values
2168 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2169 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2170 report_fatal_error("SSE register return with SSE disabled");
2173 // If we prefer to use the value in xmm registers, copy it out as f80 and
2174 // use a truncate to move it from fp stack reg to xmm reg.
2175 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2176 isScalarFPTypeInSSEReg(VA.getValVT()))
2179 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2180 CopyVT, InFlag).getValue(1);
2181 SDValue Val = Chain.getValue(0);
2183 if (CopyVT != VA.getValVT())
2184 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2185 // This truncation won't change the value.
2186 DAG.getIntPtrConstant(1));
2188 InFlag = Chain.getValue(2);
2189 InVals.push_back(Val);
2195 //===----------------------------------------------------------------------===//
2196 // C & StdCall & Fast Calling Convention implementation
2197 //===----------------------------------------------------------------------===//
2198 // StdCall calling convention seems to be standard for many Windows' API
2199 // routines and around. It differs from C calling convention just a little:
2200 // callee should clean up the stack, not caller. Symbols should be also
2201 // decorated in some fancy way :) It doesn't support any vector arguments.
2202 // For info on fast calling convention see Fast Calling Convention (tail call)
2203 // implementation LowerX86_32FastCCCallTo.
2205 /// CallIsStructReturn - Determines whether a call uses struct return
2207 enum StructReturnType {
2212 static StructReturnType
2213 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2215 return NotStructReturn;
2217 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2218 if (!Flags.isSRet())
2219 return NotStructReturn;
2220 if (Flags.isInReg())
2221 return RegStructReturn;
2222 return StackStructReturn;
2225 /// ArgsAreStructReturn - Determines whether a function uses struct
2226 /// return semantics.
2227 static StructReturnType
2228 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2230 return NotStructReturn;
2232 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2233 if (!Flags.isSRet())
2234 return NotStructReturn;
2235 if (Flags.isInReg())
2236 return RegStructReturn;
2237 return StackStructReturn;
2240 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2241 /// by "Src" to address "Dst" with size and alignment information specified by
2242 /// the specific parameter attribute. The copy will be passed as a byval
2243 /// function parameter.
2245 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2246 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2248 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2250 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2251 /*isVolatile*/false, /*AlwaysInline=*/true,
2252 MachinePointerInfo(), MachinePointerInfo());
2255 /// IsTailCallConvention - Return true if the calling convention is one that
2256 /// supports tail call optimization.
2257 static bool IsTailCallConvention(CallingConv::ID CC) {
2258 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2259 CC == CallingConv::HiPE);
2262 /// \brief Return true if the calling convention is a C calling convention.
2263 static bool IsCCallConvention(CallingConv::ID CC) {
2264 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2265 CC == CallingConv::X86_64_SysV);
2268 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2269 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2273 CallingConv::ID CalleeCC = CS.getCallingConv();
2274 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2280 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2281 /// a tailcall target by changing its ABI.
2282 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2283 bool GuaranteedTailCallOpt) {
2284 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2288 X86TargetLowering::LowerMemArgument(SDValue Chain,
2289 CallingConv::ID CallConv,
2290 const SmallVectorImpl<ISD::InputArg> &Ins,
2291 SDLoc dl, SelectionDAG &DAG,
2292 const CCValAssign &VA,
2293 MachineFrameInfo *MFI,
2295 // Create the nodes corresponding to a load from this parameter slot.
2296 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2297 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2298 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2299 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2302 // If value is passed by pointer we have address passed instead of the value
2304 if (VA.getLocInfo() == CCValAssign::Indirect)
2305 ValVT = VA.getLocVT();
2307 ValVT = VA.getValVT();
2309 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2310 // changed with more analysis.
2311 // In case of tail call optimization mark all arguments mutable. Since they
2312 // could be overwritten by lowering of arguments in case of a tail call.
2313 if (Flags.isByVal()) {
2314 unsigned Bytes = Flags.getByValSize();
2315 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2316 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2317 return DAG.getFrameIndex(FI, getPointerTy());
2319 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2320 VA.getLocMemOffset(), isImmutable);
2321 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2322 return DAG.getLoad(ValVT, dl, Chain, FIN,
2323 MachinePointerInfo::getFixedStack(FI),
2324 false, false, false, 0);
2328 // FIXME: Get this from tablegen.
2329 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2330 const X86Subtarget *Subtarget) {
2331 assert(Subtarget->is64Bit());
2333 if (Subtarget->isCallingConvWin64(CallConv)) {
2334 static const MCPhysReg GPR64ArgRegsWin64[] = {
2335 X86::RCX, X86::RDX, X86::R8, X86::R9
2337 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2340 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2341 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2343 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2346 // FIXME: Get this from tablegen.
2347 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2348 CallingConv::ID CallConv,
2349 const X86Subtarget *Subtarget) {
2350 assert(Subtarget->is64Bit());
2351 if (Subtarget->isCallingConvWin64(CallConv)) {
2352 // The XMM registers which might contain var arg parameters are shadowed
2353 // in their paired GPR. So we only need to save the GPR to their home
2355 // TODO: __vectorcall will change this.
2359 const Function *Fn = MF.getFunction();
2360 bool NoImplicitFloatOps = Fn->getAttributes().
2361 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2362 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2363 "SSE register cannot be used when SSE is disabled!");
2364 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2365 !Subtarget->hasSSE1())
2366 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2370 static const MCPhysReg XMMArgRegs64Bit[] = {
2371 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2372 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2374 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2378 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2379 CallingConv::ID CallConv,
2381 const SmallVectorImpl<ISD::InputArg> &Ins,
2384 SmallVectorImpl<SDValue> &InVals)
2386 MachineFunction &MF = DAG.getMachineFunction();
2387 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2389 const Function* Fn = MF.getFunction();
2390 if (Fn->hasExternalLinkage() &&
2391 Subtarget->isTargetCygMing() &&
2392 Fn->getName() == "main")
2393 FuncInfo->setForceFramePointer(true);
2395 MachineFrameInfo *MFI = MF.getFrameInfo();
2396 bool Is64Bit = Subtarget->is64Bit();
2397 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2399 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2400 "Var args not supported with calling convention fastcc, ghc or hipe");
2402 // Assign locations to all of the incoming arguments.
2403 SmallVector<CCValAssign, 16> ArgLocs;
2404 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2406 // Allocate shadow area for Win64
2408 CCInfo.AllocateStack(32, 8);
2410 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2412 unsigned LastVal = ~0U;
2414 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2415 CCValAssign &VA = ArgLocs[i];
2416 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2418 assert(VA.getValNo() != LastVal &&
2419 "Don't support value assigned to multiple locs yet");
2421 LastVal = VA.getValNo();
2423 if (VA.isRegLoc()) {
2424 EVT RegVT = VA.getLocVT();
2425 const TargetRegisterClass *RC;
2426 if (RegVT == MVT::i32)
2427 RC = &X86::GR32RegClass;
2428 else if (Is64Bit && RegVT == MVT::i64)
2429 RC = &X86::GR64RegClass;
2430 else if (RegVT == MVT::f32)
2431 RC = &X86::FR32RegClass;
2432 else if (RegVT == MVT::f64)
2433 RC = &X86::FR64RegClass;
2434 else if (RegVT.is512BitVector())
2435 RC = &X86::VR512RegClass;
2436 else if (RegVT.is256BitVector())
2437 RC = &X86::VR256RegClass;
2438 else if (RegVT.is128BitVector())
2439 RC = &X86::VR128RegClass;
2440 else if (RegVT == MVT::x86mmx)
2441 RC = &X86::VR64RegClass;
2442 else if (RegVT == MVT::i1)
2443 RC = &X86::VK1RegClass;
2444 else if (RegVT == MVT::v8i1)
2445 RC = &X86::VK8RegClass;
2446 else if (RegVT == MVT::v16i1)
2447 RC = &X86::VK16RegClass;
2448 else if (RegVT == MVT::v32i1)
2449 RC = &X86::VK32RegClass;
2450 else if (RegVT == MVT::v64i1)
2451 RC = &X86::VK64RegClass;
2453 llvm_unreachable("Unknown argument type!");
2455 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2456 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2458 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2459 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2461 if (VA.getLocInfo() == CCValAssign::SExt)
2462 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2463 DAG.getValueType(VA.getValVT()));
2464 else if (VA.getLocInfo() == CCValAssign::ZExt)
2465 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::BCvt)
2468 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2470 if (VA.isExtInLoc()) {
2471 // Handle MMX values passed in XMM regs.
2472 if (RegVT.isVector())
2473 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2475 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2478 assert(VA.isMemLoc());
2479 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2482 // If value is passed via pointer - do a load.
2483 if (VA.getLocInfo() == CCValAssign::Indirect)
2484 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2485 MachinePointerInfo(), false, false, false, 0);
2487 InVals.push_back(ArgValue);
2490 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2491 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2492 // The x86-64 ABIs require that for returning structs by value we copy
2493 // the sret argument into %rax/%eax (depending on ABI) for the return.
2494 // Win32 requires us to put the sret argument to %eax as well.
2495 // Save the argument into a virtual register so that we can access it
2496 // from the return points.
2497 if (Ins[i].Flags.isSRet()) {
2498 unsigned Reg = FuncInfo->getSRetReturnReg();
2500 MVT PtrTy = getPointerTy();
2501 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2502 FuncInfo->setSRetReturnReg(Reg);
2504 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2505 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2511 unsigned StackSize = CCInfo.getNextStackOffset();
2512 // Align stack specially for tail calls.
2513 if (FuncIsMadeTailCallSafe(CallConv,
2514 MF.getTarget().Options.GuaranteedTailCallOpt))
2515 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2517 // If the function takes variable number of arguments, make a frame index for
2518 // the start of the first vararg value... for expansion of llvm.va_start. We
2519 // can skip this if there are no va_start calls.
2520 if (MFI->hasVAStart() &&
2521 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2522 CallConv != CallingConv::X86_ThisCall))) {
2523 FuncInfo->setVarArgsFrameIndex(
2524 MFI->CreateFixedObject(1, StackSize, true));
2527 // 64-bit calling conventions support varargs and register parameters, so we
2528 // have to do extra work to spill them in the prologue or forward them to
2530 if (Is64Bit && isVarArg &&
2531 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2532 // Find the first unallocated argument registers.
2533 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2534 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2535 unsigned NumIntRegs =
2536 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2537 unsigned NumXMMRegs =
2538 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2539 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2540 "SSE register cannot be used when SSE is disabled!");
2542 // Gather all the live in physical registers.
2543 SmallVector<SDValue, 6> LiveGPRs;
2544 SmallVector<SDValue, 8> LiveXMMRegs;
2546 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2547 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2549 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2551 if (!ArgXMMs.empty()) {
2552 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2553 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2554 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2555 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2556 LiveXMMRegs.push_back(
2557 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2561 // Store them to the va_list returned by va_start.
2562 if (MFI->hasVAStart()) {
2564 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2565 // Get to the caller-allocated home save location. Add 8 to account
2566 // for the return address.
2567 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2568 FuncInfo->setRegSaveFrameIndex(
2569 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2570 // Fixup to set vararg frame on shadow area (4 x i64).
2572 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2574 // For X86-64, if there are vararg parameters that are passed via
2575 // registers, then we must store them to their spots on the stack so
2576 // they may be loaded by deferencing the result of va_next.
2577 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2578 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2579 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2580 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2583 // Store the integer parameter registers.
2584 SmallVector<SDValue, 8> MemOps;
2585 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2587 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2588 for (SDValue Val : LiveGPRs) {
2589 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2590 DAG.getIntPtrConstant(Offset));
2592 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2593 MachinePointerInfo::getFixedStack(
2594 FuncInfo->getRegSaveFrameIndex(), Offset),
2596 MemOps.push_back(Store);
2600 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2601 // Now store the XMM (fp + vector) parameter registers.
2602 SmallVector<SDValue, 12> SaveXMMOps;
2603 SaveXMMOps.push_back(Chain);
2604 SaveXMMOps.push_back(ALVal);
2605 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2606 FuncInfo->getRegSaveFrameIndex()));
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getVarArgsFPOffset()));
2609 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2611 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2612 MVT::Other, SaveXMMOps));
2615 if (!MemOps.empty())
2616 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2618 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2619 // to the liveout set on a musttail call.
2620 assert(MFI->hasMustTailInVarArgFunc());
2621 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2622 typedef X86MachineFunctionInfo::Forward Forward;
2624 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2626 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2627 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2628 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2631 if (!ArgXMMs.empty()) {
2633 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2634 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2635 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2637 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2639 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2640 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2642 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2648 // Some CCs need callee pop.
2649 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2650 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2651 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2653 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2654 // If this is an sret function, the return should pop the hidden pointer.
2655 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2656 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2657 argsAreStructReturn(Ins) == StackStructReturn)
2658 FuncInfo->setBytesToPopOnReturn(4);
2662 // RegSaveFrameIndex is X86-64 only.
2663 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2664 if (CallConv == CallingConv::X86_FastCall ||
2665 CallConv == CallingConv::X86_ThisCall)
2666 // fastcc functions can't have varargs.
2667 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2670 FuncInfo->setArgumentStackSize(StackSize);
2676 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2677 SDValue StackPtr, SDValue Arg,
2678 SDLoc dl, SelectionDAG &DAG,
2679 const CCValAssign &VA,
2680 ISD::ArgFlagsTy Flags) const {
2681 unsigned LocMemOffset = VA.getLocMemOffset();
2682 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2683 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2684 if (Flags.isByVal())
2685 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2687 return DAG.getStore(Chain, dl, Arg, PtrOff,
2688 MachinePointerInfo::getStack(LocMemOffset),
2692 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2693 /// optimization is performed and it is required.
2695 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2696 SDValue &OutRetAddr, SDValue Chain,
2697 bool IsTailCall, bool Is64Bit,
2698 int FPDiff, SDLoc dl) const {
2699 // Adjust the Return address stack slot.
2700 EVT VT = getPointerTy();
2701 OutRetAddr = getReturnAddressFrameIndex(DAG);
2703 // Load the "old" Return address.
2704 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2705 false, false, false, 0);
2706 return SDValue(OutRetAddr.getNode(), 1);
2709 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2710 /// optimization is performed and it is required (FPDiff!=0).
2711 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2712 SDValue Chain, SDValue RetAddrFrIdx,
2713 EVT PtrVT, unsigned SlotSize,
2714 int FPDiff, SDLoc dl) {
2715 // Store the return address to the appropriate stack slot.
2716 if (!FPDiff) return Chain;
2717 // Calculate the new stack slot for the return address.
2718 int NewReturnAddrFI =
2719 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2721 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2722 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2723 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2729 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2730 SmallVectorImpl<SDValue> &InVals) const {
2731 SelectionDAG &DAG = CLI.DAG;
2733 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2734 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2735 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2736 SDValue Chain = CLI.Chain;
2737 SDValue Callee = CLI.Callee;
2738 CallingConv::ID CallConv = CLI.CallConv;
2739 bool &isTailCall = CLI.IsTailCall;
2740 bool isVarArg = CLI.IsVarArg;
2742 MachineFunction &MF = DAG.getMachineFunction();
2743 bool Is64Bit = Subtarget->is64Bit();
2744 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2745 StructReturnType SR = callIsStructReturn(Outs);
2746 bool IsSibcall = false;
2747 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2749 if (MF.getTarget().Options.DisableTailCalls)
2752 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2754 // Force this to be a tail call. The verifier rules are enough to ensure
2755 // that we can lower this successfully without moving the return address
2758 } else if (isTailCall) {
2759 // Check if it's really possible to do a tail call.
2760 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2761 isVarArg, SR != NotStructReturn,
2762 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2763 Outs, OutVals, Ins, DAG);
2765 // Sibcalls are automatically detected tailcalls which do not require
2767 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2774 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2775 "Var args not supported with calling convention fastcc, ghc or hipe");
2777 // Analyze operands of the call, assigning locations to each operand.
2778 SmallVector<CCValAssign, 16> ArgLocs;
2779 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2781 // Allocate shadow area for Win64
2783 CCInfo.AllocateStack(32, 8);
2785 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2787 // Get a count of how many bytes are to be pushed on the stack.
2788 unsigned NumBytes = CCInfo.getNextStackOffset();
2790 // This is a sibcall. The memory operands are available in caller's
2791 // own caller's stack.
2793 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2794 IsTailCallConvention(CallConv))
2795 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2798 if (isTailCall && !IsSibcall && !IsMustTail) {
2799 // Lower arguments at fp - stackoffset + fpdiff.
2800 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2802 FPDiff = NumBytesCallerPushed - NumBytes;
2804 // Set the delta of movement of the returnaddr stackslot.
2805 // But only set if delta is greater than previous delta.
2806 if (FPDiff < X86Info->getTCReturnAddrDelta())
2807 X86Info->setTCReturnAddrDelta(FPDiff);
2810 unsigned NumBytesToPush = NumBytes;
2811 unsigned NumBytesToPop = NumBytes;
2813 // If we have an inalloca argument, all stack space has already been allocated
2814 // for us and be right at the top of the stack. We don't support multiple
2815 // arguments passed in memory when using inalloca.
2816 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2818 if (!ArgLocs.back().isMemLoc())
2819 report_fatal_error("cannot use inalloca attribute on a register "
2821 if (ArgLocs.back().getLocMemOffset() != 0)
2822 report_fatal_error("any parameter with the inalloca attribute must be "
2823 "the only memory argument");
2827 Chain = DAG.getCALLSEQ_START(
2828 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2830 SDValue RetAddrFrIdx;
2831 // Load return address for tail calls.
2832 if (isTailCall && FPDiff)
2833 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2834 Is64Bit, FPDiff, dl);
2836 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2837 SmallVector<SDValue, 8> MemOpChains;
2840 // Walk the register/memloc assignments, inserting copies/loads. In the case
2841 // of tail call optimization arguments are handle later.
2842 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2843 DAG.getSubtarget().getRegisterInfo());
2844 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2845 // Skip inalloca arguments, they have already been written.
2846 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2847 if (Flags.isInAlloca())
2850 CCValAssign &VA = ArgLocs[i];
2851 EVT RegVT = VA.getLocVT();
2852 SDValue Arg = OutVals[i];
2853 bool isByVal = Flags.isByVal();
2855 // Promote the value if needed.
2856 switch (VA.getLocInfo()) {
2857 default: llvm_unreachable("Unknown loc info!");
2858 case CCValAssign::Full: break;
2859 case CCValAssign::SExt:
2860 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2862 case CCValAssign::ZExt:
2863 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::AExt:
2866 if (RegVT.is128BitVector()) {
2867 // Special case: passing MMX values in XMM registers.
2868 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2869 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2870 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2872 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2874 case CCValAssign::BCvt:
2875 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2877 case CCValAssign::Indirect: {
2878 // Store the argument.
2879 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2880 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2881 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2882 MachinePointerInfo::getFixedStack(FI),
2889 if (VA.isRegLoc()) {
2890 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2891 if (isVarArg && IsWin64) {
2892 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2893 // shadow reg if callee is a varargs function.
2894 unsigned ShadowReg = 0;
2895 switch (VA.getLocReg()) {
2896 case X86::XMM0: ShadowReg = X86::RCX; break;
2897 case X86::XMM1: ShadowReg = X86::RDX; break;
2898 case X86::XMM2: ShadowReg = X86::R8; break;
2899 case X86::XMM3: ShadowReg = X86::R9; break;
2902 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2904 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2905 assert(VA.isMemLoc());
2906 if (!StackPtr.getNode())
2907 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2909 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2910 dl, DAG, VA, Flags));
2914 if (!MemOpChains.empty())
2915 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2917 if (Subtarget->isPICStyleGOT()) {
2918 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2921 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2922 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2924 // If we are tail calling and generating PIC/GOT style code load the
2925 // address of the callee into ECX. The value in ecx is used as target of
2926 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2927 // for tail calls on PIC/GOT architectures. Normally we would just put the
2928 // address of GOT into ebx and then call target@PLT. But for tail calls
2929 // ebx would be restored (since ebx is callee saved) before jumping to the
2932 // Note: The actual moving to ECX is done further down.
2933 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2934 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2935 !G->getGlobal()->hasProtectedVisibility())
2936 Callee = LowerGlobalAddress(Callee, DAG);
2937 else if (isa<ExternalSymbolSDNode>(Callee))
2938 Callee = LowerExternalSymbol(Callee, DAG);
2942 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2943 // From AMD64 ABI document:
2944 // For calls that may call functions that use varargs or stdargs
2945 // (prototype-less calls or calls to functions containing ellipsis (...) in
2946 // the declaration) %al is used as hidden argument to specify the number
2947 // of SSE registers used. The contents of %al do not need to match exactly
2948 // the number of registers, but must be an ubound on the number of SSE
2949 // registers used and is in the range 0 - 8 inclusive.
2951 // Count the number of XMM registers allocated.
2952 static const MCPhysReg XMMArgRegs[] = {
2953 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2954 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2956 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2957 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2958 && "SSE registers cannot be used when SSE is disabled");
2960 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2961 DAG.getConstant(NumXMMRegs, MVT::i8)));
2964 if (Is64Bit && isVarArg && IsMustTail) {
2965 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2966 for (const auto &F : Forwards) {
2967 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2968 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2972 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2973 // don't need this because the eligibility check rejects calls that require
2974 // shuffling arguments passed in memory.
2975 if (!IsSibcall && isTailCall) {
2976 // Force all the incoming stack arguments to be loaded from the stack
2977 // before any new outgoing arguments are stored to the stack, because the
2978 // outgoing stack slots may alias the incoming argument stack slots, and
2979 // the alias isn't otherwise explicit. This is slightly more conservative
2980 // than necessary, because it means that each store effectively depends
2981 // on every argument instead of just those arguments it would clobber.
2982 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2984 SmallVector<SDValue, 8> MemOpChains2;
2987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2988 CCValAssign &VA = ArgLocs[i];
2991 assert(VA.isMemLoc());
2992 SDValue Arg = OutVals[i];
2993 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2994 // Skip inalloca arguments. They don't require any work.
2995 if (Flags.isInAlloca())
2997 // Create frame index.
2998 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2999 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3000 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3001 FIN = DAG.getFrameIndex(FI, getPointerTy());
3003 if (Flags.isByVal()) {
3004 // Copy relative to framepointer.
3005 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3006 if (!StackPtr.getNode())
3007 StackPtr = DAG.getCopyFromReg(Chain, dl,
3008 RegInfo->getStackRegister(),
3010 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3012 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3016 // Store relative to framepointer.
3017 MemOpChains2.push_back(
3018 DAG.getStore(ArgChain, dl, Arg, FIN,
3019 MachinePointerInfo::getFixedStack(FI),
3024 if (!MemOpChains2.empty())
3025 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3027 // Store the return address to the appropriate stack slot.
3028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3029 getPointerTy(), RegInfo->getSlotSize(),
3033 // Build a sequence of copy-to-reg nodes chained together with token chain
3034 // and flag operands which copy the outgoing args into registers.
3036 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3037 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3038 RegsToPass[i].second, InFlag);
3039 InFlag = Chain.getValue(1);
3042 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3043 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3044 // In the 64-bit large code model, we have to make all calls
3045 // through a register, since the call instruction's 32-bit
3046 // pc-relative offset may not be large enough to hold the whole
3048 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3049 // If the callee is a GlobalAddress node (quite common, every direct call
3050 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3053 // We should use extra load for direct calls to dllimported functions in
3055 const GlobalValue *GV = G->getGlobal();
3056 if (!GV->hasDLLImportStorageClass()) {
3057 unsigned char OpFlags = 0;
3058 bool ExtraLoad = false;
3059 unsigned WrapperKind = ISD::DELETED_NODE;
3061 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3062 // external symbols most go through the PLT in PIC mode. If the symbol
3063 // has hidden or protected visibility, or if it is static or local, then
3064 // we don't need to use the PLT - we can directly call it.
3065 if (Subtarget->isTargetELF() &&
3066 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3067 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3068 OpFlags = X86II::MO_PLT;
3069 } else if (Subtarget->isPICStyleStubAny() &&
3070 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3071 (!Subtarget->getTargetTriple().isMacOSX() ||
3072 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3073 // PC-relative references to external symbols should go through $stub,
3074 // unless we're building with the leopard linker or later, which
3075 // automatically synthesizes these stubs.
3076 OpFlags = X86II::MO_DARWIN_STUB;
3077 } else if (Subtarget->isPICStyleRIPRel() &&
3078 isa<Function>(GV) &&
3079 cast<Function>(GV)->getAttributes().
3080 hasAttribute(AttributeSet::FunctionIndex,
3081 Attribute::NonLazyBind)) {
3082 // If the function is marked as non-lazy, generate an indirect call
3083 // which loads from the GOT directly. This avoids runtime overhead
3084 // at the cost of eager binding (and one extra byte of encoding).
3085 OpFlags = X86II::MO_GOTPCREL;
3086 WrapperKind = X86ISD::WrapperRIP;
3090 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3091 G->getOffset(), OpFlags);
3093 // Add a wrapper if needed.
3094 if (WrapperKind != ISD::DELETED_NODE)
3095 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3096 // Add extra indirection if needed.
3098 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3099 MachinePointerInfo::getGOT(),
3100 false, false, false, 0);
3102 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3103 unsigned char OpFlags = 0;
3105 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3106 // external symbols should go through the PLT.
3107 if (Subtarget->isTargetELF() &&
3108 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3109 OpFlags = X86II::MO_PLT;
3110 } else if (Subtarget->isPICStyleStubAny() &&
3111 (!Subtarget->getTargetTriple().isMacOSX() ||
3112 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3113 // PC-relative references to external symbols should go through $stub,
3114 // unless we're building with the leopard linker or later, which
3115 // automatically synthesizes these stubs.
3116 OpFlags = X86II::MO_DARWIN_STUB;
3119 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3121 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3122 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3123 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3126 // Returns a chain & a flag for retval copy to use.
3127 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3128 SmallVector<SDValue, 8> Ops;
3130 if (!IsSibcall && isTailCall) {
3131 Chain = DAG.getCALLSEQ_END(Chain,
3132 DAG.getIntPtrConstant(NumBytesToPop, true),
3133 DAG.getIntPtrConstant(0, true), InFlag, dl);
3134 InFlag = Chain.getValue(1);
3137 Ops.push_back(Chain);
3138 Ops.push_back(Callee);
3141 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3143 // Add argument registers to the end of the list so that they are known live
3145 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3146 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3147 RegsToPass[i].second.getValueType()));
3149 // Add a register mask operand representing the call-preserved registers.
3150 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3151 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3152 assert(Mask && "Missing call preserved mask for calling convention");
3153 Ops.push_back(DAG.getRegisterMask(Mask));
3155 if (InFlag.getNode())
3156 Ops.push_back(InFlag);
3160 //// If this is the first return lowered for this function, add the regs
3161 //// to the liveout set for the function.
3162 // This isn't right, although it's probably harmless on x86; liveouts
3163 // should be computed from returns not tail calls. Consider a void
3164 // function making a tail call to a function returning int.
3165 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3168 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3169 InFlag = Chain.getValue(1);
3171 // Create the CALLSEQ_END node.
3172 unsigned NumBytesForCalleeToPop;
3173 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3174 DAG.getTarget().Options.GuaranteedTailCallOpt))
3175 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3176 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3177 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3178 SR == StackStructReturn)
3179 // If this is a call to a struct-return function, the callee
3180 // pops the hidden struct pointer, so we have to push it back.
3181 // This is common for Darwin/X86, Linux & Mingw32 targets.
3182 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3183 NumBytesForCalleeToPop = 4;
3185 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3187 // Returns a flag for retval copy to use.
3189 Chain = DAG.getCALLSEQ_END(Chain,
3190 DAG.getIntPtrConstant(NumBytesToPop, true),
3191 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3194 InFlag = Chain.getValue(1);
3197 // Handle result values, copying them out of physregs into vregs that we
3199 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3200 Ins, dl, DAG, InVals);
3203 //===----------------------------------------------------------------------===//
3204 // Fast Calling Convention (tail call) implementation
3205 //===----------------------------------------------------------------------===//
3207 // Like std call, callee cleans arguments, convention except that ECX is
3208 // reserved for storing the tail called function address. Only 2 registers are
3209 // free for argument passing (inreg). Tail call optimization is performed
3211 // * tailcallopt is enabled
3212 // * caller/callee are fastcc
3213 // On X86_64 architecture with GOT-style position independent code only local
3214 // (within module) calls are supported at the moment.
3215 // To keep the stack aligned according to platform abi the function
3216 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3217 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3218 // If a tail called function callee has more arguments than the caller the
3219 // caller needs to make sure that there is room to move the RETADDR to. This is
3220 // achieved by reserving an area the size of the argument delta right after the
3221 // original RETADDR, but before the saved framepointer or the spilled registers
3222 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3234 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3235 /// for a 16 byte align requirement.
3237 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3238 SelectionDAG& DAG) const {
3239 MachineFunction &MF = DAG.getMachineFunction();
3240 const TargetMachine &TM = MF.getTarget();
3241 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3242 TM.getSubtargetImpl()->getRegisterInfo());
3243 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3244 unsigned StackAlignment = TFI.getStackAlignment();
3245 uint64_t AlignMask = StackAlignment - 1;
3246 int64_t Offset = StackSize;
3247 unsigned SlotSize = RegInfo->getSlotSize();
3248 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3249 // Number smaller than 12 so just add the difference.
3250 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3252 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3253 Offset = ((~AlignMask) & Offset) + StackAlignment +
3254 (StackAlignment-SlotSize);
3259 /// MatchingStackOffset - Return true if the given stack call argument is
3260 /// already available in the same position (relatively) of the caller's
3261 /// incoming argument stack.
3263 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3264 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3265 const X86InstrInfo *TII) {
3266 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3268 if (Arg.getOpcode() == ISD::CopyFromReg) {
3269 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3270 if (!TargetRegisterInfo::isVirtualRegister(VR))
3272 MachineInstr *Def = MRI->getVRegDef(VR);
3275 if (!Flags.isByVal()) {
3276 if (!TII->isLoadFromStackSlot(Def, FI))
3279 unsigned Opcode = Def->getOpcode();
3280 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3281 Def->getOperand(1).isFI()) {
3282 FI = Def->getOperand(1).getIndex();
3283 Bytes = Flags.getByValSize();
3287 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3288 if (Flags.isByVal())
3289 // ByVal argument is passed in as a pointer but it's now being
3290 // dereferenced. e.g.
3291 // define @foo(%struct.X* %A) {
3292 // tail call @bar(%struct.X* byval %A)
3295 SDValue Ptr = Ld->getBasePtr();
3296 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3299 FI = FINode->getIndex();
3300 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3301 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3302 FI = FINode->getIndex();
3303 Bytes = Flags.getByValSize();
3307 assert(FI != INT_MAX);
3308 if (!MFI->isFixedObjectIndex(FI))
3310 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3313 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3314 /// for tail call optimization. Targets which want to do tail call
3315 /// optimization should implement this function.
3317 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3318 CallingConv::ID CalleeCC,
3320 bool isCalleeStructRet,
3321 bool isCallerStructRet,
3323 const SmallVectorImpl<ISD::OutputArg> &Outs,
3324 const SmallVectorImpl<SDValue> &OutVals,
3325 const SmallVectorImpl<ISD::InputArg> &Ins,
3326 SelectionDAG &DAG) const {
3327 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3330 // If -tailcallopt is specified, make fastcc functions tail-callable.
3331 const MachineFunction &MF = DAG.getMachineFunction();
3332 const Function *CallerF = MF.getFunction();
3334 // If the function return type is x86_fp80 and the callee return type is not,
3335 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3336 // perform a tailcall optimization here.
3337 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3340 CallingConv::ID CallerCC = CallerF->getCallingConv();
3341 bool CCMatch = CallerCC == CalleeCC;
3342 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3343 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3345 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3346 if (IsTailCallConvention(CalleeCC) && CCMatch)
3351 // Look for obvious safe cases to perform tail call optimization that do not
3352 // require ABI changes. This is what gcc calls sibcall.
3354 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3355 // emit a special epilogue.
3356 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3357 DAG.getSubtarget().getRegisterInfo());
3358 if (RegInfo->needsStackRealignment(MF))
3361 // Also avoid sibcall optimization if either caller or callee uses struct
3362 // return semantics.
3363 if (isCalleeStructRet || isCallerStructRet)
3366 // An stdcall/thiscall caller is expected to clean up its arguments; the
3367 // callee isn't going to do that.
3368 // FIXME: this is more restrictive than needed. We could produce a tailcall
3369 // when the stack adjustment matches. For example, with a thiscall that takes
3370 // only one argument.
3371 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3372 CallerCC == CallingConv::X86_ThisCall))
3375 // Do not sibcall optimize vararg calls unless all arguments are passed via
3377 if (isVarArg && !Outs.empty()) {
3379 // Optimizing for varargs on Win64 is unlikely to be safe without
3380 // additional testing.
3381 if (IsCalleeWin64 || IsCallerWin64)
3384 SmallVector<CCValAssign, 16> ArgLocs;
3385 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3388 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3389 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3390 if (!ArgLocs[i].isRegLoc())
3394 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3395 // stack. Therefore, if it's not used by the call it is not safe to optimize
3396 // this into a sibcall.
3397 bool Unused = false;
3398 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3405 SmallVector<CCValAssign, 16> RVLocs;
3406 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3408 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3409 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3410 CCValAssign &VA = RVLocs[i];
3411 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3416 // If the calling conventions do not match, then we'd better make sure the
3417 // results are returned in the same way as what the caller expects.
3419 SmallVector<CCValAssign, 16> RVLocs1;
3420 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3422 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3424 SmallVector<CCValAssign, 16> RVLocs2;
3425 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3427 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3429 if (RVLocs1.size() != RVLocs2.size())
3431 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3432 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3434 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3436 if (RVLocs1[i].isRegLoc()) {
3437 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3440 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3446 // If the callee takes no arguments then go on to check the results of the
3448 if (!Outs.empty()) {
3449 // Check if stack adjustment is needed. For now, do not do this if any
3450 // argument is passed on the stack.
3451 SmallVector<CCValAssign, 16> ArgLocs;
3452 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3455 // Allocate shadow area for Win64
3457 CCInfo.AllocateStack(32, 8);
3459 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3460 if (CCInfo.getNextStackOffset()) {
3461 MachineFunction &MF = DAG.getMachineFunction();
3462 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3465 // Check if the arguments are already laid out in the right way as
3466 // the caller's fixed stack objects.
3467 MachineFrameInfo *MFI = MF.getFrameInfo();
3468 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3469 const X86InstrInfo *TII =
3470 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3471 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3472 CCValAssign &VA = ArgLocs[i];
3473 SDValue Arg = OutVals[i];
3474 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3475 if (VA.getLocInfo() == CCValAssign::Indirect)
3477 if (!VA.isRegLoc()) {
3478 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3485 // If the tailcall address may be in a register, then make sure it's
3486 // possible to register allocate for it. In 32-bit, the call address can
3487 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3488 // callee-saved registers are restored. These happen to be the same
3489 // registers used to pass 'inreg' arguments so watch out for those.
3490 if (!Subtarget->is64Bit() &&
3491 ((!isa<GlobalAddressSDNode>(Callee) &&
3492 !isa<ExternalSymbolSDNode>(Callee)) ||
3493 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3494 unsigned NumInRegs = 0;
3495 // In PIC we need an extra register to formulate the address computation
3497 unsigned MaxInRegs =
3498 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3500 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3501 CCValAssign &VA = ArgLocs[i];
3504 unsigned Reg = VA.getLocReg();
3507 case X86::EAX: case X86::EDX: case X86::ECX:
3508 if (++NumInRegs == MaxInRegs)
3520 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3521 const TargetLibraryInfo *libInfo) const {
3522 return X86::createFastISel(funcInfo, libInfo);
3525 //===----------------------------------------------------------------------===//
3526 // Other Lowering Hooks
3527 //===----------------------------------------------------------------------===//
3529 static bool MayFoldLoad(SDValue Op) {
3530 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3533 static bool MayFoldIntoStore(SDValue Op) {
3534 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3537 static bool isTargetShuffle(unsigned Opcode) {
3539 default: return false;
3540 case X86ISD::BLENDI:
3541 case X86ISD::PSHUFB:
3542 case X86ISD::PSHUFD:
3543 case X86ISD::PSHUFHW:
3544 case X86ISD::PSHUFLW:
3546 case X86ISD::PALIGNR:
3547 case X86ISD::MOVLHPS:
3548 case X86ISD::MOVLHPD:
3549 case X86ISD::MOVHLPS:
3550 case X86ISD::MOVLPS:
3551 case X86ISD::MOVLPD:
3552 case X86ISD::MOVSHDUP:
3553 case X86ISD::MOVSLDUP:
3554 case X86ISD::MOVDDUP:
3557 case X86ISD::UNPCKL:
3558 case X86ISD::UNPCKH:
3559 case X86ISD::VPERMILPI:
3560 case X86ISD::VPERM2X128:
3561 case X86ISD::VPERMI:
3566 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3567 SDValue V1, SelectionDAG &DAG) {
3569 default: llvm_unreachable("Unknown x86 shuffle node");
3570 case X86ISD::MOVSHDUP:
3571 case X86ISD::MOVSLDUP:
3572 case X86ISD::MOVDDUP:
3573 return DAG.getNode(Opc, dl, VT, V1);
3577 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3578 SDValue V1, unsigned TargetMask,
3579 SelectionDAG &DAG) {
3581 default: llvm_unreachable("Unknown x86 shuffle node");
3582 case X86ISD::PSHUFD:
3583 case X86ISD::PSHUFHW:
3584 case X86ISD::PSHUFLW:
3585 case X86ISD::VPERMILPI:
3586 case X86ISD::VPERMI:
3587 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3591 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3592 SDValue V1, SDValue V2, unsigned TargetMask,
3593 SelectionDAG &DAG) {
3595 default: llvm_unreachable("Unknown x86 shuffle node");
3596 case X86ISD::PALIGNR:
3597 case X86ISD::VALIGN:
3599 case X86ISD::VPERM2X128:
3600 return DAG.getNode(Opc, dl, VT, V1, V2,
3601 DAG.getConstant(TargetMask, MVT::i8));
3605 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3606 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3608 default: llvm_unreachable("Unknown x86 shuffle node");
3609 case X86ISD::MOVLHPS:
3610 case X86ISD::MOVLHPD:
3611 case X86ISD::MOVHLPS:
3612 case X86ISD::MOVLPS:
3613 case X86ISD::MOVLPD:
3616 case X86ISD::UNPCKL:
3617 case X86ISD::UNPCKH:
3618 return DAG.getNode(Opc, dl, VT, V1, V2);
3622 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3623 MachineFunction &MF = DAG.getMachineFunction();
3624 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3625 DAG.getSubtarget().getRegisterInfo());
3626 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3627 int ReturnAddrIndex = FuncInfo->getRAIndex();
3629 if (ReturnAddrIndex == 0) {
3630 // Set up a frame object for the return address.
3631 unsigned SlotSize = RegInfo->getSlotSize();
3632 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3635 FuncInfo->setRAIndex(ReturnAddrIndex);
3638 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3641 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3642 bool hasSymbolicDisplacement) {
3643 // Offset should fit into 32 bit immediate field.
3644 if (!isInt<32>(Offset))
3647 // If we don't have a symbolic displacement - we don't have any extra
3649 if (!hasSymbolicDisplacement)
3652 // FIXME: Some tweaks might be needed for medium code model.
3653 if (M != CodeModel::Small && M != CodeModel::Kernel)
3656 // For small code model we assume that latest object is 16MB before end of 31
3657 // bits boundary. We may also accept pretty large negative constants knowing
3658 // that all objects are in the positive half of address space.
3659 if (M == CodeModel::Small && Offset < 16*1024*1024)
3662 // For kernel code model we know that all object resist in the negative half
3663 // of 32bits address space. We may not accept negative offsets, since they may
3664 // be just off and we may accept pretty large positive ones.
3665 if (M == CodeModel::Kernel && Offset > 0)
3671 /// isCalleePop - Determines whether the callee is required to pop its
3672 /// own arguments. Callee pop is necessary to support tail calls.
3673 bool X86::isCalleePop(CallingConv::ID CallingConv,
3674 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3675 switch (CallingConv) {
3678 case CallingConv::X86_StdCall:
3679 case CallingConv::X86_FastCall:
3680 case CallingConv::X86_ThisCall:
3682 case CallingConv::Fast:
3683 case CallingConv::GHC:
3684 case CallingConv::HiPE:
3691 /// \brief Return true if the condition is an unsigned comparison operation.
3692 static bool isX86CCUnsigned(unsigned X86CC) {
3694 default: llvm_unreachable("Invalid integer condition!");
3695 case X86::COND_E: return true;
3696 case X86::COND_G: return false;
3697 case X86::COND_GE: return false;
3698 case X86::COND_L: return false;
3699 case X86::COND_LE: return false;
3700 case X86::COND_NE: return true;
3701 case X86::COND_B: return true;
3702 case X86::COND_A: return true;
3703 case X86::COND_BE: return true;
3704 case X86::COND_AE: return true;
3706 llvm_unreachable("covered switch fell through?!");
3709 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3710 /// specific condition code, returning the condition code and the LHS/RHS of the
3711 /// comparison to make.
3712 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3713 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3715 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3716 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3717 // X > -1 -> X == 0, jump !sign.
3718 RHS = DAG.getConstant(0, RHS.getValueType());
3719 return X86::COND_NS;
3721 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3722 // X < 0 -> X == 0, jump on sign.
3725 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3727 RHS = DAG.getConstant(0, RHS.getValueType());
3728 return X86::COND_LE;
3732 switch (SetCCOpcode) {
3733 default: llvm_unreachable("Invalid integer condition!");
3734 case ISD::SETEQ: return X86::COND_E;
3735 case ISD::SETGT: return X86::COND_G;
3736 case ISD::SETGE: return X86::COND_GE;
3737 case ISD::SETLT: return X86::COND_L;
3738 case ISD::SETLE: return X86::COND_LE;
3739 case ISD::SETNE: return X86::COND_NE;
3740 case ISD::SETULT: return X86::COND_B;
3741 case ISD::SETUGT: return X86::COND_A;
3742 case ISD::SETULE: return X86::COND_BE;
3743 case ISD::SETUGE: return X86::COND_AE;
3747 // First determine if it is required or is profitable to flip the operands.
3749 // If LHS is a foldable load, but RHS is not, flip the condition.
3750 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3751 !ISD::isNON_EXTLoad(RHS.getNode())) {
3752 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3753 std::swap(LHS, RHS);
3756 switch (SetCCOpcode) {
3762 std::swap(LHS, RHS);
3766 // On a floating point condition, the flags are set as follows:
3768 // 0 | 0 | 0 | X > Y
3769 // 0 | 0 | 1 | X < Y
3770 // 1 | 0 | 0 | X == Y
3771 // 1 | 1 | 1 | unordered
3772 switch (SetCCOpcode) {
3773 default: llvm_unreachable("Condcode should be pre-legalized away");
3775 case ISD::SETEQ: return X86::COND_E;
3776 case ISD::SETOLT: // flipped
3778 case ISD::SETGT: return X86::COND_A;
3779 case ISD::SETOLE: // flipped
3781 case ISD::SETGE: return X86::COND_AE;
3782 case ISD::SETUGT: // flipped
3784 case ISD::SETLT: return X86::COND_B;
3785 case ISD::SETUGE: // flipped
3787 case ISD::SETLE: return X86::COND_BE;
3789 case ISD::SETNE: return X86::COND_NE;
3790 case ISD::SETUO: return X86::COND_P;
3791 case ISD::SETO: return X86::COND_NP;
3793 case ISD::SETUNE: return X86::COND_INVALID;
3797 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3798 /// code. Current x86 isa includes the following FP cmov instructions:
3799 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3800 static bool hasFPCMov(unsigned X86CC) {
3816 /// isFPImmLegal - Returns true if the target can instruction select the
3817 /// specified FP immediate natively. If false, the legalizer will
3818 /// materialize the FP immediate as a load from a constant pool.
3819 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3820 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3821 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3827 /// \brief Returns true if it is beneficial to convert a load of a constant
3828 /// to just the constant itself.
3829 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3831 assert(Ty->isIntegerTy());
3833 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3834 if (BitSize == 0 || BitSize > 64)
3839 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3840 /// the specified range (L, H].
3841 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3842 return (Val < 0) || (Val >= Low && Val < Hi);
3845 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3846 /// specified value.
3847 static bool isUndefOrEqual(int Val, int CmpVal) {
3848 return (Val < 0 || Val == CmpVal);
3851 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3852 /// from position Pos and ending in Pos+Size, falls within the specified
3853 /// sequential range (L, L+Pos]. or is undef.
3854 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3855 unsigned Pos, unsigned Size, int Low) {
3856 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3857 if (!isUndefOrEqual(Mask[i], Low))
3862 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3863 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3864 /// operand - by default will match for first operand.
3865 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3866 bool TestSecondOperand = false) {
3867 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3868 VT != MVT::v2f64 && VT != MVT::v2i64)
3871 unsigned NumElems = VT.getVectorNumElements();
3872 unsigned Lo = TestSecondOperand ? NumElems : 0;
3873 unsigned Hi = Lo + NumElems;
3875 for (unsigned i = 0; i < NumElems; ++i)
3876 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3882 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3883 /// is suitable for input to PSHUFHW.
3884 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3885 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3888 // Lower quadword copied in order or undef.
3889 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3892 // Upper quadword shuffled.
3893 for (unsigned i = 4; i != 8; ++i)
3894 if (!isUndefOrInRange(Mask[i], 4, 8))
3897 if (VT == MVT::v16i16) {
3898 // Lower quadword copied in order or undef.
3899 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3902 // Upper quadword shuffled.
3903 for (unsigned i = 12; i != 16; ++i)
3904 if (!isUndefOrInRange(Mask[i], 12, 16))
3911 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3912 /// is suitable for input to PSHUFLW.
3913 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3914 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3917 // Upper quadword copied in order.
3918 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3921 // Lower quadword shuffled.
3922 for (unsigned i = 0; i != 4; ++i)
3923 if (!isUndefOrInRange(Mask[i], 0, 4))
3926 if (VT == MVT::v16i16) {
3927 // Upper quadword copied in order.
3928 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3931 // Lower quadword shuffled.
3932 for (unsigned i = 8; i != 12; ++i)
3933 if (!isUndefOrInRange(Mask[i], 8, 12))
3940 /// \brief Return true if the mask specifies a shuffle of elements that is
3941 /// suitable for input to intralane (palignr) or interlane (valign) vector
3943 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3944 unsigned NumElts = VT.getVectorNumElements();
3945 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3946 unsigned NumLaneElts = NumElts/NumLanes;
3948 // Do not handle 64-bit element shuffles with palignr.
3949 if (NumLaneElts == 2)
3952 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3954 for (i = 0; i != NumLaneElts; ++i) {
3959 // Lane is all undef, go to next lane
3960 if (i == NumLaneElts)
3963 int Start = Mask[i+l];
3965 // Make sure its in this lane in one of the sources
3966 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3967 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3970 // If not lane 0, then we must match lane 0
3971 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3974 // Correct second source to be contiguous with first source
3975 if (Start >= (int)NumElts)
3976 Start -= NumElts - NumLaneElts;
3978 // Make sure we're shifting in the right direction.
3979 if (Start <= (int)(i+l))
3984 // Check the rest of the elements to see if they are consecutive.
3985 for (++i; i != NumLaneElts; ++i) {
3986 int Idx = Mask[i+l];
3988 // Make sure its in this lane
3989 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3990 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3993 // If not lane 0, then we must match lane 0
3994 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3997 if (Idx >= (int)NumElts)
3998 Idx -= NumElts - NumLaneElts;
4000 if (!isUndefOrEqual(Idx, Start+i))
4009 /// \brief Return true if the node specifies a shuffle of elements that is
4010 /// suitable for input to PALIGNR.
4011 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4012 const X86Subtarget *Subtarget) {
4013 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4014 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4015 VT.is512BitVector())
4016 // FIXME: Add AVX512BW.
4019 return isAlignrMask(Mask, VT, false);
4022 /// \brief Return true if the node specifies a shuffle of elements that is
4023 /// suitable for input to VALIGN.
4024 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4025 const X86Subtarget *Subtarget) {
4026 // FIXME: Add AVX512VL.
4027 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4029 return isAlignrMask(Mask, VT, true);
4032 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4033 /// the two vector operands have swapped position.
4034 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4035 unsigned NumElems) {
4036 for (unsigned i = 0; i != NumElems; ++i) {
4040 else if (idx < (int)NumElems)
4041 Mask[i] = idx + NumElems;
4043 Mask[i] = idx - NumElems;
4047 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4048 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4049 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4050 /// reverse of what x86 shuffles want.
4051 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4053 unsigned NumElems = VT.getVectorNumElements();
4054 unsigned NumLanes = VT.getSizeInBits()/128;
4055 unsigned NumLaneElems = NumElems/NumLanes;
4057 if (NumLaneElems != 2 && NumLaneElems != 4)
4060 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4061 bool symetricMaskRequired =
4062 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4064 // VSHUFPSY divides the resulting vector into 4 chunks.
4065 // The sources are also splitted into 4 chunks, and each destination
4066 // chunk must come from a different source chunk.
4068 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4069 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4071 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4072 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4074 // VSHUFPDY divides the resulting vector into 4 chunks.
4075 // The sources are also splitted into 4 chunks, and each destination
4076 // chunk must come from a different source chunk.
4078 // SRC1 => X3 X2 X1 X0
4079 // SRC2 => Y3 Y2 Y1 Y0
4081 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4083 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4084 unsigned HalfLaneElems = NumLaneElems/2;
4085 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4086 for (unsigned i = 0; i != NumLaneElems; ++i) {
4087 int Idx = Mask[i+l];
4088 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4089 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4091 // For VSHUFPSY, the mask of the second half must be the same as the
4092 // first but with the appropriate offsets. This works in the same way as
4093 // VPERMILPS works with masks.
4094 if (!symetricMaskRequired || Idx < 0)
4096 if (MaskVal[i] < 0) {
4097 MaskVal[i] = Idx - l;
4100 if ((signed)(Idx - l) != MaskVal[i])
4108 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4109 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4110 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4111 if (!VT.is128BitVector())
4114 unsigned NumElems = VT.getVectorNumElements();
4119 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4120 return isUndefOrEqual(Mask[0], 6) &&
4121 isUndefOrEqual(Mask[1], 7) &&
4122 isUndefOrEqual(Mask[2], 2) &&
4123 isUndefOrEqual(Mask[3], 3);
4126 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4127 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4129 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4130 if (!VT.is128BitVector())
4133 unsigned NumElems = VT.getVectorNumElements();
4138 return isUndefOrEqual(Mask[0], 2) &&
4139 isUndefOrEqual(Mask[1], 3) &&
4140 isUndefOrEqual(Mask[2], 2) &&
4141 isUndefOrEqual(Mask[3], 3);
4144 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4145 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4146 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4147 if (!VT.is128BitVector())
4150 unsigned NumElems = VT.getVectorNumElements();
4152 if (NumElems != 2 && NumElems != 4)
4155 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4156 if (!isUndefOrEqual(Mask[i], i + NumElems))
4159 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4160 if (!isUndefOrEqual(Mask[i], i))
4166 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4167 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4168 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4169 if (!VT.is128BitVector())
4172 unsigned NumElems = VT.getVectorNumElements();
4174 if (NumElems != 2 && NumElems != 4)
4177 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4178 if (!isUndefOrEqual(Mask[i], i))
4181 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4182 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4188 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4189 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4190 /// i. e: If all but one element come from the same vector.
4191 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4192 // TODO: Deal with AVX's VINSERTPS
4193 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4196 unsigned CorrectPosV1 = 0;
4197 unsigned CorrectPosV2 = 0;
4198 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4199 if (Mask[i] == -1) {
4207 else if (Mask[i] == i + 4)
4211 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4212 // We have 3 elements (undefs count as elements from any vector) from one
4213 // vector, and one from another.
4220 // Some special combinations that can be optimized.
4223 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4224 SelectionDAG &DAG) {
4225 MVT VT = SVOp->getSimpleValueType(0);
4228 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4231 ArrayRef<int> Mask = SVOp->getMask();
4233 // These are the special masks that may be optimized.
4234 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4235 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4236 bool MatchEvenMask = true;
4237 bool MatchOddMask = true;
4238 for (int i=0; i<8; ++i) {
4239 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4240 MatchEvenMask = false;
4241 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4242 MatchOddMask = false;
4245 if (!MatchEvenMask && !MatchOddMask)
4248 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4250 SDValue Op0 = SVOp->getOperand(0);
4251 SDValue Op1 = SVOp->getOperand(1);
4253 if (MatchEvenMask) {
4254 // Shift the second operand right to 32 bits.
4255 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4256 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4258 // Shift the first operand left to 32 bits.
4259 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4260 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4262 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4263 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4266 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4267 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4268 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4269 bool HasInt256, bool V2IsSplat = false) {
4271 assert(VT.getSizeInBits() >= 128 &&
4272 "Unsupported vector type for unpckl");
4274 unsigned NumElts = VT.getVectorNumElements();
4275 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4276 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4279 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4280 "Unsupported vector type for unpckh");
4282 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4293 if (!isUndefOrEqual(BitI1, NumElts))
4296 if (!isUndefOrEqual(BitI1, j + NumElts))
4305 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4306 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4307 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4308 bool HasInt256, bool V2IsSplat = false) {
4309 assert(VT.getSizeInBits() >= 128 &&
4310 "Unsupported vector type for unpckh");
4312 unsigned NumElts = VT.getVectorNumElements();
4313 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4314 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4317 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4318 "Unsupported vector type for unpckh");
4320 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4321 unsigned NumLanes = VT.getSizeInBits()/128;
4322 unsigned NumLaneElts = NumElts/NumLanes;
4324 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4325 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4326 int BitI = Mask[l+i];
4327 int BitI1 = Mask[l+i+1];
4328 if (!isUndefOrEqual(BitI, j))
4331 if (isUndefOrEqual(BitI1, NumElts))
4334 if (!isUndefOrEqual(BitI1, j+NumElts))
4342 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4343 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4345 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4346 unsigned NumElts = VT.getVectorNumElements();
4347 bool Is256BitVec = VT.is256BitVector();
4349 if (VT.is512BitVector())
4351 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4352 "Unsupported vector type for unpckh");
4354 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4355 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4358 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4359 // FIXME: Need a better way to get rid of this, there's no latency difference
4360 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4361 // the former later. We should also remove the "_undef" special mask.
4362 if (NumElts == 4 && Is256BitVec)
4365 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4366 // independently on 128-bit lanes.
4367 unsigned NumLanes = VT.getSizeInBits()/128;
4368 unsigned NumLaneElts = NumElts/NumLanes;
4370 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4371 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4372 int BitI = Mask[l+i];
4373 int BitI1 = Mask[l+i+1];
4375 if (!isUndefOrEqual(BitI, j))
4377 if (!isUndefOrEqual(BitI1, j))
4385 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4386 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4388 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4389 unsigned NumElts = VT.getVectorNumElements();
4391 if (VT.is512BitVector())
4394 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4395 "Unsupported vector type for unpckh");
4397 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4398 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4401 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4402 // independently on 128-bit lanes.
4403 unsigned NumLanes = VT.getSizeInBits()/128;
4404 unsigned NumLaneElts = NumElts/NumLanes;
4406 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4407 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4408 int BitI = Mask[l+i];
4409 int BitI1 = Mask[l+i+1];
4410 if (!isUndefOrEqual(BitI, j))
4412 if (!isUndefOrEqual(BitI1, j))
4419 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4420 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4421 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4422 if (!VT.is512BitVector())
4425 unsigned NumElts = VT.getVectorNumElements();
4426 unsigned HalfSize = NumElts/2;
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4434 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4442 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4443 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4444 /// MOVSD, and MOVD, i.e. setting the lowest element.
4445 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4446 if (VT.getVectorElementType().getSizeInBits() < 32)
4448 if (!VT.is128BitVector())
4451 unsigned NumElts = VT.getVectorNumElements();
4453 if (!isUndefOrEqual(Mask[0], NumElts))
4456 for (unsigned i = 1; i != NumElts; ++i)
4457 if (!isUndefOrEqual(Mask[i], i))
4463 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4464 /// as permutations between 128-bit chunks or halves. As an example: this
4466 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4467 /// The first half comes from the second half of V1 and the second half from the
4468 /// the second half of V2.
4469 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4470 if (!HasFp256 || !VT.is256BitVector())
4473 // The shuffle result is divided into half A and half B. In total the two
4474 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4475 // B must come from C, D, E or F.
4476 unsigned HalfSize = VT.getVectorNumElements()/2;
4477 bool MatchA = false, MatchB = false;
4479 // Check if A comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4487 // Check if B comes from one of C, D, E, F.
4488 for (unsigned Half = 0; Half != 4; ++Half) {
4489 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4495 return MatchA && MatchB;
4498 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4499 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4500 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4501 MVT VT = SVOp->getSimpleValueType(0);
4503 unsigned HalfSize = VT.getVectorNumElements()/2;
4505 unsigned FstHalf = 0, SndHalf = 0;
4506 for (unsigned i = 0; i < HalfSize; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4512 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4513 if (SVOp->getMaskElt(i) > 0) {
4514 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4519 return (FstHalf | (SndHalf << 4));
4522 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4523 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4524 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4528 unsigned NumElts = VT.getVectorNumElements();
4530 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4531 for (unsigned i = 0; i != NumElts; ++i) {
4534 Imm8 |= Mask[i] << (i*2);
4539 unsigned LaneSize = 4;
4540 SmallVector<int, 4> MaskVal(LaneSize, -1);
4542 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4543 for (unsigned i = 0; i != LaneSize; ++i) {
4544 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4548 if (MaskVal[i] < 0) {
4549 MaskVal[i] = Mask[i+l] - l;
4550 Imm8 |= MaskVal[i] << (i*2);
4553 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4560 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4561 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4562 /// Note that VPERMIL mask matching is different depending whether theunderlying
4563 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4564 /// to the same elements of the low, but to the higher half of the source.
4565 /// In VPERMILPD the two lanes could be shuffled independently of each other
4566 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4567 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4568 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4569 if (VT.getSizeInBits() < 256 || EltSize < 32)
4571 bool symetricMaskRequired = (EltSize == 32);
4572 unsigned NumElts = VT.getVectorNumElements();
4574 unsigned NumLanes = VT.getSizeInBits()/128;
4575 unsigned LaneSize = NumElts/NumLanes;
4576 // 2 or 4 elements in one lane
4578 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4579 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4580 for (unsigned i = 0; i != LaneSize; ++i) {
4581 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4583 if (symetricMaskRequired) {
4584 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4585 ExpectedMaskVal[i] = Mask[i+l] - l;
4588 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4596 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4597 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4598 /// element of vector 2 and the other elements to come from vector 1 in order.
4599 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4600 bool V2IsSplat = false, bool V2IsUndef = false) {
4601 if (!VT.is128BitVector())
4604 unsigned NumOps = VT.getVectorNumElements();
4605 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4608 if (!isUndefOrEqual(Mask[0], 0))
4611 for (unsigned i = 1; i != NumOps; ++i)
4612 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4613 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4614 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4620 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4621 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4622 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4623 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4624 const X86Subtarget *Subtarget) {
4625 if (!Subtarget->hasSSE3())
4628 unsigned NumElems = VT.getVectorNumElements();
4630 if ((VT.is128BitVector() && NumElems != 4) ||
4631 (VT.is256BitVector() && NumElems != 8) ||
4632 (VT.is512BitVector() && NumElems != 16))
4635 // "i+1" is the value the indexed mask element must have
4636 for (unsigned i = 0; i != NumElems; i += 2)
4637 if (!isUndefOrEqual(Mask[i], i+1) ||
4638 !isUndefOrEqual(Mask[i+1], i+1))
4644 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4645 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4646 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4647 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4648 const X86Subtarget *Subtarget) {
4649 if (!Subtarget->hasSSE3())
4652 unsigned NumElems = VT.getVectorNumElements();
4654 if ((VT.is128BitVector() && NumElems != 4) ||
4655 (VT.is256BitVector() && NumElems != 8) ||
4656 (VT.is512BitVector() && NumElems != 16))
4659 // "i" is the value the indexed mask element must have
4660 for (unsigned i = 0; i != NumElems; i += 2)
4661 if (!isUndefOrEqual(Mask[i], i) ||
4662 !isUndefOrEqual(Mask[i+1], i))
4668 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4669 /// specifies a shuffle of elements that is suitable for input to 256-bit
4670 /// version of MOVDDUP.
4671 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4672 if (!HasFp256 || !VT.is256BitVector())
4675 unsigned NumElts = VT.getVectorNumElements();
4679 for (unsigned i = 0; i != NumElts/2; ++i)
4680 if (!isUndefOrEqual(Mask[i], 0))
4682 for (unsigned i = NumElts/2; i != NumElts; ++i)
4683 if (!isUndefOrEqual(Mask[i], NumElts/2))
4688 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4689 /// specifies a shuffle of elements that is suitable for input to 128-bit
4690 /// version of MOVDDUP.
4691 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4692 if (!VT.is128BitVector())
4695 unsigned e = VT.getVectorNumElements() / 2;
4696 for (unsigned i = 0; i != e; ++i)
4697 if (!isUndefOrEqual(Mask[i], i))
4699 for (unsigned i = 0; i != e; ++i)
4700 if (!isUndefOrEqual(Mask[e+i], i))
4705 /// isVEXTRACTIndex - Return true if the specified
4706 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4707 /// suitable for instruction that extract 128 or 256 bit vectors
4708 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4709 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4710 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4713 // The index should be aligned on a vecWidth-bit boundary.
4715 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4717 MVT VT = N->getSimpleValueType(0);
4718 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4719 bool Result = (Index * ElSize) % vecWidth == 0;
4724 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4725 /// operand specifies a subvector insert that is suitable for input to
4726 /// insertion of 128 or 256-bit subvectors
4727 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4728 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4729 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4731 // The index should be aligned on a vecWidth-bit boundary.
4733 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4735 MVT VT = N->getSimpleValueType(0);
4736 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4737 bool Result = (Index * ElSize) % vecWidth == 0;
4742 bool X86::isVINSERT128Index(SDNode *N) {
4743 return isVINSERTIndex(N, 128);
4746 bool X86::isVINSERT256Index(SDNode *N) {
4747 return isVINSERTIndex(N, 256);
4750 bool X86::isVEXTRACT128Index(SDNode *N) {
4751 return isVEXTRACTIndex(N, 128);
4754 bool X86::isVEXTRACT256Index(SDNode *N) {
4755 return isVEXTRACTIndex(N, 256);
4758 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4759 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4760 /// Handles 128-bit and 256-bit.
4761 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4762 MVT VT = N->getSimpleValueType(0);
4764 assert((VT.getSizeInBits() >= 128) &&
4765 "Unsupported vector type for PSHUF/SHUFP");
4767 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4768 // independently on 128-bit lanes.
4769 unsigned NumElts = VT.getVectorNumElements();
4770 unsigned NumLanes = VT.getSizeInBits()/128;
4771 unsigned NumLaneElts = NumElts/NumLanes;
4773 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4774 "Only supports 2, 4 or 8 elements per lane");
4776 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4778 for (unsigned i = 0; i != NumElts; ++i) {
4779 int Elt = N->getMaskElt(i);
4780 if (Elt < 0) continue;
4781 Elt &= NumLaneElts - 1;
4782 unsigned ShAmt = (i << Shift) % 8;
4783 Mask |= Elt << ShAmt;
4789 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4790 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4791 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4792 MVT VT = N->getSimpleValueType(0);
4794 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4795 "Unsupported vector type for PSHUFHW");
4797 unsigned NumElts = VT.getVectorNumElements();
4800 for (unsigned l = 0; l != NumElts; l += 8) {
4801 // 8 nodes per lane, but we only care about the last 4.
4802 for (unsigned i = 0; i < 4; ++i) {
4803 int Elt = N->getMaskElt(l+i+4);
4804 if (Elt < 0) continue;
4805 Elt &= 0x3; // only 2-bits.
4806 Mask |= Elt << (i * 2);
4813 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4814 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4815 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4816 MVT VT = N->getSimpleValueType(0);
4818 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4819 "Unsupported vector type for PSHUFHW");
4821 unsigned NumElts = VT.getVectorNumElements();
4824 for (unsigned l = 0; l != NumElts; l += 8) {
4825 // 8 nodes per lane, but we only care about the first 4.
4826 for (unsigned i = 0; i < 4; ++i) {
4827 int Elt = N->getMaskElt(l+i);
4828 if (Elt < 0) continue;
4829 Elt &= 0x3; // only 2-bits
4830 Mask |= Elt << (i * 2);
4837 /// \brief Return the appropriate immediate to shuffle the specified
4838 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4839 /// VALIGN (if Interlane is true) instructions.
4840 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4842 MVT VT = SVOp->getSimpleValueType(0);
4843 unsigned EltSize = InterLane ? 1 :
4844 VT.getVectorElementType().getSizeInBits() >> 3;
4846 unsigned NumElts = VT.getVectorNumElements();
4847 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4848 unsigned NumLaneElts = NumElts/NumLanes;
4852 for (i = 0; i != NumElts; ++i) {
4853 Val = SVOp->getMaskElt(i);
4857 if (Val >= (int)NumElts)
4858 Val -= NumElts - NumLaneElts;
4860 assert(Val - i > 0 && "PALIGNR imm should be positive");
4861 return (Val - i) * EltSize;
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4866 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, false);
4870 /// \brief Return the appropriate immediate to shuffle the specified
4871 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4872 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4873 return getShuffleAlignrImmediate(SVOp, true);
4877 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4878 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4879 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4880 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4883 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4885 MVT VecVT = N->getOperand(0).getSimpleValueType();
4886 MVT ElVT = VecVT.getVectorElementType();
4888 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4889 return Index / NumElemsPerChunk;
4892 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4893 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4894 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4895 llvm_unreachable("Illegal insert subvector for VINSERT");
4898 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4900 MVT VecVT = N->getSimpleValueType(0);
4901 MVT ElVT = VecVT.getVectorElementType();
4903 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4904 return Index / NumElemsPerChunk;
4907 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4909 /// and VINSERTI128 instructions.
4910 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 128);
4914 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4915 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4916 /// and VINSERTI64x4 instructions.
4917 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4918 return getExtractVEXTRACTImmediate(N, 256);
4921 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4923 /// and VINSERTI128 instructions.
4924 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 128);
4928 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4929 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4930 /// and VINSERTI64x4 instructions.
4931 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4932 return getInsertVINSERTImmediate(N, 256);
4935 /// isZero - Returns true if Elt is a constant integer zero
4936 static bool isZero(SDValue V) {
4937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4938 return C && C->isNullValue();
4941 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4943 bool X86::isZeroNode(SDValue Elt) {
4946 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4947 return CFP->getValueAPF().isPosZero();
4951 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4952 /// match movhlps. The lower half elements should come from upper half of
4953 /// V1 (and in order), and the upper half elements should come from the upper
4954 /// half of V2 (and in order).
4955 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4956 if (!VT.is128BitVector())
4958 if (VT.getVectorNumElements() != 4)
4960 for (unsigned i = 0, e = 2; i != e; ++i)
4961 if (!isUndefOrEqual(Mask[i], i+2))
4963 for (unsigned i = 2; i != 4; ++i)
4964 if (!isUndefOrEqual(Mask[i], i+4))
4969 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4970 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4972 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4973 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4975 N = N->getOperand(0).getNode();
4976 if (!ISD::isNON_EXTLoad(N))
4979 *LD = cast<LoadSDNode>(N);
4983 // Test whether the given value is a vector value which will be legalized
4985 static bool WillBeConstantPoolLoad(SDNode *N) {
4986 if (N->getOpcode() != ISD::BUILD_VECTOR)
4989 // Check for any non-constant elements.
4990 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4991 switch (N->getOperand(i).getNode()->getOpcode()) {
4993 case ISD::ConstantFP:
5000 // Vectors of all-zeros and all-ones are materialized with special
5001 // instructions rather than being loaded.
5002 return !ISD::isBuildVectorAllZeros(N) &&
5003 !ISD::isBuildVectorAllOnes(N);
5006 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5007 /// match movlp{s|d}. The lower half elements should come from lower half of
5008 /// V1 (and in order), and the upper half elements should come from the upper
5009 /// half of V2 (and in order). And since V1 will become the source of the
5010 /// MOVLP, it must be either a vector load or a scalar load to vector.
5011 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5012 ArrayRef<int> Mask, MVT VT) {
5013 if (!VT.is128BitVector())
5016 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5018 // Is V2 is a vector load, don't do this transformation. We will try to use
5019 // load folding shufps op.
5020 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5023 unsigned NumElems = VT.getVectorNumElements();
5025 if (NumElems != 2 && NumElems != 4)
5027 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5028 if (!isUndefOrEqual(Mask[i], i))
5030 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5031 if (!isUndefOrEqual(Mask[i], i+NumElems))
5036 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5037 /// to an zero vector.
5038 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5039 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5040 SDValue V1 = N->getOperand(0);
5041 SDValue V2 = N->getOperand(1);
5042 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5043 for (unsigned i = 0; i != NumElems; ++i) {
5044 int Idx = N->getMaskElt(i);
5045 if (Idx >= (int)NumElems) {
5046 unsigned Opc = V2.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5052 } else if (Idx >= 0) {
5053 unsigned Opc = V1.getOpcode();
5054 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5056 if (Opc != ISD::BUILD_VECTOR ||
5057 !X86::isZeroNode(V1.getOperand(Idx)))
5064 /// getZeroVector - Returns a vector of specified type with all zero elements.
5066 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5067 SelectionDAG &DAG, SDLoc dl) {
5068 assert(VT.isVector() && "Expected a vector type");
5070 // Always build SSE zero vectors as <4 x i32> bitcasted
5071 // to their dest type. This ensures they get CSE'd.
5073 if (VT.is128BitVector()) { // SSE
5074 if (Subtarget->hasSSE2()) { // SSE2
5075 SDValue Cst = DAG.getConstant(0, MVT::i32);
5076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5078 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5081 } else if (VT.is256BitVector()) { // AVX
5082 if (Subtarget->hasInt256()) { // AVX2
5083 SDValue Cst = DAG.getConstant(0, MVT::i32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5087 // 256-bit logic and arithmetic instructions in AVX are all
5088 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5089 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5090 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5093 } else if (VT.is512BitVector()) { // AVX-512
5094 SDValue Cst = DAG.getConstant(0, MVT::i32);
5095 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5096 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5097 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5098 } else if (VT.getScalarType() == MVT::i1) {
5099 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5100 SDValue Cst = DAG.getConstant(0, MVT::i1);
5101 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5102 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5104 llvm_unreachable("Unexpected vector type");
5106 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5109 /// getOnesVector - Returns a vector of specified type with all bits set.
5110 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5111 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5112 /// Then bitcast to their original type, ensuring they get CSE'd.
5113 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5115 assert(VT.isVector() && "Expected a vector type");
5117 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5119 if (VT.is256BitVector()) {
5120 if (HasInt256) { // AVX2
5121 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5124 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5125 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5127 } else if (VT.is128BitVector()) {
5128 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5130 llvm_unreachable("Unexpected vector type");
5132 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5135 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5136 /// that point to V2 points to its first element.
5137 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5138 for (unsigned i = 0; i != NumElems; ++i) {
5139 if (Mask[i] > (int)NumElems) {
5145 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5146 /// operation of specified width.
5147 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5149 unsigned NumElems = VT.getVectorNumElements();
5150 SmallVector<int, 8> Mask;
5151 Mask.push_back(NumElems);
5152 for (unsigned i = 1; i != NumElems; ++i)
5154 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5157 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5158 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5160 unsigned NumElems = VT.getVectorNumElements();
5161 SmallVector<int, 8> Mask;
5162 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5164 Mask.push_back(i + NumElems);
5166 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5169 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5170 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5172 unsigned NumElems = VT.getVectorNumElements();
5173 SmallVector<int, 8> Mask;
5174 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5175 Mask.push_back(i + Half);
5176 Mask.push_back(i + NumElems + Half);
5178 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5181 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5182 // a generic shuffle instruction because the target has no such instructions.
5183 // Generate shuffles which repeat i16 and i8 several times until they can be
5184 // represented by v4f32 and then be manipulated by target suported shuffles.
5185 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5186 MVT VT = V.getSimpleValueType();
5187 int NumElems = VT.getVectorNumElements();
5190 while (NumElems > 4) {
5191 if (EltNo < NumElems/2) {
5192 V = getUnpackl(DAG, dl, VT, V, V);
5194 V = getUnpackh(DAG, dl, VT, V, V);
5195 EltNo -= NumElems/2;
5202 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5203 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5204 MVT VT = V.getSimpleValueType();
5207 if (VT.is128BitVector()) {
5208 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5209 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5210 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5212 } else if (VT.is256BitVector()) {
5213 // To use VPERMILPS to splat scalars, the second half of indicies must
5214 // refer to the higher part, which is a duplication of the lower one,
5215 // because VPERMILPS can only handle in-lane permutations.
5216 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5217 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5219 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5220 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5223 llvm_unreachable("Vector size not supported");
5225 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5228 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5229 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5230 MVT SrcVT = SV->getSimpleValueType(0);
5231 SDValue V1 = SV->getOperand(0);
5234 int EltNo = SV->getSplatIndex();
5235 int NumElems = SrcVT.getVectorNumElements();
5236 bool Is256BitVec = SrcVT.is256BitVector();
5238 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5239 "Unknown how to promote splat for type");
5241 // Extract the 128-bit part containing the splat element and update
5242 // the splat element index when it refers to the higher register.
5244 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5245 if (EltNo >= NumElems/2)
5246 EltNo -= NumElems/2;
5249 // All i16 and i8 vector types can't be used directly by a generic shuffle
5250 // instruction because the target has no such instruction. Generate shuffles
5251 // which repeat i16 and i8 several times until they fit in i32, and then can
5252 // be manipulated by target suported shuffles.
5253 MVT EltVT = SrcVT.getVectorElementType();
5254 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5255 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5257 // Recreate the 256-bit vector and place the same 128-bit vector
5258 // into the low and high part. This is necessary because we want
5259 // to use VPERM* to shuffle the vectors
5261 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5264 return getLegalSplat(DAG, V1, EltNo);
5267 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5268 /// vector of zero or undef vector. This produces a shuffle where the low
5269 /// element of V2 is swizzled into the zero/undef vector, landing at element
5270 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5271 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5273 const X86Subtarget *Subtarget,
5274 SelectionDAG &DAG) {
5275 MVT VT = V2.getSimpleValueType();
5277 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5278 unsigned NumElems = VT.getVectorNumElements();
5279 SmallVector<int, 16> MaskVec;
5280 for (unsigned i = 0; i != NumElems; ++i)
5281 // If this is the insertion idx, put the low elt of V2 here.
5282 MaskVec.push_back(i == Idx ? NumElems : i);
5283 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5286 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5287 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5288 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5289 /// shuffles which use a single input multiple times, and in those cases it will
5290 /// adjust the mask to only have indices within that single input.
5291 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5292 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5293 unsigned NumElems = VT.getVectorNumElements();
5297 bool IsFakeUnary = false;
5298 switch(N->getOpcode()) {
5299 case X86ISD::BLENDI:
5300 ImmN = N->getOperand(N->getNumOperands()-1);
5301 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5304 ImmN = N->getOperand(N->getNumOperands()-1);
5305 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::UNPCKH:
5309 DecodeUNPCKHMask(VT, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::UNPCKL:
5313 DecodeUNPCKLMask(VT, Mask);
5314 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 case X86ISD::MOVHLPS:
5317 DecodeMOVHLPSMask(NumElems, Mask);
5318 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5320 case X86ISD::MOVLHPS:
5321 DecodeMOVLHPSMask(NumElems, Mask);
5322 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5324 case X86ISD::PALIGNR:
5325 ImmN = N->getOperand(N->getNumOperands()-1);
5326 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFD:
5329 case X86ISD::VPERMILPI:
5330 ImmN = N->getOperand(N->getNumOperands()-1);
5331 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5334 case X86ISD::PSHUFHW:
5335 ImmN = N->getOperand(N->getNumOperands()-1);
5336 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5339 case X86ISD::PSHUFLW:
5340 ImmN = N->getOperand(N->getNumOperands()-1);
5341 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5344 case X86ISD::PSHUFB: {
5346 SDValue MaskNode = N->getOperand(1);
5347 while (MaskNode->getOpcode() == ISD::BITCAST)
5348 MaskNode = MaskNode->getOperand(0);
5350 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5351 // If we have a build-vector, then things are easy.
5352 EVT VT = MaskNode.getValueType();
5353 assert(VT.isVector() &&
5354 "Can't produce a non-vector with a build_vector!");
5355 if (!VT.isInteger())
5358 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5360 SmallVector<uint64_t, 32> RawMask;
5361 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5362 SDValue Op = MaskNode->getOperand(i);
5363 if (Op->getOpcode() == ISD::UNDEF) {
5364 RawMask.push_back((uint64_t)SM_SentinelUndef);
5367 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5370 APInt MaskElement = CN->getAPIntValue();
5372 // We now have to decode the element which could be any integer size and
5373 // extract each byte of it.
5374 for (int j = 0; j < NumBytesPerElement; ++j) {
5375 // Note that this is x86 and so always little endian: the low byte is
5376 // the first byte of the mask.
5377 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5378 MaskElement = MaskElement.lshr(8);
5381 DecodePSHUFBMask(RawMask, Mask);
5385 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5389 SDValue Ptr = MaskLoad->getBasePtr();
5390 if (Ptr->getOpcode() == X86ISD::Wrapper)
5391 Ptr = Ptr->getOperand(0);
5393 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5394 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5397 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5398 // FIXME: Support AVX-512 here.
5399 Type *Ty = C->getType();
5400 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5401 Ty->getVectorNumElements() != 32))
5404 DecodePSHUFBMask(C, Mask);
5410 case X86ISD::VPERMI:
5411 ImmN = N->getOperand(N->getNumOperands()-1);
5412 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 case X86ISD::MOVSD: {
5417 // The index 0 always comes from the first element of the second source,
5418 // this is why MOVSS and MOVSD are used in the first place. The other
5419 // elements come from the other positions of the first source vector
5420 Mask.push_back(NumElems);
5421 for (unsigned i = 1; i != NumElems; ++i) {
5426 case X86ISD::VPERM2X128:
5427 ImmN = N->getOperand(N->getNumOperands()-1);
5428 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5429 if (Mask.empty()) return false;
5431 case X86ISD::MOVSLDUP:
5432 DecodeMOVSLDUPMask(VT, Mask);
5434 case X86ISD::MOVSHDUP:
5435 DecodeMOVSHDUPMask(VT, Mask);
5437 case X86ISD::MOVDDUP:
5438 case X86ISD::MOVLHPD:
5439 case X86ISD::MOVLPD:
5440 case X86ISD::MOVLPS:
5441 // Not yet implemented
5443 default: llvm_unreachable("unknown target shuffle node");
5446 // If we have a fake unary shuffle, the shuffle mask is spread across two
5447 // inputs that are actually the same node. Re-map the mask to always point
5448 // into the first input.
5451 if (M >= (int)Mask.size())
5457 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5458 /// element of the result of the vector shuffle.
5459 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5462 return SDValue(); // Limit search depth.
5464 SDValue V = SDValue(N, 0);
5465 EVT VT = V.getValueType();
5466 unsigned Opcode = V.getOpcode();
5468 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5469 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5470 int Elt = SV->getMaskElt(Index);
5473 return DAG.getUNDEF(VT.getVectorElementType());
5475 unsigned NumElems = VT.getVectorNumElements();
5476 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5477 : SV->getOperand(1);
5478 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5481 // Recurse into target specific vector shuffles to find scalars.
5482 if (isTargetShuffle(Opcode)) {
5483 MVT ShufVT = V.getSimpleValueType();
5484 unsigned NumElems = ShufVT.getVectorNumElements();
5485 SmallVector<int, 16> ShuffleMask;
5488 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5491 int Elt = ShuffleMask[Index];
5493 return DAG.getUNDEF(ShufVT.getVectorElementType());
5495 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5497 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5501 // Actual nodes that may contain scalar elements
5502 if (Opcode == ISD::BITCAST) {
5503 V = V.getOperand(0);
5504 EVT SrcVT = V.getValueType();
5505 unsigned NumElems = VT.getVectorNumElements();
5507 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5511 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5512 return (Index == 0) ? V.getOperand(0)
5513 : DAG.getUNDEF(VT.getVectorElementType());
5515 if (V.getOpcode() == ISD::BUILD_VECTOR)
5516 return V.getOperand(Index);
5521 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5522 /// shuffle operation which come from a consecutively from a zero. The
5523 /// search can start in two different directions, from left or right.
5524 /// We count undefs as zeros until PreferredNum is reached.
5525 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5526 unsigned NumElems, bool ZerosFromLeft,
5528 unsigned PreferredNum = -1U) {
5529 unsigned NumZeros = 0;
5530 for (unsigned i = 0; i != NumElems; ++i) {
5531 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5532 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5536 if (X86::isZeroNode(Elt))
5538 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5539 NumZeros = std::min(NumZeros + 1, PreferredNum);
5547 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5548 /// correspond consecutively to elements from one of the vector operands,
5549 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5551 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5552 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5553 unsigned NumElems, unsigned &OpNum) {
5554 bool SeenV1 = false;
5555 bool SeenV2 = false;
5557 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5558 int Idx = SVOp->getMaskElt(i);
5559 // Ignore undef indicies
5563 if (Idx < (int)NumElems)
5568 // Only accept consecutive elements from the same vector
5569 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5573 OpNum = SeenV1 ? 0 : 1;
5577 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5578 /// logical left shift of a vector.
5579 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5580 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5582 SVOp->getSimpleValueType(0).getVectorNumElements();
5583 unsigned NumZeros = getNumOfConsecutiveZeros(
5584 SVOp, NumElems, false /* check zeros from right */, DAG,
5585 SVOp->getMaskElt(0));
5591 // Considering the elements in the mask that are not consecutive zeros,
5592 // check if they consecutively come from only one of the source vectors.
5594 // V1 = {X, A, B, C} 0
5596 // vector_shuffle V1, V2 <1, 2, 3, X>
5598 if (!isShuffleMaskConsecutive(SVOp,
5599 0, // Mask Start Index
5600 NumElems-NumZeros, // Mask End Index(exclusive)
5601 NumZeros, // Where to start looking in the src vector
5602 NumElems, // Number of elements in vector
5603 OpSrc)) // Which source operand ?
5608 ShVal = SVOp->getOperand(OpSrc);
5612 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5613 /// logical left shift of a vector.
5614 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5615 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5617 SVOp->getSimpleValueType(0).getVectorNumElements();
5618 unsigned NumZeros = getNumOfConsecutiveZeros(
5619 SVOp, NumElems, true /* check zeros from left */, DAG,
5620 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5626 // Considering the elements in the mask that are not consecutive zeros,
5627 // check if they consecutively come from only one of the source vectors.
5629 // 0 { A, B, X, X } = V2
5631 // vector_shuffle V1, V2 <X, X, 4, 5>
5633 if (!isShuffleMaskConsecutive(SVOp,
5634 NumZeros, // Mask Start Index
5635 NumElems, // Mask End Index(exclusive)
5636 0, // Where to start looking in the src vector
5637 NumElems, // Number of elements in vector
5638 OpSrc)) // Which source operand ?
5643 ShVal = SVOp->getOperand(OpSrc);
5647 /// isVectorShift - Returns true if the shuffle can be implemented as a
5648 /// logical left or right shift of a vector.
5649 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5650 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5651 // Although the logic below support any bitwidth size, there are no
5652 // shift instructions which handle more than 128-bit vectors.
5653 if (!SVOp->getSimpleValueType(0).is128BitVector())
5656 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5657 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5663 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5665 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5666 unsigned NumNonZero, unsigned NumZero,
5668 const X86Subtarget* Subtarget,
5669 const TargetLowering &TLI) {
5676 for (unsigned i = 0; i < 16; ++i) {
5677 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5678 if (ThisIsNonZero && First) {
5680 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5682 V = DAG.getUNDEF(MVT::v8i16);
5687 SDValue ThisElt, LastElt;
5688 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5689 if (LastIsNonZero) {
5690 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5691 MVT::i16, Op.getOperand(i-1));
5693 if (ThisIsNonZero) {
5694 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5695 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5696 ThisElt, DAG.getConstant(8, MVT::i8));
5698 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5702 if (ThisElt.getNode())
5703 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5704 DAG.getIntPtrConstant(i/2));
5708 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5711 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5713 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5714 unsigned NumNonZero, unsigned NumZero,
5716 const X86Subtarget* Subtarget,
5717 const TargetLowering &TLI) {
5724 for (unsigned i = 0; i < 8; ++i) {
5725 bool isNonZero = (NonZeros & (1 << i)) != 0;
5729 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5731 V = DAG.getUNDEF(MVT::v8i16);
5734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5735 MVT::v8i16, V, Op.getOperand(i),
5736 DAG.getIntPtrConstant(i));
5743 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5744 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5745 const X86Subtarget *Subtarget,
5746 const TargetLowering &TLI) {
5747 // Find all zeroable elements.
5749 for (int i=0; i < 4; ++i) {
5750 SDValue Elt = Op->getOperand(i);
5751 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5753 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5754 [](bool M) { return !M; }) > 1 &&
5755 "We expect at least two non-zero elements!");
5757 // We only know how to deal with build_vector nodes where elements are either
5758 // zeroable or extract_vector_elt with constant index.
5759 SDValue FirstNonZero;
5760 for (int i=0; i < 4; ++i) {
5763 SDValue Elt = Op->getOperand(i);
5764 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5765 !isa<ConstantSDNode>(Elt.getOperand(1)))
5767 // Make sure that this node is extracting from a 128-bit vector.
5768 MVT VT = Elt.getOperand(0).getSimpleValueType();
5769 if (!VT.is128BitVector())
5771 if (!FirstNonZero.getNode())
5775 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5776 SDValue V1 = FirstNonZero.getOperand(0);
5777 MVT VT = V1.getSimpleValueType();
5779 // See if this build_vector can be lowered as a blend with zero.
5781 unsigned EltMaskIdx, EltIdx;
5783 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5784 if (Zeroable[EltIdx]) {
5785 // The zero vector will be on the right hand side.
5786 Mask[EltIdx] = EltIdx+4;
5790 Elt = Op->getOperand(EltIdx);
5791 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5792 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5793 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5795 Mask[EltIdx] = EltIdx;
5799 // Let the shuffle legalizer deal with blend operations.
5800 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5801 if (V1.getSimpleValueType() != VT)
5802 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5803 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5806 // See if we can lower this build_vector to a INSERTPS.
5807 if (!Subtarget->hasSSE41())
5810 SDValue V2 = Elt.getOperand(0);
5811 if (Elt == FirstNonZero)
5814 bool CanFold = true;
5815 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5819 SDValue Current = Op->getOperand(i);
5820 SDValue SrcVector = Current->getOperand(0);
5823 CanFold = SrcVector == V1 &&
5824 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5830 assert(V1.getNode() && "Expected at least two non-zero elements!");
5831 if (V1.getSimpleValueType() != MVT::v4f32)
5832 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5833 if (V2.getSimpleValueType() != MVT::v4f32)
5834 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5836 // Ok, we can emit an INSERTPS instruction.
5838 for (int i = 0; i < 4; ++i)
5842 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5843 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5844 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5845 DAG.getIntPtrConstant(InsertPSMask));
5846 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5849 /// getVShift - Return a vector logical shift node.
5851 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5852 unsigned NumBits, SelectionDAG &DAG,
5853 const TargetLowering &TLI, SDLoc dl) {
5854 assert(VT.is128BitVector() && "Unknown type for VShift");
5855 EVT ShVT = MVT::v2i64;
5856 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5857 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5858 return DAG.getNode(ISD::BITCAST, dl, VT,
5859 DAG.getNode(Opc, dl, ShVT, SrcOp,
5860 DAG.getConstant(NumBits,
5861 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5865 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5867 // Check if the scalar load can be widened into a vector load. And if
5868 // the address is "base + cst" see if the cst can be "absorbed" into
5869 // the shuffle mask.
5870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5871 SDValue Ptr = LD->getBasePtr();
5872 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5874 EVT PVT = LD->getValueType(0);
5875 if (PVT != MVT::i32 && PVT != MVT::f32)
5880 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5881 FI = FINode->getIndex();
5883 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5884 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5885 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5886 Offset = Ptr.getConstantOperandVal(1);
5887 Ptr = Ptr.getOperand(0);
5892 // FIXME: 256-bit vector instructions don't require a strict alignment,
5893 // improve this code to support it better.
5894 unsigned RequiredAlign = VT.getSizeInBits()/8;
5895 SDValue Chain = LD->getChain();
5896 // Make sure the stack object alignment is at least 16 or 32.
5897 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5898 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5899 if (MFI->isFixedObjectIndex(FI)) {
5900 // Can't change the alignment. FIXME: It's possible to compute
5901 // the exact stack offset and reference FI + adjust offset instead.
5902 // If someone *really* cares about this. That's the way to implement it.
5905 MFI->setObjectAlignment(FI, RequiredAlign);
5909 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5910 // Ptr + (Offset & ~15).
5913 if ((Offset % RequiredAlign) & 3)
5915 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5917 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5918 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5920 int EltNo = (Offset - StartOffset) >> 2;
5921 unsigned NumElems = VT.getVectorNumElements();
5923 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5924 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5925 LD->getPointerInfo().getWithOffset(StartOffset),
5926 false, false, false, 0);
5928 SmallVector<int, 8> Mask;
5929 for (unsigned i = 0; i != NumElems; ++i)
5930 Mask.push_back(EltNo);
5932 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5938 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5939 /// vector of type 'VT', see if the elements can be replaced by a single large
5940 /// load which has the same value as a build_vector whose operands are 'elts'.
5942 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5944 /// FIXME: we'd also like to handle the case where the last elements are zero
5945 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5946 /// There's even a handy isZeroNode for that purpose.
5947 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5948 SDLoc &DL, SelectionDAG &DAG,
5949 bool isAfterLegalize) {
5950 EVT EltVT = VT.getVectorElementType();
5951 unsigned NumElems = Elts.size();
5953 LoadSDNode *LDBase = nullptr;
5954 unsigned LastLoadedElt = -1U;
5956 // For each element in the initializer, see if we've found a load or an undef.
5957 // If we don't find an initial load element, or later load elements are
5958 // non-consecutive, bail out.
5959 for (unsigned i = 0; i < NumElems; ++i) {
5960 SDValue Elt = Elts[i];
5962 if (!Elt.getNode() ||
5963 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5966 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5968 LDBase = cast<LoadSDNode>(Elt.getNode());
5972 if (Elt.getOpcode() == ISD::UNDEF)
5975 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5976 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5981 // If we have found an entire vector of loads and undefs, then return a large
5982 // load of the entire vector width starting at the base pointer. If we found
5983 // consecutive loads for the low half, generate a vzext_load node.
5984 if (LastLoadedElt == NumElems - 1) {
5986 if (isAfterLegalize &&
5987 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5990 SDValue NewLd = SDValue();
5992 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5993 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5994 LDBase->getPointerInfo(),
5995 LDBase->isVolatile(), LDBase->isNonTemporal(),
5996 LDBase->isInvariant(), 0);
5997 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5998 LDBase->getPointerInfo(),
5999 LDBase->isVolatile(), LDBase->isNonTemporal(),
6000 LDBase->isInvariant(), LDBase->getAlignment());
6002 if (LDBase->hasAnyUseOfValue(1)) {
6003 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6005 SDValue(NewLd.getNode(), 1));
6006 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6007 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6008 SDValue(NewLd.getNode(), 1));
6013 if (NumElems == 4 && LastLoadedElt == 1 &&
6014 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6015 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6016 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6018 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6019 LDBase->getPointerInfo(),
6020 LDBase->getAlignment(),
6021 false/*isVolatile*/, true/*ReadMem*/,
6024 // Make sure the newly-created LOAD is in the same position as LDBase in
6025 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6026 // update uses of LDBase's output chain to use the TokenFactor.
6027 if (LDBase->hasAnyUseOfValue(1)) {
6028 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6029 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6030 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6031 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6032 SDValue(ResNode.getNode(), 1));
6035 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6040 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6041 /// to generate a splat value for the following cases:
6042 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6043 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6044 /// a scalar load, or a constant.
6045 /// The VBROADCAST node is returned when a pattern is found,
6046 /// or SDValue() otherwise.
6047 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6048 SelectionDAG &DAG) {
6049 // VBROADCAST requires AVX.
6050 // TODO: Splats could be generated for non-AVX CPUs using SSE
6051 // instructions, but there's less potential gain for only 128-bit vectors.
6052 if (!Subtarget->hasAVX())
6055 MVT VT = Op.getSimpleValueType();
6058 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6059 "Unsupported vector type for broadcast.");
6064 switch (Op.getOpcode()) {
6066 // Unknown pattern found.
6069 case ISD::BUILD_VECTOR: {
6070 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6071 BitVector UndefElements;
6072 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6074 // We need a splat of a single value to use broadcast, and it doesn't
6075 // make any sense if the value is only in one element of the vector.
6076 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6080 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6081 Ld.getOpcode() == ISD::ConstantFP);
6083 // Make sure that all of the users of a non-constant load are from the
6084 // BUILD_VECTOR node.
6085 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6090 case ISD::VECTOR_SHUFFLE: {
6091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6093 // Shuffles must have a splat mask where the first element is
6095 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6098 SDValue Sc = Op.getOperand(0);
6099 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6100 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6102 if (!Subtarget->hasInt256())
6105 // Use the register form of the broadcast instruction available on AVX2.
6106 if (VT.getSizeInBits() >= 256)
6107 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6111 Ld = Sc.getOperand(0);
6112 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6113 Ld.getOpcode() == ISD::ConstantFP);
6115 // The scalar_to_vector node and the suspected
6116 // load node must have exactly one user.
6117 // Constants may have multiple users.
6119 // AVX-512 has register version of the broadcast
6120 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6121 Ld.getValueType().getSizeInBits() >= 32;
6122 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6129 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6130 bool IsGE256 = (VT.getSizeInBits() >= 256);
6132 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6133 // instruction to save 8 or more bytes of constant pool data.
6134 // TODO: If multiple splats are generated to load the same constant,
6135 // it may be detrimental to overall size. There needs to be a way to detect
6136 // that condition to know if this is truly a size win.
6137 const Function *F = DAG.getMachineFunction().getFunction();
6138 bool OptForSize = F->getAttributes().
6139 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6141 // Handle broadcasting a single constant scalar from the constant pool
6143 // On Sandybridge (no AVX2), it is still better to load a constant vector
6144 // from the constant pool and not to broadcast it from a scalar.
6145 // But override that restriction when optimizing for size.
6146 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6147 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6148 EVT CVT = Ld.getValueType();
6149 assert(!CVT.isVector() && "Must not broadcast a vector type");
6151 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6152 // For size optimization, also splat v2f64 and v2i64, and for size opt
6153 // with AVX2, also splat i8 and i16.
6154 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6155 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6156 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6157 const Constant *C = nullptr;
6158 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6159 C = CI->getConstantIntValue();
6160 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6161 C = CF->getConstantFPValue();
6163 assert(C && "Invalid constant type");
6165 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6166 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6167 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6168 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6169 MachinePointerInfo::getConstantPool(),
6170 false, false, false, Alignment);
6172 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6176 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6178 // Handle AVX2 in-register broadcasts.
6179 if (!IsLoad && Subtarget->hasInt256() &&
6180 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6183 // The scalar source must be a normal load.
6187 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6191 // double since there is no vbroadcastsd xmm
6192 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6193 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // Unsupported broadcast.
6201 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6202 /// underlying vector and index.
6204 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6206 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6208 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6209 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6212 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6214 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6216 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6217 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6220 // In this case the vector is the extract_subvector expression and the index
6221 // is 2, as specified by the shuffle.
6222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6223 SDValue ShuffleVec = SVOp->getOperand(0);
6224 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6225 assert(ShuffleVecVT.getVectorElementType() ==
6226 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6228 int ShuffleIdx = SVOp->getMaskElt(Idx);
6229 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6230 ExtractedFromVec = ShuffleVec;
6236 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6237 MVT VT = Op.getSimpleValueType();
6239 // Skip if insert_vec_elt is not supported.
6240 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6241 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6245 unsigned NumElems = Op.getNumOperands();
6249 SmallVector<unsigned, 4> InsertIndices;
6250 SmallVector<int, 8> Mask(NumElems, -1);
6252 for (unsigned i = 0; i != NumElems; ++i) {
6253 unsigned Opc = Op.getOperand(i).getOpcode();
6255 if (Opc == ISD::UNDEF)
6258 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6259 // Quit if more than 1 elements need inserting.
6260 if (InsertIndices.size() > 1)
6263 InsertIndices.push_back(i);
6267 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6268 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6269 // Quit if non-constant index.
6270 if (!isa<ConstantSDNode>(ExtIdx))
6272 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6274 // Quit if extracted from vector of different type.
6275 if (ExtractedFromVec.getValueType() != VT)
6278 if (!VecIn1.getNode())
6279 VecIn1 = ExtractedFromVec;
6280 else if (VecIn1 != ExtractedFromVec) {
6281 if (!VecIn2.getNode())
6282 VecIn2 = ExtractedFromVec;
6283 else if (VecIn2 != ExtractedFromVec)
6284 // Quit if more than 2 vectors to shuffle
6288 if (ExtractedFromVec == VecIn1)
6290 else if (ExtractedFromVec == VecIn2)
6291 Mask[i] = Idx + NumElems;
6294 if (!VecIn1.getNode())
6297 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6298 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6299 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6300 unsigned Idx = InsertIndices[i];
6301 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6302 DAG.getIntPtrConstant(Idx));
6308 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6310 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6312 MVT VT = Op.getSimpleValueType();
6313 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6314 "Unexpected type in LowerBUILD_VECTORvXi1!");
6317 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6318 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6319 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6320 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6323 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6324 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6325 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6326 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6329 bool AllContants = true;
6330 uint64_t Immediate = 0;
6331 int NonConstIdx = -1;
6332 bool IsSplat = true;
6333 unsigned NumNonConsts = 0;
6334 unsigned NumConsts = 0;
6335 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6336 SDValue In = Op.getOperand(idx);
6337 if (In.getOpcode() == ISD::UNDEF)
6339 if (!isa<ConstantSDNode>(In)) {
6340 AllContants = false;
6346 if (cast<ConstantSDNode>(In)->getZExtValue())
6347 Immediate |= (1ULL << idx);
6349 if (In != Op.getOperand(0))
6354 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6355 DAG.getConstant(Immediate, MVT::i16));
6356 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6357 DAG.getIntPtrConstant(0));
6360 if (NumNonConsts == 1 && NonConstIdx != 0) {
6363 SDValue VecAsImm = DAG.getConstant(Immediate,
6364 MVT::getIntegerVT(VT.getSizeInBits()));
6365 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6368 DstVec = DAG.getUNDEF(VT);
6369 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6370 Op.getOperand(NonConstIdx),
6371 DAG.getIntPtrConstant(NonConstIdx));
6373 if (!IsSplat && (NonConstIdx != 0))
6374 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6375 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6378 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6379 DAG.getConstant(-1, SelectVT),
6380 DAG.getConstant(0, SelectVT));
6382 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6383 DAG.getConstant((Immediate | 1), SelectVT),
6384 DAG.getConstant(Immediate, SelectVT));
6385 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6388 /// \brief Return true if \p N implements a horizontal binop and return the
6389 /// operands for the horizontal binop into V0 and V1.
6391 /// This is a helper function of PerformBUILD_VECTORCombine.
6392 /// This function checks that the build_vector \p N in input implements a
6393 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6394 /// operation to match.
6395 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6396 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6397 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6400 /// This function only analyzes elements of \p N whose indices are
6401 /// in range [BaseIdx, LastIdx).
6402 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6404 unsigned BaseIdx, unsigned LastIdx,
6405 SDValue &V0, SDValue &V1) {
6406 EVT VT = N->getValueType(0);
6408 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6409 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6410 "Invalid Vector in input!");
6412 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6413 bool CanFold = true;
6414 unsigned ExpectedVExtractIdx = BaseIdx;
6415 unsigned NumElts = LastIdx - BaseIdx;
6416 V0 = DAG.getUNDEF(VT);
6417 V1 = DAG.getUNDEF(VT);
6419 // Check if N implements a horizontal binop.
6420 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6421 SDValue Op = N->getOperand(i + BaseIdx);
6424 if (Op->getOpcode() == ISD::UNDEF) {
6425 // Update the expected vector extract index.
6426 if (i * 2 == NumElts)
6427 ExpectedVExtractIdx = BaseIdx;
6428 ExpectedVExtractIdx += 2;
6432 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6437 SDValue Op0 = Op.getOperand(0);
6438 SDValue Op1 = Op.getOperand(1);
6440 // Try to match the following pattern:
6441 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6442 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6444 Op0.getOperand(0) == Op1.getOperand(0) &&
6445 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6446 isa<ConstantSDNode>(Op1.getOperand(1)));
6450 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6451 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6453 if (i * 2 < NumElts) {
6454 if (V0.getOpcode() == ISD::UNDEF)
6455 V0 = Op0.getOperand(0);
6457 if (V1.getOpcode() == ISD::UNDEF)
6458 V1 = Op0.getOperand(0);
6459 if (i * 2 == NumElts)
6460 ExpectedVExtractIdx = BaseIdx;
6463 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6464 if (I0 == ExpectedVExtractIdx)
6465 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6466 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6467 // Try to match the following dag sequence:
6468 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6469 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6473 ExpectedVExtractIdx += 2;
6479 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6480 /// a concat_vector.
6482 /// This is a helper function of PerformBUILD_VECTORCombine.
6483 /// This function expects two 256-bit vectors called V0 and V1.
6484 /// At first, each vector is split into two separate 128-bit vectors.
6485 /// Then, the resulting 128-bit vectors are used to implement two
6486 /// horizontal binary operations.
6488 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6490 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6491 /// the two new horizontal binop.
6492 /// When Mode is set, the first horizontal binop dag node would take as input
6493 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6494 /// horizontal binop dag node would take as input the lower 128-bit of V1
6495 /// and the upper 128-bit of V1.
6497 /// HADD V0_LO, V0_HI
6498 /// HADD V1_LO, V1_HI
6500 /// Otherwise, the first horizontal binop dag node takes as input the lower
6501 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6502 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6504 /// HADD V0_LO, V1_LO
6505 /// HADD V0_HI, V1_HI
6507 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6508 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6509 /// the upper 128-bits of the result.
6510 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6511 SDLoc DL, SelectionDAG &DAG,
6512 unsigned X86Opcode, bool Mode,
6513 bool isUndefLO, bool isUndefHI) {
6514 EVT VT = V0.getValueType();
6515 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6516 "Invalid nodes in input!");
6518 unsigned NumElts = VT.getVectorNumElements();
6519 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6520 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6521 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6522 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6523 EVT NewVT = V0_LO.getValueType();
6525 SDValue LO = DAG.getUNDEF(NewVT);
6526 SDValue HI = DAG.getUNDEF(NewVT);
6529 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6530 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6531 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6532 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6533 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6535 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6536 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6537 V1_LO->getOpcode() != ISD::UNDEF))
6538 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6540 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6541 V1_HI->getOpcode() != ISD::UNDEF))
6542 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6545 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6548 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6549 /// sequence of 'vadd + vsub + blendi'.
6550 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6551 const X86Subtarget *Subtarget) {
6553 EVT VT = BV->getValueType(0);
6554 unsigned NumElts = VT.getVectorNumElements();
6555 SDValue InVec0 = DAG.getUNDEF(VT);
6556 SDValue InVec1 = DAG.getUNDEF(VT);
6558 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6559 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6561 // Odd-numbered elements in the input build vector are obtained from
6562 // adding two integer/float elements.
6563 // Even-numbered elements in the input build vector are obtained from
6564 // subtracting two integer/float elements.
6565 unsigned ExpectedOpcode = ISD::FSUB;
6566 unsigned NextExpectedOpcode = ISD::FADD;
6567 bool AddFound = false;
6568 bool SubFound = false;
6570 for (unsigned i = 0, e = NumElts; i != e; i++) {
6571 SDValue Op = BV->getOperand(i);
6573 // Skip 'undef' values.
6574 unsigned Opcode = Op.getOpcode();
6575 if (Opcode == ISD::UNDEF) {
6576 std::swap(ExpectedOpcode, NextExpectedOpcode);
6580 // Early exit if we found an unexpected opcode.
6581 if (Opcode != ExpectedOpcode)
6584 SDValue Op0 = Op.getOperand(0);
6585 SDValue Op1 = Op.getOperand(1);
6587 // Try to match the following pattern:
6588 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6589 // Early exit if we cannot match that sequence.
6590 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6592 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6593 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6594 Op0.getOperand(1) != Op1.getOperand(1))
6597 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6601 // We found a valid add/sub node. Update the information accordingly.
6607 // Update InVec0 and InVec1.
6608 if (InVec0.getOpcode() == ISD::UNDEF)
6609 InVec0 = Op0.getOperand(0);
6610 if (InVec1.getOpcode() == ISD::UNDEF)
6611 InVec1 = Op1.getOperand(0);
6613 // Make sure that operands in input to each add/sub node always
6614 // come from a same pair of vectors.
6615 if (InVec0 != Op0.getOperand(0)) {
6616 if (ExpectedOpcode == ISD::FSUB)
6619 // FADD is commutable. Try to commute the operands
6620 // and then test again.
6621 std::swap(Op0, Op1);
6622 if (InVec0 != Op0.getOperand(0))
6626 if (InVec1 != Op1.getOperand(0))
6629 // Update the pair of expected opcodes.
6630 std::swap(ExpectedOpcode, NextExpectedOpcode);
6633 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6634 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6635 InVec1.getOpcode() != ISD::UNDEF)
6636 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6641 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6642 const X86Subtarget *Subtarget) {
6644 EVT VT = N->getValueType(0);
6645 unsigned NumElts = VT.getVectorNumElements();
6646 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6647 SDValue InVec0, InVec1;
6649 // Try to match an ADDSUB.
6650 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6651 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6652 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6653 if (Value.getNode())
6657 // Try to match horizontal ADD/SUB.
6658 unsigned NumUndefsLO = 0;
6659 unsigned NumUndefsHI = 0;
6660 unsigned Half = NumElts/2;
6662 // Count the number of UNDEF operands in the build_vector in input.
6663 for (unsigned i = 0, e = Half; i != e; ++i)
6664 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6667 for (unsigned i = Half, e = NumElts; i != e; ++i)
6668 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6671 // Early exit if this is either a build_vector of all UNDEFs or all the
6672 // operands but one are UNDEF.
6673 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6676 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6677 // Try to match an SSE3 float HADD/HSUB.
6678 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6679 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6681 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6682 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6683 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6684 // Try to match an SSSE3 integer HADD/HSUB.
6685 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6686 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6688 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6689 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6692 if (!Subtarget->hasAVX())
6695 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6696 // Try to match an AVX horizontal add/sub of packed single/double
6697 // precision floating point values from 256-bit vectors.
6698 SDValue InVec2, InVec3;
6699 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6700 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6701 ((InVec0.getOpcode() == ISD::UNDEF ||
6702 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6703 ((InVec1.getOpcode() == ISD::UNDEF ||
6704 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6705 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6707 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6708 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6709 ((InVec0.getOpcode() == ISD::UNDEF ||
6710 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6711 ((InVec1.getOpcode() == ISD::UNDEF ||
6712 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6713 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6714 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6715 // Try to match an AVX2 horizontal add/sub of signed integers.
6716 SDValue InVec2, InVec3;
6718 bool CanFold = true;
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6721 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6722 ((InVec0.getOpcode() == ISD::UNDEF ||
6723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6724 ((InVec1.getOpcode() == ISD::UNDEF ||
6725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6726 X86Opcode = X86ISD::HADD;
6727 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6728 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6729 ((InVec0.getOpcode() == ISD::UNDEF ||
6730 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6731 ((InVec1.getOpcode() == ISD::UNDEF ||
6732 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6733 X86Opcode = X86ISD::HSUB;
6738 // Fold this build_vector into a single horizontal add/sub.
6739 // Do this only if the target has AVX2.
6740 if (Subtarget->hasAVX2())
6741 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6743 // Do not try to expand this build_vector into a pair of horizontal
6744 // add/sub if we can emit a pair of scalar add/sub.
6745 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6748 // Convert this build_vector into a pair of horizontal binop followed by
6750 bool isUndefLO = NumUndefsLO == Half;
6751 bool isUndefHI = NumUndefsHI == Half;
6752 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6753 isUndefLO, isUndefHI);
6757 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6758 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6760 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6761 X86Opcode = X86ISD::HADD;
6762 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6763 X86Opcode = X86ISD::HSUB;
6764 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6765 X86Opcode = X86ISD::FHADD;
6766 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6767 X86Opcode = X86ISD::FHSUB;
6771 // Don't try to expand this build_vector into a pair of horizontal add/sub
6772 // if we can simply emit a pair of scalar add/sub.
6773 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6776 // Convert this build_vector into two horizontal add/sub followed by
6778 bool isUndefLO = NumUndefsLO == Half;
6779 bool isUndefHI = NumUndefsHI == Half;
6780 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6781 isUndefLO, isUndefHI);
6788 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6791 MVT VT = Op.getSimpleValueType();
6792 MVT ExtVT = VT.getVectorElementType();
6793 unsigned NumElems = Op.getNumOperands();
6795 // Generate vectors for predicate vectors.
6796 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6797 return LowerBUILD_VECTORvXi1(Op, DAG);
6799 // Vectors containing all zeros can be matched by pxor and xorps later
6800 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6801 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6802 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6803 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6806 return getZeroVector(VT, Subtarget, DAG, dl);
6809 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6810 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6811 // vpcmpeqd on 256-bit vectors.
6812 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6813 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6816 if (!VT.is512BitVector())
6817 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6820 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6821 if (Broadcast.getNode())
6824 unsigned EVTBits = ExtVT.getSizeInBits();
6826 unsigned NumZero = 0;
6827 unsigned NumNonZero = 0;
6828 unsigned NonZeros = 0;
6829 bool IsAllConstants = true;
6830 SmallSet<SDValue, 8> Values;
6831 for (unsigned i = 0; i < NumElems; ++i) {
6832 SDValue Elt = Op.getOperand(i);
6833 if (Elt.getOpcode() == ISD::UNDEF)
6836 if (Elt.getOpcode() != ISD::Constant &&
6837 Elt.getOpcode() != ISD::ConstantFP)
6838 IsAllConstants = false;
6839 if (X86::isZeroNode(Elt))
6842 NonZeros |= (1 << i);
6847 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6848 if (NumNonZero == 0)
6849 return DAG.getUNDEF(VT);
6851 // Special case for single non-zero, non-undef, element.
6852 if (NumNonZero == 1) {
6853 unsigned Idx = countTrailingZeros(NonZeros);
6854 SDValue Item = Op.getOperand(Idx);
6856 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6857 // the value are obviously zero, truncate the value to i32 and do the
6858 // insertion that way. Only do this if the value is non-constant or if the
6859 // value is a constant being inserted into element 0. It is cheaper to do
6860 // a constant pool load than it is to do a movd + shuffle.
6861 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6862 (!IsAllConstants || Idx == 0)) {
6863 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6865 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6866 EVT VecVT = MVT::v4i32;
6867 unsigned VecElts = 4;
6869 // Truncate the value (which may itself be a constant) to i32, and
6870 // convert it to a vector with movd (S2V+shuffle to zero extend).
6871 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6874 // If using the new shuffle lowering, just directly insert this.
6875 if (ExperimentalVectorShuffleLowering)
6877 ISD::BITCAST, dl, VT,
6878 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 // Now we have our 32-bit value zero extended in the low element of
6883 // a vector. If Idx != 0, swizzle it into place.
6885 SmallVector<int, 4> Mask;
6886 Mask.push_back(Idx);
6887 for (unsigned i = 1; i != VecElts; ++i)
6889 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6892 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6896 // If we have a constant or non-constant insertion into the low element of
6897 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6898 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6899 // depending on what the source datatype is.
6902 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6904 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6905 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6906 if (VT.is256BitVector() || VT.is512BitVector()) {
6907 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6908 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6909 Item, DAG.getIntPtrConstant(0));
6911 assert(VT.is128BitVector() && "Expected an SSE value type!");
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6914 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6917 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6918 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6920 if (VT.is256BitVector()) {
6921 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6922 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6924 assert(VT.is128BitVector() && "Expected an SSE value type!");
6925 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6927 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6931 // Is it a vector logical left shift?
6932 if (NumElems == 2 && Idx == 1 &&
6933 X86::isZeroNode(Op.getOperand(0)) &&
6934 !X86::isZeroNode(Op.getOperand(1))) {
6935 unsigned NumBits = VT.getSizeInBits();
6936 return getVShift(true, VT,
6937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6938 VT, Op.getOperand(1)),
6939 NumBits/2, DAG, *this, dl);
6942 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6945 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6946 // is a non-constant being inserted into an element other than the low one,
6947 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6948 // movd/movss) to move this into the low element, then shuffle it into
6950 if (EVTBits == 32) {
6951 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6953 // If using the new shuffle lowering, just directly insert this.
6954 if (ExperimentalVectorShuffleLowering)
6955 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6957 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6958 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6959 SmallVector<int, 8> MaskVec;
6960 for (unsigned i = 0; i != NumElems; ++i)
6961 MaskVec.push_back(i == Idx ? 0 : 1);
6962 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6966 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6967 if (Values.size() == 1) {
6968 if (EVTBits == 32) {
6969 // Instead of a shuffle like this:
6970 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6971 // Check if it's possible to issue this instead.
6972 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6973 unsigned Idx = countTrailingZeros(NonZeros);
6974 SDValue Item = Op.getOperand(Idx);
6975 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6976 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6981 // A vector full of immediates; various special cases are already
6982 // handled, so this is best done with a single constant-pool load.
6986 // For AVX-length vectors, build the individual 128-bit pieces and use
6987 // shuffles to put them in place.
6988 if (VT.is256BitVector() || VT.is512BitVector()) {
6989 SmallVector<SDValue, 64> V;
6990 for (unsigned i = 0; i != NumElems; ++i)
6991 V.push_back(Op.getOperand(i));
6993 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6995 // Build both the lower and upper subvector.
6996 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6997 makeArrayRef(&V[0], NumElems/2));
6998 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6999 makeArrayRef(&V[NumElems / 2], NumElems/2));
7001 // Recreate the wider vector with the lower and upper part.
7002 if (VT.is256BitVector())
7003 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7004 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7007 // Let legalizer expand 2-wide build_vectors.
7008 if (EVTBits == 64) {
7009 if (NumNonZero == 1) {
7010 // One half is zero or undef.
7011 unsigned Idx = countTrailingZeros(NonZeros);
7012 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7013 Op.getOperand(Idx));
7014 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7019 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7020 if (EVTBits == 8 && NumElems == 16) {
7021 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7023 if (V.getNode()) return V;
7026 if (EVTBits == 16 && NumElems == 8) {
7027 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7029 if (V.getNode()) return V;
7032 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7033 if (EVTBits == 32 && NumElems == 4) {
7034 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7039 // If element VT is == 32 bits, turn it into a number of shuffles.
7040 SmallVector<SDValue, 8> V(NumElems);
7041 if (NumElems == 4 && NumZero > 0) {
7042 for (unsigned i = 0; i < 4; ++i) {
7043 bool isZero = !(NonZeros & (1 << i));
7045 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7050 for (unsigned i = 0; i < 2; ++i) {
7051 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7054 V[i] = V[i*2]; // Must be a zero vector.
7057 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7060 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7063 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7068 bool Reverse1 = (NonZeros & 0x3) == 2;
7069 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7073 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7074 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7076 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7079 if (Values.size() > 1 && VT.is128BitVector()) {
7080 // Check for a build vector of consecutive loads.
7081 for (unsigned i = 0; i < NumElems; ++i)
7082 V[i] = Op.getOperand(i);
7084 // Check for elements which are consecutive loads.
7085 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7089 // Check for a build vector from mostly shuffle plus few inserting.
7090 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7094 // For SSE 4.1, use insertps to put the high elements into the low element.
7095 if (getSubtarget()->hasSSE41()) {
7097 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7098 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7100 Result = DAG.getUNDEF(VT);
7102 for (unsigned i = 1; i < NumElems; ++i) {
7103 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7104 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7105 Op.getOperand(i), DAG.getIntPtrConstant(i));
7110 // Otherwise, expand into a number of unpckl*, start by extending each of
7111 // our (non-undef) elements to the full vector width with the element in the
7112 // bottom slot of the vector (which generates no code for SSE).
7113 for (unsigned i = 0; i < NumElems; ++i) {
7114 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7115 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7117 V[i] = DAG.getUNDEF(VT);
7120 // Next, we iteratively mix elements, e.g. for v4f32:
7121 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7122 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7123 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7124 unsigned EltStride = NumElems >> 1;
7125 while (EltStride != 0) {
7126 for (unsigned i = 0; i < EltStride; ++i) {
7127 // If V[i+EltStride] is undef and this is the first round of mixing,
7128 // then it is safe to just drop this shuffle: V[i] is already in the
7129 // right place, the one element (since it's the first round) being
7130 // inserted as undef can be dropped. This isn't safe for successive
7131 // rounds because they will permute elements within both vectors.
7132 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7133 EltStride == NumElems/2)
7136 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7145 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7146 // to create 256-bit vectors from two other 128-bit ones.
7147 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7149 MVT ResVT = Op.getSimpleValueType();
7151 assert((ResVT.is256BitVector() ||
7152 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7154 SDValue V1 = Op.getOperand(0);
7155 SDValue V2 = Op.getOperand(1);
7156 unsigned NumElems = ResVT.getVectorNumElements();
7157 if(ResVT.is256BitVector())
7158 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7160 if (Op.getNumOperands() == 4) {
7161 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7162 ResVT.getVectorNumElements()/2);
7163 SDValue V3 = Op.getOperand(2);
7164 SDValue V4 = Op.getOperand(3);
7165 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7166 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7168 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7171 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7172 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7173 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7174 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7175 Op.getNumOperands() == 4)));
7177 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7178 // from two other 128-bit ones.
7180 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7181 return LowerAVXCONCAT_VECTORS(Op, DAG);
7185 //===----------------------------------------------------------------------===//
7186 // Vector shuffle lowering
7188 // This is an experimental code path for lowering vector shuffles on x86. It is
7189 // designed to handle arbitrary vector shuffles and blends, gracefully
7190 // degrading performance as necessary. It works hard to recognize idiomatic
7191 // shuffles and lower them to optimal instruction patterns without leaving
7192 // a framework that allows reasonably efficient handling of all vector shuffle
7194 //===----------------------------------------------------------------------===//
7196 /// \brief Tiny helper function to identify a no-op mask.
7198 /// This is a somewhat boring predicate function. It checks whether the mask
7199 /// array input, which is assumed to be a single-input shuffle mask of the kind
7200 /// used by the X86 shuffle instructions (not a fully general
7201 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7202 /// in-place shuffle are 'no-op's.
7203 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7204 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7205 if (Mask[i] != -1 && Mask[i] != i)
7210 /// \brief Helper function to classify a mask as a single-input mask.
7212 /// This isn't a generic single-input test because in the vector shuffle
7213 /// lowering we canonicalize single inputs to be the first input operand. This
7214 /// means we can more quickly test for a single input by only checking whether
7215 /// an input from the second operand exists. We also assume that the size of
7216 /// mask corresponds to the size of the input vectors which isn't true in the
7217 /// fully general case.
7218 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7220 if (M >= (int)Mask.size())
7225 /// \brief Test whether there are elements crossing 128-bit lanes in this
7228 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7229 /// and we routinely test for these.
7230 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7231 int LaneSize = 128 / VT.getScalarSizeInBits();
7232 int Size = Mask.size();
7233 for (int i = 0; i < Size; ++i)
7234 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7239 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7241 /// This checks a shuffle mask to see if it is performing the same
7242 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7243 /// that it is also not lane-crossing. It may however involve a blend from the
7244 /// same lane of a second vector.
7246 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7247 /// non-trivial to compute in the face of undef lanes. The representation is
7248 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7249 /// entries from both V1 and V2 inputs to the wider mask.
7251 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7252 SmallVectorImpl<int> &RepeatedMask) {
7253 int LaneSize = 128 / VT.getScalarSizeInBits();
7254 RepeatedMask.resize(LaneSize, -1);
7255 int Size = Mask.size();
7256 for (int i = 0; i < Size; ++i) {
7259 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7260 // This entry crosses lanes, so there is no way to model this shuffle.
7263 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7264 if (RepeatedMask[i % LaneSize] == -1)
7265 // This is the first non-undef entry in this slot of a 128-bit lane.
7266 RepeatedMask[i % LaneSize] =
7267 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7268 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7269 // Found a mismatch with the repeated mask.
7275 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7276 // 2013 will allow us to use it as a non-type template parameter.
7279 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7281 /// See its documentation for details.
7282 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7283 if (Mask.size() != Args.size())
7285 for (int i = 0, e = Mask.size(); i < e; ++i) {
7286 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7287 if (Mask[i] != -1 && Mask[i] != *Args[i])
7295 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7298 /// This is a fast way to test a shuffle mask against a fixed pattern:
7300 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7302 /// It returns true if the mask is exactly as wide as the argument list, and
7303 /// each element of the mask is either -1 (signifying undef) or the value given
7304 /// in the argument.
7305 static const VariadicFunction1<
7306 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7308 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7310 /// This helper function produces an 8-bit shuffle immediate corresponding to
7311 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7312 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7315 /// NB: We rely heavily on "undef" masks preserving the input lane.
7316 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7317 SelectionDAG &DAG) {
7318 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7319 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7320 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7321 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7322 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7325 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7326 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7327 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7328 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7329 return DAG.getConstant(Imm, MVT::i8);
7332 /// \brief Try to emit a blend instruction for a shuffle.
7334 /// This doesn't do any checks for the availability of instructions for blending
7335 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7336 /// be matched in the backend with the type given. What it does check for is
7337 /// that the shuffle mask is in fact a blend.
7338 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7339 SDValue V2, ArrayRef<int> Mask,
7340 const X86Subtarget *Subtarget,
7341 SelectionDAG &DAG) {
7343 unsigned BlendMask = 0;
7344 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7345 if (Mask[i] >= Size) {
7346 if (Mask[i] != i + Size)
7347 return SDValue(); // Shuffled V2 input!
7348 BlendMask |= 1u << i;
7351 if (Mask[i] >= 0 && Mask[i] != i)
7352 return SDValue(); // Shuffled V1 input!
7354 switch (VT.SimpleTy) {
7359 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7360 DAG.getConstant(BlendMask, MVT::i8));
7364 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7369 // that instruction.
7370 if (Subtarget->hasAVX2()) {
7371 // Scale the blend by the number of 32-bit dwords per element.
7372 int Scale = VT.getScalarSizeInBits() / 32;
7374 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7375 if (Mask[i] >= Size)
7376 for (int j = 0; j < Scale; ++j)
7377 BlendMask |= 1u << (i * Scale + j);
7379 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7380 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7381 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7382 return DAG.getNode(ISD::BITCAST, DL, VT,
7383 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7384 DAG.getConstant(BlendMask, MVT::i8)));
7388 // For integer shuffles we need to expand the mask and cast the inputs to
7389 // v8i16s prior to blending.
7390 int Scale = 8 / VT.getVectorNumElements();
7392 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7393 if (Mask[i] >= Size)
7394 for (int j = 0; j < Scale; ++j)
7395 BlendMask |= 1u << (i * Scale + j);
7397 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7398 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7399 return DAG.getNode(ISD::BITCAST, DL, VT,
7400 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7401 DAG.getConstant(BlendMask, MVT::i8)));
7405 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7406 SmallVector<int, 8> RepeatedMask;
7407 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7408 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7409 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7411 for (int i = 0; i < 8; ++i)
7412 if (RepeatedMask[i] >= 16)
7413 BlendMask |= 1u << i;
7414 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7415 DAG.getConstant(BlendMask, MVT::i8));
7420 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7421 // Scale the blend by the number of bytes per element.
7422 int Scale = VT.getScalarSizeInBits() / 8;
7423 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7425 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7426 // mix of LLVM's code generator and the x86 backend. We tell the code
7427 // generator that boolean values in the elements of an x86 vector register
7428 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7429 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7430 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7431 // of the element (the remaining are ignored) and 0 in that high bit would
7432 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7433 // the LLVM model for boolean values in vector elements gets the relevant
7434 // bit set, it is set backwards and over constrained relative to x86's
7436 SDValue VSELECTMask[32];
7437 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7438 for (int j = 0; j < Scale; ++j)
7439 VSELECTMask[Scale * i + j] =
7440 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7441 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7443 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7444 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7446 ISD::BITCAST, DL, VT,
7447 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7448 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7453 llvm_unreachable("Not a supported integer vector type!");
7457 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7458 /// unblended shuffles followed by an unshuffled blend.
7460 /// This matches the extremely common pattern for handling combined
7461 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7463 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7467 SelectionDAG &DAG) {
7468 // Shuffle the input elements into the desired positions in V1 and V2 and
7469 // blend them together.
7470 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7471 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7472 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7473 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7474 if (Mask[i] >= 0 && Mask[i] < Size) {
7475 V1Mask[i] = Mask[i];
7477 } else if (Mask[i] >= Size) {
7478 V2Mask[i] = Mask[i] - Size;
7479 BlendMask[i] = i + Size;
7482 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7483 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7484 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7487 /// \brief Try to lower a vector shuffle as a byte rotation.
7489 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7490 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7491 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7492 /// try to generically lower a vector shuffle through such an pattern. It
7493 /// does not check for the profitability of lowering either as PALIGNR or
7494 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7495 /// This matches shuffle vectors that look like:
7497 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7499 /// Essentially it concatenates V1 and V2, shifts right by some number of
7500 /// elements, and takes the low elements as the result. Note that while this is
7501 /// specified as a *right shift* because x86 is little-endian, it is a *left
7502 /// rotate* of the vector lanes.
7504 /// Note that this only handles 128-bit vector widths currently.
7505 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7508 const X86Subtarget *Subtarget,
7509 SelectionDAG &DAG) {
7510 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7512 // We need to detect various ways of spelling a rotation:
7513 // [11, 12, 13, 14, 15, 0, 1, 2]
7514 // [-1, 12, 13, 14, -1, -1, 1, -1]
7515 // [-1, -1, -1, -1, -1, -1, 1, 2]
7516 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7517 // [-1, 4, 5, 6, -1, -1, 9, -1]
7518 // [-1, 4, 5, 6, -1, -1, -1, -1]
7521 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7524 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7526 // Based on the mod-Size value of this mask element determine where
7527 // a rotated vector would have started.
7528 int StartIdx = i - (Mask[i] % Size);
7530 // The identity rotation isn't interesting, stop.
7533 // If we found the tail of a vector the rotation must be the missing
7534 // front. If we found the head of a vector, it must be how much of the head.
7535 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7538 Rotation = CandidateRotation;
7539 else if (Rotation != CandidateRotation)
7540 // The rotations don't match, so we can't match this mask.
7543 // Compute which value this mask is pointing at.
7544 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7546 // Compute which of the two target values this index should be assigned to.
7547 // This reflects whether the high elements are remaining or the low elements
7549 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7551 // Either set up this value if we've not encountered it before, or check
7552 // that it remains consistent.
7555 else if (TargetV != MaskV)
7556 // This may be a rotation, but it pulls from the inputs in some
7557 // unsupported interleaving.
7561 // Check that we successfully analyzed the mask, and normalize the results.
7562 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7563 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7569 assert(VT.getSizeInBits() == 128 &&
7570 "Rotate-based lowering only supports 128-bit lowering!");
7571 assert(Mask.size() <= 16 &&
7572 "Can shuffle at most 16 bytes in a 128-bit vector!");
7574 // The actual rotate instruction rotates bytes, so we need to scale the
7575 // rotation based on how many bytes are in the vector.
7576 int Scale = 16 / Mask.size();
7578 // SSSE3 targets can use the palignr instruction
7579 if (Subtarget->hasSSSE3()) {
7580 // Cast the inputs to v16i8 to match PALIGNR.
7581 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7582 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7584 return DAG.getNode(ISD::BITCAST, DL, VT,
7585 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7586 DAG.getConstant(Rotation * Scale, MVT::i8)));
7589 // Default SSE2 implementation
7590 int LoByteShift = 16 - Rotation * Scale;
7591 int HiByteShift = Rotation * Scale;
7593 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7594 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7595 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7597 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7598 DAG.getConstant(8 * LoByteShift, MVT::i8));
7599 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7600 DAG.getConstant(8 * HiByteShift, MVT::i8));
7601 return DAG.getNode(ISD::BITCAST, DL, VT,
7602 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7605 /// \brief Compute whether each element of a shuffle is zeroable.
7607 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7608 /// Either it is an undef element in the shuffle mask, the element of the input
7609 /// referenced is undef, or the element of the input referenced is known to be
7610 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7611 /// as many lanes with this technique as possible to simplify the remaining
7613 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7614 SDValue V1, SDValue V2) {
7615 SmallBitVector Zeroable(Mask.size(), false);
7617 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7618 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7620 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7622 // Handle the easy cases.
7623 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7628 // If this is an index into a build_vector node, dig out the input value and
7630 SDValue V = M < Size ? V1 : V2;
7631 if (V.getOpcode() != ISD::BUILD_VECTOR)
7634 SDValue Input = V.getOperand(M % Size);
7635 // The UNDEF opcode check really should be dead code here, but not quite
7636 // worth asserting on (it isn't invalid, just unexpected).
7637 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7644 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7646 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7647 /// byte-shift instructions. The mask must consist of a shifted sequential
7648 /// shuffle from one of the input vectors and zeroable elements for the
7649 /// remaining 'shifted in' elements.
7651 /// Note that this only handles 128-bit vector widths currently.
7652 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7653 SDValue V2, ArrayRef<int> Mask,
7654 SelectionDAG &DAG) {
7655 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7657 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7659 int Size = Mask.size();
7660 int Scale = 16 / Size;
7662 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7663 ArrayRef<int> Mask) {
7664 for (int i = StartIndex; i < EndIndex; i++) {
7667 if (i + Base != Mask[i] - MaskOffset)
7673 for (int Shift = 1; Shift < Size; Shift++) {
7674 int ByteShift = Shift * Scale;
7676 // PSRLDQ : (little-endian) right byte shift
7677 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7678 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7679 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7680 bool ZeroableRight = true;
7681 for (int i = Size - Shift; i < Size; i++) {
7682 ZeroableRight &= Zeroable[i];
7685 if (ZeroableRight) {
7686 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7687 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7689 if (ValidShiftRight1 || ValidShiftRight2) {
7690 // Cast the inputs to v2i64 to match PSRLDQ.
7691 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7692 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7693 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7694 DAG.getConstant(ByteShift * 8, MVT::i8));
7695 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7699 // PSLLDQ : (little-endian) left byte shift
7700 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7701 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7702 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7703 bool ZeroableLeft = true;
7704 for (int i = 0; i < Shift; i++) {
7705 ZeroableLeft &= Zeroable[i];
7709 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7710 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7712 if (ValidShiftLeft1 || ValidShiftLeft2) {
7713 // Cast the inputs to v2i64 to match PSLLDQ.
7714 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7715 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7716 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7717 DAG.getConstant(ByteShift * 8, MVT::i8));
7718 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7726 /// \brief Lower a vector shuffle as a zero or any extension.
7728 /// Given a specific number of elements, element bit width, and extension
7729 /// stride, produce either a zero or any extension based on the available
7730 /// features of the subtarget.
7731 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7732 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7733 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7734 assert(Scale > 1 && "Need a scale to extend.");
7735 int EltBits = VT.getSizeInBits() / NumElements;
7736 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7737 "Only 8, 16, and 32 bit elements can be extended.");
7738 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7740 // Found a valid zext mask! Try various lowering strategies based on the
7741 // input type and available ISA extensions.
7742 if (Subtarget->hasSSE41()) {
7743 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7744 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7745 NumElements / Scale);
7746 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7747 return DAG.getNode(ISD::BITCAST, DL, VT,
7748 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7751 // For any extends we can cheat for larger element sizes and use shuffle
7752 // instructions that can fold with a load and/or copy.
7753 if (AnyExt && EltBits == 32) {
7754 int PSHUFDMask[4] = {0, -1, 1, -1};
7756 ISD::BITCAST, DL, VT,
7757 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7758 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7759 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7761 if (AnyExt && EltBits == 16 && Scale > 2) {
7762 int PSHUFDMask[4] = {0, -1, 0, -1};
7763 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7764 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7765 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7766 int PSHUFHWMask[4] = {1, -1, -1, -1};
7768 ISD::BITCAST, DL, VT,
7769 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7770 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7771 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7774 // If this would require more than 2 unpack instructions to expand, use
7775 // pshufb when available. We can only use more than 2 unpack instructions
7776 // when zero extending i8 elements which also makes it easier to use pshufb.
7777 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7778 assert(NumElements == 16 && "Unexpected byte vector width!");
7779 SDValue PSHUFBMask[16];
7780 for (int i = 0; i < 16; ++i)
7782 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7783 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7784 return DAG.getNode(ISD::BITCAST, DL, VT,
7785 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7786 DAG.getNode(ISD::BUILD_VECTOR, DL,
7787 MVT::v16i8, PSHUFBMask)));
7790 // Otherwise emit a sequence of unpacks.
7792 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7793 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7794 : getZeroVector(InputVT, Subtarget, DAG, DL);
7795 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7796 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7800 } while (Scale > 1);
7801 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7804 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7806 /// This routine will try to do everything in its power to cleverly lower
7807 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7808 /// check for the profitability of this lowering, it tries to aggressively
7809 /// match this pattern. It will use all of the micro-architectural details it
7810 /// can to emit an efficient lowering. It handles both blends with all-zero
7811 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7812 /// masking out later).
7814 /// The reason we have dedicated lowering for zext-style shuffles is that they
7815 /// are both incredibly common and often quite performance sensitive.
7816 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7817 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7818 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7819 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7821 int Bits = VT.getSizeInBits();
7822 int NumElements = Mask.size();
7824 // Define a helper function to check a particular ext-scale and lower to it if
7826 auto Lower = [&](int Scale) -> SDValue {
7829 for (int i = 0; i < NumElements; ++i) {
7831 continue; // Valid anywhere but doesn't tell us anything.
7832 if (i % Scale != 0) {
7833 // Each of the extend elements needs to be zeroable.
7837 // We no lorger are in the anyext case.
7842 // Each of the base elements needs to be consecutive indices into the
7843 // same input vector.
7844 SDValue V = Mask[i] < NumElements ? V1 : V2;
7847 else if (InputV != V)
7848 return SDValue(); // Flip-flopping inputs.
7850 if (Mask[i] % NumElements != i / Scale)
7851 return SDValue(); // Non-consecutive strided elemenst.
7854 // If we fail to find an input, we have a zero-shuffle which should always
7855 // have already been handled.
7856 // FIXME: Maybe handle this here in case during blending we end up with one?
7860 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7861 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7864 // The widest scale possible for extending is to a 64-bit integer.
7865 assert(Bits % 64 == 0 &&
7866 "The number of bits in a vector must be divisible by 64 on x86!");
7867 int NumExtElements = Bits / 64;
7869 // Each iteration, try extending the elements half as much, but into twice as
7871 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7872 assert(NumElements % NumExtElements == 0 &&
7873 "The input vector size must be divisble by the extended size.");
7874 if (SDValue V = Lower(NumElements / NumExtElements))
7878 // No viable ext lowering found.
7882 /// \brief Try to get a scalar value for a specific element of a vector.
7884 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7885 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7886 SelectionDAG &DAG) {
7887 MVT VT = V.getSimpleValueType();
7888 MVT EltVT = VT.getVectorElementType();
7889 while (V.getOpcode() == ISD::BITCAST)
7890 V = V.getOperand(0);
7891 // If the bitcasts shift the element size, we can't extract an equivalent
7893 MVT NewVT = V.getSimpleValueType();
7894 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7897 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7898 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7899 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7904 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7906 /// This is particularly important because the set of instructions varies
7907 /// significantly based on whether the operand is a load or not.
7908 static bool isShuffleFoldableLoad(SDValue V) {
7909 while (V.getOpcode() == ISD::BITCAST)
7910 V = V.getOperand(0);
7912 return ISD::isNON_EXTLoad(V.getNode());
7915 /// \brief Try to lower insertion of a single element into a zero vector.
7917 /// This is a common pattern that we have especially efficient patterns to lower
7918 /// across all subtarget feature sets.
7919 static SDValue lowerVectorShuffleAsElementInsertion(
7920 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7921 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7922 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7924 MVT EltVT = VT.getVectorElementType();
7926 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7927 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7929 bool IsV1Zeroable = true;
7930 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7931 if (i != V2Index && !Zeroable[i]) {
7932 IsV1Zeroable = false;
7936 // Check for a single input from a SCALAR_TO_VECTOR node.
7937 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7938 // all the smarts here sunk into that routine. However, the current
7939 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7940 // vector shuffle lowering is dead.
7941 if (SDValue V2S = getScalarValueForVectorElement(
7942 V2, Mask[V2Index] - Mask.size(), DAG)) {
7943 // We need to zext the scalar if it is smaller than an i32.
7944 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7945 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7946 // Using zext to expand a narrow element won't work for non-zero
7951 // Zero-extend directly to i32.
7953 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7955 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7956 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7957 EltVT == MVT::i16) {
7958 // Either not inserting from the low element of the input or the input
7959 // element size is too small to use VZEXT_MOVL to clear the high bits.
7963 if (!IsV1Zeroable) {
7964 // If V1 can't be treated as a zero vector we have fewer options to lower
7965 // this. We can't support integer vectors or non-zero targets cheaply, and
7966 // the V1 elements can't be permuted in any way.
7967 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7968 if (!VT.isFloatingPoint() || V2Index != 0)
7970 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7971 V1Mask[V2Index] = -1;
7972 if (!isNoopShuffleMask(V1Mask))
7974 // This is essentially a special case blend operation, but if we have
7975 // general purpose blend operations, they are always faster. Bail and let
7976 // the rest of the lowering handle these as blends.
7977 if (Subtarget->hasSSE41())
7980 // Otherwise, use MOVSD or MOVSS.
7981 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7982 "Only two types of floating point element types to handle!");
7983 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7987 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7989 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7992 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7993 // the desired position. Otherwise it is more efficient to do a vector
7994 // shift left. We know that we can do a vector shift left because all
7995 // the inputs are zero.
7996 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7997 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7998 V2Shuffle[V2Index] = 0;
7999 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8001 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8003 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8005 V2Index * EltVT.getSizeInBits(),
8006 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8007 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8013 /// \brief Try to lower broadcast of a single element.
8015 /// For convenience, this code also bundles all of the subtarget feature set
8016 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8017 /// a convenient way to factor it out.
8018 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8020 const X86Subtarget *Subtarget,
8021 SelectionDAG &DAG) {
8022 if (!Subtarget->hasAVX())
8024 if (VT.isInteger() && !Subtarget->hasAVX2())
8027 // Check that the mask is a broadcast.
8028 int BroadcastIdx = -1;
8030 if (M >= 0 && BroadcastIdx == -1)
8032 else if (M >= 0 && M != BroadcastIdx)
8035 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8036 "a sorted mask where the broadcast "
8039 // Go up the chain of (vector) values to try and find a scalar load that
8040 // we can combine with the broadcast.
8042 switch (V.getOpcode()) {
8043 case ISD::CONCAT_VECTORS: {
8044 int OperandSize = Mask.size() / V.getNumOperands();
8045 V = V.getOperand(BroadcastIdx / OperandSize);
8046 BroadcastIdx %= OperandSize;
8050 case ISD::INSERT_SUBVECTOR: {
8051 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8052 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8056 int BeginIdx = (int)ConstantIdx->getZExtValue();
8058 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8059 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8060 BroadcastIdx -= BeginIdx;
8071 // Check if this is a broadcast of a scalar. We special case lowering
8072 // for scalars so that we can more effectively fold with loads.
8073 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8074 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8075 V = V.getOperand(BroadcastIdx);
8077 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8079 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8081 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8082 // We can't broadcast from a vector register w/o AVX2, and we can only
8083 // broadcast from the zero-element of a vector register.
8087 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8090 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8092 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8093 /// support for floating point shuffles but not integer shuffles. These
8094 /// instructions will incur a domain crossing penalty on some chips though so
8095 /// it is better to avoid lowering through this for integer vectors where
8097 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8098 const X86Subtarget *Subtarget,
8099 SelectionDAG &DAG) {
8101 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8102 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8105 ArrayRef<int> Mask = SVOp->getMask();
8106 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8108 if (isSingleInputShuffleMask(Mask)) {
8109 // Straight shuffle of a single input vector. Simulate this by using the
8110 // single input as both of the "inputs" to this instruction..
8111 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8113 if (Subtarget->hasAVX()) {
8114 // If we have AVX, we can use VPERMILPS which will allow folding a load
8115 // into the shuffle.
8116 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8117 DAG.getConstant(SHUFPDMask, MVT::i8));
8120 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8121 DAG.getConstant(SHUFPDMask, MVT::i8));
8123 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8124 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8126 // Use dedicated unpack instructions for masks that match their pattern.
8127 if (isShuffleEquivalent(Mask, 0, 2))
8128 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8129 if (isShuffleEquivalent(Mask, 1, 3))
8130 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8132 // If we have a single input, insert that into V1 if we can do so cheaply.
8133 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8134 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8135 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8137 // Try inverting the insertion since for v2 masks it is easy to do and we
8138 // can't reliably sort the mask one way or the other.
8139 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8140 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8142 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8146 // Try to use one of the special instruction patterns to handle two common
8147 // blend patterns if a zero-blend above didn't work.
8148 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8149 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8150 // We can either use a special instruction to load over the low double or
8151 // to move just the low double.
8153 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8155 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8157 if (Subtarget->hasSSE41())
8158 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8162 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8163 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8164 DAG.getConstant(SHUFPDMask, MVT::i8));
8167 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8169 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8170 /// the integer unit to minimize domain crossing penalties. However, for blends
8171 /// it falls back to the floating point shuffle operation with appropriate bit
8173 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8174 const X86Subtarget *Subtarget,
8175 SelectionDAG &DAG) {
8177 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8178 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8181 ArrayRef<int> Mask = SVOp->getMask();
8182 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8184 if (isSingleInputShuffleMask(Mask)) {
8185 // Check for being able to broadcast a single element.
8186 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8187 Mask, Subtarget, DAG))
8190 // Straight shuffle of a single input vector. For everything from SSE2
8191 // onward this has a single fast instruction with no scary immediates.
8192 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8193 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8194 int WidenedMask[4] = {
8195 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8196 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8198 ISD::BITCAST, DL, MVT::v2i64,
8199 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8200 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8203 // If we have a single input from V2 insert that into V1 if we can do so
8205 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8206 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8207 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8209 // Try inverting the insertion since for v2 masks it is easy to do and we
8210 // can't reliably sort the mask one way or the other.
8211 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8212 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8213 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8214 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8218 // Use dedicated unpack instructions for masks that match their pattern.
8219 if (isShuffleEquivalent(Mask, 0, 2))
8220 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8221 if (isShuffleEquivalent(Mask, 1, 3))
8222 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8224 if (Subtarget->hasSSE41())
8225 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8229 // Try to use byte shift instructions.
8230 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8231 DL, MVT::v2i64, V1, V2, Mask, DAG))
8234 // Try to use byte rotation instructions.
8235 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8236 if (Subtarget->hasSSSE3())
8237 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8238 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8241 // We implement this with SHUFPD which is pretty lame because it will likely
8242 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8243 // However, all the alternatives are still more cycles and newer chips don't
8244 // have this problem. It would be really nice if x86 had better shuffles here.
8245 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8246 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8247 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8248 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8251 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8253 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8254 /// It makes no assumptions about whether this is the *best* lowering, it simply
8256 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8257 ArrayRef<int> Mask, SDValue V1,
8258 SDValue V2, SelectionDAG &DAG) {
8259 SDValue LowV = V1, HighV = V2;
8260 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8263 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8265 if (NumV2Elements == 1) {
8267 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8270 // Compute the index adjacent to V2Index and in the same half by toggling
8272 int V2AdjIndex = V2Index ^ 1;
8274 if (Mask[V2AdjIndex] == -1) {
8275 // Handles all the cases where we have a single V2 element and an undef.
8276 // This will only ever happen in the high lanes because we commute the
8277 // vector otherwise.
8279 std::swap(LowV, HighV);
8280 NewMask[V2Index] -= 4;
8282 // Handle the case where the V2 element ends up adjacent to a V1 element.
8283 // To make this work, blend them together as the first step.
8284 int V1Index = V2AdjIndex;
8285 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8286 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8287 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8289 // Now proceed to reconstruct the final blend as we have the necessary
8290 // high or low half formed.
8297 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8298 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8300 } else if (NumV2Elements == 2) {
8301 if (Mask[0] < 4 && Mask[1] < 4) {
8302 // Handle the easy case where we have V1 in the low lanes and V2 in the
8306 } else if (Mask[2] < 4 && Mask[3] < 4) {
8307 // We also handle the reversed case because this utility may get called
8308 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8309 // arrange things in the right direction.
8315 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8316 // trying to place elements directly, just blend them and set up the final
8317 // shuffle to place them.
8319 // The first two blend mask elements are for V1, the second two are for
8321 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8322 Mask[2] < 4 ? Mask[2] : Mask[3],
8323 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8324 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8325 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8326 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8328 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8331 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8332 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8333 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8334 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8337 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8338 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8341 /// \brief Lower 4-lane 32-bit floating point shuffles.
8343 /// Uses instructions exclusively from the floating point unit to minimize
8344 /// domain crossing penalties, as these are sufficient to implement all v4f32
8346 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8347 const X86Subtarget *Subtarget,
8348 SelectionDAG &DAG) {
8350 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8351 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8354 ArrayRef<int> Mask = SVOp->getMask();
8355 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8358 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8360 if (NumV2Elements == 0) {
8361 // Check for being able to broadcast a single element.
8362 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8363 Mask, Subtarget, DAG))
8366 if (Subtarget->hasAVX()) {
8367 // If we have AVX, we can use VPERMILPS which will allow folding a load
8368 // into the shuffle.
8369 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8370 getV4X86ShuffleImm8ForMask(Mask, DAG));
8373 // Otherwise, use a straight shuffle of a single input vector. We pass the
8374 // input vector to both operands to simulate this with a SHUFPS.
8375 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8376 getV4X86ShuffleImm8ForMask(Mask, DAG));
8379 // Use dedicated unpack instructions for masks that match their pattern.
8380 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8381 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8382 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8383 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8385 // There are special ways we can lower some single-element blends. However, we
8386 // have custom ways we can lower more complex single-element blends below that
8387 // we defer to if both this and BLENDPS fail to match, so restrict this to
8388 // when the V2 input is targeting element 0 of the mask -- that is the fast
8390 if (NumV2Elements == 1 && Mask[0] >= 4)
8391 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8392 Mask, Subtarget, DAG))
8395 if (Subtarget->hasSSE41())
8396 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8400 // Check for whether we can use INSERTPS to perform the blend. We only use
8401 // INSERTPS when the V1 elements are already in the correct locations
8402 // because otherwise we can just always use two SHUFPS instructions which
8403 // are much smaller to encode than a SHUFPS and an INSERTPS.
8404 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8406 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8409 // When using INSERTPS we can zero any lane of the destination. Collect
8410 // the zero inputs into a mask and drop them from the lanes of V1 which
8411 // actually need to be present as inputs to the INSERTPS.
8412 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8414 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8415 bool InsertNeedsShuffle = false;
8417 for (int i = 0; i < 4; ++i)
8421 } else if (Mask[i] != i) {
8422 InsertNeedsShuffle = true;
8427 // We don't want to use INSERTPS or other insertion techniques if it will
8428 // require shuffling anyways.
8429 if (!InsertNeedsShuffle) {
8430 // If all of V1 is zeroable, replace it with undef.
8431 if ((ZMask | 1 << V2Index) == 0xF)
8432 V1 = DAG.getUNDEF(MVT::v4f32);
8434 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8435 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8437 // Insert the V2 element into the desired position.
8438 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8439 DAG.getConstant(InsertPSMask, MVT::i8));
8443 // Otherwise fall back to a SHUFPS lowering strategy.
8444 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8447 /// \brief Lower 4-lane i32 vector shuffles.
8449 /// We try to handle these with integer-domain shuffles where we can, but for
8450 /// blends we use the floating point domain blend instructions.
8451 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8452 const X86Subtarget *Subtarget,
8453 SelectionDAG &DAG) {
8455 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8456 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8459 ArrayRef<int> Mask = SVOp->getMask();
8460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8462 // Whenever we can lower this as a zext, that instruction is strictly faster
8463 // than any alternative. It also allows us to fold memory operands into the
8464 // shuffle in many cases.
8465 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8466 Mask, Subtarget, DAG))
8470 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8472 if (NumV2Elements == 0) {
8473 // Check for being able to broadcast a single element.
8474 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8475 Mask, Subtarget, DAG))
8478 // Straight shuffle of a single input vector. For everything from SSE2
8479 // onward this has a single fast instruction with no scary immediates.
8480 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8481 // but we aren't actually going to use the UNPCK instruction because doing
8482 // so prevents folding a load into this instruction or making a copy.
8483 const int UnpackLoMask[] = {0, 0, 1, 1};
8484 const int UnpackHiMask[] = {2, 2, 3, 3};
8485 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8486 Mask = UnpackLoMask;
8487 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8488 Mask = UnpackHiMask;
8490 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8491 getV4X86ShuffleImm8ForMask(Mask, DAG));
8494 // There are special ways we can lower some single-element blends.
8495 if (NumV2Elements == 1)
8496 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8497 Mask, Subtarget, DAG))
8500 // Use dedicated unpack instructions for masks that match their pattern.
8501 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8502 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8503 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8504 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8506 if (Subtarget->hasSSE41())
8507 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8511 // Try to use byte shift instructions.
8512 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8513 DL, MVT::v4i32, V1, V2, Mask, DAG))
8516 // Try to use byte rotation instructions.
8517 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8518 if (Subtarget->hasSSSE3())
8519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8520 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8523 // We implement this with SHUFPS because it can blend from two vectors.
8524 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8525 // up the inputs, bypassing domain shift penalties that we would encur if we
8526 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8528 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8529 DAG.getVectorShuffle(
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8532 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8535 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8536 /// shuffle lowering, and the most complex part.
8538 /// The lowering strategy is to try to form pairs of input lanes which are
8539 /// targeted at the same half of the final vector, and then use a dword shuffle
8540 /// to place them onto the right half, and finally unpack the paired lanes into
8541 /// their final position.
8543 /// The exact breakdown of how to form these dword pairs and align them on the
8544 /// correct sides is really tricky. See the comments within the function for
8545 /// more of the details.
8546 static SDValue lowerV8I16SingleInputVectorShuffle(
8547 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8548 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8549 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8550 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8551 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8553 SmallVector<int, 4> LoInputs;
8554 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8555 [](int M) { return M >= 0; });
8556 std::sort(LoInputs.begin(), LoInputs.end());
8557 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8558 SmallVector<int, 4> HiInputs;
8559 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8560 [](int M) { return M >= 0; });
8561 std::sort(HiInputs.begin(), HiInputs.end());
8562 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8564 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8565 int NumHToL = LoInputs.size() - NumLToL;
8567 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8568 int NumHToH = HiInputs.size() - NumLToH;
8569 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8570 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8571 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8572 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8574 // Check for being able to broadcast a single element.
8575 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8576 Mask, Subtarget, DAG))
8579 // Use dedicated unpack instructions for masks that match their pattern.
8580 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8581 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8582 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8583 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8585 // Try to use byte shift instructions.
8586 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8587 DL, MVT::v8i16, V, V, Mask, DAG))
8590 // Try to use byte rotation instructions.
8591 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8592 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8595 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8596 // such inputs we can swap two of the dwords across the half mark and end up
8597 // with <=2 inputs to each half in each half. Once there, we can fall through
8598 // to the generic code below. For example:
8600 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8601 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8603 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8604 // and an existing 2-into-2 on the other half. In this case we may have to
8605 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8606 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8607 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8608 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8609 // half than the one we target for fixing) will be fixed when we re-enter this
8610 // path. We will also combine away any sequence of PSHUFD instructions that
8611 // result into a single instruction. Here is an example of the tricky case:
8613 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8614 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8616 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8618 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8619 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8621 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8622 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8624 // The result is fine to be handled by the generic logic.
8625 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8626 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8627 int AOffset, int BOffset) {
8628 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8629 "Must call this with A having 3 or 1 inputs from the A half.");
8630 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8631 "Must call this with B having 1 or 3 inputs from the B half.");
8632 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8633 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8635 // Compute the index of dword with only one word among the three inputs in
8636 // a half by taking the sum of the half with three inputs and subtracting
8637 // the sum of the actual three inputs. The difference is the remaining
8640 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8641 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8642 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8643 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8644 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8645 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8646 int TripleNonInputIdx =
8647 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8648 TripleDWord = TripleNonInputIdx / 2;
8650 // We use xor with one to compute the adjacent DWord to whichever one the
8652 OneInputDWord = (OneInput / 2) ^ 1;
8654 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8655 // and BToA inputs. If there is also such a problem with the BToB and AToB
8656 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8657 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8658 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8659 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8660 // Compute how many inputs will be flipped by swapping these DWords. We
8662 // to balance this to ensure we don't form a 3-1 shuffle in the other
8664 int NumFlippedAToBInputs =
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8666 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8667 int NumFlippedBToBInputs =
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8669 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8670 if ((NumFlippedAToBInputs == 1 &&
8671 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8672 (NumFlippedBToBInputs == 1 &&
8673 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8674 // We choose whether to fix the A half or B half based on whether that
8675 // half has zero flipped inputs. At zero, we may not be able to fix it
8676 // with that half. We also bias towards fixing the B half because that
8677 // will more commonly be the high half, and we have to bias one way.
8678 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8679 ArrayRef<int> Inputs) {
8680 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8681 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8682 PinnedIdx ^ 1) != Inputs.end();
8683 // Determine whether the free index is in the flipped dword or the
8684 // unflipped dword based on where the pinned index is. We use this bit
8685 // in an xor to conditionally select the adjacent dword.
8686 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8687 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8688 FixFreeIdx) != Inputs.end();
8689 if (IsFixIdxInput == IsFixFreeIdxInput)
8691 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8692 FixFreeIdx) != Inputs.end();
8693 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8694 "We need to be changing the number of flipped inputs!");
8695 int PSHUFHalfMask[] = {0, 1, 2, 3};
8696 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8697 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8699 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8702 if (M != -1 && M == FixIdx)
8704 else if (M != -1 && M == FixFreeIdx)
8707 if (NumFlippedBToBInputs != 0) {
8709 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8710 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8712 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8714 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8715 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8720 int PSHUFDMask[] = {0, 1, 2, 3};
8721 PSHUFDMask[ADWord] = BDWord;
8722 PSHUFDMask[BDWord] = ADWord;
8723 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8724 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8725 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8726 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8728 // Adjust the mask to match the new locations of A and B.
8730 if (M != -1 && M/2 == ADWord)
8731 M = 2 * BDWord + M % 2;
8732 else if (M != -1 && M/2 == BDWord)
8733 M = 2 * ADWord + M % 2;
8735 // Recurse back into this routine to re-compute state now that this isn't
8736 // a 3 and 1 problem.
8737 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8740 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8741 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8742 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8743 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8745 // At this point there are at most two inputs to the low and high halves from
8746 // each half. That means the inputs can always be grouped into dwords and
8747 // those dwords can then be moved to the correct half with a dword shuffle.
8748 // We use at most one low and one high word shuffle to collect these paired
8749 // inputs into dwords, and finally a dword shuffle to place them.
8750 int PSHUFLMask[4] = {-1, -1, -1, -1};
8751 int PSHUFHMask[4] = {-1, -1, -1, -1};
8752 int PSHUFDMask[4] = {-1, -1, -1, -1};
8754 // First fix the masks for all the inputs that are staying in their
8755 // original halves. This will then dictate the targets of the cross-half
8757 auto fixInPlaceInputs =
8758 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8759 MutableArrayRef<int> SourceHalfMask,
8760 MutableArrayRef<int> HalfMask, int HalfOffset) {
8761 if (InPlaceInputs.empty())
8763 if (InPlaceInputs.size() == 1) {
8764 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8765 InPlaceInputs[0] - HalfOffset;
8766 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8769 if (IncomingInputs.empty()) {
8770 // Just fix all of the in place inputs.
8771 for (int Input : InPlaceInputs) {
8772 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8773 PSHUFDMask[Input / 2] = Input / 2;
8778 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8779 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8780 InPlaceInputs[0] - HalfOffset;
8781 // Put the second input next to the first so that they are packed into
8782 // a dword. We find the adjacent index by toggling the low bit.
8783 int AdjIndex = InPlaceInputs[0] ^ 1;
8784 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8785 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8786 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8788 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8789 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8791 // Now gather the cross-half inputs and place them into a free dword of
8792 // their target half.
8793 // FIXME: This operation could almost certainly be simplified dramatically to
8794 // look more like the 3-1 fixing operation.
8795 auto moveInputsToRightHalf = [&PSHUFDMask](
8796 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8797 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8798 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8800 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8801 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8803 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8805 int LowWord = Word & ~1;
8806 int HighWord = Word | 1;
8807 return isWordClobbered(SourceHalfMask, LowWord) ||
8808 isWordClobbered(SourceHalfMask, HighWord);
8811 if (IncomingInputs.empty())
8814 if (ExistingInputs.empty()) {
8815 // Map any dwords with inputs from them into the right half.
8816 for (int Input : IncomingInputs) {
8817 // If the source half mask maps over the inputs, turn those into
8818 // swaps and use the swapped lane.
8819 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8820 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8821 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8822 Input - SourceOffset;
8823 // We have to swap the uses in our half mask in one sweep.
8824 for (int &M : HalfMask)
8825 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8827 else if (M == Input)
8828 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8830 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8831 Input - SourceOffset &&
8832 "Previous placement doesn't match!");
8834 // Note that this correctly re-maps both when we do a swap and when
8835 // we observe the other side of the swap above. We rely on that to
8836 // avoid swapping the members of the input list directly.
8837 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8840 // Map the input's dword into the correct half.
8841 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8842 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8844 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8846 "Previous placement doesn't match!");
8849 // And just directly shift any other-half mask elements to be same-half
8850 // as we will have mirrored the dword containing the element into the
8851 // same position within that half.
8852 for (int &M : HalfMask)
8853 if (M >= SourceOffset && M < SourceOffset + 4) {
8854 M = M - SourceOffset + DestOffset;
8855 assert(M >= 0 && "This should never wrap below zero!");
8860 // Ensure we have the input in a viable dword of its current half. This
8861 // is particularly tricky because the original position may be clobbered
8862 // by inputs being moved and *staying* in that half.
8863 if (IncomingInputs.size() == 1) {
8864 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8865 int InputFixed = std::find(std::begin(SourceHalfMask),
8866 std::end(SourceHalfMask), -1) -
8867 std::begin(SourceHalfMask) + SourceOffset;
8868 SourceHalfMask[InputFixed - SourceOffset] =
8869 IncomingInputs[0] - SourceOffset;
8870 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8872 IncomingInputs[0] = InputFixed;
8874 } else if (IncomingInputs.size() == 2) {
8875 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8876 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8877 // We have two non-adjacent or clobbered inputs we need to extract from
8878 // the source half. To do this, we need to map them into some adjacent
8879 // dword slot in the source mask.
8880 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8881 IncomingInputs[1] - SourceOffset};
8883 // If there is a free slot in the source half mask adjacent to one of
8884 // the inputs, place the other input in it. We use (Index XOR 1) to
8885 // compute an adjacent index.
8886 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8887 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8888 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8889 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8890 InputsFixed[1] = InputsFixed[0] ^ 1;
8891 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8892 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8893 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8894 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8895 InputsFixed[0] = InputsFixed[1] ^ 1;
8896 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8897 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8898 // The two inputs are in the same DWord but it is clobbered and the
8899 // adjacent DWord isn't used at all. Move both inputs to the free
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8902 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8903 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8904 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8906 // The only way we hit this point is if there is no clobbering
8907 // (because there are no off-half inputs to this half) and there is no
8908 // free slot adjacent to one of the inputs. In this case, we have to
8909 // swap an input with a non-input.
8910 for (int i = 0; i < 4; ++i)
8911 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8912 "We can't handle any clobbers here!");
8913 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8914 "Cannot have adjacent inputs here!");
8916 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8917 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8919 // We also have to update the final source mask in this case because
8920 // it may need to undo the above swap.
8921 for (int &M : FinalSourceHalfMask)
8922 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8923 M = InputsFixed[1] + SourceOffset;
8924 else if (M == InputsFixed[1] + SourceOffset)
8925 M = (InputsFixed[0] ^ 1) + SourceOffset;
8927 InputsFixed[1] = InputsFixed[0] ^ 1;
8930 // Point everything at the fixed inputs.
8931 for (int &M : HalfMask)
8932 if (M == IncomingInputs[0])
8933 M = InputsFixed[0] + SourceOffset;
8934 else if (M == IncomingInputs[1])
8935 M = InputsFixed[1] + SourceOffset;
8937 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8938 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8941 llvm_unreachable("Unhandled input size!");
8944 // Now hoist the DWord down to the right half.
8945 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8946 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8947 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8948 for (int &M : HalfMask)
8949 for (int Input : IncomingInputs)
8951 M = FreeDWord * 2 + Input % 2;
8953 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8954 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8955 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8956 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8958 // Now enact all the shuffles we've computed to move the inputs into their
8960 if (!isNoopShuffleMask(PSHUFLMask))
8961 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8962 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8963 if (!isNoopShuffleMask(PSHUFHMask))
8964 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8965 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8966 if (!isNoopShuffleMask(PSHUFDMask))
8967 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8968 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8969 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8970 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8972 // At this point, each half should contain all its inputs, and we can then
8973 // just shuffle them into their final position.
8974 assert(std::count_if(LoMask.begin(), LoMask.end(),
8975 [](int M) { return M >= 4; }) == 0 &&
8976 "Failed to lift all the high half inputs to the low mask!");
8977 assert(std::count_if(HiMask.begin(), HiMask.end(),
8978 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8979 "Failed to lift all the low half inputs to the high mask!");
8981 // Do a half shuffle for the low mask.
8982 if (!isNoopShuffleMask(LoMask))
8983 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8984 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8986 // Do a half shuffle with the high mask after shifting its values down.
8987 for (int &M : HiMask)
8990 if (!isNoopShuffleMask(HiMask))
8991 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8992 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8997 /// \brief Detect whether the mask pattern should be lowered through
9000 /// This essentially tests whether viewing the mask as an interleaving of two
9001 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9002 /// lowering it through interleaving is a significantly better strategy.
9003 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9004 int NumEvenInputs[2] = {0, 0};
9005 int NumOddInputs[2] = {0, 0};
9006 int NumLoInputs[2] = {0, 0};
9007 int NumHiInputs[2] = {0, 0};
9008 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9012 int InputIdx = Mask[i] >= Size;
9015 ++NumLoInputs[InputIdx];
9017 ++NumHiInputs[InputIdx];
9020 ++NumEvenInputs[InputIdx];
9022 ++NumOddInputs[InputIdx];
9025 // The minimum number of cross-input results for both the interleaved and
9026 // split cases. If interleaving results in fewer cross-input results, return
9028 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9029 NumEvenInputs[0] + NumOddInputs[1]);
9030 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9031 NumLoInputs[0] + NumHiInputs[1]);
9032 return InterleavedCrosses < SplitCrosses;
9035 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9037 /// This strategy only works when the inputs from each vector fit into a single
9038 /// half of that vector, and generally there are not so many inputs as to leave
9039 /// the in-place shuffles required highly constrained (and thus expensive). It
9040 /// shifts all the inputs into a single side of both input vectors and then
9041 /// uses an unpack to interleave these inputs in a single vector. At that
9042 /// point, we will fall back on the generic single input shuffle lowering.
9043 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9045 MutableArrayRef<int> Mask,
9046 const X86Subtarget *Subtarget,
9047 SelectionDAG &DAG) {
9048 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9050 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9051 for (int i = 0; i < 8; ++i)
9052 if (Mask[i] >= 0 && Mask[i] < 4)
9053 LoV1Inputs.push_back(i);
9054 else if (Mask[i] >= 4 && Mask[i] < 8)
9055 HiV1Inputs.push_back(i);
9056 else if (Mask[i] >= 8 && Mask[i] < 12)
9057 LoV2Inputs.push_back(i);
9058 else if (Mask[i] >= 12)
9059 HiV2Inputs.push_back(i);
9061 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9062 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9065 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9067 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9069 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9070 HiV1Inputs.size() + HiV2Inputs.size();
9072 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9073 ArrayRef<int> HiInputs, bool MoveToLo,
9075 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9076 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9077 if (BadInputs.empty())
9080 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9081 int MoveOffset = MoveToLo ? 0 : 4;
9083 if (GoodInputs.empty()) {
9084 for (int BadInput : BadInputs) {
9085 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9086 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9089 if (GoodInputs.size() == 2) {
9090 // If the low inputs are spread across two dwords, pack them into
9092 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9093 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9094 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9095 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9097 // Otherwise pin the good inputs.
9098 for (int GoodInput : GoodInputs)
9099 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9102 if (BadInputs.size() == 2) {
9103 // If we have two bad inputs then there may be either one or two good
9104 // inputs fixed in place. Find a fixed input, and then find the *other*
9105 // two adjacent indices by using modular arithmetic.
9107 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9108 [](int M) { return M >= 0; }) -
9109 std::begin(MoveMask);
9111 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9112 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9113 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9114 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9115 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9116 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9117 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9119 assert(BadInputs.size() == 1 && "All sizes handled");
9120 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9121 std::end(MoveMask), -1) -
9122 std::begin(MoveMask);
9123 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9124 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9128 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9131 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9133 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9136 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9137 // cross-half traffic in the final shuffle.
9139 // Munge the mask to be a single-input mask after the unpack merges the
9143 M = 2 * (M % 4) + (M / 8);
9145 return DAG.getVectorShuffle(
9146 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9147 DL, MVT::v8i16, V1, V2),
9148 DAG.getUNDEF(MVT::v8i16), Mask);
9151 /// \brief Generic lowering of 8-lane i16 shuffles.
9153 /// This handles both single-input shuffles and combined shuffle/blends with
9154 /// two inputs. The single input shuffles are immediately delegated to
9155 /// a dedicated lowering routine.
9157 /// The blends are lowered in one of three fundamental ways. If there are few
9158 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9159 /// of the input is significantly cheaper when lowered as an interleaving of
9160 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9161 /// halves of the inputs separately (making them have relatively few inputs)
9162 /// and then concatenate them.
9163 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9164 const X86Subtarget *Subtarget,
9165 SelectionDAG &DAG) {
9167 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9168 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9171 ArrayRef<int> OrigMask = SVOp->getMask();
9172 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9173 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9174 MutableArrayRef<int> Mask(MaskStorage);
9176 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9178 // Whenever we can lower this as a zext, that instruction is strictly faster
9179 // than any alternative.
9180 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9181 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9184 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9185 auto isV2 = [](int M) { return M >= 8; };
9187 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9188 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9190 if (NumV2Inputs == 0)
9191 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9193 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9194 "to be V1-input shuffles.");
9196 // There are special ways we can lower some single-element blends.
9197 if (NumV2Inputs == 1)
9198 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9199 Mask, Subtarget, DAG))
9202 // Use dedicated unpack instructions for masks that match their pattern.
9203 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9204 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9205 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9206 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9208 if (Subtarget->hasSSE41())
9209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9213 // Try to use byte shift instructions.
9214 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9215 DL, MVT::v8i16, V1, V2, Mask, DAG))
9218 // Try to use byte rotation instructions.
9219 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9220 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9223 if (NumV1Inputs + NumV2Inputs <= 4)
9224 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9226 // Check whether an interleaving lowering is likely to be more efficient.
9227 // This isn't perfect but it is a strong heuristic that tends to work well on
9228 // the kinds of shuffles that show up in practice.
9230 // FIXME: Handle 1x, 2x, and 4x interleaving.
9231 if (shouldLowerAsInterleaving(Mask)) {
9232 // FIXME: Figure out whether we should pack these into the low or high
9235 int EMask[8], OMask[8];
9236 for (int i = 0; i < 4; ++i) {
9237 EMask[i] = Mask[2*i];
9238 OMask[i] = Mask[2*i + 1];
9243 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9244 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9246 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9249 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9250 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9252 for (int i = 0; i < 4; ++i) {
9253 LoBlendMask[i] = Mask[i];
9254 HiBlendMask[i] = Mask[i + 4];
9257 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9258 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9259 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9260 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9262 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9263 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9266 /// \brief Check whether a compaction lowering can be done by dropping even
9267 /// elements and compute how many times even elements must be dropped.
9269 /// This handles shuffles which take every Nth element where N is a power of
9270 /// two. Example shuffle masks:
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9273 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9274 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9275 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9276 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9277 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9279 /// Any of these lanes can of course be undef.
9281 /// This routine only supports N <= 3.
9282 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9285 /// \returns N above, or the number of times even elements must be dropped if
9286 /// there is such a number. Otherwise returns zero.
9287 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9288 // Figure out whether we're looping over two inputs or just one.
9289 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9291 // The modulus for the shuffle vector entries is based on whether this is
9292 // a single input or not.
9293 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9294 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9295 "We should only be called with masks with a power-of-2 size!");
9297 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9299 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9300 // and 2^3 simultaneously. This is because we may have ambiguity with
9301 // partially undef inputs.
9302 bool ViableForN[3] = {true, true, true};
9304 for (int i = 0, e = Mask.size(); i < e; ++i) {
9305 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9310 bool IsAnyViable = false;
9311 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9312 if (ViableForN[j]) {
9315 // The shuffle mask must be equal to (i * 2^N) % M.
9316 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9319 ViableForN[j] = false;
9321 // Early exit if we exhaust the possible powers of two.
9326 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9330 // Return 0 as there is no viable power of two.
9334 /// \brief Generic lowering of v16i8 shuffles.
9336 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9337 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9338 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9339 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9341 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9342 const X86Subtarget *Subtarget,
9343 SelectionDAG &DAG) {
9345 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9346 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9349 ArrayRef<int> OrigMask = SVOp->getMask();
9350 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9352 // Try to use byte shift instructions.
9353 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9354 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9357 // Try to use byte rotation instructions.
9358 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9359 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9362 // Try to use a zext lowering.
9363 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9364 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9367 int MaskStorage[16] = {
9368 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9369 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9370 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9371 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9372 MutableArrayRef<int> Mask(MaskStorage);
9373 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9374 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9377 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9379 // For single-input shuffles, there are some nicer lowering tricks we can use.
9380 if (NumV2Elements == 0) {
9381 // Check for being able to broadcast a single element.
9382 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9383 Mask, Subtarget, DAG))
9386 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9387 // Notably, this handles splat and partial-splat shuffles more efficiently.
9388 // However, it only makes sense if the pre-duplication shuffle simplifies
9389 // things significantly. Currently, this means we need to be able to
9390 // express the pre-duplication shuffle as an i16 shuffle.
9392 // FIXME: We should check for other patterns which can be widened into an
9393 // i16 shuffle as well.
9394 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9395 for (int i = 0; i < 16; i += 2)
9396 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9401 auto tryToWidenViaDuplication = [&]() -> SDValue {
9402 if (!canWidenViaDuplication(Mask))
9404 SmallVector<int, 4> LoInputs;
9405 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9406 [](int M) { return M >= 0 && M < 8; });
9407 std::sort(LoInputs.begin(), LoInputs.end());
9408 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9410 SmallVector<int, 4> HiInputs;
9411 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9412 [](int M) { return M >= 8; });
9413 std::sort(HiInputs.begin(), HiInputs.end());
9414 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9417 bool TargetLo = LoInputs.size() >= HiInputs.size();
9418 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9419 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9421 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 SmallDenseMap<int, int, 8> LaneMap;
9423 for (int I : InPlaceInputs) {
9424 PreDupI16Shuffle[I/2] = I/2;
9427 int j = TargetLo ? 0 : 4, je = j + 4;
9428 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9429 // Check if j is already a shuffle of this input. This happens when
9430 // there are two adjacent bytes after we move the low one.
9431 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9432 // If we haven't yet mapped the input, search for a slot into which
9434 while (j < je && PreDupI16Shuffle[j] != -1)
9438 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9441 // Map this input with the i16 shuffle.
9442 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9445 // Update the lane map based on the mapping we ended up with.
9446 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9449 ISD::BITCAST, DL, MVT::v16i8,
9450 DAG.getVectorShuffle(MVT::v8i16, DL,
9451 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9452 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9454 // Unpack the bytes to form the i16s that will be shuffled into place.
9455 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9456 MVT::v16i8, V1, V1);
9458 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9459 for (int i = 0; i < 16; ++i)
9460 if (Mask[i] != -1) {
9461 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9462 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9463 if (PostDupI16Shuffle[i / 2] == -1)
9464 PostDupI16Shuffle[i / 2] = MappedMask;
9466 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9467 "Conflicting entrties in the original shuffle!");
9470 ISD::BITCAST, DL, MVT::v16i8,
9471 DAG.getVectorShuffle(MVT::v8i16, DL,
9472 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9473 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9475 if (SDValue V = tryToWidenViaDuplication())
9479 // Check whether an interleaving lowering is likely to be more efficient.
9480 // This isn't perfect but it is a strong heuristic that tends to work well on
9481 // the kinds of shuffles that show up in practice.
9483 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9484 if (shouldLowerAsInterleaving(Mask)) {
9485 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9486 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9488 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9489 return (M >= 8 && M < 16) || M >= 24;
9491 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9492 -1, -1, -1, -1, -1, -1, -1, -1};
9493 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9494 -1, -1, -1, -1, -1, -1, -1, -1};
9495 bool UnpackLo = NumLoHalf >= NumHiHalf;
9496 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9497 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9498 for (int i = 0; i < 8; ++i) {
9499 TargetEMask[i] = Mask[2 * i];
9500 TargetOMask[i] = Mask[2 * i + 1];
9503 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9504 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9506 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9507 MVT::v16i8, Evens, Odds);
9510 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9511 // with PSHUFB. It is important to do this before we attempt to generate any
9512 // blends but after all of the single-input lowerings. If the single input
9513 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9514 // want to preserve that and we can DAG combine any longer sequences into
9515 // a PSHUFB in the end. But once we start blending from multiple inputs,
9516 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9517 // and there are *very* few patterns that would actually be faster than the
9518 // PSHUFB approach because of its ability to zero lanes.
9520 // FIXME: The only exceptions to the above are blends which are exact
9521 // interleavings with direct instructions supporting them. We currently don't
9522 // handle those well here.
9523 if (Subtarget->hasSSSE3()) {
9526 for (int i = 0; i < 16; ++i)
9527 if (Mask[i] == -1) {
9528 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9530 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9532 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9534 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9535 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9536 if (isSingleInputShuffleMask(Mask))
9537 return V1; // Single inputs are easy.
9539 // Otherwise, blend the two.
9540 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9541 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9542 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9545 // There are special ways we can lower some single-element blends.
9546 if (NumV2Elements == 1)
9547 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9548 Mask, Subtarget, DAG))
9551 // Check whether a compaction lowering can be done. This handles shuffles
9552 // which take every Nth element for some even N. See the helper function for
9555 // We special case these as they can be particularly efficiently handled with
9556 // the PACKUSB instruction on x86 and they show up in common patterns of
9557 // rearranging bytes to truncate wide elements.
9558 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9559 // NumEvenDrops is the power of two stride of the elements. Another way of
9560 // thinking about it is that we need to drop the even elements this many
9561 // times to get the original input.
9562 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9564 // First we need to zero all the dropped bytes.
9565 assert(NumEvenDrops <= 3 &&
9566 "No support for dropping even elements more than 3 times.");
9567 // We use the mask type to pick which bytes are preserved based on how many
9568 // elements are dropped.
9569 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9570 SDValue ByteClearMask =
9571 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9572 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9573 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9575 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9577 // Now pack things back together.
9578 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9579 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9580 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9581 for (int i = 1; i < NumEvenDrops; ++i) {
9582 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9583 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9589 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9592 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9594 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9595 MutableArrayRef<int> V1HalfBlendMask,
9596 MutableArrayRef<int> V2HalfBlendMask) {
9597 for (int i = 0; i < 8; ++i)
9598 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9599 V1HalfBlendMask[i] = HalfMask[i];
9601 } else if (HalfMask[i] >= 16) {
9602 V2HalfBlendMask[i] = HalfMask[i] - 16;
9603 HalfMask[i] = i + 8;
9606 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9607 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9609 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9611 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9612 MutableArrayRef<int> HiBlendMask) {
9614 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9615 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9617 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9618 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9619 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9620 [](int M) { return M >= 0 && M % 2 == 1; })) {
9621 // Use a mask to drop the high bytes.
9622 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9623 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9624 DAG.getConstant(0x00FF, MVT::v8i16));
9626 // This will be a single vector shuffle instead of a blend so nuke V2.
9627 V2 = DAG.getUNDEF(MVT::v8i16);
9629 // Squash the masks to point directly into V1.
9630 for (int &M : LoBlendMask)
9633 for (int &M : HiBlendMask)
9637 // Otherwise just unpack the low half of V into V1 and the high half into
9638 // V2 so that we can blend them as i16s.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9640 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9641 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9642 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9645 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9646 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9647 return std::make_pair(BlendedLo, BlendedHi);
9649 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9650 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9651 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9653 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9654 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9656 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9659 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9661 /// This routine breaks down the specific type of 128-bit shuffle and
9662 /// dispatches to the lowering routines accordingly.
9663 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9664 MVT VT, const X86Subtarget *Subtarget,
9665 SelectionDAG &DAG) {
9666 switch (VT.SimpleTy) {
9668 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9670 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9672 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9674 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9676 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9678 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9681 llvm_unreachable("Unimplemented!");
9685 /// \brief Helper function to test whether a shuffle mask could be
9686 /// simplified by widening the elements being shuffled.
9688 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9689 /// leaves it in an unspecified state.
9691 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9692 /// shuffle masks. The latter have the special property of a '-2' representing
9693 /// a zero-ed lane of a vector.
9694 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9695 SmallVectorImpl<int> &WidenedMask) {
9696 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9697 // If both elements are undef, its trivial.
9698 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9699 WidenedMask.push_back(SM_SentinelUndef);
9703 // Check for an undef mask and a mask value properly aligned to fit with
9704 // a pair of values. If we find such a case, use the non-undef mask's value.
9705 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9706 WidenedMask.push_back(Mask[i + 1] / 2);
9709 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9710 WidenedMask.push_back(Mask[i] / 2);
9714 // When zeroing, we need to spread the zeroing across both lanes to widen.
9715 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9716 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9717 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9718 WidenedMask.push_back(SM_SentinelZero);
9724 // Finally check if the two mask values are adjacent and aligned with
9726 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9727 WidenedMask.push_back(Mask[i] / 2);
9731 // Otherwise we can't safely widen the elements used in this shuffle.
9734 assert(WidenedMask.size() == Mask.size() / 2 &&
9735 "Incorrect size of mask after widening the elements!");
9740 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9742 /// This routine just extracts two subvectors, shuffles them independently, and
9743 /// then concatenates them back together. This should work effectively with all
9744 /// AVX vector shuffle types.
9745 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9746 SDValue V2, ArrayRef<int> Mask,
9747 SelectionDAG &DAG) {
9748 assert(VT.getSizeInBits() >= 256 &&
9749 "Only for 256-bit or wider vector shuffles!");
9750 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9751 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9753 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9754 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9756 int NumElements = VT.getVectorNumElements();
9757 int SplitNumElements = NumElements / 2;
9758 MVT ScalarVT = VT.getScalarType();
9759 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9761 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9762 DAG.getIntPtrConstant(0));
9763 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9764 DAG.getIntPtrConstant(SplitNumElements));
9765 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9766 DAG.getIntPtrConstant(0));
9767 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9768 DAG.getIntPtrConstant(SplitNumElements));
9770 // Now create two 4-way blends of these half-width vectors.
9771 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9772 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9773 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9774 for (int i = 0; i < SplitNumElements; ++i) {
9775 int M = HalfMask[i];
9776 if (M >= NumElements) {
9777 if (M >= NumElements + SplitNumElements)
9781 V2BlendMask.push_back(M - NumElements);
9782 V1BlendMask.push_back(-1);
9783 BlendMask.push_back(SplitNumElements + i);
9784 } else if (M >= 0) {
9785 if (M >= SplitNumElements)
9789 V2BlendMask.push_back(-1);
9790 V1BlendMask.push_back(M);
9791 BlendMask.push_back(i);
9793 V2BlendMask.push_back(-1);
9794 V1BlendMask.push_back(-1);
9795 BlendMask.push_back(-1);
9799 // Because the lowering happens after all combining takes place, we need to
9800 // manually combine these blend masks as much as possible so that we create
9801 // a minimal number of high-level vector shuffle nodes.
9803 // First try just blending the halves of V1 or V2.
9804 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9805 return DAG.getUNDEF(SplitVT);
9806 if (!UseLoV2 && !UseHiV2)
9807 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9808 if (!UseLoV1 && !UseHiV1)
9809 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9811 SDValue V1Blend, V2Blend;
9812 if (UseLoV1 && UseHiV1) {
9814 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9816 // We only use half of V1 so map the usage down into the final blend mask.
9817 V1Blend = UseLoV1 ? LoV1 : HiV1;
9818 for (int i = 0; i < SplitNumElements; ++i)
9819 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9820 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9822 if (UseLoV2 && UseHiV2) {
9824 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9826 // We only use half of V2 so map the usage down into the final blend mask.
9827 V2Blend = UseLoV2 ? LoV2 : HiV2;
9828 for (int i = 0; i < SplitNumElements; ++i)
9829 if (BlendMask[i] >= SplitNumElements)
9830 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9832 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9834 SDValue Lo = HalfBlend(LoMask);
9835 SDValue Hi = HalfBlend(HiMask);
9836 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9839 /// \brief Either split a vector in halves or decompose the shuffles and the
9842 /// This is provided as a good fallback for many lowerings of non-single-input
9843 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9844 /// between splitting the shuffle into 128-bit components and stitching those
9845 /// back together vs. extracting the single-input shuffles and blending those
9847 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9848 SDValue V2, ArrayRef<int> Mask,
9849 SelectionDAG &DAG) {
9850 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9851 "lower single-input shuffles as it "
9852 "could then recurse on itself.");
9853 int Size = Mask.size();
9855 // If this can be modeled as a broadcast of two elements followed by a blend,
9856 // prefer that lowering. This is especially important because broadcasts can
9857 // often fold with memory operands.
9858 auto DoBothBroadcast = [&] {
9859 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9862 if (V2BroadcastIdx == -1)
9863 V2BroadcastIdx = M - Size;
9864 else if (M - Size != V2BroadcastIdx)
9866 } else if (M >= 0) {
9867 if (V1BroadcastIdx == -1)
9869 else if (M != V1BroadcastIdx)
9874 if (DoBothBroadcast())
9875 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9878 // If the inputs all stem from a single 128-bit lane of each input, then we
9879 // split them rather than blending because the split will decompose to
9880 // unusually few instructions.
9881 int LaneCount = VT.getSizeInBits() / 128;
9882 int LaneSize = Size / LaneCount;
9883 SmallBitVector LaneInputs[2];
9884 LaneInputs[0].resize(LaneCount, false);
9885 LaneInputs[1].resize(LaneCount, false);
9886 for (int i = 0; i < Size; ++i)
9888 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9889 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9890 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9892 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9893 // that the decomposed single-input shuffles don't end up here.
9894 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9897 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9898 /// a permutation and blend of those lanes.
9900 /// This essentially blends the out-of-lane inputs to each lane into the lane
9901 /// from a permuted copy of the vector. This lowering strategy results in four
9902 /// instructions in the worst case for a single-input cross lane shuffle which
9903 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9904 /// of. Special cases for each particular shuffle pattern should be handled
9905 /// prior to trying this lowering.
9906 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9907 SDValue V1, SDValue V2,
9909 SelectionDAG &DAG) {
9910 // FIXME: This should probably be generalized for 512-bit vectors as well.
9911 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9912 int LaneSize = Mask.size() / 2;
9914 // If there are only inputs from one 128-bit lane, splitting will in fact be
9915 // less expensive. The flags track wether the given lane contains an element
9916 // that crosses to another lane.
9917 bool LaneCrossing[2] = {false, false};
9918 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9919 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9920 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9921 if (!LaneCrossing[0] || !LaneCrossing[1])
9922 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9924 if (isSingleInputShuffleMask(Mask)) {
9925 SmallVector<int, 32> FlippedBlendMask;
9926 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9927 FlippedBlendMask.push_back(
9928 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9930 : Mask[i] % LaneSize +
9931 (i / LaneSize) * LaneSize + Size));
9933 // Flip the vector, and blend the results which should now be in-lane. The
9934 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9935 // 5 for the high source. The value 3 selects the high half of source 2 and
9936 // the value 2 selects the low half of source 2. We only use source 2 to
9937 // allow folding it into a memory operand.
9938 unsigned PERMMask = 3 | 2 << 4;
9939 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9940 V1, DAG.getConstant(PERMMask, MVT::i8));
9941 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9944 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9945 // will be handled by the above logic and a blend of the results, much like
9946 // other patterns in AVX.
9947 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9950 /// \brief Handle lowering 2-lane 128-bit shuffles.
9951 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9952 SDValue V2, ArrayRef<int> Mask,
9953 const X86Subtarget *Subtarget,
9954 SelectionDAG &DAG) {
9955 // Blends are faster and handle all the non-lane-crossing cases.
9956 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9960 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9961 VT.getVectorNumElements() / 2);
9962 // Check for patterns which can be matched with a single insert of a 128-bit
9964 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9965 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9966 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9967 DAG.getIntPtrConstant(0));
9968 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9969 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9970 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9972 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9973 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9974 DAG.getIntPtrConstant(0));
9975 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9976 DAG.getIntPtrConstant(2));
9977 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9980 // Otherwise form a 128-bit permutation.
9981 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9982 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9983 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9984 DAG.getConstant(PermMask, MVT::i8));
9987 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9988 /// shuffling each lane.
9990 /// This will only succeed when the result of fixing the 128-bit lanes results
9991 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9992 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9993 /// the lane crosses early and then use simpler shuffles within each lane.
9995 /// FIXME: It might be worthwhile at some point to support this without
9996 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9997 /// in x86 only floating point has interesting non-repeating shuffles, and even
9998 /// those are still *marginally* more expensive.
9999 static SDValue lowerVectorShuffleByMerging128BitLanes(
10000 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10001 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10002 assert(is128BitLaneCrossingShuffleMask(VT, Mask) &&
10003 "This is only useful when there are cross-128-bit-lane shuffles.");
10005 int Size = Mask.size();
10006 int LaneSize = 128 / VT.getScalarSizeInBits();
10007 int NumLanes = Size / LaneSize;
10008 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10010 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10011 // check whether the in-128-bit lane shuffles share a repeating pattern.
10012 SmallVector<int, 4> Lanes;
10013 Lanes.resize(NumLanes, -1);
10014 SmallVector<int, 4> InLaneMask;
10015 InLaneMask.resize(LaneSize, -1);
10016 for (int i = 0; i < Size; ++i) {
10020 int j = i / LaneSize;
10022 if (Lanes[j] < 0) {
10023 // First entry we've seen for this lane.
10024 Lanes[j] = Mask[i] / LaneSize;
10025 } else if (Lanes[j] != Mask[i] / LaneSize) {
10026 // This doesn't match the lane selected previously!
10030 // Check that within each lane we have a consistent shuffle mask.
10031 int k = i % LaneSize;
10032 if (InLaneMask[k] < 0) {
10033 InLaneMask[k] = Mask[i] % LaneSize;
10034 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10035 // This doesn't fit a repeating in-lane mask.
10040 // First shuffle the lanes into place.
10041 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10042 VT.getSizeInBits() / 64);
10043 SmallVector<int, 8> LaneMask;
10044 LaneMask.resize(NumLanes * 2, -1);
10045 for (int i = 0; i < NumLanes; ++i)
10046 if (Lanes[i] >= 0) {
10047 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10048 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10051 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10052 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10053 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10055 // Cast it back to the type we actually want.
10056 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10058 // Now do a simple shuffle that isn't lane crossing.
10059 SmallVector<int, 8> NewMask;
10060 NewMask.resize(Size, -1);
10061 for (int i = 0; i < Size; ++i)
10063 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10064 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10065 "Must not introduce lane crosses at this point!");
10067 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10070 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10073 /// This returns true if the elements from a particular input are already in the
10074 /// slot required by the given mask and require no permutation.
10075 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10076 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10077 int Size = Mask.size();
10078 for (int i = 0; i < Size; ++i)
10079 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10085 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10087 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10088 /// isn't available.
10089 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10090 const X86Subtarget *Subtarget,
10091 SelectionDAG &DAG) {
10093 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10094 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10095 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10096 ArrayRef<int> Mask = SVOp->getMask();
10097 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10099 SmallVector<int, 4> WidenedMask;
10100 if (canWidenShuffleElements(Mask, WidenedMask))
10101 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10104 if (isSingleInputShuffleMask(Mask)) {
10105 // Check for being able to broadcast a single element.
10106 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10107 Mask, Subtarget, DAG))
10110 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10111 // Non-half-crossing single input shuffles can be lowerid with an
10112 // interleaved permutation.
10113 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10114 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10115 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10116 DAG.getConstant(VPERMILPMask, MVT::i8));
10119 // With AVX2 we have direct support for this permutation.
10120 if (Subtarget->hasAVX2())
10121 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10122 getV4X86ShuffleImm8ForMask(Mask, DAG));
10124 // Otherwise, fall back.
10125 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10129 // X86 has dedicated unpack instructions that can handle specific blend
10130 // operations: UNPCKH and UNPCKL.
10131 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10132 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10133 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10134 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10136 // If we have a single input to the zero element, insert that into V1 if we
10137 // can do so cheaply.
10138 int NumV2Elements =
10139 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10140 if (NumV2Elements == 1 && Mask[0] >= 4)
10141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10142 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10145 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10149 // Check if the blend happens to exactly fit that of SHUFPD.
10150 if ((Mask[0] == -1 || Mask[0] < 2) &&
10151 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10152 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10153 (Mask[3] == -1 || Mask[3] >= 6)) {
10154 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10155 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10156 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10157 DAG.getConstant(SHUFPDMask, MVT::i8));
10159 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10160 (Mask[1] == -1 || Mask[1] < 2) &&
10161 (Mask[2] == -1 || Mask[2] >= 6) &&
10162 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10163 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10164 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10165 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10166 DAG.getConstant(SHUFPDMask, MVT::i8));
10169 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10170 // shuffle. However, if we have AVX2 and either inputs are already in place,
10171 // we will be able to shuffle even across lanes the other input in a single
10172 // instruction so skip this pattern.
10173 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask) &&
10174 !(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10175 isShuffleMaskInputInPlace(1, Mask))))
10176 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10177 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10180 // If we have AVX2 then we always want to lower with a blend because an v4 we
10181 // can fully permute the elements.
10182 if (Subtarget->hasAVX2())
10183 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10186 // Otherwise fall back on generic lowering.
10187 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10190 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10192 /// This routine is only called when we have AVX2 and thus a reasonable
10193 /// instruction set for v4i64 shuffling..
10194 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10195 const X86Subtarget *Subtarget,
10196 SelectionDAG &DAG) {
10198 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10199 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10200 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10201 ArrayRef<int> Mask = SVOp->getMask();
10202 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10203 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10205 SmallVector<int, 4> WidenedMask;
10206 if (canWidenShuffleElements(Mask, WidenedMask))
10207 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10210 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10214 // Check for being able to broadcast a single element.
10215 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10216 Mask, Subtarget, DAG))
10219 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10220 // use lower latency instructions that will operate on both 128-bit lanes.
10221 SmallVector<int, 2> RepeatedMask;
10222 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10223 if (isSingleInputShuffleMask(Mask)) {
10224 int PSHUFDMask[] = {-1, -1, -1, -1};
10225 for (int i = 0; i < 2; ++i)
10226 if (RepeatedMask[i] >= 0) {
10227 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10228 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10230 return DAG.getNode(
10231 ISD::BITCAST, DL, MVT::v4i64,
10232 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10233 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10234 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10237 // Use dedicated unpack instructions for masks that match their pattern.
10238 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10239 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10240 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10241 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10244 // AVX2 provides a direct instruction for permuting a single input across
10246 if (isSingleInputShuffleMask(Mask))
10247 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10248 getV4X86ShuffleImm8ForMask(Mask, DAG));
10250 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10251 // shuffle. However, if we have AVX2 and either inputs are already in place,
10252 // we will be able to shuffle even across lanes the other input in a single
10253 // instruction so skip this pattern.
10254 if (is128BitLaneCrossingShuffleMask(MVT::v4i64, Mask) &&
10255 !(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10256 isShuffleMaskInputInPlace(1, Mask))))
10257 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10258 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10261 // Otherwise fall back on generic blend lowering.
10262 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10266 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10268 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10269 /// isn't available.
10270 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10271 const X86Subtarget *Subtarget,
10272 SelectionDAG &DAG) {
10274 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10275 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10276 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10277 ArrayRef<int> Mask = SVOp->getMask();
10278 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10280 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10284 // Check for being able to broadcast a single element.
10285 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10286 Mask, Subtarget, DAG))
10289 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10290 // options to efficiently lower the shuffle.
10291 SmallVector<int, 4> RepeatedMask;
10292 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10293 assert(RepeatedMask.size() == 4 &&
10294 "Repeated masks must be half the mask width!");
10295 if (isSingleInputShuffleMask(Mask))
10296 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10297 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10299 // Use dedicated unpack instructions for masks that match their pattern.
10300 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10301 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10302 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10303 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10305 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10306 // have already handled any direct blends. We also need to squash the
10307 // repeated mask into a simulated v4f32 mask.
10308 for (int i = 0; i < 4; ++i)
10309 if (RepeatedMask[i] >= 8)
10310 RepeatedMask[i] -= 4;
10311 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10314 // If we have a single input shuffle with different shuffle patterns in the
10315 // two 128-bit lanes use the variable mask to VPERMILPS.
10316 if (isSingleInputShuffleMask(Mask)) {
10317 SDValue VPermMask[8];
10318 for (int i = 0; i < 8; ++i)
10319 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10320 : DAG.getConstant(Mask[i], MVT::i32);
10321 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10322 return DAG.getNode(
10323 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10324 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10326 if (Subtarget->hasAVX2())
10327 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10328 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10329 DAG.getNode(ISD::BUILD_VECTOR, DL,
10330 MVT::v8i32, VPermMask)),
10333 // Otherwise, fall back.
10334 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10338 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10340 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10341 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10342 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10345 // If we have AVX2 then we always want to lower with a blend because at v8 we
10346 // can fully permute the elements.
10347 if (Subtarget->hasAVX2())
10348 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10351 // Otherwise fall back on generic lowering.
10352 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10355 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10357 /// This routine is only called when we have AVX2 and thus a reasonable
10358 /// instruction set for v8i32 shuffling..
10359 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10360 const X86Subtarget *Subtarget,
10361 SelectionDAG &DAG) {
10363 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10364 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10366 ArrayRef<int> Mask = SVOp->getMask();
10367 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10368 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10370 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10374 // Check for being able to broadcast a single element.
10375 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10376 Mask, Subtarget, DAG))
10379 // If the shuffle mask is repeated in each 128-bit lane we can use more
10380 // efficient instructions that mirror the shuffles across the two 128-bit
10382 SmallVector<int, 4> RepeatedMask;
10383 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10384 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10385 if (isSingleInputShuffleMask(Mask))
10386 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10387 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10389 // Use dedicated unpack instructions for masks that match their pattern.
10390 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10391 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10392 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10393 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10396 // If the shuffle patterns aren't repeated but it is a single input, directly
10397 // generate a cross-lane VPERMD instruction.
10398 if (isSingleInputShuffleMask(Mask)) {
10399 SDValue VPermMask[8];
10400 for (int i = 0; i < 8; ++i)
10401 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10402 : DAG.getConstant(Mask[i], MVT::i32);
10403 return DAG.getNode(
10404 X86ISD::VPERMV, DL, MVT::v8i32,
10405 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10408 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10410 if (is128BitLaneCrossingShuffleMask(MVT::v8i32, Mask))
10411 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10412 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10415 // Otherwise fall back on generic blend lowering.
10416 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10420 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10422 /// This routine is only called when we have AVX2 and thus a reasonable
10423 /// instruction set for v16i16 shuffling..
10424 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10425 const X86Subtarget *Subtarget,
10426 SelectionDAG &DAG) {
10428 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10429 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10431 ArrayRef<int> Mask = SVOp->getMask();
10432 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10433 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10435 // Check for being able to broadcast a single element.
10436 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10437 Mask, Subtarget, DAG))
10440 // There are no generalized cross-lane shuffle operations available on i16
10442 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask)) {
10443 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10445 if (!isSingleInputShuffleMask(Mask))
10446 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10447 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10450 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10454 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10458 // Use dedicated unpack instructions for masks that match their pattern.
10459 if (isShuffleEquivalent(Mask,
10460 // First 128-bit lane:
10461 0, 16, 1, 17, 2, 18, 3, 19,
10462 // Second 128-bit lane:
10463 8, 24, 9, 25, 10, 26, 11, 27))
10464 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10465 if (isShuffleEquivalent(Mask,
10466 // First 128-bit lane:
10467 4, 20, 5, 21, 6, 22, 7, 23,
10468 // Second 128-bit lane:
10469 12, 28, 13, 29, 14, 30, 15, 31))
10470 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10472 if (isSingleInputShuffleMask(Mask)) {
10473 SDValue PSHUFBMask[32];
10474 for (int i = 0; i < 16; ++i) {
10475 if (Mask[i] == -1) {
10476 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10480 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10481 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10482 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10483 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10485 return DAG.getNode(
10486 ISD::BITCAST, DL, MVT::v16i16,
10488 X86ISD::PSHUFB, DL, MVT::v32i8,
10489 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10490 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10493 // Otherwise fall back on generic lowering.
10494 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10497 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10499 /// This routine is only called when we have AVX2 and thus a reasonable
10500 /// instruction set for v32i8 shuffling..
10501 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10502 const X86Subtarget *Subtarget,
10503 SelectionDAG &DAG) {
10505 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10506 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10508 ArrayRef<int> Mask = SVOp->getMask();
10509 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10510 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10512 // Check for being able to broadcast a single element.
10513 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10514 Mask, Subtarget, DAG))
10517 // There are no generalized cross-lane shuffle operations available on i8
10519 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask)) {
10520 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10522 if (!isSingleInputShuffleMask(Mask))
10523 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10524 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10527 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2, Mask,
10531 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10535 // Use dedicated unpack instructions for masks that match their pattern.
10536 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10538 if (isShuffleEquivalent(
10540 // First 128-bit lane:
10541 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10542 // Second 128-bit lane:
10543 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10544 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10545 if (isShuffleEquivalent(
10547 // First 128-bit lane:
10548 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10549 // Second 128-bit lane:
10550 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10551 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10553 if (isSingleInputShuffleMask(Mask)) {
10554 SDValue PSHUFBMask[32];
10555 for (int i = 0; i < 32; ++i)
10558 ? DAG.getUNDEF(MVT::i8)
10559 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10561 return DAG.getNode(
10562 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10563 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10566 // Otherwise fall back on generic lowering.
10567 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10570 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10572 /// This routine either breaks down the specific type of a 256-bit x86 vector
10573 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10574 /// together based on the available instructions.
10575 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10576 MVT VT, const X86Subtarget *Subtarget,
10577 SelectionDAG &DAG) {
10579 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10580 ArrayRef<int> Mask = SVOp->getMask();
10582 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10583 // check for those subtargets here and avoid much of the subtarget querying in
10584 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10585 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10586 // floating point types there eventually, just immediately cast everything to
10587 // a float and operate entirely in that domain.
10588 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10589 int ElementBits = VT.getScalarSizeInBits();
10590 if (ElementBits < 32)
10591 // No floating point type available, decompose into 128-bit vectors.
10592 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10594 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10595 VT.getVectorNumElements());
10596 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10597 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10598 return DAG.getNode(ISD::BITCAST, DL, VT,
10599 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10602 switch (VT.SimpleTy) {
10604 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10606 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10608 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10610 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10612 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10614 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10617 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10621 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10622 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10623 const X86Subtarget *Subtarget,
10624 SelectionDAG &DAG) {
10626 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10627 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10628 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10629 ArrayRef<int> Mask = SVOp->getMask();
10630 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10632 // FIXME: Implement direct support for this type!
10633 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10636 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10637 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10638 const X86Subtarget *Subtarget,
10639 SelectionDAG &DAG) {
10641 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10642 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10643 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10644 ArrayRef<int> Mask = SVOp->getMask();
10645 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10647 // FIXME: Implement direct support for this type!
10648 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10651 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10652 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10653 const X86Subtarget *Subtarget,
10654 SelectionDAG &DAG) {
10656 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10657 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10659 ArrayRef<int> Mask = SVOp->getMask();
10660 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10662 // FIXME: Implement direct support for this type!
10663 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10666 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10667 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10668 const X86Subtarget *Subtarget,
10669 SelectionDAG &DAG) {
10671 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10672 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10673 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10674 ArrayRef<int> Mask = SVOp->getMask();
10675 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10677 // FIXME: Implement direct support for this type!
10678 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10681 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10682 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10683 const X86Subtarget *Subtarget,
10684 SelectionDAG &DAG) {
10686 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10687 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10689 ArrayRef<int> Mask = SVOp->getMask();
10690 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10691 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10693 // FIXME: Implement direct support for this type!
10694 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10697 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10698 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10699 const X86Subtarget *Subtarget,
10700 SelectionDAG &DAG) {
10702 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10703 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10705 ArrayRef<int> Mask = SVOp->getMask();
10706 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10707 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10709 // FIXME: Implement direct support for this type!
10710 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10713 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10715 /// This routine either breaks down the specific type of a 512-bit x86 vector
10716 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10717 /// together based on the available instructions.
10718 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10719 MVT VT, const X86Subtarget *Subtarget,
10720 SelectionDAG &DAG) {
10722 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10723 ArrayRef<int> Mask = SVOp->getMask();
10724 assert(Subtarget->hasAVX512() &&
10725 "Cannot lower 512-bit vectors w/ basic ISA!");
10727 // Check for being able to broadcast a single element.
10728 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10729 Mask, Subtarget, DAG))
10732 // Dispatch to each element type for lowering. If we don't have supprot for
10733 // specific element type shuffles at 512 bits, immediately split them and
10734 // lower them. Each lowering routine of a given type is allowed to assume that
10735 // the requisite ISA extensions for that element type are available.
10736 switch (VT.SimpleTy) {
10738 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10740 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10742 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10744 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10746 if (Subtarget->hasBWI())
10747 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10750 if (Subtarget->hasBWI())
10751 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10758 // Otherwise fall back on splitting.
10759 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10762 /// \brief Top-level lowering for x86 vector shuffles.
10764 /// This handles decomposition, canonicalization, and lowering of all x86
10765 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10766 /// above in helper routines. The canonicalization attempts to widen shuffles
10767 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10768 /// s.t. only one of the two inputs needs to be tested, etc.
10769 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10770 SelectionDAG &DAG) {
10771 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10772 ArrayRef<int> Mask = SVOp->getMask();
10773 SDValue V1 = Op.getOperand(0);
10774 SDValue V2 = Op.getOperand(1);
10775 MVT VT = Op.getSimpleValueType();
10776 int NumElements = VT.getVectorNumElements();
10779 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10781 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10782 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10783 if (V1IsUndef && V2IsUndef)
10784 return DAG.getUNDEF(VT);
10786 // When we create a shuffle node we put the UNDEF node to second operand,
10787 // but in some cases the first operand may be transformed to UNDEF.
10788 // In this case we should just commute the node.
10790 return DAG.getCommutedVectorShuffle(*SVOp);
10792 // Check for non-undef masks pointing at an undef vector and make the masks
10793 // undef as well. This makes it easier to match the shuffle based solely on
10797 if (M >= NumElements) {
10798 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10799 for (int &M : NewMask)
10800 if (M >= NumElements)
10802 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10805 // Try to collapse shuffles into using a vector type with fewer elements but
10806 // wider element types. We cap this to not form integers or floating point
10807 // elements wider than 64 bits, but it might be interesting to form i128
10808 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10809 SmallVector<int, 16> WidenedMask;
10810 if (VT.getScalarSizeInBits() < 64 &&
10811 canWidenShuffleElements(Mask, WidenedMask)) {
10812 MVT NewEltVT = VT.isFloatingPoint()
10813 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10814 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10815 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10816 // Make sure that the new vector type is legal. For example, v2f64 isn't
10818 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10819 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10820 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10821 return DAG.getNode(ISD::BITCAST, dl, VT,
10822 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10826 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10827 for (int M : SVOp->getMask())
10829 ++NumUndefElements;
10830 else if (M < NumElements)
10835 // Commute the shuffle as needed such that more elements come from V1 than
10836 // V2. This allows us to match the shuffle pattern strictly on how many
10837 // elements come from V1 without handling the symmetric cases.
10838 if (NumV2Elements > NumV1Elements)
10839 return DAG.getCommutedVectorShuffle(*SVOp);
10841 // When the number of V1 and V2 elements are the same, try to minimize the
10842 // number of uses of V2 in the low half of the vector. When that is tied,
10843 // ensure that the sum of indices for V1 is equal to or lower than the sum
10845 if (NumV1Elements == NumV2Elements) {
10846 int LowV1Elements = 0, LowV2Elements = 0;
10847 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10848 if (M >= NumElements)
10852 if (LowV2Elements > LowV1Elements) {
10853 return DAG.getCommutedVectorShuffle(*SVOp);
10854 } else if (LowV2Elements == LowV1Elements) {
10855 int SumV1Indices = 0, SumV2Indices = 0;
10856 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10857 if (SVOp->getMask()[i] >= NumElements)
10859 else if (SVOp->getMask()[i] >= 0)
10861 if (SumV2Indices < SumV1Indices)
10862 return DAG.getCommutedVectorShuffle(*SVOp);
10866 // For each vector width, delegate to a specialized lowering routine.
10867 if (VT.getSizeInBits() == 128)
10868 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10870 if (VT.getSizeInBits() == 256)
10871 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10873 // Force AVX-512 vectors to be scalarized for now.
10874 // FIXME: Implement AVX-512 support!
10875 if (VT.getSizeInBits() == 512)
10876 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10878 llvm_unreachable("Unimplemented!");
10882 //===----------------------------------------------------------------------===//
10883 // Legacy vector shuffle lowering
10885 // This code is the legacy code handling vector shuffles until the above
10886 // replaces its functionality and performance.
10887 //===----------------------------------------------------------------------===//
10889 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10890 bool hasInt256, unsigned *MaskOut = nullptr) {
10891 MVT EltVT = VT.getVectorElementType();
10893 // There is no blend with immediate in AVX-512.
10894 if (VT.is512BitVector())
10897 if (!hasSSE41 || EltVT == MVT::i8)
10899 if (!hasInt256 && VT == MVT::v16i16)
10902 unsigned MaskValue = 0;
10903 unsigned NumElems = VT.getVectorNumElements();
10904 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10905 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10906 unsigned NumElemsInLane = NumElems / NumLanes;
10908 // Blend for v16i16 should be symetric for the both lanes.
10909 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10911 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10912 int EltIdx = MaskVals[i];
10914 if ((EltIdx < 0 || EltIdx == (int)i) &&
10915 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10918 if (((unsigned)EltIdx == (i + NumElems)) &&
10919 (SndLaneEltIdx < 0 ||
10920 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10921 MaskValue |= (1 << i);
10927 *MaskOut = MaskValue;
10931 // Try to lower a shuffle node into a simple blend instruction.
10932 // This function assumes isBlendMask returns true for this
10933 // SuffleVectorSDNode
10934 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10935 unsigned MaskValue,
10936 const X86Subtarget *Subtarget,
10937 SelectionDAG &DAG) {
10938 MVT VT = SVOp->getSimpleValueType(0);
10939 MVT EltVT = VT.getVectorElementType();
10940 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10941 Subtarget->hasInt256() && "Trying to lower a "
10942 "VECTOR_SHUFFLE to a Blend but "
10943 "with the wrong mask"));
10944 SDValue V1 = SVOp->getOperand(0);
10945 SDValue V2 = SVOp->getOperand(1);
10947 unsigned NumElems = VT.getVectorNumElements();
10949 // Convert i32 vectors to floating point if it is not AVX2.
10950 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10952 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10953 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10955 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10956 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10959 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10960 DAG.getConstant(MaskValue, MVT::i32));
10961 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10964 /// In vector type \p VT, return true if the element at index \p InputIdx
10965 /// falls on a different 128-bit lane than \p OutputIdx.
10966 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10967 unsigned OutputIdx) {
10968 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10969 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10972 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10973 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10974 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10975 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10977 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10978 SelectionDAG &DAG) {
10979 MVT VT = V1.getSimpleValueType();
10980 assert(VT.is128BitVector() || VT.is256BitVector());
10982 MVT EltVT = VT.getVectorElementType();
10983 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10984 unsigned NumElts = VT.getVectorNumElements();
10986 SmallVector<SDValue, 32> PshufbMask;
10987 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10988 int InputIdx = MaskVals[OutputIdx];
10989 unsigned InputByteIdx;
10991 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10992 InputByteIdx = 0x80;
10994 // Cross lane is not allowed.
10995 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10997 InputByteIdx = InputIdx * EltSizeInBytes;
10998 // Index is an byte offset within the 128-bit lane.
10999 InputByteIdx &= 0xf;
11002 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11003 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11004 if (InputByteIdx != 0x80)
11009 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11011 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11012 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11013 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11016 // v8i16 shuffles - Prefer shuffles in the following order:
11017 // 1. [all] pshuflw, pshufhw, optional move
11018 // 2. [ssse3] 1 x pshufb
11019 // 3. [ssse3] 2 x pshufb + 1 x por
11020 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11022 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11023 SelectionDAG &DAG) {
11024 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11025 SDValue V1 = SVOp->getOperand(0);
11026 SDValue V2 = SVOp->getOperand(1);
11028 SmallVector<int, 8> MaskVals;
11030 // Determine if more than 1 of the words in each of the low and high quadwords
11031 // of the result come from the same quadword of one of the two inputs. Undef
11032 // mask values count as coming from any quadword, for better codegen.
11034 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11035 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11036 unsigned LoQuad[] = { 0, 0, 0, 0 };
11037 unsigned HiQuad[] = { 0, 0, 0, 0 };
11038 // Indices of quads used.
11039 std::bitset<4> InputQuads;
11040 for (unsigned i = 0; i < 8; ++i) {
11041 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11042 int EltIdx = SVOp->getMaskElt(i);
11043 MaskVals.push_back(EltIdx);
11051 ++Quad[EltIdx / 4];
11052 InputQuads.set(EltIdx / 4);
11055 int BestLoQuad = -1;
11056 unsigned MaxQuad = 1;
11057 for (unsigned i = 0; i < 4; ++i) {
11058 if (LoQuad[i] > MaxQuad) {
11060 MaxQuad = LoQuad[i];
11064 int BestHiQuad = -1;
11066 for (unsigned i = 0; i < 4; ++i) {
11067 if (HiQuad[i] > MaxQuad) {
11069 MaxQuad = HiQuad[i];
11073 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11074 // of the two input vectors, shuffle them into one input vector so only a
11075 // single pshufb instruction is necessary. If there are more than 2 input
11076 // quads, disable the next transformation since it does not help SSSE3.
11077 bool V1Used = InputQuads[0] || InputQuads[1];
11078 bool V2Used = InputQuads[2] || InputQuads[3];
11079 if (Subtarget->hasSSSE3()) {
11080 if (InputQuads.count() == 2 && V1Used && V2Used) {
11081 BestLoQuad = InputQuads[0] ? 0 : 1;
11082 BestHiQuad = InputQuads[2] ? 2 : 3;
11084 if (InputQuads.count() > 2) {
11090 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11091 // the shuffle mask. If a quad is scored as -1, that means that it contains
11092 // words from all 4 input quadwords.
11094 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11096 BestLoQuad < 0 ? 0 : BestLoQuad,
11097 BestHiQuad < 0 ? 1 : BestHiQuad
11099 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11100 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11101 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11102 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11104 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11105 // source words for the shuffle, to aid later transformations.
11106 bool AllWordsInNewV = true;
11107 bool InOrder[2] = { true, true };
11108 for (unsigned i = 0; i != 8; ++i) {
11109 int idx = MaskVals[i];
11111 InOrder[i/4] = false;
11112 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11114 AllWordsInNewV = false;
11118 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11119 if (AllWordsInNewV) {
11120 for (int i = 0; i != 8; ++i) {
11121 int idx = MaskVals[i];
11124 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11125 if ((idx != i) && idx < 4)
11127 if ((idx != i) && idx > 3)
11136 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11137 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11138 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11139 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11140 unsigned TargetMask = 0;
11141 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11142 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11143 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11144 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11145 getShufflePSHUFLWImmediate(SVOp);
11146 V1 = NewV.getOperand(0);
11147 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11151 // Promote splats to a larger type which usually leads to more efficient code.
11152 // FIXME: Is this true if pshufb is available?
11153 if (SVOp->isSplat())
11154 return PromoteSplat(SVOp, DAG);
11156 // If we have SSSE3, and all words of the result are from 1 input vector,
11157 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11158 // is present, fall back to case 4.
11159 if (Subtarget->hasSSSE3()) {
11160 SmallVector<SDValue,16> pshufbMask;
11162 // If we have elements from both input vectors, set the high bit of the
11163 // shuffle mask element to zero out elements that come from V2 in the V1
11164 // mask, and elements that come from V1 in the V2 mask, so that the two
11165 // results can be OR'd together.
11166 bool TwoInputs = V1Used && V2Used;
11167 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11169 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11171 // Calculate the shuffle mask for the second input, shuffle it, and
11172 // OR it with the first shuffled input.
11173 CommuteVectorShuffleMask(MaskVals, 8);
11174 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11175 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11176 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11179 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11180 // and update MaskVals with new element order.
11181 std::bitset<8> InOrder;
11182 if (BestLoQuad >= 0) {
11183 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11184 for (int i = 0; i != 4; ++i) {
11185 int idx = MaskVals[i];
11188 } else if ((idx / 4) == BestLoQuad) {
11189 MaskV[i] = idx & 3;
11193 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11196 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11198 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11199 NewV.getOperand(0),
11200 getShufflePSHUFLWImmediate(SVOp), DAG);
11204 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11205 // and update MaskVals with the new element order.
11206 if (BestHiQuad >= 0) {
11207 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11208 for (unsigned i = 4; i != 8; ++i) {
11209 int idx = MaskVals[i];
11212 } else if ((idx / 4) == BestHiQuad) {
11213 MaskV[i] = (idx & 3) + 4;
11217 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11220 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11222 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11223 NewV.getOperand(0),
11224 getShufflePSHUFHWImmediate(SVOp), DAG);
11228 // In case BestHi & BestLo were both -1, which means each quadword has a word
11229 // from each of the four input quadwords, calculate the InOrder bitvector now
11230 // before falling through to the insert/extract cleanup.
11231 if (BestLoQuad == -1 && BestHiQuad == -1) {
11233 for (int i = 0; i != 8; ++i)
11234 if (MaskVals[i] < 0 || MaskVals[i] == i)
11238 // The other elements are put in the right place using pextrw and pinsrw.
11239 for (unsigned i = 0; i != 8; ++i) {
11242 int EltIdx = MaskVals[i];
11245 SDValue ExtOp = (EltIdx < 8) ?
11246 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11247 DAG.getIntPtrConstant(EltIdx)) :
11248 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11249 DAG.getIntPtrConstant(EltIdx - 8));
11250 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11251 DAG.getIntPtrConstant(i));
11256 /// \brief v16i16 shuffles
11258 /// FIXME: We only support generation of a single pshufb currently. We can
11259 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11260 /// well (e.g 2 x pshufb + 1 x por).
11262 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11264 SDValue V1 = SVOp->getOperand(0);
11265 SDValue V2 = SVOp->getOperand(1);
11268 if (V2.getOpcode() != ISD::UNDEF)
11271 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11272 return getPSHUFB(MaskVals, V1, dl, DAG);
11275 // v16i8 shuffles - Prefer shuffles in the following order:
11276 // 1. [ssse3] 1 x pshufb
11277 // 2. [ssse3] 2 x pshufb + 1 x por
11278 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11279 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11280 const X86Subtarget* Subtarget,
11281 SelectionDAG &DAG) {
11282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11283 SDValue V1 = SVOp->getOperand(0);
11284 SDValue V2 = SVOp->getOperand(1);
11286 ArrayRef<int> MaskVals = SVOp->getMask();
11288 // Promote splats to a larger type which usually leads to more efficient code.
11289 // FIXME: Is this true if pshufb is available?
11290 if (SVOp->isSplat())
11291 return PromoteSplat(SVOp, DAG);
11293 // If we have SSSE3, case 1 is generated when all result bytes come from
11294 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11295 // present, fall back to case 3.
11297 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11298 if (Subtarget->hasSSSE3()) {
11299 SmallVector<SDValue,16> pshufbMask;
11301 // If all result elements are from one input vector, then only translate
11302 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11304 // Otherwise, we have elements from both input vectors, and must zero out
11305 // elements that come from V2 in the first mask, and V1 in the second mask
11306 // so that we can OR them together.
11307 for (unsigned i = 0; i != 16; ++i) {
11308 int EltIdx = MaskVals[i];
11309 if (EltIdx < 0 || EltIdx >= 16)
11311 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11313 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11314 DAG.getNode(ISD::BUILD_VECTOR, dl,
11315 MVT::v16i8, pshufbMask));
11317 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11318 // the 2nd operand if it's undefined or zero.
11319 if (V2.getOpcode() == ISD::UNDEF ||
11320 ISD::isBuildVectorAllZeros(V2.getNode()))
11323 // Calculate the shuffle mask for the second input, shuffle it, and
11324 // OR it with the first shuffled input.
11325 pshufbMask.clear();
11326 for (unsigned i = 0; i != 16; ++i) {
11327 int EltIdx = MaskVals[i];
11328 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11329 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11331 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11332 DAG.getNode(ISD::BUILD_VECTOR, dl,
11333 MVT::v16i8, pshufbMask));
11334 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11337 // No SSSE3 - Calculate in place words and then fix all out of place words
11338 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11339 // the 16 different words that comprise the two doublequadword input vectors.
11340 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11341 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11343 for (int i = 0; i != 8; ++i) {
11344 int Elt0 = MaskVals[i*2];
11345 int Elt1 = MaskVals[i*2+1];
11347 // This word of the result is all undef, skip it.
11348 if (Elt0 < 0 && Elt1 < 0)
11351 // This word of the result is already in the correct place, skip it.
11352 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11355 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11356 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11359 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11360 // using a single extract together, load it and store it.
11361 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11362 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11363 DAG.getIntPtrConstant(Elt1 / 2));
11364 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11365 DAG.getIntPtrConstant(i));
11369 // If Elt1 is defined, extract it from the appropriate source. If the
11370 // source byte is not also odd, shift the extracted word left 8 bits
11371 // otherwise clear the bottom 8 bits if we need to do an or.
11373 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11374 DAG.getIntPtrConstant(Elt1 / 2));
11375 if ((Elt1 & 1) == 0)
11376 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11378 TLI.getShiftAmountTy(InsElt.getValueType())));
11379 else if (Elt0 >= 0)
11380 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11381 DAG.getConstant(0xFF00, MVT::i16));
11383 // If Elt0 is defined, extract it from the appropriate source. If the
11384 // source byte is not also even, shift the extracted word right 8 bits. If
11385 // Elt1 was also defined, OR the extracted values together before
11386 // inserting them in the result.
11388 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11389 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11390 if ((Elt0 & 1) != 0)
11391 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11393 TLI.getShiftAmountTy(InsElt0.getValueType())));
11394 else if (Elt1 >= 0)
11395 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11396 DAG.getConstant(0x00FF, MVT::i16));
11397 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11400 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11401 DAG.getIntPtrConstant(i));
11403 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11406 // v32i8 shuffles - Translate to VPSHUFB if possible.
11408 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11409 const X86Subtarget *Subtarget,
11410 SelectionDAG &DAG) {
11411 MVT VT = SVOp->getSimpleValueType(0);
11412 SDValue V1 = SVOp->getOperand(0);
11413 SDValue V2 = SVOp->getOperand(1);
11415 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11417 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11418 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11419 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11421 // VPSHUFB may be generated if
11422 // (1) one of input vector is undefined or zeroinitializer.
11423 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11424 // And (2) the mask indexes don't cross the 128-bit lane.
11425 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11426 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11429 if (V1IsAllZero && !V2IsAllZero) {
11430 CommuteVectorShuffleMask(MaskVals, 32);
11433 return getPSHUFB(MaskVals, V1, dl, DAG);
11436 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11437 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11438 /// done when every pair / quad of shuffle mask elements point to elements in
11439 /// the right sequence. e.g.
11440 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11442 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11443 SelectionDAG &DAG) {
11444 MVT VT = SVOp->getSimpleValueType(0);
11446 unsigned NumElems = VT.getVectorNumElements();
11449 switch (VT.SimpleTy) {
11450 default: llvm_unreachable("Unexpected!");
11453 return SDValue(SVOp, 0);
11454 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11455 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11456 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11457 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11458 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11459 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11462 SmallVector<int, 8> MaskVec;
11463 for (unsigned i = 0; i != NumElems; i += Scale) {
11465 for (unsigned j = 0; j != Scale; ++j) {
11466 int EltIdx = SVOp->getMaskElt(i+j);
11470 StartIdx = (EltIdx / Scale);
11471 if (EltIdx != (int)(StartIdx*Scale + j))
11474 MaskVec.push_back(StartIdx);
11477 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11478 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11479 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11482 /// getVZextMovL - Return a zero-extending vector move low node.
11484 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11485 SDValue SrcOp, SelectionDAG &DAG,
11486 const X86Subtarget *Subtarget, SDLoc dl) {
11487 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11488 LoadSDNode *LD = nullptr;
11489 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11490 LD = dyn_cast<LoadSDNode>(SrcOp);
11492 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11494 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11495 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11496 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11497 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11498 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11500 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11501 return DAG.getNode(ISD::BITCAST, dl, VT,
11502 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11503 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11505 SrcOp.getOperand(0)
11511 return DAG.getNode(ISD::BITCAST, dl, VT,
11512 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11513 DAG.getNode(ISD::BITCAST, dl,
11517 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11518 /// which could not be matched by any known target speficic shuffle
11520 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11522 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11523 if (NewOp.getNode())
11526 MVT VT = SVOp->getSimpleValueType(0);
11528 unsigned NumElems = VT.getVectorNumElements();
11529 unsigned NumLaneElems = NumElems / 2;
11532 MVT EltVT = VT.getVectorElementType();
11533 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11536 SmallVector<int, 16> Mask;
11537 for (unsigned l = 0; l < 2; ++l) {
11538 // Build a shuffle mask for the output, discovering on the fly which
11539 // input vectors to use as shuffle operands (recorded in InputUsed).
11540 // If building a suitable shuffle vector proves too hard, then bail
11541 // out with UseBuildVector set.
11542 bool UseBuildVector = false;
11543 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11544 unsigned LaneStart = l * NumLaneElems;
11545 for (unsigned i = 0; i != NumLaneElems; ++i) {
11546 // The mask element. This indexes into the input.
11547 int Idx = SVOp->getMaskElt(i+LaneStart);
11549 // the mask element does not index into any input vector.
11550 Mask.push_back(-1);
11554 // The input vector this mask element indexes into.
11555 int Input = Idx / NumLaneElems;
11557 // Turn the index into an offset from the start of the input vector.
11558 Idx -= Input * NumLaneElems;
11560 // Find or create a shuffle vector operand to hold this input.
11562 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11563 if (InputUsed[OpNo] == Input)
11564 // This input vector is already an operand.
11566 if (InputUsed[OpNo] < 0) {
11567 // Create a new operand for this input vector.
11568 InputUsed[OpNo] = Input;
11573 if (OpNo >= array_lengthof(InputUsed)) {
11574 // More than two input vectors used! Give up on trying to create a
11575 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11576 UseBuildVector = true;
11580 // Add the mask index for the new shuffle vector.
11581 Mask.push_back(Idx + OpNo * NumLaneElems);
11584 if (UseBuildVector) {
11585 SmallVector<SDValue, 16> SVOps;
11586 for (unsigned i = 0; i != NumLaneElems; ++i) {
11587 // The mask element. This indexes into the input.
11588 int Idx = SVOp->getMaskElt(i+LaneStart);
11590 SVOps.push_back(DAG.getUNDEF(EltVT));
11594 // The input vector this mask element indexes into.
11595 int Input = Idx / NumElems;
11597 // Turn the index into an offset from the start of the input vector.
11598 Idx -= Input * NumElems;
11600 // Extract the vector element by hand.
11601 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11602 SVOp->getOperand(Input),
11603 DAG.getIntPtrConstant(Idx)));
11606 // Construct the output using a BUILD_VECTOR.
11607 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11608 } else if (InputUsed[0] < 0) {
11609 // No input vectors were used! The result is undefined.
11610 Output[l] = DAG.getUNDEF(NVT);
11612 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11613 (InputUsed[0] % 2) * NumLaneElems,
11615 // If only one input was used, use an undefined vector for the other.
11616 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11617 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11618 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11619 // At least one input vector was used. Create a new shuffle vector.
11620 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11626 // Concatenate the result back
11627 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11630 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11631 /// 4 elements, and match them with several different shuffle types.
11633 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11634 SDValue V1 = SVOp->getOperand(0);
11635 SDValue V2 = SVOp->getOperand(1);
11637 MVT VT = SVOp->getSimpleValueType(0);
11639 assert(VT.is128BitVector() && "Unsupported vector size");
11641 std::pair<int, int> Locs[4];
11642 int Mask1[] = { -1, -1, -1, -1 };
11643 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11645 unsigned NumHi = 0;
11646 unsigned NumLo = 0;
11647 for (unsigned i = 0; i != 4; ++i) {
11648 int Idx = PermMask[i];
11650 Locs[i] = std::make_pair(-1, -1);
11652 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11654 Locs[i] = std::make_pair(0, NumLo);
11655 Mask1[NumLo] = Idx;
11658 Locs[i] = std::make_pair(1, NumHi);
11660 Mask1[2+NumHi] = Idx;
11666 if (NumLo <= 2 && NumHi <= 2) {
11667 // If no more than two elements come from either vector. This can be
11668 // implemented with two shuffles. First shuffle gather the elements.
11669 // The second shuffle, which takes the first shuffle as both of its
11670 // vector operands, put the elements into the right order.
11671 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11673 int Mask2[] = { -1, -1, -1, -1 };
11675 for (unsigned i = 0; i != 4; ++i)
11676 if (Locs[i].first != -1) {
11677 unsigned Idx = (i < 2) ? 0 : 4;
11678 Idx += Locs[i].first * 2 + Locs[i].second;
11682 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11685 if (NumLo == 3 || NumHi == 3) {
11686 // Otherwise, we must have three elements from one vector, call it X, and
11687 // one element from the other, call it Y. First, use a shufps to build an
11688 // intermediate vector with the one element from Y and the element from X
11689 // that will be in the same half in the final destination (the indexes don't
11690 // matter). Then, use a shufps to build the final vector, taking the half
11691 // containing the element from Y from the intermediate, and the other half
11694 // Normalize it so the 3 elements come from V1.
11695 CommuteVectorShuffleMask(PermMask, 4);
11699 // Find the element from V2.
11701 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11702 int Val = PermMask[HiIndex];
11709 Mask1[0] = PermMask[HiIndex];
11711 Mask1[2] = PermMask[HiIndex^1];
11713 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11715 if (HiIndex >= 2) {
11716 Mask1[0] = PermMask[0];
11717 Mask1[1] = PermMask[1];
11718 Mask1[2] = HiIndex & 1 ? 6 : 4;
11719 Mask1[3] = HiIndex & 1 ? 4 : 6;
11720 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11723 Mask1[0] = HiIndex & 1 ? 2 : 0;
11724 Mask1[1] = HiIndex & 1 ? 0 : 2;
11725 Mask1[2] = PermMask[2];
11726 Mask1[3] = PermMask[3];
11731 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11734 // Break it into (shuffle shuffle_hi, shuffle_lo).
11735 int LoMask[] = { -1, -1, -1, -1 };
11736 int HiMask[] = { -1, -1, -1, -1 };
11738 int *MaskPtr = LoMask;
11739 unsigned MaskIdx = 0;
11740 unsigned LoIdx = 0;
11741 unsigned HiIdx = 2;
11742 for (unsigned i = 0; i != 4; ++i) {
11749 int Idx = PermMask[i];
11751 Locs[i] = std::make_pair(-1, -1);
11752 } else if (Idx < 4) {
11753 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11754 MaskPtr[LoIdx] = Idx;
11757 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11758 MaskPtr[HiIdx] = Idx;
11763 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11764 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11765 int MaskOps[] = { -1, -1, -1, -1 };
11766 for (unsigned i = 0; i != 4; ++i)
11767 if (Locs[i].first != -1)
11768 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11769 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11772 static bool MayFoldVectorLoad(SDValue V) {
11773 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11774 V = V.getOperand(0);
11776 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11777 V = V.getOperand(0);
11778 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11779 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11780 // BUILD_VECTOR (load), undef
11781 V = V.getOperand(0);
11783 return MayFoldLoad(V);
11787 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11788 MVT VT = Op.getSimpleValueType();
11790 // Canonizalize to v2f64.
11791 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11792 return DAG.getNode(ISD::BITCAST, dl, VT,
11793 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11798 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11800 SDValue V1 = Op.getOperand(0);
11801 SDValue V2 = Op.getOperand(1);
11802 MVT VT = Op.getSimpleValueType();
11804 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11806 if (HasSSE2 && VT == MVT::v2f64)
11807 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11809 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11810 return DAG.getNode(ISD::BITCAST, dl, VT,
11811 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11812 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11813 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11817 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11818 SDValue V1 = Op.getOperand(0);
11819 SDValue V2 = Op.getOperand(1);
11820 MVT VT = Op.getSimpleValueType();
11822 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11823 "unsupported shuffle type");
11825 if (V2.getOpcode() == ISD::UNDEF)
11829 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11833 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11834 SDValue V1 = Op.getOperand(0);
11835 SDValue V2 = Op.getOperand(1);
11836 MVT VT = Op.getSimpleValueType();
11837 unsigned NumElems = VT.getVectorNumElements();
11839 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11840 // operand of these instructions is only memory, so check if there's a
11841 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11843 bool CanFoldLoad = false;
11845 // Trivial case, when V2 comes from a load.
11846 if (MayFoldVectorLoad(V2))
11847 CanFoldLoad = true;
11849 // When V1 is a load, it can be folded later into a store in isel, example:
11850 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11852 // (MOVLPSmr addr:$src1, VR128:$src2)
11853 // So, recognize this potential and also use MOVLPS or MOVLPD
11854 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11855 CanFoldLoad = true;
11857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11859 if (HasSSE2 && NumElems == 2)
11860 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11863 // If we don't care about the second element, proceed to use movss.
11864 if (SVOp->getMaskElt(1) != -1)
11865 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11868 // movl and movlp will both match v2i64, but v2i64 is never matched by
11869 // movl earlier because we make it strict to avoid messing with the movlp load
11870 // folding logic (see the code above getMOVLP call). Match it here then,
11871 // this is horrible, but will stay like this until we move all shuffle
11872 // matching to x86 specific nodes. Note that for the 1st condition all
11873 // types are matched with movsd.
11875 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11876 // as to remove this logic from here, as much as possible
11877 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11878 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11879 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11882 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11884 // Invert the operand order and use SHUFPS to match it.
11885 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11886 getShuffleSHUFImmediate(SVOp), DAG);
11889 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11890 SelectionDAG &DAG) {
11892 MVT VT = Load->getSimpleValueType(0);
11893 MVT EVT = VT.getVectorElementType();
11894 SDValue Addr = Load->getOperand(1);
11895 SDValue NewAddr = DAG.getNode(
11896 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11897 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11900 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11901 DAG.getMachineFunction().getMachineMemOperand(
11902 Load->getMemOperand(), 0, EVT.getStoreSize()));
11906 // It is only safe to call this function if isINSERTPSMask is true for
11907 // this shufflevector mask.
11908 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11909 SelectionDAG &DAG) {
11910 // Generate an insertps instruction when inserting an f32 from memory onto a
11911 // v4f32 or when copying a member from one v4f32 to another.
11912 // We also use it for transferring i32 from one register to another,
11913 // since it simply copies the same bits.
11914 // If we're transferring an i32 from memory to a specific element in a
11915 // register, we output a generic DAG that will match the PINSRD
11917 MVT VT = SVOp->getSimpleValueType(0);
11918 MVT EVT = VT.getVectorElementType();
11919 SDValue V1 = SVOp->getOperand(0);
11920 SDValue V2 = SVOp->getOperand(1);
11921 auto Mask = SVOp->getMask();
11922 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11923 "unsupported vector type for insertps/pinsrd");
11925 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11926 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11927 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11931 unsigned DestIndex;
11935 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11938 // If we have 1 element from each vector, we have to check if we're
11939 // changing V1's element's place. If so, we're done. Otherwise, we
11940 // should assume we're changing V2's element's place and behave
11942 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11943 assert(DestIndex <= INT32_MAX && "truncated destination index");
11944 if (FromV1 == FromV2 &&
11945 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11949 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11952 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11953 "More than one element from V1 and from V2, or no elements from one "
11954 "of the vectors. This case should not have returned true from "
11959 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11962 // Get an index into the source vector in the range [0,4) (the mask is
11963 // in the range [0,8) because it can address V1 and V2)
11964 unsigned SrcIndex = Mask[DestIndex] % 4;
11965 if (MayFoldLoad(From)) {
11966 // Trivial case, when From comes from a load and is only used by the
11967 // shuffle. Make it use insertps from the vector that we need from that
11970 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11971 if (!NewLoad.getNode())
11974 if (EVT == MVT::f32) {
11975 // Create this as a scalar to vector to match the instruction pattern.
11976 SDValue LoadScalarToVector =
11977 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11978 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11979 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11981 } else { // EVT == MVT::i32
11982 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11983 // instruction, to match the PINSRD instruction, which loads an i32 to a
11984 // certain vector element.
11985 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11986 DAG.getConstant(DestIndex, MVT::i32));
11990 // Vector-element-to-vector
11991 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11992 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11995 // Reduce a vector shuffle to zext.
11996 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11997 SelectionDAG &DAG) {
11998 // PMOVZX is only available from SSE41.
11999 if (!Subtarget->hasSSE41())
12002 MVT VT = Op.getSimpleValueType();
12004 // Only AVX2 support 256-bit vector integer extending.
12005 if (!Subtarget->hasInt256() && VT.is256BitVector())
12008 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12010 SDValue V1 = Op.getOperand(0);
12011 SDValue V2 = Op.getOperand(1);
12012 unsigned NumElems = VT.getVectorNumElements();
12014 // Extending is an unary operation and the element type of the source vector
12015 // won't be equal to or larger than i64.
12016 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12017 VT.getVectorElementType() == MVT::i64)
12020 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12021 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12022 while ((1U << Shift) < NumElems) {
12023 if (SVOp->getMaskElt(1U << Shift) == 1)
12026 // The maximal ratio is 8, i.e. from i8 to i64.
12031 // Check the shuffle mask.
12032 unsigned Mask = (1U << Shift) - 1;
12033 for (unsigned i = 0; i != NumElems; ++i) {
12034 int EltIdx = SVOp->getMaskElt(i);
12035 if ((i & Mask) != 0 && EltIdx != -1)
12037 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12041 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12042 MVT NeVT = MVT::getIntegerVT(NBits);
12043 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12045 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12048 return DAG.getNode(ISD::BITCAST, DL, VT,
12049 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12052 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12053 SelectionDAG &DAG) {
12054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12055 MVT VT = Op.getSimpleValueType();
12057 SDValue V1 = Op.getOperand(0);
12058 SDValue V2 = Op.getOperand(1);
12060 if (isZeroShuffle(SVOp))
12061 return getZeroVector(VT, Subtarget, DAG, dl);
12063 // Handle splat operations
12064 if (SVOp->isSplat()) {
12065 // Use vbroadcast whenever the splat comes from a foldable load
12066 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12067 if (Broadcast.getNode())
12071 // Check integer expanding shuffles.
12072 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12073 if (NewOp.getNode())
12076 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12078 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12079 VT == MVT::v32i8) {
12080 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12081 if (NewOp.getNode())
12082 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12083 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12084 // FIXME: Figure out a cleaner way to do this.
12085 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12086 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12087 if (NewOp.getNode()) {
12088 MVT NewVT = NewOp.getSimpleValueType();
12089 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12090 NewVT, true, false))
12091 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12094 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12095 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12096 if (NewOp.getNode()) {
12097 MVT NewVT = NewOp.getSimpleValueType();
12098 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12099 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12108 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12109 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12110 SDValue V1 = Op.getOperand(0);
12111 SDValue V2 = Op.getOperand(1);
12112 MVT VT = Op.getSimpleValueType();
12114 unsigned NumElems = VT.getVectorNumElements();
12115 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12116 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12117 bool V1IsSplat = false;
12118 bool V2IsSplat = false;
12119 bool HasSSE2 = Subtarget->hasSSE2();
12120 bool HasFp256 = Subtarget->hasFp256();
12121 bool HasInt256 = Subtarget->hasInt256();
12122 MachineFunction &MF = DAG.getMachineFunction();
12123 bool OptForSize = MF.getFunction()->getAttributes().
12124 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12126 // Check if we should use the experimental vector shuffle lowering. If so,
12127 // delegate completely to that code path.
12128 if (ExperimentalVectorShuffleLowering)
12129 return lowerVectorShuffle(Op, Subtarget, DAG);
12131 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12133 if (V1IsUndef && V2IsUndef)
12134 return DAG.getUNDEF(VT);
12136 // When we create a shuffle node we put the UNDEF node to second operand,
12137 // but in some cases the first operand may be transformed to UNDEF.
12138 // In this case we should just commute the node.
12140 return DAG.getCommutedVectorShuffle(*SVOp);
12142 // Vector shuffle lowering takes 3 steps:
12144 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12145 // narrowing and commutation of operands should be handled.
12146 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12148 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12149 // so the shuffle can be broken into other shuffles and the legalizer can
12150 // try the lowering again.
12152 // The general idea is that no vector_shuffle operation should be left to
12153 // be matched during isel, all of them must be converted to a target specific
12156 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12157 // narrowing and commutation of operands should be handled. The actual code
12158 // doesn't include all of those, work in progress...
12159 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12160 if (NewOp.getNode())
12163 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12165 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12166 // unpckh_undef). Only use pshufd if speed is more important than size.
12167 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12168 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12169 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12170 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12172 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12173 V2IsUndef && MayFoldVectorLoad(V1))
12174 return getMOVDDup(Op, dl, V1, DAG);
12176 if (isMOVHLPS_v_undef_Mask(M, VT))
12177 return getMOVHighToLow(Op, dl, DAG);
12179 // Use to match splats
12180 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12181 (VT == MVT::v2f64 || VT == MVT::v2i64))
12182 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12184 if (isPSHUFDMask(M, VT)) {
12185 // The actual implementation will match the mask in the if above and then
12186 // during isel it can match several different instructions, not only pshufd
12187 // as its name says, sad but true, emulate the behavior for now...
12188 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12189 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12191 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12193 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12194 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12196 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12197 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12200 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12204 if (isPALIGNRMask(M, VT, Subtarget))
12205 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12206 getShufflePALIGNRImmediate(SVOp),
12209 if (isVALIGNMask(M, VT, Subtarget))
12210 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12211 getShuffleVALIGNImmediate(SVOp),
12214 // Check if this can be converted into a logical shift.
12215 bool isLeft = false;
12216 unsigned ShAmt = 0;
12218 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12219 if (isShift && ShVal.hasOneUse()) {
12220 // If the shifted value has multiple uses, it may be cheaper to use
12221 // v_set0 + movlhps or movhlps, etc.
12222 MVT EltVT = VT.getVectorElementType();
12223 ShAmt *= EltVT.getSizeInBits();
12224 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12227 if (isMOVLMask(M, VT)) {
12228 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12229 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12230 if (!isMOVLPMask(M, VT)) {
12231 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12232 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12234 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12235 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12239 // FIXME: fold these into legal mask.
12240 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12241 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12243 if (isMOVHLPSMask(M, VT))
12244 return getMOVHighToLow(Op, dl, DAG);
12246 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12247 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12249 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12250 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12252 if (isMOVLPMask(M, VT))
12253 return getMOVLP(Op, dl, DAG, HasSSE2);
12255 if (ShouldXformToMOVHLPS(M, VT) ||
12256 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12257 return DAG.getCommutedVectorShuffle(*SVOp);
12260 // No better options. Use a vshldq / vsrldq.
12261 MVT EltVT = VT.getVectorElementType();
12262 ShAmt *= EltVT.getSizeInBits();
12263 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12266 bool Commuted = false;
12267 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12268 // 1,1,1,1 -> v8i16 though.
12269 BitVector UndefElements;
12270 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12271 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12273 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12274 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12277 // Canonicalize the splat or undef, if present, to be on the RHS.
12278 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12279 CommuteVectorShuffleMask(M, NumElems);
12281 std::swap(V1IsSplat, V2IsSplat);
12285 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12286 // Shuffling low element of v1 into undef, just return v1.
12289 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12290 // the instruction selector will not match, so get a canonical MOVL with
12291 // swapped operands to undo the commute.
12292 return getMOVL(DAG, dl, VT, V2, V1);
12295 if (isUNPCKLMask(M, VT, HasInt256))
12296 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12298 if (isUNPCKHMask(M, VT, HasInt256))
12299 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12302 // Normalize mask so all entries that point to V2 points to its first
12303 // element then try to match unpck{h|l} again. If match, return a
12304 // new vector_shuffle with the corrected mask.p
12305 SmallVector<int, 8> NewMask(M.begin(), M.end());
12306 NormalizeMask(NewMask, NumElems);
12307 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12308 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12309 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12310 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12314 // Commute is back and try unpck* again.
12315 // FIXME: this seems wrong.
12316 CommuteVectorShuffleMask(M, NumElems);
12318 std::swap(V1IsSplat, V2IsSplat);
12320 if (isUNPCKLMask(M, VT, HasInt256))
12321 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12323 if (isUNPCKHMask(M, VT, HasInt256))
12324 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12327 // Normalize the node to match x86 shuffle ops if needed
12328 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12329 return DAG.getCommutedVectorShuffle(*SVOp);
12331 // The checks below are all present in isShuffleMaskLegal, but they are
12332 // inlined here right now to enable us to directly emit target specific
12333 // nodes, and remove one by one until they don't return Op anymore.
12335 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12336 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12337 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12338 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12341 if (isPSHUFHWMask(M, VT, HasInt256))
12342 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12343 getShufflePSHUFHWImmediate(SVOp),
12346 if (isPSHUFLWMask(M, VT, HasInt256))
12347 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12348 getShufflePSHUFLWImmediate(SVOp),
12351 unsigned MaskValue;
12352 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12354 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12356 if (isSHUFPMask(M, VT))
12357 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12358 getShuffleSHUFImmediate(SVOp), DAG);
12360 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12361 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12362 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12363 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12365 //===--------------------------------------------------------------------===//
12366 // Generate target specific nodes for 128 or 256-bit shuffles only
12367 // supported in the AVX instruction set.
12370 // Handle VMOVDDUPY permutations
12371 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12372 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12374 // Handle VPERMILPS/D* permutations
12375 if (isVPERMILPMask(M, VT)) {
12376 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12377 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12378 getShuffleSHUFImmediate(SVOp), DAG);
12379 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12380 getShuffleSHUFImmediate(SVOp), DAG);
12384 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12385 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12386 Idx*(NumElems/2), DAG, dl);
12388 // Handle VPERM2F128/VPERM2I128 permutations
12389 if (isVPERM2X128Mask(M, VT, HasFp256))
12390 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12391 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12393 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12394 return getINSERTPS(SVOp, dl, DAG);
12397 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12398 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12400 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12401 VT.is512BitVector()) {
12402 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12403 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12404 SmallVector<SDValue, 16> permclMask;
12405 for (unsigned i = 0; i != NumElems; ++i) {
12406 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12409 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12411 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12412 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12413 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12414 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12415 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12418 //===--------------------------------------------------------------------===//
12419 // Since no target specific shuffle was selected for this generic one,
12420 // lower it into other known shuffles. FIXME: this isn't true yet, but
12421 // this is the plan.
12424 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12425 if (VT == MVT::v8i16) {
12426 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12427 if (NewOp.getNode())
12431 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12432 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12433 if (NewOp.getNode())
12437 if (VT == MVT::v16i8) {
12438 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12439 if (NewOp.getNode())
12443 if (VT == MVT::v32i8) {
12444 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12445 if (NewOp.getNode())
12449 // Handle all 128-bit wide vectors with 4 elements, and match them with
12450 // several different shuffle types.
12451 if (NumElems == 4 && VT.is128BitVector())
12452 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12454 // Handle general 256-bit shuffles
12455 if (VT.is256BitVector())
12456 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12461 // This function assumes its argument is a BUILD_VECTOR of constants or
12462 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12464 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12465 unsigned &MaskValue) {
12467 unsigned NumElems = BuildVector->getNumOperands();
12468 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12469 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12470 unsigned NumElemsInLane = NumElems / NumLanes;
12472 // Blend for v16i16 should be symetric for the both lanes.
12473 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12474 SDValue EltCond = BuildVector->getOperand(i);
12475 SDValue SndLaneEltCond =
12476 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12478 int Lane1Cond = -1, Lane2Cond = -1;
12479 if (isa<ConstantSDNode>(EltCond))
12480 Lane1Cond = !isZero(EltCond);
12481 if (isa<ConstantSDNode>(SndLaneEltCond))
12482 Lane2Cond = !isZero(SndLaneEltCond);
12484 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12485 // Lane1Cond != 0, means we want the first argument.
12486 // Lane1Cond == 0, means we want the second argument.
12487 // The encoding of this argument is 0 for the first argument, 1
12488 // for the second. Therefore, invert the condition.
12489 MaskValue |= !Lane1Cond << i;
12490 else if (Lane1Cond < 0)
12491 MaskValue |= !Lane2Cond << i;
12498 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12500 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12501 SelectionDAG &DAG) {
12502 SDValue Cond = Op.getOperand(0);
12503 SDValue LHS = Op.getOperand(1);
12504 SDValue RHS = Op.getOperand(2);
12506 MVT VT = Op.getSimpleValueType();
12507 MVT EltVT = VT.getVectorElementType();
12508 unsigned NumElems = VT.getVectorNumElements();
12510 // There is no blend with immediate in AVX-512.
12511 if (VT.is512BitVector())
12514 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12516 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12519 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12522 // Check the mask for BLEND and build the value.
12523 unsigned MaskValue = 0;
12524 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12527 // Convert i32 vectors to floating point if it is not AVX2.
12528 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12530 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12531 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12533 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12534 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12537 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12538 DAG.getConstant(MaskValue, MVT::i32));
12539 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12542 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12543 // A vselect where all conditions and data are constants can be optimized into
12544 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12545 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12546 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12547 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12550 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12551 if (BlendOp.getNode())
12554 // Some types for vselect were previously set to Expand, not Legal or
12555 // Custom. Return an empty SDValue so we fall-through to Expand, after
12556 // the Custom lowering phase.
12557 MVT VT = Op.getSimpleValueType();
12558 switch (VT.SimpleTy) {
12563 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12568 // We couldn't create a "Blend with immediate" node.
12569 // This node should still be legal, but we'll have to emit a blendv*
12574 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12575 MVT VT = Op.getSimpleValueType();
12578 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12581 if (VT.getSizeInBits() == 8) {
12582 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12583 Op.getOperand(0), Op.getOperand(1));
12584 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12585 DAG.getValueType(VT));
12586 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12589 if (VT.getSizeInBits() == 16) {
12590 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12591 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12593 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12594 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12595 DAG.getNode(ISD::BITCAST, dl,
12598 Op.getOperand(1)));
12599 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12600 Op.getOperand(0), Op.getOperand(1));
12601 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12602 DAG.getValueType(VT));
12603 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12606 if (VT == MVT::f32) {
12607 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12608 // the result back to FR32 register. It's only worth matching if the
12609 // result has a single use which is a store or a bitcast to i32. And in
12610 // the case of a store, it's not worth it if the index is a constant 0,
12611 // because a MOVSSmr can be used instead, which is smaller and faster.
12612 if (!Op.hasOneUse())
12614 SDNode *User = *Op.getNode()->use_begin();
12615 if ((User->getOpcode() != ISD::STORE ||
12616 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12617 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12618 (User->getOpcode() != ISD::BITCAST ||
12619 User->getValueType(0) != MVT::i32))
12621 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12622 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12625 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12628 if (VT == MVT::i32 || VT == MVT::i64) {
12629 // ExtractPS/pextrq works with constant index.
12630 if (isa<ConstantSDNode>(Op.getOperand(1)))
12636 /// Extract one bit from mask vector, like v16i1 or v8i1.
12637 /// AVX-512 feature.
12639 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12640 SDValue Vec = Op.getOperand(0);
12642 MVT VecVT = Vec.getSimpleValueType();
12643 SDValue Idx = Op.getOperand(1);
12644 MVT EltVT = Op.getSimpleValueType();
12646 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12648 // variable index can't be handled in mask registers,
12649 // extend vector to VR512
12650 if (!isa<ConstantSDNode>(Idx)) {
12651 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12652 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12653 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12654 ExtVT.getVectorElementType(), Ext, Idx);
12655 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12658 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12659 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12660 unsigned MaxSift = rc->getSize()*8 - 1;
12661 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12662 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12663 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12664 DAG.getConstant(MaxSift, MVT::i8));
12665 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12666 DAG.getIntPtrConstant(0));
12670 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12671 SelectionDAG &DAG) const {
12673 SDValue Vec = Op.getOperand(0);
12674 MVT VecVT = Vec.getSimpleValueType();
12675 SDValue Idx = Op.getOperand(1);
12677 if (Op.getSimpleValueType() == MVT::i1)
12678 return ExtractBitFromMaskVector(Op, DAG);
12680 if (!isa<ConstantSDNode>(Idx)) {
12681 if (VecVT.is512BitVector() ||
12682 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12683 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12686 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12687 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12688 MaskEltVT.getSizeInBits());
12690 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12691 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12692 getZeroVector(MaskVT, Subtarget, DAG, dl),
12693 Idx, DAG.getConstant(0, getPointerTy()));
12694 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12695 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12696 Perm, DAG.getConstant(0, getPointerTy()));
12701 // If this is a 256-bit vector result, first extract the 128-bit vector and
12702 // then extract the element from the 128-bit vector.
12703 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12705 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12706 // Get the 128-bit vector.
12707 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12708 MVT EltVT = VecVT.getVectorElementType();
12710 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12712 //if (IdxVal >= NumElems/2)
12713 // IdxVal -= NumElems/2;
12714 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12715 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12716 DAG.getConstant(IdxVal, MVT::i32));
12719 assert(VecVT.is128BitVector() && "Unexpected vector length");
12721 if (Subtarget->hasSSE41()) {
12722 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12727 MVT VT = Op.getSimpleValueType();
12728 // TODO: handle v16i8.
12729 if (VT.getSizeInBits() == 16) {
12730 SDValue Vec = Op.getOperand(0);
12731 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12733 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12734 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12735 DAG.getNode(ISD::BITCAST, dl,
12737 Op.getOperand(1)));
12738 // Transform it so it match pextrw which produces a 32-bit result.
12739 MVT EltVT = MVT::i32;
12740 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12741 Op.getOperand(0), Op.getOperand(1));
12742 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12743 DAG.getValueType(VT));
12744 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12747 if (VT.getSizeInBits() == 32) {
12748 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12752 // SHUFPS the element to the lowest double word, then movss.
12753 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12754 MVT VVT = Op.getOperand(0).getSimpleValueType();
12755 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12756 DAG.getUNDEF(VVT), Mask);
12757 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12758 DAG.getIntPtrConstant(0));
12761 if (VT.getSizeInBits() == 64) {
12762 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12763 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12764 // to match extract_elt for f64.
12765 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12769 // UNPCKHPD the element to the lowest double word, then movsd.
12770 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12771 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12772 int Mask[2] = { 1, -1 };
12773 MVT VVT = Op.getOperand(0).getSimpleValueType();
12774 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12775 DAG.getUNDEF(VVT), Mask);
12776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12777 DAG.getIntPtrConstant(0));
12783 /// Insert one bit to mask vector, like v16i1 or v8i1.
12784 /// AVX-512 feature.
12786 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12788 SDValue Vec = Op.getOperand(0);
12789 SDValue Elt = Op.getOperand(1);
12790 SDValue Idx = Op.getOperand(2);
12791 MVT VecVT = Vec.getSimpleValueType();
12793 if (!isa<ConstantSDNode>(Idx)) {
12794 // Non constant index. Extend source and destination,
12795 // insert element and then truncate the result.
12796 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12797 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12798 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12799 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12800 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12801 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12804 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12805 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12806 if (Vec.getOpcode() == ISD::UNDEF)
12807 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12808 DAG.getConstant(IdxVal, MVT::i8));
12809 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12810 unsigned MaxSift = rc->getSize()*8 - 1;
12811 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12812 DAG.getConstant(MaxSift, MVT::i8));
12813 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12814 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12815 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12818 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12819 SelectionDAG &DAG) const {
12820 MVT VT = Op.getSimpleValueType();
12821 MVT EltVT = VT.getVectorElementType();
12823 if (EltVT == MVT::i1)
12824 return InsertBitToMaskVector(Op, DAG);
12827 SDValue N0 = Op.getOperand(0);
12828 SDValue N1 = Op.getOperand(1);
12829 SDValue N2 = Op.getOperand(2);
12830 if (!isa<ConstantSDNode>(N2))
12832 auto *N2C = cast<ConstantSDNode>(N2);
12833 unsigned IdxVal = N2C->getZExtValue();
12835 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12836 // into that, and then insert the subvector back into the result.
12837 if (VT.is256BitVector() || VT.is512BitVector()) {
12838 // Get the desired 128-bit vector half.
12839 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12841 // Insert the element into the desired half.
12842 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12843 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12845 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12846 DAG.getConstant(IdxIn128, MVT::i32));
12848 // Insert the changed part back to the 256-bit vector
12849 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12851 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12853 if (Subtarget->hasSSE41()) {
12854 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12856 if (VT == MVT::v8i16) {
12857 Opc = X86ISD::PINSRW;
12859 assert(VT == MVT::v16i8);
12860 Opc = X86ISD::PINSRB;
12863 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12865 if (N1.getValueType() != MVT::i32)
12866 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12867 if (N2.getValueType() != MVT::i32)
12868 N2 = DAG.getIntPtrConstant(IdxVal);
12869 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12872 if (EltVT == MVT::f32) {
12873 // Bits [7:6] of the constant are the source select. This will always be
12874 // zero here. The DAG Combiner may combine an extract_elt index into
12876 // bits. For example (insert (extract, 3), 2) could be matched by
12878 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12879 // Bits [5:4] of the constant are the destination select. This is the
12880 // value of the incoming immediate.
12881 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12882 // combine either bitwise AND or insert of float 0.0 to set these bits.
12883 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12884 // Create this as a scalar to vector..
12885 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12886 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12889 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12890 // PINSR* works with constant index.
12895 if (EltVT == MVT::i8)
12898 if (EltVT.getSizeInBits() == 16) {
12899 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12900 // as its second argument.
12901 if (N1.getValueType() != MVT::i32)
12902 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12903 if (N2.getValueType() != MVT::i32)
12904 N2 = DAG.getIntPtrConstant(IdxVal);
12905 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12910 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12912 MVT OpVT = Op.getSimpleValueType();
12914 // If this is a 256-bit vector result, first insert into a 128-bit
12915 // vector and then insert into the 256-bit vector.
12916 if (!OpVT.is128BitVector()) {
12917 // Insert into a 128-bit vector.
12918 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12919 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12920 OpVT.getVectorNumElements() / SizeFactor);
12922 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12924 // Insert the 128-bit vector.
12925 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12928 if (OpVT == MVT::v1i64 &&
12929 Op.getOperand(0).getValueType() == MVT::i64)
12930 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12932 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12933 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12934 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12935 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12938 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12939 // a simple subregister reference or explicit instructions to grab
12940 // upper bits of a vector.
12941 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12942 SelectionDAG &DAG) {
12944 SDValue In = Op.getOperand(0);
12945 SDValue Idx = Op.getOperand(1);
12946 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12947 MVT ResVT = Op.getSimpleValueType();
12948 MVT InVT = In.getSimpleValueType();
12950 if (Subtarget->hasFp256()) {
12951 if (ResVT.is128BitVector() &&
12952 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12953 isa<ConstantSDNode>(Idx)) {
12954 return Extract128BitVector(In, IdxVal, DAG, dl);
12956 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12957 isa<ConstantSDNode>(Idx)) {
12958 return Extract256BitVector(In, IdxVal, DAG, dl);
12964 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12965 // simple superregister reference or explicit instructions to insert
12966 // the upper bits of a vector.
12967 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12968 SelectionDAG &DAG) {
12969 if (Subtarget->hasFp256()) {
12970 SDLoc dl(Op.getNode());
12971 SDValue Vec = Op.getNode()->getOperand(0);
12972 SDValue SubVec = Op.getNode()->getOperand(1);
12973 SDValue Idx = Op.getNode()->getOperand(2);
12975 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12976 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12977 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12978 isa<ConstantSDNode>(Idx)) {
12979 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12980 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12983 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12984 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12985 isa<ConstantSDNode>(Idx)) {
12986 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12987 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12993 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12994 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12995 // one of the above mentioned nodes. It has to be wrapped because otherwise
12996 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12997 // be used to form addressing mode. These wrapped nodes will be selected
13000 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13001 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13003 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13004 // global base reg.
13005 unsigned char OpFlag = 0;
13006 unsigned WrapperKind = X86ISD::Wrapper;
13007 CodeModel::Model M = DAG.getTarget().getCodeModel();
13009 if (Subtarget->isPICStyleRIPRel() &&
13010 (M == CodeModel::Small || M == CodeModel::Kernel))
13011 WrapperKind = X86ISD::WrapperRIP;
13012 else if (Subtarget->isPICStyleGOT())
13013 OpFlag = X86II::MO_GOTOFF;
13014 else if (Subtarget->isPICStyleStubPIC())
13015 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13017 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13018 CP->getAlignment(),
13019 CP->getOffset(), OpFlag);
13021 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13022 // With PIC, the address is actually $g + Offset.
13024 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13025 DAG.getNode(X86ISD::GlobalBaseReg,
13026 SDLoc(), getPointerTy()),
13033 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13034 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13036 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13037 // global base reg.
13038 unsigned char OpFlag = 0;
13039 unsigned WrapperKind = X86ISD::Wrapper;
13040 CodeModel::Model M = DAG.getTarget().getCodeModel();
13042 if (Subtarget->isPICStyleRIPRel() &&
13043 (M == CodeModel::Small || M == CodeModel::Kernel))
13044 WrapperKind = X86ISD::WrapperRIP;
13045 else if (Subtarget->isPICStyleGOT())
13046 OpFlag = X86II::MO_GOTOFF;
13047 else if (Subtarget->isPICStyleStubPIC())
13048 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13050 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13053 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13055 // With PIC, the address is actually $g + Offset.
13057 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13058 DAG.getNode(X86ISD::GlobalBaseReg,
13059 SDLoc(), getPointerTy()),
13066 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13067 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13069 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13070 // global base reg.
13071 unsigned char OpFlag = 0;
13072 unsigned WrapperKind = X86ISD::Wrapper;
13073 CodeModel::Model M = DAG.getTarget().getCodeModel();
13075 if (Subtarget->isPICStyleRIPRel() &&
13076 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13077 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13078 OpFlag = X86II::MO_GOTPCREL;
13079 WrapperKind = X86ISD::WrapperRIP;
13080 } else if (Subtarget->isPICStyleGOT()) {
13081 OpFlag = X86II::MO_GOT;
13082 } else if (Subtarget->isPICStyleStubPIC()) {
13083 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13084 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13085 OpFlag = X86II::MO_DARWIN_NONLAZY;
13088 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13091 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13093 // With PIC, the address is actually $g + Offset.
13094 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13095 !Subtarget->is64Bit()) {
13096 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13097 DAG.getNode(X86ISD::GlobalBaseReg,
13098 SDLoc(), getPointerTy()),
13102 // For symbols that require a load from a stub to get the address, emit the
13104 if (isGlobalStubReference(OpFlag))
13105 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13106 MachinePointerInfo::getGOT(), false, false, false, 0);
13112 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13113 // Create the TargetBlockAddressAddress node.
13114 unsigned char OpFlags =
13115 Subtarget->ClassifyBlockAddressReference();
13116 CodeModel::Model M = DAG.getTarget().getCodeModel();
13117 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13118 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13120 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13123 if (Subtarget->isPICStyleRIPRel() &&
13124 (M == CodeModel::Small || M == CodeModel::Kernel))
13125 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13127 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13129 // With PIC, the address is actually $g + Offset.
13130 if (isGlobalRelativeToPICBase(OpFlags)) {
13131 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13132 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13140 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13141 int64_t Offset, SelectionDAG &DAG) const {
13142 // Create the TargetGlobalAddress node, folding in the constant
13143 // offset if it is legal.
13144 unsigned char OpFlags =
13145 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13146 CodeModel::Model M = DAG.getTarget().getCodeModel();
13148 if (OpFlags == X86II::MO_NO_FLAG &&
13149 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13150 // A direct static reference to a global.
13151 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13154 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13157 if (Subtarget->isPICStyleRIPRel() &&
13158 (M == CodeModel::Small || M == CodeModel::Kernel))
13159 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13161 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13163 // With PIC, the address is actually $g + Offset.
13164 if (isGlobalRelativeToPICBase(OpFlags)) {
13165 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13166 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13170 // For globals that require a load from a stub to get the address, emit the
13172 if (isGlobalStubReference(OpFlags))
13173 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13174 MachinePointerInfo::getGOT(), false, false, false, 0);
13176 // If there was a non-zero offset that we didn't fold, create an explicit
13177 // addition for it.
13179 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13180 DAG.getConstant(Offset, getPointerTy()));
13186 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13187 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13188 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13189 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13193 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13194 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13195 unsigned char OperandFlags, bool LocalDynamic = false) {
13196 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13197 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13199 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13200 GA->getValueType(0),
13204 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13208 SDValue Ops[] = { Chain, TGA, *InFlag };
13209 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13211 SDValue Ops[] = { Chain, TGA };
13212 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13215 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13216 MFI->setAdjustsStack(true);
13217 MFI->setHasCalls(true);
13219 SDValue Flag = Chain.getValue(1);
13220 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13223 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13225 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13228 SDLoc dl(GA); // ? function entry point might be better
13229 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13230 DAG.getNode(X86ISD::GlobalBaseReg,
13231 SDLoc(), PtrVT), InFlag);
13232 InFlag = Chain.getValue(1);
13234 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13237 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13239 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13241 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13242 X86::RAX, X86II::MO_TLSGD);
13245 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13251 // Get the start address of the TLS block for this module.
13252 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13253 .getInfo<X86MachineFunctionInfo>();
13254 MFI->incNumLocalDynamicTLSAccesses();
13258 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13259 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13262 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13263 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13264 InFlag = Chain.getValue(1);
13265 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13266 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13269 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13273 unsigned char OperandFlags = X86II::MO_DTPOFF;
13274 unsigned WrapperKind = X86ISD::Wrapper;
13275 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13276 GA->getValueType(0),
13277 GA->getOffset(), OperandFlags);
13278 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13280 // Add x@dtpoff with the base.
13281 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13284 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13285 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13286 const EVT PtrVT, TLSModel::Model model,
13287 bool is64Bit, bool isPIC) {
13290 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13291 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13292 is64Bit ? 257 : 256));
13294 SDValue ThreadPointer =
13295 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13296 MachinePointerInfo(Ptr), false, false, false, 0);
13298 unsigned char OperandFlags = 0;
13299 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13301 unsigned WrapperKind = X86ISD::Wrapper;
13302 if (model == TLSModel::LocalExec) {
13303 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13304 } else if (model == TLSModel::InitialExec) {
13306 OperandFlags = X86II::MO_GOTTPOFF;
13307 WrapperKind = X86ISD::WrapperRIP;
13309 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13312 llvm_unreachable("Unexpected model");
13315 // emit "addl x@ntpoff,%eax" (local exec)
13316 // or "addl x@indntpoff,%eax" (initial exec)
13317 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13319 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13320 GA->getOffset(), OperandFlags);
13321 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13323 if (model == TLSModel::InitialExec) {
13324 if (isPIC && !is64Bit) {
13325 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13326 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13330 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13331 MachinePointerInfo::getGOT(), false, false, false, 0);
13334 // The address of the thread local variable is the add of the thread
13335 // pointer with the offset of the variable.
13336 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13340 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13342 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13343 const GlobalValue *GV = GA->getGlobal();
13345 if (Subtarget->isTargetELF()) {
13346 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13349 case TLSModel::GeneralDynamic:
13350 if (Subtarget->is64Bit())
13351 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13352 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13353 case TLSModel::LocalDynamic:
13354 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13355 Subtarget->is64Bit());
13356 case TLSModel::InitialExec:
13357 case TLSModel::LocalExec:
13358 return LowerToTLSExecModel(
13359 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13360 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13362 llvm_unreachable("Unknown TLS model.");
13365 if (Subtarget->isTargetDarwin()) {
13366 // Darwin only has one model of TLS. Lower to that.
13367 unsigned char OpFlag = 0;
13368 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13369 X86ISD::WrapperRIP : X86ISD::Wrapper;
13371 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13372 // global base reg.
13373 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13374 !Subtarget->is64Bit();
13376 OpFlag = X86II::MO_TLVP_PIC_BASE;
13378 OpFlag = X86II::MO_TLVP;
13380 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13381 GA->getValueType(0),
13382 GA->getOffset(), OpFlag);
13383 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13385 // With PIC32, the address is actually $g + Offset.
13387 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13388 DAG.getNode(X86ISD::GlobalBaseReg,
13389 SDLoc(), getPointerTy()),
13392 // Lowering the machine isd will make sure everything is in the right
13394 SDValue Chain = DAG.getEntryNode();
13395 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13396 SDValue Args[] = { Chain, Offset };
13397 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13399 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13400 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13401 MFI->setAdjustsStack(true);
13403 // And our return value (tls address) is in the standard call return value
13405 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13406 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13407 Chain.getValue(1));
13410 if (Subtarget->isTargetKnownWindowsMSVC() ||
13411 Subtarget->isTargetWindowsGNU()) {
13412 // Just use the implicit TLS architecture
13413 // Need to generate someting similar to:
13414 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13416 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13417 // mov rcx, qword [rdx+rcx*8]
13418 // mov eax, .tls$:tlsvar
13419 // [rax+rcx] contains the address
13420 // Windows 64bit: gs:0x58
13421 // Windows 32bit: fs:__tls_array
13424 SDValue Chain = DAG.getEntryNode();
13426 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13427 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13428 // use its literal value of 0x2C.
13429 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13430 ? Type::getInt8PtrTy(*DAG.getContext(),
13432 : Type::getInt32PtrTy(*DAG.getContext(),
13436 Subtarget->is64Bit()
13437 ? DAG.getIntPtrConstant(0x58)
13438 : (Subtarget->isTargetWindowsGNU()
13439 ? DAG.getIntPtrConstant(0x2C)
13440 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13442 SDValue ThreadPointer =
13443 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13444 MachinePointerInfo(Ptr), false, false, false, 0);
13446 // Load the _tls_index variable
13447 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13448 if (Subtarget->is64Bit())
13449 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13450 IDX, MachinePointerInfo(), MVT::i32,
13451 false, false, false, 0);
13453 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13454 false, false, false, 0);
13456 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13458 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13460 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13461 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13462 false, false, false, 0);
13464 // Get the offset of start of .tls section
13465 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13466 GA->getValueType(0),
13467 GA->getOffset(), X86II::MO_SECREL);
13468 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13470 // The address of the thread local variable is the add of the thread
13471 // pointer with the offset of the variable.
13472 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13475 llvm_unreachable("TLS not implemented for this target.");
13478 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13479 /// and take a 2 x i32 value to shift plus a shift amount.
13480 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13481 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13482 MVT VT = Op.getSimpleValueType();
13483 unsigned VTBits = VT.getSizeInBits();
13485 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13486 SDValue ShOpLo = Op.getOperand(0);
13487 SDValue ShOpHi = Op.getOperand(1);
13488 SDValue ShAmt = Op.getOperand(2);
13489 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13490 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13492 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13493 DAG.getConstant(VTBits - 1, MVT::i8));
13494 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13495 DAG.getConstant(VTBits - 1, MVT::i8))
13496 : DAG.getConstant(0, VT);
13498 SDValue Tmp2, Tmp3;
13499 if (Op.getOpcode() == ISD::SHL_PARTS) {
13500 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13501 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13503 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13504 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13507 // If the shift amount is larger or equal than the width of a part we can't
13508 // rely on the results of shld/shrd. Insert a test and select the appropriate
13509 // values for large shift amounts.
13510 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13511 DAG.getConstant(VTBits, MVT::i8));
13512 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13513 AndNode, DAG.getConstant(0, MVT::i8));
13516 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13517 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13518 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13520 if (Op.getOpcode() == ISD::SHL_PARTS) {
13521 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13522 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13524 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13525 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13528 SDValue Ops[2] = { Lo, Hi };
13529 return DAG.getMergeValues(Ops, dl);
13532 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13533 SelectionDAG &DAG) const {
13534 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13537 if (SrcVT.isVector()) {
13538 if (SrcVT.getVectorElementType() == MVT::i1) {
13539 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13540 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13541 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13542 Op.getOperand(0)));
13547 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13548 "Unknown SINT_TO_FP to lower!");
13550 // These are really Legal; return the operand so the caller accepts it as
13552 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13554 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13555 Subtarget->is64Bit()) {
13559 unsigned Size = SrcVT.getSizeInBits()/8;
13560 MachineFunction &MF = DAG.getMachineFunction();
13561 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13562 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13563 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13565 MachinePointerInfo::getFixedStack(SSFI),
13567 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13570 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13572 SelectionDAG &DAG) const {
13576 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13578 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13580 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13582 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13584 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13585 MachineMemOperand *MMO;
13587 int SSFI = FI->getIndex();
13589 DAG.getMachineFunction()
13590 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13591 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13593 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13594 StackSlot = StackSlot.getOperand(1);
13596 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13597 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13599 Tys, Ops, SrcVT, MMO);
13602 Chain = Result.getValue(1);
13603 SDValue InFlag = Result.getValue(2);
13605 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13606 // shouldn't be necessary except that RFP cannot be live across
13607 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13608 MachineFunction &MF = DAG.getMachineFunction();
13609 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13610 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13611 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13612 Tys = DAG.getVTList(MVT::Other);
13614 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13616 MachineMemOperand *MMO =
13617 DAG.getMachineFunction()
13618 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13619 MachineMemOperand::MOStore, SSFISize, SSFISize);
13621 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13622 Ops, Op.getValueType(), MMO);
13623 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13624 MachinePointerInfo::getFixedStack(SSFI),
13625 false, false, false, 0);
13631 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13632 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13633 SelectionDAG &DAG) const {
13634 // This algorithm is not obvious. Here it is what we're trying to output:
13637 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13638 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13640 haddpd %xmm0, %xmm0
13642 pshufd $0x4e, %xmm0, %xmm1
13648 LLVMContext *Context = DAG.getContext();
13650 // Build some magic constants.
13651 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13652 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13653 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13655 SmallVector<Constant*,2> CV1;
13657 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13658 APInt(64, 0x4330000000000000ULL))));
13660 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13661 APInt(64, 0x4530000000000000ULL))));
13662 Constant *C1 = ConstantVector::get(CV1);
13663 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13665 // Load the 64-bit value into an XMM register.
13666 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13668 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13669 MachinePointerInfo::getConstantPool(),
13670 false, false, false, 16);
13671 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13672 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13675 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13676 MachinePointerInfo::getConstantPool(),
13677 false, false, false, 16);
13678 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13679 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13682 if (Subtarget->hasSSE3()) {
13683 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13684 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13686 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13687 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13689 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13690 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13694 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13695 DAG.getIntPtrConstant(0));
13698 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13699 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13700 SelectionDAG &DAG) const {
13702 // FP constant to bias correct the final result.
13703 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13706 // Load the 32-bit value into an XMM register.
13707 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13710 // Zero out the upper parts of the register.
13711 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13713 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13714 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13715 DAG.getIntPtrConstant(0));
13717 // Or the load with the bias.
13718 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13719 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13720 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13721 MVT::v2f64, Load)),
13722 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13723 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13724 MVT::v2f64, Bias)));
13725 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13726 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13727 DAG.getIntPtrConstant(0));
13729 // Subtract the bias.
13730 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13732 // Handle final rounding.
13733 EVT DestVT = Op.getValueType();
13735 if (DestVT.bitsLT(MVT::f64))
13736 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13737 DAG.getIntPtrConstant(0));
13738 if (DestVT.bitsGT(MVT::f64))
13739 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13741 // Handle final rounding.
13745 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13746 const X86Subtarget &Subtarget) {
13747 // The algorithm is the following:
13748 // #ifdef __SSE4_1__
13749 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13750 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13751 // (uint4) 0x53000000, 0xaa);
13753 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13754 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13756 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13757 // return (float4) lo + fhi;
13760 SDValue V = Op->getOperand(0);
13761 EVT VecIntVT = V.getValueType();
13762 bool Is128 = VecIntVT == MVT::v4i32;
13763 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13764 // If we convert to something else than the supported type, e.g., to v4f64,
13766 if (VecFloatVT != Op->getValueType(0))
13769 unsigned NumElts = VecIntVT.getVectorNumElements();
13770 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13771 "Unsupported custom type");
13772 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13774 // In the #idef/#else code, we have in common:
13775 // - The vector of constants:
13781 // Create the splat vector for 0x4b000000.
13782 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13783 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13784 CstLow, CstLow, CstLow, CstLow};
13785 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13786 makeArrayRef(&CstLowArray[0], NumElts));
13787 // Create the splat vector for 0x53000000.
13788 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13789 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13790 CstHigh, CstHigh, CstHigh, CstHigh};
13791 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13792 makeArrayRef(&CstHighArray[0], NumElts));
13794 // Create the right shift.
13795 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13796 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13797 CstShift, CstShift, CstShift, CstShift};
13798 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13799 makeArrayRef(&CstShiftArray[0], NumElts));
13800 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13803 if (Subtarget.hasSSE41()) {
13804 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13805 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13806 SDValue VecCstLowBitcast =
13807 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13808 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13809 // Low will be bitcasted right away, so do not bother bitcasting back to its
13811 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13812 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13813 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13814 // (uint4) 0x53000000, 0xaa);
13815 SDValue VecCstHighBitcast =
13816 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13817 SDValue VecShiftBitcast =
13818 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13819 // High will be bitcasted right away, so do not bother bitcasting back to
13820 // its original type.
13821 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13822 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13824 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13825 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13826 CstMask, CstMask, CstMask);
13827 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13828 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13829 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13831 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13832 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13835 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13836 SDValue CstFAdd = DAG.getConstantFP(
13837 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13838 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13839 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13840 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13841 makeArrayRef(&CstFAddArray[0], NumElts));
13843 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13844 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13846 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13847 // return (float4) lo + fhi;
13848 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13849 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13852 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13853 SelectionDAG &DAG) const {
13854 SDValue N0 = Op.getOperand(0);
13855 MVT SVT = N0.getSimpleValueType();
13858 switch (SVT.SimpleTy) {
13860 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13865 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13866 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13867 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13871 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13873 llvm_unreachable(nullptr);
13876 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13877 SelectionDAG &DAG) const {
13878 SDValue N0 = Op.getOperand(0);
13881 if (Op.getValueType().isVector())
13882 return lowerUINT_TO_FP_vec(Op, DAG);
13884 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13885 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13886 // the optimization here.
13887 if (DAG.SignBitIsZero(N0))
13888 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13890 MVT SrcVT = N0.getSimpleValueType();
13891 MVT DstVT = Op.getSimpleValueType();
13892 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13893 return LowerUINT_TO_FP_i64(Op, DAG);
13894 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13895 return LowerUINT_TO_FP_i32(Op, DAG);
13896 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13899 // Make a 64-bit buffer, and use it to build an FILD.
13900 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13901 if (SrcVT == MVT::i32) {
13902 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13903 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13904 getPointerTy(), StackSlot, WordOff);
13905 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13906 StackSlot, MachinePointerInfo(),
13908 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13909 OffsetSlot, MachinePointerInfo(),
13911 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13915 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13916 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13917 StackSlot, MachinePointerInfo(),
13919 // For i64 source, we need to add the appropriate power of 2 if the input
13920 // was negative. This is the same as the optimization in
13921 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13922 // we must be careful to do the computation in x87 extended precision, not
13923 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13924 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13925 MachineMemOperand *MMO =
13926 DAG.getMachineFunction()
13927 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13928 MachineMemOperand::MOLoad, 8, 8);
13930 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13931 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13932 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13935 APInt FF(32, 0x5F800000ULL);
13937 // Check whether the sign bit is set.
13938 SDValue SignSet = DAG.getSetCC(dl,
13939 getSetCCResultType(*DAG.getContext(), MVT::i64),
13940 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13943 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13944 SDValue FudgePtr = DAG.getConstantPool(
13945 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13948 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13949 SDValue Zero = DAG.getIntPtrConstant(0);
13950 SDValue Four = DAG.getIntPtrConstant(4);
13951 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13953 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13955 // Load the value out, extending it from f32 to f80.
13956 // FIXME: Avoid the extend by constructing the right constant pool?
13957 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13958 FudgePtr, MachinePointerInfo::getConstantPool(),
13959 MVT::f32, false, false, false, 4);
13960 // Extend everything to 80 bits to force it to be done on x87.
13961 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13962 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13965 std::pair<SDValue,SDValue>
13966 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13967 bool IsSigned, bool IsReplace) const {
13970 EVT DstTy = Op.getValueType();
13972 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13973 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13977 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13978 DstTy.getSimpleVT() >= MVT::i16 &&
13979 "Unknown FP_TO_INT to lower!");
13981 // These are really Legal.
13982 if (DstTy == MVT::i32 &&
13983 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13984 return std::make_pair(SDValue(), SDValue());
13985 if (Subtarget->is64Bit() &&
13986 DstTy == MVT::i64 &&
13987 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13988 return std::make_pair(SDValue(), SDValue());
13990 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13991 // stack slot, or into the FTOL runtime function.
13992 MachineFunction &MF = DAG.getMachineFunction();
13993 unsigned MemSize = DstTy.getSizeInBits()/8;
13994 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13995 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13998 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13999 Opc = X86ISD::WIN_FTOL;
14001 switch (DstTy.getSimpleVT().SimpleTy) {
14002 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14003 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14004 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14005 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14008 SDValue Chain = DAG.getEntryNode();
14009 SDValue Value = Op.getOperand(0);
14010 EVT TheVT = Op.getOperand(0).getValueType();
14011 // FIXME This causes a redundant load/store if the SSE-class value is already
14012 // in memory, such as if it is on the callstack.
14013 if (isScalarFPTypeInSSEReg(TheVT)) {
14014 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14015 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14016 MachinePointerInfo::getFixedStack(SSFI),
14018 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14020 Chain, StackSlot, DAG.getValueType(TheVT)
14023 MachineMemOperand *MMO =
14024 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14025 MachineMemOperand::MOLoad, MemSize, MemSize);
14026 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14027 Chain = Value.getValue(1);
14028 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14029 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14032 MachineMemOperand *MMO =
14033 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14034 MachineMemOperand::MOStore, MemSize, MemSize);
14036 if (Opc != X86ISD::WIN_FTOL) {
14037 // Build the FP_TO_INT*_IN_MEM
14038 SDValue Ops[] = { Chain, Value, StackSlot };
14039 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14041 return std::make_pair(FIST, StackSlot);
14043 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14044 DAG.getVTList(MVT::Other, MVT::Glue),
14046 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14047 MVT::i32, ftol.getValue(1));
14048 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14049 MVT::i32, eax.getValue(2));
14050 SDValue Ops[] = { eax, edx };
14051 SDValue pair = IsReplace
14052 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14053 : DAG.getMergeValues(Ops, DL);
14054 return std::make_pair(pair, SDValue());
14058 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14059 const X86Subtarget *Subtarget) {
14060 MVT VT = Op->getSimpleValueType(0);
14061 SDValue In = Op->getOperand(0);
14062 MVT InVT = In.getSimpleValueType();
14065 // Optimize vectors in AVX mode:
14068 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14069 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14070 // Concat upper and lower parts.
14073 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14074 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14075 // Concat upper and lower parts.
14078 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14079 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14080 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14083 if (Subtarget->hasInt256())
14084 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14086 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14087 SDValue Undef = DAG.getUNDEF(InVT);
14088 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14089 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14090 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14092 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14093 VT.getVectorNumElements()/2);
14095 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14096 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14098 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14101 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14102 SelectionDAG &DAG) {
14103 MVT VT = Op->getSimpleValueType(0);
14104 SDValue In = Op->getOperand(0);
14105 MVT InVT = In.getSimpleValueType();
14107 unsigned int NumElts = VT.getVectorNumElements();
14108 if (NumElts != 8 && NumElts != 16)
14111 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14112 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14114 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14116 // Now we have only mask extension
14117 assert(InVT.getVectorElementType() == MVT::i1);
14118 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14119 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14120 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14121 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14122 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14123 MachinePointerInfo::getConstantPool(),
14124 false, false, false, Alignment);
14126 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14127 if (VT.is512BitVector())
14129 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14132 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14133 SelectionDAG &DAG) {
14134 if (Subtarget->hasFp256()) {
14135 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14143 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14144 SelectionDAG &DAG) {
14146 MVT VT = Op.getSimpleValueType();
14147 SDValue In = Op.getOperand(0);
14148 MVT SVT = In.getSimpleValueType();
14150 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14151 return LowerZERO_EXTEND_AVX512(Op, DAG);
14153 if (Subtarget->hasFp256()) {
14154 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14159 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14160 VT.getVectorNumElements() != SVT.getVectorNumElements());
14164 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14166 MVT VT = Op.getSimpleValueType();
14167 SDValue In = Op.getOperand(0);
14168 MVT InVT = In.getSimpleValueType();
14170 if (VT == MVT::i1) {
14171 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14172 "Invalid scalar TRUNCATE operation");
14173 if (InVT.getSizeInBits() >= 32)
14175 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14176 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14178 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14179 "Invalid TRUNCATE operation");
14181 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14182 if (VT.getVectorElementType().getSizeInBits() >=8)
14183 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14185 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14186 unsigned NumElts = InVT.getVectorNumElements();
14187 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14188 if (InVT.getSizeInBits() < 512) {
14189 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14190 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14194 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14195 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14196 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14197 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14198 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14199 MachinePointerInfo::getConstantPool(),
14200 false, false, false, Alignment);
14201 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14202 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14203 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14206 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14207 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14208 if (Subtarget->hasInt256()) {
14209 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14210 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14211 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14213 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14214 DAG.getIntPtrConstant(0));
14217 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14218 DAG.getIntPtrConstant(0));
14219 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14220 DAG.getIntPtrConstant(2));
14221 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14222 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14223 static const int ShufMask[] = {0, 2, 4, 6};
14224 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14227 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14228 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14229 if (Subtarget->hasInt256()) {
14230 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14232 SmallVector<SDValue,32> pshufbMask;
14233 for (unsigned i = 0; i < 2; ++i) {
14234 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14235 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14236 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14237 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14238 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14239 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14240 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14241 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14242 for (unsigned j = 0; j < 8; ++j)
14243 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14245 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14246 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14247 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14249 static const int ShufMask[] = {0, 2, -1, -1};
14250 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14252 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14253 DAG.getIntPtrConstant(0));
14254 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14257 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14258 DAG.getIntPtrConstant(0));
14260 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14261 DAG.getIntPtrConstant(4));
14263 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14264 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14266 // The PSHUFB mask:
14267 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14268 -1, -1, -1, -1, -1, -1, -1, -1};
14270 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14271 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14272 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14274 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14275 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14277 // The MOVLHPS Mask:
14278 static const int ShufMask2[] = {0, 1, 4, 5};
14279 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14280 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14283 // Handle truncation of V256 to V128 using shuffles.
14284 if (!VT.is128BitVector() || !InVT.is256BitVector())
14287 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14289 unsigned NumElems = VT.getVectorNumElements();
14290 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14292 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14293 // Prepare truncation shuffle mask
14294 for (unsigned i = 0; i != NumElems; ++i)
14295 MaskVec[i] = i * 2;
14296 SDValue V = DAG.getVectorShuffle(NVT, DL,
14297 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14298 DAG.getUNDEF(NVT), &MaskVec[0]);
14299 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14300 DAG.getIntPtrConstant(0));
14303 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14304 SelectionDAG &DAG) const {
14305 assert(!Op.getSimpleValueType().isVector());
14307 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14308 /*IsSigned=*/ true, /*IsReplace=*/ false);
14309 SDValue FIST = Vals.first, StackSlot = Vals.second;
14310 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14311 if (!FIST.getNode()) return Op;
14313 if (StackSlot.getNode())
14314 // Load the result.
14315 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14316 FIST, StackSlot, MachinePointerInfo(),
14317 false, false, false, 0);
14319 // The node is the result.
14323 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14324 SelectionDAG &DAG) const {
14325 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14326 /*IsSigned=*/ false, /*IsReplace=*/ false);
14327 SDValue FIST = Vals.first, StackSlot = Vals.second;
14328 assert(FIST.getNode() && "Unexpected failure");
14330 if (StackSlot.getNode())
14331 // Load the result.
14332 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14333 FIST, StackSlot, MachinePointerInfo(),
14334 false, false, false, 0);
14336 // The node is the result.
14340 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14342 MVT VT = Op.getSimpleValueType();
14343 SDValue In = Op.getOperand(0);
14344 MVT SVT = In.getSimpleValueType();
14346 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14348 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14349 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14350 In, DAG.getUNDEF(SVT)));
14353 /// The only differences between FABS and FNEG are the mask and the logic op.
14354 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14355 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14356 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14357 "Wrong opcode for lowering FABS or FNEG.");
14359 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14361 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14362 // into an FNABS. We'll lower the FABS after that if it is still in use.
14364 for (SDNode *User : Op->uses())
14365 if (User->getOpcode() == ISD::FNEG)
14368 SDValue Op0 = Op.getOperand(0);
14369 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14372 MVT VT = Op.getSimpleValueType();
14373 // Assume scalar op for initialization; update for vector if needed.
14374 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14375 // generate a 16-byte vector constant and logic op even for the scalar case.
14376 // Using a 16-byte mask allows folding the load of the mask with
14377 // the logic op, so it can save (~4 bytes) on code size.
14379 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14380 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14381 // decide if we should generate a 16-byte constant mask when we only need 4 or
14382 // 8 bytes for the scalar case.
14383 if (VT.isVector()) {
14384 EltVT = VT.getVectorElementType();
14385 NumElts = VT.getVectorNumElements();
14388 unsigned EltBits = EltVT.getSizeInBits();
14389 LLVMContext *Context = DAG.getContext();
14390 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14392 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14393 Constant *C = ConstantInt::get(*Context, MaskElt);
14394 C = ConstantVector::getSplat(NumElts, C);
14395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14396 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14397 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14398 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14399 MachinePointerInfo::getConstantPool(),
14400 false, false, false, Alignment);
14402 if (VT.isVector()) {
14403 // For a vector, cast operands to a vector type, perform the logic op,
14404 // and cast the result back to the original value type.
14405 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14406 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14407 SDValue Operand = IsFNABS ?
14408 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14409 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14410 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14411 return DAG.getNode(ISD::BITCAST, dl, VT,
14412 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14415 // If not vector, then scalar.
14416 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14417 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14418 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14421 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14423 LLVMContext *Context = DAG.getContext();
14424 SDValue Op0 = Op.getOperand(0);
14425 SDValue Op1 = Op.getOperand(1);
14427 MVT VT = Op.getSimpleValueType();
14428 MVT SrcVT = Op1.getSimpleValueType();
14430 // If second operand is smaller, extend it first.
14431 if (SrcVT.bitsLT(VT)) {
14432 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14435 // And if it is bigger, shrink it first.
14436 if (SrcVT.bitsGT(VT)) {
14437 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14441 // At this point the operands and the result should have the same
14442 // type, and that won't be f80 since that is not custom lowered.
14444 // First get the sign bit of second operand.
14445 SmallVector<Constant*,4> CV;
14446 if (SrcVT == MVT::f64) {
14447 const fltSemantics &Sem = APFloat::IEEEdouble;
14448 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14449 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14451 const fltSemantics &Sem = APFloat::IEEEsingle;
14452 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14453 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14454 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14455 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14457 Constant *C = ConstantVector::get(CV);
14458 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14459 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14460 MachinePointerInfo::getConstantPool(),
14461 false, false, false, 16);
14462 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14464 // Shift sign bit right or left if the two operands have different types.
14465 if (SrcVT.bitsGT(VT)) {
14466 // Op0 is MVT::f32, Op1 is MVT::f64.
14467 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14468 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14469 DAG.getConstant(32, MVT::i32));
14470 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14471 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14472 DAG.getIntPtrConstant(0));
14475 // Clear first operand sign bit.
14477 if (VT == MVT::f64) {
14478 const fltSemantics &Sem = APFloat::IEEEdouble;
14479 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14480 APInt(64, ~(1ULL << 63)))));
14481 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14483 const fltSemantics &Sem = APFloat::IEEEsingle;
14484 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14485 APInt(32, ~(1U << 31)))));
14486 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14487 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14488 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14490 C = ConstantVector::get(CV);
14491 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14492 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14493 MachinePointerInfo::getConstantPool(),
14494 false, false, false, 16);
14495 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14497 // Or the value with the sign bit.
14498 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14501 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14502 SDValue N0 = Op.getOperand(0);
14504 MVT VT = Op.getSimpleValueType();
14506 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14507 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14508 DAG.getConstant(1, VT));
14509 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14512 // Check whether an OR'd tree is PTEST-able.
14513 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14514 SelectionDAG &DAG) {
14515 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14517 if (!Subtarget->hasSSE41())
14520 if (!Op->hasOneUse())
14523 SDNode *N = Op.getNode();
14526 SmallVector<SDValue, 8> Opnds;
14527 DenseMap<SDValue, unsigned> VecInMap;
14528 SmallVector<SDValue, 8> VecIns;
14529 EVT VT = MVT::Other;
14531 // Recognize a special case where a vector is casted into wide integer to
14533 Opnds.push_back(N->getOperand(0));
14534 Opnds.push_back(N->getOperand(1));
14536 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14537 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14538 // BFS traverse all OR'd operands.
14539 if (I->getOpcode() == ISD::OR) {
14540 Opnds.push_back(I->getOperand(0));
14541 Opnds.push_back(I->getOperand(1));
14542 // Re-evaluate the number of nodes to be traversed.
14543 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14547 // Quit if a non-EXTRACT_VECTOR_ELT
14548 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14551 // Quit if without a constant index.
14552 SDValue Idx = I->getOperand(1);
14553 if (!isa<ConstantSDNode>(Idx))
14556 SDValue ExtractedFromVec = I->getOperand(0);
14557 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14558 if (M == VecInMap.end()) {
14559 VT = ExtractedFromVec.getValueType();
14560 // Quit if not 128/256-bit vector.
14561 if (!VT.is128BitVector() && !VT.is256BitVector())
14563 // Quit if not the same type.
14564 if (VecInMap.begin() != VecInMap.end() &&
14565 VT != VecInMap.begin()->first.getValueType())
14567 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14568 VecIns.push_back(ExtractedFromVec);
14570 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14573 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14574 "Not extracted from 128-/256-bit vector.");
14576 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14578 for (DenseMap<SDValue, unsigned>::const_iterator
14579 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14580 // Quit if not all elements are used.
14581 if (I->second != FullMask)
14585 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14587 // Cast all vectors into TestVT for PTEST.
14588 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14589 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14591 // If more than one full vectors are evaluated, OR them first before PTEST.
14592 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14593 // Each iteration will OR 2 nodes and append the result until there is only
14594 // 1 node left, i.e. the final OR'd value of all vectors.
14595 SDValue LHS = VecIns[Slot];
14596 SDValue RHS = VecIns[Slot + 1];
14597 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14600 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14601 VecIns.back(), VecIns.back());
14604 /// \brief return true if \c Op has a use that doesn't just read flags.
14605 static bool hasNonFlagsUse(SDValue Op) {
14606 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14608 SDNode *User = *UI;
14609 unsigned UOpNo = UI.getOperandNo();
14610 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14611 // Look pass truncate.
14612 UOpNo = User->use_begin().getOperandNo();
14613 User = *User->use_begin();
14616 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14617 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14623 /// Emit nodes that will be selected as "test Op0,Op0", or something
14625 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14626 SelectionDAG &DAG) const {
14627 if (Op.getValueType() == MVT::i1)
14628 // KORTEST instruction should be selected
14629 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14630 DAG.getConstant(0, Op.getValueType()));
14632 // CF and OF aren't always set the way we want. Determine which
14633 // of these we need.
14634 bool NeedCF = false;
14635 bool NeedOF = false;
14638 case X86::COND_A: case X86::COND_AE:
14639 case X86::COND_B: case X86::COND_BE:
14642 case X86::COND_G: case X86::COND_GE:
14643 case X86::COND_L: case X86::COND_LE:
14644 case X86::COND_O: case X86::COND_NO: {
14645 // Check if we really need to set the
14646 // Overflow flag. If NoSignedWrap is present
14647 // that is not actually needed.
14648 switch (Op->getOpcode()) {
14653 const BinaryWithFlagsSDNode *BinNode =
14654 cast<BinaryWithFlagsSDNode>(Op.getNode());
14655 if (BinNode->hasNoSignedWrap())
14665 // See if we can use the EFLAGS value from the operand instead of
14666 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14667 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14668 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14669 // Emit a CMP with 0, which is the TEST pattern.
14670 //if (Op.getValueType() == MVT::i1)
14671 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14672 // DAG.getConstant(0, MVT::i1));
14673 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14674 DAG.getConstant(0, Op.getValueType()));
14676 unsigned Opcode = 0;
14677 unsigned NumOperands = 0;
14679 // Truncate operations may prevent the merge of the SETCC instruction
14680 // and the arithmetic instruction before it. Attempt to truncate the operands
14681 // of the arithmetic instruction and use a reduced bit-width instruction.
14682 bool NeedTruncation = false;
14683 SDValue ArithOp = Op;
14684 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14685 SDValue Arith = Op->getOperand(0);
14686 // Both the trunc and the arithmetic op need to have one user each.
14687 if (Arith->hasOneUse())
14688 switch (Arith.getOpcode()) {
14695 NeedTruncation = true;
14701 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14702 // which may be the result of a CAST. We use the variable 'Op', which is the
14703 // non-casted variable when we check for possible users.
14704 switch (ArithOp.getOpcode()) {
14706 // Due to an isel shortcoming, be conservative if this add is likely to be
14707 // selected as part of a load-modify-store instruction. When the root node
14708 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14709 // uses of other nodes in the match, such as the ADD in this case. This
14710 // leads to the ADD being left around and reselected, with the result being
14711 // two adds in the output. Alas, even if none our users are stores, that
14712 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14713 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14714 // climbing the DAG back to the root, and it doesn't seem to be worth the
14716 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14717 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14718 if (UI->getOpcode() != ISD::CopyToReg &&
14719 UI->getOpcode() != ISD::SETCC &&
14720 UI->getOpcode() != ISD::STORE)
14723 if (ConstantSDNode *C =
14724 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14725 // An add of one will be selected as an INC.
14726 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14727 Opcode = X86ISD::INC;
14732 // An add of negative one (subtract of one) will be selected as a DEC.
14733 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14734 Opcode = X86ISD::DEC;
14740 // Otherwise use a regular EFLAGS-setting add.
14741 Opcode = X86ISD::ADD;
14746 // If we have a constant logical shift that's only used in a comparison
14747 // against zero turn it into an equivalent AND. This allows turning it into
14748 // a TEST instruction later.
14749 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14750 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14751 EVT VT = Op.getValueType();
14752 unsigned BitWidth = VT.getSizeInBits();
14753 unsigned ShAmt = Op->getConstantOperandVal(1);
14754 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14756 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14757 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14758 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14759 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14761 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14762 DAG.getConstant(Mask, VT));
14763 DAG.ReplaceAllUsesWith(Op, New);
14769 // If the primary and result isn't used, don't bother using X86ISD::AND,
14770 // because a TEST instruction will be better.
14771 if (!hasNonFlagsUse(Op))
14777 // Due to the ISEL shortcoming noted above, be conservative if this op is
14778 // likely to be selected as part of a load-modify-store instruction.
14779 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14780 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14781 if (UI->getOpcode() == ISD::STORE)
14784 // Otherwise use a regular EFLAGS-setting instruction.
14785 switch (ArithOp.getOpcode()) {
14786 default: llvm_unreachable("unexpected operator!");
14787 case ISD::SUB: Opcode = X86ISD::SUB; break;
14788 case ISD::XOR: Opcode = X86ISD::XOR; break;
14789 case ISD::AND: Opcode = X86ISD::AND; break;
14791 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14792 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14793 if (EFLAGS.getNode())
14796 Opcode = X86ISD::OR;
14810 return SDValue(Op.getNode(), 1);
14816 // If we found that truncation is beneficial, perform the truncation and
14818 if (NeedTruncation) {
14819 EVT VT = Op.getValueType();
14820 SDValue WideVal = Op->getOperand(0);
14821 EVT WideVT = WideVal.getValueType();
14822 unsigned ConvertedOp = 0;
14823 // Use a target machine opcode to prevent further DAGCombine
14824 // optimizations that may separate the arithmetic operations
14825 // from the setcc node.
14826 switch (WideVal.getOpcode()) {
14828 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14829 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14830 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14831 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14832 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14837 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14838 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14839 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14840 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14846 // Emit a CMP with 0, which is the TEST pattern.
14847 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14848 DAG.getConstant(0, Op.getValueType()));
14850 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14851 SmallVector<SDValue, 4> Ops;
14852 for (unsigned i = 0; i != NumOperands; ++i)
14853 Ops.push_back(Op.getOperand(i));
14855 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14856 DAG.ReplaceAllUsesWith(Op, New);
14857 return SDValue(New.getNode(), 1);
14860 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14862 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14863 SDLoc dl, SelectionDAG &DAG) const {
14864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14865 if (C->getAPIntValue() == 0)
14866 return EmitTest(Op0, X86CC, dl, DAG);
14868 if (Op0.getValueType() == MVT::i1)
14869 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14872 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14873 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14874 // Do the comparison at i32 if it's smaller, besides the Atom case.
14875 // This avoids subregister aliasing issues. Keep the smaller reference
14876 // if we're optimizing for size, however, as that'll allow better folding
14877 // of memory operations.
14878 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14879 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14880 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14881 !Subtarget->isAtom()) {
14882 unsigned ExtendOp =
14883 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14884 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14885 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14887 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14888 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14889 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14891 return SDValue(Sub.getNode(), 1);
14893 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14896 /// Convert a comparison if required by the subtarget.
14897 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14898 SelectionDAG &DAG) const {
14899 // If the subtarget does not support the FUCOMI instruction, floating-point
14900 // comparisons have to be converted.
14901 if (Subtarget->hasCMov() ||
14902 Cmp.getOpcode() != X86ISD::CMP ||
14903 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14904 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14907 // The instruction selector will select an FUCOM instruction instead of
14908 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14909 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14910 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14912 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14913 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14914 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14915 DAG.getConstant(8, MVT::i8));
14916 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14917 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14920 /// The minimum architected relative accuracy is 2^-12. We need one
14921 /// Newton-Raphson step to have a good float result (24 bits of precision).
14922 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14923 DAGCombinerInfo &DCI,
14924 unsigned &RefinementSteps,
14925 bool &UseOneConstNR) const {
14926 // FIXME: We should use instruction latency models to calculate the cost of
14927 // each potential sequence, but this is very hard to do reliably because
14928 // at least Intel's Core* chips have variable timing based on the number of
14929 // significant digits in the divisor and/or sqrt operand.
14930 if (!Subtarget->useSqrtEst())
14933 EVT VT = Op.getValueType();
14935 // SSE1 has rsqrtss and rsqrtps.
14936 // TODO: Add support for AVX512 (v16f32).
14937 // It is likely not profitable to do this for f64 because a double-precision
14938 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14939 // instructions: convert to single, rsqrtss, convert back to double, refine
14940 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14941 // along with FMA, this could be a throughput win.
14942 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14943 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14944 RefinementSteps = 1;
14945 UseOneConstNR = false;
14946 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14951 /// The minimum architected relative accuracy is 2^-12. We need one
14952 /// Newton-Raphson step to have a good float result (24 bits of precision).
14953 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14954 DAGCombinerInfo &DCI,
14955 unsigned &RefinementSteps) const {
14956 // FIXME: We should use instruction latency models to calculate the cost of
14957 // each potential sequence, but this is very hard to do reliably because
14958 // at least Intel's Core* chips have variable timing based on the number of
14959 // significant digits in the divisor.
14960 if (!Subtarget->useReciprocalEst())
14963 EVT VT = Op.getValueType();
14965 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14966 // TODO: Add support for AVX512 (v16f32).
14967 // It is likely not profitable to do this for f64 because a double-precision
14968 // reciprocal estimate with refinement on x86 prior to FMA requires
14969 // 15 instructions: convert to single, rcpss, convert back to double, refine
14970 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14971 // along with FMA, this could be a throughput win.
14972 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14973 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14974 RefinementSteps = ReciprocalEstimateRefinementSteps;
14975 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14980 static bool isAllOnes(SDValue V) {
14981 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14982 return C && C->isAllOnesValue();
14985 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14986 /// if it's possible.
14987 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14988 SDLoc dl, SelectionDAG &DAG) const {
14989 SDValue Op0 = And.getOperand(0);
14990 SDValue Op1 = And.getOperand(1);
14991 if (Op0.getOpcode() == ISD::TRUNCATE)
14992 Op0 = Op0.getOperand(0);
14993 if (Op1.getOpcode() == ISD::TRUNCATE)
14994 Op1 = Op1.getOperand(0);
14997 if (Op1.getOpcode() == ISD::SHL)
14998 std::swap(Op0, Op1);
14999 if (Op0.getOpcode() == ISD::SHL) {
15000 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15001 if (And00C->getZExtValue() == 1) {
15002 // If we looked past a truncate, check that it's only truncating away
15004 unsigned BitWidth = Op0.getValueSizeInBits();
15005 unsigned AndBitWidth = And.getValueSizeInBits();
15006 if (BitWidth > AndBitWidth) {
15008 DAG.computeKnownBits(Op0, Zeros, Ones);
15009 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15013 RHS = Op0.getOperand(1);
15015 } else if (Op1.getOpcode() == ISD::Constant) {
15016 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15017 uint64_t AndRHSVal = AndRHS->getZExtValue();
15018 SDValue AndLHS = Op0;
15020 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15021 LHS = AndLHS.getOperand(0);
15022 RHS = AndLHS.getOperand(1);
15025 // Use BT if the immediate can't be encoded in a TEST instruction.
15026 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15028 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15032 if (LHS.getNode()) {
15033 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15034 // instruction. Since the shift amount is in-range-or-undefined, we know
15035 // that doing a bittest on the i32 value is ok. We extend to i32 because
15036 // the encoding for the i16 version is larger than the i32 version.
15037 // Also promote i16 to i32 for performance / code size reason.
15038 if (LHS.getValueType() == MVT::i8 ||
15039 LHS.getValueType() == MVT::i16)
15040 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15042 // If the operand types disagree, extend the shift amount to match. Since
15043 // BT ignores high bits (like shifts) we can use anyextend.
15044 if (LHS.getValueType() != RHS.getValueType())
15045 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15047 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15048 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15049 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15050 DAG.getConstant(Cond, MVT::i8), BT);
15056 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15058 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15063 // SSE Condition code mapping:
15072 switch (SetCCOpcode) {
15073 default: llvm_unreachable("Unexpected SETCC condition");
15075 case ISD::SETEQ: SSECC = 0; break;
15077 case ISD::SETGT: Swap = true; // Fallthrough
15079 case ISD::SETOLT: SSECC = 1; break;
15081 case ISD::SETGE: Swap = true; // Fallthrough
15083 case ISD::SETOLE: SSECC = 2; break;
15084 case ISD::SETUO: SSECC = 3; break;
15086 case ISD::SETNE: SSECC = 4; break;
15087 case ISD::SETULE: Swap = true; // Fallthrough
15088 case ISD::SETUGE: SSECC = 5; break;
15089 case ISD::SETULT: Swap = true; // Fallthrough
15090 case ISD::SETUGT: SSECC = 6; break;
15091 case ISD::SETO: SSECC = 7; break;
15093 case ISD::SETONE: SSECC = 8; break;
15096 std::swap(Op0, Op1);
15101 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15102 // ones, and then concatenate the result back.
15103 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15104 MVT VT = Op.getSimpleValueType();
15106 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15107 "Unsupported value type for operation");
15109 unsigned NumElems = VT.getVectorNumElements();
15111 SDValue CC = Op.getOperand(2);
15113 // Extract the LHS vectors
15114 SDValue LHS = Op.getOperand(0);
15115 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15116 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15118 // Extract the RHS vectors
15119 SDValue RHS = Op.getOperand(1);
15120 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15121 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15123 // Issue the operation on the smaller types and concatenate the result back
15124 MVT EltVT = VT.getVectorElementType();
15125 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15126 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15127 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15128 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15131 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15132 const X86Subtarget *Subtarget) {
15133 SDValue Op0 = Op.getOperand(0);
15134 SDValue Op1 = Op.getOperand(1);
15135 SDValue CC = Op.getOperand(2);
15136 MVT VT = Op.getSimpleValueType();
15139 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15140 Op.getValueType().getScalarType() == MVT::i1 &&
15141 "Cannot set masked compare for this operation");
15143 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15145 bool Unsigned = false;
15148 switch (SetCCOpcode) {
15149 default: llvm_unreachable("Unexpected SETCC condition");
15150 case ISD::SETNE: SSECC = 4; break;
15151 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15152 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15153 case ISD::SETLT: Swap = true; //fall-through
15154 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15155 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15156 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15157 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15158 case ISD::SETULE: Unsigned = true; //fall-through
15159 case ISD::SETLE: SSECC = 2; break;
15163 std::swap(Op0, Op1);
15165 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15166 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15167 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15168 DAG.getConstant(SSECC, MVT::i8));
15171 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15172 /// operand \p Op1. If non-trivial (for example because it's not constant)
15173 /// return an empty value.
15174 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15176 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15180 MVT VT = Op1.getSimpleValueType();
15181 MVT EVT = VT.getVectorElementType();
15182 unsigned n = VT.getVectorNumElements();
15183 SmallVector<SDValue, 8> ULTOp1;
15185 for (unsigned i = 0; i < n; ++i) {
15186 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15187 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15190 // Avoid underflow.
15191 APInt Val = Elt->getAPIntValue();
15195 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15198 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15201 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15202 SelectionDAG &DAG) {
15203 SDValue Op0 = Op.getOperand(0);
15204 SDValue Op1 = Op.getOperand(1);
15205 SDValue CC = Op.getOperand(2);
15206 MVT VT = Op.getSimpleValueType();
15207 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15208 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15213 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15214 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15217 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15218 unsigned Opc = X86ISD::CMPP;
15219 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15220 assert(VT.getVectorNumElements() <= 16);
15221 Opc = X86ISD::CMPM;
15223 // In the two special cases we can't handle, emit two comparisons.
15226 unsigned CombineOpc;
15227 if (SetCCOpcode == ISD::SETUEQ) {
15228 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15230 assert(SetCCOpcode == ISD::SETONE);
15231 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15234 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15235 DAG.getConstant(CC0, MVT::i8));
15236 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15237 DAG.getConstant(CC1, MVT::i8));
15238 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15240 // Handle all other FP comparisons here.
15241 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15242 DAG.getConstant(SSECC, MVT::i8));
15245 // Break 256-bit integer vector compare into smaller ones.
15246 if (VT.is256BitVector() && !Subtarget->hasInt256())
15247 return Lower256IntVSETCC(Op, DAG);
15249 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15250 EVT OpVT = Op1.getValueType();
15251 if (Subtarget->hasAVX512()) {
15252 if (Op1.getValueType().is512BitVector() ||
15253 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15254 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15255 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15257 // In AVX-512 architecture setcc returns mask with i1 elements,
15258 // But there is no compare instruction for i8 and i16 elements in KNL.
15259 // We are not talking about 512-bit operands in this case, these
15260 // types are illegal.
15262 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15263 OpVT.getVectorElementType().getSizeInBits() >= 8))
15264 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15265 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15268 // We are handling one of the integer comparisons here. Since SSE only has
15269 // GT and EQ comparisons for integer, swapping operands and multiple
15270 // operations may be required for some comparisons.
15272 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15273 bool Subus = false;
15275 switch (SetCCOpcode) {
15276 default: llvm_unreachable("Unexpected SETCC condition");
15277 case ISD::SETNE: Invert = true;
15278 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15279 case ISD::SETLT: Swap = true;
15280 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15281 case ISD::SETGE: Swap = true;
15282 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15283 Invert = true; break;
15284 case ISD::SETULT: Swap = true;
15285 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15286 FlipSigns = true; break;
15287 case ISD::SETUGE: Swap = true;
15288 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15289 FlipSigns = true; Invert = true; break;
15292 // Special case: Use min/max operations for SETULE/SETUGE
15293 MVT VET = VT.getVectorElementType();
15295 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15296 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15299 switch (SetCCOpcode) {
15301 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15302 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15305 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15308 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15309 if (!MinMax && hasSubus) {
15310 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15312 // t = psubus Op0, Op1
15313 // pcmpeq t, <0..0>
15314 switch (SetCCOpcode) {
15316 case ISD::SETULT: {
15317 // If the comparison is against a constant we can turn this into a
15318 // setule. With psubus, setule does not require a swap. This is
15319 // beneficial because the constant in the register is no longer
15320 // destructed as the destination so it can be hoisted out of a loop.
15321 // Only do this pre-AVX since vpcmp* is no longer destructive.
15322 if (Subtarget->hasAVX())
15324 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15325 if (ULEOp1.getNode()) {
15327 Subus = true; Invert = false; Swap = false;
15331 // Psubus is better than flip-sign because it requires no inversion.
15332 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15333 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15337 Opc = X86ISD::SUBUS;
15343 std::swap(Op0, Op1);
15345 // Check that the operation in question is available (most are plain SSE2,
15346 // but PCMPGTQ and PCMPEQQ have different requirements).
15347 if (VT == MVT::v2i64) {
15348 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15349 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15351 // First cast everything to the right type.
15352 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15353 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15355 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15356 // bits of the inputs before performing those operations. The lower
15357 // compare is always unsigned.
15360 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15362 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15363 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15364 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15365 Sign, Zero, Sign, Zero);
15367 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15368 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15370 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15371 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15372 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15374 // Create masks for only the low parts/high parts of the 64 bit integers.
15375 static const int MaskHi[] = { 1, 1, 3, 3 };
15376 static const int MaskLo[] = { 0, 0, 2, 2 };
15377 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15378 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15379 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15381 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15382 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15385 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15387 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15390 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15391 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15392 // pcmpeqd + pshufd + pand.
15393 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15395 // First cast everything to the right type.
15396 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15397 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15400 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15402 // Make sure the lower and upper halves are both all-ones.
15403 static const int Mask[] = { 1, 0, 3, 2 };
15404 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15405 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15408 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15410 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15414 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15415 // bits of the inputs before performing those operations.
15417 EVT EltVT = VT.getVectorElementType();
15418 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15419 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15420 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15423 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15425 // If the logical-not of the result is required, perform that now.
15427 Result = DAG.getNOT(dl, Result, VT);
15430 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15433 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15434 getZeroVector(VT, Subtarget, DAG, dl));
15439 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15441 MVT VT = Op.getSimpleValueType();
15443 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15445 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15446 && "SetCC type must be 8-bit or 1-bit integer");
15447 SDValue Op0 = Op.getOperand(0);
15448 SDValue Op1 = Op.getOperand(1);
15450 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15452 // Optimize to BT if possible.
15453 // Lower (X & (1 << N)) == 0 to BT(X, N).
15454 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15455 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15456 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15457 Op1.getOpcode() == ISD::Constant &&
15458 cast<ConstantSDNode>(Op1)->isNullValue() &&
15459 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15460 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15461 if (NewSetCC.getNode())
15465 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15467 if (Op1.getOpcode() == ISD::Constant &&
15468 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15469 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15470 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15472 // If the input is a setcc, then reuse the input setcc or use a new one with
15473 // the inverted condition.
15474 if (Op0.getOpcode() == X86ISD::SETCC) {
15475 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15476 bool Invert = (CC == ISD::SETNE) ^
15477 cast<ConstantSDNode>(Op1)->isNullValue();
15481 CCode = X86::GetOppositeBranchCondition(CCode);
15482 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15483 DAG.getConstant(CCode, MVT::i8),
15484 Op0.getOperand(1));
15486 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15490 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15491 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15492 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15494 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15495 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15498 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15499 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15500 if (X86CC == X86::COND_INVALID)
15503 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15504 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15505 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15506 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15508 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15512 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15513 static bool isX86LogicalCmp(SDValue Op) {
15514 unsigned Opc = Op.getNode()->getOpcode();
15515 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15516 Opc == X86ISD::SAHF)
15518 if (Op.getResNo() == 1 &&
15519 (Opc == X86ISD::ADD ||
15520 Opc == X86ISD::SUB ||
15521 Opc == X86ISD::ADC ||
15522 Opc == X86ISD::SBB ||
15523 Opc == X86ISD::SMUL ||
15524 Opc == X86ISD::UMUL ||
15525 Opc == X86ISD::INC ||
15526 Opc == X86ISD::DEC ||
15527 Opc == X86ISD::OR ||
15528 Opc == X86ISD::XOR ||
15529 Opc == X86ISD::AND))
15532 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15538 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15539 if (V.getOpcode() != ISD::TRUNCATE)
15542 SDValue VOp0 = V.getOperand(0);
15543 unsigned InBits = VOp0.getValueSizeInBits();
15544 unsigned Bits = V.getValueSizeInBits();
15545 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15548 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15549 bool addTest = true;
15550 SDValue Cond = Op.getOperand(0);
15551 SDValue Op1 = Op.getOperand(1);
15552 SDValue Op2 = Op.getOperand(2);
15554 EVT VT = Op1.getValueType();
15557 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15558 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15559 // sequence later on.
15560 if (Cond.getOpcode() == ISD::SETCC &&
15561 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15562 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15563 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15564 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15565 int SSECC = translateX86FSETCC(
15566 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15569 if (Subtarget->hasAVX512()) {
15570 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15571 DAG.getConstant(SSECC, MVT::i8));
15572 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15574 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15575 DAG.getConstant(SSECC, MVT::i8));
15576 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15577 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15578 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15582 if (Cond.getOpcode() == ISD::SETCC) {
15583 SDValue NewCond = LowerSETCC(Cond, DAG);
15584 if (NewCond.getNode())
15588 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15589 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15590 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15591 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15592 if (Cond.getOpcode() == X86ISD::SETCC &&
15593 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15594 isZero(Cond.getOperand(1).getOperand(1))) {
15595 SDValue Cmp = Cond.getOperand(1);
15597 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15599 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15600 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15601 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15603 SDValue CmpOp0 = Cmp.getOperand(0);
15604 // Apply further optimizations for special cases
15605 // (select (x != 0), -1, 0) -> neg & sbb
15606 // (select (x == 0), 0, -1) -> neg & sbb
15607 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15608 if (YC->isNullValue() &&
15609 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15610 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15611 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15612 DAG.getConstant(0, CmpOp0.getValueType()),
15614 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15615 DAG.getConstant(X86::COND_B, MVT::i8),
15616 SDValue(Neg.getNode(), 1));
15620 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15621 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15622 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15624 SDValue Res = // Res = 0 or -1.
15625 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15626 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15628 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15629 Res = DAG.getNOT(DL, Res, Res.getValueType());
15631 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15632 if (!N2C || !N2C->isNullValue())
15633 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15638 // Look past (and (setcc_carry (cmp ...)), 1).
15639 if (Cond.getOpcode() == ISD::AND &&
15640 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15641 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15642 if (C && C->getAPIntValue() == 1)
15643 Cond = Cond.getOperand(0);
15646 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15647 // setting operand in place of the X86ISD::SETCC.
15648 unsigned CondOpcode = Cond.getOpcode();
15649 if (CondOpcode == X86ISD::SETCC ||
15650 CondOpcode == X86ISD::SETCC_CARRY) {
15651 CC = Cond.getOperand(0);
15653 SDValue Cmp = Cond.getOperand(1);
15654 unsigned Opc = Cmp.getOpcode();
15655 MVT VT = Op.getSimpleValueType();
15657 bool IllegalFPCMov = false;
15658 if (VT.isFloatingPoint() && !VT.isVector() &&
15659 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15660 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15662 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15663 Opc == X86ISD::BT) { // FIXME
15667 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15668 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15669 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15670 Cond.getOperand(0).getValueType() != MVT::i8)) {
15671 SDValue LHS = Cond.getOperand(0);
15672 SDValue RHS = Cond.getOperand(1);
15673 unsigned X86Opcode;
15676 switch (CondOpcode) {
15677 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15678 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15679 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15680 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15681 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15682 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15683 default: llvm_unreachable("unexpected overflowing operator");
15685 if (CondOpcode == ISD::UMULO)
15686 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15689 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15691 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15693 if (CondOpcode == ISD::UMULO)
15694 Cond = X86Op.getValue(2);
15696 Cond = X86Op.getValue(1);
15698 CC = DAG.getConstant(X86Cond, MVT::i8);
15703 // Look pass the truncate if the high bits are known zero.
15704 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15705 Cond = Cond.getOperand(0);
15707 // We know the result of AND is compared against zero. Try to match
15709 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15710 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15711 if (NewSetCC.getNode()) {
15712 CC = NewSetCC.getOperand(0);
15713 Cond = NewSetCC.getOperand(1);
15720 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15721 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15724 // a < b ? -1 : 0 -> RES = ~setcc_carry
15725 // a < b ? 0 : -1 -> RES = setcc_carry
15726 // a >= b ? -1 : 0 -> RES = setcc_carry
15727 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15728 if (Cond.getOpcode() == X86ISD::SUB) {
15729 Cond = ConvertCmpIfNecessary(Cond, DAG);
15730 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15732 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15733 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15734 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15735 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15736 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15737 return DAG.getNOT(DL, Res, Res.getValueType());
15742 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15743 // widen the cmov and push the truncate through. This avoids introducing a new
15744 // branch during isel and doesn't add any extensions.
15745 if (Op.getValueType() == MVT::i8 &&
15746 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15747 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15748 if (T1.getValueType() == T2.getValueType() &&
15749 // Blacklist CopyFromReg to avoid partial register stalls.
15750 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15751 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15752 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15753 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15757 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15758 // condition is true.
15759 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15760 SDValue Ops[] = { Op2, Op1, CC, Cond };
15761 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15764 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15765 SelectionDAG &DAG) {
15766 MVT VT = Op->getSimpleValueType(0);
15767 SDValue In = Op->getOperand(0);
15768 MVT InVT = In.getSimpleValueType();
15769 MVT VTElt = VT.getVectorElementType();
15770 MVT InVTElt = InVT.getVectorElementType();
15774 if ((InVTElt == MVT::i1) &&
15775 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15776 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15778 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15779 VTElt.getSizeInBits() <= 16)) ||
15781 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15782 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15784 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15785 VTElt.getSizeInBits() >= 32))))
15786 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15788 unsigned int NumElts = VT.getVectorNumElements();
15790 if (NumElts != 8 && NumElts != 16)
15793 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15794 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15795 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15796 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15800 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15802 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15803 Constant *C = ConstantInt::get(*DAG.getContext(),
15804 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15806 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15807 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15808 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15809 MachinePointerInfo::getConstantPool(),
15810 false, false, false, Alignment);
15811 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15812 if (VT.is512BitVector())
15814 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15817 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15818 SelectionDAG &DAG) {
15819 MVT VT = Op->getSimpleValueType(0);
15820 SDValue In = Op->getOperand(0);
15821 MVT InVT = In.getSimpleValueType();
15824 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15825 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15827 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15828 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15829 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15832 if (Subtarget->hasInt256())
15833 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15835 // Optimize vectors in AVX mode
15836 // Sign extend v8i16 to v8i32 and
15839 // Divide input vector into two parts
15840 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15841 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15842 // concat the vectors to original VT
15844 unsigned NumElems = InVT.getVectorNumElements();
15845 SDValue Undef = DAG.getUNDEF(InVT);
15847 SmallVector<int,8> ShufMask1(NumElems, -1);
15848 for (unsigned i = 0; i != NumElems/2; ++i)
15851 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15853 SmallVector<int,8> ShufMask2(NumElems, -1);
15854 for (unsigned i = 0; i != NumElems/2; ++i)
15855 ShufMask2[i] = i + NumElems/2;
15857 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15859 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15860 VT.getVectorNumElements()/2);
15862 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15863 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15865 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15868 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15869 // may emit an illegal shuffle but the expansion is still better than scalar
15870 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15871 // we'll emit a shuffle and a arithmetic shift.
15872 // TODO: It is possible to support ZExt by zeroing the undef values during
15873 // the shuffle phase or after the shuffle.
15874 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15875 SelectionDAG &DAG) {
15876 MVT RegVT = Op.getSimpleValueType();
15877 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15878 assert(RegVT.isInteger() &&
15879 "We only custom lower integer vector sext loads.");
15881 // Nothing useful we can do without SSE2 shuffles.
15882 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15884 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15886 EVT MemVT = Ld->getMemoryVT();
15887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15888 unsigned RegSz = RegVT.getSizeInBits();
15890 ISD::LoadExtType Ext = Ld->getExtensionType();
15892 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15893 && "Only anyext and sext are currently implemented.");
15894 assert(MemVT != RegVT && "Cannot extend to the same type");
15895 assert(MemVT.isVector() && "Must load a vector from memory");
15897 unsigned NumElems = RegVT.getVectorNumElements();
15898 unsigned MemSz = MemVT.getSizeInBits();
15899 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15901 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15902 // The only way in which we have a legal 256-bit vector result but not the
15903 // integer 256-bit operations needed to directly lower a sextload is if we
15904 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15905 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15906 // correctly legalized. We do this late to allow the canonical form of
15907 // sextload to persist throughout the rest of the DAG combiner -- it wants
15908 // to fold together any extensions it can, and so will fuse a sign_extend
15909 // of an sextload into a sextload targeting a wider value.
15911 if (MemSz == 128) {
15912 // Just switch this to a normal load.
15913 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15914 "it must be a legal 128-bit vector "
15916 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15917 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15918 Ld->isInvariant(), Ld->getAlignment());
15920 assert(MemSz < 128 &&
15921 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15922 // Do an sext load to a 128-bit vector type. We want to use the same
15923 // number of elements, but elements half as wide. This will end up being
15924 // recursively lowered by this routine, but will succeed as we definitely
15925 // have all the necessary features if we're using AVX1.
15927 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15928 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15930 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15931 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15932 Ld->isNonTemporal(), Ld->isInvariant(),
15933 Ld->getAlignment());
15936 // Replace chain users with the new chain.
15937 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15938 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15940 // Finally, do a normal sign-extend to the desired register.
15941 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15944 // All sizes must be a power of two.
15945 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15946 "Non-power-of-two elements are not custom lowered!");
15948 // Attempt to load the original value using scalar loads.
15949 // Find the largest scalar type that divides the total loaded size.
15950 MVT SclrLoadTy = MVT::i8;
15951 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15952 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15953 MVT Tp = (MVT::SimpleValueType)tp;
15954 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15959 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15960 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15962 SclrLoadTy = MVT::f64;
15964 // Calculate the number of scalar loads that we need to perform
15965 // in order to load our vector from memory.
15966 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15968 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15969 "Can only lower sext loads with a single scalar load!");
15971 unsigned loadRegZize = RegSz;
15972 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15975 // Represent our vector as a sequence of elements which are the
15976 // largest scalar that we can load.
15977 EVT LoadUnitVecVT = EVT::getVectorVT(
15978 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15980 // Represent the data using the same element type that is stored in
15981 // memory. In practice, we ''widen'' MemVT.
15983 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15984 loadRegZize / MemVT.getScalarType().getSizeInBits());
15986 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15987 "Invalid vector type");
15989 // We can't shuffle using an illegal type.
15990 assert(TLI.isTypeLegal(WideVecVT) &&
15991 "We only lower types that form legal widened vector types");
15993 SmallVector<SDValue, 8> Chains;
15994 SDValue Ptr = Ld->getBasePtr();
15995 SDValue Increment =
15996 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15997 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15999 for (unsigned i = 0; i < NumLoads; ++i) {
16000 // Perform a single load.
16001 SDValue ScalarLoad =
16002 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16003 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16004 Ld->getAlignment());
16005 Chains.push_back(ScalarLoad.getValue(1));
16006 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16007 // another round of DAGCombining.
16009 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16011 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16012 ScalarLoad, DAG.getIntPtrConstant(i));
16014 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16017 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16019 // Bitcast the loaded value to a vector of the original element type, in
16020 // the size of the target vector type.
16021 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16022 unsigned SizeRatio = RegSz / MemSz;
16024 if (Ext == ISD::SEXTLOAD) {
16025 // If we have SSE4.1, we can directly emit a VSEXT node.
16026 if (Subtarget->hasSSE41()) {
16027 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16028 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16032 // Otherwise we'll shuffle the small elements in the high bits of the
16033 // larger type and perform an arithmetic shift. If the shift is not legal
16034 // it's better to scalarize.
16035 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16036 "We can't implement a sext load without an arithmetic right shift!");
16038 // Redistribute the loaded elements into the different locations.
16039 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16040 for (unsigned i = 0; i != NumElems; ++i)
16041 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16043 SDValue Shuff = DAG.getVectorShuffle(
16044 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16046 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16048 // Build the arithmetic shift.
16049 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16050 MemVT.getVectorElementType().getSizeInBits();
16052 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16054 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16058 // Redistribute the loaded elements into the different locations.
16059 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16060 for (unsigned i = 0; i != NumElems; ++i)
16061 ShuffleVec[i * SizeRatio] = i;
16063 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16064 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16066 // Bitcast to the requested type.
16067 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16068 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16072 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16073 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16074 // from the AND / OR.
16075 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16076 Opc = Op.getOpcode();
16077 if (Opc != ISD::OR && Opc != ISD::AND)
16079 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16080 Op.getOperand(0).hasOneUse() &&
16081 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16082 Op.getOperand(1).hasOneUse());
16085 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16086 // 1 and that the SETCC node has a single use.
16087 static bool isXor1OfSetCC(SDValue Op) {
16088 if (Op.getOpcode() != ISD::XOR)
16090 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16091 if (N1C && N1C->getAPIntValue() == 1) {
16092 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16093 Op.getOperand(0).hasOneUse();
16098 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16099 bool addTest = true;
16100 SDValue Chain = Op.getOperand(0);
16101 SDValue Cond = Op.getOperand(1);
16102 SDValue Dest = Op.getOperand(2);
16105 bool Inverted = false;
16107 if (Cond.getOpcode() == ISD::SETCC) {
16108 // Check for setcc([su]{add,sub,mul}o == 0).
16109 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16110 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16111 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16112 Cond.getOperand(0).getResNo() == 1 &&
16113 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16114 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16115 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16116 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16117 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16118 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16120 Cond = Cond.getOperand(0);
16122 SDValue NewCond = LowerSETCC(Cond, DAG);
16123 if (NewCond.getNode())
16128 // FIXME: LowerXALUO doesn't handle these!!
16129 else if (Cond.getOpcode() == X86ISD::ADD ||
16130 Cond.getOpcode() == X86ISD::SUB ||
16131 Cond.getOpcode() == X86ISD::SMUL ||
16132 Cond.getOpcode() == X86ISD::UMUL)
16133 Cond = LowerXALUO(Cond, DAG);
16136 // Look pass (and (setcc_carry (cmp ...)), 1).
16137 if (Cond.getOpcode() == ISD::AND &&
16138 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16139 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16140 if (C && C->getAPIntValue() == 1)
16141 Cond = Cond.getOperand(0);
16144 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16145 // setting operand in place of the X86ISD::SETCC.
16146 unsigned CondOpcode = Cond.getOpcode();
16147 if (CondOpcode == X86ISD::SETCC ||
16148 CondOpcode == X86ISD::SETCC_CARRY) {
16149 CC = Cond.getOperand(0);
16151 SDValue Cmp = Cond.getOperand(1);
16152 unsigned Opc = Cmp.getOpcode();
16153 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16154 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16158 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16162 // These can only come from an arithmetic instruction with overflow,
16163 // e.g. SADDO, UADDO.
16164 Cond = Cond.getNode()->getOperand(1);
16170 CondOpcode = Cond.getOpcode();
16171 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16172 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16173 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16174 Cond.getOperand(0).getValueType() != MVT::i8)) {
16175 SDValue LHS = Cond.getOperand(0);
16176 SDValue RHS = Cond.getOperand(1);
16177 unsigned X86Opcode;
16180 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16181 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16183 switch (CondOpcode) {
16184 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16186 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16188 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16191 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16192 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16194 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16196 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16199 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16200 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16201 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16202 default: llvm_unreachable("unexpected overflowing operator");
16205 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16206 if (CondOpcode == ISD::UMULO)
16207 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16210 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16212 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16214 if (CondOpcode == ISD::UMULO)
16215 Cond = X86Op.getValue(2);
16217 Cond = X86Op.getValue(1);
16219 CC = DAG.getConstant(X86Cond, MVT::i8);
16223 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16224 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16225 if (CondOpc == ISD::OR) {
16226 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16227 // two branches instead of an explicit OR instruction with a
16229 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16230 isX86LogicalCmp(Cmp)) {
16231 CC = Cond.getOperand(0).getOperand(0);
16232 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16233 Chain, Dest, CC, Cmp);
16234 CC = Cond.getOperand(1).getOperand(0);
16238 } else { // ISD::AND
16239 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16240 // two branches instead of an explicit AND instruction with a
16241 // separate test. However, we only do this if this block doesn't
16242 // have a fall-through edge, because this requires an explicit
16243 // jmp when the condition is false.
16244 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16245 isX86LogicalCmp(Cmp) &&
16246 Op.getNode()->hasOneUse()) {
16247 X86::CondCode CCode =
16248 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16249 CCode = X86::GetOppositeBranchCondition(CCode);
16250 CC = DAG.getConstant(CCode, MVT::i8);
16251 SDNode *User = *Op.getNode()->use_begin();
16252 // Look for an unconditional branch following this conditional branch.
16253 // We need this because we need to reverse the successors in order
16254 // to implement FCMP_OEQ.
16255 if (User->getOpcode() == ISD::BR) {
16256 SDValue FalseBB = User->getOperand(1);
16258 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16259 assert(NewBR == User);
16263 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16264 Chain, Dest, CC, Cmp);
16265 X86::CondCode CCode =
16266 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16267 CCode = X86::GetOppositeBranchCondition(CCode);
16268 CC = DAG.getConstant(CCode, MVT::i8);
16274 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16275 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16276 // It should be transformed during dag combiner except when the condition
16277 // is set by a arithmetics with overflow node.
16278 X86::CondCode CCode =
16279 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16280 CCode = X86::GetOppositeBranchCondition(CCode);
16281 CC = DAG.getConstant(CCode, MVT::i8);
16282 Cond = Cond.getOperand(0).getOperand(1);
16284 } else if (Cond.getOpcode() == ISD::SETCC &&
16285 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16286 // For FCMP_OEQ, we can emit
16287 // two branches instead of an explicit AND instruction with a
16288 // separate test. However, we only do this if this block doesn't
16289 // have a fall-through edge, because this requires an explicit
16290 // jmp when the condition is false.
16291 if (Op.getNode()->hasOneUse()) {
16292 SDNode *User = *Op.getNode()->use_begin();
16293 // Look for an unconditional branch following this conditional branch.
16294 // We need this because we need to reverse the successors in order
16295 // to implement FCMP_OEQ.
16296 if (User->getOpcode() == ISD::BR) {
16297 SDValue FalseBB = User->getOperand(1);
16299 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16300 assert(NewBR == User);
16304 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16305 Cond.getOperand(0), Cond.getOperand(1));
16306 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16307 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16308 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16309 Chain, Dest, CC, Cmp);
16310 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16315 } else if (Cond.getOpcode() == ISD::SETCC &&
16316 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16317 // For FCMP_UNE, we can emit
16318 // two branches instead of an explicit AND instruction with a
16319 // separate test. However, we only do this if this block doesn't
16320 // have a fall-through edge, because this requires an explicit
16321 // jmp when the condition is false.
16322 if (Op.getNode()->hasOneUse()) {
16323 SDNode *User = *Op.getNode()->use_begin();
16324 // Look for an unconditional branch following this conditional branch.
16325 // We need this because we need to reverse the successors in order
16326 // to implement FCMP_UNE.
16327 if (User->getOpcode() == ISD::BR) {
16328 SDValue FalseBB = User->getOperand(1);
16330 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16331 assert(NewBR == User);
16334 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16335 Cond.getOperand(0), Cond.getOperand(1));
16336 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16337 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16338 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16339 Chain, Dest, CC, Cmp);
16340 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16350 // Look pass the truncate if the high bits are known zero.
16351 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16352 Cond = Cond.getOperand(0);
16354 // We know the result of AND is compared against zero. Try to match
16356 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16357 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16358 if (NewSetCC.getNode()) {
16359 CC = NewSetCC.getOperand(0);
16360 Cond = NewSetCC.getOperand(1);
16367 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16368 CC = DAG.getConstant(X86Cond, MVT::i8);
16369 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16371 Cond = ConvertCmpIfNecessary(Cond, DAG);
16372 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16373 Chain, Dest, CC, Cond);
16376 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16377 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16378 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16379 // that the guard pages used by the OS virtual memory manager are allocated in
16380 // correct sequence.
16382 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16383 SelectionDAG &DAG) const {
16384 MachineFunction &MF = DAG.getMachineFunction();
16385 bool SplitStack = MF.shouldSplitStack();
16386 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16392 SDNode* Node = Op.getNode();
16394 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16395 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16396 " not tell us which reg is the stack pointer!");
16397 EVT VT = Node->getValueType(0);
16398 SDValue Tmp1 = SDValue(Node, 0);
16399 SDValue Tmp2 = SDValue(Node, 1);
16400 SDValue Tmp3 = Node->getOperand(2);
16401 SDValue Chain = Tmp1.getOperand(0);
16403 // Chain the dynamic stack allocation so that it doesn't modify the stack
16404 // pointer when other instructions are using the stack.
16405 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16408 SDValue Size = Tmp2.getOperand(1);
16409 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16410 Chain = SP.getValue(1);
16411 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16412 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16413 unsigned StackAlign = TFI.getStackAlignment();
16414 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16415 if (Align > StackAlign)
16416 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16417 DAG.getConstant(-(uint64_t)Align, VT));
16418 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16420 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16421 DAG.getIntPtrConstant(0, true), SDValue(),
16424 SDValue Ops[2] = { Tmp1, Tmp2 };
16425 return DAG.getMergeValues(Ops, dl);
16429 SDValue Chain = Op.getOperand(0);
16430 SDValue Size = Op.getOperand(1);
16431 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16432 EVT VT = Op.getNode()->getValueType(0);
16434 bool Is64Bit = Subtarget->is64Bit();
16435 EVT SPTy = getPointerTy();
16438 MachineRegisterInfo &MRI = MF.getRegInfo();
16441 // The 64 bit implementation of segmented stacks needs to clobber both r10
16442 // r11. This makes it impossible to use it along with nested parameters.
16443 const Function *F = MF.getFunction();
16445 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16447 if (I->hasNestAttr())
16448 report_fatal_error("Cannot use segmented stacks with functions that "
16449 "have nested arguments.");
16452 const TargetRegisterClass *AddrRegClass =
16453 getRegClassFor(getPointerTy());
16454 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16455 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16456 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16457 DAG.getRegister(Vreg, SPTy));
16458 SDValue Ops1[2] = { Value, Chain };
16459 return DAG.getMergeValues(Ops1, dl);
16462 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16464 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16465 Flag = Chain.getValue(1);
16466 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16468 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16470 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16471 DAG.getSubtarget().getRegisterInfo());
16472 unsigned SPReg = RegInfo->getStackRegister();
16473 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16474 Chain = SP.getValue(1);
16477 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16478 DAG.getConstant(-(uint64_t)Align, VT));
16479 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16482 SDValue Ops1[2] = { SP, Chain };
16483 return DAG.getMergeValues(Ops1, dl);
16487 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16488 MachineFunction &MF = DAG.getMachineFunction();
16489 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16491 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16494 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16495 // vastart just stores the address of the VarArgsFrameIndex slot into the
16496 // memory location argument.
16497 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16499 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16500 MachinePointerInfo(SV), false, false, 0);
16504 // gp_offset (0 - 6 * 8)
16505 // fp_offset (48 - 48 + 8 * 16)
16506 // overflow_arg_area (point to parameters coming in memory).
16508 SmallVector<SDValue, 8> MemOps;
16509 SDValue FIN = Op.getOperand(1);
16511 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16512 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16514 FIN, MachinePointerInfo(SV), false, false, 0);
16515 MemOps.push_back(Store);
16518 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16519 FIN, DAG.getIntPtrConstant(4));
16520 Store = DAG.getStore(Op.getOperand(0), DL,
16521 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16523 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16524 MemOps.push_back(Store);
16526 // Store ptr to overflow_arg_area
16527 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16528 FIN, DAG.getIntPtrConstant(4));
16529 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16531 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16532 MachinePointerInfo(SV, 8),
16534 MemOps.push_back(Store);
16536 // Store ptr to reg_save_area.
16537 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16538 FIN, DAG.getIntPtrConstant(8));
16539 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16541 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16542 MachinePointerInfo(SV, 16), false, false, 0);
16543 MemOps.push_back(Store);
16544 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16547 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16548 assert(Subtarget->is64Bit() &&
16549 "LowerVAARG only handles 64-bit va_arg!");
16550 assert((Subtarget->isTargetLinux() ||
16551 Subtarget->isTargetDarwin()) &&
16552 "Unhandled target in LowerVAARG");
16553 assert(Op.getNode()->getNumOperands() == 4);
16554 SDValue Chain = Op.getOperand(0);
16555 SDValue SrcPtr = Op.getOperand(1);
16556 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16557 unsigned Align = Op.getConstantOperandVal(3);
16560 EVT ArgVT = Op.getNode()->getValueType(0);
16561 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16562 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16565 // Decide which area this value should be read from.
16566 // TODO: Implement the AMD64 ABI in its entirety. This simple
16567 // selection mechanism works only for the basic types.
16568 if (ArgVT == MVT::f80) {
16569 llvm_unreachable("va_arg for f80 not yet implemented");
16570 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16571 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16572 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16573 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16575 llvm_unreachable("Unhandled argument type in LowerVAARG");
16578 if (ArgMode == 2) {
16579 // Sanity Check: Make sure using fp_offset makes sense.
16580 assert(!DAG.getTarget().Options.UseSoftFloat &&
16581 !(DAG.getMachineFunction()
16582 .getFunction()->getAttributes()
16583 .hasAttribute(AttributeSet::FunctionIndex,
16584 Attribute::NoImplicitFloat)) &&
16585 Subtarget->hasSSE1());
16588 // Insert VAARG_64 node into the DAG
16589 // VAARG_64 returns two values: Variable Argument Address, Chain
16590 SmallVector<SDValue, 11> InstOps;
16591 InstOps.push_back(Chain);
16592 InstOps.push_back(SrcPtr);
16593 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16594 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16595 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16596 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16597 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16598 VTs, InstOps, MVT::i64,
16599 MachinePointerInfo(SV),
16601 /*Volatile=*/false,
16603 /*WriteMem=*/true);
16604 Chain = VAARG.getValue(1);
16606 // Load the next argument and return it
16607 return DAG.getLoad(ArgVT, dl,
16610 MachinePointerInfo(),
16611 false, false, false, 0);
16614 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16615 SelectionDAG &DAG) {
16616 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16617 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16618 SDValue Chain = Op.getOperand(0);
16619 SDValue DstPtr = Op.getOperand(1);
16620 SDValue SrcPtr = Op.getOperand(2);
16621 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16622 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16625 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16626 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16628 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16631 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16632 // amount is a constant. Takes immediate version of shift as input.
16633 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16634 SDValue SrcOp, uint64_t ShiftAmt,
16635 SelectionDAG &DAG) {
16636 MVT ElementType = VT.getVectorElementType();
16638 // Fold this packed shift into its first operand if ShiftAmt is 0.
16642 // Check for ShiftAmt >= element width
16643 if (ShiftAmt >= ElementType.getSizeInBits()) {
16644 if (Opc == X86ISD::VSRAI)
16645 ShiftAmt = ElementType.getSizeInBits() - 1;
16647 return DAG.getConstant(0, VT);
16650 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16651 && "Unknown target vector shift-by-constant node");
16653 // Fold this packed vector shift into a build vector if SrcOp is a
16654 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16655 if (VT == SrcOp.getSimpleValueType() &&
16656 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16657 SmallVector<SDValue, 8> Elts;
16658 unsigned NumElts = SrcOp->getNumOperands();
16659 ConstantSDNode *ND;
16662 default: llvm_unreachable(nullptr);
16663 case X86ISD::VSHLI:
16664 for (unsigned i=0; i!=NumElts; ++i) {
16665 SDValue CurrentOp = SrcOp->getOperand(i);
16666 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16667 Elts.push_back(CurrentOp);
16670 ND = cast<ConstantSDNode>(CurrentOp);
16671 const APInt &C = ND->getAPIntValue();
16672 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16675 case X86ISD::VSRLI:
16676 for (unsigned i=0; i!=NumElts; ++i) {
16677 SDValue CurrentOp = SrcOp->getOperand(i);
16678 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16679 Elts.push_back(CurrentOp);
16682 ND = cast<ConstantSDNode>(CurrentOp);
16683 const APInt &C = ND->getAPIntValue();
16684 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16687 case X86ISD::VSRAI:
16688 for (unsigned i=0; i!=NumElts; ++i) {
16689 SDValue CurrentOp = SrcOp->getOperand(i);
16690 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16691 Elts.push_back(CurrentOp);
16694 ND = cast<ConstantSDNode>(CurrentOp);
16695 const APInt &C = ND->getAPIntValue();
16696 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16701 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16704 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16707 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16708 // may or may not be a constant. Takes immediate version of shift as input.
16709 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16710 SDValue SrcOp, SDValue ShAmt,
16711 SelectionDAG &DAG) {
16712 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16714 // Catch shift-by-constant.
16715 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16716 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16717 CShAmt->getZExtValue(), DAG);
16719 // Change opcode to non-immediate version
16721 default: llvm_unreachable("Unknown target vector shift node");
16722 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16723 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16724 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16727 // Need to build a vector containing shift amount
16728 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16731 ShOps[1] = DAG.getConstant(0, MVT::i32);
16732 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16733 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16735 // The return type has to be a 128-bit type with the same element
16736 // type as the input type.
16737 MVT EltVT = VT.getVectorElementType();
16738 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16740 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16741 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16744 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16745 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16746 /// necessary casting for \p Mask when lowering masking intrinsics.
16747 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16748 SDValue PreservedSrc,
16749 const X86Subtarget *Subtarget,
16750 SelectionDAG &DAG) {
16751 EVT VT = Op.getValueType();
16752 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16753 MVT::i1, VT.getVectorNumElements());
16754 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16755 Mask.getValueType().getSizeInBits());
16758 assert(MaskVT.isSimple() && "invalid mask type");
16760 if (isAllOnes(Mask))
16763 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16764 // are extracted by EXTRACT_SUBVECTOR.
16765 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16766 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16767 DAG.getIntPtrConstant(0));
16769 switch (Op.getOpcode()) {
16771 case X86ISD::PCMPEQM:
16772 case X86ISD::PCMPGTM:
16774 case X86ISD::CMPMU:
16775 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16777 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16778 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16779 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16782 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16784 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16785 case Intrinsic::x86_fma_vfmadd_ps:
16786 case Intrinsic::x86_fma_vfmadd_pd:
16787 case Intrinsic::x86_fma_vfmadd_ps_256:
16788 case Intrinsic::x86_fma_vfmadd_pd_256:
16789 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16790 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16791 return X86ISD::FMADD;
16792 case Intrinsic::x86_fma_vfmsub_ps:
16793 case Intrinsic::x86_fma_vfmsub_pd:
16794 case Intrinsic::x86_fma_vfmsub_ps_256:
16795 case Intrinsic::x86_fma_vfmsub_pd_256:
16796 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16797 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16798 return X86ISD::FMSUB;
16799 case Intrinsic::x86_fma_vfnmadd_ps:
16800 case Intrinsic::x86_fma_vfnmadd_pd:
16801 case Intrinsic::x86_fma_vfnmadd_ps_256:
16802 case Intrinsic::x86_fma_vfnmadd_pd_256:
16803 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16804 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16805 return X86ISD::FNMADD;
16806 case Intrinsic::x86_fma_vfnmsub_ps:
16807 case Intrinsic::x86_fma_vfnmsub_pd:
16808 case Intrinsic::x86_fma_vfnmsub_ps_256:
16809 case Intrinsic::x86_fma_vfnmsub_pd_256:
16810 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16811 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16812 return X86ISD::FNMSUB;
16813 case Intrinsic::x86_fma_vfmaddsub_ps:
16814 case Intrinsic::x86_fma_vfmaddsub_pd:
16815 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16816 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16817 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16818 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16819 return X86ISD::FMADDSUB;
16820 case Intrinsic::x86_fma_vfmsubadd_ps:
16821 case Intrinsic::x86_fma_vfmsubadd_pd:
16822 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16823 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16824 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16825 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16826 return X86ISD::FMSUBADD;
16830 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16831 SelectionDAG &DAG) {
16833 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16834 EVT VT = Op.getValueType();
16835 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16837 switch(IntrData->Type) {
16838 case INTR_TYPE_1OP:
16839 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16840 case INTR_TYPE_2OP:
16841 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16843 case INTR_TYPE_3OP:
16844 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16845 Op.getOperand(2), Op.getOperand(3));
16846 case INTR_TYPE_1OP_MASK_RM: {
16847 SDValue Src = Op.getOperand(1);
16848 SDValue Src0 = Op.getOperand(2);
16849 SDValue Mask = Op.getOperand(3);
16850 SDValue RoundingMode = Op.getOperand(4);
16851 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16853 Mask, Src0, Subtarget, DAG);
16857 case CMP_MASK_CC: {
16858 // Comparison intrinsics with masks.
16859 // Example of transformation:
16860 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16861 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16863 // (v8i1 (insert_subvector undef,
16864 // (v2i1 (and (PCMPEQM %a, %b),
16865 // (extract_subvector
16866 // (v8i1 (bitcast %mask)), 0))), 0))))
16867 EVT VT = Op.getOperand(1).getValueType();
16868 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16869 VT.getVectorNumElements());
16870 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16871 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16872 Mask.getValueType().getSizeInBits());
16874 if (IntrData->Type == CMP_MASK_CC) {
16875 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16876 Op.getOperand(2), Op.getOperand(3));
16878 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16879 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16882 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16883 DAG.getTargetConstant(0, MaskVT),
16885 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16886 DAG.getUNDEF(BitcastVT), CmpMask,
16887 DAG.getIntPtrConstant(0));
16888 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16890 case COMI: { // Comparison intrinsics
16891 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16892 SDValue LHS = Op.getOperand(1);
16893 SDValue RHS = Op.getOperand(2);
16894 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16895 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16896 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16897 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16898 DAG.getConstant(X86CC, MVT::i8), Cond);
16899 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16902 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16903 Op.getOperand(1), Op.getOperand(2), DAG);
16905 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16906 Op.getOperand(1), Op.getOperand(2), DAG),
16907 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16914 default: return SDValue(); // Don't custom lower most intrinsics.
16916 // Arithmetic intrinsics.
16917 case Intrinsic::x86_sse2_pmulu_dq:
16918 case Intrinsic::x86_avx2_pmulu_dq:
16919 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16920 Op.getOperand(1), Op.getOperand(2));
16922 case Intrinsic::x86_sse41_pmuldq:
16923 case Intrinsic::x86_avx2_pmul_dq:
16924 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16925 Op.getOperand(1), Op.getOperand(2));
16927 case Intrinsic::x86_sse2_pmulhu_w:
16928 case Intrinsic::x86_avx2_pmulhu_w:
16929 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16930 Op.getOperand(1), Op.getOperand(2));
16932 case Intrinsic::x86_sse2_pmulh_w:
16933 case Intrinsic::x86_avx2_pmulh_w:
16934 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16935 Op.getOperand(1), Op.getOperand(2));
16937 // SSE/SSE2/AVX floating point max/min intrinsics.
16938 case Intrinsic::x86_sse_max_ps:
16939 case Intrinsic::x86_sse2_max_pd:
16940 case Intrinsic::x86_avx_max_ps_256:
16941 case Intrinsic::x86_avx_max_pd_256:
16942 case Intrinsic::x86_sse_min_ps:
16943 case Intrinsic::x86_sse2_min_pd:
16944 case Intrinsic::x86_avx_min_ps_256:
16945 case Intrinsic::x86_avx_min_pd_256: {
16948 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16949 case Intrinsic::x86_sse_max_ps:
16950 case Intrinsic::x86_sse2_max_pd:
16951 case Intrinsic::x86_avx_max_ps_256:
16952 case Intrinsic::x86_avx_max_pd_256:
16953 Opcode = X86ISD::FMAX;
16955 case Intrinsic::x86_sse_min_ps:
16956 case Intrinsic::x86_sse2_min_pd:
16957 case Intrinsic::x86_avx_min_ps_256:
16958 case Intrinsic::x86_avx_min_pd_256:
16959 Opcode = X86ISD::FMIN;
16962 return DAG.getNode(Opcode, dl, Op.getValueType(),
16963 Op.getOperand(1), Op.getOperand(2));
16966 // AVX2 variable shift intrinsics
16967 case Intrinsic::x86_avx2_psllv_d:
16968 case Intrinsic::x86_avx2_psllv_q:
16969 case Intrinsic::x86_avx2_psllv_d_256:
16970 case Intrinsic::x86_avx2_psllv_q_256:
16971 case Intrinsic::x86_avx2_psrlv_d:
16972 case Intrinsic::x86_avx2_psrlv_q:
16973 case Intrinsic::x86_avx2_psrlv_d_256:
16974 case Intrinsic::x86_avx2_psrlv_q_256:
16975 case Intrinsic::x86_avx2_psrav_d:
16976 case Intrinsic::x86_avx2_psrav_d_256: {
16979 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16980 case Intrinsic::x86_avx2_psllv_d:
16981 case Intrinsic::x86_avx2_psllv_q:
16982 case Intrinsic::x86_avx2_psllv_d_256:
16983 case Intrinsic::x86_avx2_psllv_q_256:
16986 case Intrinsic::x86_avx2_psrlv_d:
16987 case Intrinsic::x86_avx2_psrlv_q:
16988 case Intrinsic::x86_avx2_psrlv_d_256:
16989 case Intrinsic::x86_avx2_psrlv_q_256:
16992 case Intrinsic::x86_avx2_psrav_d:
16993 case Intrinsic::x86_avx2_psrav_d_256:
16997 return DAG.getNode(Opcode, dl, Op.getValueType(),
16998 Op.getOperand(1), Op.getOperand(2));
17001 case Intrinsic::x86_sse2_packssdw_128:
17002 case Intrinsic::x86_sse2_packsswb_128:
17003 case Intrinsic::x86_avx2_packssdw:
17004 case Intrinsic::x86_avx2_packsswb:
17005 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17006 Op.getOperand(1), Op.getOperand(2));
17008 case Intrinsic::x86_sse2_packuswb_128:
17009 case Intrinsic::x86_sse41_packusdw:
17010 case Intrinsic::x86_avx2_packuswb:
17011 case Intrinsic::x86_avx2_packusdw:
17012 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17013 Op.getOperand(1), Op.getOperand(2));
17015 case Intrinsic::x86_ssse3_pshuf_b_128:
17016 case Intrinsic::x86_avx2_pshuf_b:
17017 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17018 Op.getOperand(1), Op.getOperand(2));
17020 case Intrinsic::x86_sse2_pshuf_d:
17021 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17022 Op.getOperand(1), Op.getOperand(2));
17024 case Intrinsic::x86_sse2_pshufl_w:
17025 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17026 Op.getOperand(1), Op.getOperand(2));
17028 case Intrinsic::x86_sse2_pshufh_w:
17029 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17030 Op.getOperand(1), Op.getOperand(2));
17032 case Intrinsic::x86_ssse3_psign_b_128:
17033 case Intrinsic::x86_ssse3_psign_w_128:
17034 case Intrinsic::x86_ssse3_psign_d_128:
17035 case Intrinsic::x86_avx2_psign_b:
17036 case Intrinsic::x86_avx2_psign_w:
17037 case Intrinsic::x86_avx2_psign_d:
17038 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17039 Op.getOperand(1), Op.getOperand(2));
17041 case Intrinsic::x86_avx2_permd:
17042 case Intrinsic::x86_avx2_permps:
17043 // Operands intentionally swapped. Mask is last operand to intrinsic,
17044 // but second operand for node/instruction.
17045 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17046 Op.getOperand(2), Op.getOperand(1));
17048 case Intrinsic::x86_avx512_mask_valign_q_512:
17049 case Intrinsic::x86_avx512_mask_valign_d_512:
17050 // Vector source operands are swapped.
17051 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17052 Op.getValueType(), Op.getOperand(2),
17055 Op.getOperand(5), Op.getOperand(4),
17058 // ptest and testp intrinsics. The intrinsic these come from are designed to
17059 // return an integer value, not just an instruction so lower it to the ptest
17060 // or testp pattern and a setcc for the result.
17061 case Intrinsic::x86_sse41_ptestz:
17062 case Intrinsic::x86_sse41_ptestc:
17063 case Intrinsic::x86_sse41_ptestnzc:
17064 case Intrinsic::x86_avx_ptestz_256:
17065 case Intrinsic::x86_avx_ptestc_256:
17066 case Intrinsic::x86_avx_ptestnzc_256:
17067 case Intrinsic::x86_avx_vtestz_ps:
17068 case Intrinsic::x86_avx_vtestc_ps:
17069 case Intrinsic::x86_avx_vtestnzc_ps:
17070 case Intrinsic::x86_avx_vtestz_pd:
17071 case Intrinsic::x86_avx_vtestc_pd:
17072 case Intrinsic::x86_avx_vtestnzc_pd:
17073 case Intrinsic::x86_avx_vtestz_ps_256:
17074 case Intrinsic::x86_avx_vtestc_ps_256:
17075 case Intrinsic::x86_avx_vtestnzc_ps_256:
17076 case Intrinsic::x86_avx_vtestz_pd_256:
17077 case Intrinsic::x86_avx_vtestc_pd_256:
17078 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17079 bool IsTestPacked = false;
17082 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17083 case Intrinsic::x86_avx_vtestz_ps:
17084 case Intrinsic::x86_avx_vtestz_pd:
17085 case Intrinsic::x86_avx_vtestz_ps_256:
17086 case Intrinsic::x86_avx_vtestz_pd_256:
17087 IsTestPacked = true; // Fallthrough
17088 case Intrinsic::x86_sse41_ptestz:
17089 case Intrinsic::x86_avx_ptestz_256:
17091 X86CC = X86::COND_E;
17093 case Intrinsic::x86_avx_vtestc_ps:
17094 case Intrinsic::x86_avx_vtestc_pd:
17095 case Intrinsic::x86_avx_vtestc_ps_256:
17096 case Intrinsic::x86_avx_vtestc_pd_256:
17097 IsTestPacked = true; // Fallthrough
17098 case Intrinsic::x86_sse41_ptestc:
17099 case Intrinsic::x86_avx_ptestc_256:
17101 X86CC = X86::COND_B;
17103 case Intrinsic::x86_avx_vtestnzc_ps:
17104 case Intrinsic::x86_avx_vtestnzc_pd:
17105 case Intrinsic::x86_avx_vtestnzc_ps_256:
17106 case Intrinsic::x86_avx_vtestnzc_pd_256:
17107 IsTestPacked = true; // Fallthrough
17108 case Intrinsic::x86_sse41_ptestnzc:
17109 case Intrinsic::x86_avx_ptestnzc_256:
17111 X86CC = X86::COND_A;
17115 SDValue LHS = Op.getOperand(1);
17116 SDValue RHS = Op.getOperand(2);
17117 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17118 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17119 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17120 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17121 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17123 case Intrinsic::x86_avx512_kortestz_w:
17124 case Intrinsic::x86_avx512_kortestc_w: {
17125 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17126 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17127 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17128 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17129 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17130 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17131 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17134 case Intrinsic::x86_sse42_pcmpistria128:
17135 case Intrinsic::x86_sse42_pcmpestria128:
17136 case Intrinsic::x86_sse42_pcmpistric128:
17137 case Intrinsic::x86_sse42_pcmpestric128:
17138 case Intrinsic::x86_sse42_pcmpistrio128:
17139 case Intrinsic::x86_sse42_pcmpestrio128:
17140 case Intrinsic::x86_sse42_pcmpistris128:
17141 case Intrinsic::x86_sse42_pcmpestris128:
17142 case Intrinsic::x86_sse42_pcmpistriz128:
17143 case Intrinsic::x86_sse42_pcmpestriz128: {
17147 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17148 case Intrinsic::x86_sse42_pcmpistria128:
17149 Opcode = X86ISD::PCMPISTRI;
17150 X86CC = X86::COND_A;
17152 case Intrinsic::x86_sse42_pcmpestria128:
17153 Opcode = X86ISD::PCMPESTRI;
17154 X86CC = X86::COND_A;
17156 case Intrinsic::x86_sse42_pcmpistric128:
17157 Opcode = X86ISD::PCMPISTRI;
17158 X86CC = X86::COND_B;
17160 case Intrinsic::x86_sse42_pcmpestric128:
17161 Opcode = X86ISD::PCMPESTRI;
17162 X86CC = X86::COND_B;
17164 case Intrinsic::x86_sse42_pcmpistrio128:
17165 Opcode = X86ISD::PCMPISTRI;
17166 X86CC = X86::COND_O;
17168 case Intrinsic::x86_sse42_pcmpestrio128:
17169 Opcode = X86ISD::PCMPESTRI;
17170 X86CC = X86::COND_O;
17172 case Intrinsic::x86_sse42_pcmpistris128:
17173 Opcode = X86ISD::PCMPISTRI;
17174 X86CC = X86::COND_S;
17176 case Intrinsic::x86_sse42_pcmpestris128:
17177 Opcode = X86ISD::PCMPESTRI;
17178 X86CC = X86::COND_S;
17180 case Intrinsic::x86_sse42_pcmpistriz128:
17181 Opcode = X86ISD::PCMPISTRI;
17182 X86CC = X86::COND_E;
17184 case Intrinsic::x86_sse42_pcmpestriz128:
17185 Opcode = X86ISD::PCMPESTRI;
17186 X86CC = X86::COND_E;
17189 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17190 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17191 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17192 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17193 DAG.getConstant(X86CC, MVT::i8),
17194 SDValue(PCMP.getNode(), 1));
17195 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17198 case Intrinsic::x86_sse42_pcmpistri128:
17199 case Intrinsic::x86_sse42_pcmpestri128: {
17201 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17202 Opcode = X86ISD::PCMPISTRI;
17204 Opcode = X86ISD::PCMPESTRI;
17206 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17207 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17208 return DAG.getNode(Opcode, dl, VTs, NewOps);
17211 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17212 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17213 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17214 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17215 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17216 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17217 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17218 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17219 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17220 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17221 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17222 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17223 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17224 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17225 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17226 dl, Op.getValueType(),
17230 Op.getOperand(4), Op.getOperand(1),
17236 case Intrinsic::x86_fma_vfmadd_ps:
17237 case Intrinsic::x86_fma_vfmadd_pd:
17238 case Intrinsic::x86_fma_vfmsub_ps:
17239 case Intrinsic::x86_fma_vfmsub_pd:
17240 case Intrinsic::x86_fma_vfnmadd_ps:
17241 case Intrinsic::x86_fma_vfnmadd_pd:
17242 case Intrinsic::x86_fma_vfnmsub_ps:
17243 case Intrinsic::x86_fma_vfnmsub_pd:
17244 case Intrinsic::x86_fma_vfmaddsub_ps:
17245 case Intrinsic::x86_fma_vfmaddsub_pd:
17246 case Intrinsic::x86_fma_vfmsubadd_ps:
17247 case Intrinsic::x86_fma_vfmsubadd_pd:
17248 case Intrinsic::x86_fma_vfmadd_ps_256:
17249 case Intrinsic::x86_fma_vfmadd_pd_256:
17250 case Intrinsic::x86_fma_vfmsub_ps_256:
17251 case Intrinsic::x86_fma_vfmsub_pd_256:
17252 case Intrinsic::x86_fma_vfnmadd_ps_256:
17253 case Intrinsic::x86_fma_vfnmadd_pd_256:
17254 case Intrinsic::x86_fma_vfnmsub_ps_256:
17255 case Intrinsic::x86_fma_vfnmsub_pd_256:
17256 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17257 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17258 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17259 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17260 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17261 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17265 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17266 SDValue Src, SDValue Mask, SDValue Base,
17267 SDValue Index, SDValue ScaleOp, SDValue Chain,
17268 const X86Subtarget * Subtarget) {
17270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17271 assert(C && "Invalid scale type");
17272 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17273 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17274 Index.getSimpleValueType().getVectorNumElements());
17276 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17278 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17280 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17281 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17282 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17283 SDValue Segment = DAG.getRegister(0, MVT::i32);
17284 if (Src.getOpcode() == ISD::UNDEF)
17285 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17286 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17287 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17288 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17289 return DAG.getMergeValues(RetOps, dl);
17292 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17293 SDValue Src, SDValue Mask, SDValue Base,
17294 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17297 assert(C && "Invalid scale type");
17298 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17299 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17300 SDValue Segment = DAG.getRegister(0, MVT::i32);
17301 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17302 Index.getSimpleValueType().getVectorNumElements());
17304 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17306 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17308 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17309 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17310 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17311 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17312 return SDValue(Res, 1);
17315 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17316 SDValue Mask, SDValue Base, SDValue Index,
17317 SDValue ScaleOp, SDValue Chain) {
17319 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17320 assert(C && "Invalid scale type");
17321 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17322 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17323 SDValue Segment = DAG.getRegister(0, MVT::i32);
17325 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17327 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17329 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17331 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17332 //SDVTList VTs = DAG.getVTList(MVT::Other);
17333 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17334 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17335 return SDValue(Res, 0);
17338 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17339 // read performance monitor counters (x86_rdpmc).
17340 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17341 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17342 SmallVectorImpl<SDValue> &Results) {
17343 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17344 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17347 // The ECX register is used to select the index of the performance counter
17349 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17351 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17353 // Reads the content of a 64-bit performance counter and returns it in the
17354 // registers EDX:EAX.
17355 if (Subtarget->is64Bit()) {
17356 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17357 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17360 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17361 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17364 Chain = HI.getValue(1);
17366 if (Subtarget->is64Bit()) {
17367 // The EAX register is loaded with the low-order 32 bits. The EDX register
17368 // is loaded with the supported high-order bits of the counter.
17369 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17370 DAG.getConstant(32, MVT::i8));
17371 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17372 Results.push_back(Chain);
17376 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17377 SDValue Ops[] = { LO, HI };
17378 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17379 Results.push_back(Pair);
17380 Results.push_back(Chain);
17383 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17384 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17385 // also used to custom lower READCYCLECOUNTER nodes.
17386 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17387 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17388 SmallVectorImpl<SDValue> &Results) {
17389 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17390 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17393 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17394 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17395 // and the EAX register is loaded with the low-order 32 bits.
17396 if (Subtarget->is64Bit()) {
17397 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17398 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17401 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17402 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17405 SDValue Chain = HI.getValue(1);
17407 if (Opcode == X86ISD::RDTSCP_DAG) {
17408 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17410 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17411 // the ECX register. Add 'ecx' explicitly to the chain.
17412 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17414 // Explicitly store the content of ECX at the location passed in input
17415 // to the 'rdtscp' intrinsic.
17416 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17417 MachinePointerInfo(), false, false, 0);
17420 if (Subtarget->is64Bit()) {
17421 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17422 // the EAX register is loaded with the low-order 32 bits.
17423 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17424 DAG.getConstant(32, MVT::i8));
17425 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17426 Results.push_back(Chain);
17430 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17431 SDValue Ops[] = { LO, HI };
17432 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17433 Results.push_back(Pair);
17434 Results.push_back(Chain);
17437 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17438 SelectionDAG &DAG) {
17439 SmallVector<SDValue, 2> Results;
17441 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17443 return DAG.getMergeValues(Results, DL);
17447 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17448 SelectionDAG &DAG) {
17449 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17451 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17456 switch(IntrData->Type) {
17458 llvm_unreachable("Unknown Intrinsic Type");
17462 // Emit the node with the right value type.
17463 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17464 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17466 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17467 // Otherwise return the value from Rand, which is always 0, casted to i32.
17468 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17469 DAG.getConstant(1, Op->getValueType(1)),
17470 DAG.getConstant(X86::COND_B, MVT::i32),
17471 SDValue(Result.getNode(), 1) };
17472 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17473 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17476 // Return { result, isValid, chain }.
17477 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17478 SDValue(Result.getNode(), 2));
17481 //gather(v1, mask, index, base, scale);
17482 SDValue Chain = Op.getOperand(0);
17483 SDValue Src = Op.getOperand(2);
17484 SDValue Base = Op.getOperand(3);
17485 SDValue Index = Op.getOperand(4);
17486 SDValue Mask = Op.getOperand(5);
17487 SDValue Scale = Op.getOperand(6);
17488 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17492 //scatter(base, mask, index, v1, scale);
17493 SDValue Chain = Op.getOperand(0);
17494 SDValue Base = Op.getOperand(2);
17495 SDValue Mask = Op.getOperand(3);
17496 SDValue Index = Op.getOperand(4);
17497 SDValue Src = Op.getOperand(5);
17498 SDValue Scale = Op.getOperand(6);
17499 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17502 SDValue Hint = Op.getOperand(6);
17504 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17505 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17506 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17507 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17508 SDValue Chain = Op.getOperand(0);
17509 SDValue Mask = Op.getOperand(2);
17510 SDValue Index = Op.getOperand(3);
17511 SDValue Base = Op.getOperand(4);
17512 SDValue Scale = Op.getOperand(5);
17513 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17515 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17517 SmallVector<SDValue, 2> Results;
17518 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17519 return DAG.getMergeValues(Results, dl);
17521 // Read Performance Monitoring Counters.
17523 SmallVector<SDValue, 2> Results;
17524 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17525 return DAG.getMergeValues(Results, dl);
17527 // XTEST intrinsics.
17529 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17530 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17531 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17532 DAG.getConstant(X86::COND_NE, MVT::i8),
17534 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17535 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17536 Ret, SDValue(InTrans.getNode(), 1));
17540 SmallVector<SDValue, 2> Results;
17541 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17542 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17543 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17544 DAG.getConstant(-1, MVT::i8));
17545 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17546 Op.getOperand(4), GenCF.getValue(1));
17547 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17548 Op.getOperand(5), MachinePointerInfo(),
17550 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17551 DAG.getConstant(X86::COND_B, MVT::i8),
17553 Results.push_back(SetCC);
17554 Results.push_back(Store);
17555 return DAG.getMergeValues(Results, dl);
17560 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17561 SelectionDAG &DAG) const {
17562 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17563 MFI->setReturnAddressIsTaken(true);
17565 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17568 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17570 EVT PtrVT = getPointerTy();
17573 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17574 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17575 DAG.getSubtarget().getRegisterInfo());
17576 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17577 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17578 DAG.getNode(ISD::ADD, dl, PtrVT,
17579 FrameAddr, Offset),
17580 MachinePointerInfo(), false, false, false, 0);
17583 // Just load the return address.
17584 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17585 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17586 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17589 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17590 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17591 MFI->setFrameAddressIsTaken(true);
17593 EVT VT = Op.getValueType();
17594 SDLoc dl(Op); // FIXME probably not meaningful
17595 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17596 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17597 DAG.getSubtarget().getRegisterInfo());
17598 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17599 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17600 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17601 "Invalid Frame Register!");
17602 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17604 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17605 MachinePointerInfo(),
17606 false, false, false, 0);
17610 // FIXME? Maybe this could be a TableGen attribute on some registers and
17611 // this table could be generated automatically from RegInfo.
17612 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17614 unsigned Reg = StringSwitch<unsigned>(RegName)
17615 .Case("esp", X86::ESP)
17616 .Case("rsp", X86::RSP)
17620 report_fatal_error("Invalid register name global variable");
17623 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17624 SelectionDAG &DAG) const {
17625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17626 DAG.getSubtarget().getRegisterInfo());
17627 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17630 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17631 SDValue Chain = Op.getOperand(0);
17632 SDValue Offset = Op.getOperand(1);
17633 SDValue Handler = Op.getOperand(2);
17636 EVT PtrVT = getPointerTy();
17637 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17638 DAG.getSubtarget().getRegisterInfo());
17639 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17640 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17641 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17642 "Invalid Frame Register!");
17643 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17644 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17646 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17647 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17648 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17649 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17651 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17653 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17654 DAG.getRegister(StoreAddrReg, PtrVT));
17657 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17658 SelectionDAG &DAG) const {
17660 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17661 DAG.getVTList(MVT::i32, MVT::Other),
17662 Op.getOperand(0), Op.getOperand(1));
17665 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17666 SelectionDAG &DAG) const {
17668 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17669 Op.getOperand(0), Op.getOperand(1));
17672 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17673 return Op.getOperand(0);
17676 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17677 SelectionDAG &DAG) const {
17678 SDValue Root = Op.getOperand(0);
17679 SDValue Trmp = Op.getOperand(1); // trampoline
17680 SDValue FPtr = Op.getOperand(2); // nested function
17681 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17684 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17685 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17687 if (Subtarget->is64Bit()) {
17688 SDValue OutChains[6];
17690 // Large code-model.
17691 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17692 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17694 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17695 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17697 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17699 // Load the pointer to the nested function into R11.
17700 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17701 SDValue Addr = Trmp;
17702 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17703 Addr, MachinePointerInfo(TrmpAddr),
17706 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17707 DAG.getConstant(2, MVT::i64));
17708 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17709 MachinePointerInfo(TrmpAddr, 2),
17712 // Load the 'nest' parameter value into R10.
17713 // R10 is specified in X86CallingConv.td
17714 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17715 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17716 DAG.getConstant(10, MVT::i64));
17717 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17718 Addr, MachinePointerInfo(TrmpAddr, 10),
17721 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17722 DAG.getConstant(12, MVT::i64));
17723 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17724 MachinePointerInfo(TrmpAddr, 12),
17727 // Jump to the nested function.
17728 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17729 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17730 DAG.getConstant(20, MVT::i64));
17731 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17732 Addr, MachinePointerInfo(TrmpAddr, 20),
17735 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17736 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17737 DAG.getConstant(22, MVT::i64));
17738 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17739 MachinePointerInfo(TrmpAddr, 22),
17742 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17744 const Function *Func =
17745 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17746 CallingConv::ID CC = Func->getCallingConv();
17751 llvm_unreachable("Unsupported calling convention");
17752 case CallingConv::C:
17753 case CallingConv::X86_StdCall: {
17754 // Pass 'nest' parameter in ECX.
17755 // Must be kept in sync with X86CallingConv.td
17756 NestReg = X86::ECX;
17758 // Check that ECX wasn't needed by an 'inreg' parameter.
17759 FunctionType *FTy = Func->getFunctionType();
17760 const AttributeSet &Attrs = Func->getAttributes();
17762 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17763 unsigned InRegCount = 0;
17766 for (FunctionType::param_iterator I = FTy->param_begin(),
17767 E = FTy->param_end(); I != E; ++I, ++Idx)
17768 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17769 // FIXME: should only count parameters that are lowered to integers.
17770 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17772 if (InRegCount > 2) {
17773 report_fatal_error("Nest register in use - reduce number of inreg"
17779 case CallingConv::X86_FastCall:
17780 case CallingConv::X86_ThisCall:
17781 case CallingConv::Fast:
17782 // Pass 'nest' parameter in EAX.
17783 // Must be kept in sync with X86CallingConv.td
17784 NestReg = X86::EAX;
17788 SDValue OutChains[4];
17789 SDValue Addr, Disp;
17791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17792 DAG.getConstant(10, MVT::i32));
17793 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17795 // This is storing the opcode for MOV32ri.
17796 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17797 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17798 OutChains[0] = DAG.getStore(Root, dl,
17799 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17800 Trmp, MachinePointerInfo(TrmpAddr),
17803 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17804 DAG.getConstant(1, MVT::i32));
17805 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17806 MachinePointerInfo(TrmpAddr, 1),
17809 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17810 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17811 DAG.getConstant(5, MVT::i32));
17812 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17813 MachinePointerInfo(TrmpAddr, 5),
17816 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17817 DAG.getConstant(6, MVT::i32));
17818 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17819 MachinePointerInfo(TrmpAddr, 6),
17822 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17826 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17827 SelectionDAG &DAG) const {
17829 The rounding mode is in bits 11:10 of FPSR, and has the following
17831 00 Round to nearest
17836 FLT_ROUNDS, on the other hand, expects the following:
17843 To perform the conversion, we do:
17844 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17847 MachineFunction &MF = DAG.getMachineFunction();
17848 const TargetMachine &TM = MF.getTarget();
17849 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17850 unsigned StackAlignment = TFI.getStackAlignment();
17851 MVT VT = Op.getSimpleValueType();
17854 // Save FP Control Word to stack slot
17855 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17856 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17858 MachineMemOperand *MMO =
17859 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17860 MachineMemOperand::MOStore, 2, 2);
17862 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17863 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17864 DAG.getVTList(MVT::Other),
17865 Ops, MVT::i16, MMO);
17867 // Load FP Control Word from stack slot
17868 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17869 MachinePointerInfo(), false, false, false, 0);
17871 // Transform as necessary
17873 DAG.getNode(ISD::SRL, DL, MVT::i16,
17874 DAG.getNode(ISD::AND, DL, MVT::i16,
17875 CWD, DAG.getConstant(0x800, MVT::i16)),
17876 DAG.getConstant(11, MVT::i8));
17878 DAG.getNode(ISD::SRL, DL, MVT::i16,
17879 DAG.getNode(ISD::AND, DL, MVT::i16,
17880 CWD, DAG.getConstant(0x400, MVT::i16)),
17881 DAG.getConstant(9, MVT::i8));
17884 DAG.getNode(ISD::AND, DL, MVT::i16,
17885 DAG.getNode(ISD::ADD, DL, MVT::i16,
17886 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17887 DAG.getConstant(1, MVT::i16)),
17888 DAG.getConstant(3, MVT::i16));
17890 return DAG.getNode((VT.getSizeInBits() < 16 ?
17891 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17894 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17895 MVT VT = Op.getSimpleValueType();
17897 unsigned NumBits = VT.getSizeInBits();
17900 Op = Op.getOperand(0);
17901 if (VT == MVT::i8) {
17902 // Zero extend to i32 since there is not an i8 bsr.
17904 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17907 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17908 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17909 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17911 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17914 DAG.getConstant(NumBits+NumBits-1, OpVT),
17915 DAG.getConstant(X86::COND_E, MVT::i8),
17918 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17920 // Finally xor with NumBits-1.
17921 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17924 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17928 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17929 MVT VT = Op.getSimpleValueType();
17931 unsigned NumBits = VT.getSizeInBits();
17934 Op = Op.getOperand(0);
17935 if (VT == MVT::i8) {
17936 // Zero extend to i32 since there is not an i8 bsr.
17938 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17941 // Issue a bsr (scan bits in reverse).
17942 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17943 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17945 // And xor with NumBits-1.
17946 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17949 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17953 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17954 MVT VT = Op.getSimpleValueType();
17955 unsigned NumBits = VT.getSizeInBits();
17957 Op = Op.getOperand(0);
17959 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17960 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17961 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17963 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17966 DAG.getConstant(NumBits, VT),
17967 DAG.getConstant(X86::COND_E, MVT::i8),
17970 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17973 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17974 // ones, and then concatenate the result back.
17975 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17976 MVT VT = Op.getSimpleValueType();
17978 assert(VT.is256BitVector() && VT.isInteger() &&
17979 "Unsupported value type for operation");
17981 unsigned NumElems = VT.getVectorNumElements();
17984 // Extract the LHS vectors
17985 SDValue LHS = Op.getOperand(0);
17986 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17987 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17989 // Extract the RHS vectors
17990 SDValue RHS = Op.getOperand(1);
17991 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17992 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17994 MVT EltVT = VT.getVectorElementType();
17995 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17997 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17998 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17999 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18002 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18003 assert(Op.getSimpleValueType().is256BitVector() &&
18004 Op.getSimpleValueType().isInteger() &&
18005 "Only handle AVX 256-bit vector integer operation");
18006 return Lower256IntArith(Op, DAG);
18009 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18010 assert(Op.getSimpleValueType().is256BitVector() &&
18011 Op.getSimpleValueType().isInteger() &&
18012 "Only handle AVX 256-bit vector integer operation");
18013 return Lower256IntArith(Op, DAG);
18016 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18017 SelectionDAG &DAG) {
18019 MVT VT = Op.getSimpleValueType();
18021 // Decompose 256-bit ops into smaller 128-bit ops.
18022 if (VT.is256BitVector() && !Subtarget->hasInt256())
18023 return Lower256IntArith(Op, DAG);
18025 SDValue A = Op.getOperand(0);
18026 SDValue B = Op.getOperand(1);
18028 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18029 if (VT == MVT::v4i32) {
18030 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18031 "Should not custom lower when pmuldq is available!");
18033 // Extract the odd parts.
18034 static const int UnpackMask[] = { 1, -1, 3, -1 };
18035 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18036 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18038 // Multiply the even parts.
18039 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18040 // Now multiply odd parts.
18041 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18043 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18044 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18046 // Merge the two vectors back together with a shuffle. This expands into 2
18048 static const int ShufMask[] = { 0, 4, 2, 6 };
18049 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18052 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18053 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18055 // Ahi = psrlqi(a, 32);
18056 // Bhi = psrlqi(b, 32);
18058 // AloBlo = pmuludq(a, b);
18059 // AloBhi = pmuludq(a, Bhi);
18060 // AhiBlo = pmuludq(Ahi, b);
18062 // AloBhi = psllqi(AloBhi, 32);
18063 // AhiBlo = psllqi(AhiBlo, 32);
18064 // return AloBlo + AloBhi + AhiBlo;
18066 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18067 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18069 // Bit cast to 32-bit vectors for MULUDQ
18070 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18071 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18072 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18073 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18074 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18075 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18077 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18078 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18079 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18081 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18082 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18084 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18085 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18088 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18089 assert(Subtarget->isTargetWin64() && "Unexpected target");
18090 EVT VT = Op.getValueType();
18091 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18092 "Unexpected return type for lowering");
18096 switch (Op->getOpcode()) {
18097 default: llvm_unreachable("Unexpected request for libcall!");
18098 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18099 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18100 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18101 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18102 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18103 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18107 SDValue InChain = DAG.getEntryNode();
18109 TargetLowering::ArgListTy Args;
18110 TargetLowering::ArgListEntry Entry;
18111 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18112 EVT ArgVT = Op->getOperand(i).getValueType();
18113 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18114 "Unexpected argument type for lowering");
18115 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18116 Entry.Node = StackPtr;
18117 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18119 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18120 Entry.Ty = PointerType::get(ArgTy,0);
18121 Entry.isSExt = false;
18122 Entry.isZExt = false;
18123 Args.push_back(Entry);
18126 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18129 TargetLowering::CallLoweringInfo CLI(DAG);
18130 CLI.setDebugLoc(dl).setChain(InChain)
18131 .setCallee(getLibcallCallingConv(LC),
18132 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18133 Callee, std::move(Args), 0)
18134 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18136 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18137 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18140 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18141 SelectionDAG &DAG) {
18142 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18143 EVT VT = Op0.getValueType();
18146 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18147 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18149 // PMULxD operations multiply each even value (starting at 0) of LHS with
18150 // the related value of RHS and produce a widen result.
18151 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18152 // => <2 x i64> <ae|cg>
18154 // In other word, to have all the results, we need to perform two PMULxD:
18155 // 1. one with the even values.
18156 // 2. one with the odd values.
18157 // To achieve #2, with need to place the odd values at an even position.
18159 // Place the odd value at an even position (basically, shift all values 1
18160 // step to the left):
18161 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18162 // <a|b|c|d> => <b|undef|d|undef>
18163 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18164 // <e|f|g|h> => <f|undef|h|undef>
18165 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18167 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18169 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18170 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18172 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18173 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18174 // => <2 x i64> <ae|cg>
18175 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18176 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18177 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18178 // => <2 x i64> <bf|dh>
18179 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18180 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18182 // Shuffle it back into the right order.
18183 SDValue Highs, Lows;
18184 if (VT == MVT::v8i32) {
18185 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18186 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18187 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18188 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18190 const int HighMask[] = {1, 5, 3, 7};
18191 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18192 const int LowMask[] = {0, 4, 2, 6};
18193 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18196 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18197 // unsigned multiply.
18198 if (IsSigned && !Subtarget->hasSSE41()) {
18200 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18201 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18202 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18203 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18204 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18206 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18207 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18210 // The first result of MUL_LOHI is actually the low value, followed by the
18212 SDValue Ops[] = {Lows, Highs};
18213 return DAG.getMergeValues(Ops, dl);
18216 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18217 const X86Subtarget *Subtarget) {
18218 MVT VT = Op.getSimpleValueType();
18220 SDValue R = Op.getOperand(0);
18221 SDValue Amt = Op.getOperand(1);
18223 // Optimize shl/srl/sra with constant shift amount.
18224 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18225 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18226 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18228 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18229 (Subtarget->hasInt256() &&
18230 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18231 (Subtarget->hasAVX512() &&
18232 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18233 if (Op.getOpcode() == ISD::SHL)
18234 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18236 if (Op.getOpcode() == ISD::SRL)
18237 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18239 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18240 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18244 if (VT == MVT::v16i8) {
18245 if (Op.getOpcode() == ISD::SHL) {
18246 // Make a large shift.
18247 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18248 MVT::v8i16, R, ShiftAmt,
18250 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18251 // Zero out the rightmost bits.
18252 SmallVector<SDValue, 16> V(16,
18253 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18255 return DAG.getNode(ISD::AND, dl, VT, SHL,
18256 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18258 if (Op.getOpcode() == ISD::SRL) {
18259 // Make a large shift.
18260 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18261 MVT::v8i16, R, ShiftAmt,
18263 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18264 // Zero out the leftmost bits.
18265 SmallVector<SDValue, 16> V(16,
18266 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18268 return DAG.getNode(ISD::AND, dl, VT, SRL,
18269 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18271 if (Op.getOpcode() == ISD::SRA) {
18272 if (ShiftAmt == 7) {
18273 // R s>> 7 === R s< 0
18274 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18275 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18278 // R s>> a === ((R u>> a) ^ m) - m
18279 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18280 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18282 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18283 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18284 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18287 llvm_unreachable("Unknown shift opcode.");
18290 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18291 if (Op.getOpcode() == ISD::SHL) {
18292 // Make a large shift.
18293 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18294 MVT::v16i16, R, ShiftAmt,
18296 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18297 // Zero out the rightmost bits.
18298 SmallVector<SDValue, 32> V(32,
18299 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18301 return DAG.getNode(ISD::AND, dl, VT, SHL,
18302 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18304 if (Op.getOpcode() == ISD::SRL) {
18305 // Make a large shift.
18306 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18307 MVT::v16i16, R, ShiftAmt,
18309 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18310 // Zero out the leftmost bits.
18311 SmallVector<SDValue, 32> V(32,
18312 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18314 return DAG.getNode(ISD::AND, dl, VT, SRL,
18315 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18317 if (Op.getOpcode() == ISD::SRA) {
18318 if (ShiftAmt == 7) {
18319 // R s>> 7 === R s< 0
18320 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18321 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18324 // R s>> a === ((R u>> a) ^ m) - m
18325 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18326 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18328 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18329 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18330 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18333 llvm_unreachable("Unknown shift opcode.");
18338 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18339 if (!Subtarget->is64Bit() &&
18340 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18341 Amt.getOpcode() == ISD::BITCAST &&
18342 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18343 Amt = Amt.getOperand(0);
18344 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18345 VT.getVectorNumElements();
18346 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18347 uint64_t ShiftAmt = 0;
18348 for (unsigned i = 0; i != Ratio; ++i) {
18349 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18353 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18355 // Check remaining shift amounts.
18356 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18357 uint64_t ShAmt = 0;
18358 for (unsigned j = 0; j != Ratio; ++j) {
18359 ConstantSDNode *C =
18360 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18364 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18366 if (ShAmt != ShiftAmt)
18369 switch (Op.getOpcode()) {
18371 llvm_unreachable("Unknown shift opcode!");
18373 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18376 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18379 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18387 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18388 const X86Subtarget* Subtarget) {
18389 MVT VT = Op.getSimpleValueType();
18391 SDValue R = Op.getOperand(0);
18392 SDValue Amt = Op.getOperand(1);
18394 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18395 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18396 (Subtarget->hasInt256() &&
18397 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18398 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18399 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18401 EVT EltVT = VT.getVectorElementType();
18403 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18404 unsigned NumElts = VT.getVectorNumElements();
18406 for (i = 0; i != NumElts; ++i) {
18407 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18411 for (j = i; j != NumElts; ++j) {
18412 SDValue Arg = Amt.getOperand(j);
18413 if (Arg.getOpcode() == ISD::UNDEF) continue;
18414 if (Arg != Amt.getOperand(i))
18417 if (i != NumElts && j == NumElts)
18418 BaseShAmt = Amt.getOperand(i);
18420 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18421 Amt = Amt.getOperand(0);
18422 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18423 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18424 SDValue InVec = Amt.getOperand(0);
18425 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18426 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18428 for (; i != NumElts; ++i) {
18429 SDValue Arg = InVec.getOperand(i);
18430 if (Arg.getOpcode() == ISD::UNDEF) continue;
18434 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18435 if (ConstantSDNode *C =
18436 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18437 unsigned SplatIdx =
18438 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18439 if (C->getZExtValue() == SplatIdx)
18440 BaseShAmt = InVec.getOperand(1);
18443 if (!BaseShAmt.getNode())
18444 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18445 DAG.getIntPtrConstant(0));
18449 if (BaseShAmt.getNode()) {
18450 if (EltVT.bitsGT(MVT::i32))
18451 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18452 else if (EltVT.bitsLT(MVT::i32))
18453 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18455 switch (Op.getOpcode()) {
18457 llvm_unreachable("Unknown shift opcode!");
18459 switch (VT.SimpleTy) {
18460 default: return SDValue();
18469 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18472 switch (VT.SimpleTy) {
18473 default: return SDValue();
18480 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18483 switch (VT.SimpleTy) {
18484 default: return SDValue();
18493 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18499 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18500 if (!Subtarget->is64Bit() &&
18501 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18502 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18503 Amt.getOpcode() == ISD::BITCAST &&
18504 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18505 Amt = Amt.getOperand(0);
18506 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18507 VT.getVectorNumElements();
18508 std::vector<SDValue> Vals(Ratio);
18509 for (unsigned i = 0; i != Ratio; ++i)
18510 Vals[i] = Amt.getOperand(i);
18511 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18512 for (unsigned j = 0; j != Ratio; ++j)
18513 if (Vals[j] != Amt.getOperand(i + j))
18516 switch (Op.getOpcode()) {
18518 llvm_unreachable("Unknown shift opcode!");
18520 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18522 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18524 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18531 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18532 SelectionDAG &DAG) {
18533 MVT VT = Op.getSimpleValueType();
18535 SDValue R = Op.getOperand(0);
18536 SDValue Amt = Op.getOperand(1);
18539 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18540 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18542 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18546 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18550 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18552 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18553 if (Subtarget->hasInt256()) {
18554 if (Op.getOpcode() == ISD::SRL &&
18555 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18556 VT == MVT::v4i64 || VT == MVT::v8i32))
18558 if (Op.getOpcode() == ISD::SHL &&
18559 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18560 VT == MVT::v4i64 || VT == MVT::v8i32))
18562 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18566 // If possible, lower this packed shift into a vector multiply instead of
18567 // expanding it into a sequence of scalar shifts.
18568 // Do this only if the vector shift count is a constant build_vector.
18569 if (Op.getOpcode() == ISD::SHL &&
18570 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18571 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18572 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18573 SmallVector<SDValue, 8> Elts;
18574 EVT SVT = VT.getScalarType();
18575 unsigned SVTBits = SVT.getSizeInBits();
18576 const APInt &One = APInt(SVTBits, 1);
18577 unsigned NumElems = VT.getVectorNumElements();
18579 for (unsigned i=0; i !=NumElems; ++i) {
18580 SDValue Op = Amt->getOperand(i);
18581 if (Op->getOpcode() == ISD::UNDEF) {
18582 Elts.push_back(Op);
18586 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18587 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18588 uint64_t ShAmt = C.getZExtValue();
18589 if (ShAmt >= SVTBits) {
18590 Elts.push_back(DAG.getUNDEF(SVT));
18593 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18595 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18596 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18599 // Lower SHL with variable shift amount.
18600 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18601 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18603 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18604 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18605 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18606 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18609 // If possible, lower this shift as a sequence of two shifts by
18610 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18612 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18614 // Could be rewritten as:
18615 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18617 // The advantage is that the two shifts from the example would be
18618 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18619 // the vector shift into four scalar shifts plus four pairs of vector
18621 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18622 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18623 unsigned TargetOpcode = X86ISD::MOVSS;
18624 bool CanBeSimplified;
18625 // The splat value for the first packed shift (the 'X' from the example).
18626 SDValue Amt1 = Amt->getOperand(0);
18627 // The splat value for the second packed shift (the 'Y' from the example).
18628 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18629 Amt->getOperand(2);
18631 // See if it is possible to replace this node with a sequence of
18632 // two shifts followed by a MOVSS/MOVSD
18633 if (VT == MVT::v4i32) {
18634 // Check if it is legal to use a MOVSS.
18635 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18636 Amt2 == Amt->getOperand(3);
18637 if (!CanBeSimplified) {
18638 // Otherwise, check if we can still simplify this node using a MOVSD.
18639 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18640 Amt->getOperand(2) == Amt->getOperand(3);
18641 TargetOpcode = X86ISD::MOVSD;
18642 Amt2 = Amt->getOperand(2);
18645 // Do similar checks for the case where the machine value type
18647 CanBeSimplified = Amt1 == Amt->getOperand(1);
18648 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18649 CanBeSimplified = Amt2 == Amt->getOperand(i);
18651 if (!CanBeSimplified) {
18652 TargetOpcode = X86ISD::MOVSD;
18653 CanBeSimplified = true;
18654 Amt2 = Amt->getOperand(4);
18655 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18656 CanBeSimplified = Amt1 == Amt->getOperand(i);
18657 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18658 CanBeSimplified = Amt2 == Amt->getOperand(j);
18662 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18663 isa<ConstantSDNode>(Amt2)) {
18664 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18665 EVT CastVT = MVT::v4i32;
18667 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18668 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18670 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18671 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18672 if (TargetOpcode == X86ISD::MOVSD)
18673 CastVT = MVT::v2i64;
18674 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18675 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18676 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18678 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18682 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18683 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18686 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18687 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18689 // Turn 'a' into a mask suitable for VSELECT
18690 SDValue VSelM = DAG.getConstant(0x80, VT);
18691 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18692 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18694 SDValue CM1 = DAG.getConstant(0x0f, VT);
18695 SDValue CM2 = DAG.getConstant(0x3f, VT);
18697 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18698 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18699 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18700 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18701 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18704 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18705 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18706 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18708 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18709 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18710 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18711 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18712 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18715 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18716 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18717 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18719 // return VSELECT(r, r+r, a);
18720 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18721 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18725 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18726 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18727 // solution better.
18728 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18729 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18731 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18732 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18733 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18734 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18735 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18738 // Decompose 256-bit shifts into smaller 128-bit shifts.
18739 if (VT.is256BitVector()) {
18740 unsigned NumElems = VT.getVectorNumElements();
18741 MVT EltVT = VT.getVectorElementType();
18742 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18744 // Extract the two vectors
18745 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18746 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18748 // Recreate the shift amount vectors
18749 SDValue Amt1, Amt2;
18750 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18751 // Constant shift amount
18752 SmallVector<SDValue, 4> Amt1Csts;
18753 SmallVector<SDValue, 4> Amt2Csts;
18754 for (unsigned i = 0; i != NumElems/2; ++i)
18755 Amt1Csts.push_back(Amt->getOperand(i));
18756 for (unsigned i = NumElems/2; i != NumElems; ++i)
18757 Amt2Csts.push_back(Amt->getOperand(i));
18759 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18760 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18762 // Variable shift amount
18763 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18764 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18767 // Issue new vector shifts for the smaller types
18768 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18769 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18771 // Concatenate the result back
18772 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18778 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18779 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18780 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18781 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18782 // has only one use.
18783 SDNode *N = Op.getNode();
18784 SDValue LHS = N->getOperand(0);
18785 SDValue RHS = N->getOperand(1);
18786 unsigned BaseOp = 0;
18789 switch (Op.getOpcode()) {
18790 default: llvm_unreachable("Unknown ovf instruction!");
18792 // A subtract of one will be selected as a INC. Note that INC doesn't
18793 // set CF, so we can't do this for UADDO.
18794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18796 BaseOp = X86ISD::INC;
18797 Cond = X86::COND_O;
18800 BaseOp = X86ISD::ADD;
18801 Cond = X86::COND_O;
18804 BaseOp = X86ISD::ADD;
18805 Cond = X86::COND_B;
18808 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18809 // set CF, so we can't do this for USUBO.
18810 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18812 BaseOp = X86ISD::DEC;
18813 Cond = X86::COND_O;
18816 BaseOp = X86ISD::SUB;
18817 Cond = X86::COND_O;
18820 BaseOp = X86ISD::SUB;
18821 Cond = X86::COND_B;
18824 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18825 Cond = X86::COND_O;
18827 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18828 if (N->getValueType(0) == MVT::i8) {
18829 BaseOp = X86ISD::UMUL8;
18830 Cond = X86::COND_O;
18833 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18835 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18838 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18839 DAG.getConstant(X86::COND_O, MVT::i32),
18840 SDValue(Sum.getNode(), 2));
18842 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18846 // Also sets EFLAGS.
18847 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18848 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18851 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18852 DAG.getConstant(Cond, MVT::i32),
18853 SDValue(Sum.getNode(), 1));
18855 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18858 // Sign extension of the low part of vector elements. This may be used either
18859 // when sign extend instructions are not available or if the vector element
18860 // sizes already match the sign-extended size. If the vector elements are in
18861 // their pre-extended size and sign extend instructions are available, that will
18862 // be handled by LowerSIGN_EXTEND.
18863 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18864 SelectionDAG &DAG) const {
18866 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18867 MVT VT = Op.getSimpleValueType();
18869 if (!Subtarget->hasSSE2() || !VT.isVector())
18872 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18873 ExtraVT.getScalarType().getSizeInBits();
18875 switch (VT.SimpleTy) {
18876 default: return SDValue();
18879 if (!Subtarget->hasFp256())
18881 if (!Subtarget->hasInt256()) {
18882 // needs to be split
18883 unsigned NumElems = VT.getVectorNumElements();
18885 // Extract the LHS vectors
18886 SDValue LHS = Op.getOperand(0);
18887 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18888 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18890 MVT EltVT = VT.getVectorElementType();
18891 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18893 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18894 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18895 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18897 SDValue Extra = DAG.getValueType(ExtraVT);
18899 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18900 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18902 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18907 SDValue Op0 = Op.getOperand(0);
18909 // This is a sign extension of some low part of vector elements without
18910 // changing the size of the vector elements themselves:
18911 // Shift-Left + Shift-Right-Algebraic.
18912 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18914 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18920 /// Returns true if the operand type is exactly twice the native width, and
18921 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18922 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18923 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18924 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18925 const X86Subtarget &Subtarget =
18926 getTargetMachine().getSubtarget<X86Subtarget>();
18927 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18930 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18931 else if (OpWidth == 128)
18932 return Subtarget.hasCmpxchg16b();
18937 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18938 return needsCmpXchgNb(SI->getValueOperand()->getType());
18941 // Note: this turns large loads into lock cmpxchg8b/16b.
18942 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18943 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18944 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18945 return needsCmpXchgNb(PTy->getElementType());
18948 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18949 const X86Subtarget &Subtarget =
18950 getTargetMachine().getSubtarget<X86Subtarget>();
18951 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18952 const Type *MemType = AI->getType();
18954 // If the operand is too big, we must see if cmpxchg8/16b is available
18955 // and default to library calls otherwise.
18956 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18957 return needsCmpXchgNb(MemType);
18959 AtomicRMWInst::BinOp Op = AI->getOperation();
18962 llvm_unreachable("Unknown atomic operation");
18963 case AtomicRMWInst::Xchg:
18964 case AtomicRMWInst::Add:
18965 case AtomicRMWInst::Sub:
18966 // It's better to use xadd, xsub or xchg for these in all cases.
18968 case AtomicRMWInst::Or:
18969 case AtomicRMWInst::And:
18970 case AtomicRMWInst::Xor:
18971 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18972 // prefix to a normal instruction for these operations.
18973 return !AI->use_empty();
18974 case AtomicRMWInst::Nand:
18975 case AtomicRMWInst::Max:
18976 case AtomicRMWInst::Min:
18977 case AtomicRMWInst::UMax:
18978 case AtomicRMWInst::UMin:
18979 // These always require a non-trivial set of data operations on x86. We must
18980 // use a cmpxchg loop.
18985 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18986 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18987 // no-sse2). There isn't any reason to disable it if the target processor
18989 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18993 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18994 const X86Subtarget &Subtarget =
18995 getTargetMachine().getSubtarget<X86Subtarget>();
18996 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18997 const Type *MemType = AI->getType();
18998 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18999 // there is no benefit in turning such RMWs into loads, and it is actually
19000 // harmful as it introduces a mfence.
19001 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19004 auto Builder = IRBuilder<>(AI);
19005 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19006 auto SynchScope = AI->getSynchScope();
19007 // We must restrict the ordering to avoid generating loads with Release or
19008 // ReleaseAcquire orderings.
19009 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19010 auto Ptr = AI->getPointerOperand();
19012 // Before the load we need a fence. Here is an example lifted from
19013 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19016 // x.store(1, relaxed);
19017 // r1 = y.fetch_add(0, release);
19019 // y.fetch_add(42, acquire);
19020 // r2 = x.load(relaxed);
19021 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19022 // lowered to just a load without a fence. A mfence flushes the store buffer,
19023 // making the optimization clearly correct.
19024 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19025 // otherwise, we might be able to be more agressive on relaxed idempotent
19026 // rmw. In practice, they do not look useful, so we don't try to be
19027 // especially clever.
19028 if (SynchScope == SingleThread) {
19029 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19030 // the IR level, so we must wrap it in an intrinsic.
19032 } else if (hasMFENCE(Subtarget)) {
19033 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19034 Intrinsic::x86_sse2_mfence);
19035 Builder.CreateCall(MFence);
19037 // FIXME: it might make sense to use a locked operation here but on a
19038 // different cache-line to prevent cache-line bouncing. In practice it
19039 // is probably a small win, and x86 processors without mfence are rare
19040 // enough that we do not bother.
19044 // Finally we can emit the atomic load.
19045 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19046 AI->getType()->getPrimitiveSizeInBits());
19047 Loaded->setAtomic(Order, SynchScope);
19048 AI->replaceAllUsesWith(Loaded);
19049 AI->eraseFromParent();
19053 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19054 SelectionDAG &DAG) {
19056 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19057 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19058 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19059 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19061 // The only fence that needs an instruction is a sequentially-consistent
19062 // cross-thread fence.
19063 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19064 if (hasMFENCE(*Subtarget))
19065 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19067 SDValue Chain = Op.getOperand(0);
19068 SDValue Zero = DAG.getConstant(0, MVT::i32);
19070 DAG.getRegister(X86::ESP, MVT::i32), // Base
19071 DAG.getTargetConstant(1, MVT::i8), // Scale
19072 DAG.getRegister(0, MVT::i32), // Index
19073 DAG.getTargetConstant(0, MVT::i32), // Disp
19074 DAG.getRegister(0, MVT::i32), // Segment.
19078 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19079 return SDValue(Res, 0);
19082 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19083 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19086 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19087 SelectionDAG &DAG) {
19088 MVT T = Op.getSimpleValueType();
19092 switch(T.SimpleTy) {
19093 default: llvm_unreachable("Invalid value type!");
19094 case MVT::i8: Reg = X86::AL; size = 1; break;
19095 case MVT::i16: Reg = X86::AX; size = 2; break;
19096 case MVT::i32: Reg = X86::EAX; size = 4; break;
19098 assert(Subtarget->is64Bit() && "Node not type legal!");
19099 Reg = X86::RAX; size = 8;
19102 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19103 Op.getOperand(2), SDValue());
19104 SDValue Ops[] = { cpIn.getValue(0),
19107 DAG.getTargetConstant(size, MVT::i8),
19108 cpIn.getValue(1) };
19109 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19110 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19111 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19115 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19116 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19117 MVT::i32, cpOut.getValue(2));
19118 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19119 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19121 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19122 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19123 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19127 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19128 SelectionDAG &DAG) {
19129 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19130 MVT DstVT = Op.getSimpleValueType();
19132 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19133 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19134 if (DstVT != MVT::f64)
19135 // This conversion needs to be expanded.
19138 SDValue InVec = Op->getOperand(0);
19140 unsigned NumElts = SrcVT.getVectorNumElements();
19141 EVT SVT = SrcVT.getVectorElementType();
19143 // Widen the vector in input in the case of MVT::v2i32.
19144 // Example: from MVT::v2i32 to MVT::v4i32.
19145 SmallVector<SDValue, 16> Elts;
19146 for (unsigned i = 0, e = NumElts; i != e; ++i)
19147 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19148 DAG.getIntPtrConstant(i)));
19150 // Explicitly mark the extra elements as Undef.
19151 SDValue Undef = DAG.getUNDEF(SVT);
19152 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19153 Elts.push_back(Undef);
19155 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19156 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19157 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19158 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19159 DAG.getIntPtrConstant(0));
19162 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19163 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19164 assert((DstVT == MVT::i64 ||
19165 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19166 "Unexpected custom BITCAST");
19167 // i64 <=> MMX conversions are Legal.
19168 if (SrcVT==MVT::i64 && DstVT.isVector())
19170 if (DstVT==MVT::i64 && SrcVT.isVector())
19172 // MMX <=> MMX conversions are Legal.
19173 if (SrcVT.isVector() && DstVT.isVector())
19175 // All other conversions need to be expanded.
19179 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19180 SDNode *Node = Op.getNode();
19182 EVT T = Node->getValueType(0);
19183 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19184 DAG.getConstant(0, T), Node->getOperand(2));
19185 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19186 cast<AtomicSDNode>(Node)->getMemoryVT(),
19187 Node->getOperand(0),
19188 Node->getOperand(1), negOp,
19189 cast<AtomicSDNode>(Node)->getMemOperand(),
19190 cast<AtomicSDNode>(Node)->getOrdering(),
19191 cast<AtomicSDNode>(Node)->getSynchScope());
19194 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19195 SDNode *Node = Op.getNode();
19197 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19199 // Convert seq_cst store -> xchg
19200 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19201 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19202 // (The only way to get a 16-byte store is cmpxchg16b)
19203 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19204 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19205 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19206 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19207 cast<AtomicSDNode>(Node)->getMemoryVT(),
19208 Node->getOperand(0),
19209 Node->getOperand(1), Node->getOperand(2),
19210 cast<AtomicSDNode>(Node)->getMemOperand(),
19211 cast<AtomicSDNode>(Node)->getOrdering(),
19212 cast<AtomicSDNode>(Node)->getSynchScope());
19213 return Swap.getValue(1);
19215 // Other atomic stores have a simple pattern.
19219 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19220 EVT VT = Op.getNode()->getSimpleValueType(0);
19222 // Let legalize expand this if it isn't a legal type yet.
19223 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19226 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19229 bool ExtraOp = false;
19230 switch (Op.getOpcode()) {
19231 default: llvm_unreachable("Invalid code");
19232 case ISD::ADDC: Opc = X86ISD::ADD; break;
19233 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19234 case ISD::SUBC: Opc = X86ISD::SUB; break;
19235 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19239 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19241 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19242 Op.getOperand(1), Op.getOperand(2));
19245 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19246 SelectionDAG &DAG) {
19247 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19249 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19250 // which returns the values as { float, float } (in XMM0) or
19251 // { double, double } (which is returned in XMM0, XMM1).
19253 SDValue Arg = Op.getOperand(0);
19254 EVT ArgVT = Arg.getValueType();
19255 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19257 TargetLowering::ArgListTy Args;
19258 TargetLowering::ArgListEntry Entry;
19262 Entry.isSExt = false;
19263 Entry.isZExt = false;
19264 Args.push_back(Entry);
19266 bool isF64 = ArgVT == MVT::f64;
19267 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19268 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19269 // the results are returned via SRet in memory.
19270 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19272 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19274 Type *RetTy = isF64
19275 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19276 : (Type*)VectorType::get(ArgTy, 4);
19278 TargetLowering::CallLoweringInfo CLI(DAG);
19279 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19280 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19282 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19285 // Returned in xmm0 and xmm1.
19286 return CallResult.first;
19288 // Returned in bits 0:31 and 32:64 xmm0.
19289 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19290 CallResult.first, DAG.getIntPtrConstant(0));
19291 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19292 CallResult.first, DAG.getIntPtrConstant(1));
19293 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19294 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19297 /// LowerOperation - Provide custom lowering hooks for some operations.
19299 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19300 switch (Op.getOpcode()) {
19301 default: llvm_unreachable("Should not custom lower this!");
19302 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19303 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19304 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19305 return LowerCMP_SWAP(Op, Subtarget, DAG);
19306 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19307 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19308 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19309 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19310 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19311 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19312 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19313 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19314 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19315 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19316 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19317 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19318 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19319 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19320 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19321 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19322 case ISD::SHL_PARTS:
19323 case ISD::SRA_PARTS:
19324 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19325 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19326 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19327 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19328 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19329 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19330 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19331 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19332 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19333 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19334 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19336 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19337 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19338 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19339 case ISD::SETCC: return LowerSETCC(Op, DAG);
19340 case ISD::SELECT: return LowerSELECT(Op, DAG);
19341 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19342 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19343 case ISD::VASTART: return LowerVASTART(Op, DAG);
19344 case ISD::VAARG: return LowerVAARG(Op, DAG);
19345 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19346 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19347 case ISD::INTRINSIC_VOID:
19348 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19349 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19350 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19351 case ISD::FRAME_TO_ARGS_OFFSET:
19352 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19353 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19354 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19355 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19356 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19357 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19358 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19359 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19360 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19361 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19362 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19363 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19364 case ISD::UMUL_LOHI:
19365 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19368 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19374 case ISD::UMULO: return LowerXALUO(Op, DAG);
19375 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19376 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19380 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19381 case ISD::ADD: return LowerADD(Op, DAG);
19382 case ISD::SUB: return LowerSUB(Op, DAG);
19383 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19387 /// ReplaceNodeResults - Replace a node with an illegal result type
19388 /// with a new node built out of custom code.
19389 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19390 SmallVectorImpl<SDValue>&Results,
19391 SelectionDAG &DAG) const {
19393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19394 switch (N->getOpcode()) {
19396 llvm_unreachable("Do not know how to custom type legalize this operation!");
19397 case ISD::SIGN_EXTEND_INREG:
19402 // We don't want to expand or promote these.
19409 case ISD::UDIVREM: {
19410 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19411 Results.push_back(V);
19414 case ISD::FP_TO_SINT:
19415 case ISD::FP_TO_UINT: {
19416 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19418 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19421 std::pair<SDValue,SDValue> Vals =
19422 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19423 SDValue FIST = Vals.first, StackSlot = Vals.second;
19424 if (FIST.getNode()) {
19425 EVT VT = N->getValueType(0);
19426 // Return a load from the stack slot.
19427 if (StackSlot.getNode())
19428 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19429 MachinePointerInfo(),
19430 false, false, false, 0));
19432 Results.push_back(FIST);
19436 case ISD::UINT_TO_FP: {
19437 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19438 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19439 N->getValueType(0) != MVT::v2f32)
19441 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19443 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19445 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19446 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19447 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19448 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19449 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19450 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19453 case ISD::FP_ROUND: {
19454 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19456 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19457 Results.push_back(V);
19460 case ISD::INTRINSIC_W_CHAIN: {
19461 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19463 default : llvm_unreachable("Do not know how to custom type "
19464 "legalize this intrinsic operation!");
19465 case Intrinsic::x86_rdtsc:
19466 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19468 case Intrinsic::x86_rdtscp:
19469 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19471 case Intrinsic::x86_rdpmc:
19472 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19475 case ISD::READCYCLECOUNTER: {
19476 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19479 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19480 EVT T = N->getValueType(0);
19481 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19482 bool Regs64bit = T == MVT::i128;
19483 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19484 SDValue cpInL, cpInH;
19485 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19486 DAG.getConstant(0, HalfT));
19487 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19488 DAG.getConstant(1, HalfT));
19489 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19490 Regs64bit ? X86::RAX : X86::EAX,
19492 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19493 Regs64bit ? X86::RDX : X86::EDX,
19494 cpInH, cpInL.getValue(1));
19495 SDValue swapInL, swapInH;
19496 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19497 DAG.getConstant(0, HalfT));
19498 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19499 DAG.getConstant(1, HalfT));
19500 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19501 Regs64bit ? X86::RBX : X86::EBX,
19502 swapInL, cpInH.getValue(1));
19503 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19504 Regs64bit ? X86::RCX : X86::ECX,
19505 swapInH, swapInL.getValue(1));
19506 SDValue Ops[] = { swapInH.getValue(0),
19508 swapInH.getValue(1) };
19509 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19510 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19511 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19512 X86ISD::LCMPXCHG8_DAG;
19513 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19514 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19515 Regs64bit ? X86::RAX : X86::EAX,
19516 HalfT, Result.getValue(1));
19517 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19518 Regs64bit ? X86::RDX : X86::EDX,
19519 HalfT, cpOutL.getValue(2));
19520 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19522 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19523 MVT::i32, cpOutH.getValue(2));
19525 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19526 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19527 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19529 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19530 Results.push_back(Success);
19531 Results.push_back(EFLAGS.getValue(1));
19534 case ISD::ATOMIC_SWAP:
19535 case ISD::ATOMIC_LOAD_ADD:
19536 case ISD::ATOMIC_LOAD_SUB:
19537 case ISD::ATOMIC_LOAD_AND:
19538 case ISD::ATOMIC_LOAD_OR:
19539 case ISD::ATOMIC_LOAD_XOR:
19540 case ISD::ATOMIC_LOAD_NAND:
19541 case ISD::ATOMIC_LOAD_MIN:
19542 case ISD::ATOMIC_LOAD_MAX:
19543 case ISD::ATOMIC_LOAD_UMIN:
19544 case ISD::ATOMIC_LOAD_UMAX:
19545 case ISD::ATOMIC_LOAD: {
19546 // Delegate to generic TypeLegalization. Situations we can really handle
19547 // should have already been dealt with by AtomicExpandPass.cpp.
19550 case ISD::BITCAST: {
19551 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19552 EVT DstVT = N->getValueType(0);
19553 EVT SrcVT = N->getOperand(0)->getValueType(0);
19555 if (SrcVT != MVT::f64 ||
19556 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19559 unsigned NumElts = DstVT.getVectorNumElements();
19560 EVT SVT = DstVT.getVectorElementType();
19561 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19562 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19563 MVT::v2f64, N->getOperand(0));
19564 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19566 if (ExperimentalVectorWideningLegalization) {
19567 // If we are legalizing vectors by widening, we already have the desired
19568 // legal vector type, just return it.
19569 Results.push_back(ToVecInt);
19573 SmallVector<SDValue, 8> Elts;
19574 for (unsigned i = 0, e = NumElts; i != e; ++i)
19575 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19576 ToVecInt, DAG.getIntPtrConstant(i)));
19578 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19583 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19585 default: return nullptr;
19586 case X86ISD::BSF: return "X86ISD::BSF";
19587 case X86ISD::BSR: return "X86ISD::BSR";
19588 case X86ISD::SHLD: return "X86ISD::SHLD";
19589 case X86ISD::SHRD: return "X86ISD::SHRD";
19590 case X86ISD::FAND: return "X86ISD::FAND";
19591 case X86ISD::FANDN: return "X86ISD::FANDN";
19592 case X86ISD::FOR: return "X86ISD::FOR";
19593 case X86ISD::FXOR: return "X86ISD::FXOR";
19594 case X86ISD::FSRL: return "X86ISD::FSRL";
19595 case X86ISD::FILD: return "X86ISD::FILD";
19596 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19597 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19598 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19599 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19600 case X86ISD::FLD: return "X86ISD::FLD";
19601 case X86ISD::FST: return "X86ISD::FST";
19602 case X86ISD::CALL: return "X86ISD::CALL";
19603 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19604 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19605 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19606 case X86ISD::BT: return "X86ISD::BT";
19607 case X86ISD::CMP: return "X86ISD::CMP";
19608 case X86ISD::COMI: return "X86ISD::COMI";
19609 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19610 case X86ISD::CMPM: return "X86ISD::CMPM";
19611 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19612 case X86ISD::SETCC: return "X86ISD::SETCC";
19613 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19614 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19615 case X86ISD::CMOV: return "X86ISD::CMOV";
19616 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19617 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19618 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19619 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19620 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19621 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19622 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19623 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19624 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19625 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19626 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19627 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19628 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19629 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19630 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19631 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19632 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19633 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19634 case X86ISD::HADD: return "X86ISD::HADD";
19635 case X86ISD::HSUB: return "X86ISD::HSUB";
19636 case X86ISD::FHADD: return "X86ISD::FHADD";
19637 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19638 case X86ISD::UMAX: return "X86ISD::UMAX";
19639 case X86ISD::UMIN: return "X86ISD::UMIN";
19640 case X86ISD::SMAX: return "X86ISD::SMAX";
19641 case X86ISD::SMIN: return "X86ISD::SMIN";
19642 case X86ISD::FMAX: return "X86ISD::FMAX";
19643 case X86ISD::FMIN: return "X86ISD::FMIN";
19644 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19645 case X86ISD::FMINC: return "X86ISD::FMINC";
19646 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19647 case X86ISD::FRCP: return "X86ISD::FRCP";
19648 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19649 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19650 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19651 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19652 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19653 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19654 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19655 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19656 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19657 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19658 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19659 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19660 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19661 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19662 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19663 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19664 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19665 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19666 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19667 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19668 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19669 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19670 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19671 case X86ISD::VSHL: return "X86ISD::VSHL";
19672 case X86ISD::VSRL: return "X86ISD::VSRL";
19673 case X86ISD::VSRA: return "X86ISD::VSRA";
19674 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19675 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19676 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19677 case X86ISD::CMPP: return "X86ISD::CMPP";
19678 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19679 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19680 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19681 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19682 case X86ISD::ADD: return "X86ISD::ADD";
19683 case X86ISD::SUB: return "X86ISD::SUB";
19684 case X86ISD::ADC: return "X86ISD::ADC";
19685 case X86ISD::SBB: return "X86ISD::SBB";
19686 case X86ISD::SMUL: return "X86ISD::SMUL";
19687 case X86ISD::UMUL: return "X86ISD::UMUL";
19688 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19689 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19690 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19691 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19692 case X86ISD::INC: return "X86ISD::INC";
19693 case X86ISD::DEC: return "X86ISD::DEC";
19694 case X86ISD::OR: return "X86ISD::OR";
19695 case X86ISD::XOR: return "X86ISD::XOR";
19696 case X86ISD::AND: return "X86ISD::AND";
19697 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19698 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19699 case X86ISD::PTEST: return "X86ISD::PTEST";
19700 case X86ISD::TESTP: return "X86ISD::TESTP";
19701 case X86ISD::TESTM: return "X86ISD::TESTM";
19702 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19703 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19704 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19705 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19706 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19707 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19708 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19709 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19710 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19711 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19712 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19713 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19714 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19715 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19716 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19717 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19718 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19719 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19720 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19721 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19722 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19723 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19724 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19725 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19726 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19727 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19728 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19729 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19730 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19731 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19732 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19733 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19734 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19735 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19736 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19737 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19738 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19739 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19740 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19741 case X86ISD::SAHF: return "X86ISD::SAHF";
19742 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19743 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19744 case X86ISD::FMADD: return "X86ISD::FMADD";
19745 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19746 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19747 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19748 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19749 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19750 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19751 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19752 case X86ISD::XTEST: return "X86ISD::XTEST";
19756 // isLegalAddressingMode - Return true if the addressing mode represented
19757 // by AM is legal for this target, for a load/store of the specified type.
19758 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19760 // X86 supports extremely general addressing modes.
19761 CodeModel::Model M = getTargetMachine().getCodeModel();
19762 Reloc::Model R = getTargetMachine().getRelocationModel();
19764 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19765 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19770 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19772 // If a reference to this global requires an extra load, we can't fold it.
19773 if (isGlobalStubReference(GVFlags))
19776 // If BaseGV requires a register for the PIC base, we cannot also have a
19777 // BaseReg specified.
19778 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19781 // If lower 4G is not available, then we must use rip-relative addressing.
19782 if ((M != CodeModel::Small || R != Reloc::Static) &&
19783 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19787 switch (AM.Scale) {
19793 // These scales always work.
19798 // These scales are formed with basereg+scalereg. Only accept if there is
19803 default: // Other stuff never works.
19810 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19811 unsigned Bits = Ty->getScalarSizeInBits();
19813 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19814 // particularly cheaper than those without.
19818 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19819 // variable shifts just as cheap as scalar ones.
19820 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19823 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19824 // fully general vector.
19828 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19829 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19831 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19832 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19833 return NumBits1 > NumBits2;
19836 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19837 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19840 if (!isTypeLegal(EVT::getEVT(Ty1)))
19843 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19845 // Assuming the caller doesn't have a zeroext or signext return parameter,
19846 // truncation all the way down to i1 is valid.
19850 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19851 return isInt<32>(Imm);
19854 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19855 // Can also use sub to handle negated immediates.
19856 return isInt<32>(Imm);
19859 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19860 if (!VT1.isInteger() || !VT2.isInteger())
19862 unsigned NumBits1 = VT1.getSizeInBits();
19863 unsigned NumBits2 = VT2.getSizeInBits();
19864 return NumBits1 > NumBits2;
19867 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19868 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19869 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19872 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19873 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19874 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19877 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19878 EVT VT1 = Val.getValueType();
19879 if (isZExtFree(VT1, VT2))
19882 if (Val.getOpcode() != ISD::LOAD)
19885 if (!VT1.isSimple() || !VT1.isInteger() ||
19886 !VT2.isSimple() || !VT2.isInteger())
19889 switch (VT1.getSimpleVT().SimpleTy) {
19894 // X86 has 8, 16, and 32-bit zero-extending loads.
19902 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19903 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19906 VT = VT.getScalarType();
19908 if (!VT.isSimple())
19911 switch (VT.getSimpleVT().SimpleTy) {
19922 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19923 // i16 instructions are longer (0x66 prefix) and potentially slower.
19924 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19927 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19928 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19929 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19930 /// are assumed to be legal.
19932 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19934 if (!VT.isSimple())
19937 MVT SVT = VT.getSimpleVT();
19939 // Very little shuffling can be done for 64-bit vectors right now.
19940 if (VT.getSizeInBits() == 64)
19943 // If this is a single-input shuffle with no 128 bit lane crossings we can
19944 // lower it into pshufb.
19945 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19946 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19947 bool isLegal = true;
19948 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19949 if (M[I] >= (int)SVT.getVectorNumElements() ||
19950 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19959 // FIXME: blends, shifts.
19960 return (SVT.getVectorNumElements() == 2 ||
19961 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19962 isMOVLMask(M, SVT) ||
19963 isMOVHLPSMask(M, SVT) ||
19964 isSHUFPMask(M, SVT) ||
19965 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19966 isPSHUFDMask(M, SVT) ||
19967 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19968 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19969 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19970 isPALIGNRMask(M, SVT, Subtarget) ||
19971 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19972 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19973 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19974 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19975 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19976 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19980 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19982 if (!VT.isSimple())
19985 MVT SVT = VT.getSimpleVT();
19986 unsigned NumElts = SVT.getVectorNumElements();
19987 // FIXME: This collection of masks seems suspect.
19990 if (NumElts == 4 && SVT.is128BitVector()) {
19991 return (isMOVLMask(Mask, SVT) ||
19992 isCommutedMOVLMask(Mask, SVT, true) ||
19993 isSHUFPMask(Mask, SVT) ||
19994 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19995 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19996 Subtarget->hasInt256()));
20001 //===----------------------------------------------------------------------===//
20002 // X86 Scheduler Hooks
20003 //===----------------------------------------------------------------------===//
20005 /// Utility function to emit xbegin specifying the start of an RTM region.
20006 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20007 const TargetInstrInfo *TII) {
20008 DebugLoc DL = MI->getDebugLoc();
20010 const BasicBlock *BB = MBB->getBasicBlock();
20011 MachineFunction::iterator I = MBB;
20014 // For the v = xbegin(), we generate
20025 MachineBasicBlock *thisMBB = MBB;
20026 MachineFunction *MF = MBB->getParent();
20027 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20028 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20029 MF->insert(I, mainMBB);
20030 MF->insert(I, sinkMBB);
20032 // Transfer the remainder of BB and its successor edges to sinkMBB.
20033 sinkMBB->splice(sinkMBB->begin(), MBB,
20034 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20035 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20039 // # fallthrough to mainMBB
20040 // # abortion to sinkMBB
20041 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20042 thisMBB->addSuccessor(mainMBB);
20043 thisMBB->addSuccessor(sinkMBB);
20047 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20048 mainMBB->addSuccessor(sinkMBB);
20051 // EAX is live into the sinkMBB
20052 sinkMBB->addLiveIn(X86::EAX);
20053 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20054 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20057 MI->eraseFromParent();
20061 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20062 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20063 // in the .td file.
20064 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20065 const TargetInstrInfo *TII) {
20067 switch (MI->getOpcode()) {
20068 default: llvm_unreachable("illegal opcode!");
20069 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20070 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20071 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20072 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20073 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20074 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20075 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20076 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20079 DebugLoc dl = MI->getDebugLoc();
20080 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20082 unsigned NumArgs = MI->getNumOperands();
20083 for (unsigned i = 1; i < NumArgs; ++i) {
20084 MachineOperand &Op = MI->getOperand(i);
20085 if (!(Op.isReg() && Op.isImplicit()))
20086 MIB.addOperand(Op);
20088 if (MI->hasOneMemOperand())
20089 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20091 BuildMI(*BB, MI, dl,
20092 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20093 .addReg(X86::XMM0);
20095 MI->eraseFromParent();
20099 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20100 // defs in an instruction pattern
20101 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20102 const TargetInstrInfo *TII) {
20104 switch (MI->getOpcode()) {
20105 default: llvm_unreachable("illegal opcode!");
20106 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20107 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20108 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20109 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20110 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20111 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20112 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20113 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20116 DebugLoc dl = MI->getDebugLoc();
20117 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20119 unsigned NumArgs = MI->getNumOperands(); // remove the results
20120 for (unsigned i = 1; i < NumArgs; ++i) {
20121 MachineOperand &Op = MI->getOperand(i);
20122 if (!(Op.isReg() && Op.isImplicit()))
20123 MIB.addOperand(Op);
20125 if (MI->hasOneMemOperand())
20126 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20128 BuildMI(*BB, MI, dl,
20129 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20132 MI->eraseFromParent();
20136 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20137 const TargetInstrInfo *TII,
20138 const X86Subtarget* Subtarget) {
20139 DebugLoc dl = MI->getDebugLoc();
20141 // Address into RAX/EAX, other two args into ECX, EDX.
20142 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20143 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20144 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20145 for (int i = 0; i < X86::AddrNumOperands; ++i)
20146 MIB.addOperand(MI->getOperand(i));
20148 unsigned ValOps = X86::AddrNumOperands;
20149 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20150 .addReg(MI->getOperand(ValOps).getReg());
20151 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20152 .addReg(MI->getOperand(ValOps+1).getReg());
20154 // The instruction doesn't actually take any operands though.
20155 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20157 MI->eraseFromParent(); // The pseudo is gone now.
20161 MachineBasicBlock *
20162 X86TargetLowering::EmitVAARG64WithCustomInserter(
20164 MachineBasicBlock *MBB) const {
20165 // Emit va_arg instruction on X86-64.
20167 // Operands to this pseudo-instruction:
20168 // 0 ) Output : destination address (reg)
20169 // 1-5) Input : va_list address (addr, i64mem)
20170 // 6 ) ArgSize : Size (in bytes) of vararg type
20171 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20172 // 8 ) Align : Alignment of type
20173 // 9 ) EFLAGS (implicit-def)
20175 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20176 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20178 unsigned DestReg = MI->getOperand(0).getReg();
20179 MachineOperand &Base = MI->getOperand(1);
20180 MachineOperand &Scale = MI->getOperand(2);
20181 MachineOperand &Index = MI->getOperand(3);
20182 MachineOperand &Disp = MI->getOperand(4);
20183 MachineOperand &Segment = MI->getOperand(5);
20184 unsigned ArgSize = MI->getOperand(6).getImm();
20185 unsigned ArgMode = MI->getOperand(7).getImm();
20186 unsigned Align = MI->getOperand(8).getImm();
20188 // Memory Reference
20189 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20190 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20191 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20193 // Machine Information
20194 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20195 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20196 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20197 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20198 DebugLoc DL = MI->getDebugLoc();
20200 // struct va_list {
20203 // i64 overflow_area (address)
20204 // i64 reg_save_area (address)
20206 // sizeof(va_list) = 24
20207 // alignment(va_list) = 8
20209 unsigned TotalNumIntRegs = 6;
20210 unsigned TotalNumXMMRegs = 8;
20211 bool UseGPOffset = (ArgMode == 1);
20212 bool UseFPOffset = (ArgMode == 2);
20213 unsigned MaxOffset = TotalNumIntRegs * 8 +
20214 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20216 /* Align ArgSize to a multiple of 8 */
20217 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20218 bool NeedsAlign = (Align > 8);
20220 MachineBasicBlock *thisMBB = MBB;
20221 MachineBasicBlock *overflowMBB;
20222 MachineBasicBlock *offsetMBB;
20223 MachineBasicBlock *endMBB;
20225 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20226 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20227 unsigned OffsetReg = 0;
20229 if (!UseGPOffset && !UseFPOffset) {
20230 // If we only pull from the overflow region, we don't create a branch.
20231 // We don't need to alter control flow.
20232 OffsetDestReg = 0; // unused
20233 OverflowDestReg = DestReg;
20235 offsetMBB = nullptr;
20236 overflowMBB = thisMBB;
20239 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20240 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20241 // If not, pull from overflow_area. (branch to overflowMBB)
20246 // offsetMBB overflowMBB
20251 // Registers for the PHI in endMBB
20252 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20253 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20255 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20256 MachineFunction *MF = MBB->getParent();
20257 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20258 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20259 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20261 MachineFunction::iterator MBBIter = MBB;
20264 // Insert the new basic blocks
20265 MF->insert(MBBIter, offsetMBB);
20266 MF->insert(MBBIter, overflowMBB);
20267 MF->insert(MBBIter, endMBB);
20269 // Transfer the remainder of MBB and its successor edges to endMBB.
20270 endMBB->splice(endMBB->begin(), thisMBB,
20271 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20272 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20274 // Make offsetMBB and overflowMBB successors of thisMBB
20275 thisMBB->addSuccessor(offsetMBB);
20276 thisMBB->addSuccessor(overflowMBB);
20278 // endMBB is a successor of both offsetMBB and overflowMBB
20279 offsetMBB->addSuccessor(endMBB);
20280 overflowMBB->addSuccessor(endMBB);
20282 // Load the offset value into a register
20283 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20284 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20288 .addDisp(Disp, UseFPOffset ? 4 : 0)
20289 .addOperand(Segment)
20290 .setMemRefs(MMOBegin, MMOEnd);
20292 // Check if there is enough room left to pull this argument.
20293 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20295 .addImm(MaxOffset + 8 - ArgSizeA8);
20297 // Branch to "overflowMBB" if offset >= max
20298 // Fall through to "offsetMBB" otherwise
20299 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20300 .addMBB(overflowMBB);
20303 // In offsetMBB, emit code to use the reg_save_area.
20305 assert(OffsetReg != 0);
20307 // Read the reg_save_area address.
20308 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20309 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20314 .addOperand(Segment)
20315 .setMemRefs(MMOBegin, MMOEnd);
20317 // Zero-extend the offset
20318 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20319 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20322 .addImm(X86::sub_32bit);
20324 // Add the offset to the reg_save_area to get the final address.
20325 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20326 .addReg(OffsetReg64)
20327 .addReg(RegSaveReg);
20329 // Compute the offset for the next argument
20330 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20331 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20333 .addImm(UseFPOffset ? 16 : 8);
20335 // Store it back into the va_list.
20336 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20340 .addDisp(Disp, UseFPOffset ? 4 : 0)
20341 .addOperand(Segment)
20342 .addReg(NextOffsetReg)
20343 .setMemRefs(MMOBegin, MMOEnd);
20346 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20351 // Emit code to use overflow area
20354 // Load the overflow_area address into a register.
20355 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20356 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20361 .addOperand(Segment)
20362 .setMemRefs(MMOBegin, MMOEnd);
20364 // If we need to align it, do so. Otherwise, just copy the address
20365 // to OverflowDestReg.
20367 // Align the overflow address
20368 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20369 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20371 // aligned_addr = (addr + (align-1)) & ~(align-1)
20372 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20373 .addReg(OverflowAddrReg)
20376 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20378 .addImm(~(uint64_t)(Align-1));
20380 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20381 .addReg(OverflowAddrReg);
20384 // Compute the next overflow address after this argument.
20385 // (the overflow address should be kept 8-byte aligned)
20386 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20387 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20388 .addReg(OverflowDestReg)
20389 .addImm(ArgSizeA8);
20391 // Store the new overflow address.
20392 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20397 .addOperand(Segment)
20398 .addReg(NextAddrReg)
20399 .setMemRefs(MMOBegin, MMOEnd);
20401 // If we branched, emit the PHI to the front of endMBB.
20403 BuildMI(*endMBB, endMBB->begin(), DL,
20404 TII->get(X86::PHI), DestReg)
20405 .addReg(OffsetDestReg).addMBB(offsetMBB)
20406 .addReg(OverflowDestReg).addMBB(overflowMBB);
20409 // Erase the pseudo instruction
20410 MI->eraseFromParent();
20415 MachineBasicBlock *
20416 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20418 MachineBasicBlock *MBB) const {
20419 // Emit code to save XMM registers to the stack. The ABI says that the
20420 // number of registers to save is given in %al, so it's theoretically
20421 // possible to do an indirect jump trick to avoid saving all of them,
20422 // however this code takes a simpler approach and just executes all
20423 // of the stores if %al is non-zero. It's less code, and it's probably
20424 // easier on the hardware branch predictor, and stores aren't all that
20425 // expensive anyway.
20427 // Create the new basic blocks. One block contains all the XMM stores,
20428 // and one block is the final destination regardless of whether any
20429 // stores were performed.
20430 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20431 MachineFunction *F = MBB->getParent();
20432 MachineFunction::iterator MBBIter = MBB;
20434 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20435 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20436 F->insert(MBBIter, XMMSaveMBB);
20437 F->insert(MBBIter, EndMBB);
20439 // Transfer the remainder of MBB and its successor edges to EndMBB.
20440 EndMBB->splice(EndMBB->begin(), MBB,
20441 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20442 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20444 // The original block will now fall through to the XMM save block.
20445 MBB->addSuccessor(XMMSaveMBB);
20446 // The XMMSaveMBB will fall through to the end block.
20447 XMMSaveMBB->addSuccessor(EndMBB);
20449 // Now add the instructions.
20450 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20451 DebugLoc DL = MI->getDebugLoc();
20453 unsigned CountReg = MI->getOperand(0).getReg();
20454 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20455 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20457 if (!Subtarget->isTargetWin64()) {
20458 // If %al is 0, branch around the XMM save block.
20459 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20460 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20461 MBB->addSuccessor(EndMBB);
20464 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20465 // that was just emitted, but clearly shouldn't be "saved".
20466 assert((MI->getNumOperands() <= 3 ||
20467 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20468 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20469 && "Expected last argument to be EFLAGS");
20470 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20471 // In the XMM save block, save all the XMM argument registers.
20472 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20473 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20474 MachineMemOperand *MMO =
20475 F->getMachineMemOperand(
20476 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20477 MachineMemOperand::MOStore,
20478 /*Size=*/16, /*Align=*/16);
20479 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20480 .addFrameIndex(RegSaveFrameIndex)
20481 .addImm(/*Scale=*/1)
20482 .addReg(/*IndexReg=*/0)
20483 .addImm(/*Disp=*/Offset)
20484 .addReg(/*Segment=*/0)
20485 .addReg(MI->getOperand(i).getReg())
20486 .addMemOperand(MMO);
20489 MI->eraseFromParent(); // The pseudo instruction is gone now.
20494 // The EFLAGS operand of SelectItr might be missing a kill marker
20495 // because there were multiple uses of EFLAGS, and ISel didn't know
20496 // which to mark. Figure out whether SelectItr should have had a
20497 // kill marker, and set it if it should. Returns the correct kill
20499 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20500 MachineBasicBlock* BB,
20501 const TargetRegisterInfo* TRI) {
20502 // Scan forward through BB for a use/def of EFLAGS.
20503 MachineBasicBlock::iterator miI(std::next(SelectItr));
20504 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20505 const MachineInstr& mi = *miI;
20506 if (mi.readsRegister(X86::EFLAGS))
20508 if (mi.definesRegister(X86::EFLAGS))
20509 break; // Should have kill-flag - update below.
20512 // If we hit the end of the block, check whether EFLAGS is live into a
20514 if (miI == BB->end()) {
20515 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20516 sEnd = BB->succ_end();
20517 sItr != sEnd; ++sItr) {
20518 MachineBasicBlock* succ = *sItr;
20519 if (succ->isLiveIn(X86::EFLAGS))
20524 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20525 // out. SelectMI should have a kill flag on EFLAGS.
20526 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20530 MachineBasicBlock *
20531 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20532 MachineBasicBlock *BB) const {
20533 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20534 DebugLoc DL = MI->getDebugLoc();
20536 // To "insert" a SELECT_CC instruction, we actually have to insert the
20537 // diamond control-flow pattern. The incoming instruction knows the
20538 // destination vreg to set, the condition code register to branch on, the
20539 // true/false values to select between, and a branch opcode to use.
20540 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20541 MachineFunction::iterator It = BB;
20547 // cmpTY ccX, r1, r2
20549 // fallthrough --> copy0MBB
20550 MachineBasicBlock *thisMBB = BB;
20551 MachineFunction *F = BB->getParent();
20552 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20553 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20554 F->insert(It, copy0MBB);
20555 F->insert(It, sinkMBB);
20557 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20558 // live into the sink and copy blocks.
20559 const TargetRegisterInfo *TRI =
20560 BB->getParent()->getSubtarget().getRegisterInfo();
20561 if (!MI->killsRegister(X86::EFLAGS) &&
20562 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20563 copy0MBB->addLiveIn(X86::EFLAGS);
20564 sinkMBB->addLiveIn(X86::EFLAGS);
20567 // Transfer the remainder of BB and its successor edges to sinkMBB.
20568 sinkMBB->splice(sinkMBB->begin(), BB,
20569 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20570 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20572 // Add the true and fallthrough blocks as its successors.
20573 BB->addSuccessor(copy0MBB);
20574 BB->addSuccessor(sinkMBB);
20576 // Create the conditional branch instruction.
20578 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20579 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20582 // %FalseValue = ...
20583 // # fallthrough to sinkMBB
20584 copy0MBB->addSuccessor(sinkMBB);
20587 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20589 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20590 TII->get(X86::PHI), MI->getOperand(0).getReg())
20591 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20592 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20594 MI->eraseFromParent(); // The pseudo instruction is gone now.
20598 MachineBasicBlock *
20599 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20600 MachineBasicBlock *BB) const {
20601 MachineFunction *MF = BB->getParent();
20602 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20603 DebugLoc DL = MI->getDebugLoc();
20604 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20606 assert(MF->shouldSplitStack());
20608 const bool Is64Bit = Subtarget->is64Bit();
20609 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20611 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20612 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20615 // ... [Till the alloca]
20616 // If stacklet is not large enough, jump to mallocMBB
20619 // Allocate by subtracting from RSP
20620 // Jump to continueMBB
20623 // Allocate by call to runtime
20627 // [rest of original BB]
20630 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20631 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20632 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20634 MachineRegisterInfo &MRI = MF->getRegInfo();
20635 const TargetRegisterClass *AddrRegClass =
20636 getRegClassFor(getPointerTy());
20638 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20639 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20640 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20641 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20642 sizeVReg = MI->getOperand(1).getReg(),
20643 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20645 MachineFunction::iterator MBBIter = BB;
20648 MF->insert(MBBIter, bumpMBB);
20649 MF->insert(MBBIter, mallocMBB);
20650 MF->insert(MBBIter, continueMBB);
20652 continueMBB->splice(continueMBB->begin(), BB,
20653 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20654 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20656 // Add code to the main basic block to check if the stack limit has been hit,
20657 // and if so, jump to mallocMBB otherwise to bumpMBB.
20658 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20659 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20660 .addReg(tmpSPVReg).addReg(sizeVReg);
20661 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20662 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20663 .addReg(SPLimitVReg);
20664 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20666 // bumpMBB simply decreases the stack pointer, since we know the current
20667 // stacklet has enough space.
20668 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20669 .addReg(SPLimitVReg);
20670 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20671 .addReg(SPLimitVReg);
20672 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20674 // Calls into a routine in libgcc to allocate more space from the heap.
20675 const uint32_t *RegMask = MF->getTarget()
20676 .getSubtargetImpl()
20677 ->getRegisterInfo()
20678 ->getCallPreservedMask(CallingConv::C);
20680 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20682 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20683 .addExternalSymbol("__morestack_allocate_stack_space")
20684 .addRegMask(RegMask)
20685 .addReg(X86::RDI, RegState::Implicit)
20686 .addReg(X86::RAX, RegState::ImplicitDefine);
20687 } else if (Is64Bit) {
20688 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20690 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20691 .addExternalSymbol("__morestack_allocate_stack_space")
20692 .addRegMask(RegMask)
20693 .addReg(X86::EDI, RegState::Implicit)
20694 .addReg(X86::EAX, RegState::ImplicitDefine);
20696 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20698 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20699 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20700 .addExternalSymbol("__morestack_allocate_stack_space")
20701 .addRegMask(RegMask)
20702 .addReg(X86::EAX, RegState::ImplicitDefine);
20706 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20709 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20710 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20711 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20713 // Set up the CFG correctly.
20714 BB->addSuccessor(bumpMBB);
20715 BB->addSuccessor(mallocMBB);
20716 mallocMBB->addSuccessor(continueMBB);
20717 bumpMBB->addSuccessor(continueMBB);
20719 // Take care of the PHI nodes.
20720 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20721 MI->getOperand(0).getReg())
20722 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20723 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20725 // Delete the original pseudo instruction.
20726 MI->eraseFromParent();
20729 return continueMBB;
20732 MachineBasicBlock *
20733 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20734 MachineBasicBlock *BB) const {
20735 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20736 DebugLoc DL = MI->getDebugLoc();
20738 assert(!Subtarget->isTargetMacho());
20740 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20741 // non-trivial part is impdef of ESP.
20743 if (Subtarget->isTargetWin64()) {
20744 if (Subtarget->isTargetCygMing()) {
20745 // ___chkstk(Mingw64):
20746 // Clobbers R10, R11, RAX and EFLAGS.
20748 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20749 .addExternalSymbol("___chkstk")
20750 .addReg(X86::RAX, RegState::Implicit)
20751 .addReg(X86::RSP, RegState::Implicit)
20752 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20753 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20754 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20756 // __chkstk(MSVCRT): does not update stack pointer.
20757 // Clobbers R10, R11 and EFLAGS.
20758 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20759 .addExternalSymbol("__chkstk")
20760 .addReg(X86::RAX, RegState::Implicit)
20761 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20762 // RAX has the offset to be subtracted from RSP.
20763 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20768 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20769 Subtarget->isTargetWindowsItanium())
20773 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20774 .addExternalSymbol(StackProbeSymbol)
20775 .addReg(X86::EAX, RegState::Implicit)
20776 .addReg(X86::ESP, RegState::Implicit)
20777 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20778 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20779 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20782 MI->eraseFromParent(); // The pseudo instruction is gone now.
20786 MachineBasicBlock *
20787 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20788 MachineBasicBlock *BB) const {
20789 // This is pretty easy. We're taking the value that we received from
20790 // our load from the relocation, sticking it in either RDI (x86-64)
20791 // or EAX and doing an indirect call. The return value will then
20792 // be in the normal return register.
20793 MachineFunction *F = BB->getParent();
20794 const X86InstrInfo *TII =
20795 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20796 DebugLoc DL = MI->getDebugLoc();
20798 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20799 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20801 // Get a register mask for the lowered call.
20802 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20803 // proper register mask.
20804 const uint32_t *RegMask = F->getTarget()
20805 .getSubtargetImpl()
20806 ->getRegisterInfo()
20807 ->getCallPreservedMask(CallingConv::C);
20808 if (Subtarget->is64Bit()) {
20809 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20810 TII->get(X86::MOV64rm), X86::RDI)
20812 .addImm(0).addReg(0)
20813 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20814 MI->getOperand(3).getTargetFlags())
20816 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20817 addDirectMem(MIB, X86::RDI);
20818 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20819 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20820 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20821 TII->get(X86::MOV32rm), X86::EAX)
20823 .addImm(0).addReg(0)
20824 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20825 MI->getOperand(3).getTargetFlags())
20827 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20828 addDirectMem(MIB, X86::EAX);
20829 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20831 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20832 TII->get(X86::MOV32rm), X86::EAX)
20833 .addReg(TII->getGlobalBaseReg(F))
20834 .addImm(0).addReg(0)
20835 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20836 MI->getOperand(3).getTargetFlags())
20838 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20839 addDirectMem(MIB, X86::EAX);
20840 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20843 MI->eraseFromParent(); // The pseudo instruction is gone now.
20847 MachineBasicBlock *
20848 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20849 MachineBasicBlock *MBB) const {
20850 DebugLoc DL = MI->getDebugLoc();
20851 MachineFunction *MF = MBB->getParent();
20852 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20853 MachineRegisterInfo &MRI = MF->getRegInfo();
20855 const BasicBlock *BB = MBB->getBasicBlock();
20856 MachineFunction::iterator I = MBB;
20859 // Memory Reference
20860 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20861 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20864 unsigned MemOpndSlot = 0;
20866 unsigned CurOp = 0;
20868 DstReg = MI->getOperand(CurOp++).getReg();
20869 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20870 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20871 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20872 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20874 MemOpndSlot = CurOp;
20876 MVT PVT = getPointerTy();
20877 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20878 "Invalid Pointer Size!");
20880 // For v = setjmp(buf), we generate
20883 // buf[LabelOffset] = restoreMBB
20884 // SjLjSetup restoreMBB
20890 // v = phi(main, restore)
20895 MachineBasicBlock *thisMBB = MBB;
20896 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20897 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20898 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20899 MF->insert(I, mainMBB);
20900 MF->insert(I, sinkMBB);
20901 MF->push_back(restoreMBB);
20903 MachineInstrBuilder MIB;
20905 // Transfer the remainder of BB and its successor edges to sinkMBB.
20906 sinkMBB->splice(sinkMBB->begin(), MBB,
20907 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20908 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20911 unsigned PtrStoreOpc = 0;
20912 unsigned LabelReg = 0;
20913 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20914 Reloc::Model RM = MF->getTarget().getRelocationModel();
20915 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20916 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20918 // Prepare IP either in reg or imm.
20919 if (!UseImmLabel) {
20920 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20921 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20922 LabelReg = MRI.createVirtualRegister(PtrRC);
20923 if (Subtarget->is64Bit()) {
20924 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20928 .addMBB(restoreMBB)
20931 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20932 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20933 .addReg(XII->getGlobalBaseReg(MF))
20936 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20940 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20942 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20943 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20944 if (i == X86::AddrDisp)
20945 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20947 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20950 MIB.addReg(LabelReg);
20952 MIB.addMBB(restoreMBB);
20953 MIB.setMemRefs(MMOBegin, MMOEnd);
20955 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20956 .addMBB(restoreMBB);
20958 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20959 MF->getSubtarget().getRegisterInfo());
20960 MIB.addRegMask(RegInfo->getNoPreservedMask());
20961 thisMBB->addSuccessor(mainMBB);
20962 thisMBB->addSuccessor(restoreMBB);
20966 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20967 mainMBB->addSuccessor(sinkMBB);
20970 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20971 TII->get(X86::PHI), DstReg)
20972 .addReg(mainDstReg).addMBB(mainMBB)
20973 .addReg(restoreDstReg).addMBB(restoreMBB);
20976 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20977 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20978 restoreMBB->addSuccessor(sinkMBB);
20980 MI->eraseFromParent();
20984 MachineBasicBlock *
20985 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20986 MachineBasicBlock *MBB) const {
20987 DebugLoc DL = MI->getDebugLoc();
20988 MachineFunction *MF = MBB->getParent();
20989 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20990 MachineRegisterInfo &MRI = MF->getRegInfo();
20992 // Memory Reference
20993 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20994 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20996 MVT PVT = getPointerTy();
20997 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20998 "Invalid Pointer Size!");
21000 const TargetRegisterClass *RC =
21001 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21002 unsigned Tmp = MRI.createVirtualRegister(RC);
21003 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21004 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21005 MF->getSubtarget().getRegisterInfo());
21006 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21007 unsigned SP = RegInfo->getStackRegister();
21009 MachineInstrBuilder MIB;
21011 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21012 const int64_t SPOffset = 2 * PVT.getStoreSize();
21014 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21015 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21018 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21019 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21020 MIB.addOperand(MI->getOperand(i));
21021 MIB.setMemRefs(MMOBegin, MMOEnd);
21023 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21024 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21025 if (i == X86::AddrDisp)
21026 MIB.addDisp(MI->getOperand(i), LabelOffset);
21028 MIB.addOperand(MI->getOperand(i));
21030 MIB.setMemRefs(MMOBegin, MMOEnd);
21032 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21033 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21034 if (i == X86::AddrDisp)
21035 MIB.addDisp(MI->getOperand(i), SPOffset);
21037 MIB.addOperand(MI->getOperand(i));
21039 MIB.setMemRefs(MMOBegin, MMOEnd);
21041 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21043 MI->eraseFromParent();
21047 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21048 // accumulator loops. Writing back to the accumulator allows the coalescer
21049 // to remove extra copies in the loop.
21050 MachineBasicBlock *
21051 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21052 MachineBasicBlock *MBB) const {
21053 MachineOperand &AddendOp = MI->getOperand(3);
21055 // Bail out early if the addend isn't a register - we can't switch these.
21056 if (!AddendOp.isReg())
21059 MachineFunction &MF = *MBB->getParent();
21060 MachineRegisterInfo &MRI = MF.getRegInfo();
21062 // Check whether the addend is defined by a PHI:
21063 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21064 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21065 if (!AddendDef.isPHI())
21068 // Look for the following pattern:
21070 // %addend = phi [%entry, 0], [%loop, %result]
21072 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21076 // %addend = phi [%entry, 0], [%loop, %result]
21078 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21080 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21081 assert(AddendDef.getOperand(i).isReg());
21082 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21083 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21084 if (&PHISrcInst == MI) {
21085 // Found a matching instruction.
21086 unsigned NewFMAOpc = 0;
21087 switch (MI->getOpcode()) {
21088 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21089 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21090 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21091 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21092 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21093 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21094 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21095 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21096 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21097 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21098 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21099 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21100 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21101 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21102 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21103 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21104 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21105 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21106 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21107 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21109 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21110 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21111 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21112 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21113 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21114 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21115 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21116 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21117 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21118 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21119 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21120 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21121 default: llvm_unreachable("Unrecognized FMA variant.");
21124 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21125 MachineInstrBuilder MIB =
21126 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21127 .addOperand(MI->getOperand(0))
21128 .addOperand(MI->getOperand(3))
21129 .addOperand(MI->getOperand(2))
21130 .addOperand(MI->getOperand(1));
21131 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21132 MI->eraseFromParent();
21139 MachineBasicBlock *
21140 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21141 MachineBasicBlock *BB) const {
21142 switch (MI->getOpcode()) {
21143 default: llvm_unreachable("Unexpected instr type to insert");
21144 case X86::TAILJMPd64:
21145 case X86::TAILJMPr64:
21146 case X86::TAILJMPm64:
21147 llvm_unreachable("TAILJMP64 would not be touched here.");
21148 case X86::TCRETURNdi64:
21149 case X86::TCRETURNri64:
21150 case X86::TCRETURNmi64:
21152 case X86::WIN_ALLOCA:
21153 return EmitLoweredWinAlloca(MI, BB);
21154 case X86::SEG_ALLOCA_32:
21155 case X86::SEG_ALLOCA_64:
21156 return EmitLoweredSegAlloca(MI, BB);
21157 case X86::TLSCall_32:
21158 case X86::TLSCall_64:
21159 return EmitLoweredTLSCall(MI, BB);
21160 case X86::CMOV_GR8:
21161 case X86::CMOV_FR32:
21162 case X86::CMOV_FR64:
21163 case X86::CMOV_V4F32:
21164 case X86::CMOV_V2F64:
21165 case X86::CMOV_V2I64:
21166 case X86::CMOV_V8F32:
21167 case X86::CMOV_V4F64:
21168 case X86::CMOV_V4I64:
21169 case X86::CMOV_V16F32:
21170 case X86::CMOV_V8F64:
21171 case X86::CMOV_V8I64:
21172 case X86::CMOV_GR16:
21173 case X86::CMOV_GR32:
21174 case X86::CMOV_RFP32:
21175 case X86::CMOV_RFP64:
21176 case X86::CMOV_RFP80:
21177 return EmitLoweredSelect(MI, BB);
21179 case X86::FP32_TO_INT16_IN_MEM:
21180 case X86::FP32_TO_INT32_IN_MEM:
21181 case X86::FP32_TO_INT64_IN_MEM:
21182 case X86::FP64_TO_INT16_IN_MEM:
21183 case X86::FP64_TO_INT32_IN_MEM:
21184 case X86::FP64_TO_INT64_IN_MEM:
21185 case X86::FP80_TO_INT16_IN_MEM:
21186 case X86::FP80_TO_INT32_IN_MEM:
21187 case X86::FP80_TO_INT64_IN_MEM: {
21188 MachineFunction *F = BB->getParent();
21189 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21190 DebugLoc DL = MI->getDebugLoc();
21192 // Change the floating point control register to use "round towards zero"
21193 // mode when truncating to an integer value.
21194 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21195 addFrameReference(BuildMI(*BB, MI, DL,
21196 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21198 // Load the old value of the high byte of the control word...
21200 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21201 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21204 // Set the high part to be round to zero...
21205 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21208 // Reload the modified control word now...
21209 addFrameReference(BuildMI(*BB, MI, DL,
21210 TII->get(X86::FLDCW16m)), CWFrameIdx);
21212 // Restore the memory image of control word to original value
21213 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21216 // Get the X86 opcode to use.
21218 switch (MI->getOpcode()) {
21219 default: llvm_unreachable("illegal opcode!");
21220 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21221 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21222 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21223 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21224 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21225 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21226 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21227 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21228 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21232 MachineOperand &Op = MI->getOperand(0);
21234 AM.BaseType = X86AddressMode::RegBase;
21235 AM.Base.Reg = Op.getReg();
21237 AM.BaseType = X86AddressMode::FrameIndexBase;
21238 AM.Base.FrameIndex = Op.getIndex();
21240 Op = MI->getOperand(1);
21242 AM.Scale = Op.getImm();
21243 Op = MI->getOperand(2);
21245 AM.IndexReg = Op.getImm();
21246 Op = MI->getOperand(3);
21247 if (Op.isGlobal()) {
21248 AM.GV = Op.getGlobal();
21250 AM.Disp = Op.getImm();
21252 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21253 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21255 // Reload the original control word now.
21256 addFrameReference(BuildMI(*BB, MI, DL,
21257 TII->get(X86::FLDCW16m)), CWFrameIdx);
21259 MI->eraseFromParent(); // The pseudo instruction is gone now.
21262 // String/text processing lowering.
21263 case X86::PCMPISTRM128REG:
21264 case X86::VPCMPISTRM128REG:
21265 case X86::PCMPISTRM128MEM:
21266 case X86::VPCMPISTRM128MEM:
21267 case X86::PCMPESTRM128REG:
21268 case X86::VPCMPESTRM128REG:
21269 case X86::PCMPESTRM128MEM:
21270 case X86::VPCMPESTRM128MEM:
21271 assert(Subtarget->hasSSE42() &&
21272 "Target must have SSE4.2 or AVX features enabled");
21273 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21275 // String/text processing lowering.
21276 case X86::PCMPISTRIREG:
21277 case X86::VPCMPISTRIREG:
21278 case X86::PCMPISTRIMEM:
21279 case X86::VPCMPISTRIMEM:
21280 case X86::PCMPESTRIREG:
21281 case X86::VPCMPESTRIREG:
21282 case X86::PCMPESTRIMEM:
21283 case X86::VPCMPESTRIMEM:
21284 assert(Subtarget->hasSSE42() &&
21285 "Target must have SSE4.2 or AVX features enabled");
21286 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21288 // Thread synchronization.
21290 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21295 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21297 case X86::VASTART_SAVE_XMM_REGS:
21298 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21300 case X86::VAARG_64:
21301 return EmitVAARG64WithCustomInserter(MI, BB);
21303 case X86::EH_SjLj_SetJmp32:
21304 case X86::EH_SjLj_SetJmp64:
21305 return emitEHSjLjSetJmp(MI, BB);
21307 case X86::EH_SjLj_LongJmp32:
21308 case X86::EH_SjLj_LongJmp64:
21309 return emitEHSjLjLongJmp(MI, BB);
21311 case TargetOpcode::STACKMAP:
21312 case TargetOpcode::PATCHPOINT:
21313 return emitPatchPoint(MI, BB);
21315 case X86::VFMADDPDr213r:
21316 case X86::VFMADDPSr213r:
21317 case X86::VFMADDSDr213r:
21318 case X86::VFMADDSSr213r:
21319 case X86::VFMSUBPDr213r:
21320 case X86::VFMSUBPSr213r:
21321 case X86::VFMSUBSDr213r:
21322 case X86::VFMSUBSSr213r:
21323 case X86::VFNMADDPDr213r:
21324 case X86::VFNMADDPSr213r:
21325 case X86::VFNMADDSDr213r:
21326 case X86::VFNMADDSSr213r:
21327 case X86::VFNMSUBPDr213r:
21328 case X86::VFNMSUBPSr213r:
21329 case X86::VFNMSUBSDr213r:
21330 case X86::VFNMSUBSSr213r:
21331 case X86::VFMADDSUBPDr213r:
21332 case X86::VFMADDSUBPSr213r:
21333 case X86::VFMSUBADDPDr213r:
21334 case X86::VFMSUBADDPSr213r:
21335 case X86::VFMADDPDr213rY:
21336 case X86::VFMADDPSr213rY:
21337 case X86::VFMSUBPDr213rY:
21338 case X86::VFMSUBPSr213rY:
21339 case X86::VFNMADDPDr213rY:
21340 case X86::VFNMADDPSr213rY:
21341 case X86::VFNMSUBPDr213rY:
21342 case X86::VFNMSUBPSr213rY:
21343 case X86::VFMADDSUBPDr213rY:
21344 case X86::VFMADDSUBPSr213rY:
21345 case X86::VFMSUBADDPDr213rY:
21346 case X86::VFMSUBADDPSr213rY:
21347 return emitFMA3Instr(MI, BB);
21351 //===----------------------------------------------------------------------===//
21352 // X86 Optimization Hooks
21353 //===----------------------------------------------------------------------===//
21355 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21358 const SelectionDAG &DAG,
21359 unsigned Depth) const {
21360 unsigned BitWidth = KnownZero.getBitWidth();
21361 unsigned Opc = Op.getOpcode();
21362 assert((Opc >= ISD::BUILTIN_OP_END ||
21363 Opc == ISD::INTRINSIC_WO_CHAIN ||
21364 Opc == ISD::INTRINSIC_W_CHAIN ||
21365 Opc == ISD::INTRINSIC_VOID) &&
21366 "Should use MaskedValueIsZero if you don't know whether Op"
21367 " is a target node!");
21369 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21383 // These nodes' second result is a boolean.
21384 if (Op.getResNo() == 0)
21387 case X86ISD::SETCC:
21388 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21390 case ISD::INTRINSIC_WO_CHAIN: {
21391 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21392 unsigned NumLoBits = 0;
21395 case Intrinsic::x86_sse_movmsk_ps:
21396 case Intrinsic::x86_avx_movmsk_ps_256:
21397 case Intrinsic::x86_sse2_movmsk_pd:
21398 case Intrinsic::x86_avx_movmsk_pd_256:
21399 case Intrinsic::x86_mmx_pmovmskb:
21400 case Intrinsic::x86_sse2_pmovmskb_128:
21401 case Intrinsic::x86_avx2_pmovmskb: {
21402 // High bits of movmskp{s|d}, pmovmskb are known zero.
21404 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21405 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21406 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21407 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21408 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21409 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21410 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21411 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21413 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21422 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21424 const SelectionDAG &,
21425 unsigned Depth) const {
21426 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21427 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21428 return Op.getValueType().getScalarType().getSizeInBits();
21434 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21435 /// node is a GlobalAddress + offset.
21436 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21437 const GlobalValue* &GA,
21438 int64_t &Offset) const {
21439 if (N->getOpcode() == X86ISD::Wrapper) {
21440 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21441 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21442 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21446 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21449 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21450 /// same as extracting the high 128-bit part of 256-bit vector and then
21451 /// inserting the result into the low part of a new 256-bit vector
21452 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21453 EVT VT = SVOp->getValueType(0);
21454 unsigned NumElems = VT.getVectorNumElements();
21456 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21457 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21458 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21459 SVOp->getMaskElt(j) >= 0)
21465 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21466 /// same as extracting the low 128-bit part of 256-bit vector and then
21467 /// inserting the result into the high part of a new 256-bit vector
21468 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21469 EVT VT = SVOp->getValueType(0);
21470 unsigned NumElems = VT.getVectorNumElements();
21472 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21473 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21474 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21475 SVOp->getMaskElt(j) >= 0)
21481 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21482 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21483 TargetLowering::DAGCombinerInfo &DCI,
21484 const X86Subtarget* Subtarget) {
21486 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21487 SDValue V1 = SVOp->getOperand(0);
21488 SDValue V2 = SVOp->getOperand(1);
21489 EVT VT = SVOp->getValueType(0);
21490 unsigned NumElems = VT.getVectorNumElements();
21492 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21493 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21497 // V UNDEF BUILD_VECTOR UNDEF
21499 // CONCAT_VECTOR CONCAT_VECTOR
21502 // RESULT: V + zero extended
21504 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21505 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21506 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21509 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21512 // To match the shuffle mask, the first half of the mask should
21513 // be exactly the first vector, and all the rest a splat with the
21514 // first element of the second one.
21515 for (unsigned i = 0; i != NumElems/2; ++i)
21516 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21517 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21520 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21521 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21522 if (Ld->hasNUsesOfValue(1, 0)) {
21523 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21524 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21526 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21528 Ld->getPointerInfo(),
21529 Ld->getAlignment(),
21530 false/*isVolatile*/, true/*ReadMem*/,
21531 false/*WriteMem*/);
21533 // Make sure the newly-created LOAD is in the same position as Ld in
21534 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21535 // and update uses of Ld's output chain to use the TokenFactor.
21536 if (Ld->hasAnyUseOfValue(1)) {
21537 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21538 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21539 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21540 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21541 SDValue(ResNode.getNode(), 1));
21544 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21548 // Emit a zeroed vector and insert the desired subvector on its
21550 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21551 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21552 return DCI.CombineTo(N, InsV);
21555 //===--------------------------------------------------------------------===//
21556 // Combine some shuffles into subvector extracts and inserts:
21559 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21560 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21561 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21562 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21563 return DCI.CombineTo(N, InsV);
21566 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21567 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21568 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21569 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21570 return DCI.CombineTo(N, InsV);
21576 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21579 /// This is the leaf of the recursive combinine below. When we have found some
21580 /// chain of single-use x86 shuffle instructions and accumulated the combined
21581 /// shuffle mask represented by them, this will try to pattern match that mask
21582 /// into either a single instruction if there is a special purpose instruction
21583 /// for this operation, or into a PSHUFB instruction which is a fully general
21584 /// instruction but should only be used to replace chains over a certain depth.
21585 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21586 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21587 TargetLowering::DAGCombinerInfo &DCI,
21588 const X86Subtarget *Subtarget) {
21589 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21591 // Find the operand that enters the chain. Note that multiple uses are OK
21592 // here, we're not going to remove the operand we find.
21593 SDValue Input = Op.getOperand(0);
21594 while (Input.getOpcode() == ISD::BITCAST)
21595 Input = Input.getOperand(0);
21597 MVT VT = Input.getSimpleValueType();
21598 MVT RootVT = Root.getSimpleValueType();
21601 // Just remove no-op shuffle masks.
21602 if (Mask.size() == 1) {
21603 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21608 // Use the float domain if the operand type is a floating point type.
21609 bool FloatDomain = VT.isFloatingPoint();
21611 // For floating point shuffles, we don't have free copies in the shuffle
21612 // instructions or the ability to load as part of the instruction, so
21613 // canonicalize their shuffles to UNPCK or MOV variants.
21615 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21616 // vectors because it can have a load folded into it that UNPCK cannot. This
21617 // doesn't preclude something switching to the shorter encoding post-RA.
21619 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21620 bool Lo = Mask.equals(0, 0);
21623 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21624 // is no slower than UNPCKLPD but has the option to fold the input operand
21625 // into even an unaligned memory load.
21626 if (Lo && Subtarget->hasSSE3()) {
21627 Shuffle = X86ISD::MOVDDUP;
21628 ShuffleVT = MVT::v2f64;
21630 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21631 // than the UNPCK variants.
21632 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21633 ShuffleVT = MVT::v4f32;
21635 if (Depth == 1 && Root->getOpcode() == Shuffle)
21636 return false; // Nothing to do!
21637 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21638 DCI.AddToWorklist(Op.getNode());
21639 if (Shuffle == X86ISD::MOVDDUP)
21640 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21642 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21643 DCI.AddToWorklist(Op.getNode());
21644 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21648 if (Subtarget->hasSSE3() &&
21649 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21650 bool Lo = Mask.equals(0, 0, 2, 2);
21651 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21652 MVT ShuffleVT = MVT::v4f32;
21653 if (Depth == 1 && Root->getOpcode() == Shuffle)
21654 return false; // Nothing to do!
21655 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21656 DCI.AddToWorklist(Op.getNode());
21657 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21658 DCI.AddToWorklist(Op.getNode());
21659 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21663 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21664 bool Lo = Mask.equals(0, 0, 1, 1);
21665 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21666 MVT ShuffleVT = MVT::v4f32;
21667 if (Depth == 1 && Root->getOpcode() == Shuffle)
21668 return false; // Nothing to do!
21669 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21670 DCI.AddToWorklist(Op.getNode());
21671 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21672 DCI.AddToWorklist(Op.getNode());
21673 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21679 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21680 // variants as none of these have single-instruction variants that are
21681 // superior to the UNPCK formulation.
21682 if (!FloatDomain &&
21683 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21684 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21685 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21686 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21688 bool Lo = Mask[0] == 0;
21689 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21690 if (Depth == 1 && Root->getOpcode() == Shuffle)
21691 return false; // Nothing to do!
21693 switch (Mask.size()) {
21695 ShuffleVT = MVT::v8i16;
21698 ShuffleVT = MVT::v16i8;
21701 llvm_unreachable("Impossible mask size!");
21703 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21704 DCI.AddToWorklist(Op.getNode());
21705 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21706 DCI.AddToWorklist(Op.getNode());
21707 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21712 // Don't try to re-form single instruction chains under any circumstances now
21713 // that we've done encoding canonicalization for them.
21717 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21718 // can replace them with a single PSHUFB instruction profitably. Intel's
21719 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21720 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21721 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21722 SmallVector<SDValue, 16> PSHUFBMask;
21723 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21724 int Ratio = 16 / Mask.size();
21725 for (unsigned i = 0; i < 16; ++i) {
21726 if (Mask[i / Ratio] == SM_SentinelUndef) {
21727 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21730 int M = Mask[i / Ratio] != SM_SentinelZero
21731 ? Ratio * Mask[i / Ratio] + i % Ratio
21733 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21735 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21736 DCI.AddToWorklist(Op.getNode());
21737 SDValue PSHUFBMaskOp =
21738 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21739 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21740 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21741 DCI.AddToWorklist(Op.getNode());
21742 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21747 // Failed to find any combines.
21751 /// \brief Fully generic combining of x86 shuffle instructions.
21753 /// This should be the last combine run over the x86 shuffle instructions. Once
21754 /// they have been fully optimized, this will recursively consider all chains
21755 /// of single-use shuffle instructions, build a generic model of the cumulative
21756 /// shuffle operation, and check for simpler instructions which implement this
21757 /// operation. We use this primarily for two purposes:
21759 /// 1) Collapse generic shuffles to specialized single instructions when
21760 /// equivalent. In most cases, this is just an encoding size win, but
21761 /// sometimes we will collapse multiple generic shuffles into a single
21762 /// special-purpose shuffle.
21763 /// 2) Look for sequences of shuffle instructions with 3 or more total
21764 /// instructions, and replace them with the slightly more expensive SSSE3
21765 /// PSHUFB instruction if available. We do this as the last combining step
21766 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21767 /// a suitable short sequence of other instructions. The PHUFB will either
21768 /// use a register or have to read from memory and so is slightly (but only
21769 /// slightly) more expensive than the other shuffle instructions.
21771 /// Because this is inherently a quadratic operation (for each shuffle in
21772 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21773 /// This should never be an issue in practice as the shuffle lowering doesn't
21774 /// produce sequences of more than 8 instructions.
21776 /// FIXME: We will currently miss some cases where the redundant shuffling
21777 /// would simplify under the threshold for PSHUFB formation because of
21778 /// combine-ordering. To fix this, we should do the redundant instruction
21779 /// combining in this recursive walk.
21780 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21781 ArrayRef<int> RootMask,
21782 int Depth, bool HasPSHUFB,
21784 TargetLowering::DAGCombinerInfo &DCI,
21785 const X86Subtarget *Subtarget) {
21786 // Bound the depth of our recursive combine because this is ultimately
21787 // quadratic in nature.
21791 // Directly rip through bitcasts to find the underlying operand.
21792 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21793 Op = Op.getOperand(0);
21795 MVT VT = Op.getSimpleValueType();
21796 if (!VT.isVector())
21797 return false; // Bail if we hit a non-vector.
21798 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21799 // version should be added.
21800 if (VT.getSizeInBits() != 128)
21803 assert(Root.getSimpleValueType().isVector() &&
21804 "Shuffles operate on vector types!");
21805 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21806 "Can only combine shuffles of the same vector register size.");
21808 if (!isTargetShuffle(Op.getOpcode()))
21810 SmallVector<int, 16> OpMask;
21812 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21813 // We only can combine unary shuffles which we can decode the mask for.
21814 if (!HaveMask || !IsUnary)
21817 assert(VT.getVectorNumElements() == OpMask.size() &&
21818 "Different mask size from vector size!");
21819 assert(((RootMask.size() > OpMask.size() &&
21820 RootMask.size() % OpMask.size() == 0) ||
21821 (OpMask.size() > RootMask.size() &&
21822 OpMask.size() % RootMask.size() == 0) ||
21823 OpMask.size() == RootMask.size()) &&
21824 "The smaller number of elements must divide the larger.");
21825 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21826 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21827 assert(((RootRatio == 1 && OpRatio == 1) ||
21828 (RootRatio == 1) != (OpRatio == 1)) &&
21829 "Must not have a ratio for both incoming and op masks!");
21831 SmallVector<int, 16> Mask;
21832 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21834 // Merge this shuffle operation's mask into our accumulated mask. Note that
21835 // this shuffle's mask will be the first applied to the input, followed by the
21836 // root mask to get us all the way to the root value arrangement. The reason
21837 // for this order is that we are recursing up the operation chain.
21838 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21839 int RootIdx = i / RootRatio;
21840 if (RootMask[RootIdx] < 0) {
21841 // This is a zero or undef lane, we're done.
21842 Mask.push_back(RootMask[RootIdx]);
21846 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21847 int OpIdx = RootMaskedIdx / OpRatio;
21848 if (OpMask[OpIdx] < 0) {
21849 // The incoming lanes are zero or undef, it doesn't matter which ones we
21851 Mask.push_back(OpMask[OpIdx]);
21855 // Ok, we have non-zero lanes, map them through.
21856 Mask.push_back(OpMask[OpIdx] * OpRatio +
21857 RootMaskedIdx % OpRatio);
21860 // See if we can recurse into the operand to combine more things.
21861 switch (Op.getOpcode()) {
21862 case X86ISD::PSHUFB:
21864 case X86ISD::PSHUFD:
21865 case X86ISD::PSHUFHW:
21866 case X86ISD::PSHUFLW:
21867 if (Op.getOperand(0).hasOneUse() &&
21868 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21869 HasPSHUFB, DAG, DCI, Subtarget))
21873 case X86ISD::UNPCKL:
21874 case X86ISD::UNPCKH:
21875 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21876 // We can't check for single use, we have to check that this shuffle is the only user.
21877 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21878 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21879 HasPSHUFB, DAG, DCI, Subtarget))
21884 // Minor canonicalization of the accumulated shuffle mask to make it easier
21885 // to match below. All this does is detect masks with squential pairs of
21886 // elements, and shrink them to the half-width mask. It does this in a loop
21887 // so it will reduce the size of the mask to the minimal width mask which
21888 // performs an equivalent shuffle.
21889 SmallVector<int, 16> WidenedMask;
21890 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21891 Mask = std::move(WidenedMask);
21892 WidenedMask.clear();
21895 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21899 /// \brief Get the PSHUF-style mask from PSHUF node.
21901 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21902 /// PSHUF-style masks that can be reused with such instructions.
21903 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21904 SmallVector<int, 4> Mask;
21906 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21910 switch (N.getOpcode()) {
21911 case X86ISD::PSHUFD:
21913 case X86ISD::PSHUFLW:
21916 case X86ISD::PSHUFHW:
21917 Mask.erase(Mask.begin(), Mask.begin() + 4);
21918 for (int &M : Mask)
21922 llvm_unreachable("No valid shuffle instruction found!");
21926 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21928 /// We walk up the chain and look for a combinable shuffle, skipping over
21929 /// shuffles that we could hoist this shuffle's transformation past without
21930 /// altering anything.
21932 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21934 TargetLowering::DAGCombinerInfo &DCI) {
21935 assert(N.getOpcode() == X86ISD::PSHUFD &&
21936 "Called with something other than an x86 128-bit half shuffle!");
21939 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21940 // of the shuffles in the chain so that we can form a fresh chain to replace
21942 SmallVector<SDValue, 8> Chain;
21943 SDValue V = N.getOperand(0);
21944 for (; V.hasOneUse(); V = V.getOperand(0)) {
21945 switch (V.getOpcode()) {
21947 return SDValue(); // Nothing combined!
21950 // Skip bitcasts as we always know the type for the target specific
21954 case X86ISD::PSHUFD:
21955 // Found another dword shuffle.
21958 case X86ISD::PSHUFLW:
21959 // Check that the low words (being shuffled) are the identity in the
21960 // dword shuffle, and the high words are self-contained.
21961 if (Mask[0] != 0 || Mask[1] != 1 ||
21962 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21965 Chain.push_back(V);
21968 case X86ISD::PSHUFHW:
21969 // Check that the high words (being shuffled) are the identity in the
21970 // dword shuffle, and the low words are self-contained.
21971 if (Mask[2] != 2 || Mask[3] != 3 ||
21972 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21975 Chain.push_back(V);
21978 case X86ISD::UNPCKL:
21979 case X86ISD::UNPCKH:
21980 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21981 // shuffle into a preceding word shuffle.
21982 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21985 // Search for a half-shuffle which we can combine with.
21986 unsigned CombineOp =
21987 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21988 if (V.getOperand(0) != V.getOperand(1) ||
21989 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21991 Chain.push_back(V);
21992 V = V.getOperand(0);
21994 switch (V.getOpcode()) {
21996 return SDValue(); // Nothing to combine.
21998 case X86ISD::PSHUFLW:
21999 case X86ISD::PSHUFHW:
22000 if (V.getOpcode() == CombineOp)
22003 Chain.push_back(V);
22007 V = V.getOperand(0);
22011 } while (V.hasOneUse());
22014 // Break out of the loop if we break out of the switch.
22018 if (!V.hasOneUse())
22019 // We fell out of the loop without finding a viable combining instruction.
22022 // Merge this node's mask and our incoming mask.
22023 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22024 for (int &M : Mask)
22026 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22027 getV4X86ShuffleImm8ForMask(Mask, DAG));
22029 // Rebuild the chain around this new shuffle.
22030 while (!Chain.empty()) {
22031 SDValue W = Chain.pop_back_val();
22033 if (V.getValueType() != W.getOperand(0).getValueType())
22034 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22036 switch (W.getOpcode()) {
22038 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22040 case X86ISD::UNPCKL:
22041 case X86ISD::UNPCKH:
22042 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22045 case X86ISD::PSHUFD:
22046 case X86ISD::PSHUFLW:
22047 case X86ISD::PSHUFHW:
22048 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22052 if (V.getValueType() != N.getValueType())
22053 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22055 // Return the new chain to replace N.
22059 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22061 /// We walk up the chain, skipping shuffles of the other half and looking
22062 /// through shuffles which switch halves trying to find a shuffle of the same
22063 /// pair of dwords.
22064 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22066 TargetLowering::DAGCombinerInfo &DCI) {
22068 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22069 "Called with something other than an x86 128-bit half shuffle!");
22071 unsigned CombineOpcode = N.getOpcode();
22073 // Walk up a single-use chain looking for a combinable shuffle.
22074 SDValue V = N.getOperand(0);
22075 for (; V.hasOneUse(); V = V.getOperand(0)) {
22076 switch (V.getOpcode()) {
22078 return false; // Nothing combined!
22081 // Skip bitcasts as we always know the type for the target specific
22085 case X86ISD::PSHUFLW:
22086 case X86ISD::PSHUFHW:
22087 if (V.getOpcode() == CombineOpcode)
22090 // Other-half shuffles are no-ops.
22093 // Break out of the loop if we break out of the switch.
22097 if (!V.hasOneUse())
22098 // We fell out of the loop without finding a viable combining instruction.
22101 // Combine away the bottom node as its shuffle will be accumulated into
22102 // a preceding shuffle.
22103 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22105 // Record the old value.
22108 // Merge this node's mask and our incoming mask (adjusted to account for all
22109 // the pshufd instructions encountered).
22110 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22111 for (int &M : Mask)
22113 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22114 getV4X86ShuffleImm8ForMask(Mask, DAG));
22116 // Check that the shuffles didn't cancel each other out. If not, we need to
22117 // combine to the new one.
22119 // Replace the combinable shuffle with the combined one, updating all users
22120 // so that we re-evaluate the chain here.
22121 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22126 /// \brief Try to combine x86 target specific shuffles.
22127 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22128 TargetLowering::DAGCombinerInfo &DCI,
22129 const X86Subtarget *Subtarget) {
22131 MVT VT = N.getSimpleValueType();
22132 SmallVector<int, 4> Mask;
22134 switch (N.getOpcode()) {
22135 case X86ISD::PSHUFD:
22136 case X86ISD::PSHUFLW:
22137 case X86ISD::PSHUFHW:
22138 Mask = getPSHUFShuffleMask(N);
22139 assert(Mask.size() == 4);
22145 // Nuke no-op shuffles that show up after combining.
22146 if (isNoopShuffleMask(Mask))
22147 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22149 // Look for simplifications involving one or two shuffle instructions.
22150 SDValue V = N.getOperand(0);
22151 switch (N.getOpcode()) {
22154 case X86ISD::PSHUFLW:
22155 case X86ISD::PSHUFHW:
22156 assert(VT == MVT::v8i16);
22159 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22160 return SDValue(); // We combined away this shuffle, so we're done.
22162 // See if this reduces to a PSHUFD which is no more expensive and can
22163 // combine with more operations. Note that it has to at least flip the
22164 // dwords as otherwise it would have been removed as a no-op.
22165 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22166 int DMask[] = {0, 1, 2, 3};
22167 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22168 DMask[DOffset + 0] = DOffset + 1;
22169 DMask[DOffset + 1] = DOffset + 0;
22170 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22171 DCI.AddToWorklist(V.getNode());
22172 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22173 getV4X86ShuffleImm8ForMask(DMask, DAG));
22174 DCI.AddToWorklist(V.getNode());
22175 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22178 // Look for shuffle patterns which can be implemented as a single unpack.
22179 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22180 // only works when we have a PSHUFD followed by two half-shuffles.
22181 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22182 (V.getOpcode() == X86ISD::PSHUFLW ||
22183 V.getOpcode() == X86ISD::PSHUFHW) &&
22184 V.getOpcode() != N.getOpcode() &&
22186 SDValue D = V.getOperand(0);
22187 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22188 D = D.getOperand(0);
22189 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22190 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22191 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22192 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22193 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22195 for (int i = 0; i < 4; ++i) {
22196 WordMask[i + NOffset] = Mask[i] + NOffset;
22197 WordMask[i + VOffset] = VMask[i] + VOffset;
22199 // Map the word mask through the DWord mask.
22201 for (int i = 0; i < 8; ++i)
22202 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22203 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22204 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22205 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22206 std::begin(UnpackLoMask)) ||
22207 std::equal(std::begin(MappedMask), std::end(MappedMask),
22208 std::begin(UnpackHiMask))) {
22209 // We can replace all three shuffles with an unpack.
22210 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22211 DCI.AddToWorklist(V.getNode());
22212 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22214 DL, MVT::v8i16, V, V);
22221 case X86ISD::PSHUFD:
22222 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22231 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22233 /// We combine this directly on the abstract vector shuffle nodes so it is
22234 /// easier to generically match. We also insert dummy vector shuffle nodes for
22235 /// the operands which explicitly discard the lanes which are unused by this
22236 /// operation to try to flow through the rest of the combiner the fact that
22237 /// they're unused.
22238 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22240 EVT VT = N->getValueType(0);
22242 // We only handle target-independent shuffles.
22243 // FIXME: It would be easy and harmless to use the target shuffle mask
22244 // extraction tool to support more.
22245 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22248 auto *SVN = cast<ShuffleVectorSDNode>(N);
22249 ArrayRef<int> Mask = SVN->getMask();
22250 SDValue V1 = N->getOperand(0);
22251 SDValue V2 = N->getOperand(1);
22253 // We require the first shuffle operand to be the SUB node, and the second to
22254 // be the ADD node.
22255 // FIXME: We should support the commuted patterns.
22256 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22259 // If there are other uses of these operations we can't fold them.
22260 if (!V1->hasOneUse() || !V2->hasOneUse())
22263 // Ensure that both operations have the same operands. Note that we can
22264 // commute the FADD operands.
22265 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22266 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22267 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22270 // We're looking for blends between FADD and FSUB nodes. We insist on these
22271 // nodes being lined up in a specific expected pattern.
22272 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22273 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22274 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22277 // Only specific types are legal at this point, assert so we notice if and
22278 // when these change.
22279 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22280 VT == MVT::v4f64) &&
22281 "Unknown vector type encountered!");
22283 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22286 /// PerformShuffleCombine - Performs several different shuffle combines.
22287 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22288 TargetLowering::DAGCombinerInfo &DCI,
22289 const X86Subtarget *Subtarget) {
22291 SDValue N0 = N->getOperand(0);
22292 SDValue N1 = N->getOperand(1);
22293 EVT VT = N->getValueType(0);
22295 // Don't create instructions with illegal types after legalize types has run.
22296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22297 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22300 // If we have legalized the vector types, look for blends of FADD and FSUB
22301 // nodes that we can fuse into an ADDSUB node.
22302 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22303 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22306 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22307 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22308 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22309 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22311 // During Type Legalization, when promoting illegal vector types,
22312 // the backend might introduce new shuffle dag nodes and bitcasts.
22314 // This code performs the following transformation:
22315 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22316 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22318 // We do this only if both the bitcast and the BINOP dag nodes have
22319 // one use. Also, perform this transformation only if the new binary
22320 // operation is legal. This is to avoid introducing dag nodes that
22321 // potentially need to be further expanded (or custom lowered) into a
22322 // less optimal sequence of dag nodes.
22323 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22324 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22325 N0.getOpcode() == ISD::BITCAST) {
22326 SDValue BC0 = N0.getOperand(0);
22327 EVT SVT = BC0.getValueType();
22328 unsigned Opcode = BC0.getOpcode();
22329 unsigned NumElts = VT.getVectorNumElements();
22331 if (BC0.hasOneUse() && SVT.isVector() &&
22332 SVT.getVectorNumElements() * 2 == NumElts &&
22333 TLI.isOperationLegal(Opcode, VT)) {
22334 bool CanFold = false;
22346 unsigned SVTNumElts = SVT.getVectorNumElements();
22347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22348 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22349 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22350 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22351 CanFold = SVOp->getMaskElt(i) < 0;
22354 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22355 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22356 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22357 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22362 // Only handle 128 wide vector from here on.
22363 if (!VT.is128BitVector())
22366 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22367 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22368 // consecutive, non-overlapping, and in the right order.
22369 SmallVector<SDValue, 16> Elts;
22370 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22371 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22373 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22377 if (isTargetShuffle(N->getOpcode())) {
22379 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22380 if (Shuffle.getNode())
22383 // Try recursively combining arbitrary sequences of x86 shuffle
22384 // instructions into higher-order shuffles. We do this after combining
22385 // specific PSHUF instruction sequences into their minimal form so that we
22386 // can evaluate how many specialized shuffle instructions are involved in
22387 // a particular chain.
22388 SmallVector<int, 1> NonceMask; // Just a placeholder.
22389 NonceMask.push_back(0);
22390 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22391 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22393 return SDValue(); // This routine will use CombineTo to replace N.
22399 /// PerformTruncateCombine - Converts truncate operation to
22400 /// a sequence of vector shuffle operations.
22401 /// It is possible when we truncate 256-bit vector to 128-bit vector
22402 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22403 TargetLowering::DAGCombinerInfo &DCI,
22404 const X86Subtarget *Subtarget) {
22408 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22409 /// specific shuffle of a load can be folded into a single element load.
22410 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22411 /// shuffles have been custom lowered so we need to handle those here.
22412 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22413 TargetLowering::DAGCombinerInfo &DCI) {
22414 if (DCI.isBeforeLegalizeOps())
22417 SDValue InVec = N->getOperand(0);
22418 SDValue EltNo = N->getOperand(1);
22420 if (!isa<ConstantSDNode>(EltNo))
22423 EVT OriginalVT = InVec.getValueType();
22425 if (InVec.getOpcode() == ISD::BITCAST) {
22426 // Don't duplicate a load with other uses.
22427 if (!InVec.hasOneUse())
22429 EVT BCVT = InVec.getOperand(0).getValueType();
22430 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22432 InVec = InVec.getOperand(0);
22435 EVT CurrentVT = InVec.getValueType();
22437 if (!isTargetShuffle(InVec.getOpcode()))
22440 // Don't duplicate a load with other uses.
22441 if (!InVec.hasOneUse())
22444 SmallVector<int, 16> ShuffleMask;
22446 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22447 ShuffleMask, UnaryShuffle))
22450 // Select the input vector, guarding against out of range extract vector.
22451 unsigned NumElems = CurrentVT.getVectorNumElements();
22452 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22453 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22454 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22455 : InVec.getOperand(1);
22457 // If inputs to shuffle are the same for both ops, then allow 2 uses
22458 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22460 if (LdNode.getOpcode() == ISD::BITCAST) {
22461 // Don't duplicate a load with other uses.
22462 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22465 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22466 LdNode = LdNode.getOperand(0);
22469 if (!ISD::isNormalLoad(LdNode.getNode()))
22472 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22474 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22477 EVT EltVT = N->getValueType(0);
22478 // If there's a bitcast before the shuffle, check if the load type and
22479 // alignment is valid.
22480 unsigned Align = LN0->getAlignment();
22481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22482 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22483 EltVT.getTypeForEVT(*DAG.getContext()));
22485 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22488 // All checks match so transform back to vector_shuffle so that DAG combiner
22489 // can finish the job
22492 // Create shuffle node taking into account the case that its a unary shuffle
22493 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22494 : InVec.getOperand(1);
22495 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22496 InVec.getOperand(0), Shuffle,
22498 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22499 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22503 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22504 /// generation and convert it from being a bunch of shuffles and extracts
22505 /// to a simple store and scalar loads to extract the elements.
22506 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22507 TargetLowering::DAGCombinerInfo &DCI) {
22508 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22509 if (NewOp.getNode())
22512 SDValue InputVector = N->getOperand(0);
22514 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22515 // from mmx to v2i32 has a single usage.
22516 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22517 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22518 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22519 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22520 N->getValueType(0),
22521 InputVector.getNode()->getOperand(0));
22523 // Only operate on vectors of 4 elements, where the alternative shuffling
22524 // gets to be more expensive.
22525 if (InputVector.getValueType() != MVT::v4i32)
22528 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22529 // single use which is a sign-extend or zero-extend, and all elements are
22531 SmallVector<SDNode *, 4> Uses;
22532 unsigned ExtractedElements = 0;
22533 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22534 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22535 if (UI.getUse().getResNo() != InputVector.getResNo())
22538 SDNode *Extract = *UI;
22539 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22542 if (Extract->getValueType(0) != MVT::i32)
22544 if (!Extract->hasOneUse())
22546 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22547 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22549 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22552 // Record which element was extracted.
22553 ExtractedElements |=
22554 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22556 Uses.push_back(Extract);
22559 // If not all the elements were used, this may not be worthwhile.
22560 if (ExtractedElements != 15)
22563 // Ok, we've now decided to do the transformation.
22564 SDLoc dl(InputVector);
22566 // Store the value to a temporary stack slot.
22567 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22568 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22569 MachinePointerInfo(), false, false, 0);
22571 // Replace each use (extract) with a load of the appropriate element.
22572 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22573 UE = Uses.end(); UI != UE; ++UI) {
22574 SDNode *Extract = *UI;
22576 // cOMpute the element's address.
22577 SDValue Idx = Extract->getOperand(1);
22579 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22580 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22581 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22582 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22584 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22585 StackPtr, OffsetVal);
22587 // Load the scalar.
22588 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22589 ScalarAddr, MachinePointerInfo(),
22590 false, false, false, 0);
22592 // Replace the exact with the load.
22593 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22596 // The replacement was made in place; don't return anything.
22600 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22601 static std::pair<unsigned, bool>
22602 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22603 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22604 if (!VT.isVector())
22605 return std::make_pair(0, false);
22607 bool NeedSplit = false;
22608 switch (VT.getSimpleVT().SimpleTy) {
22609 default: return std::make_pair(0, false);
22613 if (!Subtarget->hasAVX2())
22615 if (!Subtarget->hasAVX())
22616 return std::make_pair(0, false);
22621 if (!Subtarget->hasSSE2())
22622 return std::make_pair(0, false);
22625 // SSE2 has only a small subset of the operations.
22626 bool hasUnsigned = Subtarget->hasSSE41() ||
22627 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22628 bool hasSigned = Subtarget->hasSSE41() ||
22629 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22631 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22634 // Check for x CC y ? x : y.
22635 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22636 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22641 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22644 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22647 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22650 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22652 // Check for x CC y ? y : x -- a min/max with reversed arms.
22653 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22654 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22659 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22662 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22665 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22668 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22672 return std::make_pair(Opc, NeedSplit);
22676 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22677 const X86Subtarget *Subtarget) {
22679 SDValue Cond = N->getOperand(0);
22680 SDValue LHS = N->getOperand(1);
22681 SDValue RHS = N->getOperand(2);
22683 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22684 SDValue CondSrc = Cond->getOperand(0);
22685 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22686 Cond = CondSrc->getOperand(0);
22689 MVT VT = N->getSimpleValueType(0);
22690 MVT EltVT = VT.getVectorElementType();
22691 unsigned NumElems = VT.getVectorNumElements();
22692 // There is no blend with immediate in AVX-512.
22693 if (VT.is512BitVector())
22696 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22698 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22701 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22704 // A vselect where all conditions and data are constants can be optimized into
22705 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22706 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22707 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22710 unsigned MaskValue = 0;
22711 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22714 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22715 for (unsigned i = 0; i < NumElems; ++i) {
22716 // Be sure we emit undef where we can.
22717 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22718 ShuffleMask[i] = -1;
22720 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22723 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22726 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22728 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22729 TargetLowering::DAGCombinerInfo &DCI,
22730 const X86Subtarget *Subtarget) {
22732 SDValue Cond = N->getOperand(0);
22733 // Get the LHS/RHS of the select.
22734 SDValue LHS = N->getOperand(1);
22735 SDValue RHS = N->getOperand(2);
22736 EVT VT = LHS.getValueType();
22737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22739 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22740 // instructions match the semantics of the common C idiom x<y?x:y but not
22741 // x<=y?x:y, because of how they handle negative zero (which can be
22742 // ignored in unsafe-math mode).
22743 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22744 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22745 (Subtarget->hasSSE2() ||
22746 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22747 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22749 unsigned Opcode = 0;
22750 // Check for x CC y ? x : y.
22751 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22752 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22756 // Converting this to a min would handle NaNs incorrectly, and swapping
22757 // the operands would cause it to handle comparisons between positive
22758 // and negative zero incorrectly.
22759 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22760 if (!DAG.getTarget().Options.UnsafeFPMath &&
22761 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22763 std::swap(LHS, RHS);
22765 Opcode = X86ISD::FMIN;
22768 // Converting this to a min would handle comparisons between positive
22769 // and negative zero incorrectly.
22770 if (!DAG.getTarget().Options.UnsafeFPMath &&
22771 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22773 Opcode = X86ISD::FMIN;
22776 // Converting this to a min would handle both negative zeros and NaNs
22777 // incorrectly, but we can swap the operands to fix both.
22778 std::swap(LHS, RHS);
22782 Opcode = X86ISD::FMIN;
22786 // Converting this to a max would handle comparisons between positive
22787 // and negative zero incorrectly.
22788 if (!DAG.getTarget().Options.UnsafeFPMath &&
22789 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22791 Opcode = X86ISD::FMAX;
22794 // Converting this to a max would handle NaNs incorrectly, and swapping
22795 // the operands would cause it to handle comparisons between positive
22796 // and negative zero incorrectly.
22797 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22798 if (!DAG.getTarget().Options.UnsafeFPMath &&
22799 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22801 std::swap(LHS, RHS);
22803 Opcode = X86ISD::FMAX;
22806 // Converting this to a max would handle both negative zeros and NaNs
22807 // incorrectly, but we can swap the operands to fix both.
22808 std::swap(LHS, RHS);
22812 Opcode = X86ISD::FMAX;
22815 // Check for x CC y ? y : x -- a min/max with reversed arms.
22816 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22817 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22821 // Converting this to a min would handle comparisons between positive
22822 // and negative zero incorrectly, and swapping the operands would
22823 // cause it to handle NaNs incorrectly.
22824 if (!DAG.getTarget().Options.UnsafeFPMath &&
22825 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22826 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22828 std::swap(LHS, RHS);
22830 Opcode = X86ISD::FMIN;
22833 // Converting this to a min would handle NaNs incorrectly.
22834 if (!DAG.getTarget().Options.UnsafeFPMath &&
22835 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22837 Opcode = X86ISD::FMIN;
22840 // Converting this to a min would handle both negative zeros and NaNs
22841 // incorrectly, but we can swap the operands to fix both.
22842 std::swap(LHS, RHS);
22846 Opcode = X86ISD::FMIN;
22850 // Converting this to a max would handle NaNs incorrectly.
22851 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22853 Opcode = X86ISD::FMAX;
22856 // Converting this to a max would handle comparisons between positive
22857 // and negative zero incorrectly, and swapping the operands would
22858 // cause it to handle NaNs incorrectly.
22859 if (!DAG.getTarget().Options.UnsafeFPMath &&
22860 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22861 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22863 std::swap(LHS, RHS);
22865 Opcode = X86ISD::FMAX;
22868 // Converting this to a max would handle both negative zeros and NaNs
22869 // incorrectly, but we can swap the operands to fix both.
22870 std::swap(LHS, RHS);
22874 Opcode = X86ISD::FMAX;
22880 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22883 EVT CondVT = Cond.getValueType();
22884 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22885 CondVT.getVectorElementType() == MVT::i1) {
22886 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22887 // lowering on KNL. In this case we convert it to
22888 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22889 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22890 // Since SKX these selects have a proper lowering.
22891 EVT OpVT = LHS.getValueType();
22892 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22893 (OpVT.getVectorElementType() == MVT::i8 ||
22894 OpVT.getVectorElementType() == MVT::i16) &&
22895 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22896 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22897 DCI.AddToWorklist(Cond.getNode());
22898 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22901 // If this is a select between two integer constants, try to do some
22903 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22904 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22905 // Don't do this for crazy integer types.
22906 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22907 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22908 // so that TrueC (the true value) is larger than FalseC.
22909 bool NeedsCondInvert = false;
22911 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22912 // Efficiently invertible.
22913 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22914 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22915 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22916 NeedsCondInvert = true;
22917 std::swap(TrueC, FalseC);
22920 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22921 if (FalseC->getAPIntValue() == 0 &&
22922 TrueC->getAPIntValue().isPowerOf2()) {
22923 if (NeedsCondInvert) // Invert the condition if needed.
22924 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22925 DAG.getConstant(1, Cond.getValueType()));
22927 // Zero extend the condition if needed.
22928 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22930 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22931 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22932 DAG.getConstant(ShAmt, MVT::i8));
22935 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22936 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22937 if (NeedsCondInvert) // Invert the condition if needed.
22938 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22939 DAG.getConstant(1, Cond.getValueType()));
22941 // Zero extend the condition if needed.
22942 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22943 FalseC->getValueType(0), Cond);
22944 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22945 SDValue(FalseC, 0));
22948 // Optimize cases that will turn into an LEA instruction. This requires
22949 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22950 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22951 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22952 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22954 bool isFastMultiplier = false;
22956 switch ((unsigned char)Diff) {
22958 case 1: // result = add base, cond
22959 case 2: // result = lea base( , cond*2)
22960 case 3: // result = lea base(cond, cond*2)
22961 case 4: // result = lea base( , cond*4)
22962 case 5: // result = lea base(cond, cond*4)
22963 case 8: // result = lea base( , cond*8)
22964 case 9: // result = lea base(cond, cond*8)
22965 isFastMultiplier = true;
22970 if (isFastMultiplier) {
22971 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22972 if (NeedsCondInvert) // Invert the condition if needed.
22973 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22974 DAG.getConstant(1, Cond.getValueType()));
22976 // Zero extend the condition if needed.
22977 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22979 // Scale the condition by the difference.
22981 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22982 DAG.getConstant(Diff, Cond.getValueType()));
22984 // Add the base if non-zero.
22985 if (FalseC->getAPIntValue() != 0)
22986 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22987 SDValue(FalseC, 0));
22994 // Canonicalize max and min:
22995 // (x > y) ? x : y -> (x >= y) ? x : y
22996 // (x < y) ? x : y -> (x <= y) ? x : y
22997 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22998 // the need for an extra compare
22999 // against zero. e.g.
23000 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23002 // testl %edi, %edi
23004 // cmovgl %edi, %eax
23008 // cmovsl %eax, %edi
23009 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23010 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23011 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23012 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23017 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23018 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23019 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23020 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23025 // Early exit check
23026 if (!TLI.isTypeLegal(VT))
23029 // Match VSELECTs into subs with unsigned saturation.
23030 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23031 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23032 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23033 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23034 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23036 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23037 // left side invert the predicate to simplify logic below.
23039 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23041 CC = ISD::getSetCCInverse(CC, true);
23042 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23046 if (Other.getNode() && Other->getNumOperands() == 2 &&
23047 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23048 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23049 SDValue CondRHS = Cond->getOperand(1);
23051 // Look for a general sub with unsigned saturation first.
23052 // x >= y ? x-y : 0 --> subus x, y
23053 // x > y ? x-y : 0 --> subus x, y
23054 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23055 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23056 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23058 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23059 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23060 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23061 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23062 // If the RHS is a constant we have to reverse the const
23063 // canonicalization.
23064 // x > C-1 ? x+-C : 0 --> subus x, C
23065 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23066 CondRHSConst->getAPIntValue() ==
23067 (-OpRHSConst->getAPIntValue() - 1))
23068 return DAG.getNode(
23069 X86ISD::SUBUS, DL, VT, OpLHS,
23070 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23072 // Another special case: If C was a sign bit, the sub has been
23073 // canonicalized into a xor.
23074 // FIXME: Would it be better to use computeKnownBits to determine
23075 // whether it's safe to decanonicalize the xor?
23076 // x s< 0 ? x^C : 0 --> subus x, C
23077 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23078 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23079 OpRHSConst->getAPIntValue().isSignBit())
23080 // Note that we have to rebuild the RHS constant here to ensure we
23081 // don't rely on particular values of undef lanes.
23082 return DAG.getNode(
23083 X86ISD::SUBUS, DL, VT, OpLHS,
23084 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23089 // Try to match a min/max vector operation.
23090 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23091 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23092 unsigned Opc = ret.first;
23093 bool NeedSplit = ret.second;
23095 if (Opc && NeedSplit) {
23096 unsigned NumElems = VT.getVectorNumElements();
23097 // Extract the LHS vectors
23098 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23099 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23101 // Extract the RHS vectors
23102 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23103 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23105 // Create min/max for each subvector
23106 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23107 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23109 // Merge the result
23110 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23112 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23115 // Simplify vector selection if condition value type matches vselect
23117 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23118 assert(Cond.getValueType().isVector() &&
23119 "vector select expects a vector selector!");
23121 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23122 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23124 // Try invert the condition if true value is not all 1s and false value
23126 if (!TValIsAllOnes && !FValIsAllZeros &&
23127 // Check if the selector will be produced by CMPP*/PCMP*
23128 Cond.getOpcode() == ISD::SETCC &&
23129 // Check if SETCC has already been promoted
23130 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23131 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23132 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23134 if (TValIsAllZeros || FValIsAllOnes) {
23135 SDValue CC = Cond.getOperand(2);
23136 ISD::CondCode NewCC =
23137 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23138 Cond.getOperand(0).getValueType().isInteger());
23139 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23140 std::swap(LHS, RHS);
23141 TValIsAllOnes = FValIsAllOnes;
23142 FValIsAllZeros = TValIsAllZeros;
23146 if (TValIsAllOnes || FValIsAllZeros) {
23149 if (TValIsAllOnes && FValIsAllZeros)
23151 else if (TValIsAllOnes)
23152 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23153 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23154 else if (FValIsAllZeros)
23155 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23156 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23158 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23162 // Try to fold this VSELECT into a MOVSS/MOVSD
23163 if (N->getOpcode() == ISD::VSELECT &&
23164 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
23165 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
23166 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
23167 bool CanFold = false;
23168 unsigned NumElems = Cond.getNumOperands();
23172 if (isZero(Cond.getOperand(0))) {
23175 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
23176 // fold (vselect <0,-1> -> (movsd A, B)
23177 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23178 CanFold = isAllOnes(Cond.getOperand(i));
23179 } else if (isAllOnes(Cond.getOperand(0))) {
23183 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
23184 // fold (vselect <-1,0> -> (movsd B, A)
23185 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23186 CanFold = isZero(Cond.getOperand(i));
23190 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23191 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23192 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23195 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23196 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23197 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23198 // (v2i64 (bitcast B)))))
23200 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23201 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23202 // (v2f64 (bitcast B)))))
23204 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23205 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23206 // (v2i64 (bitcast A)))))
23208 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23209 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23210 // (v2f64 (bitcast A)))))
23212 CanFold = (isZero(Cond.getOperand(0)) &&
23213 isZero(Cond.getOperand(1)) &&
23214 isAllOnes(Cond.getOperand(2)) &&
23215 isAllOnes(Cond.getOperand(3)));
23217 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23218 isAllOnes(Cond.getOperand(1)) &&
23219 isZero(Cond.getOperand(2)) &&
23220 isZero(Cond.getOperand(3))) {
23222 std::swap(LHS, RHS);
23226 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23227 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23228 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23229 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23231 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23237 // If we know that this node is legal then we know that it is going to be
23238 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23239 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23240 // to simplify previous instructions.
23241 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23242 !DCI.isBeforeLegalize() &&
23243 // We explicitly check against v8i16 and v16i16 because, although
23244 // they're marked as Custom, they might only be legal when Cond is a
23245 // build_vector of constants. This will be taken care in a later
23247 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23248 VT != MVT::v8i16) &&
23249 // Don't optimize vector of constants. Those are handled by
23250 // the generic code and all the bits must be properly set for
23251 // the generic optimizer.
23252 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23253 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23255 // Don't optimize vector selects that map to mask-registers.
23259 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23260 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23262 APInt KnownZero, KnownOne;
23263 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23264 DCI.isBeforeLegalizeOps());
23265 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23266 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23268 // If we changed the computation somewhere in the DAG, this change
23269 // will affect all users of Cond.
23270 // Make sure it is fine and update all the nodes so that we do not
23271 // use the generic VSELECT anymore. Otherwise, we may perform
23272 // wrong optimizations as we messed up with the actual expectation
23273 // for the vector boolean values.
23274 if (Cond != TLO.Old) {
23275 // Check all uses of that condition operand to check whether it will be
23276 // consumed by non-BLEND instructions, which may depend on all bits are
23278 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23280 if (I->getOpcode() != ISD::VSELECT)
23281 // TODO: Add other opcodes eventually lowered into BLEND.
23284 // Update all the users of the condition, before committing the change,
23285 // so that the VSELECT optimizations that expect the correct vector
23286 // boolean value will not be triggered.
23287 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23289 DAG.ReplaceAllUsesOfValueWith(
23291 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23292 Cond, I->getOperand(1), I->getOperand(2)));
23293 DCI.CommitTargetLoweringOpt(TLO);
23296 // At this point, only Cond is changed. Change the condition
23297 // just for N to keep the opportunity to optimize all other
23298 // users their own way.
23299 DAG.ReplaceAllUsesOfValueWith(
23301 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23302 TLO.New, N->getOperand(1), N->getOperand(2)));
23307 // We should generate an X86ISD::BLENDI from a vselect if its argument
23308 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23309 // constants. This specific pattern gets generated when we split a
23310 // selector for a 512 bit vector in a machine without AVX512 (but with
23311 // 256-bit vectors), during legalization:
23313 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23315 // Iff we find this pattern and the build_vectors are built from
23316 // constants, we translate the vselect into a shuffle_vector that we
23317 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23318 if ((N->getOpcode() == ISD::VSELECT ||
23319 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23320 !DCI.isBeforeLegalize()) {
23321 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23322 if (Shuffle.getNode())
23329 // Check whether a boolean test is testing a boolean value generated by
23330 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23333 // Simplify the following patterns:
23334 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23335 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23336 // to (Op EFLAGS Cond)
23338 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23339 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23340 // to (Op EFLAGS !Cond)
23342 // where Op could be BRCOND or CMOV.
23344 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23345 // Quit if not CMP and SUB with its value result used.
23346 if (Cmp.getOpcode() != X86ISD::CMP &&
23347 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23350 // Quit if not used as a boolean value.
23351 if (CC != X86::COND_E && CC != X86::COND_NE)
23354 // Check CMP operands. One of them should be 0 or 1 and the other should be
23355 // an SetCC or extended from it.
23356 SDValue Op1 = Cmp.getOperand(0);
23357 SDValue Op2 = Cmp.getOperand(1);
23360 const ConstantSDNode* C = nullptr;
23361 bool needOppositeCond = (CC == X86::COND_E);
23362 bool checkAgainstTrue = false; // Is it a comparison against 1?
23364 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23366 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23368 else // Quit if all operands are not constants.
23371 if (C->getZExtValue() == 1) {
23372 needOppositeCond = !needOppositeCond;
23373 checkAgainstTrue = true;
23374 } else if (C->getZExtValue() != 0)
23375 // Quit if the constant is neither 0 or 1.
23378 bool truncatedToBoolWithAnd = false;
23379 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23380 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23381 SetCC.getOpcode() == ISD::TRUNCATE ||
23382 SetCC.getOpcode() == ISD::AND) {
23383 if (SetCC.getOpcode() == ISD::AND) {
23385 ConstantSDNode *CS;
23386 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23387 CS->getZExtValue() == 1)
23389 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23390 CS->getZExtValue() == 1)
23394 SetCC = SetCC.getOperand(OpIdx);
23395 truncatedToBoolWithAnd = true;
23397 SetCC = SetCC.getOperand(0);
23400 switch (SetCC.getOpcode()) {
23401 case X86ISD::SETCC_CARRY:
23402 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23403 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23404 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23405 // truncated to i1 using 'and'.
23406 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23408 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23409 "Invalid use of SETCC_CARRY!");
23411 case X86ISD::SETCC:
23412 // Set the condition code or opposite one if necessary.
23413 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23414 if (needOppositeCond)
23415 CC = X86::GetOppositeBranchCondition(CC);
23416 return SetCC.getOperand(1);
23417 case X86ISD::CMOV: {
23418 // Check whether false/true value has canonical one, i.e. 0 or 1.
23419 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23420 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23421 // Quit if true value is not a constant.
23424 // Quit if false value is not a constant.
23426 SDValue Op = SetCC.getOperand(0);
23427 // Skip 'zext' or 'trunc' node.
23428 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23429 Op.getOpcode() == ISD::TRUNCATE)
23430 Op = Op.getOperand(0);
23431 // A special case for rdrand/rdseed, where 0 is set if false cond is
23433 if ((Op.getOpcode() != X86ISD::RDRAND &&
23434 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23437 // Quit if false value is not the constant 0 or 1.
23438 bool FValIsFalse = true;
23439 if (FVal && FVal->getZExtValue() != 0) {
23440 if (FVal->getZExtValue() != 1)
23442 // If FVal is 1, opposite cond is needed.
23443 needOppositeCond = !needOppositeCond;
23444 FValIsFalse = false;
23446 // Quit if TVal is not the constant opposite of FVal.
23447 if (FValIsFalse && TVal->getZExtValue() != 1)
23449 if (!FValIsFalse && TVal->getZExtValue() != 0)
23451 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23452 if (needOppositeCond)
23453 CC = X86::GetOppositeBranchCondition(CC);
23454 return SetCC.getOperand(3);
23461 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23462 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23463 TargetLowering::DAGCombinerInfo &DCI,
23464 const X86Subtarget *Subtarget) {
23467 // If the flag operand isn't dead, don't touch this CMOV.
23468 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23471 SDValue FalseOp = N->getOperand(0);
23472 SDValue TrueOp = N->getOperand(1);
23473 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23474 SDValue Cond = N->getOperand(3);
23476 if (CC == X86::COND_E || CC == X86::COND_NE) {
23477 switch (Cond.getOpcode()) {
23481 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23482 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23483 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23489 Flags = checkBoolTestSetCCCombine(Cond, CC);
23490 if (Flags.getNode() &&
23491 // Extra check as FCMOV only supports a subset of X86 cond.
23492 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23493 SDValue Ops[] = { FalseOp, TrueOp,
23494 DAG.getConstant(CC, MVT::i8), Flags };
23495 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23498 // If this is a select between two integer constants, try to do some
23499 // optimizations. Note that the operands are ordered the opposite of SELECT
23501 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23502 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23503 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23504 // larger than FalseC (the false value).
23505 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23506 CC = X86::GetOppositeBranchCondition(CC);
23507 std::swap(TrueC, FalseC);
23508 std::swap(TrueOp, FalseOp);
23511 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23512 // This is efficient for any integer data type (including i8/i16) and
23514 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23515 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23516 DAG.getConstant(CC, MVT::i8), Cond);
23518 // Zero extend the condition if needed.
23519 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23521 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23522 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23523 DAG.getConstant(ShAmt, MVT::i8));
23524 if (N->getNumValues() == 2) // Dead flag value?
23525 return DCI.CombineTo(N, Cond, SDValue());
23529 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23530 // for any integer data type, including i8/i16.
23531 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23532 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23533 DAG.getConstant(CC, MVT::i8), Cond);
23535 // Zero extend the condition if needed.
23536 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23537 FalseC->getValueType(0), Cond);
23538 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23539 SDValue(FalseC, 0));
23541 if (N->getNumValues() == 2) // Dead flag value?
23542 return DCI.CombineTo(N, Cond, SDValue());
23546 // Optimize cases that will turn into an LEA instruction. This requires
23547 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23548 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23549 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23550 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23552 bool isFastMultiplier = false;
23554 switch ((unsigned char)Diff) {
23556 case 1: // result = add base, cond
23557 case 2: // result = lea base( , cond*2)
23558 case 3: // result = lea base(cond, cond*2)
23559 case 4: // result = lea base( , cond*4)
23560 case 5: // result = lea base(cond, cond*4)
23561 case 8: // result = lea base( , cond*8)
23562 case 9: // result = lea base(cond, cond*8)
23563 isFastMultiplier = true;
23568 if (isFastMultiplier) {
23569 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23570 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23571 DAG.getConstant(CC, MVT::i8), Cond);
23572 // Zero extend the condition if needed.
23573 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23575 // Scale the condition by the difference.
23577 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23578 DAG.getConstant(Diff, Cond.getValueType()));
23580 // Add the base if non-zero.
23581 if (FalseC->getAPIntValue() != 0)
23582 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23583 SDValue(FalseC, 0));
23584 if (N->getNumValues() == 2) // Dead flag value?
23585 return DCI.CombineTo(N, Cond, SDValue());
23592 // Handle these cases:
23593 // (select (x != c), e, c) -> select (x != c), e, x),
23594 // (select (x == c), c, e) -> select (x == c), x, e)
23595 // where the c is an integer constant, and the "select" is the combination
23596 // of CMOV and CMP.
23598 // The rationale for this change is that the conditional-move from a constant
23599 // needs two instructions, however, conditional-move from a register needs
23600 // only one instruction.
23602 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23603 // some instruction-combining opportunities. This opt needs to be
23604 // postponed as late as possible.
23606 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23607 // the DCI.xxxx conditions are provided to postpone the optimization as
23608 // late as possible.
23610 ConstantSDNode *CmpAgainst = nullptr;
23611 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23612 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23613 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23615 if (CC == X86::COND_NE &&
23616 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23617 CC = X86::GetOppositeBranchCondition(CC);
23618 std::swap(TrueOp, FalseOp);
23621 if (CC == X86::COND_E &&
23622 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23623 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23624 DAG.getConstant(CC, MVT::i8), Cond };
23625 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23633 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23634 const X86Subtarget *Subtarget) {
23635 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23637 default: return SDValue();
23638 // SSE/AVX/AVX2 blend intrinsics.
23639 case Intrinsic::x86_avx2_pblendvb:
23640 case Intrinsic::x86_avx2_pblendw:
23641 case Intrinsic::x86_avx2_pblendd_128:
23642 case Intrinsic::x86_avx2_pblendd_256:
23643 // Don't try to simplify this intrinsic if we don't have AVX2.
23644 if (!Subtarget->hasAVX2())
23647 case Intrinsic::x86_avx_blend_pd_256:
23648 case Intrinsic::x86_avx_blend_ps_256:
23649 case Intrinsic::x86_avx_blendv_pd_256:
23650 case Intrinsic::x86_avx_blendv_ps_256:
23651 // Don't try to simplify this intrinsic if we don't have AVX.
23652 if (!Subtarget->hasAVX())
23655 case Intrinsic::x86_sse41_pblendw:
23656 case Intrinsic::x86_sse41_blendpd:
23657 case Intrinsic::x86_sse41_blendps:
23658 case Intrinsic::x86_sse41_blendvps:
23659 case Intrinsic::x86_sse41_blendvpd:
23660 case Intrinsic::x86_sse41_pblendvb: {
23661 SDValue Op0 = N->getOperand(1);
23662 SDValue Op1 = N->getOperand(2);
23663 SDValue Mask = N->getOperand(3);
23665 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23666 if (!Subtarget->hasSSE41())
23669 // fold (blend A, A, Mask) -> A
23672 // fold (blend A, B, allZeros) -> A
23673 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23675 // fold (blend A, B, allOnes) -> B
23676 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23679 // Simplify the case where the mask is a constant i32 value.
23680 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23681 if (C->isNullValue())
23683 if (C->isAllOnesValue())
23690 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23691 case Intrinsic::x86_sse2_psrai_w:
23692 case Intrinsic::x86_sse2_psrai_d:
23693 case Intrinsic::x86_avx2_psrai_w:
23694 case Intrinsic::x86_avx2_psrai_d:
23695 case Intrinsic::x86_sse2_psra_w:
23696 case Intrinsic::x86_sse2_psra_d:
23697 case Intrinsic::x86_avx2_psra_w:
23698 case Intrinsic::x86_avx2_psra_d: {
23699 SDValue Op0 = N->getOperand(1);
23700 SDValue Op1 = N->getOperand(2);
23701 EVT VT = Op0.getValueType();
23702 assert(VT.isVector() && "Expected a vector type!");
23704 if (isa<BuildVectorSDNode>(Op1))
23705 Op1 = Op1.getOperand(0);
23707 if (!isa<ConstantSDNode>(Op1))
23710 EVT SVT = VT.getVectorElementType();
23711 unsigned SVTBits = SVT.getSizeInBits();
23713 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23714 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23715 uint64_t ShAmt = C.getZExtValue();
23717 // Don't try to convert this shift into a ISD::SRA if the shift
23718 // count is bigger than or equal to the element size.
23719 if (ShAmt >= SVTBits)
23722 // Trivial case: if the shift count is zero, then fold this
23723 // into the first operand.
23727 // Replace this packed shift intrinsic with a target independent
23729 SDValue Splat = DAG.getConstant(C, VT);
23730 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23735 /// PerformMulCombine - Optimize a single multiply with constant into two
23736 /// in order to implement it with two cheaper instructions, e.g.
23737 /// LEA + SHL, LEA + LEA.
23738 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23739 TargetLowering::DAGCombinerInfo &DCI) {
23740 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23743 EVT VT = N->getValueType(0);
23744 if (VT != MVT::i64)
23747 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23750 uint64_t MulAmt = C->getZExtValue();
23751 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23754 uint64_t MulAmt1 = 0;
23755 uint64_t MulAmt2 = 0;
23756 if ((MulAmt % 9) == 0) {
23758 MulAmt2 = MulAmt / 9;
23759 } else if ((MulAmt % 5) == 0) {
23761 MulAmt2 = MulAmt / 5;
23762 } else if ((MulAmt % 3) == 0) {
23764 MulAmt2 = MulAmt / 3;
23767 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23770 if (isPowerOf2_64(MulAmt2) &&
23771 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23772 // If second multiplifer is pow2, issue it first. We want the multiply by
23773 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23775 std::swap(MulAmt1, MulAmt2);
23778 if (isPowerOf2_64(MulAmt1))
23779 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23780 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23782 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23783 DAG.getConstant(MulAmt1, VT));
23785 if (isPowerOf2_64(MulAmt2))
23786 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23787 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23789 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23790 DAG.getConstant(MulAmt2, VT));
23792 // Do not add new nodes to DAG combiner worklist.
23793 DCI.CombineTo(N, NewMul, false);
23798 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23799 SDValue N0 = N->getOperand(0);
23800 SDValue N1 = N->getOperand(1);
23801 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23802 EVT VT = N0.getValueType();
23804 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23805 // since the result of setcc_c is all zero's or all ones.
23806 if (VT.isInteger() && !VT.isVector() &&
23807 N1C && N0.getOpcode() == ISD::AND &&
23808 N0.getOperand(1).getOpcode() == ISD::Constant) {
23809 SDValue N00 = N0.getOperand(0);
23810 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23811 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23812 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23813 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23814 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23815 APInt ShAmt = N1C->getAPIntValue();
23816 Mask = Mask.shl(ShAmt);
23818 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23819 N00, DAG.getConstant(Mask, VT));
23823 // Hardware support for vector shifts is sparse which makes us scalarize the
23824 // vector operations in many cases. Also, on sandybridge ADD is faster than
23826 // (shl V, 1) -> add V,V
23827 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23828 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23829 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23830 // We shift all of the values by one. In many cases we do not have
23831 // hardware support for this operation. This is better expressed as an ADD
23833 if (N1SplatC->getZExtValue() == 1)
23834 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23840 /// \brief Returns a vector of 0s if the node in input is a vector logical
23841 /// shift by a constant amount which is known to be bigger than or equal
23842 /// to the vector element size in bits.
23843 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23844 const X86Subtarget *Subtarget) {
23845 EVT VT = N->getValueType(0);
23847 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23848 (!Subtarget->hasInt256() ||
23849 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23852 SDValue Amt = N->getOperand(1);
23854 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23855 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23856 APInt ShiftAmt = AmtSplat->getAPIntValue();
23857 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23859 // SSE2/AVX2 logical shifts always return a vector of 0s
23860 // if the shift amount is bigger than or equal to
23861 // the element size. The constant shift amount will be
23862 // encoded as a 8-bit immediate.
23863 if (ShiftAmt.trunc(8).uge(MaxAmount))
23864 return getZeroVector(VT, Subtarget, DAG, DL);
23870 /// PerformShiftCombine - Combine shifts.
23871 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23872 TargetLowering::DAGCombinerInfo &DCI,
23873 const X86Subtarget *Subtarget) {
23874 if (N->getOpcode() == ISD::SHL) {
23875 SDValue V = PerformSHLCombine(N, DAG);
23876 if (V.getNode()) return V;
23879 if (N->getOpcode() != ISD::SRA) {
23880 // Try to fold this logical shift into a zero vector.
23881 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23882 if (V.getNode()) return V;
23888 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23889 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23890 // and friends. Likewise for OR -> CMPNEQSS.
23891 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23892 TargetLowering::DAGCombinerInfo &DCI,
23893 const X86Subtarget *Subtarget) {
23896 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23897 // we're requiring SSE2 for both.
23898 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23899 SDValue N0 = N->getOperand(0);
23900 SDValue N1 = N->getOperand(1);
23901 SDValue CMP0 = N0->getOperand(1);
23902 SDValue CMP1 = N1->getOperand(1);
23905 // The SETCCs should both refer to the same CMP.
23906 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23909 SDValue CMP00 = CMP0->getOperand(0);
23910 SDValue CMP01 = CMP0->getOperand(1);
23911 EVT VT = CMP00.getValueType();
23913 if (VT == MVT::f32 || VT == MVT::f64) {
23914 bool ExpectingFlags = false;
23915 // Check for any users that want flags:
23916 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23917 !ExpectingFlags && UI != UE; ++UI)
23918 switch (UI->getOpcode()) {
23923 ExpectingFlags = true;
23925 case ISD::CopyToReg:
23926 case ISD::SIGN_EXTEND:
23927 case ISD::ZERO_EXTEND:
23928 case ISD::ANY_EXTEND:
23932 if (!ExpectingFlags) {
23933 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23934 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23936 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23937 X86::CondCode tmp = cc0;
23942 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23943 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23944 // FIXME: need symbolic constants for these magic numbers.
23945 // See X86ATTInstPrinter.cpp:printSSECC().
23946 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23947 if (Subtarget->hasAVX512()) {
23948 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23949 CMP01, DAG.getConstant(x86cc, MVT::i8));
23950 if (N->getValueType(0) != MVT::i1)
23951 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23955 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23956 CMP00.getValueType(), CMP00, CMP01,
23957 DAG.getConstant(x86cc, MVT::i8));
23959 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23960 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23962 if (is64BitFP && !Subtarget->is64Bit()) {
23963 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23964 // 64-bit integer, since that's not a legal type. Since
23965 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23966 // bits, but can do this little dance to extract the lowest 32 bits
23967 // and work with those going forward.
23968 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23970 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23972 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23973 Vector32, DAG.getIntPtrConstant(0));
23977 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23978 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23979 DAG.getConstant(1, IntVT));
23980 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23981 return OneBitOfTruth;
23989 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23990 /// so it can be folded inside ANDNP.
23991 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23992 EVT VT = N->getValueType(0);
23994 // Match direct AllOnes for 128 and 256-bit vectors
23995 if (ISD::isBuildVectorAllOnes(N))
23998 // Look through a bit convert.
23999 if (N->getOpcode() == ISD::BITCAST)
24000 N = N->getOperand(0).getNode();
24002 // Sometimes the operand may come from a insert_subvector building a 256-bit
24004 if (VT.is256BitVector() &&
24005 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24006 SDValue V1 = N->getOperand(0);
24007 SDValue V2 = N->getOperand(1);
24009 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24010 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24011 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24012 ISD::isBuildVectorAllOnes(V2.getNode()))
24019 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24020 // register. In most cases we actually compare or select YMM-sized registers
24021 // and mixing the two types creates horrible code. This method optimizes
24022 // some of the transition sequences.
24023 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24024 TargetLowering::DAGCombinerInfo &DCI,
24025 const X86Subtarget *Subtarget) {
24026 EVT VT = N->getValueType(0);
24027 if (!VT.is256BitVector())
24030 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24031 N->getOpcode() == ISD::ZERO_EXTEND ||
24032 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24034 SDValue Narrow = N->getOperand(0);
24035 EVT NarrowVT = Narrow->getValueType(0);
24036 if (!NarrowVT.is128BitVector())
24039 if (Narrow->getOpcode() != ISD::XOR &&
24040 Narrow->getOpcode() != ISD::AND &&
24041 Narrow->getOpcode() != ISD::OR)
24044 SDValue N0 = Narrow->getOperand(0);
24045 SDValue N1 = Narrow->getOperand(1);
24048 // The Left side has to be a trunc.
24049 if (N0.getOpcode() != ISD::TRUNCATE)
24052 // The type of the truncated inputs.
24053 EVT WideVT = N0->getOperand(0)->getValueType(0);
24057 // The right side has to be a 'trunc' or a constant vector.
24058 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24059 ConstantSDNode *RHSConstSplat = nullptr;
24060 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24061 RHSConstSplat = RHSBV->getConstantSplatNode();
24062 if (!RHSTrunc && !RHSConstSplat)
24065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24067 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24070 // Set N0 and N1 to hold the inputs to the new wide operation.
24071 N0 = N0->getOperand(0);
24072 if (RHSConstSplat) {
24073 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24074 SDValue(RHSConstSplat, 0));
24075 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24076 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24077 } else if (RHSTrunc) {
24078 N1 = N1->getOperand(0);
24081 // Generate the wide operation.
24082 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24083 unsigned Opcode = N->getOpcode();
24085 case ISD::ANY_EXTEND:
24087 case ISD::ZERO_EXTEND: {
24088 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24089 APInt Mask = APInt::getAllOnesValue(InBits);
24090 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24091 return DAG.getNode(ISD::AND, DL, VT,
24092 Op, DAG.getConstant(Mask, VT));
24094 case ISD::SIGN_EXTEND:
24095 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24096 Op, DAG.getValueType(NarrowVT));
24098 llvm_unreachable("Unexpected opcode");
24102 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24103 TargetLowering::DAGCombinerInfo &DCI,
24104 const X86Subtarget *Subtarget) {
24105 EVT VT = N->getValueType(0);
24106 if (DCI.isBeforeLegalizeOps())
24109 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24113 // Create BEXTR instructions
24114 // BEXTR is ((X >> imm) & (2**size-1))
24115 if (VT == MVT::i32 || VT == MVT::i64) {
24116 SDValue N0 = N->getOperand(0);
24117 SDValue N1 = N->getOperand(1);
24120 // Check for BEXTR.
24121 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24122 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24123 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24124 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24125 if (MaskNode && ShiftNode) {
24126 uint64_t Mask = MaskNode->getZExtValue();
24127 uint64_t Shift = ShiftNode->getZExtValue();
24128 if (isMask_64(Mask)) {
24129 uint64_t MaskSize = CountPopulation_64(Mask);
24130 if (Shift + MaskSize <= VT.getSizeInBits())
24131 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24132 DAG.getConstant(Shift | (MaskSize << 8), VT));
24140 // Want to form ANDNP nodes:
24141 // 1) In the hopes of then easily combining them with OR and AND nodes
24142 // to form PBLEND/PSIGN.
24143 // 2) To match ANDN packed intrinsics
24144 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24147 SDValue N0 = N->getOperand(0);
24148 SDValue N1 = N->getOperand(1);
24151 // Check LHS for vnot
24152 if (N0.getOpcode() == ISD::XOR &&
24153 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24154 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24155 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24157 // Check RHS for vnot
24158 if (N1.getOpcode() == ISD::XOR &&
24159 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24160 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24161 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24166 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24167 TargetLowering::DAGCombinerInfo &DCI,
24168 const X86Subtarget *Subtarget) {
24169 if (DCI.isBeforeLegalizeOps())
24172 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24176 SDValue N0 = N->getOperand(0);
24177 SDValue N1 = N->getOperand(1);
24178 EVT VT = N->getValueType(0);
24180 // look for psign/blend
24181 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24182 if (!Subtarget->hasSSSE3() ||
24183 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24186 // Canonicalize pandn to RHS
24187 if (N0.getOpcode() == X86ISD::ANDNP)
24189 // or (and (m, y), (pandn m, x))
24190 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24191 SDValue Mask = N1.getOperand(0);
24192 SDValue X = N1.getOperand(1);
24194 if (N0.getOperand(0) == Mask)
24195 Y = N0.getOperand(1);
24196 if (N0.getOperand(1) == Mask)
24197 Y = N0.getOperand(0);
24199 // Check to see if the mask appeared in both the AND and ANDNP and
24203 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24204 // Look through mask bitcast.
24205 if (Mask.getOpcode() == ISD::BITCAST)
24206 Mask = Mask.getOperand(0);
24207 if (X.getOpcode() == ISD::BITCAST)
24208 X = X.getOperand(0);
24209 if (Y.getOpcode() == ISD::BITCAST)
24210 Y = Y.getOperand(0);
24212 EVT MaskVT = Mask.getValueType();
24214 // Validate that the Mask operand is a vector sra node.
24215 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24216 // there is no psrai.b
24217 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24218 unsigned SraAmt = ~0;
24219 if (Mask.getOpcode() == ISD::SRA) {
24220 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24221 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24222 SraAmt = AmtConst->getZExtValue();
24223 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24224 SDValue SraC = Mask.getOperand(1);
24225 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24227 if ((SraAmt + 1) != EltBits)
24232 // Now we know we at least have a plendvb with the mask val. See if
24233 // we can form a psignb/w/d.
24234 // psign = x.type == y.type == mask.type && y = sub(0, x);
24235 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24236 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24237 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24238 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24239 "Unsupported VT for PSIGN");
24240 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24241 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24243 // PBLENDVB only available on SSE 4.1
24244 if (!Subtarget->hasSSE41())
24247 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24249 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24250 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24251 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24252 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24253 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24257 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24260 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24261 MachineFunction &MF = DAG.getMachineFunction();
24262 bool OptForSize = MF.getFunction()->getAttributes().
24263 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24265 // SHLD/SHRD instructions have lower register pressure, but on some
24266 // platforms they have higher latency than the equivalent
24267 // series of shifts/or that would otherwise be generated.
24268 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24269 // have higher latencies and we are not optimizing for size.
24270 if (!OptForSize && Subtarget->isSHLDSlow())
24273 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24275 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24277 if (!N0.hasOneUse() || !N1.hasOneUse())
24280 SDValue ShAmt0 = N0.getOperand(1);
24281 if (ShAmt0.getValueType() != MVT::i8)
24283 SDValue ShAmt1 = N1.getOperand(1);
24284 if (ShAmt1.getValueType() != MVT::i8)
24286 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24287 ShAmt0 = ShAmt0.getOperand(0);
24288 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24289 ShAmt1 = ShAmt1.getOperand(0);
24292 unsigned Opc = X86ISD::SHLD;
24293 SDValue Op0 = N0.getOperand(0);
24294 SDValue Op1 = N1.getOperand(0);
24295 if (ShAmt0.getOpcode() == ISD::SUB) {
24296 Opc = X86ISD::SHRD;
24297 std::swap(Op0, Op1);
24298 std::swap(ShAmt0, ShAmt1);
24301 unsigned Bits = VT.getSizeInBits();
24302 if (ShAmt1.getOpcode() == ISD::SUB) {
24303 SDValue Sum = ShAmt1.getOperand(0);
24304 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24305 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24306 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24307 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24308 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24309 return DAG.getNode(Opc, DL, VT,
24311 DAG.getNode(ISD::TRUNCATE, DL,
24314 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24315 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24317 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24318 return DAG.getNode(Opc, DL, VT,
24319 N0.getOperand(0), N1.getOperand(0),
24320 DAG.getNode(ISD::TRUNCATE, DL,
24327 // Generate NEG and CMOV for integer abs.
24328 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24329 EVT VT = N->getValueType(0);
24331 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24332 // 8-bit integer abs to NEG and CMOV.
24333 if (VT.isInteger() && VT.getSizeInBits() == 8)
24336 SDValue N0 = N->getOperand(0);
24337 SDValue N1 = N->getOperand(1);
24340 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24341 // and change it to SUB and CMOV.
24342 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24343 N0.getOpcode() == ISD::ADD &&
24344 N0.getOperand(1) == N1 &&
24345 N1.getOpcode() == ISD::SRA &&
24346 N1.getOperand(0) == N0.getOperand(0))
24347 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24348 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24349 // Generate SUB & CMOV.
24350 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24351 DAG.getConstant(0, VT), N0.getOperand(0));
24353 SDValue Ops[] = { N0.getOperand(0), Neg,
24354 DAG.getConstant(X86::COND_GE, MVT::i8),
24355 SDValue(Neg.getNode(), 1) };
24356 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24361 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24362 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24363 TargetLowering::DAGCombinerInfo &DCI,
24364 const X86Subtarget *Subtarget) {
24365 if (DCI.isBeforeLegalizeOps())
24368 if (Subtarget->hasCMov()) {
24369 SDValue RV = performIntegerAbsCombine(N, DAG);
24377 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24378 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24379 TargetLowering::DAGCombinerInfo &DCI,
24380 const X86Subtarget *Subtarget) {
24381 LoadSDNode *Ld = cast<LoadSDNode>(N);
24382 EVT RegVT = Ld->getValueType(0);
24383 EVT MemVT = Ld->getMemoryVT();
24385 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24387 // On Sandybridge unaligned 256bit loads are inefficient.
24388 ISD::LoadExtType Ext = Ld->getExtensionType();
24389 unsigned Alignment = Ld->getAlignment();
24390 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24391 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24392 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24393 unsigned NumElems = RegVT.getVectorNumElements();
24397 SDValue Ptr = Ld->getBasePtr();
24398 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24400 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24402 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24403 Ld->getPointerInfo(), Ld->isVolatile(),
24404 Ld->isNonTemporal(), Ld->isInvariant(),
24406 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24407 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24408 Ld->getPointerInfo(), Ld->isVolatile(),
24409 Ld->isNonTemporal(), Ld->isInvariant(),
24410 std::min(16U, Alignment));
24411 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24413 Load2.getValue(1));
24415 SDValue NewVec = DAG.getUNDEF(RegVT);
24416 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24417 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24418 return DCI.CombineTo(N, NewVec, TF, true);
24424 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24425 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24426 const X86Subtarget *Subtarget) {
24427 StoreSDNode *St = cast<StoreSDNode>(N);
24428 EVT VT = St->getValue().getValueType();
24429 EVT StVT = St->getMemoryVT();
24431 SDValue StoredVal = St->getOperand(1);
24432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24434 // If we are saving a concatenation of two XMM registers, perform two stores.
24435 // On Sandy Bridge, 256-bit memory operations are executed by two
24436 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24437 // memory operation.
24438 unsigned Alignment = St->getAlignment();
24439 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24440 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24441 StVT == VT && !IsAligned) {
24442 unsigned NumElems = VT.getVectorNumElements();
24446 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24447 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24449 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24450 SDValue Ptr0 = St->getBasePtr();
24451 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24453 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24454 St->getPointerInfo(), St->isVolatile(),
24455 St->isNonTemporal(), Alignment);
24456 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24457 St->getPointerInfo(), St->isVolatile(),
24458 St->isNonTemporal(),
24459 std::min(16U, Alignment));
24460 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24463 // Optimize trunc store (of multiple scalars) to shuffle and store.
24464 // First, pack all of the elements in one place. Next, store to memory
24465 // in fewer chunks.
24466 if (St->isTruncatingStore() && VT.isVector()) {
24467 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24468 unsigned NumElems = VT.getVectorNumElements();
24469 assert(StVT != VT && "Cannot truncate to the same type");
24470 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24471 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24473 // From, To sizes and ElemCount must be pow of two
24474 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24475 // We are going to use the original vector elt for storing.
24476 // Accumulated smaller vector elements must be a multiple of the store size.
24477 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24479 unsigned SizeRatio = FromSz / ToSz;
24481 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24483 // Create a type on which we perform the shuffle
24484 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24485 StVT.getScalarType(), NumElems*SizeRatio);
24487 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24489 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24490 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24491 for (unsigned i = 0; i != NumElems; ++i)
24492 ShuffleVec[i] = i * SizeRatio;
24494 // Can't shuffle using an illegal type.
24495 if (!TLI.isTypeLegal(WideVecVT))
24498 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24499 DAG.getUNDEF(WideVecVT),
24501 // At this point all of the data is stored at the bottom of the
24502 // register. We now need to save it to mem.
24504 // Find the largest store unit
24505 MVT StoreType = MVT::i8;
24506 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24507 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24508 MVT Tp = (MVT::SimpleValueType)tp;
24509 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24513 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24514 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24515 (64 <= NumElems * ToSz))
24516 StoreType = MVT::f64;
24518 // Bitcast the original vector into a vector of store-size units
24519 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24520 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24521 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24522 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24523 SmallVector<SDValue, 8> Chains;
24524 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24525 TLI.getPointerTy());
24526 SDValue Ptr = St->getBasePtr();
24528 // Perform one or more big stores into memory.
24529 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24530 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24531 StoreType, ShuffWide,
24532 DAG.getIntPtrConstant(i));
24533 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24534 St->getPointerInfo(), St->isVolatile(),
24535 St->isNonTemporal(), St->getAlignment());
24536 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24537 Chains.push_back(Ch);
24540 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24543 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24544 // the FP state in cases where an emms may be missing.
24545 // A preferable solution to the general problem is to figure out the right
24546 // places to insert EMMS. This qualifies as a quick hack.
24548 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24549 if (VT.getSizeInBits() != 64)
24552 const Function *F = DAG.getMachineFunction().getFunction();
24553 bool NoImplicitFloatOps = F->getAttributes().
24554 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24555 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24556 && Subtarget->hasSSE2();
24557 if ((VT.isVector() ||
24558 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24559 isa<LoadSDNode>(St->getValue()) &&
24560 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24561 St->getChain().hasOneUse() && !St->isVolatile()) {
24562 SDNode* LdVal = St->getValue().getNode();
24563 LoadSDNode *Ld = nullptr;
24564 int TokenFactorIndex = -1;
24565 SmallVector<SDValue, 8> Ops;
24566 SDNode* ChainVal = St->getChain().getNode();
24567 // Must be a store of a load. We currently handle two cases: the load
24568 // is a direct child, and it's under an intervening TokenFactor. It is
24569 // possible to dig deeper under nested TokenFactors.
24570 if (ChainVal == LdVal)
24571 Ld = cast<LoadSDNode>(St->getChain());
24572 else if (St->getValue().hasOneUse() &&
24573 ChainVal->getOpcode() == ISD::TokenFactor) {
24574 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24575 if (ChainVal->getOperand(i).getNode() == LdVal) {
24576 TokenFactorIndex = i;
24577 Ld = cast<LoadSDNode>(St->getValue());
24579 Ops.push_back(ChainVal->getOperand(i));
24583 if (!Ld || !ISD::isNormalLoad(Ld))
24586 // If this is not the MMX case, i.e. we are just turning i64 load/store
24587 // into f64 load/store, avoid the transformation if there are multiple
24588 // uses of the loaded value.
24589 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24594 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24595 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24597 if (Subtarget->is64Bit() || F64IsLegal) {
24598 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24599 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24600 Ld->getPointerInfo(), Ld->isVolatile(),
24601 Ld->isNonTemporal(), Ld->isInvariant(),
24602 Ld->getAlignment());
24603 SDValue NewChain = NewLd.getValue(1);
24604 if (TokenFactorIndex != -1) {
24605 Ops.push_back(NewChain);
24606 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24608 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24609 St->getPointerInfo(),
24610 St->isVolatile(), St->isNonTemporal(),
24611 St->getAlignment());
24614 // Otherwise, lower to two pairs of 32-bit loads / stores.
24615 SDValue LoAddr = Ld->getBasePtr();
24616 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24617 DAG.getConstant(4, MVT::i32));
24619 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24620 Ld->getPointerInfo(),
24621 Ld->isVolatile(), Ld->isNonTemporal(),
24622 Ld->isInvariant(), Ld->getAlignment());
24623 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24624 Ld->getPointerInfo().getWithOffset(4),
24625 Ld->isVolatile(), Ld->isNonTemporal(),
24627 MinAlign(Ld->getAlignment(), 4));
24629 SDValue NewChain = LoLd.getValue(1);
24630 if (TokenFactorIndex != -1) {
24631 Ops.push_back(LoLd);
24632 Ops.push_back(HiLd);
24633 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24636 LoAddr = St->getBasePtr();
24637 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24638 DAG.getConstant(4, MVT::i32));
24640 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24641 St->getPointerInfo(),
24642 St->isVolatile(), St->isNonTemporal(),
24643 St->getAlignment());
24644 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24645 St->getPointerInfo().getWithOffset(4),
24647 St->isNonTemporal(),
24648 MinAlign(St->getAlignment(), 4));
24649 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24654 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24655 /// and return the operands for the horizontal operation in LHS and RHS. A
24656 /// horizontal operation performs the binary operation on successive elements
24657 /// of its first operand, then on successive elements of its second operand,
24658 /// returning the resulting values in a vector. For example, if
24659 /// A = < float a0, float a1, float a2, float a3 >
24661 /// B = < float b0, float b1, float b2, float b3 >
24662 /// then the result of doing a horizontal operation on A and B is
24663 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24664 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24665 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24666 /// set to A, RHS to B, and the routine returns 'true'.
24667 /// Note that the binary operation should have the property that if one of the
24668 /// operands is UNDEF then the result is UNDEF.
24669 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24670 // Look for the following pattern: if
24671 // A = < float a0, float a1, float a2, float a3 >
24672 // B = < float b0, float b1, float b2, float b3 >
24674 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24675 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24676 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24677 // which is A horizontal-op B.
24679 // At least one of the operands should be a vector shuffle.
24680 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24681 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24684 MVT VT = LHS.getSimpleValueType();
24686 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24687 "Unsupported vector type for horizontal add/sub");
24689 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24690 // operate independently on 128-bit lanes.
24691 unsigned NumElts = VT.getVectorNumElements();
24692 unsigned NumLanes = VT.getSizeInBits()/128;
24693 unsigned NumLaneElts = NumElts / NumLanes;
24694 assert((NumLaneElts % 2 == 0) &&
24695 "Vector type should have an even number of elements in each lane");
24696 unsigned HalfLaneElts = NumLaneElts/2;
24698 // View LHS in the form
24699 // LHS = VECTOR_SHUFFLE A, B, LMask
24700 // If LHS is not a shuffle then pretend it is the shuffle
24701 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24702 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24705 SmallVector<int, 16> LMask(NumElts);
24706 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24707 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24708 A = LHS.getOperand(0);
24709 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24710 B = LHS.getOperand(1);
24711 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24712 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24714 if (LHS.getOpcode() != ISD::UNDEF)
24716 for (unsigned i = 0; i != NumElts; ++i)
24720 // Likewise, view RHS in the form
24721 // RHS = VECTOR_SHUFFLE C, D, RMask
24723 SmallVector<int, 16> RMask(NumElts);
24724 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24725 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24726 C = RHS.getOperand(0);
24727 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24728 D = RHS.getOperand(1);
24729 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24730 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24732 if (RHS.getOpcode() != ISD::UNDEF)
24734 for (unsigned i = 0; i != NumElts; ++i)
24738 // Check that the shuffles are both shuffling the same vectors.
24739 if (!(A == C && B == D) && !(A == D && B == C))
24742 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24743 if (!A.getNode() && !B.getNode())
24746 // If A and B occur in reverse order in RHS, then "swap" them (which means
24747 // rewriting the mask).
24749 CommuteVectorShuffleMask(RMask, NumElts);
24751 // At this point LHS and RHS are equivalent to
24752 // LHS = VECTOR_SHUFFLE A, B, LMask
24753 // RHS = VECTOR_SHUFFLE A, B, RMask
24754 // Check that the masks correspond to performing a horizontal operation.
24755 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24756 for (unsigned i = 0; i != NumLaneElts; ++i) {
24757 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24759 // Ignore any UNDEF components.
24760 if (LIdx < 0 || RIdx < 0 ||
24761 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24762 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24765 // Check that successive elements are being operated on. If not, this is
24766 // not a horizontal operation.
24767 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24768 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24769 if (!(LIdx == Index && RIdx == Index + 1) &&
24770 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24775 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24776 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24780 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24781 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24782 const X86Subtarget *Subtarget) {
24783 EVT VT = N->getValueType(0);
24784 SDValue LHS = N->getOperand(0);
24785 SDValue RHS = N->getOperand(1);
24787 // Try to synthesize horizontal adds from adds of shuffles.
24788 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24789 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24790 isHorizontalBinOp(LHS, RHS, true))
24791 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24795 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24796 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24797 const X86Subtarget *Subtarget) {
24798 EVT VT = N->getValueType(0);
24799 SDValue LHS = N->getOperand(0);
24800 SDValue RHS = N->getOperand(1);
24802 // Try to synthesize horizontal subs from subs of shuffles.
24803 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24804 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24805 isHorizontalBinOp(LHS, RHS, false))
24806 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24810 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24811 /// X86ISD::FXOR nodes.
24812 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24813 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24814 // F[X]OR(0.0, x) -> x
24815 // F[X]OR(x, 0.0) -> x
24816 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24817 if (C->getValueAPF().isPosZero())
24818 return N->getOperand(1);
24819 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24820 if (C->getValueAPF().isPosZero())
24821 return N->getOperand(0);
24825 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24826 /// X86ISD::FMAX nodes.
24827 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24828 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24830 // Only perform optimizations if UnsafeMath is used.
24831 if (!DAG.getTarget().Options.UnsafeFPMath)
24834 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24835 // into FMINC and FMAXC, which are Commutative operations.
24836 unsigned NewOp = 0;
24837 switch (N->getOpcode()) {
24838 default: llvm_unreachable("unknown opcode");
24839 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24840 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24843 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24844 N->getOperand(0), N->getOperand(1));
24847 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24848 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24849 // FAND(0.0, x) -> 0.0
24850 // FAND(x, 0.0) -> 0.0
24851 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24852 if (C->getValueAPF().isPosZero())
24853 return N->getOperand(0);
24854 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24855 if (C->getValueAPF().isPosZero())
24856 return N->getOperand(1);
24860 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24861 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24862 // FANDN(x, 0.0) -> 0.0
24863 // FANDN(0.0, x) -> x
24864 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24865 if (C->getValueAPF().isPosZero())
24866 return N->getOperand(1);
24867 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24868 if (C->getValueAPF().isPosZero())
24869 return N->getOperand(1);
24873 static SDValue PerformBTCombine(SDNode *N,
24875 TargetLowering::DAGCombinerInfo &DCI) {
24876 // BT ignores high bits in the bit index operand.
24877 SDValue Op1 = N->getOperand(1);
24878 if (Op1.hasOneUse()) {
24879 unsigned BitWidth = Op1.getValueSizeInBits();
24880 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24881 APInt KnownZero, KnownOne;
24882 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24883 !DCI.isBeforeLegalizeOps());
24884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24885 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24886 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24887 DCI.CommitTargetLoweringOpt(TLO);
24892 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24893 SDValue Op = N->getOperand(0);
24894 if (Op.getOpcode() == ISD::BITCAST)
24895 Op = Op.getOperand(0);
24896 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24897 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24898 VT.getVectorElementType().getSizeInBits() ==
24899 OpVT.getVectorElementType().getSizeInBits()) {
24900 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24905 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24906 const X86Subtarget *Subtarget) {
24907 EVT VT = N->getValueType(0);
24908 if (!VT.isVector())
24911 SDValue N0 = N->getOperand(0);
24912 SDValue N1 = N->getOperand(1);
24913 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24916 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24917 // both SSE and AVX2 since there is no sign-extended shift right
24918 // operation on a vector with 64-bit elements.
24919 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24920 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24921 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24922 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24923 SDValue N00 = N0.getOperand(0);
24925 // EXTLOAD has a better solution on AVX2,
24926 // it may be replaced with X86ISD::VSEXT node.
24927 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24928 if (!ISD::isNormalLoad(N00.getNode()))
24931 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24932 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24934 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24940 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24941 TargetLowering::DAGCombinerInfo &DCI,
24942 const X86Subtarget *Subtarget) {
24943 SDValue N0 = N->getOperand(0);
24944 EVT VT = N->getValueType(0);
24946 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24947 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24948 // This exposes the sext to the sdivrem lowering, so that it directly extends
24949 // from AH (which we otherwise need to do contortions to access).
24950 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24951 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24953 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24954 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24955 N0.getOperand(0), N0.getOperand(1));
24956 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24957 return R.getValue(1);
24960 if (!DCI.isBeforeLegalizeOps())
24963 if (!Subtarget->hasFp256())
24966 if (VT.isVector() && VT.getSizeInBits() == 256) {
24967 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24975 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24976 const X86Subtarget* Subtarget) {
24978 EVT VT = N->getValueType(0);
24980 // Let legalize expand this if it isn't a legal type yet.
24981 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24984 EVT ScalarVT = VT.getScalarType();
24985 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24986 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24989 SDValue A = N->getOperand(0);
24990 SDValue B = N->getOperand(1);
24991 SDValue C = N->getOperand(2);
24993 bool NegA = (A.getOpcode() == ISD::FNEG);
24994 bool NegB = (B.getOpcode() == ISD::FNEG);
24995 bool NegC = (C.getOpcode() == ISD::FNEG);
24997 // Negative multiplication when NegA xor NegB
24998 bool NegMul = (NegA != NegB);
25000 A = A.getOperand(0);
25002 B = B.getOperand(0);
25004 C = C.getOperand(0);
25008 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25010 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25012 return DAG.getNode(Opcode, dl, VT, A, B, C);
25015 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25016 TargetLowering::DAGCombinerInfo &DCI,
25017 const X86Subtarget *Subtarget) {
25018 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25019 // (and (i32 x86isd::setcc_carry), 1)
25020 // This eliminates the zext. This transformation is necessary because
25021 // ISD::SETCC is always legalized to i8.
25023 SDValue N0 = N->getOperand(0);
25024 EVT VT = N->getValueType(0);
25026 if (N0.getOpcode() == ISD::AND &&
25028 N0.getOperand(0).hasOneUse()) {
25029 SDValue N00 = N0.getOperand(0);
25030 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25032 if (!C || C->getZExtValue() != 1)
25034 return DAG.getNode(ISD::AND, dl, VT,
25035 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25036 N00.getOperand(0), N00.getOperand(1)),
25037 DAG.getConstant(1, VT));
25041 if (N0.getOpcode() == ISD::TRUNCATE &&
25043 N0.getOperand(0).hasOneUse()) {
25044 SDValue N00 = N0.getOperand(0);
25045 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25046 return DAG.getNode(ISD::AND, dl, VT,
25047 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25048 N00.getOperand(0), N00.getOperand(1)),
25049 DAG.getConstant(1, VT));
25052 if (VT.is256BitVector()) {
25053 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25058 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25059 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25060 // This exposes the zext to the udivrem lowering, so that it directly extends
25061 // from AH (which we otherwise need to do contortions to access).
25062 if (N0.getOpcode() == ISD::UDIVREM &&
25063 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25064 (VT == MVT::i32 || VT == MVT::i64)) {
25065 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25066 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25067 N0.getOperand(0), N0.getOperand(1));
25068 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25069 return R.getValue(1);
25075 // Optimize x == -y --> x+y == 0
25076 // x != -y --> x+y != 0
25077 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25078 const X86Subtarget* Subtarget) {
25079 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25080 SDValue LHS = N->getOperand(0);
25081 SDValue RHS = N->getOperand(1);
25082 EVT VT = N->getValueType(0);
25085 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25087 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25088 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25089 LHS.getValueType(), RHS, LHS.getOperand(1));
25090 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25091 addV, DAG.getConstant(0, addV.getValueType()), CC);
25093 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25095 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25096 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25097 RHS.getValueType(), LHS, RHS.getOperand(1));
25098 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25099 addV, DAG.getConstant(0, addV.getValueType()), CC);
25102 if (VT.getScalarType() == MVT::i1) {
25103 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25104 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25105 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25106 if (!IsSEXT0 && !IsVZero0)
25108 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25109 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25110 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25112 if (!IsSEXT1 && !IsVZero1)
25115 if (IsSEXT0 && IsVZero1) {
25116 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25117 if (CC == ISD::SETEQ)
25118 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25119 return LHS.getOperand(0);
25121 if (IsSEXT1 && IsVZero0) {
25122 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25123 if (CC == ISD::SETEQ)
25124 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25125 return RHS.getOperand(0);
25132 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25133 const X86Subtarget *Subtarget) {
25135 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25136 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25137 "X86insertps is only defined for v4x32");
25139 SDValue Ld = N->getOperand(1);
25140 if (MayFoldLoad(Ld)) {
25141 // Extract the countS bits from the immediate so we can get the proper
25142 // address when narrowing the vector load to a specific element.
25143 // When the second source op is a memory address, interps doesn't use
25144 // countS and just gets an f32 from that address.
25145 unsigned DestIndex =
25146 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25147 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25151 // Create this as a scalar to vector to match the instruction pattern.
25152 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25153 // countS bits are ignored when loading from memory on insertps, which
25154 // means we don't need to explicitly set them to 0.
25155 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25156 LoadScalarToVector, N->getOperand(2));
25159 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25160 // as "sbb reg,reg", since it can be extended without zext and produces
25161 // an all-ones bit which is more useful than 0/1 in some cases.
25162 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25165 return DAG.getNode(ISD::AND, DL, VT,
25166 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25167 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25168 DAG.getConstant(1, VT));
25169 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25170 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25171 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25172 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25175 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25176 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25177 TargetLowering::DAGCombinerInfo &DCI,
25178 const X86Subtarget *Subtarget) {
25180 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25181 SDValue EFLAGS = N->getOperand(1);
25183 if (CC == X86::COND_A) {
25184 // Try to convert COND_A into COND_B in an attempt to facilitate
25185 // materializing "setb reg".
25187 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25188 // cannot take an immediate as its first operand.
25190 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25191 EFLAGS.getValueType().isInteger() &&
25192 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25193 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25194 EFLAGS.getNode()->getVTList(),
25195 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25196 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25197 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25201 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25202 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25204 if (CC == X86::COND_B)
25205 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25209 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25210 if (Flags.getNode()) {
25211 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25212 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25218 // Optimize branch condition evaluation.
25220 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25221 TargetLowering::DAGCombinerInfo &DCI,
25222 const X86Subtarget *Subtarget) {
25224 SDValue Chain = N->getOperand(0);
25225 SDValue Dest = N->getOperand(1);
25226 SDValue EFLAGS = N->getOperand(3);
25227 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25231 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25232 if (Flags.getNode()) {
25233 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25234 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25241 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25242 SelectionDAG &DAG) {
25243 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25244 // optimize away operation when it's from a constant.
25246 // The general transformation is:
25247 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25248 // AND(VECTOR_CMP(x,y), constant2)
25249 // constant2 = UNARYOP(constant)
25251 // Early exit if this isn't a vector operation, the operand of the
25252 // unary operation isn't a bitwise AND, or if the sizes of the operations
25253 // aren't the same.
25254 EVT VT = N->getValueType(0);
25255 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25256 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25257 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25260 // Now check that the other operand of the AND is a constant. We could
25261 // make the transformation for non-constant splats as well, but it's unclear
25262 // that would be a benefit as it would not eliminate any operations, just
25263 // perform one more step in scalar code before moving to the vector unit.
25264 if (BuildVectorSDNode *BV =
25265 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25266 // Bail out if the vector isn't a constant.
25267 if (!BV->isConstant())
25270 // Everything checks out. Build up the new and improved node.
25272 EVT IntVT = BV->getValueType(0);
25273 // Create a new constant of the appropriate type for the transformed
25275 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25276 // The AND node needs bitcasts to/from an integer vector type around it.
25277 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25278 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25279 N->getOperand(0)->getOperand(0), MaskConst);
25280 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25287 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25288 const X86TargetLowering *XTLI) {
25289 // First try to optimize away the conversion entirely when it's
25290 // conditionally from a constant. Vectors only.
25291 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25292 if (Res != SDValue())
25295 // Now move on to more general possibilities.
25296 SDValue Op0 = N->getOperand(0);
25297 EVT InVT = Op0->getValueType(0);
25299 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25300 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25302 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25303 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25304 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25307 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25308 // a 32-bit target where SSE doesn't support i64->FP operations.
25309 if (Op0.getOpcode() == ISD::LOAD) {
25310 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25311 EVT VT = Ld->getValueType(0);
25312 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25313 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25314 !XTLI->getSubtarget()->is64Bit() &&
25316 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25317 Ld->getChain(), Op0, DAG);
25318 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25325 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25326 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25327 X86TargetLowering::DAGCombinerInfo &DCI) {
25328 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25329 // the result is either zero or one (depending on the input carry bit).
25330 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25331 if (X86::isZeroNode(N->getOperand(0)) &&
25332 X86::isZeroNode(N->getOperand(1)) &&
25333 // We don't have a good way to replace an EFLAGS use, so only do this when
25335 SDValue(N, 1).use_empty()) {
25337 EVT VT = N->getValueType(0);
25338 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25339 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25340 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25341 DAG.getConstant(X86::COND_B,MVT::i8),
25343 DAG.getConstant(1, VT));
25344 return DCI.CombineTo(N, Res1, CarryOut);
25350 // fold (add Y, (sete X, 0)) -> adc 0, Y
25351 // (add Y, (setne X, 0)) -> sbb -1, Y
25352 // (sub (sete X, 0), Y) -> sbb 0, Y
25353 // (sub (setne X, 0), Y) -> adc -1, Y
25354 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25357 // Look through ZExts.
25358 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25359 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25362 SDValue SetCC = Ext.getOperand(0);
25363 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25366 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25367 if (CC != X86::COND_E && CC != X86::COND_NE)
25370 SDValue Cmp = SetCC.getOperand(1);
25371 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25372 !X86::isZeroNode(Cmp.getOperand(1)) ||
25373 !Cmp.getOperand(0).getValueType().isInteger())
25376 SDValue CmpOp0 = Cmp.getOperand(0);
25377 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25378 DAG.getConstant(1, CmpOp0.getValueType()));
25380 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25381 if (CC == X86::COND_NE)
25382 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25383 DL, OtherVal.getValueType(), OtherVal,
25384 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25385 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25386 DL, OtherVal.getValueType(), OtherVal,
25387 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25390 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25391 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25392 const X86Subtarget *Subtarget) {
25393 EVT VT = N->getValueType(0);
25394 SDValue Op0 = N->getOperand(0);
25395 SDValue Op1 = N->getOperand(1);
25397 // Try to synthesize horizontal adds from adds of shuffles.
25398 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25399 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25400 isHorizontalBinOp(Op0, Op1, true))
25401 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25403 return OptimizeConditionalInDecrement(N, DAG);
25406 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25407 const X86Subtarget *Subtarget) {
25408 SDValue Op0 = N->getOperand(0);
25409 SDValue Op1 = N->getOperand(1);
25411 // X86 can't encode an immediate LHS of a sub. See if we can push the
25412 // negation into a preceding instruction.
25413 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25414 // If the RHS of the sub is a XOR with one use and a constant, invert the
25415 // immediate. Then add one to the LHS of the sub so we can turn
25416 // X-Y -> X+~Y+1, saving one register.
25417 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25418 isa<ConstantSDNode>(Op1.getOperand(1))) {
25419 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25420 EVT VT = Op0.getValueType();
25421 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25423 DAG.getConstant(~XorC, VT));
25424 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25425 DAG.getConstant(C->getAPIntValue()+1, VT));
25429 // Try to synthesize horizontal adds from adds of shuffles.
25430 EVT VT = N->getValueType(0);
25431 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25432 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25433 isHorizontalBinOp(Op0, Op1, true))
25434 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25436 return OptimizeConditionalInDecrement(N, DAG);
25439 /// performVZEXTCombine - Performs build vector combines
25440 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25441 TargetLowering::DAGCombinerInfo &DCI,
25442 const X86Subtarget *Subtarget) {
25444 MVT VT = N->getSimpleValueType(0);
25445 SDValue Op = N->getOperand(0);
25446 MVT OpVT = Op.getSimpleValueType();
25447 MVT OpEltVT = OpVT.getVectorElementType();
25448 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25450 // (vzext (bitcast (vzext (x)) -> (vzext x)
25452 while (V.getOpcode() == ISD::BITCAST)
25453 V = V.getOperand(0);
25455 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25456 MVT InnerVT = V.getSimpleValueType();
25457 MVT InnerEltVT = InnerVT.getVectorElementType();
25459 // If the element sizes match exactly, we can just do one larger vzext. This
25460 // is always an exact type match as vzext operates on integer types.
25461 if (OpEltVT == InnerEltVT) {
25462 assert(OpVT == InnerVT && "Types must match for vzext!");
25463 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25466 // The only other way we can combine them is if only a single element of the
25467 // inner vzext is used in the input to the outer vzext.
25468 if (InnerEltVT.getSizeInBits() < InputBits)
25471 // In this case, the inner vzext is completely dead because we're going to
25472 // only look at bits inside of the low element. Just do the outer vzext on
25473 // a bitcast of the input to the inner.
25474 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25475 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25478 // Check if we can bypass extracting and re-inserting an element of an input
25479 // vector. Essentialy:
25480 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25481 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25482 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25483 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25484 SDValue ExtractedV = V.getOperand(0);
25485 SDValue OrigV = ExtractedV.getOperand(0);
25486 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25487 if (ExtractIdx->getZExtValue() == 0) {
25488 MVT OrigVT = OrigV.getSimpleValueType();
25489 // Extract a subvector if necessary...
25490 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25491 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25492 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25493 OrigVT.getVectorNumElements() / Ratio);
25494 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25495 DAG.getIntPtrConstant(0));
25497 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25498 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25505 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25506 DAGCombinerInfo &DCI) const {
25507 SelectionDAG &DAG = DCI.DAG;
25508 switch (N->getOpcode()) {
25510 case ISD::EXTRACT_VECTOR_ELT:
25511 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25514 case X86ISD::SHRUNKBLEND:
25515 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25516 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25517 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25518 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25519 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25520 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25523 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25524 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25525 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25526 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25527 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25528 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25529 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25530 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25531 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25533 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25535 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25536 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25537 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25538 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25539 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25540 case ISD::ANY_EXTEND:
25541 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25542 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25543 case ISD::SIGN_EXTEND_INREG:
25544 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25545 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25546 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25547 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25548 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25549 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25550 case X86ISD::SHUFP: // Handle all target specific shuffles
25551 case X86ISD::PALIGNR:
25552 case X86ISD::UNPCKH:
25553 case X86ISD::UNPCKL:
25554 case X86ISD::MOVHLPS:
25555 case X86ISD::MOVLHPS:
25556 case X86ISD::PSHUFB:
25557 case X86ISD::PSHUFD:
25558 case X86ISD::PSHUFHW:
25559 case X86ISD::PSHUFLW:
25560 case X86ISD::MOVSS:
25561 case X86ISD::MOVSD:
25562 case X86ISD::VPERMILPI:
25563 case X86ISD::VPERM2X128:
25564 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25565 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25566 case ISD::INTRINSIC_WO_CHAIN:
25567 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25568 case X86ISD::INSERTPS:
25569 return PerformINSERTPSCombine(N, DAG, Subtarget);
25570 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25576 /// isTypeDesirableForOp - Return true if the target has native support for
25577 /// the specified value type and it is 'desirable' to use the type for the
25578 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25579 /// instruction encodings are longer and some i16 instructions are slow.
25580 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25581 if (!isTypeLegal(VT))
25583 if (VT != MVT::i16)
25590 case ISD::SIGN_EXTEND:
25591 case ISD::ZERO_EXTEND:
25592 case ISD::ANY_EXTEND:
25605 /// IsDesirableToPromoteOp - This method query the target whether it is
25606 /// beneficial for dag combiner to promote the specified node. If true, it
25607 /// should return the desired promotion type by reference.
25608 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25609 EVT VT = Op.getValueType();
25610 if (VT != MVT::i16)
25613 bool Promote = false;
25614 bool Commute = false;
25615 switch (Op.getOpcode()) {
25618 LoadSDNode *LD = cast<LoadSDNode>(Op);
25619 // If the non-extending load has a single use and it's not live out, then it
25620 // might be folded.
25621 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25622 Op.hasOneUse()*/) {
25623 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25624 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25625 // The only case where we'd want to promote LOAD (rather then it being
25626 // promoted as an operand is when it's only use is liveout.
25627 if (UI->getOpcode() != ISD::CopyToReg)
25634 case ISD::SIGN_EXTEND:
25635 case ISD::ZERO_EXTEND:
25636 case ISD::ANY_EXTEND:
25641 SDValue N0 = Op.getOperand(0);
25642 // Look out for (store (shl (load), x)).
25643 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25656 SDValue N0 = Op.getOperand(0);
25657 SDValue N1 = Op.getOperand(1);
25658 if (!Commute && MayFoldLoad(N1))
25660 // Avoid disabling potential load folding opportunities.
25661 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25663 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25673 //===----------------------------------------------------------------------===//
25674 // X86 Inline Assembly Support
25675 //===----------------------------------------------------------------------===//
25678 // Helper to match a string separated by whitespace.
25679 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25680 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25682 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25683 StringRef piece(*args[i]);
25684 if (!s.startswith(piece)) // Check if the piece matches.
25687 s = s.substr(piece.size());
25688 StringRef::size_type pos = s.find_first_not_of(" \t");
25689 if (pos == 0) // We matched a prefix.
25697 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25700 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25702 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25703 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25704 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25705 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25707 if (AsmPieces.size() == 3)
25709 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25716 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25717 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25719 std::string AsmStr = IA->getAsmString();
25721 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25722 if (!Ty || Ty->getBitWidth() % 16 != 0)
25725 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25726 SmallVector<StringRef, 4> AsmPieces;
25727 SplitString(AsmStr, AsmPieces, ";\n");
25729 switch (AsmPieces.size()) {
25730 default: return false;
25732 // FIXME: this should verify that we are targeting a 486 or better. If not,
25733 // we will turn this bswap into something that will be lowered to logical
25734 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25735 // lower so don't worry about this.
25737 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25738 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25739 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25740 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25741 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25742 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25743 // No need to check constraints, nothing other than the equivalent of
25744 // "=r,0" would be valid here.
25745 return IntrinsicLowering::LowerToByteSwap(CI);
25748 // rorw $$8, ${0:w} --> llvm.bswap.i16
25749 if (CI->getType()->isIntegerTy(16) &&
25750 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25751 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25752 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25754 const std::string &ConstraintsStr = IA->getConstraintString();
25755 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25756 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25757 if (clobbersFlagRegisters(AsmPieces))
25758 return IntrinsicLowering::LowerToByteSwap(CI);
25762 if (CI->getType()->isIntegerTy(32) &&
25763 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25764 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25765 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25766 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25768 const std::string &ConstraintsStr = IA->getConstraintString();
25769 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25770 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25771 if (clobbersFlagRegisters(AsmPieces))
25772 return IntrinsicLowering::LowerToByteSwap(CI);
25775 if (CI->getType()->isIntegerTy(64)) {
25776 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25777 if (Constraints.size() >= 2 &&
25778 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25779 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25780 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25781 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25782 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25783 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25784 return IntrinsicLowering::LowerToByteSwap(CI);
25792 /// getConstraintType - Given a constraint letter, return the type of
25793 /// constraint it is for this target.
25794 X86TargetLowering::ConstraintType
25795 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25796 if (Constraint.size() == 1) {
25797 switch (Constraint[0]) {
25808 return C_RegisterClass;
25832 return TargetLowering::getConstraintType(Constraint);
25835 /// Examine constraint type and operand type and determine a weight value.
25836 /// This object must already have been set up with the operand type
25837 /// and the current alternative constraint selected.
25838 TargetLowering::ConstraintWeight
25839 X86TargetLowering::getSingleConstraintMatchWeight(
25840 AsmOperandInfo &info, const char *constraint) const {
25841 ConstraintWeight weight = CW_Invalid;
25842 Value *CallOperandVal = info.CallOperandVal;
25843 // If we don't have a value, we can't do a match,
25844 // but allow it at the lowest weight.
25845 if (!CallOperandVal)
25847 Type *type = CallOperandVal->getType();
25848 // Look at the constraint type.
25849 switch (*constraint) {
25851 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25862 if (CallOperandVal->getType()->isIntegerTy())
25863 weight = CW_SpecificReg;
25868 if (type->isFloatingPointTy())
25869 weight = CW_SpecificReg;
25872 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25873 weight = CW_SpecificReg;
25877 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25878 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25879 weight = CW_Register;
25882 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25883 if (C->getZExtValue() <= 31)
25884 weight = CW_Constant;
25888 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25889 if (C->getZExtValue() <= 63)
25890 weight = CW_Constant;
25894 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25895 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25896 weight = CW_Constant;
25900 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25901 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25902 weight = CW_Constant;
25906 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25907 if (C->getZExtValue() <= 3)
25908 weight = CW_Constant;
25912 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25913 if (C->getZExtValue() <= 0xff)
25914 weight = CW_Constant;
25919 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25920 weight = CW_Constant;
25924 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25925 if ((C->getSExtValue() >= -0x80000000LL) &&
25926 (C->getSExtValue() <= 0x7fffffffLL))
25927 weight = CW_Constant;
25931 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25932 if (C->getZExtValue() <= 0xffffffff)
25933 weight = CW_Constant;
25940 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25941 /// with another that has more specific requirements based on the type of the
25942 /// corresponding operand.
25943 const char *X86TargetLowering::
25944 LowerXConstraint(EVT ConstraintVT) const {
25945 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25946 // 'f' like normal targets.
25947 if (ConstraintVT.isFloatingPoint()) {
25948 if (Subtarget->hasSSE2())
25950 if (Subtarget->hasSSE1())
25954 return TargetLowering::LowerXConstraint(ConstraintVT);
25957 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25958 /// vector. If it is invalid, don't add anything to Ops.
25959 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25960 std::string &Constraint,
25961 std::vector<SDValue>&Ops,
25962 SelectionDAG &DAG) const {
25965 // Only support length 1 constraints for now.
25966 if (Constraint.length() > 1) return;
25968 char ConstraintLetter = Constraint[0];
25969 switch (ConstraintLetter) {
25972 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25973 if (C->getZExtValue() <= 31) {
25974 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25981 if (C->getZExtValue() <= 63) {
25982 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25989 if (isInt<8>(C->getSExtValue())) {
25990 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25997 if (C->getZExtValue() <= 255) {
25998 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26004 // 32-bit signed value
26005 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26006 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26007 C->getSExtValue())) {
26008 // Widen to 64 bits here to get it sign extended.
26009 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26012 // FIXME gcc accepts some relocatable values here too, but only in certain
26013 // memory models; it's complicated.
26018 // 32-bit unsigned value
26019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26020 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26021 C->getZExtValue())) {
26022 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26026 // FIXME gcc accepts some relocatable values here too, but only in certain
26027 // memory models; it's complicated.
26031 // Literal immediates are always ok.
26032 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26033 // Widen to 64 bits here to get it sign extended.
26034 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26038 // In any sort of PIC mode addresses need to be computed at runtime by
26039 // adding in a register or some sort of table lookup. These can't
26040 // be used as immediates.
26041 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26044 // If we are in non-pic codegen mode, we allow the address of a global (with
26045 // an optional displacement) to be used with 'i'.
26046 GlobalAddressSDNode *GA = nullptr;
26047 int64_t Offset = 0;
26049 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26051 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26052 Offset += GA->getOffset();
26054 } else if (Op.getOpcode() == ISD::ADD) {
26055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26056 Offset += C->getZExtValue();
26057 Op = Op.getOperand(0);
26060 } else if (Op.getOpcode() == ISD::SUB) {
26061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26062 Offset += -C->getZExtValue();
26063 Op = Op.getOperand(0);
26068 // Otherwise, this isn't something we can handle, reject it.
26072 const GlobalValue *GV = GA->getGlobal();
26073 // If we require an extra load to get this address, as in PIC mode, we
26074 // can't accept it.
26075 if (isGlobalStubReference(
26076 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26079 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26080 GA->getValueType(0), Offset);
26085 if (Result.getNode()) {
26086 Ops.push_back(Result);
26089 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26092 std::pair<unsigned, const TargetRegisterClass*>
26093 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26095 // First, see if this is a constraint that directly corresponds to an LLVM
26097 if (Constraint.size() == 1) {
26098 // GCC Constraint Letters
26099 switch (Constraint[0]) {
26101 // TODO: Slight differences here in allocation order and leaving
26102 // RIP in the class. Do they matter any more here than they do
26103 // in the normal allocation?
26104 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26105 if (Subtarget->is64Bit()) {
26106 if (VT == MVT::i32 || VT == MVT::f32)
26107 return std::make_pair(0U, &X86::GR32RegClass);
26108 if (VT == MVT::i16)
26109 return std::make_pair(0U, &X86::GR16RegClass);
26110 if (VT == MVT::i8 || VT == MVT::i1)
26111 return std::make_pair(0U, &X86::GR8RegClass);
26112 if (VT == MVT::i64 || VT == MVT::f64)
26113 return std::make_pair(0U, &X86::GR64RegClass);
26116 // 32-bit fallthrough
26117 case 'Q': // Q_REGS
26118 if (VT == MVT::i32 || VT == MVT::f32)
26119 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26120 if (VT == MVT::i16)
26121 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26122 if (VT == MVT::i8 || VT == MVT::i1)
26123 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26124 if (VT == MVT::i64)
26125 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26127 case 'r': // GENERAL_REGS
26128 case 'l': // INDEX_REGS
26129 if (VT == MVT::i8 || VT == MVT::i1)
26130 return std::make_pair(0U, &X86::GR8RegClass);
26131 if (VT == MVT::i16)
26132 return std::make_pair(0U, &X86::GR16RegClass);
26133 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26134 return std::make_pair(0U, &X86::GR32RegClass);
26135 return std::make_pair(0U, &X86::GR64RegClass);
26136 case 'R': // LEGACY_REGS
26137 if (VT == MVT::i8 || VT == MVT::i1)
26138 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26139 if (VT == MVT::i16)
26140 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26141 if (VT == MVT::i32 || !Subtarget->is64Bit())
26142 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26143 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26144 case 'f': // FP Stack registers.
26145 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26146 // value to the correct fpstack register class.
26147 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26148 return std::make_pair(0U, &X86::RFP32RegClass);
26149 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26150 return std::make_pair(0U, &X86::RFP64RegClass);
26151 return std::make_pair(0U, &X86::RFP80RegClass);
26152 case 'y': // MMX_REGS if MMX allowed.
26153 if (!Subtarget->hasMMX()) break;
26154 return std::make_pair(0U, &X86::VR64RegClass);
26155 case 'Y': // SSE_REGS if SSE2 allowed
26156 if (!Subtarget->hasSSE2()) break;
26158 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26159 if (!Subtarget->hasSSE1()) break;
26161 switch (VT.SimpleTy) {
26163 // Scalar SSE types.
26166 return std::make_pair(0U, &X86::FR32RegClass);
26169 return std::make_pair(0U, &X86::FR64RegClass);
26177 return std::make_pair(0U, &X86::VR128RegClass);
26185 return std::make_pair(0U, &X86::VR256RegClass);
26190 return std::make_pair(0U, &X86::VR512RegClass);
26196 // Use the default implementation in TargetLowering to convert the register
26197 // constraint into a member of a register class.
26198 std::pair<unsigned, const TargetRegisterClass*> Res;
26199 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26201 // Not found as a standard register?
26203 // Map st(0) -> st(7) -> ST0
26204 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26205 tolower(Constraint[1]) == 's' &&
26206 tolower(Constraint[2]) == 't' &&
26207 Constraint[3] == '(' &&
26208 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26209 Constraint[5] == ')' &&
26210 Constraint[6] == '}') {
26212 Res.first = X86::FP0+Constraint[4]-'0';
26213 Res.second = &X86::RFP80RegClass;
26217 // GCC allows "st(0)" to be called just plain "st".
26218 if (StringRef("{st}").equals_lower(Constraint)) {
26219 Res.first = X86::FP0;
26220 Res.second = &X86::RFP80RegClass;
26225 if (StringRef("{flags}").equals_lower(Constraint)) {
26226 Res.first = X86::EFLAGS;
26227 Res.second = &X86::CCRRegClass;
26231 // 'A' means EAX + EDX.
26232 if (Constraint == "A") {
26233 Res.first = X86::EAX;
26234 Res.second = &X86::GR32_ADRegClass;
26240 // Otherwise, check to see if this is a register class of the wrong value
26241 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26242 // turn into {ax},{dx}.
26243 if (Res.second->hasType(VT))
26244 return Res; // Correct type already, nothing to do.
26246 // All of the single-register GCC register classes map their values onto
26247 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26248 // really want an 8-bit or 32-bit register, map to the appropriate register
26249 // class and return the appropriate register.
26250 if (Res.second == &X86::GR16RegClass) {
26251 if (VT == MVT::i8 || VT == MVT::i1) {
26252 unsigned DestReg = 0;
26253 switch (Res.first) {
26255 case X86::AX: DestReg = X86::AL; break;
26256 case X86::DX: DestReg = X86::DL; break;
26257 case X86::CX: DestReg = X86::CL; break;
26258 case X86::BX: DestReg = X86::BL; break;
26261 Res.first = DestReg;
26262 Res.second = &X86::GR8RegClass;
26264 } else if (VT == MVT::i32 || VT == MVT::f32) {
26265 unsigned DestReg = 0;
26266 switch (Res.first) {
26268 case X86::AX: DestReg = X86::EAX; break;
26269 case X86::DX: DestReg = X86::EDX; break;
26270 case X86::CX: DestReg = X86::ECX; break;
26271 case X86::BX: DestReg = X86::EBX; break;
26272 case X86::SI: DestReg = X86::ESI; break;
26273 case X86::DI: DestReg = X86::EDI; break;
26274 case X86::BP: DestReg = X86::EBP; break;
26275 case X86::SP: DestReg = X86::ESP; break;
26278 Res.first = DestReg;
26279 Res.second = &X86::GR32RegClass;
26281 } else if (VT == MVT::i64 || VT == MVT::f64) {
26282 unsigned DestReg = 0;
26283 switch (Res.first) {
26285 case X86::AX: DestReg = X86::RAX; break;
26286 case X86::DX: DestReg = X86::RDX; break;
26287 case X86::CX: DestReg = X86::RCX; break;
26288 case X86::BX: DestReg = X86::RBX; break;
26289 case X86::SI: DestReg = X86::RSI; break;
26290 case X86::DI: DestReg = X86::RDI; break;
26291 case X86::BP: DestReg = X86::RBP; break;
26292 case X86::SP: DestReg = X86::RSP; break;
26295 Res.first = DestReg;
26296 Res.second = &X86::GR64RegClass;
26299 } else if (Res.second == &X86::FR32RegClass ||
26300 Res.second == &X86::FR64RegClass ||
26301 Res.second == &X86::VR128RegClass ||
26302 Res.second == &X86::VR256RegClass ||
26303 Res.second == &X86::FR32XRegClass ||
26304 Res.second == &X86::FR64XRegClass ||
26305 Res.second == &X86::VR128XRegClass ||
26306 Res.second == &X86::VR256XRegClass ||
26307 Res.second == &X86::VR512RegClass) {
26308 // Handle references to XMM physical registers that got mapped into the
26309 // wrong class. This can happen with constraints like {xmm0} where the
26310 // target independent register mapper will just pick the first match it can
26311 // find, ignoring the required type.
26313 if (VT == MVT::f32 || VT == MVT::i32)
26314 Res.second = &X86::FR32RegClass;
26315 else if (VT == MVT::f64 || VT == MVT::i64)
26316 Res.second = &X86::FR64RegClass;
26317 else if (X86::VR128RegClass.hasType(VT))
26318 Res.second = &X86::VR128RegClass;
26319 else if (X86::VR256RegClass.hasType(VT))
26320 Res.second = &X86::VR256RegClass;
26321 else if (X86::VR512RegClass.hasType(VT))
26322 Res.second = &X86::VR512RegClass;
26328 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26330 // Scaling factors are not free at all.
26331 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26332 // will take 2 allocations in the out of order engine instead of 1
26333 // for plain addressing mode, i.e. inst (reg1).
26335 // vaddps (%rsi,%drx), %ymm0, %ymm1
26336 // Requires two allocations (one for the load, one for the computation)
26338 // vaddps (%rsi), %ymm0, %ymm1
26339 // Requires just 1 allocation, i.e., freeing allocations for other operations
26340 // and having less micro operations to execute.
26342 // For some X86 architectures, this is even worse because for instance for
26343 // stores, the complex addressing mode forces the instruction to use the
26344 // "load" ports instead of the dedicated "store" port.
26345 // E.g., on Haswell:
26346 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26347 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26348 if (isLegalAddressingMode(AM, Ty))
26349 // Scale represents reg2 * scale, thus account for 1
26350 // as soon as we use a second register.
26351 return AM.Scale != 0;
26355 bool X86TargetLowering::isTargetFTOL() const {
26356 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();