1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
43 // Forward declarations.
44 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
46 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
47 : TargetLowering(TM) {
48 Subtarget = &TM.getSubtarget<X86Subtarget>();
49 X86ScalarSSEf64 = Subtarget->hasSSE2();
50 X86ScalarSSEf32 = Subtarget->hasSSE1();
51 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
55 RegInfo = TM.getRegisterInfo();
58 // Set up the TargetLowering object.
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
62 setSetCCResultContents(ZeroOrOneSetCCResult);
63 setSchedulingPreference(SchedulingForRegPressure);
64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
65 setStackPointerRegisterToSaveRestore(X86StackPtr);
67 if (Subtarget->isTargetDarwin()) {
68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
71 } else if (Subtarget->isTargetMingw()) {
72 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
103 if (Subtarget->is64Bit()) {
104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
118 // SSE has no i16 to fp conversion, only i32
119 if (X86ScalarSSEf32) {
120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
121 // f32 and f64 cases are Legal, f80 case is not
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
129 // are Legal, f80 is custom lowered.
130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
138 if (X86ScalarSSEf32) {
139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
140 // f32 and f64 cases are Legal, f80 case is not
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
147 // Handle FP_TO_UINT by promoting the destination to a larger signed
149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
158 // Expand FP_TO_UINT into a select.
159 // FIXME: We would like to use a Custom expander here eventually to do
160 // the optimal thing for SSE vs. the default expansion in the legalizer.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
163 // With SSE3 we can use fisttpll to convert to a signed i64.
164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
167 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
168 if (!X86ScalarSSEf64) {
169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
173 // Scalar integer divide and remainder are lowered to use operations that
174 // produce two results, to match the available instructions. This exposes
175 // the two-result form to trivial CSE, which is able to combine x/y and x%y
176 // into a single instruction.
178 // Scalar integer multiply-high is also lowered to use two-result
179 // operations, to match the available instructions. However, plain multiply
180 // (low) operations are left as Legal, as there are single-result
181 // instructions for this in x86. Using the two-result multiply instructions
182 // when both high and low results are needed must be arranged by dagcombine.
183 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
187 setOperationAction(ISD::SREM , MVT::i8 , Expand);
188 setOperationAction(ISD::UREM , MVT::i8 , Expand);
189 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
190 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
191 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
193 setOperationAction(ISD::SREM , MVT::i16 , Expand);
194 setOperationAction(ISD::UREM , MVT::i16 , Expand);
195 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
196 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
197 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
199 setOperationAction(ISD::SREM , MVT::i32 , Expand);
200 setOperationAction(ISD::UREM , MVT::i32 , Expand);
201 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
205 setOperationAction(ISD::SREM , MVT::i64 , Expand);
206 setOperationAction(ISD::UREM , MVT::i64 , Expand);
208 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
209 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
210 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
212 if (Subtarget->is64Bit())
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
244 // X86 wants to expand cmov itself.
245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
260 // X86 ret instruction may pop stack.
261 setOperationAction(ISD::RET , MVT::Other, Custom);
262 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
265 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
266 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
267 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
268 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
269 if (Subtarget->is64Bit())
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
271 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
272 if (Subtarget->is64Bit()) {
273 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
274 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
275 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
276 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
278 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
279 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
280 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
282 if (Subtarget->is64Bit()) {
283 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
284 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
288 if (Subtarget->hasSSE1())
289 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
291 if (!Subtarget->hasSSE2())
292 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
294 // Expand certain atomics
295 setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
296 setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
297 setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
298 setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
300 setOperationAction(ISD::ATOMIC_LOAD_SUB_8, MVT::i8, Expand);
301 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Expand);
302 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Expand);
303 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Expand);
305 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
306 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
307 // FIXME - use subtarget debug flags
308 if (!Subtarget->isTargetDarwin() &&
309 !Subtarget->isTargetELF() &&
310 !Subtarget->isTargetCygMing()) {
311 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
312 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
315 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
316 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
317 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
318 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
319 if (Subtarget->is64Bit()) {
320 setExceptionPointerRegister(X86::RAX);
321 setExceptionSelectorRegister(X86::RDX);
323 setExceptionPointerRegister(X86::EAX);
324 setExceptionSelectorRegister(X86::EDX);
326 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
327 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
329 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
331 setOperationAction(ISD::TRAP, MVT::Other, Legal);
333 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
334 setOperationAction(ISD::VASTART , MVT::Other, Custom);
335 setOperationAction(ISD::VAEND , MVT::Other, Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::VAARG , MVT::Other, Custom);
338 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
340 setOperationAction(ISD::VAARG , MVT::Other, Expand);
341 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
344 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
345 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
346 if (Subtarget->is64Bit())
347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
348 if (Subtarget->isTargetCygMing())
349 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
353 if (X86ScalarSSEf64) {
354 // f32 and f64 use SSE.
355 // Set up the FP register classes.
356 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
357 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
359 // Use ANDPD to simulate FABS.
360 setOperationAction(ISD::FABS , MVT::f64, Custom);
361 setOperationAction(ISD::FABS , MVT::f32, Custom);
363 // Use XORP to simulate FNEG.
364 setOperationAction(ISD::FNEG , MVT::f64, Custom);
365 setOperationAction(ISD::FNEG , MVT::f32, Custom);
367 // Use ANDPD and ORPD to simulate FCOPYSIGN.
368 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
369 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
371 // We don't support sin/cos/fmod
372 setOperationAction(ISD::FSIN , MVT::f64, Expand);
373 setOperationAction(ISD::FCOS , MVT::f64, Expand);
374 setOperationAction(ISD::FSIN , MVT::f32, Expand);
375 setOperationAction(ISD::FCOS , MVT::f32, Expand);
377 // Expand FP immediates into loads from the stack, except for the special
379 addLegalFPImmediate(APFloat(+0.0)); // xorpd
380 addLegalFPImmediate(APFloat(+0.0f)); // xorps
382 // Floating truncations from f80 and extensions to f80 go through memory.
383 // If optimizing, we lie about this though and handle it in
384 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
386 setConvertAction(MVT::f32, MVT::f80, Expand);
387 setConvertAction(MVT::f64, MVT::f80, Expand);
388 setConvertAction(MVT::f80, MVT::f32, Expand);
389 setConvertAction(MVT::f80, MVT::f64, Expand);
391 } else if (X86ScalarSSEf32) {
392 // Use SSE for f32, x87 for f64.
393 // Set up the FP register classes.
394 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
395 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
397 // Use ANDPS to simulate FABS.
398 setOperationAction(ISD::FABS , MVT::f32, Custom);
400 // Use XORP to simulate FNEG.
401 setOperationAction(ISD::FNEG , MVT::f32, Custom);
403 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
405 // Use ANDPS and ORPS to simulate FCOPYSIGN.
406 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
407 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
409 // We don't support sin/cos/fmod
410 setOperationAction(ISD::FSIN , MVT::f32, Expand);
411 setOperationAction(ISD::FCOS , MVT::f32, Expand);
413 // Special cases we handle for FP constants.
414 addLegalFPImmediate(APFloat(+0.0f)); // xorps
415 addLegalFPImmediate(APFloat(+0.0)); // FLD0
416 addLegalFPImmediate(APFloat(+1.0)); // FLD1
417 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
418 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
420 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
421 // this though and handle it in InstructionSelectPreprocess so that
422 // dagcombine2 can hack on these.
424 setConvertAction(MVT::f32, MVT::f64, Expand);
425 setConvertAction(MVT::f32, MVT::f80, Expand);
426 setConvertAction(MVT::f80, MVT::f32, Expand);
427 setConvertAction(MVT::f64, MVT::f32, Expand);
428 // And x87->x87 truncations also.
429 setConvertAction(MVT::f80, MVT::f64, Expand);
433 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
434 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
437 // f32 and f64 in x87.
438 // Set up the FP register classes.
439 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
440 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
442 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
443 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
444 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
445 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
447 // Floating truncations go through memory. If optimizing, we lie about
448 // this though and handle it in InstructionSelectPreprocess so that
449 // dagcombine2 can hack on these.
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 setConvertAction(MVT::f80, MVT::f64, Expand);
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
460 addLegalFPImmediate(APFloat(+0.0)); // FLD0
461 addLegalFPImmediate(APFloat(+1.0)); // FLD1
462 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
463 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
464 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
465 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
466 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
467 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
470 // Long double always uses X87.
471 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
472 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
473 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
475 APFloat TmpFlt(+0.0);
476 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
477 addLegalFPImmediate(TmpFlt); // FLD0
479 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
480 APFloat TmpFlt2(+1.0);
481 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
482 addLegalFPImmediate(TmpFlt2); // FLD1
483 TmpFlt2.changeSign();
484 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
488 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
489 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
492 // Always use a library call for pow.
493 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
494 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
495 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
497 setOperationAction(ISD::FLOG, MVT::f32, Expand);
498 setOperationAction(ISD::FLOG, MVT::f64, Expand);
499 setOperationAction(ISD::FLOG, MVT::f80, Expand);
500 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
501 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
502 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
503 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
504 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
505 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
506 setOperationAction(ISD::FEXP, MVT::f32, Expand);
507 setOperationAction(ISD::FEXP, MVT::f64, Expand);
508 setOperationAction(ISD::FEXP, MVT::f80, Expand);
509 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
510 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
511 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
513 // First set operation action for all vector types to expand. Then we
514 // will selectively turn on ones that can be effectively codegen'd.
515 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
516 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
517 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
532 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
557 if (Subtarget->hasMMX()) {
558 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
559 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
560 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
561 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
562 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
564 // FIXME: add MMX packed arithmetics
566 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
567 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
568 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
569 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
571 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
572 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
573 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
574 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
576 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
577 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
579 setOperationAction(ISD::AND, MVT::v8i8, Promote);
580 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
581 setOperationAction(ISD::AND, MVT::v4i16, Promote);
582 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
583 setOperationAction(ISD::AND, MVT::v2i32, Promote);
584 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
585 setOperationAction(ISD::AND, MVT::v1i64, Legal);
587 setOperationAction(ISD::OR, MVT::v8i8, Promote);
588 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
589 setOperationAction(ISD::OR, MVT::v4i16, Promote);
590 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
591 setOperationAction(ISD::OR, MVT::v2i32, Promote);
592 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
593 setOperationAction(ISD::OR, MVT::v1i64, Legal);
595 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
596 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
597 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
598 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
599 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
600 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
601 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
603 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
604 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
605 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
606 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
607 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
608 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
609 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
610 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
611 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
613 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
614 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
615 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
616 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
617 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
619 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
621 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
622 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
624 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
625 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
626 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
627 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
629 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
632 if (Subtarget->hasSSE1()) {
633 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
635 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
636 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
637 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
638 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
639 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
640 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
641 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
642 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
644 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
645 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
646 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
649 if (Subtarget->hasSSE2()) {
650 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
651 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
652 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
653 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
654 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
656 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
657 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
658 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
659 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
660 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
661 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
662 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
663 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
664 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
665 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
666 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
667 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
668 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
669 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
670 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
672 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
673 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
674 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
675 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
679 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
680 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
683 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
684 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
685 MVT VT = (MVT::SimpleValueType)i;
686 // Do not attempt to custom lower non-power-of-2 vectors
687 if (!isPowerOf2_32(VT.getVectorNumElements()))
689 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
690 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
691 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
693 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
694 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
695 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
696 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
698 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
699 if (Subtarget->is64Bit()) {
700 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
701 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
704 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
705 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
706 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
707 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
708 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
709 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
710 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
711 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
712 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
713 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
714 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
715 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
718 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
720 // Custom lower v2i64 and v2f64 selects.
721 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
722 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
723 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
724 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
728 if (Subtarget->hasSSE41()) {
729 // FIXME: Do we need to handle scalar-to-vector here?
730 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
731 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
733 // i8 and i16 vectors are custom , because the source register and source
734 // source memory operand types are not the same width. f32 vectors are
735 // custom since the immediate controlling the insert encodes additional
737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
740 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
742 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
744 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
747 if (Subtarget->is64Bit()) {
748 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
749 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
753 if (Subtarget->hasSSE42()) {
754 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
757 // We want to custom lower some of our intrinsics.
758 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
760 // We have target-specific dag combine patterns for the following nodes:
761 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
762 setTargetDAGCombine(ISD::BUILD_VECTOR);
763 setTargetDAGCombine(ISD::SELECT);
764 setTargetDAGCombine(ISD::STORE);
766 computeRegisterProperties();
768 // FIXME: These should be based on subtarget info. Plus, the values should
769 // be smaller when we are in optimizing for size mode.
770 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
771 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
772 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
773 allowUnalignedMemoryAccesses = true; // x86 supports it!
774 setPrefLoopAlignment(16);
778 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
783 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
784 /// the desired ByVal argument alignment.
785 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
788 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
789 if (VTy->getBitWidth() == 128)
791 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
792 unsigned EltAlign = 0;
793 getMaxByValAlign(ATy->getElementType(), EltAlign);
794 if (EltAlign > MaxAlign)
796 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
797 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
798 unsigned EltAlign = 0;
799 getMaxByValAlign(STy->getElementType(i), EltAlign);
800 if (EltAlign > MaxAlign)
809 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
810 /// function arguments in the caller parameter area. For X86, aggregates
811 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
812 /// are at 4-byte boundaries.
813 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
814 if (Subtarget->is64Bit()) {
815 // Max of 8 and alignment of type.
816 unsigned TyAlign = TD->getABITypeAlignment(Ty);
823 if (Subtarget->hasSSE1())
824 getMaxByValAlign(Ty, Align);
828 /// getOptimalMemOpType - Returns the target specific optimal type for load
829 /// and store operations as a result of memset, memcpy, and memmove
830 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
833 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
834 bool isSrcConst, bool isSrcStr) const {
835 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
837 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
839 if (Subtarget->is64Bit() && Size >= 8)
845 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
847 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
848 SelectionDAG &DAG) const {
849 if (usesGlobalOffsetTable())
850 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
851 if (!Subtarget->isPICStyleRIPRel())
852 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
856 //===----------------------------------------------------------------------===//
857 // Return Value Calling Convention Implementation
858 //===----------------------------------------------------------------------===//
860 #include "X86GenCallingConv.inc"
862 /// LowerRET - Lower an ISD::RET node.
863 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
864 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
866 SmallVector<CCValAssign, 16> RVLocs;
867 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
868 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
869 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
870 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
872 // If this is the first return lowered for this function, add the regs to the
873 // liveout set for the function.
874 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
875 for (unsigned i = 0; i != RVLocs.size(); ++i)
876 if (RVLocs[i].isRegLoc())
877 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
879 SDValue Chain = Op.getOperand(0);
881 // Handle tail call return.
882 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
883 if (Chain.getOpcode() == X86ISD::TAILCALL) {
884 SDValue TailCall = Chain;
885 SDValue TargetAddress = TailCall.getOperand(1);
886 SDValue StackAdjustment = TailCall.getOperand(2);
887 assert(((TargetAddress.getOpcode() == ISD::Register &&
888 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
889 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
890 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
891 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
892 "Expecting an global address, external symbol, or register");
893 assert(StackAdjustment.getOpcode() == ISD::Constant &&
894 "Expecting a const value");
896 SmallVector<SDValue,8> Operands;
897 Operands.push_back(Chain.getOperand(0));
898 Operands.push_back(TargetAddress);
899 Operands.push_back(StackAdjustment);
900 // Copy registers used by the call. Last operand is a flag so it is not
902 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
903 Operands.push_back(Chain.getOperand(i));
905 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
912 SmallVector<SDValue, 6> RetOps;
913 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
914 // Operand #1 = Bytes To Pop
915 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
917 // Copy the result values into the output registers.
918 for (unsigned i = 0; i != RVLocs.size(); ++i) {
919 CCValAssign &VA = RVLocs[i];
920 assert(VA.isRegLoc() && "Can only return in registers!");
921 SDValue ValToCopy = Op.getOperand(i*2+1);
923 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
924 // the RET instruction and handled by the FP Stackifier.
925 if (RVLocs[i].getLocReg() == X86::ST0 ||
926 RVLocs[i].getLocReg() == X86::ST1) {
927 // If this is a copy from an xmm register to ST(0), use an FPExtend to
928 // change the value to the FP stack register class.
929 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
930 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
931 RetOps.push_back(ValToCopy);
932 // Don't emit a copytoreg.
936 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
937 Flag = Chain.getValue(1);
940 // The x86-64 ABI for returning structs by value requires that we copy
941 // the sret argument into %rax for the return. We saved the argument into
942 // a virtual register in the entry block, so now we copy the value out
944 if (Subtarget->is64Bit() &&
945 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
946 MachineFunction &MF = DAG.getMachineFunction();
947 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
948 unsigned Reg = FuncInfo->getSRetReturnReg();
950 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
951 FuncInfo->setSRetReturnReg(Reg);
953 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
955 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
956 Flag = Chain.getValue(1);
959 RetOps[0] = Chain; // Update chain.
961 // Add the flag if we have it.
963 RetOps.push_back(Flag);
965 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
969 /// LowerCallResult - Lower the result values of an ISD::CALL into the
970 /// appropriate copies out of appropriate physical registers. This assumes that
971 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
972 /// being lowered. The returns a SDNode with the same number of values as the
974 SDNode *X86TargetLowering::
975 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
976 unsigned CallingConv, SelectionDAG &DAG) {
978 // Assign locations to each value returned by this call.
979 SmallVector<CCValAssign, 16> RVLocs;
980 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
981 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
982 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
984 SmallVector<SDValue, 8> ResultVals;
986 // Copy all of the result registers out of their specified physreg.
987 for (unsigned i = 0; i != RVLocs.size(); ++i) {
988 MVT CopyVT = RVLocs[i].getValVT();
990 // If this is a call to a function that returns an fp value on the floating
991 // point stack, but where we prefer to use the value in xmm registers, copy
992 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
993 if ((RVLocs[i].getLocReg() == X86::ST0 ||
994 RVLocs[i].getLocReg() == X86::ST1) &&
995 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
999 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1000 CopyVT, InFlag).getValue(1);
1001 SDValue Val = Chain.getValue(0);
1002 InFlag = Chain.getValue(2);
1004 if (CopyVT != RVLocs[i].getValVT()) {
1005 // Round the F80 the right size, which also moves to the appropriate xmm
1007 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1008 // This truncation won't change the value.
1009 DAG.getIntPtrConstant(1));
1012 ResultVals.push_back(Val);
1015 // Merge everything together with a MERGE_VALUES node.
1016 ResultVals.push_back(Chain);
1017 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
1018 ResultVals.size()).getNode();
1022 //===----------------------------------------------------------------------===//
1023 // C & StdCall & Fast Calling Convention implementation
1024 //===----------------------------------------------------------------------===//
1025 // StdCall calling convention seems to be standard for many Windows' API
1026 // routines and around. It differs from C calling convention just a little:
1027 // callee should clean up the stack, not caller. Symbols should be also
1028 // decorated in some fancy way :) It doesn't support any vector arguments.
1029 // For info on fast calling convention see Fast Calling Convention (tail call)
1030 // implementation LowerX86_32FastCCCallTo.
1032 /// AddLiveIn - This helper function adds the specified physical register to the
1033 /// MachineFunction as a live in value. It also creates a corresponding virtual
1034 /// register for it.
1035 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1036 const TargetRegisterClass *RC) {
1037 assert(RC->contains(PReg) && "Not the correct regclass!");
1038 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1039 MF.getRegInfo().addLiveIn(PReg, VReg);
1043 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1045 static bool CallIsStructReturn(SDValue Op) {
1046 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1050 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
1053 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1054 /// return semantics.
1055 static bool ArgsAreStructReturn(SDValue Op) {
1056 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1060 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1063 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1064 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1066 bool X86TargetLowering::IsCalleePop(SDValue Op) {
1067 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1071 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1074 case CallingConv::X86_StdCall:
1075 return !Subtarget->is64Bit();
1076 case CallingConv::X86_FastCall:
1077 return !Subtarget->is64Bit();
1078 case CallingConv::Fast:
1079 return PerformTailCallOpt;
1083 /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1084 /// FORMAL_ARGUMENTS node.
1085 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const {
1086 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1088 if (Subtarget->is64Bit()) {
1089 if (Subtarget->isTargetWin64())
1090 return CC_X86_Win64_C;
1091 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1092 return CC_X86_64_TailCall;
1097 if (CC == CallingConv::X86_FastCall)
1098 return CC_X86_32_FastCall;
1099 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1100 return CC_X86_32_TailCall;
1105 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1106 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1108 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1109 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1110 if (CC == CallingConv::X86_FastCall)
1112 else if (CC == CallingConv::X86_StdCall)
1118 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1119 /// in a register before calling.
1120 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1121 return !IsTailCall && !Is64Bit &&
1122 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1123 Subtarget->isPICStyleGOT();
1126 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1127 /// address to be loaded in a register.
1129 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1130 return !Is64Bit && IsTailCall &&
1131 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1132 Subtarget->isPICStyleGOT();
1135 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1136 /// by "Src" to address "Dst" with size and alignment information specified by
1137 /// the specific parameter attribute. The copy will be passed as a byval
1138 /// function parameter.
1140 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1141 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1142 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1143 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1144 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1147 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1148 const CCValAssign &VA,
1149 MachineFrameInfo *MFI,
1151 SDValue Root, unsigned i) {
1152 // Create the nodes corresponding to a load from this parameter slot.
1153 ISD::ArgFlagsTy Flags =
1154 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1155 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1156 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1158 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1159 // changed with more analysis.
1160 // In case of tail call optimization mark all arguments mutable. Since they
1161 // could be overwritten by lowering of arguments in case of a tail call.
1162 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1163 VA.getLocMemOffset(), isImmutable);
1164 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1165 if (Flags.isByVal())
1167 return DAG.getLoad(VA.getValVT(), Root, FIN,
1168 PseudoSourceValue::getFixedStack(FI), 0);
1172 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1173 MachineFunction &MF = DAG.getMachineFunction();
1174 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1176 const Function* Fn = MF.getFunction();
1177 if (Fn->hasExternalLinkage() &&
1178 Subtarget->isTargetCygMing() &&
1179 Fn->getName() == "main")
1180 FuncInfo->setForceFramePointer(true);
1182 // Decorate the function name.
1183 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1185 MachineFrameInfo *MFI = MF.getFrameInfo();
1186 SDValue Root = Op.getOperand(0);
1187 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1188 unsigned CC = MF.getFunction()->getCallingConv();
1189 bool Is64Bit = Subtarget->is64Bit();
1190 bool IsWin64 = Subtarget->isTargetWin64();
1192 assert(!(isVarArg && CC == CallingConv::Fast) &&
1193 "Var args not supported with calling convention fastcc");
1195 // Assign locations to all of the incoming arguments.
1196 SmallVector<CCValAssign, 16> ArgLocs;
1197 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1198 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(Op));
1200 SmallVector<SDValue, 8> ArgValues;
1201 unsigned LastVal = ~0U;
1202 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1203 CCValAssign &VA = ArgLocs[i];
1204 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1206 assert(VA.getValNo() != LastVal &&
1207 "Don't support value assigned to multiple locs yet");
1208 LastVal = VA.getValNo();
1210 if (VA.isRegLoc()) {
1211 MVT RegVT = VA.getLocVT();
1212 TargetRegisterClass *RC;
1213 if (RegVT == MVT::i32)
1214 RC = X86::GR32RegisterClass;
1215 else if (Is64Bit && RegVT == MVT::i64)
1216 RC = X86::GR64RegisterClass;
1217 else if (RegVT == MVT::f32)
1218 RC = X86::FR32RegisterClass;
1219 else if (RegVT == MVT::f64)
1220 RC = X86::FR64RegisterClass;
1221 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1222 RC = X86::VR128RegisterClass;
1223 else if (RegVT.isVector()) {
1224 assert(RegVT.getSizeInBits() == 64);
1226 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1228 // Darwin calling convention passes MMX values in either GPRs or
1229 // XMMs in x86-64. Other targets pass them in memory.
1230 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1231 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1234 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1239 assert(0 && "Unknown argument type!");
1242 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1243 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1245 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1246 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1248 if (VA.getLocInfo() == CCValAssign::SExt)
1249 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1250 DAG.getValueType(VA.getValVT()));
1251 else if (VA.getLocInfo() == CCValAssign::ZExt)
1252 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1253 DAG.getValueType(VA.getValVT()));
1255 if (VA.getLocInfo() != CCValAssign::Full)
1256 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1258 // Handle MMX values passed in GPRs.
1259 if (Is64Bit && RegVT != VA.getLocVT()) {
1260 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1261 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1262 else if (RC == X86::VR128RegisterClass) {
1263 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1264 DAG.getConstant(0, MVT::i64));
1265 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1269 ArgValues.push_back(ArgValue);
1271 assert(VA.isMemLoc());
1272 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1276 // The x86-64 ABI for returning structs by value requires that we copy
1277 // the sret argument into %rax for the return. Save the argument into
1278 // a virtual register so that we can access it from the return points.
1279 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1280 MachineFunction &MF = DAG.getMachineFunction();
1281 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1282 unsigned Reg = FuncInfo->getSRetReturnReg();
1284 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1285 FuncInfo->setSRetReturnReg(Reg);
1287 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1288 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1291 unsigned StackSize = CCInfo.getNextStackOffset();
1292 // align stack specially for tail calls
1293 if (PerformTailCallOpt && CC == CallingConv::Fast)
1294 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1296 // If the function takes variable number of arguments, make a frame index for
1297 // the start of the first vararg value... for expansion of llvm.va_start.
1299 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1300 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1303 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1305 // FIXME: We should really autogenerate these arrays
1306 static const unsigned GPR64ArgRegsWin64[] = {
1307 X86::RCX, X86::RDX, X86::R8, X86::R9
1309 static const unsigned XMMArgRegsWin64[] = {
1310 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1312 static const unsigned GPR64ArgRegs64Bit[] = {
1313 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1315 static const unsigned XMMArgRegs64Bit[] = {
1316 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1317 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1319 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1322 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1323 GPR64ArgRegs = GPR64ArgRegsWin64;
1324 XMMArgRegs = XMMArgRegsWin64;
1326 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1327 GPR64ArgRegs = GPR64ArgRegs64Bit;
1328 XMMArgRegs = XMMArgRegs64Bit;
1330 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1332 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1335 // For X86-64, if there are vararg parameters that are passed via
1336 // registers, then we must store them to their spots on the stack so they
1337 // may be loaded by deferencing the result of va_next.
1338 VarArgsGPOffset = NumIntRegs * 8;
1339 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1340 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1341 TotalNumXMMRegs * 16, 16);
1343 // Store the integer parameter registers.
1344 SmallVector<SDValue, 8> MemOps;
1345 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1346 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1347 DAG.getIntPtrConstant(VarArgsGPOffset));
1348 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1349 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1350 X86::GR64RegisterClass);
1351 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1353 DAG.getStore(Val.getValue(1), Val, FIN,
1354 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1355 MemOps.push_back(Store);
1356 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1357 DAG.getIntPtrConstant(8));
1360 // Now store the XMM (fp + vector) parameter registers.
1361 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1362 DAG.getIntPtrConstant(VarArgsFPOffset));
1363 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1364 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1365 X86::VR128RegisterClass);
1366 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1368 DAG.getStore(Val.getValue(1), Val, FIN,
1369 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1370 MemOps.push_back(Store);
1371 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1372 DAG.getIntPtrConstant(16));
1374 if (!MemOps.empty())
1375 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1376 &MemOps[0], MemOps.size());
1380 ArgValues.push_back(Root);
1382 // Some CCs need callee pop.
1383 if (IsCalleePop(Op)) {
1384 BytesToPopOnReturn = StackSize; // Callee pops everything.
1385 BytesCallerReserves = 0;
1387 BytesToPopOnReturn = 0; // Callee pops nothing.
1388 // If this is an sret function, the return should pop the hidden pointer.
1389 if (!Is64Bit && ArgsAreStructReturn(Op))
1390 BytesToPopOnReturn = 4;
1391 BytesCallerReserves = StackSize;
1395 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1396 if (CC == CallingConv::X86_FastCall)
1397 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1400 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1402 // Return the new list of results.
1403 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1404 ArgValues.size()).getValue(Op.getResNo());
1408 X86TargetLowering::LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
1409 const SDValue &StackPtr,
1410 const CCValAssign &VA,
1413 unsigned LocMemOffset = VA.getLocMemOffset();
1414 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1415 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1416 ISD::ArgFlagsTy Flags =
1417 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1418 if (Flags.isByVal()) {
1419 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1421 return DAG.getStore(Chain, Arg, PtrOff,
1422 PseudoSourceValue::getStack(), LocMemOffset);
1425 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1426 /// optimization is performed and it is required.
1428 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1429 SDValue &OutRetAddr,
1434 if (!IsTailCall || FPDiff==0) return Chain;
1436 // Adjust the Return address stack slot.
1437 MVT VT = getPointerTy();
1438 OutRetAddr = getReturnAddressFrameIndex(DAG);
1439 // Load the "old" Return address.
1440 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1441 return SDValue(OutRetAddr.getNode(), 1);
1444 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1445 /// optimization is performed and it is required (FPDiff!=0).
1447 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1448 SDValue Chain, SDValue RetAddrFrIdx,
1449 bool Is64Bit, int FPDiff) {
1450 // Store the return address to the appropriate stack slot.
1451 if (!FPDiff) return Chain;
1452 // Calculate the new stack slot for the return address.
1453 int SlotSize = Is64Bit ? 8 : 4;
1454 int NewReturnAddrFI =
1455 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1456 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1457 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1458 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1459 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1463 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1464 MachineFunction &MF = DAG.getMachineFunction();
1465 SDValue Chain = Op.getOperand(0);
1466 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1467 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1468 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1469 && CC == CallingConv::Fast && PerformTailCallOpt;
1470 SDValue Callee = Op.getOperand(4);
1471 bool Is64Bit = Subtarget->is64Bit();
1472 bool IsStructRet = CallIsStructReturn(Op);
1474 assert(!(isVarArg && CC == CallingConv::Fast) &&
1475 "Var args not supported with calling convention fastcc");
1477 // Analyze operands of the call, assigning locations to each operand.
1478 SmallVector<CCValAssign, 16> ArgLocs;
1479 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1480 CCInfo.AnalyzeCallOperands(Op.getNode(), CCAssignFnForNode(Op));
1482 // Get a count of how many bytes are to be pushed on the stack.
1483 unsigned NumBytes = CCInfo.getNextStackOffset();
1485 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1489 // Lower arguments at fp - stackoffset + fpdiff.
1490 unsigned NumBytesCallerPushed =
1491 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1492 FPDiff = NumBytesCallerPushed - NumBytes;
1494 // Set the delta of movement of the returnaddr stackslot.
1495 // But only set if delta is greater than previous delta.
1496 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1497 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1500 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1502 SDValue RetAddrFrIdx;
1503 // Load return adress for tail calls.
1504 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1507 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1508 SmallVector<SDValue, 8> MemOpChains;
1511 // Walk the register/memloc assignments, inserting copies/loads. In the case
1512 // of tail call optimization arguments are handle later.
1513 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1514 CCValAssign &VA = ArgLocs[i];
1515 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
1516 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
1517 getArgFlags().isByVal();
1519 // Promote the value if needed.
1520 switch (VA.getLocInfo()) {
1521 default: assert(0 && "Unknown loc info!");
1522 case CCValAssign::Full: break;
1523 case CCValAssign::SExt:
1524 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1526 case CCValAssign::ZExt:
1527 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1529 case CCValAssign::AExt:
1530 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1534 if (VA.isRegLoc()) {
1536 MVT RegVT = VA.getLocVT();
1537 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1538 switch (VA.getLocReg()) {
1541 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1543 // Special case: passing MMX values in GPR registers.
1544 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1547 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1548 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1549 // Special case: passing MMX values in XMM registers.
1550 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1551 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1552 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1553 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1554 getMOVLMask(2, DAG));
1559 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1561 if (!IsTailCall || (IsTailCall && isByVal)) {
1562 assert(VA.isMemLoc());
1563 if (StackPtr.getNode() == 0)
1564 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1566 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1572 if (!MemOpChains.empty())
1573 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1574 &MemOpChains[0], MemOpChains.size());
1576 // Build a sequence of copy-to-reg nodes chained together with token chain
1577 // and flag operands which copy the outgoing args into registers.
1579 // Tail call byval lowering might overwrite argument registers so in case of
1580 // tail call optimization the copies to registers are lowered later.
1582 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1583 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1585 InFlag = Chain.getValue(1);
1588 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1590 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1591 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1592 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1594 InFlag = Chain.getValue(1);
1596 // If we are tail calling and generating PIC/GOT style code load the address
1597 // of the callee into ecx. The value in ecx is used as target of the tail
1598 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1599 // calls on PIC/GOT architectures. Normally we would just put the address of
1600 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1601 // restored (since ebx is callee saved) before jumping to the target@PLT.
1602 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1603 // Note: The actual moving to ecx is done further down.
1604 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1605 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1606 !G->getGlobal()->hasProtectedVisibility())
1607 Callee = LowerGlobalAddress(Callee, DAG);
1608 else if (isa<ExternalSymbolSDNode>(Callee))
1609 Callee = LowerExternalSymbol(Callee,DAG);
1612 if (Is64Bit && isVarArg) {
1613 // From AMD64 ABI document:
1614 // For calls that may call functions that use varargs or stdargs
1615 // (prototype-less calls or calls to functions containing ellipsis (...) in
1616 // the declaration) %al is used as hidden argument to specify the number
1617 // of SSE registers used. The contents of %al do not need to match exactly
1618 // the number of registers, but must be an ubound on the number of SSE
1619 // registers used and is in the range 0 - 8 inclusive.
1621 // FIXME: Verify this on Win64
1622 // Count the number of XMM registers allocated.
1623 static const unsigned XMMArgRegs[] = {
1624 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1625 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1627 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1629 Chain = DAG.getCopyToReg(Chain, X86::AL,
1630 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1631 InFlag = Chain.getValue(1);
1635 // For tail calls lower the arguments to the 'real' stack slot.
1637 SmallVector<SDValue, 8> MemOpChains2;
1640 // Do not flag preceeding copytoreg stuff together with the following stuff.
1642 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1643 CCValAssign &VA = ArgLocs[i];
1644 if (!VA.isRegLoc()) {
1645 assert(VA.isMemLoc());
1646 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
1647 SDValue FlagsOp = Op.getOperand(6+2*VA.getValNo());
1648 ISD::ArgFlagsTy Flags =
1649 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
1650 // Create frame index.
1651 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1652 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1653 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1654 FIN = DAG.getFrameIndex(FI, getPointerTy());
1656 if (Flags.isByVal()) {
1657 // Copy relative to framepointer.
1658 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1659 if (StackPtr.getNode() == 0)
1660 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1661 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1663 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1666 // Store relative to framepointer.
1667 MemOpChains2.push_back(
1668 DAG.getStore(Chain, Arg, FIN,
1669 PseudoSourceValue::getFixedStack(FI), 0));
1674 if (!MemOpChains2.empty())
1675 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1676 &MemOpChains2[0], MemOpChains2.size());
1678 // Copy arguments to their registers.
1679 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1680 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1682 InFlag = Chain.getValue(1);
1686 // Store the return address to the appropriate stack slot.
1687 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1691 // If the callee is a GlobalAddress node (quite common, every direct call is)
1692 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1693 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1694 // We should use extra load for direct calls to dllimported functions in
1696 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1697 getTargetMachine(), true))
1698 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1699 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1700 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1701 } else if (IsTailCall) {
1702 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1704 Chain = DAG.getCopyToReg(Chain,
1705 DAG.getRegister(Opc, getPointerTy()),
1707 Callee = DAG.getRegister(Opc, getPointerTy());
1708 // Add register as live out.
1709 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1712 // Returns a chain & a flag for retval copy to use.
1713 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1714 SmallVector<SDValue, 8> Ops;
1717 Ops.push_back(Chain);
1718 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1719 Ops.push_back(DAG.getIntPtrConstant(0));
1720 if (InFlag.getNode())
1721 Ops.push_back(InFlag);
1722 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1723 InFlag = Chain.getValue(1);
1725 // Returns a chain & a flag for retval copy to use.
1726 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1730 Ops.push_back(Chain);
1731 Ops.push_back(Callee);
1734 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1736 // Add argument registers to the end of the list so that they are known live
1738 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1739 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1740 RegsToPass[i].second.getValueType()));
1742 // Add an implicit use GOT pointer in EBX.
1743 if (!IsTailCall && !Is64Bit &&
1744 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1745 Subtarget->isPICStyleGOT())
1746 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1748 // Add an implicit use of AL for x86 vararg functions.
1749 if (Is64Bit && isVarArg)
1750 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1752 if (InFlag.getNode())
1753 Ops.push_back(InFlag);
1756 assert(InFlag.getNode() &&
1757 "Flag must be set. Depend on flag being set in LowerRET");
1758 Chain = DAG.getNode(X86ISD::TAILCALL,
1759 Op.getNode()->getVTList(), &Ops[0], Ops.size());
1761 return SDValue(Chain.getNode(), Op.getResNo());
1764 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1765 InFlag = Chain.getValue(1);
1767 // Create the CALLSEQ_END node.
1768 unsigned NumBytesForCalleeToPush;
1769 if (IsCalleePop(Op))
1770 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1771 else if (!Is64Bit && IsStructRet)
1772 // If this is is a call to a struct-return function, the callee
1773 // pops the hidden struct pointer, so we have to push it back.
1774 // This is common for Darwin/X86, Linux & Mingw32 targets.
1775 NumBytesForCalleeToPush = 4;
1777 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1779 // Returns a flag for retval copy to use.
1780 Chain = DAG.getCALLSEQ_END(Chain,
1781 DAG.getIntPtrConstant(NumBytes),
1782 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1784 InFlag = Chain.getValue(1);
1786 // Handle result values, copying them out of physregs into vregs that we
1788 return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC, DAG),
1793 //===----------------------------------------------------------------------===//
1794 // Fast Calling Convention (tail call) implementation
1795 //===----------------------------------------------------------------------===//
1797 // Like std call, callee cleans arguments, convention except that ECX is
1798 // reserved for storing the tail called function address. Only 2 registers are
1799 // free for argument passing (inreg). Tail call optimization is performed
1801 // * tailcallopt is enabled
1802 // * caller/callee are fastcc
1803 // On X86_64 architecture with GOT-style position independent code only local
1804 // (within module) calls are supported at the moment.
1805 // To keep the stack aligned according to platform abi the function
1806 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1807 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1808 // If a tail called function callee has more arguments than the caller the
1809 // caller needs to make sure that there is room to move the RETADDR to. This is
1810 // achieved by reserving an area the size of the argument delta right after the
1811 // original REtADDR, but before the saved framepointer or the spilled registers
1812 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1824 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1825 /// for a 16 byte align requirement.
1826 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1827 SelectionDAG& DAG) {
1828 MachineFunction &MF = DAG.getMachineFunction();
1829 const TargetMachine &TM = MF.getTarget();
1830 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1831 unsigned StackAlignment = TFI.getStackAlignment();
1832 uint64_t AlignMask = StackAlignment - 1;
1833 int64_t Offset = StackSize;
1834 uint64_t SlotSize = TD->getPointerSize();
1835 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1836 // Number smaller than 12 so just add the difference.
1837 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1839 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1840 Offset = ((~AlignMask) & Offset) + StackAlignment +
1841 (StackAlignment-SlotSize);
1846 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1847 /// following the call is a return. A function is eligible if caller/callee
1848 /// calling conventions match, currently only fastcc supports tail calls, and
1849 /// the function CALL is immediatly followed by a RET.
1850 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
1852 SelectionDAG& DAG) const {
1853 if (!PerformTailCallOpt)
1856 if (CheckTailCallReturnConstraints(Call, Ret)) {
1857 MachineFunction &MF = DAG.getMachineFunction();
1858 unsigned CallerCC = MF.getFunction()->getCallingConv();
1859 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1860 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1861 SDValue Callee = Call.getOperand(4);
1862 // On x86/32Bit PIC/GOT tail calls are supported.
1863 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1864 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1867 // Can only do local tail calls (in same module, hidden or protected) on
1868 // x86_64 PIC/GOT at the moment.
1869 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1870 return G->getGlobal()->hasHiddenVisibility()
1871 || G->getGlobal()->hasProtectedVisibility();
1879 X86TargetLowering::createFastISel(MachineFunction &mf,
1880 DenseMap<const Value *, unsigned> &vm,
1881 DenseMap<const BasicBlock *,
1882 MachineBasicBlock *> &bm) {
1883 return X86::createFastISel(mf, vm, bm);
1887 //===----------------------------------------------------------------------===//
1888 // Other Lowering Hooks
1889 //===----------------------------------------------------------------------===//
1892 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1893 MachineFunction &MF = DAG.getMachineFunction();
1894 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1895 int ReturnAddrIndex = FuncInfo->getRAIndex();
1896 uint64_t SlotSize = TD->getPointerSize();
1898 if (ReturnAddrIndex == 0) {
1899 // Set up a frame object for the return address.
1900 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1901 FuncInfo->setRAIndex(ReturnAddrIndex);
1904 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1908 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1909 /// specific condition code. It returns a false if it cannot do a direct
1910 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1912 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1913 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1914 SelectionDAG &DAG) {
1915 X86CC = X86::COND_INVALID;
1917 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1918 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1919 // X > -1 -> X == 0, jump !sign.
1920 RHS = DAG.getConstant(0, RHS.getValueType());
1921 X86CC = X86::COND_NS;
1923 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1924 // X < 0 -> X == 0, jump on sign.
1925 X86CC = X86::COND_S;
1927 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1929 RHS = DAG.getConstant(0, RHS.getValueType());
1930 X86CC = X86::COND_LE;
1935 switch (SetCCOpcode) {
1937 case ISD::SETEQ: X86CC = X86::COND_E; break;
1938 case ISD::SETGT: X86CC = X86::COND_G; break;
1939 case ISD::SETGE: X86CC = X86::COND_GE; break;
1940 case ISD::SETLT: X86CC = X86::COND_L; break;
1941 case ISD::SETLE: X86CC = X86::COND_LE; break;
1942 case ISD::SETNE: X86CC = X86::COND_NE; break;
1943 case ISD::SETULT: X86CC = X86::COND_B; break;
1944 case ISD::SETUGT: X86CC = X86::COND_A; break;
1945 case ISD::SETULE: X86CC = X86::COND_BE; break;
1946 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1949 // First determine if it requires or is profitable to flip the operands.
1951 switch (SetCCOpcode) {
1961 // If LHS is a foldable load, but RHS is not, flip the condition.
1963 (ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
1964 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
1965 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1969 std::swap(LHS, RHS);
1971 // On a floating point condition, the flags are set as follows:
1973 // 0 | 0 | 0 | X > Y
1974 // 0 | 0 | 1 | X < Y
1975 // 1 | 0 | 0 | X == Y
1976 // 1 | 1 | 1 | unordered
1977 switch (SetCCOpcode) {
1981 X86CC = X86::COND_E;
1983 case ISD::SETOLT: // flipped
1986 X86CC = X86::COND_A;
1988 case ISD::SETOLE: // flipped
1991 X86CC = X86::COND_AE;
1993 case ISD::SETUGT: // flipped
1996 X86CC = X86::COND_B;
1998 case ISD::SETUGE: // flipped
2001 X86CC = X86::COND_BE;
2005 X86CC = X86::COND_NE;
2008 X86CC = X86::COND_P;
2011 X86CC = X86::COND_NP;
2016 return X86CC != X86::COND_INVALID;
2019 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2020 /// code. Current x86 isa includes the following FP cmov instructions:
2021 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2022 static bool hasFPCMov(unsigned X86CC) {
2038 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2039 /// true if Op is undef or if its value falls within the specified range (L, H].
2040 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2041 if (Op.getOpcode() == ISD::UNDEF)
2044 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
2045 return (Val >= Low && Val < Hi);
2048 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2049 /// true if Op is undef or if its value equal to the specified value.
2050 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2051 if (Op.getOpcode() == ISD::UNDEF)
2053 return cast<ConstantSDNode>(Op)->getValue() == Val;
2056 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2057 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2058 bool X86::isPSHUFDMask(SDNode *N) {
2059 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2061 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2064 // Check if the value doesn't reference the second vector.
2065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2066 SDValue Arg = N->getOperand(i);
2067 if (Arg.getOpcode() == ISD::UNDEF) continue;
2068 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2069 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
2076 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2077 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2078 bool X86::isPSHUFHWMask(SDNode *N) {
2079 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2081 if (N->getNumOperands() != 8)
2084 // Lower quadword copied in order.
2085 for (unsigned i = 0; i != 4; ++i) {
2086 SDValue Arg = N->getOperand(i);
2087 if (Arg.getOpcode() == ISD::UNDEF) continue;
2088 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2089 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2093 // Upper quadword shuffled.
2094 for (unsigned i = 4; i != 8; ++i) {
2095 SDValue Arg = N->getOperand(i);
2096 if (Arg.getOpcode() == ISD::UNDEF) continue;
2097 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2098 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2099 if (Val < 4 || Val > 7)
2106 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2107 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2108 bool X86::isPSHUFLWMask(SDNode *N) {
2109 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2111 if (N->getNumOperands() != 8)
2114 // Upper quadword copied in order.
2115 for (unsigned i = 4; i != 8; ++i)
2116 if (!isUndefOrEqual(N->getOperand(i), i))
2119 // Lower quadword shuffled.
2120 for (unsigned i = 0; i != 4; ++i)
2121 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2127 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2128 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2129 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2130 if (NumElems != 2 && NumElems != 4) return false;
2132 unsigned Half = NumElems / 2;
2133 for (unsigned i = 0; i < Half; ++i)
2134 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2136 for (unsigned i = Half; i < NumElems; ++i)
2137 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2143 bool X86::isSHUFPMask(SDNode *N) {
2144 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2145 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2148 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2149 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2150 /// half elements to come from vector 1 (which would equal the dest.) and
2151 /// the upper half to come from vector 2.
2152 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2153 if (NumOps != 2 && NumOps != 4) return false;
2155 unsigned Half = NumOps / 2;
2156 for (unsigned i = 0; i < Half; ++i)
2157 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2159 for (unsigned i = Half; i < NumOps; ++i)
2160 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2165 static bool isCommutedSHUFP(SDNode *N) {
2166 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2167 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2170 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2171 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2172 bool X86::isMOVHLPSMask(SDNode *N) {
2173 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2175 if (N->getNumOperands() != 4)
2178 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2179 return isUndefOrEqual(N->getOperand(0), 6) &&
2180 isUndefOrEqual(N->getOperand(1), 7) &&
2181 isUndefOrEqual(N->getOperand(2), 2) &&
2182 isUndefOrEqual(N->getOperand(3), 3);
2185 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2186 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2188 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2189 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2191 if (N->getNumOperands() != 4)
2194 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2195 return isUndefOrEqual(N->getOperand(0), 2) &&
2196 isUndefOrEqual(N->getOperand(1), 3) &&
2197 isUndefOrEqual(N->getOperand(2), 2) &&
2198 isUndefOrEqual(N->getOperand(3), 3);
2201 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2202 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2203 bool X86::isMOVLPMask(SDNode *N) {
2204 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2206 unsigned NumElems = N->getNumOperands();
2207 if (NumElems != 2 && NumElems != 4)
2210 for (unsigned i = 0; i < NumElems/2; ++i)
2211 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2214 for (unsigned i = NumElems/2; i < NumElems; ++i)
2215 if (!isUndefOrEqual(N->getOperand(i), i))
2221 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2222 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2224 bool X86::isMOVHPMask(SDNode *N) {
2225 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2227 unsigned NumElems = N->getNumOperands();
2228 if (NumElems != 2 && NumElems != 4)
2231 for (unsigned i = 0; i < NumElems/2; ++i)
2232 if (!isUndefOrEqual(N->getOperand(i), i))
2235 for (unsigned i = 0; i < NumElems/2; ++i) {
2236 SDValue Arg = N->getOperand(i + NumElems/2);
2237 if (!isUndefOrEqual(Arg, i + NumElems))
2244 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2245 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2246 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2247 bool V2IsSplat = false) {
2248 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2251 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2252 SDValue BitI = Elts[i];
2253 SDValue BitI1 = Elts[i+1];
2254 if (!isUndefOrEqual(BitI, j))
2257 if (isUndefOrEqual(BitI1, NumElts))
2260 if (!isUndefOrEqual(BitI1, j + NumElts))
2268 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2269 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2270 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2273 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2274 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2275 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2276 bool V2IsSplat = false) {
2277 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2280 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2281 SDValue BitI = Elts[i];
2282 SDValue BitI1 = Elts[i+1];
2283 if (!isUndefOrEqual(BitI, j + NumElts/2))
2286 if (isUndefOrEqual(BitI1, NumElts))
2289 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2297 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2298 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2299 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2302 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2303 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2305 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2306 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2308 unsigned NumElems = N->getNumOperands();
2309 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2312 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2313 SDValue BitI = N->getOperand(i);
2314 SDValue BitI1 = N->getOperand(i+1);
2316 if (!isUndefOrEqual(BitI, j))
2318 if (!isUndefOrEqual(BitI1, j))
2325 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2326 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2328 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2329 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2331 unsigned NumElems = N->getNumOperands();
2332 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2335 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2336 SDValue BitI = N->getOperand(i);
2337 SDValue BitI1 = N->getOperand(i + 1);
2339 if (!isUndefOrEqual(BitI, j))
2341 if (!isUndefOrEqual(BitI1, j))
2348 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2349 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2350 /// MOVSD, and MOVD, i.e. setting the lowest element.
2351 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2352 if (NumElts != 2 && NumElts != 4)
2355 if (!isUndefOrEqual(Elts[0], NumElts))
2358 for (unsigned i = 1; i < NumElts; ++i) {
2359 if (!isUndefOrEqual(Elts[i], i))
2366 bool X86::isMOVLMask(SDNode *N) {
2367 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2368 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2371 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2372 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2373 /// element of vector 2 and the other elements to come from vector 1 in order.
2374 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2375 bool V2IsSplat = false,
2376 bool V2IsUndef = false) {
2377 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2380 if (!isUndefOrEqual(Ops[0], 0))
2383 for (unsigned i = 1; i < NumOps; ++i) {
2384 SDValue Arg = Ops[i];
2385 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2386 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2387 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2394 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2395 bool V2IsUndef = false) {
2396 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2397 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2398 V2IsSplat, V2IsUndef);
2401 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2402 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2403 bool X86::isMOVSHDUPMask(SDNode *N) {
2404 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2406 if (N->getNumOperands() != 4)
2409 // Expect 1, 1, 3, 3
2410 for (unsigned i = 0; i < 2; ++i) {
2411 SDValue Arg = N->getOperand(i);
2412 if (Arg.getOpcode() == ISD::UNDEF) continue;
2413 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2414 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2415 if (Val != 1) return false;
2419 for (unsigned i = 2; i < 4; ++i) {
2420 SDValue Arg = N->getOperand(i);
2421 if (Arg.getOpcode() == ISD::UNDEF) continue;
2422 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2423 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2424 if (Val != 3) return false;
2428 // Don't use movshdup if it can be done with a shufps.
2432 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2433 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2434 bool X86::isMOVSLDUPMask(SDNode *N) {
2435 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2437 if (N->getNumOperands() != 4)
2440 // Expect 0, 0, 2, 2
2441 for (unsigned i = 0; i < 2; ++i) {
2442 SDValue Arg = N->getOperand(i);
2443 if (Arg.getOpcode() == ISD::UNDEF) continue;
2444 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2445 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2446 if (Val != 0) return false;
2450 for (unsigned i = 2; i < 4; ++i) {
2451 SDValue Arg = N->getOperand(i);
2452 if (Arg.getOpcode() == ISD::UNDEF) continue;
2453 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2454 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2455 if (Val != 2) return false;
2459 // Don't use movshdup if it can be done with a shufps.
2463 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2464 /// specifies a identity operation on the LHS or RHS.
2465 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2466 unsigned NumElems = N->getNumOperands();
2467 for (unsigned i = 0; i < NumElems; ++i)
2468 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2473 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2474 /// a splat of a single element.
2475 static bool isSplatMask(SDNode *N) {
2476 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2478 // This is a splat operation if each element of the permute is the same, and
2479 // if the value doesn't reference the second vector.
2480 unsigned NumElems = N->getNumOperands();
2481 SDValue ElementBase;
2483 for (; i != NumElems; ++i) {
2484 SDValue Elt = N->getOperand(i);
2485 if (isa<ConstantSDNode>(Elt)) {
2491 if (!ElementBase.getNode())
2494 for (; i != NumElems; ++i) {
2495 SDValue Arg = N->getOperand(i);
2496 if (Arg.getOpcode() == ISD::UNDEF) continue;
2497 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2498 if (Arg != ElementBase) return false;
2501 // Make sure it is a splat of the first vector operand.
2502 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2505 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2506 /// a splat of a single element and it's a 2 or 4 element mask.
2507 bool X86::isSplatMask(SDNode *N) {
2508 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2510 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2511 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2513 return ::isSplatMask(N);
2516 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2517 /// specifies a splat of zero element.
2518 bool X86::isSplatLoMask(SDNode *N) {
2519 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2521 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2522 if (!isUndefOrEqual(N->getOperand(i), 0))
2527 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2528 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2530 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2531 unsigned NumOperands = N->getNumOperands();
2532 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2534 for (unsigned i = 0; i < NumOperands; ++i) {
2536 SDValue Arg = N->getOperand(NumOperands-i-1);
2537 if (Arg.getOpcode() != ISD::UNDEF)
2538 Val = cast<ConstantSDNode>(Arg)->getValue();
2539 if (Val >= NumOperands) Val -= NumOperands;
2541 if (i != NumOperands - 1)
2548 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2549 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2551 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2553 // 8 nodes, but we only care about the last 4.
2554 for (unsigned i = 7; i >= 4; --i) {
2556 SDValue Arg = N->getOperand(i);
2557 if (Arg.getOpcode() != ISD::UNDEF)
2558 Val = cast<ConstantSDNode>(Arg)->getValue();
2567 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2568 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2570 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2572 // 8 nodes, but we only care about the first 4.
2573 for (int i = 3; i >= 0; --i) {
2575 SDValue Arg = N->getOperand(i);
2576 if (Arg.getOpcode() != ISD::UNDEF)
2577 Val = cast<ConstantSDNode>(Arg)->getValue();
2586 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2587 /// specifies a 8 element shuffle that can be broken into a pair of
2588 /// PSHUFHW and PSHUFLW.
2589 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2590 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2592 if (N->getNumOperands() != 8)
2595 // Lower quadword shuffled.
2596 for (unsigned i = 0; i != 4; ++i) {
2597 SDValue Arg = N->getOperand(i);
2598 if (Arg.getOpcode() == ISD::UNDEF) continue;
2599 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2600 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2605 // Upper quadword shuffled.
2606 for (unsigned i = 4; i != 8; ++i) {
2607 SDValue Arg = N->getOperand(i);
2608 if (Arg.getOpcode() == ISD::UNDEF) continue;
2609 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2610 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2611 if (Val < 4 || Val > 7)
2618 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2619 /// values in ther permute mask.
2620 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2621 SDValue &V2, SDValue &Mask,
2622 SelectionDAG &DAG) {
2623 MVT VT = Op.getValueType();
2624 MVT MaskVT = Mask.getValueType();
2625 MVT EltVT = MaskVT.getVectorElementType();
2626 unsigned NumElems = Mask.getNumOperands();
2627 SmallVector<SDValue, 8> MaskVec;
2629 for (unsigned i = 0; i != NumElems; ++i) {
2630 SDValue Arg = Mask.getOperand(i);
2631 if (Arg.getOpcode() == ISD::UNDEF) {
2632 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2635 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2636 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2638 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2640 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2644 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2645 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2648 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2649 /// the two vector operands have swapped position.
2651 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2652 MVT MaskVT = Mask.getValueType();
2653 MVT EltVT = MaskVT.getVectorElementType();
2654 unsigned NumElems = Mask.getNumOperands();
2655 SmallVector<SDValue, 8> MaskVec;
2656 for (unsigned i = 0; i != NumElems; ++i) {
2657 SDValue Arg = Mask.getOperand(i);
2658 if (Arg.getOpcode() == ISD::UNDEF) {
2659 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2662 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2663 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2665 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2667 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2669 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2673 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2674 /// match movhlps. The lower half elements should come from upper half of
2675 /// V1 (and in order), and the upper half elements should come from the upper
2676 /// half of V2 (and in order).
2677 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2678 unsigned NumElems = Mask->getNumOperands();
2681 for (unsigned i = 0, e = 2; i != e; ++i)
2682 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2684 for (unsigned i = 2; i != 4; ++i)
2685 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2690 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2691 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2693 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2694 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2695 N = N->getOperand(0).getNode();
2696 if (ISD::isNON_EXTLoad(N)) {
2698 *LD = cast<LoadSDNode>(N);
2705 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2706 /// match movlp{s|d}. The lower half elements should come from lower half of
2707 /// V1 (and in order), and the upper half elements should come from the upper
2708 /// half of V2 (and in order). And since V1 will become the source of the
2709 /// MOVLP, it must be either a vector load or a scalar load to vector.
2710 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2711 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2713 // Is V2 is a vector load, don't do this transformation. We will try to use
2714 // load folding shufps op.
2715 if (ISD::isNON_EXTLoad(V2))
2718 unsigned NumElems = Mask->getNumOperands();
2719 if (NumElems != 2 && NumElems != 4)
2721 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2722 if (!isUndefOrEqual(Mask->getOperand(i), i))
2724 for (unsigned i = NumElems/2; i != NumElems; ++i)
2725 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2730 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2732 static bool isSplatVector(SDNode *N) {
2733 if (N->getOpcode() != ISD::BUILD_VECTOR)
2736 SDValue SplatValue = N->getOperand(0);
2737 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2738 if (N->getOperand(i) != SplatValue)
2743 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2745 static bool isUndefShuffle(SDNode *N) {
2746 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2749 SDValue V1 = N->getOperand(0);
2750 SDValue V2 = N->getOperand(1);
2751 SDValue Mask = N->getOperand(2);
2752 unsigned NumElems = Mask.getNumOperands();
2753 for (unsigned i = 0; i != NumElems; ++i) {
2754 SDValue Arg = Mask.getOperand(i);
2755 if (Arg.getOpcode() != ISD::UNDEF) {
2756 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2757 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2759 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2766 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2768 static inline bool isZeroNode(SDValue Elt) {
2769 return ((isa<ConstantSDNode>(Elt) &&
2770 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2771 (isa<ConstantFPSDNode>(Elt) &&
2772 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2775 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2776 /// to an zero vector.
2777 static bool isZeroShuffle(SDNode *N) {
2778 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2781 SDValue V1 = N->getOperand(0);
2782 SDValue V2 = N->getOperand(1);
2783 SDValue Mask = N->getOperand(2);
2784 unsigned NumElems = Mask.getNumOperands();
2785 for (unsigned i = 0; i != NumElems; ++i) {
2786 SDValue Arg = Mask.getOperand(i);
2787 if (Arg.getOpcode() == ISD::UNDEF)
2790 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2791 if (Idx < NumElems) {
2792 unsigned Opc = V1.getNode()->getOpcode();
2793 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2795 if (Opc != ISD::BUILD_VECTOR ||
2796 !isZeroNode(V1.getNode()->getOperand(Idx)))
2798 } else if (Idx >= NumElems) {
2799 unsigned Opc = V2.getNode()->getOpcode();
2800 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2802 if (Opc != ISD::BUILD_VECTOR ||
2803 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2810 /// getZeroVector - Returns a vector of specified type with all zero elements.
2812 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2813 assert(VT.isVector() && "Expected a vector type");
2815 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2816 // type. This ensures they get CSE'd.
2818 if (VT.getSizeInBits() == 64) { // MMX
2819 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2820 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2821 } else if (HasSSE2) { // SSE2
2822 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2823 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2825 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2826 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2828 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2831 /// getOnesVector - Returns a vector of specified type with all bits set.
2833 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2834 assert(VT.isVector() && "Expected a vector type");
2836 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2837 // type. This ensures they get CSE'd.
2838 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2840 if (VT.getSizeInBits() == 64) // MMX
2841 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2843 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2844 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2848 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2849 /// that point to V2 points to its first element.
2850 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2851 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2853 bool Changed = false;
2854 SmallVector<SDValue, 8> MaskVec;
2855 unsigned NumElems = Mask.getNumOperands();
2856 for (unsigned i = 0; i != NumElems; ++i) {
2857 SDValue Arg = Mask.getOperand(i);
2858 if (Arg.getOpcode() != ISD::UNDEF) {
2859 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2860 if (Val > NumElems) {
2861 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2865 MaskVec.push_back(Arg);
2869 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2870 &MaskVec[0], MaskVec.size());
2874 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2875 /// operation of specified width.
2876 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2877 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2878 MVT BaseVT = MaskVT.getVectorElementType();
2880 SmallVector<SDValue, 8> MaskVec;
2881 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2882 for (unsigned i = 1; i != NumElems; ++i)
2883 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2884 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2887 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2888 /// of specified width.
2889 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2890 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2891 MVT BaseVT = MaskVT.getVectorElementType();
2892 SmallVector<SDValue, 8> MaskVec;
2893 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2894 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2895 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2897 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2900 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2901 /// of specified width.
2902 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2903 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2904 MVT BaseVT = MaskVT.getVectorElementType();
2905 unsigned Half = NumElems/2;
2906 SmallVector<SDValue, 8> MaskVec;
2907 for (unsigned i = 0; i != Half; ++i) {
2908 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2909 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2911 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2914 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2915 /// element #0 of a vector with the specified index, leaving the rest of the
2916 /// elements in place.
2917 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2918 SelectionDAG &DAG) {
2919 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2920 MVT BaseVT = MaskVT.getVectorElementType();
2921 SmallVector<SDValue, 8> MaskVec;
2922 // Element #0 of the result gets the elt we are replacing.
2923 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2924 for (unsigned i = 1; i != NumElems; ++i)
2925 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2926 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2929 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2930 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2931 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2932 MVT VT = Op.getValueType();
2935 SDValue V1 = Op.getOperand(0);
2936 SDValue Mask = Op.getOperand(2);
2937 unsigned NumElems = Mask.getNumOperands();
2938 // Special handling of v4f32 -> v4i32.
2939 if (VT != MVT::v4f32) {
2940 Mask = getUnpacklMask(NumElems, DAG);
2941 while (NumElems > 4) {
2942 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2945 Mask = getZeroVector(MVT::v4i32, true, DAG);
2948 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2949 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2950 DAG.getNode(ISD::UNDEF, PVT), Mask);
2951 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2954 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2955 /// vector of zero or undef vector. This produces a shuffle where the low
2956 /// element of V2 is swizzled into the zero/undef vector, landing at element
2957 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2958 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
2959 bool isZero, bool HasSSE2,
2960 SelectionDAG &DAG) {
2961 MVT VT = V2.getValueType();
2963 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
2964 unsigned NumElems = V2.getValueType().getVectorNumElements();
2965 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2966 MVT EVT = MaskVT.getVectorElementType();
2967 SmallVector<SDValue, 16> MaskVec;
2968 for (unsigned i = 0; i != NumElems; ++i)
2969 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2970 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2972 MaskVec.push_back(DAG.getConstant(i, EVT));
2973 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2974 &MaskVec[0], MaskVec.size());
2975 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2978 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
2979 /// a shuffle that is zero.
2981 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
2982 unsigned NumElems, bool Low,
2983 SelectionDAG &DAG) {
2984 unsigned NumZeros = 0;
2985 for (unsigned i = 0; i < NumElems; ++i) {
2986 unsigned Index = Low ? i : NumElems-i-1;
2987 SDValue Idx = Mask.getOperand(Index);
2988 if (Idx.getOpcode() == ISD::UNDEF) {
2992 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
2993 if (Elt.getNode() && isZeroNode(Elt))
3001 /// isVectorShift - Returns true if the shuffle can be implemented as a
3002 /// logical left or right shift of a vector.
3003 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3004 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3005 unsigned NumElems = Mask.getNumOperands();
3008 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3011 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3016 bool SeenV1 = false;
3017 bool SeenV2 = false;
3018 for (unsigned i = NumZeros; i < NumElems; ++i) {
3019 unsigned Val = isLeft ? (i - NumZeros) : i;
3020 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3021 if (Idx.getOpcode() == ISD::UNDEF)
3023 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
3024 if (Index < NumElems)
3033 if (SeenV1 && SeenV2)
3036 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3042 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3044 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3045 unsigned NumNonZero, unsigned NumZero,
3046 SelectionDAG &DAG, TargetLowering &TLI) {
3052 for (unsigned i = 0; i < 16; ++i) {
3053 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3054 if (ThisIsNonZero && First) {
3056 V = getZeroVector(MVT::v8i16, true, DAG);
3058 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3063 SDValue ThisElt(0, 0), LastElt(0, 0);
3064 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3065 if (LastIsNonZero) {
3066 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3068 if (ThisIsNonZero) {
3069 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3070 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3071 ThisElt, DAG.getConstant(8, MVT::i8));
3073 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3077 if (ThisElt.getNode())
3078 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3079 DAG.getIntPtrConstant(i/2));
3083 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3086 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3088 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3089 unsigned NumNonZero, unsigned NumZero,
3090 SelectionDAG &DAG, TargetLowering &TLI) {
3096 for (unsigned i = 0; i < 8; ++i) {
3097 bool isNonZero = (NonZeros & (1 << i)) != 0;
3101 V = getZeroVector(MVT::v8i16, true, DAG);
3103 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3106 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3107 DAG.getIntPtrConstant(i));
3114 /// getVShift - Return a vector logical shift node.
3116 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3117 unsigned NumBits, SelectionDAG &DAG,
3118 const TargetLowering &TLI) {
3119 bool isMMX = VT.getSizeInBits() == 64;
3120 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3121 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3122 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3123 return DAG.getNode(ISD::BIT_CONVERT, VT,
3124 DAG.getNode(Opc, ShVT, SrcOp,
3125 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3129 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3130 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3131 if (ISD::isBuildVectorAllZeros(Op.getNode())
3132 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3133 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3134 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3135 // eliminated on x86-32 hosts.
3136 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3139 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3140 return getOnesVector(Op.getValueType(), DAG);
3141 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3144 MVT VT = Op.getValueType();
3145 MVT EVT = VT.getVectorElementType();
3146 unsigned EVTBits = EVT.getSizeInBits();
3148 unsigned NumElems = Op.getNumOperands();
3149 unsigned NumZero = 0;
3150 unsigned NumNonZero = 0;
3151 unsigned NonZeros = 0;
3152 bool IsAllConstants = true;
3153 SmallSet<SDValue, 8> Values;
3154 for (unsigned i = 0; i < NumElems; ++i) {
3155 SDValue Elt = Op.getOperand(i);
3156 if (Elt.getOpcode() == ISD::UNDEF)
3159 if (Elt.getOpcode() != ISD::Constant &&
3160 Elt.getOpcode() != ISD::ConstantFP)
3161 IsAllConstants = false;
3162 if (isZeroNode(Elt))
3165 NonZeros |= (1 << i);
3170 if (NumNonZero == 0) {
3171 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3172 return DAG.getNode(ISD::UNDEF, VT);
3175 // Special case for single non-zero, non-undef, element.
3176 if (NumNonZero == 1 && NumElems <= 4) {
3177 unsigned Idx = CountTrailingZeros_32(NonZeros);
3178 SDValue Item = Op.getOperand(Idx);
3180 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3181 // the value are obviously zero, truncate the value to i32 and do the
3182 // insertion that way. Only do this if the value is non-constant or if the
3183 // value is a constant being inserted into element 0. It is cheaper to do
3184 // a constant pool load than it is to do a movd + shuffle.
3185 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3186 (!IsAllConstants || Idx == 0)) {
3187 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3188 // Handle MMX and SSE both.
3189 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3190 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3192 // Truncate the value (which may itself be a constant) to i32, and
3193 // convert it to a vector with movd (S2V+shuffle to zero extend).
3194 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3195 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3196 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3197 Subtarget->hasSSE2(), DAG);
3199 // Now we have our 32-bit value zero extended in the low element of
3200 // a vector. If Idx != 0, swizzle it into place.
3203 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3204 getSwapEltZeroMask(VecElts, Idx, DAG)
3206 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3208 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3212 // If we have a constant or non-constant insertion into the low element of
3213 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3214 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3215 // depending on what the source datatype is. Because we can only get here
3216 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3218 // Don't do this for i64 values on x86-32.
3219 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3220 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3221 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3222 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3223 Subtarget->hasSSE2(), DAG);
3226 // Is it a vector logical left shift?
3227 if (NumElems == 2 && Idx == 1 &&
3228 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3229 unsigned NumBits = VT.getSizeInBits();
3230 return getVShift(true, VT,
3231 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3232 NumBits/2, DAG, *this);
3235 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3238 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3239 // is a non-constant being inserted into an element other than the low one,
3240 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3241 // movd/movss) to move this into the low element, then shuffle it into
3243 if (EVTBits == 32) {
3244 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3246 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3247 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3248 Subtarget->hasSSE2(), DAG);
3249 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3250 MVT MaskEVT = MaskVT.getVectorElementType();
3251 SmallVector<SDValue, 8> MaskVec;
3252 for (unsigned i = 0; i < NumElems; i++)
3253 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3254 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3255 &MaskVec[0], MaskVec.size());
3256 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3257 DAG.getNode(ISD::UNDEF, VT), Mask);
3261 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3262 if (Values.size() == 1)
3265 // A vector full of immediates; various special cases are already
3266 // handled, so this is best done with a single constant-pool load.
3270 // Let legalizer expand 2-wide build_vectors.
3271 if (EVTBits == 64) {
3272 if (NumNonZero == 1) {
3273 // One half is zero or undef.
3274 unsigned Idx = CountTrailingZeros_32(NonZeros);
3275 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3276 Op.getOperand(Idx));
3277 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3278 Subtarget->hasSSE2(), DAG);
3283 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3284 if (EVTBits == 8 && NumElems == 16) {
3285 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3287 if (V.getNode()) return V;
3290 if (EVTBits == 16 && NumElems == 8) {
3291 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3293 if (V.getNode()) return V;
3296 // If element VT is == 32 bits, turn it into a number of shuffles.
3297 SmallVector<SDValue, 8> V;
3299 if (NumElems == 4 && NumZero > 0) {
3300 for (unsigned i = 0; i < 4; ++i) {
3301 bool isZero = !(NonZeros & (1 << i));
3303 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3305 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3308 for (unsigned i = 0; i < 2; ++i) {
3309 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3312 V[i] = V[i*2]; // Must be a zero vector.
3315 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3316 getMOVLMask(NumElems, DAG));
3319 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3320 getMOVLMask(NumElems, DAG));
3323 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3324 getUnpacklMask(NumElems, DAG));
3329 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3330 MVT EVT = MaskVT.getVectorElementType();
3331 SmallVector<SDValue, 8> MaskVec;
3332 bool Reverse = (NonZeros & 0x3) == 2;
3333 for (unsigned i = 0; i < 2; ++i)
3335 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3337 MaskVec.push_back(DAG.getConstant(i, EVT));
3338 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3339 for (unsigned i = 0; i < 2; ++i)
3341 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3343 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3344 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3345 &MaskVec[0], MaskVec.size());
3346 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3349 if (Values.size() > 2) {
3350 // Expand into a number of unpckl*.
3352 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3353 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3354 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3355 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3356 for (unsigned i = 0; i < NumElems; ++i)
3357 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3359 while (NumElems != 0) {
3360 for (unsigned i = 0; i < NumElems; ++i)
3361 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3372 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3373 SDValue PermMask, SelectionDAG &DAG,
3374 TargetLowering &TLI) {
3376 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3377 MVT MaskEVT = MaskVT.getVectorElementType();
3378 MVT PtrVT = TLI.getPointerTy();
3379 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3380 PermMask.getNode()->op_end());
3382 // First record which half of which vector the low elements come from.
3383 SmallVector<unsigned, 4> LowQuad(4);
3384 for (unsigned i = 0; i < 4; ++i) {
3385 SDValue Elt = MaskElts[i];
3386 if (Elt.getOpcode() == ISD::UNDEF)
3388 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3389 int QuadIdx = EltIdx / 4;
3393 int BestLowQuad = -1;
3394 unsigned MaxQuad = 1;
3395 for (unsigned i = 0; i < 4; ++i) {
3396 if (LowQuad[i] > MaxQuad) {
3398 MaxQuad = LowQuad[i];
3402 // Record which half of which vector the high elements come from.
3403 SmallVector<unsigned, 4> HighQuad(4);
3404 for (unsigned i = 4; i < 8; ++i) {
3405 SDValue Elt = MaskElts[i];
3406 if (Elt.getOpcode() == ISD::UNDEF)
3408 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3409 int QuadIdx = EltIdx / 4;
3410 ++HighQuad[QuadIdx];
3413 int BestHighQuad = -1;
3415 for (unsigned i = 0; i < 4; ++i) {
3416 if (HighQuad[i] > MaxQuad) {
3418 MaxQuad = HighQuad[i];
3422 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3423 if (BestLowQuad != -1 || BestHighQuad != -1) {
3424 // First sort the 4 chunks in order using shufpd.
3425 SmallVector<SDValue, 8> MaskVec;
3427 if (BestLowQuad != -1)
3428 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3430 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3432 if (BestHighQuad != -1)
3433 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3435 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3437 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3438 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3439 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3440 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3441 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3443 // Now sort high and low parts separately.
3444 BitVector InOrder(8);
3445 if (BestLowQuad != -1) {
3446 // Sort lower half in order using PSHUFLW.
3448 bool AnyOutOrder = false;
3450 for (unsigned i = 0; i != 4; ++i) {
3451 SDValue Elt = MaskElts[i];
3452 if (Elt.getOpcode() == ISD::UNDEF) {
3453 MaskVec.push_back(Elt);
3456 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3460 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3462 // If this element is in the right place after this shuffle, then
3464 if ((int)(EltIdx / 4) == BestLowQuad)
3469 for (unsigned i = 4; i != 8; ++i)
3470 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3471 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3472 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3476 if (BestHighQuad != -1) {
3477 // Sort high half in order using PSHUFHW if possible.
3480 for (unsigned i = 0; i != 4; ++i)
3481 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3483 bool AnyOutOrder = false;
3484 for (unsigned i = 4; i != 8; ++i) {
3485 SDValue Elt = MaskElts[i];
3486 if (Elt.getOpcode() == ISD::UNDEF) {
3487 MaskVec.push_back(Elt);
3490 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3494 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3496 // If this element is in the right place after this shuffle, then
3498 if ((int)(EltIdx / 4) == BestHighQuad)
3504 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3505 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3509 // The other elements are put in the right place using pextrw and pinsrw.
3510 for (unsigned i = 0; i != 8; ++i) {
3513 SDValue Elt = MaskElts[i];
3514 if (Elt.getOpcode() == ISD::UNDEF)
3516 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3517 SDValue ExtOp = (EltIdx < 8)
3518 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3519 DAG.getConstant(EltIdx, PtrVT))
3520 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3521 DAG.getConstant(EltIdx - 8, PtrVT));
3522 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3523 DAG.getConstant(i, PtrVT));
3529 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3530 // few as possible. First, let's find out how many elements are already in the
3532 unsigned V1InOrder = 0;
3533 unsigned V1FromV1 = 0;
3534 unsigned V2InOrder = 0;
3535 unsigned V2FromV2 = 0;
3536 SmallVector<SDValue, 8> V1Elts;
3537 SmallVector<SDValue, 8> V2Elts;
3538 for (unsigned i = 0; i < 8; ++i) {
3539 SDValue Elt = MaskElts[i];
3540 if (Elt.getOpcode() == ISD::UNDEF) {
3541 V1Elts.push_back(Elt);
3542 V2Elts.push_back(Elt);
3547 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3549 V1Elts.push_back(Elt);
3550 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3552 } else if (EltIdx == i+8) {
3553 V1Elts.push_back(Elt);
3554 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3556 } else if (EltIdx < 8) {
3557 V1Elts.push_back(Elt);
3560 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3565 if (V2InOrder > V1InOrder) {
3566 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3568 std::swap(V1Elts, V2Elts);
3569 std::swap(V1FromV1, V2FromV2);
3572 if ((V1FromV1 + V1InOrder) != 8) {
3573 // Some elements are from V2.
3575 // If there are elements that are from V1 but out of place,
3576 // then first sort them in place
3577 SmallVector<SDValue, 8> MaskVec;
3578 for (unsigned i = 0; i < 8; ++i) {
3579 SDValue Elt = V1Elts[i];
3580 if (Elt.getOpcode() == ISD::UNDEF) {
3581 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3584 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3586 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3588 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3590 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3591 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3595 for (unsigned i = 0; i < 8; ++i) {
3596 SDValue Elt = V1Elts[i];
3597 if (Elt.getOpcode() == ISD::UNDEF)
3599 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3602 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3603 DAG.getConstant(EltIdx - 8, PtrVT));
3604 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3605 DAG.getConstant(i, PtrVT));
3609 // All elements are from V1.
3611 for (unsigned i = 0; i < 8; ++i) {
3612 SDValue Elt = V1Elts[i];
3613 if (Elt.getOpcode() == ISD::UNDEF)
3615 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3616 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3617 DAG.getConstant(EltIdx, PtrVT));
3618 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3619 DAG.getConstant(i, PtrVT));
3625 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3626 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3627 /// done when every pair / quad of shuffle mask elements point to elements in
3628 /// the right sequence. e.g.
3629 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3631 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3633 SDValue PermMask, SelectionDAG &DAG,
3634 TargetLowering &TLI) {
3635 unsigned NumElems = PermMask.getNumOperands();
3636 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3637 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3638 MVT MaskEltVT = MaskVT.getVectorElementType();
3640 switch (VT.getSimpleVT()) {
3641 default: assert(false && "Unexpected!");
3642 case MVT::v4f32: NewVT = MVT::v2f64; break;
3643 case MVT::v4i32: NewVT = MVT::v2i64; break;
3644 case MVT::v8i16: NewVT = MVT::v4i32; break;
3645 case MVT::v16i8: NewVT = MVT::v4i32; break;
3648 if (NewWidth == 2) {
3654 unsigned Scale = NumElems / NewWidth;
3655 SmallVector<SDValue, 8> MaskVec;
3656 for (unsigned i = 0; i < NumElems; i += Scale) {
3657 unsigned StartIdx = ~0U;
3658 for (unsigned j = 0; j < Scale; ++j) {
3659 SDValue Elt = PermMask.getOperand(i+j);
3660 if (Elt.getOpcode() == ISD::UNDEF)
3662 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3663 if (StartIdx == ~0U)
3664 StartIdx = EltIdx - (EltIdx % Scale);
3665 if (EltIdx != StartIdx + j)
3668 if (StartIdx == ~0U)
3669 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3671 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3674 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3675 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3676 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3677 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3678 &MaskVec[0], MaskVec.size()));
3681 /// getVZextMovL - Return a zero-extending vector move low node.
3683 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3684 SDValue SrcOp, SelectionDAG &DAG,
3685 const X86Subtarget *Subtarget) {
3686 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3687 LoadSDNode *LD = NULL;
3688 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3689 LD = dyn_cast<LoadSDNode>(SrcOp);
3691 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3693 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3694 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3695 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3696 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3697 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3699 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3700 return DAG.getNode(ISD::BIT_CONVERT, VT,
3701 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3702 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3709 return DAG.getNode(ISD::BIT_CONVERT, VT,
3710 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3711 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3714 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3717 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3718 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3719 MVT MaskVT = PermMask.getValueType();
3720 MVT MaskEVT = MaskVT.getVectorElementType();
3721 SmallVector<std::pair<int, int>, 8> Locs;
3723 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3726 for (unsigned i = 0; i != 4; ++i) {
3727 SDValue Elt = PermMask.getOperand(i);
3728 if (Elt.getOpcode() == ISD::UNDEF) {
3729 Locs[i] = std::make_pair(-1, -1);
3731 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3732 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3734 Locs[i] = std::make_pair(0, NumLo);
3738 Locs[i] = std::make_pair(1, NumHi);
3740 Mask1[2+NumHi] = Elt;
3746 if (NumLo <= 2 && NumHi <= 2) {
3747 // If no more than two elements come from either vector. This can be
3748 // implemented with two shuffles. First shuffle gather the elements.
3749 // The second shuffle, which takes the first shuffle as both of its
3750 // vector operands, put the elements into the right order.
3751 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3752 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3753 &Mask1[0], Mask1.size()));
3755 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3756 for (unsigned i = 0; i != 4; ++i) {
3757 if (Locs[i].first == -1)
3760 unsigned Idx = (i < 2) ? 0 : 4;
3761 Idx += Locs[i].first * 2 + Locs[i].second;
3762 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3766 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3767 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3768 &Mask2[0], Mask2.size()));
3769 } else if (NumLo == 3 || NumHi == 3) {
3770 // Otherwise, we must have three elements from one vector, call it X, and
3771 // one element from the other, call it Y. First, use a shufps to build an
3772 // intermediate vector with the one element from Y and the element from X
3773 // that will be in the same half in the final destination (the indexes don't
3774 // matter). Then, use a shufps to build the final vector, taking the half
3775 // containing the element from Y from the intermediate, and the other half
3778 // Normalize it so the 3 elements come from V1.
3779 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3783 // Find the element from V2.
3785 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3786 SDValue Elt = PermMask.getOperand(HiIndex);
3787 if (Elt.getOpcode() == ISD::UNDEF)
3789 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3794 Mask1[0] = PermMask.getOperand(HiIndex);
3795 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3796 Mask1[2] = PermMask.getOperand(HiIndex^1);
3797 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3798 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3799 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3802 Mask1[0] = PermMask.getOperand(0);
3803 Mask1[1] = PermMask.getOperand(1);
3804 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3805 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3806 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3807 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3809 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3810 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3811 Mask1[2] = PermMask.getOperand(2);
3812 Mask1[3] = PermMask.getOperand(3);
3813 if (Mask1[2].getOpcode() != ISD::UNDEF)
3814 Mask1[2] = DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getValue()+4,
3816 if (Mask1[3].getOpcode() != ISD::UNDEF)
3817 Mask1[3] = DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getValue()+4,
3819 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3820 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3824 // Break it into (shuffle shuffle_hi, shuffle_lo).
3826 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3827 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3828 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3829 unsigned MaskIdx = 0;
3832 for (unsigned i = 0; i != 4; ++i) {
3839 SDValue Elt = PermMask.getOperand(i);
3840 if (Elt.getOpcode() == ISD::UNDEF) {
3841 Locs[i] = std::make_pair(-1, -1);
3842 } else if (cast<ConstantSDNode>(Elt)->getValue() < 4) {
3843 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3844 (*MaskPtr)[LoIdx] = Elt;
3847 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3848 (*MaskPtr)[HiIdx] = Elt;
3853 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3854 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3855 &LoMask[0], LoMask.size()));
3856 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3857 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3858 &HiMask[0], HiMask.size()));
3859 SmallVector<SDValue, 8> MaskOps;
3860 for (unsigned i = 0; i != 4; ++i) {
3861 if (Locs[i].first == -1) {
3862 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3864 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3865 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3868 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3869 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3870 &MaskOps[0], MaskOps.size()));
3874 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3875 SDValue V1 = Op.getOperand(0);
3876 SDValue V2 = Op.getOperand(1);
3877 SDValue PermMask = Op.getOperand(2);
3878 MVT VT = Op.getValueType();
3879 unsigned NumElems = PermMask.getNumOperands();
3880 bool isMMX = VT.getSizeInBits() == 64;
3881 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3882 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3883 bool V1IsSplat = false;
3884 bool V2IsSplat = false;
3886 if (isUndefShuffle(Op.getNode()))
3887 return DAG.getNode(ISD::UNDEF, VT);
3889 if (isZeroShuffle(Op.getNode()))
3890 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3892 if (isIdentityMask(PermMask.getNode()))
3894 else if (isIdentityMask(PermMask.getNode(), true))
3897 if (isSplatMask(PermMask.getNode())) {
3898 if (isMMX || NumElems < 4) return Op;
3899 // Promote it to a v4{if}32 splat.
3900 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3903 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3905 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3906 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3907 if (NewOp.getNode())
3908 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3909 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3910 // FIXME: Figure out a cleaner way to do this.
3911 // Try to make use of movq to zero out the top part.
3912 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
3913 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3915 if (NewOp.getNode()) {
3916 SDValue NewV1 = NewOp.getOperand(0);
3917 SDValue NewV2 = NewOp.getOperand(1);
3918 SDValue NewMask = NewOp.getOperand(2);
3919 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
3920 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3921 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
3924 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
3925 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3927 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
3928 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
3933 // Check if this can be converted into a logical shift.
3934 bool isLeft = false;
3937 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
3938 if (isShift && ShVal.hasOneUse()) {
3939 // If the shifted value has multiple uses, it may be cheaper to use
3940 // v_set0 + movlhps or movhlps, etc.
3941 MVT EVT = VT.getVectorElementType();
3942 ShAmt *= EVT.getSizeInBits();
3943 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3946 if (X86::isMOVLMask(PermMask.getNode())) {
3949 if (ISD::isBuildVectorAllZeros(V1.getNode()))
3950 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
3955 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
3956 X86::isMOVSLDUPMask(PermMask.getNode()) ||
3957 X86::isMOVHLPSMask(PermMask.getNode()) ||
3958 X86::isMOVHPMask(PermMask.getNode()) ||
3959 X86::isMOVLPMask(PermMask.getNode())))
3962 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
3963 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
3964 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3967 // No better options. Use a vshl / vsrl.
3968 MVT EVT = VT.getVectorElementType();
3969 ShAmt *= EVT.getSizeInBits();
3970 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3973 bool Commuted = false;
3974 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3975 // 1,1,1,1 -> v8i16 though.
3976 V1IsSplat = isSplatVector(V1.getNode());
3977 V2IsSplat = isSplatVector(V2.getNode());
3979 // Canonicalize the splat or undef, if present, to be on the RHS.
3980 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3981 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3982 std::swap(V1IsSplat, V2IsSplat);
3983 std::swap(V1IsUndef, V2IsUndef);
3987 // FIXME: Figure out a cleaner way to do this.
3988 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
3989 if (V2IsUndef) return V1;
3990 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3992 // V2 is a splat, so the mask may be malformed. That is, it may point
3993 // to any V2 element. The instruction selectior won't like this. Get
3994 // a corrected mask and commute to form a proper MOVS{S|D}.
3995 SDValue NewMask = getMOVLMask(NumElems, DAG);
3996 if (NewMask.getNode() != PermMask.getNode())
3997 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4002 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4003 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4004 X86::isUNPCKLMask(PermMask.getNode()) ||
4005 X86::isUNPCKHMask(PermMask.getNode()))
4009 // Normalize mask so all entries that point to V2 points to its first
4010 // element then try to match unpck{h|l} again. If match, return a
4011 // new vector_shuffle with the corrected mask.
4012 SDValue NewMask = NormalizeMask(PermMask, DAG);
4013 if (NewMask.getNode() != PermMask.getNode()) {
4014 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4015 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4016 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4017 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4018 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4019 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4024 // Normalize the node to match x86 shuffle ops if needed
4025 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4026 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4029 // Commute is back and try unpck* again.
4030 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4031 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4032 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4033 X86::isUNPCKLMask(PermMask.getNode()) ||
4034 X86::isUNPCKHMask(PermMask.getNode()))
4038 // Try PSHUF* first, then SHUFP*.
4039 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4040 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4041 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4042 if (V2.getOpcode() != ISD::UNDEF)
4043 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4044 DAG.getNode(ISD::UNDEF, VT), PermMask);
4049 if (Subtarget->hasSSE2() &&
4050 (X86::isPSHUFDMask(PermMask.getNode()) ||
4051 X86::isPSHUFHWMask(PermMask.getNode()) ||
4052 X86::isPSHUFLWMask(PermMask.getNode()))) {
4054 if (VT == MVT::v4f32) {
4056 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4057 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4058 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4059 } else if (V2.getOpcode() != ISD::UNDEF)
4060 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4061 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4063 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4067 // Binary or unary shufps.
4068 if (X86::isSHUFPMask(PermMask.getNode()) ||
4069 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4073 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4074 if (VT == MVT::v8i16) {
4075 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4076 if (NewOp.getNode())
4080 // Handle all 4 wide cases with a number of shuffles except for MMX.
4081 if (NumElems == 4 && !isMMX)
4082 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4088 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4089 SelectionDAG &DAG) {
4090 MVT VT = Op.getValueType();
4091 if (VT.getSizeInBits() == 8) {
4092 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4093 Op.getOperand(0), Op.getOperand(1));
4094 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4095 DAG.getValueType(VT));
4096 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4097 } else if (VT.getSizeInBits() == 16) {
4098 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4099 Op.getOperand(0), Op.getOperand(1));
4100 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4101 DAG.getValueType(VT));
4102 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4103 } else if (VT == MVT::f32) {
4104 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4105 // the result back to FR32 register. It's only worth matching if the
4106 // result has a single use which is a store or a bitcast to i32.
4107 if (!Op.hasOneUse())
4109 SDNode *User = *Op.getNode()->use_begin();
4110 if (User->getOpcode() != ISD::STORE &&
4111 (User->getOpcode() != ISD::BIT_CONVERT ||
4112 User->getValueType(0) != MVT::i32))
4114 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4115 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4117 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4124 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4125 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4128 if (Subtarget->hasSSE41()) {
4129 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4134 MVT VT = Op.getValueType();
4135 // TODO: handle v16i8.
4136 if (VT.getSizeInBits() == 16) {
4137 SDValue Vec = Op.getOperand(0);
4138 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4140 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4141 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4142 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4144 // Transform it so it match pextrw which produces a 32-bit result.
4145 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4146 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4147 Op.getOperand(0), Op.getOperand(1));
4148 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4149 DAG.getValueType(VT));
4150 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4151 } else if (VT.getSizeInBits() == 32) {
4152 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4155 // SHUFPS the element to the lowest double word, then movss.
4156 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4157 SmallVector<SDValue, 8> IdxVec;
4159 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4161 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4163 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4165 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4166 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4167 &IdxVec[0], IdxVec.size());
4168 SDValue Vec = Op.getOperand(0);
4169 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4170 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4171 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4172 DAG.getIntPtrConstant(0));
4173 } else if (VT.getSizeInBits() == 64) {
4174 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4175 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4176 // to match extract_elt for f64.
4177 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4181 // UNPCKHPD the element to the lowest double word, then movsd.
4182 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4183 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4184 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4185 SmallVector<SDValue, 8> IdxVec;
4186 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4188 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4189 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4190 &IdxVec[0], IdxVec.size());
4191 SDValue Vec = Op.getOperand(0);
4192 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4193 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4194 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4195 DAG.getIntPtrConstant(0));
4202 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4203 MVT VT = Op.getValueType();
4204 MVT EVT = VT.getVectorElementType();
4206 SDValue N0 = Op.getOperand(0);
4207 SDValue N1 = Op.getOperand(1);
4208 SDValue N2 = Op.getOperand(2);
4210 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4211 isa<ConstantSDNode>(N2)) {
4212 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4214 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4216 if (N1.getValueType() != MVT::i32)
4217 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4218 if (N2.getValueType() != MVT::i32)
4219 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4220 return DAG.getNode(Opc, VT, N0, N1, N2);
4221 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4222 // Bits [7:6] of the constant are the source select. This will always be
4223 // zero here. The DAG Combiner may combine an extract_elt index into these
4224 // bits. For example (insert (extract, 3), 2) could be matched by putting
4225 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4226 // Bits [5:4] of the constant are the destination select. This is the
4227 // value of the incoming immediate.
4228 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4229 // combine either bitwise AND or insert of float 0.0 to set these bits.
4230 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
4231 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4237 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4238 MVT VT = Op.getValueType();
4239 MVT EVT = VT.getVectorElementType();
4241 if (Subtarget->hasSSE41())
4242 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4247 SDValue N0 = Op.getOperand(0);
4248 SDValue N1 = Op.getOperand(1);
4249 SDValue N2 = Op.getOperand(2);
4251 if (EVT.getSizeInBits() == 16) {
4252 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4253 // as its second argument.
4254 if (N1.getValueType() != MVT::i32)
4255 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4256 if (N2.getValueType() != MVT::i32)
4257 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4258 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4264 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4265 if (Op.getValueType() == MVT::v2f32)
4266 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4267 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4268 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4269 Op.getOperand(0))));
4271 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4272 MVT VT = MVT::v2i32;
4273 switch (Op.getValueType().getSimpleVT()) {
4280 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4281 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4284 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4285 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4286 // one of the above mentioned nodes. It has to be wrapped because otherwise
4287 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4288 // be used to form addressing mode. These wrapped nodes will be selected
4291 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4292 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4293 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4295 CP->getAlignment());
4296 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4297 // With PIC, the address is actually $g + Offset.
4298 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4299 !Subtarget->isPICStyleRIPRel()) {
4300 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4301 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4309 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4310 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4311 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
4312 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4313 // With PIC, the address is actually $g + Offset.
4314 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4315 !Subtarget->isPICStyleRIPRel()) {
4316 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4317 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4321 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4322 // load the value at address GV, not the value of GV itself. This means that
4323 // the GlobalAddress must be in the base or index register of the address, not
4324 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4325 // The same applies for external symbols during PIC codegen
4326 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
4327 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4328 PseudoSourceValue::getGOT(), 0);
4333 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4335 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4338 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4339 DAG.getNode(X86ISD::GlobalBaseReg,
4341 InFlag = Chain.getValue(1);
4343 // emit leal symbol@TLSGD(,%ebx,1), %eax
4344 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4345 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4346 GA->getValueType(0),
4348 SDValue Ops[] = { Chain, TGA, InFlag };
4349 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4350 InFlag = Result.getValue(2);
4351 Chain = Result.getValue(1);
4353 // call ___tls_get_addr. This function receives its argument in
4354 // the register EAX.
4355 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4356 InFlag = Chain.getValue(1);
4358 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4359 SDValue Ops1[] = { Chain,
4360 DAG.getTargetExternalSymbol("___tls_get_addr",
4362 DAG.getRegister(X86::EAX, PtrVT),
4363 DAG.getRegister(X86::EBX, PtrVT),
4365 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4366 InFlag = Chain.getValue(1);
4368 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4371 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4373 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4375 SDValue InFlag, Chain;
4377 // emit leaq symbol@TLSGD(%rip), %rdi
4378 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4379 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4380 GA->getValueType(0),
4382 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4383 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4384 Chain = Result.getValue(1);
4385 InFlag = Result.getValue(2);
4387 // call __tls_get_addr. This function receives its argument in
4388 // the register RDI.
4389 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4390 InFlag = Chain.getValue(1);
4392 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4393 SDValue Ops1[] = { Chain,
4394 DAG.getTargetExternalSymbol("__tls_get_addr",
4396 DAG.getRegister(X86::RDI, PtrVT),
4398 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4399 InFlag = Chain.getValue(1);
4401 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4404 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4405 // "local exec" model.
4406 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4408 // Get the Thread Pointer
4409 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4410 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4412 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4413 GA->getValueType(0),
4415 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4417 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4418 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4419 PseudoSourceValue::getGOT(), 0);
4421 // The address of the thread local variable is the add of the thread
4422 // pointer with the offset of the variable.
4423 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4427 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4428 // TODO: implement the "local dynamic" model
4429 // TODO: implement the "initial exec"model for pic executables
4430 assert(Subtarget->isTargetELF() &&
4431 "TLS not implemented for non-ELF targets");
4432 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4433 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4434 // otherwise use the "Local Exec"TLS Model
4435 if (Subtarget->is64Bit()) {
4436 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4438 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4439 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4441 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4446 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4447 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4448 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4449 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4450 // With PIC, the address is actually $g + Offset.
4451 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4452 !Subtarget->isPICStyleRIPRel()) {
4453 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4454 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4461 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4462 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4463 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4464 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4465 // With PIC, the address is actually $g + Offset.
4466 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4467 !Subtarget->isPICStyleRIPRel()) {
4468 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4469 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4476 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4477 /// take a 2 x i32 value to shift plus a shift amount.
4478 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4479 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4480 MVT VT = Op.getValueType();
4481 unsigned VTBits = VT.getSizeInBits();
4482 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4483 SDValue ShOpLo = Op.getOperand(0);
4484 SDValue ShOpHi = Op.getOperand(1);
4485 SDValue ShAmt = Op.getOperand(2);
4486 SDValue Tmp1 = isSRA ?
4487 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4488 DAG.getConstant(0, VT);
4491 if (Op.getOpcode() == ISD::SHL_PARTS) {
4492 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4493 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4495 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4496 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4499 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4500 DAG.getConstant(VTBits, MVT::i8));
4501 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4502 AndNode, DAG.getConstant(0, MVT::i8));
4505 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4506 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4507 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4509 if (Op.getOpcode() == ISD::SHL_PARTS) {
4510 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4511 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4513 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4514 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4517 SDValue Ops[2] = { Lo, Hi };
4518 return DAG.getMergeValues(Ops, 2);
4521 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4522 MVT SrcVT = Op.getOperand(0).getValueType();
4523 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4524 "Unknown SINT_TO_FP to lower!");
4526 // These are really Legal; caller falls through into that case.
4527 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4529 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4530 Subtarget->is64Bit())
4533 unsigned Size = SrcVT.getSizeInBits()/8;
4534 MachineFunction &MF = DAG.getMachineFunction();
4535 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4536 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4537 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4539 PseudoSourceValue::getFixedStack(SSFI), 0);
4543 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4545 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4547 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4548 SmallVector<SDValue, 8> Ops;
4549 Ops.push_back(Chain);
4550 Ops.push_back(StackSlot);
4551 Ops.push_back(DAG.getValueType(SrcVT));
4552 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4553 Tys, &Ops[0], Ops.size());
4556 Chain = Result.getValue(1);
4557 SDValue InFlag = Result.getValue(2);
4559 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4560 // shouldn't be necessary except that RFP cannot be live across
4561 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4562 MachineFunction &MF = DAG.getMachineFunction();
4563 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4564 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4565 Tys = DAG.getVTList(MVT::Other);
4566 SmallVector<SDValue, 8> Ops;
4567 Ops.push_back(Chain);
4568 Ops.push_back(Result);
4569 Ops.push_back(StackSlot);
4570 Ops.push_back(DAG.getValueType(Op.getValueType()));
4571 Ops.push_back(InFlag);
4572 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4573 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4574 PseudoSourceValue::getFixedStack(SSFI), 0);
4580 std::pair<SDValue,SDValue> X86TargetLowering::
4581 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4582 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4583 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4584 "Unknown FP_TO_SINT to lower!");
4586 // These are really Legal.
4587 if (Op.getValueType() == MVT::i32 &&
4588 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4589 return std::make_pair(SDValue(), SDValue());
4590 if (Subtarget->is64Bit() &&
4591 Op.getValueType() == MVT::i64 &&
4592 Op.getOperand(0).getValueType() != MVT::f80)
4593 return std::make_pair(SDValue(), SDValue());
4595 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4597 MachineFunction &MF = DAG.getMachineFunction();
4598 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4599 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4600 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4602 switch (Op.getValueType().getSimpleVT()) {
4603 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4604 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4605 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4606 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4609 SDValue Chain = DAG.getEntryNode();
4610 SDValue Value = Op.getOperand(0);
4611 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4612 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4613 Chain = DAG.getStore(Chain, Value, StackSlot,
4614 PseudoSourceValue::getFixedStack(SSFI), 0);
4615 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4617 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4619 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4620 Chain = Value.getValue(1);
4621 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4622 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4625 // Build the FP_TO_INT*_IN_MEM
4626 SDValue Ops[] = { Chain, Value, StackSlot };
4627 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4629 return std::make_pair(FIST, StackSlot);
4632 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4633 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4634 SDValue FIST = Vals.first, StackSlot = Vals.second;
4635 if (FIST.getNode() == 0) return SDValue();
4638 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4641 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4642 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
4643 SDValue FIST = Vals.first, StackSlot = Vals.second;
4644 if (FIST.getNode() == 0) return 0;
4646 MVT VT = N->getValueType(0);
4648 // Return a load from the stack slot.
4649 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
4651 // Use MERGE_VALUES to drop the chain result value and get a node with one
4652 // result. This requires turning off getMergeValues simplification, since
4653 // otherwise it will give us Res back.
4654 return DAG.getMergeValues(&Res, 1, false).getNode();
4657 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4658 MVT VT = Op.getValueType();
4661 EltVT = VT.getVectorElementType();
4662 std::vector<Constant*> CV;
4663 if (EltVT == MVT::f64) {
4664 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4668 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4674 Constant *C = ConstantVector::get(CV);
4675 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4676 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4677 PseudoSourceValue::getConstantPool(), 0,
4679 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4682 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4683 MVT VT = Op.getValueType();
4685 unsigned EltNum = 1;
4686 if (VT.isVector()) {
4687 EltVT = VT.getVectorElementType();
4688 EltNum = VT.getVectorNumElements();
4690 std::vector<Constant*> CV;
4691 if (EltVT == MVT::f64) {
4692 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4696 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4702 Constant *C = ConstantVector::get(CV);
4703 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4704 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4705 PseudoSourceValue::getConstantPool(), 0,
4707 if (VT.isVector()) {
4708 return DAG.getNode(ISD::BIT_CONVERT, VT,
4709 DAG.getNode(ISD::XOR, MVT::v2i64,
4710 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4711 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4713 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4717 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4718 SDValue Op0 = Op.getOperand(0);
4719 SDValue Op1 = Op.getOperand(1);
4720 MVT VT = Op.getValueType();
4721 MVT SrcVT = Op1.getValueType();
4723 // If second operand is smaller, extend it first.
4724 if (SrcVT.bitsLT(VT)) {
4725 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4728 // And if it is bigger, shrink it first.
4729 if (SrcVT.bitsGT(VT)) {
4730 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4734 // At this point the operands and the result should have the same
4735 // type, and that won't be f80 since that is not custom lowered.
4737 // First get the sign bit of second operand.
4738 std::vector<Constant*> CV;
4739 if (SrcVT == MVT::f64) {
4740 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4741 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4743 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4744 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4745 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4746 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4748 Constant *C = ConstantVector::get(CV);
4749 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4750 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4751 PseudoSourceValue::getConstantPool(), 0,
4753 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4755 // Shift sign bit right or left if the two operands have different types.
4756 if (SrcVT.bitsGT(VT)) {
4757 // Op0 is MVT::f32, Op1 is MVT::f64.
4758 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4759 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4760 DAG.getConstant(32, MVT::i32));
4761 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4762 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4763 DAG.getIntPtrConstant(0));
4766 // Clear first operand sign bit.
4768 if (VT == MVT::f64) {
4769 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4770 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4772 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4773 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4774 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4775 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4777 C = ConstantVector::get(CV);
4778 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4779 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4780 PseudoSourceValue::getConstantPool(), 0,
4782 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4784 // Or the value with the sign bit.
4785 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4788 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
4789 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4791 SDValue Op0 = Op.getOperand(0);
4792 SDValue Op1 = Op.getOperand(1);
4793 SDValue CC = Op.getOperand(2);
4794 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4795 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4798 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4800 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4801 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4802 DAG.getConstant(X86CC, MVT::i8), Cond);
4805 assert(isFP && "Illegal integer SetCC!");
4807 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4808 switch (SetCCOpcode) {
4809 default: assert(false && "Illegal floating point SetCC!");
4810 case ISD::SETOEQ: { // !PF & ZF
4811 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4812 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4813 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4814 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4815 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4817 case ISD::SETUNE: { // PF | !ZF
4818 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4819 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4820 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4821 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4822 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4827 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4829 SDValue Op0 = Op.getOperand(0);
4830 SDValue Op1 = Op.getOperand(1);
4831 SDValue CC = Op.getOperand(2);
4832 MVT VT = Op.getValueType();
4833 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4834 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4838 MVT VT0 = Op0.getValueType();
4839 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
4840 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
4843 switch (SetCCOpcode) {
4846 case ISD::SETEQ: SSECC = 0; break;
4848 case ISD::SETGT: Swap = true; // Fallthrough
4850 case ISD::SETOLT: SSECC = 1; break;
4852 case ISD::SETGE: Swap = true; // Fallthrough
4854 case ISD::SETOLE: SSECC = 2; break;
4855 case ISD::SETUO: SSECC = 3; break;
4857 case ISD::SETNE: SSECC = 4; break;
4858 case ISD::SETULE: Swap = true;
4859 case ISD::SETUGE: SSECC = 5; break;
4860 case ISD::SETULT: Swap = true;
4861 case ISD::SETUGT: SSECC = 6; break;
4862 case ISD::SETO: SSECC = 7; break;
4865 std::swap(Op0, Op1);
4867 // In the two special cases we can't handle, emit two comparisons.
4869 if (SetCCOpcode == ISD::SETUEQ) {
4871 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
4872 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
4873 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
4875 else if (SetCCOpcode == ISD::SETONE) {
4877 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
4878 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
4879 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
4881 assert(0 && "Illegal FP comparison");
4883 // Handle all other FP comparisons here.
4884 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
4887 // We are handling one of the integer comparisons here. Since SSE only has
4888 // GT and EQ comparisons for integer, swapping operands and multiple
4889 // operations may be required for some comparisons.
4890 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
4891 bool Swap = false, Invert = false, FlipSigns = false;
4893 switch (VT.getSimpleVT()) {
4895 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
4896 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
4897 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
4898 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
4901 switch (SetCCOpcode) {
4903 case ISD::SETNE: Invert = true;
4904 case ISD::SETEQ: Opc = EQOpc; break;
4905 case ISD::SETLT: Swap = true;
4906 case ISD::SETGT: Opc = GTOpc; break;
4907 case ISD::SETGE: Swap = true;
4908 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
4909 case ISD::SETULT: Swap = true;
4910 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
4911 case ISD::SETUGE: Swap = true;
4912 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
4915 std::swap(Op0, Op1);
4917 // Since SSE has no unsigned integer comparisons, we need to flip the sign
4918 // bits of the inputs before performing those operations.
4920 MVT EltVT = VT.getVectorElementType();
4921 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
4922 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
4923 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
4925 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
4926 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
4929 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
4931 // If the logical-not of the result is required, perform that now.
4933 MVT EltVT = VT.getVectorElementType();
4934 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
4935 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
4936 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
4938 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
4943 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
4944 bool addTest = true;
4945 SDValue Cond = Op.getOperand(0);
4948 if (Cond.getOpcode() == ISD::SETCC)
4949 Cond = LowerSETCC(Cond, DAG);
4951 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4952 // setting operand in place of the X86ISD::SETCC.
4953 if (Cond.getOpcode() == X86ISD::SETCC) {
4954 CC = Cond.getOperand(0);
4956 SDValue Cmp = Cond.getOperand(1);
4957 unsigned Opc = Cmp.getOpcode();
4958 MVT VT = Op.getValueType();
4960 bool IllegalFPCMov = false;
4961 if (VT.isFloatingPoint() && !VT.isVector() &&
4962 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4963 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4965 if ((Opc == X86ISD::CMP ||
4966 Opc == X86ISD::COMI ||
4967 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4974 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4975 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4978 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4980 SmallVector<SDValue, 4> Ops;
4981 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4982 // condition is true.
4983 Ops.push_back(Op.getOperand(2));
4984 Ops.push_back(Op.getOperand(1));
4986 Ops.push_back(Cond);
4987 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4990 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
4991 bool addTest = true;
4992 SDValue Chain = Op.getOperand(0);
4993 SDValue Cond = Op.getOperand(1);
4994 SDValue Dest = Op.getOperand(2);
4997 if (Cond.getOpcode() == ISD::SETCC)
4998 Cond = LowerSETCC(Cond, DAG);
5000 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5001 // setting operand in place of the X86ISD::SETCC.
5002 if (Cond.getOpcode() == X86ISD::SETCC) {
5003 CC = Cond.getOperand(0);
5005 SDValue Cmp = Cond.getOperand(1);
5006 unsigned Opc = Cmp.getOpcode();
5007 if (Opc == X86ISD::CMP ||
5008 Opc == X86ISD::COMI ||
5009 Opc == X86ISD::UCOMI) {
5016 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5017 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5019 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5020 Chain, Op.getOperand(2), CC, Cond);
5024 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5025 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5026 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5027 // that the guard pages used by the OS virtual memory manager are allocated in
5028 // correct sequence.
5030 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5031 SelectionDAG &DAG) {
5032 assert(Subtarget->isTargetCygMing() &&
5033 "This should be used only on Cygwin/Mingw targets");
5036 SDValue Chain = Op.getOperand(0);
5037 SDValue Size = Op.getOperand(1);
5038 // FIXME: Ensure alignment here
5042 MVT IntPtr = getPointerTy();
5043 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5045 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
5047 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5048 Flag = Chain.getValue(1);
5050 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5051 SDValue Ops[] = { Chain,
5052 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5053 DAG.getRegister(X86::EAX, IntPtr),
5054 DAG.getRegister(X86StackPtr, SPTy),
5056 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5057 Flag = Chain.getValue(1);
5059 Chain = DAG.getCALLSEQ_END(Chain,
5060 DAG.getIntPtrConstant(0),
5061 DAG.getIntPtrConstant(0),
5064 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5066 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5067 return DAG.getMergeValues(Ops1, 2);
5071 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5073 SDValue Dst, SDValue Src,
5074 SDValue Size, unsigned Align,
5075 const Value *DstSV, uint64_t DstSVOff) {
5076 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5078 /// If not DWORD aligned or size is more than the threshold, call the library.
5079 /// The libc version is likely to be faster for these cases. It can use the
5080 /// address value and run time information about the CPU.
5081 if ((Align & 3) != 0 ||
5083 ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
5084 SDValue InFlag(0, 0);
5086 // Check to see if there is a specialized entry-point for memory zeroing.
5087 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5088 if (const char *bzeroEntry =
5089 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5090 MVT IntPtr = getPointerTy();
5091 const Type *IntPtrTy = TD->getIntPtrType();
5092 TargetLowering::ArgListTy Args;
5093 TargetLowering::ArgListEntry Entry;
5095 Entry.Ty = IntPtrTy;
5096 Args.push_back(Entry);
5098 Args.push_back(Entry);
5099 std::pair<SDValue,SDValue> CallResult =
5100 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
5101 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
5103 return CallResult.second;
5106 // Otherwise have the target-independent code call memset.
5110 uint64_t SizeVal = ConstantSize->getValue();
5111 SDValue InFlag(0, 0);
5114 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5115 unsigned BytesLeft = 0;
5116 bool TwoRepStos = false;
5119 uint64_t Val = ValC->getValue() & 255;
5121 // If the value is a constant, then we can potentially use larger sets.
5122 switch (Align & 3) {
5123 case 2: // WORD aligned
5126 Val = (Val << 8) | Val;
5128 case 0: // DWORD aligned
5131 Val = (Val << 8) | Val;
5132 Val = (Val << 16) | Val;
5133 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5136 Val = (Val << 32) | Val;
5139 default: // Byte aligned
5142 Count = DAG.getIntPtrConstant(SizeVal);
5146 if (AVT.bitsGT(MVT::i8)) {
5147 unsigned UBytes = AVT.getSizeInBits() / 8;
5148 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5149 BytesLeft = SizeVal % UBytes;
5152 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5154 InFlag = Chain.getValue(1);
5157 Count = DAG.getIntPtrConstant(SizeVal);
5158 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5159 InFlag = Chain.getValue(1);
5162 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5164 InFlag = Chain.getValue(1);
5165 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5167 InFlag = Chain.getValue(1);
5169 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5170 SmallVector<SDValue, 8> Ops;
5171 Ops.push_back(Chain);
5172 Ops.push_back(DAG.getValueType(AVT));
5173 Ops.push_back(InFlag);
5174 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5177 InFlag = Chain.getValue(1);
5179 MVT CVT = Count.getValueType();
5180 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5181 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5182 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5184 InFlag = Chain.getValue(1);
5185 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5187 Ops.push_back(Chain);
5188 Ops.push_back(DAG.getValueType(MVT::i8));
5189 Ops.push_back(InFlag);
5190 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5191 } else if (BytesLeft) {
5192 // Handle the last 1 - 7 bytes.
5193 unsigned Offset = SizeVal - BytesLeft;
5194 MVT AddrVT = Dst.getValueType();
5195 MVT SizeVT = Size.getValueType();
5197 Chain = DAG.getMemset(Chain,
5198 DAG.getNode(ISD::ADD, AddrVT, Dst,
5199 DAG.getConstant(Offset, AddrVT)),
5201 DAG.getConstant(BytesLeft, SizeVT),
5202 Align, DstSV, DstSVOff + Offset);
5205 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5210 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5211 SDValue Chain, SDValue Dst, SDValue Src,
5212 SDValue Size, unsigned Align,
5214 const Value *DstSV, uint64_t DstSVOff,
5215 const Value *SrcSV, uint64_t SrcSVOff) {
5216 // This requires the copy size to be a constant, preferrably
5217 // within a subtarget-specific limit.
5218 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5221 uint64_t SizeVal = ConstantSize->getValue();
5222 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5225 /// If not DWORD aligned, call the library.
5226 if ((Align & 3) != 0)
5231 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5234 unsigned UBytes = AVT.getSizeInBits() / 8;
5235 unsigned CountVal = SizeVal / UBytes;
5236 SDValue Count = DAG.getIntPtrConstant(CountVal);
5237 unsigned BytesLeft = SizeVal % UBytes;
5239 SDValue InFlag(0, 0);
5240 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5242 InFlag = Chain.getValue(1);
5243 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5245 InFlag = Chain.getValue(1);
5246 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5248 InFlag = Chain.getValue(1);
5250 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5251 SmallVector<SDValue, 8> Ops;
5252 Ops.push_back(Chain);
5253 Ops.push_back(DAG.getValueType(AVT));
5254 Ops.push_back(InFlag);
5255 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5257 SmallVector<SDValue, 4> Results;
5258 Results.push_back(RepMovs);
5260 // Handle the last 1 - 7 bytes.
5261 unsigned Offset = SizeVal - BytesLeft;
5262 MVT DstVT = Dst.getValueType();
5263 MVT SrcVT = Src.getValueType();
5264 MVT SizeVT = Size.getValueType();
5265 Results.push_back(DAG.getMemcpy(Chain,
5266 DAG.getNode(ISD::ADD, DstVT, Dst,
5267 DAG.getConstant(Offset, DstVT)),
5268 DAG.getNode(ISD::ADD, SrcVT, Src,
5269 DAG.getConstant(Offset, SrcVT)),
5270 DAG.getConstant(BytesLeft, SizeVT),
5271 Align, AlwaysInline,
5272 DstSV, DstSVOff + Offset,
5273 SrcSV, SrcSVOff + Offset));
5276 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5279 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5280 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5281 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5282 SDValue TheChain = N->getOperand(0);
5283 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5284 if (Subtarget->is64Bit()) {
5285 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5286 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5287 MVT::i64, rax.getValue(2));
5288 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5289 DAG.getConstant(32, MVT::i8));
5291 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5294 return DAG.getMergeValues(Ops, 2).getNode();
5297 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5298 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5299 MVT::i32, eax.getValue(2));
5300 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5301 SDValue Ops[] = { eax, edx };
5302 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5304 // Use a MERGE_VALUES to return the value and chain.
5305 Ops[1] = edx.getValue(1);
5306 return DAG.getMergeValues(Ops, 2).getNode();
5309 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5310 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5312 if (!Subtarget->is64Bit()) {
5313 // vastart just stores the address of the VarArgsFrameIndex slot into the
5314 // memory location argument.
5315 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5316 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5320 // gp_offset (0 - 6 * 8)
5321 // fp_offset (48 - 48 + 8 * 16)
5322 // overflow_arg_area (point to parameters coming in memory).
5324 SmallVector<SDValue, 8> MemOps;
5325 SDValue FIN = Op.getOperand(1);
5327 SDValue Store = DAG.getStore(Op.getOperand(0),
5328 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5330 MemOps.push_back(Store);
5333 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5334 Store = DAG.getStore(Op.getOperand(0),
5335 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5337 MemOps.push_back(Store);
5339 // Store ptr to overflow_arg_area
5340 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5341 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5342 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5343 MemOps.push_back(Store);
5345 // Store ptr to reg_save_area.
5346 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5347 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5348 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5349 MemOps.push_back(Store);
5350 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5353 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5354 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5355 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5356 SDValue Chain = Op.getOperand(0);
5357 SDValue SrcPtr = Op.getOperand(1);
5358 SDValue SrcSV = Op.getOperand(2);
5360 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5365 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5366 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5367 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5368 SDValue Chain = Op.getOperand(0);
5369 SDValue DstPtr = Op.getOperand(1);
5370 SDValue SrcPtr = Op.getOperand(2);
5371 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5372 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5374 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5375 DAG.getIntPtrConstant(24), 8, false,
5376 DstSV, 0, SrcSV, 0);
5380 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5381 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
5383 default: return SDValue(); // Don't custom lower most intrinsics.
5384 // Comparison intrinsics.
5385 case Intrinsic::x86_sse_comieq_ss:
5386 case Intrinsic::x86_sse_comilt_ss:
5387 case Intrinsic::x86_sse_comile_ss:
5388 case Intrinsic::x86_sse_comigt_ss:
5389 case Intrinsic::x86_sse_comige_ss:
5390 case Intrinsic::x86_sse_comineq_ss:
5391 case Intrinsic::x86_sse_ucomieq_ss:
5392 case Intrinsic::x86_sse_ucomilt_ss:
5393 case Intrinsic::x86_sse_ucomile_ss:
5394 case Intrinsic::x86_sse_ucomigt_ss:
5395 case Intrinsic::x86_sse_ucomige_ss:
5396 case Intrinsic::x86_sse_ucomineq_ss:
5397 case Intrinsic::x86_sse2_comieq_sd:
5398 case Intrinsic::x86_sse2_comilt_sd:
5399 case Intrinsic::x86_sse2_comile_sd:
5400 case Intrinsic::x86_sse2_comigt_sd:
5401 case Intrinsic::x86_sse2_comige_sd:
5402 case Intrinsic::x86_sse2_comineq_sd:
5403 case Intrinsic::x86_sse2_ucomieq_sd:
5404 case Intrinsic::x86_sse2_ucomilt_sd:
5405 case Intrinsic::x86_sse2_ucomile_sd:
5406 case Intrinsic::x86_sse2_ucomigt_sd:
5407 case Intrinsic::x86_sse2_ucomige_sd:
5408 case Intrinsic::x86_sse2_ucomineq_sd: {
5410 ISD::CondCode CC = ISD::SETCC_INVALID;
5413 case Intrinsic::x86_sse_comieq_ss:
5414 case Intrinsic::x86_sse2_comieq_sd:
5418 case Intrinsic::x86_sse_comilt_ss:
5419 case Intrinsic::x86_sse2_comilt_sd:
5423 case Intrinsic::x86_sse_comile_ss:
5424 case Intrinsic::x86_sse2_comile_sd:
5428 case Intrinsic::x86_sse_comigt_ss:
5429 case Intrinsic::x86_sse2_comigt_sd:
5433 case Intrinsic::x86_sse_comige_ss:
5434 case Intrinsic::x86_sse2_comige_sd:
5438 case Intrinsic::x86_sse_comineq_ss:
5439 case Intrinsic::x86_sse2_comineq_sd:
5443 case Intrinsic::x86_sse_ucomieq_ss:
5444 case Intrinsic::x86_sse2_ucomieq_sd:
5445 Opc = X86ISD::UCOMI;
5448 case Intrinsic::x86_sse_ucomilt_ss:
5449 case Intrinsic::x86_sse2_ucomilt_sd:
5450 Opc = X86ISD::UCOMI;
5453 case Intrinsic::x86_sse_ucomile_ss:
5454 case Intrinsic::x86_sse2_ucomile_sd:
5455 Opc = X86ISD::UCOMI;
5458 case Intrinsic::x86_sse_ucomigt_ss:
5459 case Intrinsic::x86_sse2_ucomigt_sd:
5460 Opc = X86ISD::UCOMI;
5463 case Intrinsic::x86_sse_ucomige_ss:
5464 case Intrinsic::x86_sse2_ucomige_sd:
5465 Opc = X86ISD::UCOMI;
5468 case Intrinsic::x86_sse_ucomineq_ss:
5469 case Intrinsic::x86_sse2_ucomineq_sd:
5470 Opc = X86ISD::UCOMI;
5476 SDValue LHS = Op.getOperand(1);
5477 SDValue RHS = Op.getOperand(2);
5478 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5480 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5481 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5482 DAG.getConstant(X86CC, MVT::i8), Cond);
5483 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5486 // Fix vector shift instructions where the last operand is a non-immediate
5488 case Intrinsic::x86_sse2_pslli_w:
5489 case Intrinsic::x86_sse2_pslli_d:
5490 case Intrinsic::x86_sse2_pslli_q:
5491 case Intrinsic::x86_sse2_psrli_w:
5492 case Intrinsic::x86_sse2_psrli_d:
5493 case Intrinsic::x86_sse2_psrli_q:
5494 case Intrinsic::x86_sse2_psrai_w:
5495 case Intrinsic::x86_sse2_psrai_d:
5496 case Intrinsic::x86_mmx_pslli_w:
5497 case Intrinsic::x86_mmx_pslli_d:
5498 case Intrinsic::x86_mmx_pslli_q:
5499 case Intrinsic::x86_mmx_psrli_w:
5500 case Intrinsic::x86_mmx_psrli_d:
5501 case Intrinsic::x86_mmx_psrli_q:
5502 case Intrinsic::x86_mmx_psrai_w:
5503 case Intrinsic::x86_mmx_psrai_d: {
5504 SDValue ShAmt = Op.getOperand(2);
5505 if (isa<ConstantSDNode>(ShAmt))
5508 unsigned NewIntNo = 0;
5509 MVT ShAmtVT = MVT::v4i32;
5511 case Intrinsic::x86_sse2_pslli_w:
5512 NewIntNo = Intrinsic::x86_sse2_psll_w;
5514 case Intrinsic::x86_sse2_pslli_d:
5515 NewIntNo = Intrinsic::x86_sse2_psll_d;
5517 case Intrinsic::x86_sse2_pslli_q:
5518 NewIntNo = Intrinsic::x86_sse2_psll_q;
5520 case Intrinsic::x86_sse2_psrli_w:
5521 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5523 case Intrinsic::x86_sse2_psrli_d:
5524 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5526 case Intrinsic::x86_sse2_psrli_q:
5527 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5529 case Intrinsic::x86_sse2_psrai_w:
5530 NewIntNo = Intrinsic::x86_sse2_psra_w;
5532 case Intrinsic::x86_sse2_psrai_d:
5533 NewIntNo = Intrinsic::x86_sse2_psra_d;
5536 ShAmtVT = MVT::v2i32;
5538 case Intrinsic::x86_mmx_pslli_w:
5539 NewIntNo = Intrinsic::x86_mmx_psll_w;
5541 case Intrinsic::x86_mmx_pslli_d:
5542 NewIntNo = Intrinsic::x86_mmx_psll_d;
5544 case Intrinsic::x86_mmx_pslli_q:
5545 NewIntNo = Intrinsic::x86_mmx_psll_q;
5547 case Intrinsic::x86_mmx_psrli_w:
5548 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5550 case Intrinsic::x86_mmx_psrli_d:
5551 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5553 case Intrinsic::x86_mmx_psrli_q:
5554 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5556 case Intrinsic::x86_mmx_psrai_w:
5557 NewIntNo = Intrinsic::x86_mmx_psra_w;
5559 case Intrinsic::x86_mmx_psrai_d:
5560 NewIntNo = Intrinsic::x86_mmx_psra_d;
5562 default: abort(); // Can't reach here.
5567 MVT VT = Op.getValueType();
5568 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5569 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5570 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5571 DAG.getConstant(NewIntNo, MVT::i32),
5572 Op.getOperand(1), ShAmt);
5577 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5578 // Depths > 0 not supported yet!
5579 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5582 // Just load the return address
5583 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5584 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5587 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5588 // Depths > 0 not supported yet!
5589 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5592 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5593 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5594 DAG.getIntPtrConstant(TD->getPointerSize()));
5597 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5598 SelectionDAG &DAG) {
5599 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5602 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5604 MachineFunction &MF = DAG.getMachineFunction();
5605 SDValue Chain = Op.getOperand(0);
5606 SDValue Offset = Op.getOperand(1);
5607 SDValue Handler = Op.getOperand(2);
5609 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5611 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
5613 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5614 DAG.getIntPtrConstant(-TD->getPointerSize()));
5615 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5616 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5617 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5618 MF.getRegInfo().addLiveOut(StoreAddrReg);
5620 return DAG.getNode(X86ISD::EH_RETURN,
5622 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
5625 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5626 SelectionDAG &DAG) {
5627 SDValue Root = Op.getOperand(0);
5628 SDValue Trmp = Op.getOperand(1); // trampoline
5629 SDValue FPtr = Op.getOperand(2); // nested function
5630 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5632 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5634 const X86InstrInfo *TII =
5635 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5637 if (Subtarget->is64Bit()) {
5638 SDValue OutChains[6];
5640 // Large code-model.
5642 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5643 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5645 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5646 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5648 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5650 // Load the pointer to the nested function into R11.
5651 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5652 SDValue Addr = Trmp;
5653 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5656 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5657 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5659 // Load the 'nest' parameter value into R10.
5660 // R10 is specified in X86CallingConv.td
5661 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5662 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5663 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5666 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5667 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5669 // Jump to the nested function.
5670 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5671 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5672 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5675 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5676 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5677 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5681 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5682 return DAG.getMergeValues(Ops, 2);
5684 const Function *Func =
5685 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5686 unsigned CC = Func->getCallingConv();
5691 assert(0 && "Unsupported calling convention");
5692 case CallingConv::C:
5693 case CallingConv::X86_StdCall: {
5694 // Pass 'nest' parameter in ECX.
5695 // Must be kept in sync with X86CallingConv.td
5698 // Check that ECX wasn't needed by an 'inreg' parameter.
5699 const FunctionType *FTy = Func->getFunctionType();
5700 const PAListPtr &Attrs = Func->getParamAttrs();
5702 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5703 unsigned InRegCount = 0;
5706 for (FunctionType::param_iterator I = FTy->param_begin(),
5707 E = FTy->param_end(); I != E; ++I, ++Idx)
5708 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5709 // FIXME: should only count parameters that are lowered to integers.
5710 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
5712 if (InRegCount > 2) {
5713 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5719 case CallingConv::X86_FastCall:
5720 case CallingConv::Fast:
5721 // Pass 'nest' parameter in EAX.
5722 // Must be kept in sync with X86CallingConv.td
5727 SDValue OutChains[4];
5730 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5731 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5733 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5734 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5735 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5738 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5739 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5741 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5742 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5743 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5744 TrmpAddr, 5, false, 1);
5746 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5747 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5750 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5751 return DAG.getMergeValues(Ops, 2);
5755 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
5757 The rounding mode is in bits 11:10 of FPSR, and has the following
5764 FLT_ROUNDS, on the other hand, expects the following:
5771 To perform the conversion, we do:
5772 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5775 MachineFunction &MF = DAG.getMachineFunction();
5776 const TargetMachine &TM = MF.getTarget();
5777 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5778 unsigned StackAlignment = TFI.getStackAlignment();
5779 MVT VT = Op.getValueType();
5781 // Save FP Control Word to stack slot
5782 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5783 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5785 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5786 DAG.getEntryNode(), StackSlot);
5788 // Load FP Control Word from stack slot
5789 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5791 // Transform as necessary
5793 DAG.getNode(ISD::SRL, MVT::i16,
5794 DAG.getNode(ISD::AND, MVT::i16,
5795 CWD, DAG.getConstant(0x800, MVT::i16)),
5796 DAG.getConstant(11, MVT::i8));
5798 DAG.getNode(ISD::SRL, MVT::i16,
5799 DAG.getNode(ISD::AND, MVT::i16,
5800 CWD, DAG.getConstant(0x400, MVT::i16)),
5801 DAG.getConstant(9, MVT::i8));
5804 DAG.getNode(ISD::AND, MVT::i16,
5805 DAG.getNode(ISD::ADD, MVT::i16,
5806 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5807 DAG.getConstant(1, MVT::i16)),
5808 DAG.getConstant(3, MVT::i16));
5811 return DAG.getNode((VT.getSizeInBits() < 16 ?
5812 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5815 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
5816 MVT VT = Op.getValueType();
5818 unsigned NumBits = VT.getSizeInBits();
5820 Op = Op.getOperand(0);
5821 if (VT == MVT::i8) {
5822 // Zero extend to i32 since there is not an i8 bsr.
5824 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5827 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5828 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5829 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5831 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5832 SmallVector<SDValue, 4> Ops;
5834 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5835 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5836 Ops.push_back(Op.getValue(1));
5837 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5839 // Finally xor with NumBits-1.
5840 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5843 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5847 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
5848 MVT VT = Op.getValueType();
5850 unsigned NumBits = VT.getSizeInBits();
5852 Op = Op.getOperand(0);
5853 if (VT == MVT::i8) {
5855 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5858 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5859 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5860 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5862 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5863 SmallVector<SDValue, 4> Ops;
5865 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5866 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5867 Ops.push_back(Op.getValue(1));
5868 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5871 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5875 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
5876 MVT T = Op.getValueType();
5879 switch(T.getSimpleVT()) {
5881 assert(false && "Invalid value type!");
5882 case MVT::i8: Reg = X86::AL; size = 1; break;
5883 case MVT::i16: Reg = X86::AX; size = 2; break;
5884 case MVT::i32: Reg = X86::EAX; size = 4; break;
5886 if (Subtarget->is64Bit()) {
5887 Reg = X86::RAX; size = 8;
5888 } else //Should go away when LowerType stuff lands
5889 return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
5892 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5893 Op.getOperand(3), SDValue());
5894 SDValue Ops[] = { cpIn.getValue(0),
5897 DAG.getTargetConstant(size, MVT::i8),
5899 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5900 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5902 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5906 SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
5907 SelectionDAG &DAG) {
5908 MVT T = Op->getValueType(0);
5909 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
5910 SDValue cpInL, cpInH;
5911 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5912 DAG.getConstant(0, MVT::i32));
5913 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5914 DAG.getConstant(1, MVT::i32));
5915 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5917 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5918 cpInH, cpInL.getValue(1));
5919 SDValue swapInL, swapInH;
5920 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5921 DAG.getConstant(0, MVT::i32));
5922 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5923 DAG.getConstant(1, MVT::i32));
5924 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5925 swapInL, cpInH.getValue(1));
5926 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5927 swapInH, swapInL.getValue(1));
5928 SDValue Ops[] = { swapInH.getValue(0),
5930 swapInH.getValue(1)};
5931 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5932 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5933 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5934 Result.getValue(1));
5935 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5936 cpOutL.getValue(2));
5937 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5938 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5939 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
5940 return DAG.getMergeValues(Vals, 2).getNode();
5943 SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,
5944 SelectionDAG &DAG) {
5945 MVT T = Op->getValueType(0);
5946 SDValue negOp = DAG.getNode(ISD::SUB, T,
5947 DAG.getConstant(0, T), Op->getOperand(2));
5948 return DAG.getAtomic((T==MVT::i8 ? ISD::ATOMIC_LOAD_ADD_8:
5949 T==MVT::i16 ? ISD::ATOMIC_LOAD_ADD_16:
5950 T==MVT::i32 ? ISD::ATOMIC_LOAD_ADD_32:
5951 T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
5952 Op->getOperand(0), Op->getOperand(1), negOp,
5953 cast<AtomicSDNode>(Op)->getSrcValue(),
5954 cast<AtomicSDNode>(Op)->getAlignment()).getNode();
5957 /// LowerOperation - Provide custom lowering hooks for some operations.
5959 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5960 switch (Op.getOpcode()) {
5961 default: assert(0 && "Should not custom lower this!");
5962 case ISD::ATOMIC_CMP_SWAP_8: return LowerCMP_SWAP(Op,DAG);
5963 case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
5964 case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
5965 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
5966 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5967 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5968 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5969 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5970 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5971 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5972 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5973 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5974 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5975 case ISD::SHL_PARTS:
5976 case ISD::SRA_PARTS:
5977 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5978 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5979 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5980 case ISD::FABS: return LowerFABS(Op, DAG);
5981 case ISD::FNEG: return LowerFNEG(Op, DAG);
5982 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5983 case ISD::SETCC: return LowerSETCC(Op, DAG);
5984 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
5985 case ISD::SELECT: return LowerSELECT(Op, DAG);
5986 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5987 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5988 case ISD::CALL: return LowerCALL(Op, DAG);
5989 case ISD::RET: return LowerRET(Op, DAG);
5990 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5991 case ISD::VASTART: return LowerVASTART(Op, DAG);
5992 case ISD::VAARG: return LowerVAARG(Op, DAG);
5993 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5994 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5995 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5996 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5997 case ISD::FRAME_TO_ARGS_OFFSET:
5998 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5999 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6000 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6001 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6002 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6003 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6004 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6006 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
6007 case ISD::READCYCLECOUNTER:
6008 return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
6012 /// ReplaceNodeResults - Replace a node with an illegal result type
6013 /// with a new node built out of custom code.
6014 SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
6015 switch (N->getOpcode()) {
6016 default: assert(0 && "Should not custom lower this!");
6017 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
6018 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
6019 case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
6020 case ISD::ATOMIC_LOAD_SUB_8: return ExpandATOMIC_LOAD_SUB(N,DAG);
6021 case ISD::ATOMIC_LOAD_SUB_16: return ExpandATOMIC_LOAD_SUB(N,DAG);
6022 case ISD::ATOMIC_LOAD_SUB_32: return ExpandATOMIC_LOAD_SUB(N,DAG);
6023 case ISD::ATOMIC_LOAD_SUB_64: return ExpandATOMIC_LOAD_SUB(N,DAG);
6027 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6029 default: return NULL;
6030 case X86ISD::BSF: return "X86ISD::BSF";
6031 case X86ISD::BSR: return "X86ISD::BSR";
6032 case X86ISD::SHLD: return "X86ISD::SHLD";
6033 case X86ISD::SHRD: return "X86ISD::SHRD";
6034 case X86ISD::FAND: return "X86ISD::FAND";
6035 case X86ISD::FOR: return "X86ISD::FOR";
6036 case X86ISD::FXOR: return "X86ISD::FXOR";
6037 case X86ISD::FSRL: return "X86ISD::FSRL";
6038 case X86ISD::FILD: return "X86ISD::FILD";
6039 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6040 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6041 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6042 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6043 case X86ISD::FLD: return "X86ISD::FLD";
6044 case X86ISD::FST: return "X86ISD::FST";
6045 case X86ISD::CALL: return "X86ISD::CALL";
6046 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6047 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6048 case X86ISD::CMP: return "X86ISD::CMP";
6049 case X86ISD::COMI: return "X86ISD::COMI";
6050 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6051 case X86ISD::SETCC: return "X86ISD::SETCC";
6052 case X86ISD::CMOV: return "X86ISD::CMOV";
6053 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6054 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6055 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6056 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6057 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6058 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6059 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6060 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6061 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6062 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6063 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6064 case X86ISD::FMAX: return "X86ISD::FMAX";
6065 case X86ISD::FMIN: return "X86ISD::FMIN";
6066 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6067 case X86ISD::FRCP: return "X86ISD::FRCP";
6068 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6069 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6070 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6071 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6072 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6073 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6074 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6075 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6076 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6077 case X86ISD::VSHL: return "X86ISD::VSHL";
6078 case X86ISD::VSRL: return "X86ISD::VSRL";
6079 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6080 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6081 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6082 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6083 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6084 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6085 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6086 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6087 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6088 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6092 // isLegalAddressingMode - Return true if the addressing mode represented
6093 // by AM is legal for this target, for a load/store of the specified type.
6094 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6095 const Type *Ty) const {
6096 // X86 supports extremely general addressing modes.
6098 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6099 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6103 // We can only fold this if we don't need an extra load.
6104 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6107 // X86-64 only supports addr of globals in small code model.
6108 if (Subtarget->is64Bit()) {
6109 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6111 // If lower 4G is not available, then we must use rip-relative addressing.
6112 if (AM.BaseOffs || AM.Scale > 1)
6123 // These scales always work.
6128 // These scales are formed with basereg+scalereg. Only accept if there is
6133 default: // Other stuff never works.
6141 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6142 if (!Ty1->isInteger() || !Ty2->isInteger())
6144 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6145 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6146 if (NumBits1 <= NumBits2)
6148 return Subtarget->is64Bit() || NumBits1 < 64;
6151 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6152 if (!VT1.isInteger() || !VT2.isInteger())
6154 unsigned NumBits1 = VT1.getSizeInBits();
6155 unsigned NumBits2 = VT2.getSizeInBits();
6156 if (NumBits1 <= NumBits2)
6158 return Subtarget->is64Bit() || NumBits1 < 64;
6161 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6162 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6163 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6164 /// are assumed to be legal.
6166 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6167 // Only do shuffles on 128-bit vector types for now.
6168 if (VT.getSizeInBits() == 64) return false;
6169 return (Mask.getNode()->getNumOperands() <= 4 ||
6170 isIdentityMask(Mask.getNode()) ||
6171 isIdentityMask(Mask.getNode(), true) ||
6172 isSplatMask(Mask.getNode()) ||
6173 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6174 X86::isUNPCKLMask(Mask.getNode()) ||
6175 X86::isUNPCKHMask(Mask.getNode()) ||
6176 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6177 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6181 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6182 MVT EVT, SelectionDAG &DAG) const {
6183 unsigned NumElts = BVOps.size();
6184 // Only do shuffles on 128-bit vector types for now.
6185 if (EVT.getSizeInBits() * NumElts == 64) return false;
6186 if (NumElts == 2) return true;
6188 return (isMOVLMask(&BVOps[0], 4) ||
6189 isCommutedMOVL(&BVOps[0], 4, true) ||
6190 isSHUFPMask(&BVOps[0], 4) ||
6191 isCommutedSHUFP(&BVOps[0], 4));
6196 //===----------------------------------------------------------------------===//
6197 // X86 Scheduler Hooks
6198 //===----------------------------------------------------------------------===//
6200 // private utility function
6202 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6203 MachineBasicBlock *MBB,
6211 TargetRegisterClass *RC,
6213 // For the atomic bitwise operator, we generate
6216 // ld t1 = [bitinstr.addr]
6217 // op t2 = t1, [bitinstr.val]
6219 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6221 // fallthrough -->nextMBB
6222 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6223 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6224 MachineFunction::iterator MBBIter = MBB;
6227 /// First build the CFG
6228 MachineFunction *F = MBB->getParent();
6229 MachineBasicBlock *thisMBB = MBB;
6230 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6231 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6232 F->insert(MBBIter, newMBB);
6233 F->insert(MBBIter, nextMBB);
6235 // Move all successors to thisMBB to nextMBB
6236 nextMBB->transferSuccessors(thisMBB);
6238 // Update thisMBB to fall through to newMBB
6239 thisMBB->addSuccessor(newMBB);
6241 // newMBB jumps to itself and fall through to nextMBB
6242 newMBB->addSuccessor(nextMBB);
6243 newMBB->addSuccessor(newMBB);
6245 // Insert instructions into newMBB based on incoming instruction
6246 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6247 MachineOperand& destOper = bInstr->getOperand(0);
6248 MachineOperand* argOpers[6];
6249 int numArgs = bInstr->getNumOperands() - 1;
6250 for (int i=0; i < numArgs; ++i)
6251 argOpers[i] = &bInstr->getOperand(i+1);
6253 // x86 address has 4 operands: base, index, scale, and displacement
6254 int lastAddrIndx = 3; // [0,3]
6257 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6258 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6259 for (int i=0; i <= lastAddrIndx; ++i)
6260 (*MIB).addOperand(*argOpers[i]);
6262 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6264 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6269 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6270 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6271 && "invalid operand");
6272 if (argOpers[valArgIndx]->isReg())
6273 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6275 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6277 (*MIB).addOperand(*argOpers[valArgIndx]);
6279 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6282 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6283 for (int i=0; i <= lastAddrIndx; ++i)
6284 (*MIB).addOperand(*argOpers[i]);
6286 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6287 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6289 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6293 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6295 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6299 // private utility function
6301 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6302 MachineBasicBlock *MBB,
6304 // For the atomic min/max operator, we generate
6307 // ld t1 = [min/max.addr]
6308 // mov t2 = [min/max.val]
6310 // cmov[cond] t2 = t1
6312 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6314 // fallthrough -->nextMBB
6316 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6317 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6318 MachineFunction::iterator MBBIter = MBB;
6321 /// First build the CFG
6322 MachineFunction *F = MBB->getParent();
6323 MachineBasicBlock *thisMBB = MBB;
6324 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6325 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6326 F->insert(MBBIter, newMBB);
6327 F->insert(MBBIter, nextMBB);
6329 // Move all successors to thisMBB to nextMBB
6330 nextMBB->transferSuccessors(thisMBB);
6332 // Update thisMBB to fall through to newMBB
6333 thisMBB->addSuccessor(newMBB);
6335 // newMBB jumps to newMBB and fall through to nextMBB
6336 newMBB->addSuccessor(nextMBB);
6337 newMBB->addSuccessor(newMBB);
6339 // Insert instructions into newMBB based on incoming instruction
6340 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6341 MachineOperand& destOper = mInstr->getOperand(0);
6342 MachineOperand* argOpers[6];
6343 int numArgs = mInstr->getNumOperands() - 1;
6344 for (int i=0; i < numArgs; ++i)
6345 argOpers[i] = &mInstr->getOperand(i+1);
6347 // x86 address has 4 operands: base, index, scale, and displacement
6348 int lastAddrIndx = 3; // [0,3]
6351 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6352 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6353 for (int i=0; i <= lastAddrIndx; ++i)
6354 (*MIB).addOperand(*argOpers[i]);
6356 // We only support register and immediate values
6357 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6358 && "invalid operand");
6360 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6361 if (argOpers[valArgIndx]->isReg())
6362 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6364 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6365 (*MIB).addOperand(*argOpers[valArgIndx]);
6367 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6370 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6375 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6376 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6380 // Cmp and exchange if none has modified the memory location
6381 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6382 for (int i=0; i <= lastAddrIndx; ++i)
6383 (*MIB).addOperand(*argOpers[i]);
6385 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6386 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
6388 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6389 MIB.addReg(X86::EAX);
6392 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6394 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6400 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6401 MachineBasicBlock *BB) {
6402 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6403 switch (MI->getOpcode()) {
6404 default: assert(false && "Unexpected instr type to insert");
6405 case X86::CMOV_FR32:
6406 case X86::CMOV_FR64:
6407 case X86::CMOV_V4F32:
6408 case X86::CMOV_V2F64:
6409 case X86::CMOV_V2I64: {
6410 // To "insert" a SELECT_CC instruction, we actually have to insert the
6411 // diamond control-flow pattern. The incoming instruction knows the
6412 // destination vreg to set, the condition code register to branch on, the
6413 // true/false values to select between, and a branch opcode to use.
6414 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6415 MachineFunction::iterator It = BB;
6421 // cmpTY ccX, r1, r2
6423 // fallthrough --> copy0MBB
6424 MachineBasicBlock *thisMBB = BB;
6425 MachineFunction *F = BB->getParent();
6426 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6427 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6429 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6430 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6431 F->insert(It, copy0MBB);
6432 F->insert(It, sinkMBB);
6433 // Update machine-CFG edges by transferring all successors of the current
6434 // block to the new block which will contain the Phi node for the select.
6435 sinkMBB->transferSuccessors(BB);
6437 // Add the true and fallthrough blocks as its successors.
6438 BB->addSuccessor(copy0MBB);
6439 BB->addSuccessor(sinkMBB);
6442 // %FalseValue = ...
6443 // # fallthrough to sinkMBB
6446 // Update machine-CFG edges
6447 BB->addSuccessor(sinkMBB);
6450 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6453 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6454 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6455 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6457 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6461 case X86::FP32_TO_INT16_IN_MEM:
6462 case X86::FP32_TO_INT32_IN_MEM:
6463 case X86::FP32_TO_INT64_IN_MEM:
6464 case X86::FP64_TO_INT16_IN_MEM:
6465 case X86::FP64_TO_INT32_IN_MEM:
6466 case X86::FP64_TO_INT64_IN_MEM:
6467 case X86::FP80_TO_INT16_IN_MEM:
6468 case X86::FP80_TO_INT32_IN_MEM:
6469 case X86::FP80_TO_INT64_IN_MEM: {
6470 // Change the floating point control register to use "round towards zero"
6471 // mode when truncating to an integer value.
6472 MachineFunction *F = BB->getParent();
6473 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6474 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6476 // Load the old value of the high byte of the control word...
6478 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6479 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6481 // Set the high part to be round to zero...
6482 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6485 // Reload the modified control word now...
6486 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6488 // Restore the memory image of control word to original value
6489 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6492 // Get the X86 opcode to use.
6494 switch (MI->getOpcode()) {
6495 default: assert(0 && "illegal opcode!");
6496 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6497 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6498 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6499 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6500 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6501 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6502 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6503 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6504 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6508 MachineOperand &Op = MI->getOperand(0);
6509 if (Op.isRegister()) {
6510 AM.BaseType = X86AddressMode::RegBase;
6511 AM.Base.Reg = Op.getReg();
6513 AM.BaseType = X86AddressMode::FrameIndexBase;
6514 AM.Base.FrameIndex = Op.getIndex();
6516 Op = MI->getOperand(1);
6517 if (Op.isImmediate())
6518 AM.Scale = Op.getImm();
6519 Op = MI->getOperand(2);
6520 if (Op.isImmediate())
6521 AM.IndexReg = Op.getImm();
6522 Op = MI->getOperand(3);
6523 if (Op.isGlobalAddress()) {
6524 AM.GV = Op.getGlobal();
6526 AM.Disp = Op.getImm();
6528 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6529 .addReg(MI->getOperand(4).getReg());
6531 // Reload the original control word now.
6532 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6534 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6537 case X86::ATOMAND32:
6538 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6539 X86::AND32ri, X86::MOV32rm,
6540 X86::LCMPXCHG32, X86::MOV32rr,
6541 X86::NOT32r, X86::EAX,
6542 X86::GR32RegisterClass);
6544 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6545 X86::OR32ri, X86::MOV32rm,
6546 X86::LCMPXCHG32, X86::MOV32rr,
6547 X86::NOT32r, X86::EAX,
6548 X86::GR32RegisterClass);
6549 case X86::ATOMXOR32:
6550 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6551 X86::XOR32ri, X86::MOV32rm,
6552 X86::LCMPXCHG32, X86::MOV32rr,
6553 X86::NOT32r, X86::EAX,
6554 X86::GR32RegisterClass);
6555 case X86::ATOMNAND32:
6556 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6557 X86::AND32ri, X86::MOV32rm,
6558 X86::LCMPXCHG32, X86::MOV32rr,
6559 X86::NOT32r, X86::EAX,
6560 X86::GR32RegisterClass, true);
6561 case X86::ATOMMIN32:
6562 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6563 case X86::ATOMMAX32:
6564 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6565 case X86::ATOMUMIN32:
6566 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6567 case X86::ATOMUMAX32:
6568 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6570 case X86::ATOMAND16:
6571 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6572 X86::AND16ri, X86::MOV16rm,
6573 X86::LCMPXCHG16, X86::MOV16rr,
6574 X86::NOT16r, X86::AX,
6575 X86::GR16RegisterClass);
6577 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
6578 X86::OR16ri, X86::MOV16rm,
6579 X86::LCMPXCHG16, X86::MOV16rr,
6580 X86::NOT16r, X86::AX,
6581 X86::GR16RegisterClass);
6582 case X86::ATOMXOR16:
6583 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
6584 X86::XOR16ri, X86::MOV16rm,
6585 X86::LCMPXCHG16, X86::MOV16rr,
6586 X86::NOT16r, X86::AX,
6587 X86::GR16RegisterClass);
6588 case X86::ATOMNAND16:
6589 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6590 X86::AND16ri, X86::MOV16rm,
6591 X86::LCMPXCHG16, X86::MOV16rr,
6592 X86::NOT16r, X86::AX,
6593 X86::GR16RegisterClass, true);
6594 case X86::ATOMMIN16:
6595 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
6596 case X86::ATOMMAX16:
6597 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
6598 case X86::ATOMUMIN16:
6599 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
6600 case X86::ATOMUMAX16:
6601 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
6604 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6605 X86::AND8ri, X86::MOV8rm,
6606 X86::LCMPXCHG8, X86::MOV8rr,
6607 X86::NOT8r, X86::AL,
6608 X86::GR8RegisterClass);
6610 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
6611 X86::OR8ri, X86::MOV8rm,
6612 X86::LCMPXCHG8, X86::MOV8rr,
6613 X86::NOT8r, X86::AL,
6614 X86::GR8RegisterClass);
6616 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
6617 X86::XOR8ri, X86::MOV8rm,
6618 X86::LCMPXCHG8, X86::MOV8rr,
6619 X86::NOT8r, X86::AL,
6620 X86::GR8RegisterClass);
6621 case X86::ATOMNAND8:
6622 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6623 X86::AND8ri, X86::MOV8rm,
6624 X86::LCMPXCHG8, X86::MOV8rr,
6625 X86::NOT8r, X86::AL,
6626 X86::GR8RegisterClass, true);
6627 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
6628 case X86::ATOMAND64:
6629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6630 X86::AND64ri32, X86::MOV64rm,
6631 X86::LCMPXCHG64, X86::MOV64rr,
6632 X86::NOT64r, X86::RAX,
6633 X86::GR64RegisterClass);
6635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
6636 X86::OR64ri32, X86::MOV64rm,
6637 X86::LCMPXCHG64, X86::MOV64rr,
6638 X86::NOT64r, X86::RAX,
6639 X86::GR64RegisterClass);
6640 case X86::ATOMXOR64:
6641 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
6642 X86::XOR64ri32, X86::MOV64rm,
6643 X86::LCMPXCHG64, X86::MOV64rr,
6644 X86::NOT64r, X86::RAX,
6645 X86::GR64RegisterClass);
6646 case X86::ATOMNAND64:
6647 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6648 X86::AND64ri32, X86::MOV64rm,
6649 X86::LCMPXCHG64, X86::MOV64rr,
6650 X86::NOT64r, X86::RAX,
6651 X86::GR64RegisterClass, true);
6652 case X86::ATOMMIN64:
6653 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
6654 case X86::ATOMMAX64:
6655 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
6656 case X86::ATOMUMIN64:
6657 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
6658 case X86::ATOMUMAX64:
6659 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
6663 //===----------------------------------------------------------------------===//
6664 // X86 Optimization Hooks
6665 //===----------------------------------------------------------------------===//
6667 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6671 const SelectionDAG &DAG,
6672 unsigned Depth) const {
6673 unsigned Opc = Op.getOpcode();
6674 assert((Opc >= ISD::BUILTIN_OP_END ||
6675 Opc == ISD::INTRINSIC_WO_CHAIN ||
6676 Opc == ISD::INTRINSIC_W_CHAIN ||
6677 Opc == ISD::INTRINSIC_VOID) &&
6678 "Should use MaskedValueIsZero if you don't know whether Op"
6679 " is a target node!");
6681 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
6685 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6686 Mask.getBitWidth() - 1);
6691 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
6692 /// node is a GlobalAddress + offset.
6693 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6694 GlobalValue* &GA, int64_t &Offset) const{
6695 if (N->getOpcode() == X86ISD::Wrapper) {
6696 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
6697 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6701 return TargetLowering::isGAPlusOffset(N, GA, Offset);
6704 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6705 const TargetLowering &TLI) {
6708 if (TLI.isGAPlusOffset(Base, GV, Offset))
6709 return (GV->getAlignment() >= N && (Offset % N) == 0);
6710 // DAG combine handles the stack object case.
6714 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
6715 unsigned NumElems, MVT EVT,
6717 SelectionDAG &DAG, MachineFrameInfo *MFI,
6718 const TargetLowering &TLI) {
6720 for (unsigned i = 0; i < NumElems; ++i) {
6721 SDValue Idx = PermMask.getOperand(i);
6722 if (Idx.getOpcode() == ISD::UNDEF) {
6728 SDValue Elt = DAG.getShuffleScalarElt(N, i);
6729 if (!Elt.getNode() ||
6730 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6733 Base = Elt.getNode();
6734 if (Base->getOpcode() == ISD::UNDEF)
6738 if (Elt.getOpcode() == ISD::UNDEF)
6741 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
6742 EVT.getSizeInBits()/8, i, MFI))
6748 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6749 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6750 /// if the load addresses are consecutive, non-overlapping, and in the right
6752 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
6753 const TargetLowering &TLI) {
6754 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6755 MVT VT = N->getValueType(0);
6756 MVT EVT = VT.getVectorElementType();
6757 SDValue PermMask = N->getOperand(2);
6758 unsigned NumElems = PermMask.getNumOperands();
6759 SDNode *Base = NULL;
6760 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6764 LoadSDNode *LD = cast<LoadSDNode>(Base);
6765 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
6766 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6767 LD->getSrcValueOffset(), LD->isVolatile());
6768 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6769 LD->getSrcValueOffset(), LD->isVolatile(),
6770 LD->getAlignment());
6773 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
6774 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
6775 const X86Subtarget *Subtarget,
6776 const TargetLowering &TLI) {
6777 unsigned NumOps = N->getNumOperands();
6779 // Ignore single operand BUILD_VECTOR.
6783 MVT VT = N->getValueType(0);
6784 MVT EVT = VT.getVectorElementType();
6785 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6786 // We are looking for load i64 and zero extend. We want to transform
6787 // it before legalizer has a chance to expand it. Also look for i64
6788 // BUILD_PAIR bit casted to f64.
6790 // This must be an insertion into a zero vector.
6791 SDValue HighElt = N->getOperand(1);
6792 if (!isZeroNode(HighElt))
6795 // Value must be a load.
6796 SDNode *Base = N->getOperand(0).getNode();
6797 if (!isa<LoadSDNode>(Base)) {
6798 if (Base->getOpcode() != ISD::BIT_CONVERT)
6800 Base = Base->getOperand(0).getNode();
6801 if (!isa<LoadSDNode>(Base))
6805 // Transform it into VZEXT_LOAD addr.
6806 LoadSDNode *LD = cast<LoadSDNode>(Base);
6808 // Load must not be an extload.
6809 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
6812 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6815 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6816 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6817 const X86Subtarget *Subtarget) {
6818 SDValue Cond = N->getOperand(0);
6820 // If we have SSE[12] support, try to form min/max nodes.
6821 if (Subtarget->hasSSE2() &&
6822 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6823 if (Cond.getOpcode() == ISD::SETCC) {
6824 // Get the LHS/RHS of the select.
6825 SDValue LHS = N->getOperand(1);
6826 SDValue RHS = N->getOperand(2);
6827 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
6829 unsigned Opcode = 0;
6830 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
6833 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6836 if (!UnsafeFPMath) break;
6838 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6840 Opcode = X86ISD::FMIN;
6843 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6846 if (!UnsafeFPMath) break;
6848 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6850 Opcode = X86ISD::FMAX;
6853 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
6856 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6859 if (!UnsafeFPMath) break;
6861 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6863 Opcode = X86ISD::FMIN;
6866 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6869 if (!UnsafeFPMath) break;
6871 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6873 Opcode = X86ISD::FMAX;
6879 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
6887 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6888 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
6889 const X86Subtarget *Subtarget) {
6890 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6891 // the FP state in cases where an emms may be missing.
6892 // A preferable solution to the general problem is to figure out the right
6893 // places to insert EMMS. This qualifies as a quick hack.
6894 StoreSDNode *St = cast<StoreSDNode>(N);
6895 if (St->getValue().getValueType().isVector() &&
6896 St->getValue().getValueType().getSizeInBits() == 64 &&
6897 isa<LoadSDNode>(St->getValue()) &&
6898 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6899 St->getChain().hasOneUse() && !St->isVolatile()) {
6900 SDNode* LdVal = St->getValue().getNode();
6902 int TokenFactorIndex = -1;
6903 SmallVector<SDValue, 8> Ops;
6904 SDNode* ChainVal = St->getChain().getNode();
6905 // Must be a store of a load. We currently handle two cases: the load
6906 // is a direct child, and it's under an intervening TokenFactor. It is
6907 // possible to dig deeper under nested TokenFactors.
6908 if (ChainVal == LdVal)
6909 Ld = cast<LoadSDNode>(St->getChain());
6910 else if (St->getValue().hasOneUse() &&
6911 ChainVal->getOpcode() == ISD::TokenFactor) {
6912 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
6913 if (ChainVal->getOperand(i).getNode() == LdVal) {
6914 TokenFactorIndex = i;
6915 Ld = cast<LoadSDNode>(St->getValue());
6917 Ops.push_back(ChainVal->getOperand(i));
6921 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6922 if (Subtarget->is64Bit()) {
6923 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6924 Ld->getBasePtr(), Ld->getSrcValue(),
6925 Ld->getSrcValueOffset(), Ld->isVolatile(),
6926 Ld->getAlignment());
6927 SDValue NewChain = NewLd.getValue(1);
6928 if (TokenFactorIndex != -1) {
6929 Ops.push_back(NewChain);
6930 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6933 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6934 St->getSrcValue(), St->getSrcValueOffset(),
6935 St->isVolatile(), St->getAlignment());
6938 // Otherwise, lower to two 32-bit copies.
6939 SDValue LoAddr = Ld->getBasePtr();
6940 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6941 DAG.getConstant(4, MVT::i32));
6943 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6944 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6945 Ld->isVolatile(), Ld->getAlignment());
6946 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6947 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6949 MinAlign(Ld->getAlignment(), 4));
6951 SDValue NewChain = LoLd.getValue(1);
6952 if (TokenFactorIndex != -1) {
6953 Ops.push_back(LoLd);
6954 Ops.push_back(HiLd);
6955 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6959 LoAddr = St->getBasePtr();
6960 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6961 DAG.getConstant(4, MVT::i32));
6963 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6964 St->getSrcValue(), St->getSrcValueOffset(),
6965 St->isVolatile(), St->getAlignment());
6966 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6968 St->getSrcValueOffset() + 4,
6970 MinAlign(St->getAlignment(), 4));
6971 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6977 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6978 /// X86ISD::FXOR nodes.
6979 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6980 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6981 // F[X]OR(0.0, x) -> x
6982 // F[X]OR(x, 0.0) -> x
6983 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6984 if (C->getValueAPF().isPosZero())
6985 return N->getOperand(1);
6986 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6987 if (C->getValueAPF().isPosZero())
6988 return N->getOperand(0);
6992 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6993 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6994 // FAND(0.0, x) -> 0.0
6995 // FAND(x, 0.0) -> 0.0
6996 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6997 if (C->getValueAPF().isPosZero())
6998 return N->getOperand(0);
6999 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7000 if (C->getValueAPF().isPosZero())
7001 return N->getOperand(1);
7006 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7007 DAGCombinerInfo &DCI) const {
7008 SelectionDAG &DAG = DCI.DAG;
7009 switch (N->getOpcode()) {
7011 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7012 case ISD::BUILD_VECTOR:
7013 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7014 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7015 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7017 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7018 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7024 //===----------------------------------------------------------------------===//
7025 // X86 Inline Assembly Support
7026 //===----------------------------------------------------------------------===//
7028 /// getConstraintType - Given a constraint letter, return the type of
7029 /// constraint it is for this target.
7030 X86TargetLowering::ConstraintType
7031 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7032 if (Constraint.size() == 1) {
7033 switch (Constraint[0]) {
7044 return C_RegisterClass;
7049 return TargetLowering::getConstraintType(Constraint);
7052 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7053 /// with another that has more specific requirements based on the type of the
7054 /// corresponding operand.
7055 const char *X86TargetLowering::
7056 LowerXConstraint(MVT ConstraintVT) const {
7057 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7058 // 'f' like normal targets.
7059 if (ConstraintVT.isFloatingPoint()) {
7060 if (Subtarget->hasSSE2())
7062 if (Subtarget->hasSSE1())
7066 return TargetLowering::LowerXConstraint(ConstraintVT);
7069 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7070 /// vector. If it is invalid, don't add anything to Ops.
7071 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7073 std::vector<SDValue>&Ops,
7074 SelectionDAG &DAG) const {
7075 SDValue Result(0, 0);
7077 switch (Constraint) {
7080 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7081 if (C->getValue() <= 31) {
7082 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
7088 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7089 if (C->getValue() <= 255) {
7090 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
7096 // Literal immediates are always ok.
7097 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7098 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
7102 // If we are in non-pic codegen mode, we allow the address of a global (with
7103 // an optional displacement) to be used with 'i'.
7104 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7107 // Match either (GA) or (GA+C)
7109 Offset = GA->getOffset();
7110 } else if (Op.getOpcode() == ISD::ADD) {
7111 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7112 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7114 Offset = GA->getOffset()+C->getValue();
7116 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7117 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7119 Offset = GA->getOffset()+C->getValue();
7126 // If addressing this global requires a load (e.g. in PIC mode), we can't
7128 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
7132 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7138 // Otherwise, not valid for this mode.
7143 if (Result.getNode()) {
7144 Ops.push_back(Result);
7147 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7150 std::vector<unsigned> X86TargetLowering::
7151 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7153 if (Constraint.size() == 1) {
7154 // FIXME: not handling fp-stack yet!
7155 switch (Constraint[0]) { // GCC X86 Constraint Letters
7156 default: break; // Unknown constraint letter
7157 case 'A': // EAX/EDX
7158 if (VT == MVT::i32 || VT == MVT::i64)
7159 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
7161 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7164 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7165 else if (VT == MVT::i16)
7166 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7167 else if (VT == MVT::i8)
7168 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7169 else if (VT == MVT::i64)
7170 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7175 return std::vector<unsigned>();
7178 std::pair<unsigned, const TargetRegisterClass*>
7179 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7181 // First, see if this is a constraint that directly corresponds to an LLVM
7183 if (Constraint.size() == 1) {
7184 // GCC Constraint Letters
7185 switch (Constraint[0]) {
7187 case 'r': // GENERAL_REGS
7188 case 'R': // LEGACY_REGS
7189 case 'l': // INDEX_REGS
7190 if (VT == MVT::i64 && Subtarget->is64Bit())
7191 return std::make_pair(0U, X86::GR64RegisterClass);
7193 return std::make_pair(0U, X86::GR32RegisterClass);
7194 else if (VT == MVT::i16)
7195 return std::make_pair(0U, X86::GR16RegisterClass);
7196 else if (VT == MVT::i8)
7197 return std::make_pair(0U, X86::GR8RegisterClass);
7199 case 'f': // FP Stack registers.
7200 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7201 // value to the correct fpstack register class.
7202 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7203 return std::make_pair(0U, X86::RFP32RegisterClass);
7204 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7205 return std::make_pair(0U, X86::RFP64RegisterClass);
7206 return std::make_pair(0U, X86::RFP80RegisterClass);
7207 case 'y': // MMX_REGS if MMX allowed.
7208 if (!Subtarget->hasMMX()) break;
7209 return std::make_pair(0U, X86::VR64RegisterClass);
7211 case 'Y': // SSE_REGS if SSE2 allowed
7212 if (!Subtarget->hasSSE2()) break;
7214 case 'x': // SSE_REGS if SSE1 allowed
7215 if (!Subtarget->hasSSE1()) break;
7217 switch (VT.getSimpleVT()) {
7219 // Scalar SSE types.
7222 return std::make_pair(0U, X86::FR32RegisterClass);
7225 return std::make_pair(0U, X86::FR64RegisterClass);
7233 return std::make_pair(0U, X86::VR128RegisterClass);
7239 // Use the default implementation in TargetLowering to convert the register
7240 // constraint into a member of a register class.
7241 std::pair<unsigned, const TargetRegisterClass*> Res;
7242 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7244 // Not found as a standard register?
7245 if (Res.second == 0) {
7246 // GCC calls "st(0)" just plain "st".
7247 if (StringsEqualNoCase("{st}", Constraint)) {
7248 Res.first = X86::ST0;
7249 Res.second = X86::RFP80RegisterClass;
7255 // Otherwise, check to see if this is a register class of the wrong value
7256 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7257 // turn into {ax},{dx}.
7258 if (Res.second->hasType(VT))
7259 return Res; // Correct type already, nothing to do.
7261 // All of the single-register GCC register classes map their values onto
7262 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7263 // really want an 8-bit or 32-bit register, map to the appropriate register
7264 // class and return the appropriate register.
7265 if (Res.second == X86::GR16RegisterClass) {
7266 if (VT == MVT::i8) {
7267 unsigned DestReg = 0;
7268 switch (Res.first) {
7270 case X86::AX: DestReg = X86::AL; break;
7271 case X86::DX: DestReg = X86::DL; break;
7272 case X86::CX: DestReg = X86::CL; break;
7273 case X86::BX: DestReg = X86::BL; break;
7276 Res.first = DestReg;
7277 Res.second = Res.second = X86::GR8RegisterClass;
7279 } else if (VT == MVT::i32) {
7280 unsigned DestReg = 0;
7281 switch (Res.first) {
7283 case X86::AX: DestReg = X86::EAX; break;
7284 case X86::DX: DestReg = X86::EDX; break;
7285 case X86::CX: DestReg = X86::ECX; break;
7286 case X86::BX: DestReg = X86::EBX; break;
7287 case X86::SI: DestReg = X86::ESI; break;
7288 case X86::DI: DestReg = X86::EDI; break;
7289 case X86::BP: DestReg = X86::EBP; break;
7290 case X86::SP: DestReg = X86::ESP; break;
7293 Res.first = DestReg;
7294 Res.second = Res.second = X86::GR32RegisterClass;
7296 } else if (VT == MVT::i64) {
7297 unsigned DestReg = 0;
7298 switch (Res.first) {
7300 case X86::AX: DestReg = X86::RAX; break;
7301 case X86::DX: DestReg = X86::RDX; break;
7302 case X86::CX: DestReg = X86::RCX; break;
7303 case X86::BX: DestReg = X86::RBX; break;
7304 case X86::SI: DestReg = X86::RSI; break;
7305 case X86::DI: DestReg = X86::RDI; break;
7306 case X86::BP: DestReg = X86::RBP; break;
7307 case X86::SP: DestReg = X86::RSP; break;
7310 Res.first = DestReg;
7311 Res.second = Res.second = X86::GR64RegisterClass;
7314 } else if (Res.second == X86::FR32RegisterClass ||
7315 Res.second == X86::FR64RegisterClass ||
7316 Res.second == X86::VR128RegisterClass) {
7317 // Handle references to XMM physical registers that got mapped into the
7318 // wrong class. This can happen with constraints like {xmm0} where the
7319 // target independent register mapper will just pick the first match it can
7320 // find, ignoring the required type.
7322 Res.second = X86::FR32RegisterClass;
7323 else if (VT == MVT::f64)
7324 Res.second = X86::FR64RegisterClass;
7325 else if (X86::VR128RegisterClass->hasType(VT))
7326 Res.second = X86::VR128RegisterClass;