1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
336 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
339 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
349 if (Subtarget->hasSSE1())
350 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
352 if (!Subtarget->hasSSE2())
353 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
387 if (Subtarget->is64Bit()) {
388 setExceptionPointerRegister(X86::RAX);
389 setExceptionSelectorRegister(X86::RDX);
391 setExceptionPointerRegister(X86::EAX);
392 setExceptionSelectorRegister(X86::EDX);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
397 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402 setOperationAction(ISD::VASTART , MVT::Other, Custom);
403 setOperationAction(ISD::VAEND , MVT::Other, Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::VAARG , MVT::Other, Custom);
406 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
408 setOperationAction(ISD::VAARG , MVT::Other, Expand);
409 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
412 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
413 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
414 if (Subtarget->is64Bit())
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416 if (Subtarget->isTargetCygMing())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 if (!UseSoftFloat && X86ScalarSSEf64) {
422 // f32 and f64 use SSE.
423 // Set up the FP register classes.
424 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
427 // Use ANDPD to simulate FABS.
428 setOperationAction(ISD::FABS , MVT::f64, Custom);
429 setOperationAction(ISD::FABS , MVT::f32, Custom);
431 // Use XORP to simulate FNEG.
432 setOperationAction(ISD::FNEG , MVT::f64, Custom);
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 // Use ANDPD and ORPD to simulate FCOPYSIGN.
436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
439 // We don't support sin/cos/fmod
440 setOperationAction(ISD::FSIN , MVT::f64, Expand);
441 setOperationAction(ISD::FCOS , MVT::f64, Expand);
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Expand FP immediates into loads from the stack, except for the special
447 addLegalFPImmediate(APFloat(+0.0)); // xorpd
448 addLegalFPImmediate(APFloat(+0.0f)); // xorps
449 } else if (!UseSoftFloat && X86ScalarSSEf32) {
450 // Use SSE for f32, x87 for f64.
451 // Set up the FP register classes.
452 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
455 // Use ANDPS to simulate FABS.
456 setOperationAction(ISD::FABS , MVT::f32, Custom);
458 // Use XORP to simulate FNEG.
459 setOperationAction(ISD::FNEG , MVT::f32, Custom);
461 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
463 // Use ANDPS and ORPS to simulate FCOPYSIGN.
464 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
467 // We don't support sin/cos/fmod
468 setOperationAction(ISD::FSIN , MVT::f32, Expand);
469 setOperationAction(ISD::FCOS , MVT::f32, Expand);
471 // Special cases we handle for FP constants.
472 addLegalFPImmediate(APFloat(+0.0f)); // xorps
473 addLegalFPImmediate(APFloat(+0.0)); // FLD0
474 addLegalFPImmediate(APFloat(+1.0)); // FLD1
475 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
479 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
480 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
482 } else if (!UseSoftFloat) {
483 // f32 and f64 in x87.
484 // Set up the FP register classes.
485 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
488 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
489 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
494 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
495 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
497 addLegalFPImmediate(APFloat(+0.0)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
507 // Long double always uses X87.
509 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
514 APFloat TmpFlt(+0.0);
515 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
517 addLegalFPImmediate(TmpFlt); // FLD0
519 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
520 APFloat TmpFlt2(+1.0);
521 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
523 addLegalFPImmediate(TmpFlt2); // FLD1
524 TmpFlt2.changeSign();
525 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
529 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
530 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
534 // Always use a library call for pow.
535 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
539 setOperationAction(ISD::FLOG, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
545 // First set operation action for all vector types to either promote
546 // (for widening) or expand (for scalarization). Then we will selectively
547 // turn on ones that can be effectively codegen'd.
548 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
601 // with -msoft-float, disable use of MMX as well.
602 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
603 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
604 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
605 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
606 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
607 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
609 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
610 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
611 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
612 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
614 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
615 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
616 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
617 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
619 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
620 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
622 setOperationAction(ISD::AND, MVT::v8i8, Promote);
623 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
624 setOperationAction(ISD::AND, MVT::v4i16, Promote);
625 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
626 setOperationAction(ISD::AND, MVT::v2i32, Promote);
627 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
628 setOperationAction(ISD::AND, MVT::v1i64, Legal);
630 setOperationAction(ISD::OR, MVT::v8i8, Promote);
631 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
632 setOperationAction(ISD::OR, MVT::v4i16, Promote);
633 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
634 setOperationAction(ISD::OR, MVT::v2i32, Promote);
635 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
636 setOperationAction(ISD::OR, MVT::v1i64, Legal);
638 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
639 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
640 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
641 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
642 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
643 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
644 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
646 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
647 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
648 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
649 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
650 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
651 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
652 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
653 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
654 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
656 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
657 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
659 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
660 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
662 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
663 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
664 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
667 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
669 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
670 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
672 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
674 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
675 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
676 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
677 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
678 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
679 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
680 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
681 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
682 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
685 if (!UseSoftFloat && Subtarget->hasSSE1()) {
686 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
688 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
689 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
690 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
691 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
692 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
693 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
694 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
695 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
696 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
697 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
698 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
699 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
702 if (!UseSoftFloat && Subtarget->hasSSE2()) {
703 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
705 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
706 // registers cannot be used even for integer operations.
707 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
708 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
709 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
710 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
712 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
713 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
714 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
715 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
716 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
717 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
718 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
719 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
720 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
721 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
722 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
723 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
724 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
725 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
726 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
727 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
729 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
730 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
731 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
732 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
734 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
735 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
736 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
740 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
741 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
742 EVT VT = (MVT::SimpleValueType)i;
743 // Do not attempt to custom lower non-power-of-2 vectors
744 if (!isPowerOf2_32(VT.getVectorNumElements()))
746 // Do not attempt to custom lower non-128-bit vectors
747 if (!VT.is128BitVector())
749 setOperationAction(ISD::BUILD_VECTOR,
750 VT.getSimpleVT().SimpleTy, Custom);
751 setOperationAction(ISD::VECTOR_SHUFFLE,
752 VT.getSimpleVT().SimpleTy, Custom);
753 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
754 VT.getSimpleVT().SimpleTy, Custom);
757 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
758 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
759 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
760 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
761 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
762 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
764 if (Subtarget->is64Bit()) {
765 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
766 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
769 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
770 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
771 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
774 // Do not attempt to promote non-128-bit vectors
775 if (!VT.is128BitVector()) {
778 setOperationAction(ISD::AND, SVT, Promote);
779 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
780 setOperationAction(ISD::OR, SVT, Promote);
781 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
782 setOperationAction(ISD::XOR, SVT, Promote);
783 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
784 setOperationAction(ISD::LOAD, SVT, Promote);
785 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
786 setOperationAction(ISD::SELECT, SVT, Promote);
787 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
790 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
792 // Custom lower v2i64 and v2f64 selects.
793 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
794 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
795 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
796 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
798 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
799 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
800 if (!DisableMMX && Subtarget->hasMMX()) {
801 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
802 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
806 if (Subtarget->hasSSE41()) {
807 // FIXME: Do we need to handle scalar-to-vector here?
808 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
810 // i8 and i16 vectors are custom , because the source register and source
811 // source memory operand types are not the same width. f32 vectors are
812 // custom since the immediate controlling the insert encodes additional
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
819 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 if (Subtarget->is64Bit()) {
825 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
830 if (Subtarget->hasSSE42()) {
831 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
834 if (!UseSoftFloat && Subtarget->hasAVX()) {
835 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
836 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
837 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
838 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
840 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
841 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
842 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
843 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
844 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
845 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
846 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
847 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
848 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
849 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
850 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
851 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
852 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
853 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
854 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
856 // Operations to consider commented out -v16i16 v32i8
857 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
858 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
859 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
860 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
861 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
862 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
863 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
864 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
865 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
866 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
867 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
868 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
869 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
870 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
872 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
873 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
874 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
875 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
877 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
878 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
879 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
883 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
885 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
887 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
891 // Not sure we want to do this since there are no 256-bit integer
894 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
895 // This includes 256-bit vectors
896 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
897 EVT VT = (MVT::SimpleValueType)i;
899 // Do not attempt to custom lower non-power-of-2 vectors
900 if (!isPowerOf2_32(VT.getVectorNumElements()))
903 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
904 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
908 if (Subtarget->is64Bit()) {
909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
910 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
915 // Not sure we want to do this since there are no 256-bit integer
918 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
919 // Including 256-bit vectors
920 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
921 EVT VT = (MVT::SimpleValueType)i;
923 if (!VT.is256BitVector()) {
926 setOperationAction(ISD::AND, VT, Promote);
927 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
928 setOperationAction(ISD::OR, VT, Promote);
929 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
930 setOperationAction(ISD::XOR, VT, Promote);
931 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
932 setOperationAction(ISD::LOAD, VT, Promote);
933 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
934 setOperationAction(ISD::SELECT, VT, Promote);
935 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
938 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
942 // We want to custom lower some of our intrinsics.
943 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
945 // Add/Sub/Mul with overflow operations are custom lowered.
946 setOperationAction(ISD::SADDO, MVT::i32, Custom);
947 setOperationAction(ISD::SADDO, MVT::i64, Custom);
948 setOperationAction(ISD::UADDO, MVT::i32, Custom);
949 setOperationAction(ISD::UADDO, MVT::i64, Custom);
950 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
951 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
952 setOperationAction(ISD::USUBO, MVT::i32, Custom);
953 setOperationAction(ISD::USUBO, MVT::i64, Custom);
954 setOperationAction(ISD::SMULO, MVT::i32, Custom);
955 setOperationAction(ISD::SMULO, MVT::i64, Custom);
957 if (!Subtarget->is64Bit()) {
958 // These libcalls are not available in 32-bit.
959 setLibcallName(RTLIB::SHL_I128, 0);
960 setLibcallName(RTLIB::SRL_I128, 0);
961 setLibcallName(RTLIB::SRA_I128, 0);
964 // We have target-specific dag combine patterns for the following nodes:
965 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
966 setTargetDAGCombine(ISD::BUILD_VECTOR);
967 setTargetDAGCombine(ISD::SELECT);
968 setTargetDAGCombine(ISD::SHL);
969 setTargetDAGCombine(ISD::SRA);
970 setTargetDAGCombine(ISD::SRL);
971 setTargetDAGCombine(ISD::STORE);
972 setTargetDAGCombine(ISD::MEMBARRIER);
973 if (Subtarget->is64Bit())
974 setTargetDAGCombine(ISD::MUL);
976 computeRegisterProperties();
978 // Divide and reminder operations have no vector equivalent and can
979 // trap. Do a custom widening for these operations in which we never
980 // generate more divides/remainder than the original vector width.
981 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
982 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
983 if (!isTypeLegal((MVT::SimpleValueType)VT)) {
984 setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
985 setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
986 setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
987 setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
991 // FIXME: These should be based on subtarget info. Plus, the values should
992 // be smaller when we are in optimizing for size mode.
993 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
994 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
995 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
996 setPrefLoopAlignment(16);
997 benefitFromCodePlacementOpt = true;
1001 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1006 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1007 /// the desired ByVal argument alignment.
1008 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1011 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1012 if (VTy->getBitWidth() == 128)
1014 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1015 unsigned EltAlign = 0;
1016 getMaxByValAlign(ATy->getElementType(), EltAlign);
1017 if (EltAlign > MaxAlign)
1018 MaxAlign = EltAlign;
1019 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1020 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1021 unsigned EltAlign = 0;
1022 getMaxByValAlign(STy->getElementType(i), EltAlign);
1023 if (EltAlign > MaxAlign)
1024 MaxAlign = EltAlign;
1032 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1033 /// function arguments in the caller parameter area. For X86, aggregates
1034 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1035 /// are at 4-byte boundaries.
1036 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1037 if (Subtarget->is64Bit()) {
1038 // Max of 8 and alignment of type.
1039 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1046 if (Subtarget->hasSSE1())
1047 getMaxByValAlign(Ty, Align);
1051 /// getOptimalMemOpType - Returns the target specific optimal type for load
1052 /// and store operations as a result of memset, memcpy, and memmove
1053 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1056 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1057 bool isSrcConst, bool isSrcStr,
1058 SelectionDAG &DAG) const {
1059 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1060 // linux. This is because the stack realignment code can't handle certain
1061 // cases like PR2962. This should be removed when PR2962 is fixed.
1062 const Function *F = DAG.getMachineFunction().getFunction();
1063 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1064 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1065 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1067 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1070 if (Subtarget->is64Bit() && Size >= 8)
1075 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1077 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1078 SelectionDAG &DAG) const {
1079 if (usesGlobalOffsetTable())
1080 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1081 if (!Subtarget->is64Bit())
1082 // This doesn't have DebugLoc associated with it, but is not really the
1083 // same as a Register.
1084 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1089 /// getFunctionAlignment - Return the Log2 alignment of this function.
1090 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1091 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1094 //===----------------------------------------------------------------------===//
1095 // Return Value Calling Convention Implementation
1096 //===----------------------------------------------------------------------===//
1098 #include "X86GenCallingConv.inc"
1101 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1102 const SmallVectorImpl<EVT> &OutTys,
1103 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1104 SelectionDAG &DAG) {
1105 SmallVector<CCValAssign, 16> RVLocs;
1106 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1107 RVLocs, *DAG.getContext());
1108 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1112 X86TargetLowering::LowerReturn(SDValue Chain,
1113 CallingConv::ID CallConv, bool isVarArg,
1114 const SmallVectorImpl<ISD::OutputArg> &Outs,
1115 DebugLoc dl, SelectionDAG &DAG) {
1117 SmallVector<CCValAssign, 16> RVLocs;
1118 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1119 RVLocs, *DAG.getContext());
1120 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1122 // If this is the first return lowered for this function, add the regs to the
1123 // liveout set for the function.
1124 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1125 for (unsigned i = 0; i != RVLocs.size(); ++i)
1126 if (RVLocs[i].isRegLoc())
1127 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1132 SmallVector<SDValue, 6> RetOps;
1133 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1134 // Operand #1 = Bytes To Pop
1135 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1137 // Copy the result values into the output registers.
1138 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1139 CCValAssign &VA = RVLocs[i];
1140 assert(VA.isRegLoc() && "Can only return in registers!");
1141 SDValue ValToCopy = Outs[i].Val;
1143 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1144 // the RET instruction and handled by the FP Stackifier.
1145 if (VA.getLocReg() == X86::ST0 ||
1146 VA.getLocReg() == X86::ST1) {
1147 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1148 // change the value to the FP stack register class.
1149 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1150 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1151 RetOps.push_back(ValToCopy);
1152 // Don't emit a copytoreg.
1156 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1157 // which is returned in RAX / RDX.
1158 if (Subtarget->is64Bit()) {
1159 EVT ValVT = ValToCopy.getValueType();
1160 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1161 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1162 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1163 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1167 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1168 Flag = Chain.getValue(1);
1171 // The x86-64 ABI for returning structs by value requires that we copy
1172 // the sret argument into %rax for the return. We saved the argument into
1173 // a virtual register in the entry block, so now we copy the value out
1175 if (Subtarget->is64Bit() &&
1176 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1177 MachineFunction &MF = DAG.getMachineFunction();
1178 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1179 unsigned Reg = FuncInfo->getSRetReturnReg();
1181 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1182 FuncInfo->setSRetReturnReg(Reg);
1184 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1186 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1187 Flag = Chain.getValue(1);
1189 // RAX now acts like a return value.
1190 MF.getRegInfo().addLiveOut(X86::RAX);
1193 RetOps[0] = Chain; // Update chain.
1195 // Add the flag if we have it.
1197 RetOps.push_back(Flag);
1199 return DAG.getNode(X86ISD::RET_FLAG, dl,
1200 MVT::Other, &RetOps[0], RetOps.size());
1203 /// LowerCallResult - Lower the result values of a call into the
1204 /// appropriate copies out of appropriate physical registers.
1207 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1208 CallingConv::ID CallConv, bool isVarArg,
1209 const SmallVectorImpl<ISD::InputArg> &Ins,
1210 DebugLoc dl, SelectionDAG &DAG,
1211 SmallVectorImpl<SDValue> &InVals) {
1213 // Assign locations to each value returned by this call.
1214 SmallVector<CCValAssign, 16> RVLocs;
1215 bool Is64Bit = Subtarget->is64Bit();
1216 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1217 RVLocs, *DAG.getContext());
1218 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1220 // Copy all of the result registers out of their specified physreg.
1221 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1222 CCValAssign &VA = RVLocs[i];
1223 EVT CopyVT = VA.getValVT();
1225 // If this is x86-64, and we disabled SSE, we can't return FP values
1226 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1227 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1228 llvm_report_error("SSE register return with SSE disabled");
1231 // If this is a call to a function that returns an fp value on the floating
1232 // point stack, but where we prefer to use the value in xmm registers, copy
1233 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1234 if ((VA.getLocReg() == X86::ST0 ||
1235 VA.getLocReg() == X86::ST1) &&
1236 isScalarFPTypeInSSEReg(VA.getValVT())) {
1241 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1242 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1243 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1244 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1245 MVT::v2i64, InFlag).getValue(1);
1246 Val = Chain.getValue(0);
1247 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1248 Val, DAG.getConstant(0, MVT::i64));
1250 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1251 MVT::i64, InFlag).getValue(1);
1252 Val = Chain.getValue(0);
1254 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1256 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1257 CopyVT, InFlag).getValue(1);
1258 Val = Chain.getValue(0);
1260 InFlag = Chain.getValue(2);
1262 if (CopyVT != VA.getValVT()) {
1263 // Round the F80 the right size, which also moves to the appropriate xmm
1265 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1266 // This truncation won't change the value.
1267 DAG.getIntPtrConstant(1));
1270 InVals.push_back(Val);
1277 //===----------------------------------------------------------------------===//
1278 // C & StdCall & Fast Calling Convention implementation
1279 //===----------------------------------------------------------------------===//
1280 // StdCall calling convention seems to be standard for many Windows' API
1281 // routines and around. It differs from C calling convention just a little:
1282 // callee should clean up the stack, not caller. Symbols should be also
1283 // decorated in some fancy way :) It doesn't support any vector arguments.
1284 // For info on fast calling convention see Fast Calling Convention (tail call)
1285 // implementation LowerX86_32FastCCCallTo.
1287 /// CallIsStructReturn - Determines whether a call uses struct return
1289 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1293 return Outs[0].Flags.isSRet();
1296 /// ArgsAreStructReturn - Determines whether a function uses struct
1297 /// return semantics.
1299 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1303 return Ins[0].Flags.isSRet();
1306 /// IsCalleePop - Determines whether the callee is required to pop its
1307 /// own arguments. Callee pop is necessary to support tail calls.
1308 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1312 switch (CallingConv) {
1315 case CallingConv::X86_StdCall:
1316 return !Subtarget->is64Bit();
1317 case CallingConv::X86_FastCall:
1318 return !Subtarget->is64Bit();
1319 case CallingConv::Fast:
1320 return PerformTailCallOpt;
1324 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1325 /// given CallingConvention value.
1326 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1327 if (Subtarget->is64Bit()) {
1328 if (Subtarget->isTargetWin64())
1329 return CC_X86_Win64_C;
1334 if (CC == CallingConv::X86_FastCall)
1335 return CC_X86_32_FastCall;
1336 else if (CC == CallingConv::Fast)
1337 return CC_X86_32_FastCC;
1342 /// NameDecorationForCallConv - Selects the appropriate decoration to
1343 /// apply to a MachineFunction containing a given calling convention.
1345 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1346 if (CallConv == CallingConv::X86_FastCall)
1348 else if (CallConv == CallingConv::X86_StdCall)
1354 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1355 /// by "Src" to address "Dst" with size and alignment information specified by
1356 /// the specific parameter attribute. The copy will be passed as a byval
1357 /// function parameter.
1359 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1360 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1362 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1363 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1364 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1368 X86TargetLowering::LowerMemArgument(SDValue Chain,
1369 CallingConv::ID CallConv,
1370 const SmallVectorImpl<ISD::InputArg> &Ins,
1371 DebugLoc dl, SelectionDAG &DAG,
1372 const CCValAssign &VA,
1373 MachineFrameInfo *MFI,
1376 // Create the nodes corresponding to a load from this parameter slot.
1377 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1378 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1379 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1382 // If value is passed by pointer we have address passed instead of the value
1384 if (VA.getLocInfo() == CCValAssign::Indirect)
1385 ValVT = VA.getLocVT();
1387 ValVT = VA.getValVT();
1389 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1390 // changed with more analysis.
1391 // In case of tail call optimization mark all arguments mutable. Since they
1392 // could be overwritten by lowering of arguments in case of a tail call.
1393 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1394 VA.getLocMemOffset(), isImmutable, false);
1395 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1396 if (Flags.isByVal())
1398 return DAG.getLoad(ValVT, dl, Chain, FIN,
1399 PseudoSourceValue::getFixedStack(FI), 0);
1403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1404 CallingConv::ID CallConv,
1406 const SmallVectorImpl<ISD::InputArg> &Ins,
1409 SmallVectorImpl<SDValue> &InVals) {
1411 MachineFunction &MF = DAG.getMachineFunction();
1412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1414 const Function* Fn = MF.getFunction();
1415 if (Fn->hasExternalLinkage() &&
1416 Subtarget->isTargetCygMing() &&
1417 Fn->getName() == "main")
1418 FuncInfo->setForceFramePointer(true);
1420 // Decorate the function name.
1421 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1423 MachineFrameInfo *MFI = MF.getFrameInfo();
1424 bool Is64Bit = Subtarget->is64Bit();
1425 bool IsWin64 = Subtarget->isTargetWin64();
1427 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1428 "Var args not supported with calling convention fastcc");
1430 // Assign locations to all of the incoming arguments.
1431 SmallVector<CCValAssign, 16> ArgLocs;
1432 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1433 ArgLocs, *DAG.getContext());
1434 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1436 unsigned LastVal = ~0U;
1438 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1439 CCValAssign &VA = ArgLocs[i];
1440 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1442 assert(VA.getValNo() != LastVal &&
1443 "Don't support value assigned to multiple locs yet");
1444 LastVal = VA.getValNo();
1446 if (VA.isRegLoc()) {
1447 EVT RegVT = VA.getLocVT();
1448 TargetRegisterClass *RC = NULL;
1449 if (RegVT == MVT::i32)
1450 RC = X86::GR32RegisterClass;
1451 else if (Is64Bit && RegVT == MVT::i64)
1452 RC = X86::GR64RegisterClass;
1453 else if (RegVT == MVT::f32)
1454 RC = X86::FR32RegisterClass;
1455 else if (RegVT == MVT::f64)
1456 RC = X86::FR64RegisterClass;
1457 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1458 RC = X86::VR128RegisterClass;
1459 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1460 RC = X86::VR64RegisterClass;
1462 llvm_unreachable("Unknown argument type!");
1464 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1465 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1467 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1468 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1470 if (VA.getLocInfo() == CCValAssign::SExt)
1471 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1472 DAG.getValueType(VA.getValVT()));
1473 else if (VA.getLocInfo() == CCValAssign::ZExt)
1474 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1475 DAG.getValueType(VA.getValVT()));
1476 else if (VA.getLocInfo() == CCValAssign::BCvt)
1477 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1479 if (VA.isExtInLoc()) {
1480 // Handle MMX values passed in XMM regs.
1481 if (RegVT.isVector()) {
1482 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1483 ArgValue, DAG.getConstant(0, MVT::i64));
1484 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1486 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1489 assert(VA.isMemLoc());
1490 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1493 // If value is passed via pointer - do a load.
1494 if (VA.getLocInfo() == CCValAssign::Indirect)
1495 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1497 InVals.push_back(ArgValue);
1500 // The x86-64 ABI for returning structs by value requires that we copy
1501 // the sret argument into %rax for the return. Save the argument into
1502 // a virtual register so that we can access it from the return points.
1503 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1504 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1505 unsigned Reg = FuncInfo->getSRetReturnReg();
1507 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1508 FuncInfo->setSRetReturnReg(Reg);
1510 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1511 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1514 unsigned StackSize = CCInfo.getNextStackOffset();
1515 // align stack specially for tail calls
1516 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1519 // If the function takes variable number of arguments, make a frame index for
1520 // the start of the first vararg value... for expansion of llvm.va_start.
1522 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1523 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1526 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1528 // FIXME: We should really autogenerate these arrays
1529 static const unsigned GPR64ArgRegsWin64[] = {
1530 X86::RCX, X86::RDX, X86::R8, X86::R9
1532 static const unsigned XMMArgRegsWin64[] = {
1533 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1535 static const unsigned GPR64ArgRegs64Bit[] = {
1536 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1538 static const unsigned XMMArgRegs64Bit[] = {
1539 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1540 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1542 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1545 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1546 GPR64ArgRegs = GPR64ArgRegsWin64;
1547 XMMArgRegs = XMMArgRegsWin64;
1549 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1550 GPR64ArgRegs = GPR64ArgRegs64Bit;
1551 XMMArgRegs = XMMArgRegs64Bit;
1553 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1555 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1558 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1559 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1560 "SSE register cannot be used when SSE is disabled!");
1561 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1562 "SSE register cannot be used when SSE is disabled!");
1563 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1564 // Kernel mode asks for SSE to be disabled, so don't push them
1566 TotalNumXMMRegs = 0;
1568 // For X86-64, if there are vararg parameters that are passed via
1569 // registers, then we must store them to their spots on the stack so they
1570 // may be loaded by deferencing the result of va_next.
1571 VarArgsGPOffset = NumIntRegs * 8;
1572 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1573 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1574 TotalNumXMMRegs * 16, 16,
1577 // Store the integer parameter registers.
1578 SmallVector<SDValue, 8> MemOps;
1579 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1580 unsigned Offset = VarArgsGPOffset;
1581 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1582 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1583 DAG.getIntPtrConstant(Offset));
1584 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1585 X86::GR64RegisterClass);
1586 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1588 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1589 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1591 MemOps.push_back(Store);
1595 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1596 // Now store the XMM (fp + vector) parameter registers.
1597 SmallVector<SDValue, 11> SaveXMMOps;
1598 SaveXMMOps.push_back(Chain);
1600 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1601 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1602 SaveXMMOps.push_back(ALVal);
1604 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1605 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1607 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1608 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1609 X86::VR128RegisterClass);
1610 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1611 SaveXMMOps.push_back(Val);
1613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1615 &SaveXMMOps[0], SaveXMMOps.size()));
1618 if (!MemOps.empty())
1619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1620 &MemOps[0], MemOps.size());
1624 // Some CCs need callee pop.
1625 if (IsCalleePop(isVarArg, CallConv)) {
1626 BytesToPopOnReturn = StackSize; // Callee pops everything.
1627 BytesCallerReserves = 0;
1629 BytesToPopOnReturn = 0; // Callee pops nothing.
1630 // If this is an sret function, the return should pop the hidden pointer.
1631 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1632 BytesToPopOnReturn = 4;
1633 BytesCallerReserves = StackSize;
1637 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1638 if (CallConv == CallingConv::X86_FastCall)
1639 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1642 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1648 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1649 SDValue StackPtr, SDValue Arg,
1650 DebugLoc dl, SelectionDAG &DAG,
1651 const CCValAssign &VA,
1652 ISD::ArgFlagsTy Flags) {
1653 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1654 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1655 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1656 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1657 if (Flags.isByVal()) {
1658 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1660 return DAG.getStore(Chain, dl, Arg, PtrOff,
1661 PseudoSourceValue::getStack(), LocMemOffset);
1664 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1665 /// optimization is performed and it is required.
1667 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1668 SDValue &OutRetAddr,
1674 if (!IsTailCall || FPDiff==0) return Chain;
1676 // Adjust the Return address stack slot.
1677 EVT VT = getPointerTy();
1678 OutRetAddr = getReturnAddressFrameIndex(DAG);
1680 // Load the "old" Return address.
1681 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1682 return SDValue(OutRetAddr.getNode(), 1);
1685 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1686 /// optimization is performed and it is required (FPDiff!=0).
1688 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1689 SDValue Chain, SDValue RetAddrFrIdx,
1690 bool Is64Bit, int FPDiff, DebugLoc dl) {
1691 // Store the return address to the appropriate stack slot.
1692 if (!FPDiff) return Chain;
1693 // Calculate the new stack slot for the return address.
1694 int SlotSize = Is64Bit ? 8 : 4;
1695 int NewReturnAddrFI =
1696 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize,
1698 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1699 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1700 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1701 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1706 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1707 CallingConv::ID CallConv, bool isVarArg,
1709 const SmallVectorImpl<ISD::OutputArg> &Outs,
1710 const SmallVectorImpl<ISD::InputArg> &Ins,
1711 DebugLoc dl, SelectionDAG &DAG,
1712 SmallVectorImpl<SDValue> &InVals) {
1714 MachineFunction &MF = DAG.getMachineFunction();
1715 bool Is64Bit = Subtarget->is64Bit();
1716 bool IsStructRet = CallIsStructReturn(Outs);
1718 assert((!isTailCall ||
1719 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1720 "IsEligibleForTailCallOptimization missed a case!");
1721 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1722 "Var args not supported with calling convention fastcc");
1724 // Analyze operands of the call, assigning locations to each operand.
1725 SmallVector<CCValAssign, 16> ArgLocs;
1726 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1727 ArgLocs, *DAG.getContext());
1728 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1730 // Get a count of how many bytes are to be pushed on the stack.
1731 unsigned NumBytes = CCInfo.getNextStackOffset();
1732 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1733 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1737 // Lower arguments at fp - stackoffset + fpdiff.
1738 unsigned NumBytesCallerPushed =
1739 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1740 FPDiff = NumBytesCallerPushed - NumBytes;
1742 // Set the delta of movement of the returnaddr stackslot.
1743 // But only set if delta is greater than previous delta.
1744 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1745 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1748 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1750 SDValue RetAddrFrIdx;
1751 // Load return adress for tail calls.
1752 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1755 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1756 SmallVector<SDValue, 8> MemOpChains;
1759 // Walk the register/memloc assignments, inserting copies/loads. In the case
1760 // of tail call optimization arguments are handle later.
1761 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1762 CCValAssign &VA = ArgLocs[i];
1763 EVT RegVT = VA.getLocVT();
1764 SDValue Arg = Outs[i].Val;
1765 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1766 bool isByVal = Flags.isByVal();
1768 // Promote the value if needed.
1769 switch (VA.getLocInfo()) {
1770 default: llvm_unreachable("Unknown loc info!");
1771 case CCValAssign::Full: break;
1772 case CCValAssign::SExt:
1773 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1775 case CCValAssign::ZExt:
1776 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1778 case CCValAssign::AExt:
1779 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1780 // Special case: passing MMX values in XMM registers.
1781 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1782 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1783 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1785 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1787 case CCValAssign::BCvt:
1788 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1790 case CCValAssign::Indirect: {
1791 // Store the argument.
1792 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1793 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1794 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1795 PseudoSourceValue::getFixedStack(FI), 0);
1801 if (VA.isRegLoc()) {
1802 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1804 if (!isTailCall || (isTailCall && isByVal)) {
1805 assert(VA.isMemLoc());
1806 if (StackPtr.getNode() == 0)
1807 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1809 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1810 dl, DAG, VA, Flags));
1815 if (!MemOpChains.empty())
1816 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1817 &MemOpChains[0], MemOpChains.size());
1819 // Build a sequence of copy-to-reg nodes chained together with token chain
1820 // and flag operands which copy the outgoing args into registers.
1822 // Tail call byval lowering might overwrite argument registers so in case of
1823 // tail call optimization the copies to registers are lowered later.
1825 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1826 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1827 RegsToPass[i].second, InFlag);
1828 InFlag = Chain.getValue(1);
1832 if (Subtarget->isPICStyleGOT()) {
1833 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1836 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1837 DAG.getNode(X86ISD::GlobalBaseReg,
1838 DebugLoc::getUnknownLoc(),
1841 InFlag = Chain.getValue(1);
1843 // If we are tail calling and generating PIC/GOT style code load the
1844 // address of the callee into ECX. The value in ecx is used as target of
1845 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1846 // for tail calls on PIC/GOT architectures. Normally we would just put the
1847 // address of GOT into ebx and then call target@PLT. But for tail calls
1848 // ebx would be restored (since ebx is callee saved) before jumping to the
1851 // Note: The actual moving to ECX is done further down.
1852 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1853 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1854 !G->getGlobal()->hasProtectedVisibility())
1855 Callee = LowerGlobalAddress(Callee, DAG);
1856 else if (isa<ExternalSymbolSDNode>(Callee))
1857 Callee = LowerExternalSymbol(Callee, DAG);
1861 if (Is64Bit && isVarArg) {
1862 // From AMD64 ABI document:
1863 // For calls that may call functions that use varargs or stdargs
1864 // (prototype-less calls or calls to functions containing ellipsis (...) in
1865 // the declaration) %al is used as hidden argument to specify the number
1866 // of SSE registers used. The contents of %al do not need to match exactly
1867 // the number of registers, but must be an ubound on the number of SSE
1868 // registers used and is in the range 0 - 8 inclusive.
1870 // FIXME: Verify this on Win64
1871 // Count the number of XMM registers allocated.
1872 static const unsigned XMMArgRegs[] = {
1873 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1874 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1876 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1877 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1878 && "SSE registers cannot be used when SSE is disabled");
1880 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1881 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1882 InFlag = Chain.getValue(1);
1886 // For tail calls lower the arguments to the 'real' stack slot.
1888 // Force all the incoming stack arguments to be loaded from the stack
1889 // before any new outgoing arguments are stored to the stack, because the
1890 // outgoing stack slots may alias the incoming argument stack slots, and
1891 // the alias isn't otherwise explicit. This is slightly more conservative
1892 // than necessary, because it means that each store effectively depends
1893 // on every argument instead of just those arguments it would clobber.
1894 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1896 SmallVector<SDValue, 8> MemOpChains2;
1899 // Do not flag preceeding copytoreg stuff together with the following stuff.
1901 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1902 CCValAssign &VA = ArgLocs[i];
1903 if (!VA.isRegLoc()) {
1904 assert(VA.isMemLoc());
1905 SDValue Arg = Outs[i].Val;
1906 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1907 // Create frame index.
1908 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1909 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1910 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1911 FIN = DAG.getFrameIndex(FI, getPointerTy());
1913 if (Flags.isByVal()) {
1914 // Copy relative to framepointer.
1915 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1916 if (StackPtr.getNode() == 0)
1917 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1919 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1921 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1925 // Store relative to framepointer.
1926 MemOpChains2.push_back(
1927 DAG.getStore(ArgChain, dl, Arg, FIN,
1928 PseudoSourceValue::getFixedStack(FI), 0));
1933 if (!MemOpChains2.empty())
1934 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1935 &MemOpChains2[0], MemOpChains2.size());
1937 // Copy arguments to their registers.
1938 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1939 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1940 RegsToPass[i].second, InFlag);
1941 InFlag = Chain.getValue(1);
1945 // Store the return address to the appropriate stack slot.
1946 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1950 bool WasGlobalOrExternal = false;
1951 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
1952 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
1953 // In the 64-bit large code model, we have to make all calls
1954 // through a register, since the call instruction's 32-bit
1955 // pc-relative offset may not be large enough to hold the whole
1957 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1958 WasGlobalOrExternal = true;
1959 // If the callee is a GlobalAddress node (quite common, every direct call
1960 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
1963 // We should use extra load for direct calls to dllimported functions in
1965 GlobalValue *GV = G->getGlobal();
1966 if (!GV->hasDLLImportLinkage()) {
1967 unsigned char OpFlags = 0;
1969 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1970 // external symbols most go through the PLT in PIC mode. If the symbol
1971 // has hidden or protected visibility, or if it is static or local, then
1972 // we don't need to use the PLT - we can directly call it.
1973 if (Subtarget->isTargetELF() &&
1974 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1975 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1976 OpFlags = X86II::MO_PLT;
1977 } else if (Subtarget->isPICStyleStubAny() &&
1978 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1979 Subtarget->getDarwinVers() < 9) {
1980 // PC-relative references to external symbols should go through $stub,
1981 // unless we're building with the leopard linker or later, which
1982 // automatically synthesizes these stubs.
1983 OpFlags = X86II::MO_DARWIN_STUB;
1986 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1987 G->getOffset(), OpFlags);
1989 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1990 WasGlobalOrExternal = true;
1991 unsigned char OpFlags = 0;
1993 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1994 // symbols should go through the PLT.
1995 if (Subtarget->isTargetELF() &&
1996 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1997 OpFlags = X86II::MO_PLT;
1998 } else if (Subtarget->isPICStyleStubAny() &&
1999 Subtarget->getDarwinVers() < 9) {
2000 // PC-relative references to external symbols should go through $stub,
2001 // unless we're building with the leopard linker or later, which
2002 // automatically synthesizes these stubs.
2003 OpFlags = X86II::MO_DARWIN_STUB;
2006 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2010 if (isTailCall && !WasGlobalOrExternal) {
2011 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2013 Chain = DAG.getCopyToReg(Chain, dl,
2014 DAG.getRegister(Opc, getPointerTy()),
2016 Callee = DAG.getRegister(Opc, getPointerTy());
2017 // Add register as live out.
2018 MF.getRegInfo().addLiveOut(Opc);
2021 // Returns a chain & a flag for retval copy to use.
2022 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2023 SmallVector<SDValue, 8> Ops;
2026 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2027 DAG.getIntPtrConstant(0, true), InFlag);
2028 InFlag = Chain.getValue(1);
2031 Ops.push_back(Chain);
2032 Ops.push_back(Callee);
2035 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2037 // Add argument registers to the end of the list so that they are known live
2039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2040 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2041 RegsToPass[i].second.getValueType()));
2043 // Add an implicit use GOT pointer in EBX.
2044 if (!isTailCall && Subtarget->isPICStyleGOT())
2045 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2047 // Add an implicit use of AL for x86 vararg functions.
2048 if (Is64Bit && isVarArg)
2049 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2051 if (InFlag.getNode())
2052 Ops.push_back(InFlag);
2055 // If this is the first return lowered for this function, add the regs
2056 // to the liveout set for the function.
2057 if (MF.getRegInfo().liveout_empty()) {
2058 SmallVector<CCValAssign, 16> RVLocs;
2059 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2061 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2062 for (unsigned i = 0; i != RVLocs.size(); ++i)
2063 if (RVLocs[i].isRegLoc())
2064 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2067 assert(((Callee.getOpcode() == ISD::Register &&
2068 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2069 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2070 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2071 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2072 "Expecting an global address, external symbol, or register");
2074 return DAG.getNode(X86ISD::TC_RETURN, dl,
2075 NodeTys, &Ops[0], Ops.size());
2078 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2079 InFlag = Chain.getValue(1);
2081 // Create the CALLSEQ_END node.
2082 unsigned NumBytesForCalleeToPush;
2083 if (IsCalleePop(isVarArg, CallConv))
2084 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2085 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2086 // If this is is a call to a struct-return function, the callee
2087 // pops the hidden struct pointer, so we have to push it back.
2088 // This is common for Darwin/X86, Linux & Mingw32 targets.
2089 NumBytesForCalleeToPush = 4;
2091 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2093 // Returns a flag for retval copy to use.
2094 Chain = DAG.getCALLSEQ_END(Chain,
2095 DAG.getIntPtrConstant(NumBytes, true),
2096 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2099 InFlag = Chain.getValue(1);
2101 // Handle result values, copying them out of physregs into vregs that we
2103 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2104 Ins, dl, DAG, InVals);
2108 //===----------------------------------------------------------------------===//
2109 // Fast Calling Convention (tail call) implementation
2110 //===----------------------------------------------------------------------===//
2112 // Like std call, callee cleans arguments, convention except that ECX is
2113 // reserved for storing the tail called function address. Only 2 registers are
2114 // free for argument passing (inreg). Tail call optimization is performed
2116 // * tailcallopt is enabled
2117 // * caller/callee are fastcc
2118 // On X86_64 architecture with GOT-style position independent code only local
2119 // (within module) calls are supported at the moment.
2120 // To keep the stack aligned according to platform abi the function
2121 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2122 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2123 // If a tail called function callee has more arguments than the caller the
2124 // caller needs to make sure that there is room to move the RETADDR to. This is
2125 // achieved by reserving an area the size of the argument delta right after the
2126 // original REtADDR, but before the saved framepointer or the spilled registers
2127 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2139 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2140 /// for a 16 byte align requirement.
2141 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2142 SelectionDAG& DAG) {
2143 MachineFunction &MF = DAG.getMachineFunction();
2144 const TargetMachine &TM = MF.getTarget();
2145 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2146 unsigned StackAlignment = TFI.getStackAlignment();
2147 uint64_t AlignMask = StackAlignment - 1;
2148 int64_t Offset = StackSize;
2149 uint64_t SlotSize = TD->getPointerSize();
2150 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2151 // Number smaller than 12 so just add the difference.
2152 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2154 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2155 Offset = ((~AlignMask) & Offset) + StackAlignment +
2156 (StackAlignment-SlotSize);
2161 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2162 /// for tail call optimization. Targets which want to do tail call
2163 /// optimization should implement this function.
2165 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2166 CallingConv::ID CalleeCC,
2168 const SmallVectorImpl<ISD::InputArg> &Ins,
2169 SelectionDAG& DAG) const {
2170 MachineFunction &MF = DAG.getMachineFunction();
2171 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2172 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2176 X86TargetLowering::createFastISel(MachineFunction &mf,
2177 MachineModuleInfo *mmo,
2179 DenseMap<const Value *, unsigned> &vm,
2180 DenseMap<const BasicBlock *,
2181 MachineBasicBlock *> &bm,
2182 DenseMap<const AllocaInst *, int> &am
2184 , SmallSet<Instruction*, 8> &cil
2187 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2195 //===----------------------------------------------------------------------===//
2196 // Other Lowering Hooks
2197 //===----------------------------------------------------------------------===//
2200 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2201 MachineFunction &MF = DAG.getMachineFunction();
2202 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2203 int ReturnAddrIndex = FuncInfo->getRAIndex();
2205 if (ReturnAddrIndex == 0) {
2206 // Set up a frame object for the return address.
2207 uint64_t SlotSize = TD->getPointerSize();
2208 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2210 FuncInfo->setRAIndex(ReturnAddrIndex);
2213 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2217 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2218 bool hasSymbolicDisplacement) {
2219 // Offset should fit into 32 bit immediate field.
2220 if (!isInt32(Offset))
2223 // If we don't have a symbolic displacement - we don't have any extra
2225 if (!hasSymbolicDisplacement)
2228 // FIXME: Some tweaks might be needed for medium code model.
2229 if (M != CodeModel::Small && M != CodeModel::Kernel)
2232 // For small code model we assume that latest object is 16MB before end of 31
2233 // bits boundary. We may also accept pretty large negative constants knowing
2234 // that all objects are in the positive half of address space.
2235 if (M == CodeModel::Small && Offset < 16*1024*1024)
2238 // For kernel code model we know that all object resist in the negative half
2239 // of 32bits address space. We may not accept negative offsets, since they may
2240 // be just off and we may accept pretty large positive ones.
2241 if (M == CodeModel::Kernel && Offset > 0)
2247 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2248 /// specific condition code, returning the condition code and the LHS/RHS of the
2249 /// comparison to make.
2250 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2251 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2253 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2254 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2255 // X > -1 -> X == 0, jump !sign.
2256 RHS = DAG.getConstant(0, RHS.getValueType());
2257 return X86::COND_NS;
2258 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2259 // X < 0 -> X == 0, jump on sign.
2261 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2263 RHS = DAG.getConstant(0, RHS.getValueType());
2264 return X86::COND_LE;
2268 switch (SetCCOpcode) {
2269 default: llvm_unreachable("Invalid integer condition!");
2270 case ISD::SETEQ: return X86::COND_E;
2271 case ISD::SETGT: return X86::COND_G;
2272 case ISD::SETGE: return X86::COND_GE;
2273 case ISD::SETLT: return X86::COND_L;
2274 case ISD::SETLE: return X86::COND_LE;
2275 case ISD::SETNE: return X86::COND_NE;
2276 case ISD::SETULT: return X86::COND_B;
2277 case ISD::SETUGT: return X86::COND_A;
2278 case ISD::SETULE: return X86::COND_BE;
2279 case ISD::SETUGE: return X86::COND_AE;
2283 // First determine if it is required or is profitable to flip the operands.
2285 // If LHS is a foldable load, but RHS is not, flip the condition.
2286 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2287 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2288 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2289 std::swap(LHS, RHS);
2292 switch (SetCCOpcode) {
2298 std::swap(LHS, RHS);
2302 // On a floating point condition, the flags are set as follows:
2304 // 0 | 0 | 0 | X > Y
2305 // 0 | 0 | 1 | X < Y
2306 // 1 | 0 | 0 | X == Y
2307 // 1 | 1 | 1 | unordered
2308 switch (SetCCOpcode) {
2309 default: llvm_unreachable("Condcode should be pre-legalized away");
2311 case ISD::SETEQ: return X86::COND_E;
2312 case ISD::SETOLT: // flipped
2314 case ISD::SETGT: return X86::COND_A;
2315 case ISD::SETOLE: // flipped
2317 case ISD::SETGE: return X86::COND_AE;
2318 case ISD::SETUGT: // flipped
2320 case ISD::SETLT: return X86::COND_B;
2321 case ISD::SETUGE: // flipped
2323 case ISD::SETLE: return X86::COND_BE;
2325 case ISD::SETNE: return X86::COND_NE;
2326 case ISD::SETUO: return X86::COND_P;
2327 case ISD::SETO: return X86::COND_NP;
2329 case ISD::SETUNE: return X86::COND_INVALID;
2333 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2334 /// code. Current x86 isa includes the following FP cmov instructions:
2335 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2336 static bool hasFPCMov(unsigned X86CC) {
2352 /// isFPImmLegal - Returns true if the target can instruction select the
2353 /// specified FP immediate natively. If false, the legalizer will
2354 /// materialize the FP immediate as a load from a constant pool.
2355 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2356 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2357 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2363 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2364 /// the specified range (L, H].
2365 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2366 return (Val < 0) || (Val >= Low && Val < Hi);
2369 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2370 /// specified value.
2371 static bool isUndefOrEqual(int Val, int CmpVal) {
2372 if (Val < 0 || Val == CmpVal)
2377 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2378 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2379 /// the second operand.
2380 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2381 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2382 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2383 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2384 return (Mask[0] < 2 && Mask[1] < 2);
2388 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2389 SmallVector<int, 8> M;
2391 return ::isPSHUFDMask(M, N->getValueType(0));
2394 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2395 /// is suitable for input to PSHUFHW.
2396 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2397 if (VT != MVT::v8i16)
2400 // Lower quadword copied in order or undef.
2401 for (int i = 0; i != 4; ++i)
2402 if (Mask[i] >= 0 && Mask[i] != i)
2405 // Upper quadword shuffled.
2406 for (int i = 4; i != 8; ++i)
2407 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2413 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2414 SmallVector<int, 8> M;
2416 return ::isPSHUFHWMask(M, N->getValueType(0));
2419 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2420 /// is suitable for input to PSHUFLW.
2421 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2422 if (VT != MVT::v8i16)
2425 // Upper quadword copied in order.
2426 for (int i = 4; i != 8; ++i)
2427 if (Mask[i] >= 0 && Mask[i] != i)
2430 // Lower quadword shuffled.
2431 for (int i = 0; i != 4; ++i)
2438 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2439 SmallVector<int, 8> M;
2441 return ::isPSHUFLWMask(M, N->getValueType(0));
2444 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2445 /// is suitable for input to PALIGNR.
2446 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2448 int i, e = VT.getVectorNumElements();
2450 // Do not handle v2i64 / v2f64 shuffles with palignr.
2451 if (e < 4 || !hasSSSE3)
2454 for (i = 0; i != e; ++i)
2458 // All undef, not a palignr.
2462 // Determine if it's ok to perform a palignr with only the LHS, since we
2463 // don't have access to the actual shuffle elements to see if RHS is undef.
2464 bool Unary = Mask[i] < (int)e;
2465 bool NeedsUnary = false;
2467 int s = Mask[i] - i;
2469 // Check the rest of the elements to see if they are consecutive.
2470 for (++i; i != e; ++i) {
2475 Unary = Unary && (m < (int)e);
2476 NeedsUnary = NeedsUnary || (m < s);
2478 if (NeedsUnary && !Unary)
2480 if (Unary && m != ((s+i) & (e-1)))
2482 if (!Unary && m != (s+i))
2488 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2489 SmallVector<int, 8> M;
2491 return ::isPALIGNRMask(M, N->getValueType(0), true);
2494 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2495 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2496 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2497 int NumElems = VT.getVectorNumElements();
2498 if (NumElems != 2 && NumElems != 4)
2501 int Half = NumElems / 2;
2502 for (int i = 0; i < Half; ++i)
2503 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2505 for (int i = Half; i < NumElems; ++i)
2506 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2512 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2513 SmallVector<int, 8> M;
2515 return ::isSHUFPMask(M, N->getValueType(0));
2518 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2519 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2520 /// half elements to come from vector 1 (which would equal the dest.) and
2521 /// the upper half to come from vector 2.
2522 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2523 int NumElems = VT.getVectorNumElements();
2525 if (NumElems != 2 && NumElems != 4)
2528 int Half = NumElems / 2;
2529 for (int i = 0; i < Half; ++i)
2530 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2532 for (int i = Half; i < NumElems; ++i)
2533 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2538 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2539 SmallVector<int, 8> M;
2541 return isCommutedSHUFPMask(M, N->getValueType(0));
2544 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2545 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2546 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2547 if (N->getValueType(0).getVectorNumElements() != 4)
2550 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2551 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2552 isUndefOrEqual(N->getMaskElt(1), 7) &&
2553 isUndefOrEqual(N->getMaskElt(2), 2) &&
2554 isUndefOrEqual(N->getMaskElt(3), 3);
2557 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2558 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2560 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2561 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2566 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2567 isUndefOrEqual(N->getMaskElt(1), 3) &&
2568 isUndefOrEqual(N->getMaskElt(2), 2) &&
2569 isUndefOrEqual(N->getMaskElt(3), 3);
2572 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2573 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2574 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2575 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2577 if (NumElems != 2 && NumElems != 4)
2580 for (unsigned i = 0; i < NumElems/2; ++i)
2581 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2584 for (unsigned i = NumElems/2; i < NumElems; ++i)
2585 if (!isUndefOrEqual(N->getMaskElt(i), i))
2591 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2592 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2593 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2594 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2596 if (NumElems != 2 && NumElems != 4)
2599 for (unsigned i = 0; i < NumElems/2; ++i)
2600 if (!isUndefOrEqual(N->getMaskElt(i), i))
2603 for (unsigned i = 0; i < NumElems/2; ++i)
2604 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2610 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2611 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2612 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2613 bool V2IsSplat = false) {
2614 int NumElts = VT.getVectorNumElements();
2615 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2618 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2620 int BitI1 = Mask[i+1];
2621 if (!isUndefOrEqual(BitI, j))
2624 if (!isUndefOrEqual(BitI1, NumElts))
2627 if (!isUndefOrEqual(BitI1, j + NumElts))
2634 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2635 SmallVector<int, 8> M;
2637 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2640 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2641 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2642 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2643 bool V2IsSplat = false) {
2644 int NumElts = VT.getVectorNumElements();
2645 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2648 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2650 int BitI1 = Mask[i+1];
2651 if (!isUndefOrEqual(BitI, j + NumElts/2))
2654 if (isUndefOrEqual(BitI1, NumElts))
2657 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2664 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2665 SmallVector<int, 8> M;
2667 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2670 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2671 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2673 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2674 int NumElems = VT.getVectorNumElements();
2675 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2678 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2680 int BitI1 = Mask[i+1];
2681 if (!isUndefOrEqual(BitI, j))
2683 if (!isUndefOrEqual(BitI1, j))
2689 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2690 SmallVector<int, 8> M;
2692 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2695 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2696 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2698 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2699 int NumElems = VT.getVectorNumElements();
2700 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2703 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2705 int BitI1 = Mask[i+1];
2706 if (!isUndefOrEqual(BitI, j))
2708 if (!isUndefOrEqual(BitI1, j))
2714 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2715 SmallVector<int, 8> M;
2717 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2720 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2721 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2722 /// MOVSD, and MOVD, i.e. setting the lowest element.
2723 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2724 if (VT.getVectorElementType().getSizeInBits() < 32)
2727 int NumElts = VT.getVectorNumElements();
2729 if (!isUndefOrEqual(Mask[0], NumElts))
2732 for (int i = 1; i < NumElts; ++i)
2733 if (!isUndefOrEqual(Mask[i], i))
2739 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2740 SmallVector<int, 8> M;
2742 return ::isMOVLMask(M, N->getValueType(0));
2745 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2746 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2747 /// element of vector 2 and the other elements to come from vector 1 in order.
2748 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2749 bool V2IsSplat = false, bool V2IsUndef = false) {
2750 int NumOps = VT.getVectorNumElements();
2751 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2754 if (!isUndefOrEqual(Mask[0], 0))
2757 for (int i = 1; i < NumOps; ++i)
2758 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2759 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2760 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2766 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2767 bool V2IsUndef = false) {
2768 SmallVector<int, 8> M;
2770 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2773 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2774 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2775 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2776 if (N->getValueType(0).getVectorNumElements() != 4)
2779 // Expect 1, 1, 3, 3
2780 for (unsigned i = 0; i < 2; ++i) {
2781 int Elt = N->getMaskElt(i);
2782 if (Elt >= 0 && Elt != 1)
2787 for (unsigned i = 2; i < 4; ++i) {
2788 int Elt = N->getMaskElt(i);
2789 if (Elt >= 0 && Elt != 3)
2794 // Don't use movshdup if it can be done with a shufps.
2795 // FIXME: verify that matching u, u, 3, 3 is what we want.
2799 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2800 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2801 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2802 if (N->getValueType(0).getVectorNumElements() != 4)
2805 // Expect 0, 0, 2, 2
2806 for (unsigned i = 0; i < 2; ++i)
2807 if (N->getMaskElt(i) > 0)
2811 for (unsigned i = 2; i < 4; ++i) {
2812 int Elt = N->getMaskElt(i);
2813 if (Elt >= 0 && Elt != 2)
2818 // Don't use movsldup if it can be done with a shufps.
2822 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2823 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2824 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2825 int e = N->getValueType(0).getVectorNumElements() / 2;
2827 for (int i = 0; i < e; ++i)
2828 if (!isUndefOrEqual(N->getMaskElt(i), i))
2830 for (int i = 0; i < e; ++i)
2831 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2836 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2837 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2838 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2840 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2842 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2844 for (int i = 0; i < NumOperands; ++i) {
2845 int Val = SVOp->getMaskElt(NumOperands-i-1);
2846 if (Val < 0) Val = 0;
2847 if (Val >= NumOperands) Val -= NumOperands;
2849 if (i != NumOperands - 1)
2855 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2856 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2857 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2860 // 8 nodes, but we only care about the last 4.
2861 for (unsigned i = 7; i >= 4; --i) {
2862 int Val = SVOp->getMaskElt(i);
2871 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2872 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2873 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2876 // 8 nodes, but we only care about the first 4.
2877 for (int i = 3; i >= 0; --i) {
2878 int Val = SVOp->getMaskElt(i);
2887 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2888 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2889 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2890 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2891 EVT VVT = N->getValueType(0);
2892 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2896 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2897 Val = SVOp->getMaskElt(i);
2901 return (Val - i) * EltSize;
2904 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2906 bool X86::isZeroNode(SDValue Elt) {
2907 return ((isa<ConstantSDNode>(Elt) &&
2908 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2909 (isa<ConstantFPSDNode>(Elt) &&
2910 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2913 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2914 /// their permute mask.
2915 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2916 SelectionDAG &DAG) {
2917 EVT VT = SVOp->getValueType(0);
2918 unsigned NumElems = VT.getVectorNumElements();
2919 SmallVector<int, 8> MaskVec;
2921 for (unsigned i = 0; i != NumElems; ++i) {
2922 int idx = SVOp->getMaskElt(i);
2924 MaskVec.push_back(idx);
2925 else if (idx < (int)NumElems)
2926 MaskVec.push_back(idx + NumElems);
2928 MaskVec.push_back(idx - NumElems);
2930 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2931 SVOp->getOperand(0), &MaskVec[0]);
2934 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2935 /// the two vector operands have swapped position.
2936 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2937 unsigned NumElems = VT.getVectorNumElements();
2938 for (unsigned i = 0; i != NumElems; ++i) {
2942 else if (idx < (int)NumElems)
2943 Mask[i] = idx + NumElems;
2945 Mask[i] = idx - NumElems;
2949 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2950 /// match movhlps. The lower half elements should come from upper half of
2951 /// V1 (and in order), and the upper half elements should come from the upper
2952 /// half of V2 (and in order).
2953 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2954 if (Op->getValueType(0).getVectorNumElements() != 4)
2956 for (unsigned i = 0, e = 2; i != e; ++i)
2957 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2959 for (unsigned i = 2; i != 4; ++i)
2960 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2965 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2966 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2968 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2969 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2971 N = N->getOperand(0).getNode();
2972 if (!ISD::isNON_EXTLoad(N))
2975 *LD = cast<LoadSDNode>(N);
2979 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2980 /// match movlp{s|d}. The lower half elements should come from lower half of
2981 /// V1 (and in order), and the upper half elements should come from the upper
2982 /// half of V2 (and in order). And since V1 will become the source of the
2983 /// MOVLP, it must be either a vector load or a scalar load to vector.
2984 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2985 ShuffleVectorSDNode *Op) {
2986 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2988 // Is V2 is a vector load, don't do this transformation. We will try to use
2989 // load folding shufps op.
2990 if (ISD::isNON_EXTLoad(V2))
2993 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2995 if (NumElems != 2 && NumElems != 4)
2997 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2998 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3000 for (unsigned i = NumElems/2; i != NumElems; ++i)
3001 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3006 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3008 static bool isSplatVector(SDNode *N) {
3009 if (N->getOpcode() != ISD::BUILD_VECTOR)
3012 SDValue SplatValue = N->getOperand(0);
3013 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3014 if (N->getOperand(i) != SplatValue)
3019 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3020 /// to an zero vector.
3021 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3022 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3023 SDValue V1 = N->getOperand(0);
3024 SDValue V2 = N->getOperand(1);
3025 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3026 for (unsigned i = 0; i != NumElems; ++i) {
3027 int Idx = N->getMaskElt(i);
3028 if (Idx >= (int)NumElems) {
3029 unsigned Opc = V2.getOpcode();
3030 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3032 if (Opc != ISD::BUILD_VECTOR ||
3033 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3035 } else if (Idx >= 0) {
3036 unsigned Opc = V1.getOpcode();
3037 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3039 if (Opc != ISD::BUILD_VECTOR ||
3040 !X86::isZeroNode(V1.getOperand(Idx)))
3047 /// getZeroVector - Returns a vector of specified type with all zero elements.
3049 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3051 assert(VT.isVector() && "Expected a vector type");
3053 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3054 // type. This ensures they get CSE'd.
3056 if (VT.getSizeInBits() == 64) { // MMX
3057 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3058 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3059 } else if (HasSSE2) { // SSE2
3060 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3061 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3063 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3064 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3066 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3069 /// getOnesVector - Returns a vector of specified type with all bits set.
3071 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3072 assert(VT.isVector() && "Expected a vector type");
3074 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3075 // type. This ensures they get CSE'd.
3076 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3078 if (VT.getSizeInBits() == 64) // MMX
3079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3081 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3082 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3086 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3087 /// that point to V2 points to its first element.
3088 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3089 EVT VT = SVOp->getValueType(0);
3090 unsigned NumElems = VT.getVectorNumElements();
3092 bool Changed = false;
3093 SmallVector<int, 8> MaskVec;
3094 SVOp->getMask(MaskVec);
3096 for (unsigned i = 0; i != NumElems; ++i) {
3097 if (MaskVec[i] > (int)NumElems) {
3098 MaskVec[i] = NumElems;
3103 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3104 SVOp->getOperand(1), &MaskVec[0]);
3105 return SDValue(SVOp, 0);
3108 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3109 /// operation of specified width.
3110 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3112 unsigned NumElems = VT.getVectorNumElements();
3113 SmallVector<int, 8> Mask;
3114 Mask.push_back(NumElems);
3115 for (unsigned i = 1; i != NumElems; ++i)
3117 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3120 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3121 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3123 unsigned NumElems = VT.getVectorNumElements();
3124 SmallVector<int, 8> Mask;
3125 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3127 Mask.push_back(i + NumElems);
3129 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3132 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3133 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3135 unsigned NumElems = VT.getVectorNumElements();
3136 unsigned Half = NumElems/2;
3137 SmallVector<int, 8> Mask;
3138 for (unsigned i = 0; i != Half; ++i) {
3139 Mask.push_back(i + Half);
3140 Mask.push_back(i + NumElems + Half);
3142 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3145 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3146 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3148 if (SV->getValueType(0).getVectorNumElements() <= 4)
3149 return SDValue(SV, 0);
3151 EVT PVT = MVT::v4f32;
3152 EVT VT = SV->getValueType(0);
3153 DebugLoc dl = SV->getDebugLoc();
3154 SDValue V1 = SV->getOperand(0);
3155 int NumElems = VT.getVectorNumElements();
3156 int EltNo = SV->getSplatIndex();
3158 // unpack elements to the correct location
3159 while (NumElems > 4) {
3160 if (EltNo < NumElems/2) {
3161 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3163 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3164 EltNo -= NumElems/2;
3169 // Perform the splat.
3170 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3171 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3172 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3173 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3176 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3177 /// vector of zero or undef vector. This produces a shuffle where the low
3178 /// element of V2 is swizzled into the zero/undef vector, landing at element
3179 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3180 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3181 bool isZero, bool HasSSE2,
3182 SelectionDAG &DAG) {
3183 EVT VT = V2.getValueType();
3185 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3186 unsigned NumElems = VT.getVectorNumElements();
3187 SmallVector<int, 16> MaskVec;
3188 for (unsigned i = 0; i != NumElems; ++i)
3189 // If this is the insertion idx, put the low elt of V2 here.
3190 MaskVec.push_back(i == Idx ? NumElems : i);
3191 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3194 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3195 /// a shuffle that is zero.
3197 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3198 bool Low, SelectionDAG &DAG) {
3199 unsigned NumZeros = 0;
3200 for (int i = 0; i < NumElems; ++i) {
3201 unsigned Index = Low ? i : NumElems-i-1;
3202 int Idx = SVOp->getMaskElt(Index);
3207 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3208 if (Elt.getNode() && X86::isZeroNode(Elt))
3216 /// isVectorShift - Returns true if the shuffle can be implemented as a
3217 /// logical left or right shift of a vector.
3218 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3219 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3220 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3221 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3224 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3227 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3231 bool SeenV1 = false;
3232 bool SeenV2 = false;
3233 for (int i = NumZeros; i < NumElems; ++i) {
3234 int Val = isLeft ? (i - NumZeros) : i;
3235 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3247 if (SeenV1 && SeenV2)
3250 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3256 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3258 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3259 unsigned NumNonZero, unsigned NumZero,
3260 SelectionDAG &DAG, TargetLowering &TLI) {
3264 DebugLoc dl = Op.getDebugLoc();
3267 for (unsigned i = 0; i < 16; ++i) {
3268 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3269 if (ThisIsNonZero && First) {
3271 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3273 V = DAG.getUNDEF(MVT::v8i16);
3278 SDValue ThisElt(0, 0), LastElt(0, 0);
3279 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3280 if (LastIsNonZero) {
3281 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3282 MVT::i16, Op.getOperand(i-1));
3284 if (ThisIsNonZero) {
3285 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3286 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3287 ThisElt, DAG.getConstant(8, MVT::i8));
3289 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3293 if (ThisElt.getNode())
3294 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3295 DAG.getIntPtrConstant(i/2));
3299 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3302 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3304 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3305 unsigned NumNonZero, unsigned NumZero,
3306 SelectionDAG &DAG, TargetLowering &TLI) {
3310 DebugLoc dl = Op.getDebugLoc();
3313 for (unsigned i = 0; i < 8; ++i) {
3314 bool isNonZero = (NonZeros & (1 << i)) != 0;
3318 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3320 V = DAG.getUNDEF(MVT::v8i16);
3323 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3324 MVT::v8i16, V, Op.getOperand(i),
3325 DAG.getIntPtrConstant(i));
3332 /// getVShift - Return a vector logical shift node.
3334 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3335 unsigned NumBits, SelectionDAG &DAG,
3336 const TargetLowering &TLI, DebugLoc dl) {
3337 bool isMMX = VT.getSizeInBits() == 64;
3338 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3339 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3340 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3341 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3342 DAG.getNode(Opc, dl, ShVT, SrcOp,
3343 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3347 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3348 SelectionDAG &DAG) {
3350 // Check if the scalar load can be widened into a vector load. And if
3351 // the address is "base + cst" see if the cst can be "absorbed" into
3352 // the shuffle mask.
3353 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3354 SDValue Ptr = LD->getBasePtr();
3355 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3357 EVT PVT = LD->getValueType(0);
3358 if (PVT != MVT::i32 && PVT != MVT::f32)
3363 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3364 FI = FINode->getIndex();
3366 } else if (Ptr.getOpcode() == ISD::ADD &&
3367 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3368 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3369 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3370 Offset = Ptr.getConstantOperandVal(1);
3371 Ptr = Ptr.getOperand(0);
3376 SDValue Chain = LD->getChain();
3377 // Make sure the stack object alignment is at least 16.
3378 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3379 if (DAG.InferPtrAlignment(Ptr) < 16) {
3380 if (MFI->isFixedObjectIndex(FI)) {
3381 // Can't change the alignment. Reference stack + offset explicitly
3382 // if stack pointer is at least 16-byte aligned.
3383 unsigned StackAlign = Subtarget->getStackAlignment();
3384 if (StackAlign < 16)
3386 Offset = MFI->getObjectOffset(FI) + Offset;
3387 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
3389 Ptr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3390 DAG.getConstant(Offset & ~15, getPointerTy()));
3393 MFI->setObjectAlignment(FI, 16);
3397 // (Offset % 16) must be multiple of 4. Then address is then
3398 // Ptr + (Offset & ~15).
3401 if ((Offset % 16) & 3)
3403 int64_t StartOffset = Offset & ~15;
3405 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3406 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3408 int EltNo = (Offset - StartOffset) >> 2;
3409 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3410 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3411 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3412 // Canonicalize it to a v4i32 shuffle.
3413 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3414 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3415 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3416 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3423 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3424 DebugLoc dl = Op.getDebugLoc();
3425 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3426 if (ISD::isBuildVectorAllZeros(Op.getNode())
3427 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3428 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3429 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3430 // eliminated on x86-32 hosts.
3431 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3434 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3435 return getOnesVector(Op.getValueType(), DAG, dl);
3436 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3439 EVT VT = Op.getValueType();
3440 EVT ExtVT = VT.getVectorElementType();
3441 unsigned EVTBits = ExtVT.getSizeInBits();
3443 unsigned NumElems = Op.getNumOperands();
3444 unsigned NumZero = 0;
3445 unsigned NumNonZero = 0;
3446 unsigned NonZeros = 0;
3447 bool IsAllConstants = true;
3448 SmallSet<SDValue, 8> Values;
3449 for (unsigned i = 0; i < NumElems; ++i) {
3450 SDValue Elt = Op.getOperand(i);
3451 if (Elt.getOpcode() == ISD::UNDEF)
3454 if (Elt.getOpcode() != ISD::Constant &&
3455 Elt.getOpcode() != ISD::ConstantFP)
3456 IsAllConstants = false;
3457 if (X86::isZeroNode(Elt))
3460 NonZeros |= (1 << i);
3465 if (NumNonZero == 0) {
3466 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3467 return DAG.getUNDEF(VT);
3470 // Special case for single non-zero, non-undef, element.
3471 if (NumNonZero == 1) {
3472 unsigned Idx = CountTrailingZeros_32(NonZeros);
3473 SDValue Item = Op.getOperand(Idx);
3475 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3476 // the value are obviously zero, truncate the value to i32 and do the
3477 // insertion that way. Only do this if the value is non-constant or if the
3478 // value is a constant being inserted into element 0. It is cheaper to do
3479 // a constant pool load than it is to do a movd + shuffle.
3480 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3481 (!IsAllConstants || Idx == 0)) {
3482 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3483 // Handle MMX and SSE both.
3484 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3485 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3487 // Truncate the value (which may itself be a constant) to i32, and
3488 // convert it to a vector with movd (S2V+shuffle to zero extend).
3489 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3490 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3491 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3492 Subtarget->hasSSE2(), DAG);
3494 // Now we have our 32-bit value zero extended in the low element of
3495 // a vector. If Idx != 0, swizzle it into place.
3497 SmallVector<int, 4> Mask;
3498 Mask.push_back(Idx);
3499 for (unsigned i = 1; i != VecElts; ++i)
3501 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3502 DAG.getUNDEF(Item.getValueType()),
3505 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3509 // If we have a constant or non-constant insertion into the low element of
3510 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3511 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3512 // depending on what the source datatype is.
3515 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3516 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3517 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3518 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3519 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3520 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3522 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3523 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3524 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3525 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3526 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3527 Subtarget->hasSSE2(), DAG);
3528 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3532 // Is it a vector logical left shift?
3533 if (NumElems == 2 && Idx == 1 &&
3534 X86::isZeroNode(Op.getOperand(0)) &&
3535 !X86::isZeroNode(Op.getOperand(1))) {
3536 unsigned NumBits = VT.getSizeInBits();
3537 return getVShift(true, VT,
3538 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3539 VT, Op.getOperand(1)),
3540 NumBits/2, DAG, *this, dl);
3543 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3546 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3547 // is a non-constant being inserted into an element other than the low one,
3548 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3549 // movd/movss) to move this into the low element, then shuffle it into
3551 if (EVTBits == 32) {
3552 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3554 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3555 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3556 Subtarget->hasSSE2(), DAG);
3557 SmallVector<int, 8> MaskVec;
3558 for (unsigned i = 0; i < NumElems; i++)
3559 MaskVec.push_back(i == Idx ? 0 : 1);
3560 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3564 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3565 if (Values.size() == 1) {
3566 if (EVTBits == 32) {
3567 // Instead of a shuffle like this:
3568 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3569 // Check if it's possible to issue this instead.
3570 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3571 unsigned Idx = CountTrailingZeros_32(NonZeros);
3572 SDValue Item = Op.getOperand(Idx);
3573 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3574 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3579 // A vector full of immediates; various special cases are already
3580 // handled, so this is best done with a single constant-pool load.
3584 // Let legalizer expand 2-wide build_vectors.
3585 if (EVTBits == 64) {
3586 if (NumNonZero == 1) {
3587 // One half is zero or undef.
3588 unsigned Idx = CountTrailingZeros_32(NonZeros);
3589 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3590 Op.getOperand(Idx));
3591 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3592 Subtarget->hasSSE2(), DAG);
3597 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3598 if (EVTBits == 8 && NumElems == 16) {
3599 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3601 if (V.getNode()) return V;
3604 if (EVTBits == 16 && NumElems == 8) {
3605 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3607 if (V.getNode()) return V;
3610 // If element VT is == 32 bits, turn it into a number of shuffles.
3611 SmallVector<SDValue, 8> V;
3613 if (NumElems == 4 && NumZero > 0) {
3614 for (unsigned i = 0; i < 4; ++i) {
3615 bool isZero = !(NonZeros & (1 << i));
3617 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3619 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3622 for (unsigned i = 0; i < 2; ++i) {
3623 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3626 V[i] = V[i*2]; // Must be a zero vector.
3629 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3632 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3635 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3640 SmallVector<int, 8> MaskVec;
3641 bool Reverse = (NonZeros & 0x3) == 2;
3642 for (unsigned i = 0; i < 2; ++i)
3643 MaskVec.push_back(Reverse ? 1-i : i);
3644 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3645 for (unsigned i = 0; i < 2; ++i)
3646 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3647 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3650 if (Values.size() > 2) {
3651 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3652 // values to be inserted is equal to the number of elements, in which case
3653 // use the unpack code below in the hopes of matching the consecutive elts
3654 // load merge pattern for shuffles.
3655 // FIXME: We could probably just check that here directly.
3656 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3657 getSubtarget()->hasSSE41()) {
3658 V[0] = DAG.getUNDEF(VT);
3659 for (unsigned i = 0; i < NumElems; ++i)
3660 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3661 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3662 Op.getOperand(i), DAG.getIntPtrConstant(i));
3665 // Expand into a number of unpckl*.
3667 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3668 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3669 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3670 for (unsigned i = 0; i < NumElems; ++i)
3671 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3673 while (NumElems != 0) {
3674 for (unsigned i = 0; i < NumElems; ++i)
3675 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3684 // v8i16 shuffles - Prefer shuffles in the following order:
3685 // 1. [all] pshuflw, pshufhw, optional move
3686 // 2. [ssse3] 1 x pshufb
3687 // 3. [ssse3] 2 x pshufb + 1 x por
3688 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3690 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3691 SelectionDAG &DAG, X86TargetLowering &TLI) {
3692 SDValue V1 = SVOp->getOperand(0);
3693 SDValue V2 = SVOp->getOperand(1);
3694 DebugLoc dl = SVOp->getDebugLoc();
3695 SmallVector<int, 8> MaskVals;
3697 // Determine if more than 1 of the words in each of the low and high quadwords
3698 // of the result come from the same quadword of one of the two inputs. Undef
3699 // mask values count as coming from any quadword, for better codegen.
3700 SmallVector<unsigned, 4> LoQuad(4);
3701 SmallVector<unsigned, 4> HiQuad(4);
3702 BitVector InputQuads(4);
3703 for (unsigned i = 0; i < 8; ++i) {
3704 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3705 int EltIdx = SVOp->getMaskElt(i);
3706 MaskVals.push_back(EltIdx);
3715 InputQuads.set(EltIdx / 4);
3718 int BestLoQuad = -1;
3719 unsigned MaxQuad = 1;
3720 for (unsigned i = 0; i < 4; ++i) {
3721 if (LoQuad[i] > MaxQuad) {
3723 MaxQuad = LoQuad[i];
3727 int BestHiQuad = -1;
3729 for (unsigned i = 0; i < 4; ++i) {
3730 if (HiQuad[i] > MaxQuad) {
3732 MaxQuad = HiQuad[i];
3736 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3737 // of the two input vectors, shuffle them into one input vector so only a
3738 // single pshufb instruction is necessary. If There are more than 2 input
3739 // quads, disable the next transformation since it does not help SSSE3.
3740 bool V1Used = InputQuads[0] || InputQuads[1];
3741 bool V2Used = InputQuads[2] || InputQuads[3];
3742 if (TLI.getSubtarget()->hasSSSE3()) {
3743 if (InputQuads.count() == 2 && V1Used && V2Used) {
3744 BestLoQuad = InputQuads.find_first();
3745 BestHiQuad = InputQuads.find_next(BestLoQuad);
3747 if (InputQuads.count() > 2) {
3753 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3754 // the shuffle mask. If a quad is scored as -1, that means that it contains
3755 // words from all 4 input quadwords.
3757 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3758 SmallVector<int, 8> MaskV;
3759 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3760 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3761 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3762 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3763 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3764 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3766 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3767 // source words for the shuffle, to aid later transformations.
3768 bool AllWordsInNewV = true;
3769 bool InOrder[2] = { true, true };
3770 for (unsigned i = 0; i != 8; ++i) {
3771 int idx = MaskVals[i];
3773 InOrder[i/4] = false;
3774 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3776 AllWordsInNewV = false;
3780 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3781 if (AllWordsInNewV) {
3782 for (int i = 0; i != 8; ++i) {
3783 int idx = MaskVals[i];
3786 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3787 if ((idx != i) && idx < 4)
3789 if ((idx != i) && idx > 3)
3798 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3799 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3800 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3801 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3802 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3806 // If we have SSSE3, and all words of the result are from 1 input vector,
3807 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3808 // is present, fall back to case 4.
3809 if (TLI.getSubtarget()->hasSSSE3()) {
3810 SmallVector<SDValue,16> pshufbMask;
3812 // If we have elements from both input vectors, set the high bit of the
3813 // shuffle mask element to zero out elements that come from V2 in the V1
3814 // mask, and elements that come from V1 in the V2 mask, so that the two
3815 // results can be OR'd together.
3816 bool TwoInputs = V1Used && V2Used;
3817 for (unsigned i = 0; i != 8; ++i) {
3818 int EltIdx = MaskVals[i] * 2;
3819 if (TwoInputs && (EltIdx >= 16)) {
3820 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3821 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3824 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3825 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3827 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3828 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3829 DAG.getNode(ISD::BUILD_VECTOR, dl,
3830 MVT::v16i8, &pshufbMask[0], 16));
3832 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3834 // Calculate the shuffle mask for the second input, shuffle it, and
3835 // OR it with the first shuffled input.
3837 for (unsigned i = 0; i != 8; ++i) {
3838 int EltIdx = MaskVals[i] * 2;
3840 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3841 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3844 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3845 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3847 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3848 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3849 DAG.getNode(ISD::BUILD_VECTOR, dl,
3850 MVT::v16i8, &pshufbMask[0], 16));
3851 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3852 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3855 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3856 // and update MaskVals with new element order.
3857 BitVector InOrder(8);
3858 if (BestLoQuad >= 0) {
3859 SmallVector<int, 8> MaskV;
3860 for (int i = 0; i != 4; ++i) {
3861 int idx = MaskVals[i];
3863 MaskV.push_back(-1);
3865 } else if ((idx / 4) == BestLoQuad) {
3866 MaskV.push_back(idx & 3);
3869 MaskV.push_back(-1);
3872 for (unsigned i = 4; i != 8; ++i)
3874 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3878 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3879 // and update MaskVals with the new element order.
3880 if (BestHiQuad >= 0) {
3881 SmallVector<int, 8> MaskV;
3882 for (unsigned i = 0; i != 4; ++i)
3884 for (unsigned i = 4; i != 8; ++i) {
3885 int idx = MaskVals[i];
3887 MaskV.push_back(-1);
3889 } else if ((idx / 4) == BestHiQuad) {
3890 MaskV.push_back((idx & 3) + 4);
3893 MaskV.push_back(-1);
3896 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3900 // In case BestHi & BestLo were both -1, which means each quadword has a word
3901 // from each of the four input quadwords, calculate the InOrder bitvector now
3902 // before falling through to the insert/extract cleanup.
3903 if (BestLoQuad == -1 && BestHiQuad == -1) {
3905 for (int i = 0; i != 8; ++i)
3906 if (MaskVals[i] < 0 || MaskVals[i] == i)
3910 // The other elements are put in the right place using pextrw and pinsrw.
3911 for (unsigned i = 0; i != 8; ++i) {
3914 int EltIdx = MaskVals[i];
3917 SDValue ExtOp = (EltIdx < 8)
3918 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3919 DAG.getIntPtrConstant(EltIdx))
3920 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3921 DAG.getIntPtrConstant(EltIdx - 8));
3922 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3923 DAG.getIntPtrConstant(i));
3928 // v16i8 shuffles - Prefer shuffles in the following order:
3929 // 1. [ssse3] 1 x pshufb
3930 // 2. [ssse3] 2 x pshufb + 1 x por
3931 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3933 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3934 SelectionDAG &DAG, X86TargetLowering &TLI) {
3935 SDValue V1 = SVOp->getOperand(0);
3936 SDValue V2 = SVOp->getOperand(1);
3937 DebugLoc dl = SVOp->getDebugLoc();
3938 SmallVector<int, 16> MaskVals;
3939 SVOp->getMask(MaskVals);
3941 // If we have SSSE3, case 1 is generated when all result bytes come from
3942 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3943 // present, fall back to case 3.
3944 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3947 for (unsigned i = 0; i < 16; ++i) {
3948 int EltIdx = MaskVals[i];
3957 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3958 if (TLI.getSubtarget()->hasSSSE3()) {
3959 SmallVector<SDValue,16> pshufbMask;
3961 // If all result elements are from one input vector, then only translate
3962 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3964 // Otherwise, we have elements from both input vectors, and must zero out
3965 // elements that come from V2 in the first mask, and V1 in the second mask
3966 // so that we can OR them together.
3967 bool TwoInputs = !(V1Only || V2Only);
3968 for (unsigned i = 0; i != 16; ++i) {
3969 int EltIdx = MaskVals[i];
3970 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3971 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3974 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3976 // If all the elements are from V2, assign it to V1 and return after
3977 // building the first pshufb.
3980 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3981 DAG.getNode(ISD::BUILD_VECTOR, dl,
3982 MVT::v16i8, &pshufbMask[0], 16));
3986 // Calculate the shuffle mask for the second input, shuffle it, and
3987 // OR it with the first shuffled input.
3989 for (unsigned i = 0; i != 16; ++i) {
3990 int EltIdx = MaskVals[i];
3992 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3995 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3997 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3998 DAG.getNode(ISD::BUILD_VECTOR, dl,
3999 MVT::v16i8, &pshufbMask[0], 16));
4000 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4003 // No SSSE3 - Calculate in place words and then fix all out of place words
4004 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4005 // the 16 different words that comprise the two doublequadword input vectors.
4006 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4007 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4008 SDValue NewV = V2Only ? V2 : V1;
4009 for (int i = 0; i != 8; ++i) {
4010 int Elt0 = MaskVals[i*2];
4011 int Elt1 = MaskVals[i*2+1];
4013 // This word of the result is all undef, skip it.
4014 if (Elt0 < 0 && Elt1 < 0)
4017 // This word of the result is already in the correct place, skip it.
4018 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4020 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4023 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4024 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4027 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4028 // using a single extract together, load it and store it.
4029 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4030 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4031 DAG.getIntPtrConstant(Elt1 / 2));
4032 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4033 DAG.getIntPtrConstant(i));
4037 // If Elt1 is defined, extract it from the appropriate source. If the
4038 // source byte is not also odd, shift the extracted word left 8 bits
4039 // otherwise clear the bottom 8 bits if we need to do an or.
4041 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4042 DAG.getIntPtrConstant(Elt1 / 2));
4043 if ((Elt1 & 1) == 0)
4044 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4045 DAG.getConstant(8, TLI.getShiftAmountTy()));
4047 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4048 DAG.getConstant(0xFF00, MVT::i16));
4050 // If Elt0 is defined, extract it from the appropriate source. If the
4051 // source byte is not also even, shift the extracted word right 8 bits. If
4052 // Elt1 was also defined, OR the extracted values together before
4053 // inserting them in the result.
4055 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4056 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4057 if ((Elt0 & 1) != 0)
4058 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4059 DAG.getConstant(8, TLI.getShiftAmountTy()));
4061 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4062 DAG.getConstant(0x00FF, MVT::i16));
4063 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4066 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4067 DAG.getIntPtrConstant(i));
4069 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4072 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4073 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4074 /// done when every pair / quad of shuffle mask elements point to elements in
4075 /// the right sequence. e.g.
4076 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4078 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4080 TargetLowering &TLI, DebugLoc dl) {
4081 EVT VT = SVOp->getValueType(0);
4082 SDValue V1 = SVOp->getOperand(0);
4083 SDValue V2 = SVOp->getOperand(1);
4084 unsigned NumElems = VT.getVectorNumElements();
4085 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4086 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4087 EVT MaskEltVT = MaskVT.getVectorElementType();
4089 switch (VT.getSimpleVT().SimpleTy) {
4090 default: assert(false && "Unexpected!");
4091 case MVT::v4f32: NewVT = MVT::v2f64; break;
4092 case MVT::v4i32: NewVT = MVT::v2i64; break;
4093 case MVT::v8i16: NewVT = MVT::v4i32; break;
4094 case MVT::v16i8: NewVT = MVT::v4i32; break;
4097 if (NewWidth == 2) {
4103 int Scale = NumElems / NewWidth;
4104 SmallVector<int, 8> MaskVec;
4105 for (unsigned i = 0; i < NumElems; i += Scale) {
4107 for (int j = 0; j < Scale; ++j) {
4108 int EltIdx = SVOp->getMaskElt(i+j);
4112 StartIdx = EltIdx - (EltIdx % Scale);
4113 if (EltIdx != StartIdx + j)
4117 MaskVec.push_back(-1);
4119 MaskVec.push_back(StartIdx / Scale);
4122 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4123 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4124 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4127 /// getVZextMovL - Return a zero-extending vector move low node.
4129 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4130 SDValue SrcOp, SelectionDAG &DAG,
4131 const X86Subtarget *Subtarget, DebugLoc dl) {
4132 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4133 LoadSDNode *LD = NULL;
4134 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4135 LD = dyn_cast<LoadSDNode>(SrcOp);
4137 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4139 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4140 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4141 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4142 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4143 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4145 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4146 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4147 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4148 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4156 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4157 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4158 DAG.getNode(ISD::BIT_CONVERT, dl,
4162 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4165 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4166 SDValue V1 = SVOp->getOperand(0);
4167 SDValue V2 = SVOp->getOperand(1);
4168 DebugLoc dl = SVOp->getDebugLoc();
4169 EVT VT = SVOp->getValueType(0);
4171 SmallVector<std::pair<int, int>, 8> Locs;
4173 SmallVector<int, 8> Mask1(4U, -1);
4174 SmallVector<int, 8> PermMask;
4175 SVOp->getMask(PermMask);
4179 for (unsigned i = 0; i != 4; ++i) {
4180 int Idx = PermMask[i];
4182 Locs[i] = std::make_pair(-1, -1);
4184 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4186 Locs[i] = std::make_pair(0, NumLo);
4190 Locs[i] = std::make_pair(1, NumHi);
4192 Mask1[2+NumHi] = Idx;
4198 if (NumLo <= 2 && NumHi <= 2) {
4199 // If no more than two elements come from either vector. This can be
4200 // implemented with two shuffles. First shuffle gather the elements.
4201 // The second shuffle, which takes the first shuffle as both of its
4202 // vector operands, put the elements into the right order.
4203 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4205 SmallVector<int, 8> Mask2(4U, -1);
4207 for (unsigned i = 0; i != 4; ++i) {
4208 if (Locs[i].first == -1)
4211 unsigned Idx = (i < 2) ? 0 : 4;
4212 Idx += Locs[i].first * 2 + Locs[i].second;
4217 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4218 } else if (NumLo == 3 || NumHi == 3) {
4219 // Otherwise, we must have three elements from one vector, call it X, and
4220 // one element from the other, call it Y. First, use a shufps to build an
4221 // intermediate vector with the one element from Y and the element from X
4222 // that will be in the same half in the final destination (the indexes don't
4223 // matter). Then, use a shufps to build the final vector, taking the half
4224 // containing the element from Y from the intermediate, and the other half
4227 // Normalize it so the 3 elements come from V1.
4228 CommuteVectorShuffleMask(PermMask, VT);
4232 // Find the element from V2.
4234 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4235 int Val = PermMask[HiIndex];
4242 Mask1[0] = PermMask[HiIndex];
4244 Mask1[2] = PermMask[HiIndex^1];
4246 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4249 Mask1[0] = PermMask[0];
4250 Mask1[1] = PermMask[1];
4251 Mask1[2] = HiIndex & 1 ? 6 : 4;
4252 Mask1[3] = HiIndex & 1 ? 4 : 6;
4253 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4255 Mask1[0] = HiIndex & 1 ? 2 : 0;
4256 Mask1[1] = HiIndex & 1 ? 0 : 2;
4257 Mask1[2] = PermMask[2];
4258 Mask1[3] = PermMask[3];
4263 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4267 // Break it into (shuffle shuffle_hi, shuffle_lo).
4269 SmallVector<int,8> LoMask(4U, -1);
4270 SmallVector<int,8> HiMask(4U, -1);
4272 SmallVector<int,8> *MaskPtr = &LoMask;
4273 unsigned MaskIdx = 0;
4276 for (unsigned i = 0; i != 4; ++i) {
4283 int Idx = PermMask[i];
4285 Locs[i] = std::make_pair(-1, -1);
4286 } else if (Idx < 4) {
4287 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4288 (*MaskPtr)[LoIdx] = Idx;
4291 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4292 (*MaskPtr)[HiIdx] = Idx;
4297 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4298 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4299 SmallVector<int, 8> MaskOps;
4300 for (unsigned i = 0; i != 4; ++i) {
4301 if (Locs[i].first == -1) {
4302 MaskOps.push_back(-1);
4304 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4305 MaskOps.push_back(Idx);
4308 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4312 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4314 SDValue V1 = Op.getOperand(0);
4315 SDValue V2 = Op.getOperand(1);
4316 EVT VT = Op.getValueType();
4317 DebugLoc dl = Op.getDebugLoc();
4318 unsigned NumElems = VT.getVectorNumElements();
4319 bool isMMX = VT.getSizeInBits() == 64;
4320 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4321 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4322 bool V1IsSplat = false;
4323 bool V2IsSplat = false;
4325 if (isZeroShuffle(SVOp))
4326 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4328 // Promote splats to v4f32.
4329 if (SVOp->isSplat()) {
4330 if (isMMX || NumElems < 4)
4332 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4335 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4337 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4338 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4339 if (NewOp.getNode())
4340 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4341 LowerVECTOR_SHUFFLE(NewOp, DAG));
4342 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4343 // FIXME: Figure out a cleaner way to do this.
4344 // Try to make use of movq to zero out the top part.
4345 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4346 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4347 if (NewOp.getNode()) {
4348 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4349 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4350 DAG, Subtarget, dl);
4352 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4353 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4354 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4355 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4356 DAG, Subtarget, dl);
4360 if (X86::isPSHUFDMask(SVOp))
4363 // Check if this can be converted into a logical shift.
4364 bool isLeft = false;
4367 bool isShift = getSubtarget()->hasSSE2() &&
4368 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4369 if (isShift && ShVal.hasOneUse()) {
4370 // If the shifted value has multiple uses, it may be cheaper to use
4371 // v_set0 + movlhps or movhlps, etc.
4372 EVT EltVT = VT.getVectorElementType();
4373 ShAmt *= EltVT.getSizeInBits();
4374 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4377 if (X86::isMOVLMask(SVOp)) {
4380 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4381 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4386 // FIXME: fold these into legal mask.
4387 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4388 X86::isMOVSLDUPMask(SVOp) ||
4389 X86::isMOVHLPSMask(SVOp) ||
4390 X86::isMOVLHPSMask(SVOp) ||
4391 X86::isMOVLPMask(SVOp)))
4394 if (ShouldXformToMOVHLPS(SVOp) ||
4395 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4396 return CommuteVectorShuffle(SVOp, DAG);
4399 // No better options. Use a vshl / vsrl.
4400 EVT EltVT = VT.getVectorElementType();
4401 ShAmt *= EltVT.getSizeInBits();
4402 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4405 bool Commuted = false;
4406 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4407 // 1,1,1,1 -> v8i16 though.
4408 V1IsSplat = isSplatVector(V1.getNode());
4409 V2IsSplat = isSplatVector(V2.getNode());
4411 // Canonicalize the splat or undef, if present, to be on the RHS.
4412 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4413 Op = CommuteVectorShuffle(SVOp, DAG);
4414 SVOp = cast<ShuffleVectorSDNode>(Op);
4415 V1 = SVOp->getOperand(0);
4416 V2 = SVOp->getOperand(1);
4417 std::swap(V1IsSplat, V2IsSplat);
4418 std::swap(V1IsUndef, V2IsUndef);
4422 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4423 // Shuffling low element of v1 into undef, just return v1.
4426 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4427 // the instruction selector will not match, so get a canonical MOVL with
4428 // swapped operands to undo the commute.
4429 return getMOVL(DAG, dl, VT, V2, V1);
4432 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4433 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4434 X86::isUNPCKLMask(SVOp) ||
4435 X86::isUNPCKHMask(SVOp))
4439 // Normalize mask so all entries that point to V2 points to its first
4440 // element then try to match unpck{h|l} again. If match, return a
4441 // new vector_shuffle with the corrected mask.
4442 SDValue NewMask = NormalizeMask(SVOp, DAG);
4443 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4444 if (NSVOp != SVOp) {
4445 if (X86::isUNPCKLMask(NSVOp, true)) {
4447 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4454 // Commute is back and try unpck* again.
4455 // FIXME: this seems wrong.
4456 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4457 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4458 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4459 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4460 X86::isUNPCKLMask(NewSVOp) ||
4461 X86::isUNPCKHMask(NewSVOp))
4465 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4467 // Normalize the node to match x86 shuffle ops if needed
4468 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4469 return CommuteVectorShuffle(SVOp, DAG);
4471 // Check for legal shuffle and return?
4472 SmallVector<int, 16> PermMask;
4473 SVOp->getMask(PermMask);
4474 if (isShuffleMaskLegal(PermMask, VT))
4477 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4478 if (VT == MVT::v8i16) {
4479 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4480 if (NewOp.getNode())
4484 if (VT == MVT::v16i8) {
4485 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4486 if (NewOp.getNode())
4490 // Handle all 4 wide cases with a number of shuffles except for MMX.
4491 if (NumElems == 4 && !isMMX)
4492 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4498 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4499 SelectionDAG &DAG) {
4500 EVT VT = Op.getValueType();
4501 DebugLoc dl = Op.getDebugLoc();
4502 if (VT.getSizeInBits() == 8) {
4503 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4504 Op.getOperand(0), Op.getOperand(1));
4505 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4506 DAG.getValueType(VT));
4507 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4508 } else if (VT.getSizeInBits() == 16) {
4509 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4510 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4512 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4513 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4514 DAG.getNode(ISD::BIT_CONVERT, dl,
4518 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4519 Op.getOperand(0), Op.getOperand(1));
4520 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4521 DAG.getValueType(VT));
4522 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4523 } else if (VT == MVT::f32) {
4524 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4525 // the result back to FR32 register. It's only worth matching if the
4526 // result has a single use which is a store or a bitcast to i32. And in
4527 // the case of a store, it's not worth it if the index is a constant 0,
4528 // because a MOVSSmr can be used instead, which is smaller and faster.
4529 if (!Op.hasOneUse())
4531 SDNode *User = *Op.getNode()->use_begin();
4532 if ((User->getOpcode() != ISD::STORE ||
4533 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4534 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4535 (User->getOpcode() != ISD::BIT_CONVERT ||
4536 User->getValueType(0) != MVT::i32))
4538 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4539 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4542 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4543 } else if (VT == MVT::i32) {
4544 // ExtractPS works with constant index.
4545 if (isa<ConstantSDNode>(Op.getOperand(1)))
4553 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4554 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4557 if (Subtarget->hasSSE41()) {
4558 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4563 EVT VT = Op.getValueType();
4564 DebugLoc dl = Op.getDebugLoc();
4565 // TODO: handle v16i8.
4566 if (VT.getSizeInBits() == 16) {
4567 SDValue Vec = Op.getOperand(0);
4568 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4570 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4571 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4572 DAG.getNode(ISD::BIT_CONVERT, dl,
4575 // Transform it so it match pextrw which produces a 32-bit result.
4576 EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4577 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4578 Op.getOperand(0), Op.getOperand(1));
4579 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4580 DAG.getValueType(VT));
4581 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4582 } else if (VT.getSizeInBits() == 32) {
4583 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4587 // SHUFPS the element to the lowest double word, then movss.
4588 int Mask[4] = { Idx, -1, -1, -1 };
4589 EVT VVT = Op.getOperand(0).getValueType();
4590 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4591 DAG.getUNDEF(VVT), Mask);
4592 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4593 DAG.getIntPtrConstant(0));
4594 } else if (VT.getSizeInBits() == 64) {
4595 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4596 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4597 // to match extract_elt for f64.
4598 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4602 // UNPCKHPD the element to the lowest double word, then movsd.
4603 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4604 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4605 int Mask[2] = { 1, -1 };
4606 EVT VVT = Op.getOperand(0).getValueType();
4607 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4608 DAG.getUNDEF(VVT), Mask);
4609 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4610 DAG.getIntPtrConstant(0));
4617 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4618 EVT VT = Op.getValueType();
4619 EVT EltVT = VT.getVectorElementType();
4620 DebugLoc dl = Op.getDebugLoc();
4622 SDValue N0 = Op.getOperand(0);
4623 SDValue N1 = Op.getOperand(1);
4624 SDValue N2 = Op.getOperand(2);
4626 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4627 isa<ConstantSDNode>(N2)) {
4628 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4630 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4632 if (N1.getValueType() != MVT::i32)
4633 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4634 if (N2.getValueType() != MVT::i32)
4635 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4636 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4637 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4638 // Bits [7:6] of the constant are the source select. This will always be
4639 // zero here. The DAG Combiner may combine an extract_elt index into these
4640 // bits. For example (insert (extract, 3), 2) could be matched by putting
4641 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4642 // Bits [5:4] of the constant are the destination select. This is the
4643 // value of the incoming immediate.
4644 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4645 // combine either bitwise AND or insert of float 0.0 to set these bits.
4646 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4647 // Create this as a scalar to vector..
4648 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4649 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4650 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4651 // PINSR* works with constant index.
4658 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4659 EVT VT = Op.getValueType();
4660 EVT EltVT = VT.getVectorElementType();
4662 if (Subtarget->hasSSE41())
4663 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4665 if (EltVT == MVT::i8)
4668 DebugLoc dl = Op.getDebugLoc();
4669 SDValue N0 = Op.getOperand(0);
4670 SDValue N1 = Op.getOperand(1);
4671 SDValue N2 = Op.getOperand(2);
4673 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4674 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4675 // as its second argument.
4676 if (N1.getValueType() != MVT::i32)
4677 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4678 if (N2.getValueType() != MVT::i32)
4679 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4680 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4686 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4687 DebugLoc dl = Op.getDebugLoc();
4688 if (Op.getValueType() == MVT::v2f32)
4689 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4690 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4691 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4692 Op.getOperand(0))));
4694 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4695 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4697 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4698 EVT VT = MVT::v2i32;
4699 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4706 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4707 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4710 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4711 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4712 // one of the above mentioned nodes. It has to be wrapped because otherwise
4713 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4714 // be used to form addressing mode. These wrapped nodes will be selected
4717 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4718 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4720 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4722 unsigned char OpFlag = 0;
4723 unsigned WrapperKind = X86ISD::Wrapper;
4724 CodeModel::Model M = getTargetMachine().getCodeModel();
4726 if (Subtarget->isPICStyleRIPRel() &&
4727 (M == CodeModel::Small || M == CodeModel::Kernel))
4728 WrapperKind = X86ISD::WrapperRIP;
4729 else if (Subtarget->isPICStyleGOT())
4730 OpFlag = X86II::MO_GOTOFF;
4731 else if (Subtarget->isPICStyleStubPIC())
4732 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4734 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4736 CP->getOffset(), OpFlag);
4737 DebugLoc DL = CP->getDebugLoc();
4738 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4739 // With PIC, the address is actually $g + Offset.
4741 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4742 DAG.getNode(X86ISD::GlobalBaseReg,
4743 DebugLoc::getUnknownLoc(), getPointerTy()),
4750 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4751 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4753 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4755 unsigned char OpFlag = 0;
4756 unsigned WrapperKind = X86ISD::Wrapper;
4757 CodeModel::Model M = getTargetMachine().getCodeModel();
4759 if (Subtarget->isPICStyleRIPRel() &&
4760 (M == CodeModel::Small || M == CodeModel::Kernel))
4761 WrapperKind = X86ISD::WrapperRIP;
4762 else if (Subtarget->isPICStyleGOT())
4763 OpFlag = X86II::MO_GOTOFF;
4764 else if (Subtarget->isPICStyleStubPIC())
4765 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4767 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4769 DebugLoc DL = JT->getDebugLoc();
4770 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4772 // With PIC, the address is actually $g + Offset.
4774 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4775 DAG.getNode(X86ISD::GlobalBaseReg,
4776 DebugLoc::getUnknownLoc(), getPointerTy()),
4784 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4785 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4787 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4789 unsigned char OpFlag = 0;
4790 unsigned WrapperKind = X86ISD::Wrapper;
4791 CodeModel::Model M = getTargetMachine().getCodeModel();
4793 if (Subtarget->isPICStyleRIPRel() &&
4794 (M == CodeModel::Small || M == CodeModel::Kernel))
4795 WrapperKind = X86ISD::WrapperRIP;
4796 else if (Subtarget->isPICStyleGOT())
4797 OpFlag = X86II::MO_GOTOFF;
4798 else if (Subtarget->isPICStyleStubPIC())
4799 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4801 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4803 DebugLoc DL = Op.getDebugLoc();
4804 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4807 // With PIC, the address is actually $g + Offset.
4808 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4809 !Subtarget->is64Bit()) {
4810 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4811 DAG.getNode(X86ISD::GlobalBaseReg,
4812 DebugLoc::getUnknownLoc(),
4821 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4822 // Create the TargetBlockAddressAddress node.
4823 unsigned char OpFlags =
4824 Subtarget->ClassifyBlockAddressReference();
4825 CodeModel::Model M = getTargetMachine().getCodeModel();
4826 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4827 DebugLoc dl = Op.getDebugLoc();
4828 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
4829 /*isTarget=*/true, OpFlags);
4831 if (Subtarget->isPICStyleRIPRel() &&
4832 (M == CodeModel::Small || M == CodeModel::Kernel))
4833 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4835 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4837 // With PIC, the address is actually $g + Offset.
4838 if (isGlobalRelativeToPICBase(OpFlags)) {
4839 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4840 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4848 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4850 SelectionDAG &DAG) const {
4851 // Create the TargetGlobalAddress node, folding in the constant
4852 // offset if it is legal.
4853 unsigned char OpFlags =
4854 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4855 CodeModel::Model M = getTargetMachine().getCodeModel();
4857 if (OpFlags == X86II::MO_NO_FLAG &&
4858 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4859 // A direct static reference to a global.
4860 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4863 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4866 if (Subtarget->isPICStyleRIPRel() &&
4867 (M == CodeModel::Small || M == CodeModel::Kernel))
4868 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4870 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4872 // With PIC, the address is actually $g + Offset.
4873 if (isGlobalRelativeToPICBase(OpFlags)) {
4874 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4875 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4879 // For globals that require a load from a stub to get the address, emit the
4881 if (isGlobalStubReference(OpFlags))
4882 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4883 PseudoSourceValue::getGOT(), 0);
4885 // If there was a non-zero offset that we didn't fold, create an explicit
4888 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4889 DAG.getConstant(Offset, getPointerTy()));
4895 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4896 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4897 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4898 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4902 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4903 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4904 unsigned char OperandFlags) {
4905 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4906 DebugLoc dl = GA->getDebugLoc();
4907 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4908 GA->getValueType(0),
4912 SDValue Ops[] = { Chain, TGA, *InFlag };
4913 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4915 SDValue Ops[] = { Chain, TGA };
4916 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4918 SDValue Flag = Chain.getValue(1);
4919 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4922 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4924 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4927 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4928 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4929 DAG.getNode(X86ISD::GlobalBaseReg,
4930 DebugLoc::getUnknownLoc(),
4932 InFlag = Chain.getValue(1);
4934 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4937 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4939 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4941 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4942 X86::RAX, X86II::MO_TLSGD);
4945 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4946 // "local exec" model.
4947 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4948 const EVT PtrVT, TLSModel::Model model,
4950 DebugLoc dl = GA->getDebugLoc();
4951 // Get the Thread Pointer
4952 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4953 DebugLoc::getUnknownLoc(), PtrVT,
4954 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4957 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4960 unsigned char OperandFlags = 0;
4961 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4963 unsigned WrapperKind = X86ISD::Wrapper;
4964 if (model == TLSModel::LocalExec) {
4965 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4966 } else if (is64Bit) {
4967 assert(model == TLSModel::InitialExec);
4968 OperandFlags = X86II::MO_GOTTPOFF;
4969 WrapperKind = X86ISD::WrapperRIP;
4971 assert(model == TLSModel::InitialExec);
4972 OperandFlags = X86II::MO_INDNTPOFF;
4975 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4977 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4978 GA->getOffset(), OperandFlags);
4979 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4981 if (model == TLSModel::InitialExec)
4982 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4983 PseudoSourceValue::getGOT(), 0);
4985 // The address of the thread local variable is the add of the thread
4986 // pointer with the offset of the variable.
4987 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4991 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4992 // TODO: implement the "local dynamic" model
4993 // TODO: implement the "initial exec"model for pic executables
4994 assert(Subtarget->isTargetELF() &&
4995 "TLS not implemented for non-ELF targets");
4996 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4997 const GlobalValue *GV = GA->getGlobal();
4999 // If GV is an alias then use the aliasee for determining
5000 // thread-localness.
5001 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5002 GV = GA->resolveAliasedGlobal(false);
5004 TLSModel::Model model = getTLSModel(GV,
5005 getTargetMachine().getRelocationModel());
5008 case TLSModel::GeneralDynamic:
5009 case TLSModel::LocalDynamic: // not implemented
5010 if (Subtarget->is64Bit())
5011 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5012 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5014 case TLSModel::InitialExec:
5015 case TLSModel::LocalExec:
5016 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5017 Subtarget->is64Bit());
5020 llvm_unreachable("Unreachable");
5025 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5026 /// take a 2 x i32 value to shift plus a shift amount.
5027 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5028 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5029 EVT VT = Op.getValueType();
5030 unsigned VTBits = VT.getSizeInBits();
5031 DebugLoc dl = Op.getDebugLoc();
5032 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5033 SDValue ShOpLo = Op.getOperand(0);
5034 SDValue ShOpHi = Op.getOperand(1);
5035 SDValue ShAmt = Op.getOperand(2);
5036 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5037 DAG.getConstant(VTBits - 1, MVT::i8))
5038 : DAG.getConstant(0, VT);
5041 if (Op.getOpcode() == ISD::SHL_PARTS) {
5042 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5043 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5045 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5046 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5049 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5050 DAG.getConstant(VTBits, MVT::i8));
5051 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5052 AndNode, DAG.getConstant(0, MVT::i8));
5055 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5056 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5057 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5059 if (Op.getOpcode() == ISD::SHL_PARTS) {
5060 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5061 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5063 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5064 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5067 SDValue Ops[2] = { Lo, Hi };
5068 return DAG.getMergeValues(Ops, 2, dl);
5071 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5072 EVT SrcVT = Op.getOperand(0).getValueType();
5074 if (SrcVT.isVector()) {
5075 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5081 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5082 "Unknown SINT_TO_FP to lower!");
5084 // These are really Legal; return the operand so the caller accepts it as
5086 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5088 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5089 Subtarget->is64Bit()) {
5093 DebugLoc dl = Op.getDebugLoc();
5094 unsigned Size = SrcVT.getSizeInBits()/8;
5095 MachineFunction &MF = DAG.getMachineFunction();
5096 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5097 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5098 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5100 PseudoSourceValue::getFixedStack(SSFI), 0);
5101 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5104 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5106 SelectionDAG &DAG) {
5108 DebugLoc dl = Op.getDebugLoc();
5110 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5112 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5114 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5115 SmallVector<SDValue, 8> Ops;
5116 Ops.push_back(Chain);
5117 Ops.push_back(StackSlot);
5118 Ops.push_back(DAG.getValueType(SrcVT));
5119 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5120 Tys, &Ops[0], Ops.size());
5123 Chain = Result.getValue(1);
5124 SDValue InFlag = Result.getValue(2);
5126 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5127 // shouldn't be necessary except that RFP cannot be live across
5128 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5129 MachineFunction &MF = DAG.getMachineFunction();
5130 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5131 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5132 Tys = DAG.getVTList(MVT::Other);
5133 SmallVector<SDValue, 8> Ops;
5134 Ops.push_back(Chain);
5135 Ops.push_back(Result);
5136 Ops.push_back(StackSlot);
5137 Ops.push_back(DAG.getValueType(Op.getValueType()));
5138 Ops.push_back(InFlag);
5139 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
5140 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5141 PseudoSourceValue::getFixedStack(SSFI), 0);
5147 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5148 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5149 // This algorithm is not obvious. Here it is in C code, more or less:
5151 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5152 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5153 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5155 // Copy ints to xmm registers.
5156 __m128i xh = _mm_cvtsi32_si128( hi );
5157 __m128i xl = _mm_cvtsi32_si128( lo );
5159 // Combine into low half of a single xmm register.
5160 __m128i x = _mm_unpacklo_epi32( xh, xl );
5164 // Merge in appropriate exponents to give the integer bits the right
5166 x = _mm_unpacklo_epi32( x, exp );
5168 // Subtract away the biases to deal with the IEEE-754 double precision
5170 d = _mm_sub_pd( (__m128d) x, bias );
5172 // All conversions up to here are exact. The correctly rounded result is
5173 // calculated using the current rounding mode using the following
5175 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5176 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5177 // store doesn't really need to be here (except
5178 // maybe to zero the other double)
5183 DebugLoc dl = Op.getDebugLoc();
5184 LLVMContext *Context = DAG.getContext();
5186 // Build some magic constants.
5187 std::vector<Constant*> CV0;
5188 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5189 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5190 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5191 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5192 Constant *C0 = ConstantVector::get(CV0);
5193 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5195 std::vector<Constant*> CV1;
5197 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5199 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5200 Constant *C1 = ConstantVector::get(CV1);
5201 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5203 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5204 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5206 DAG.getIntPtrConstant(1)));
5207 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5208 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5210 DAG.getIntPtrConstant(0)));
5211 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5212 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5213 PseudoSourceValue::getConstantPool(), 0,
5215 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5216 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5217 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5218 PseudoSourceValue::getConstantPool(), 0,
5220 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5222 // Add the halves; easiest way is to swap them into another reg first.
5223 int ShufMask[2] = { 1, -1 };
5224 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5225 DAG.getUNDEF(MVT::v2f64), ShufMask);
5226 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5227 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5228 DAG.getIntPtrConstant(0));
5231 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5232 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5233 DebugLoc dl = Op.getDebugLoc();
5234 // FP constant to bias correct the final result.
5235 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5238 // Load the 32-bit value into an XMM register.
5239 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5240 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5242 DAG.getIntPtrConstant(0)));
5244 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5245 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5246 DAG.getIntPtrConstant(0));
5248 // Or the load with the bias.
5249 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5250 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5251 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5253 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5254 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5255 MVT::v2f64, Bias)));
5256 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5257 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5258 DAG.getIntPtrConstant(0));
5260 // Subtract the bias.
5261 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5263 // Handle final rounding.
5264 EVT DestVT = Op.getValueType();
5266 if (DestVT.bitsLT(MVT::f64)) {
5267 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5268 DAG.getIntPtrConstant(0));
5269 } else if (DestVT.bitsGT(MVT::f64)) {
5270 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5273 // Handle final rounding.
5277 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5278 SDValue N0 = Op.getOperand(0);
5279 DebugLoc dl = Op.getDebugLoc();
5281 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5282 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5283 // the optimization here.
5284 if (DAG.SignBitIsZero(N0))
5285 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5287 EVT SrcVT = N0.getValueType();
5288 if (SrcVT == MVT::i64) {
5289 // We only handle SSE2 f64 target here; caller can expand the rest.
5290 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5293 return LowerUINT_TO_FP_i64(Op, DAG);
5294 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5295 return LowerUINT_TO_FP_i32(Op, DAG);
5298 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5300 // Make a 64-bit buffer, and use it to build an FILD.
5301 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5302 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5303 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5304 getPointerTy(), StackSlot, WordOff);
5305 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5306 StackSlot, NULL, 0);
5307 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5308 OffsetSlot, NULL, 0);
5309 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5312 std::pair<SDValue,SDValue> X86TargetLowering::
5313 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5314 DebugLoc dl = Op.getDebugLoc();
5316 EVT DstTy = Op.getValueType();
5319 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5323 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5324 DstTy.getSimpleVT() >= MVT::i16 &&
5325 "Unknown FP_TO_SINT to lower!");
5327 // These are really Legal.
5328 if (DstTy == MVT::i32 &&
5329 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5330 return std::make_pair(SDValue(), SDValue());
5331 if (Subtarget->is64Bit() &&
5332 DstTy == MVT::i64 &&
5333 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5334 return std::make_pair(SDValue(), SDValue());
5336 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5338 MachineFunction &MF = DAG.getMachineFunction();
5339 unsigned MemSize = DstTy.getSizeInBits()/8;
5340 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5341 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5344 switch (DstTy.getSimpleVT().SimpleTy) {
5345 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5346 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5347 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5348 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5351 SDValue Chain = DAG.getEntryNode();
5352 SDValue Value = Op.getOperand(0);
5353 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5354 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5355 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5356 PseudoSourceValue::getFixedStack(SSFI), 0);
5357 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5359 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5361 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5362 Chain = Value.getValue(1);
5363 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5364 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5367 // Build the FP_TO_INT*_IN_MEM
5368 SDValue Ops[] = { Chain, Value, StackSlot };
5369 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5371 return std::make_pair(FIST, StackSlot);
5374 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5375 if (Op.getValueType().isVector()) {
5376 if (Op.getValueType() == MVT::v2i32 &&
5377 Op.getOperand(0).getValueType() == MVT::v2f64) {
5383 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5384 SDValue FIST = Vals.first, StackSlot = Vals.second;
5385 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5386 if (FIST.getNode() == 0) return Op;
5389 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5390 FIST, StackSlot, NULL, 0);
5393 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5394 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5395 SDValue FIST = Vals.first, StackSlot = Vals.second;
5396 assert(FIST.getNode() && "Unexpected failure");
5399 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5400 FIST, StackSlot, NULL, 0);
5403 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5404 LLVMContext *Context = DAG.getContext();
5405 DebugLoc dl = Op.getDebugLoc();
5406 EVT VT = Op.getValueType();
5409 EltVT = VT.getVectorElementType();
5410 std::vector<Constant*> CV;
5411 if (EltVT == MVT::f64) {
5412 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5416 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5422 Constant *C = ConstantVector::get(CV);
5423 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5424 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5425 PseudoSourceValue::getConstantPool(), 0,
5427 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5430 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5431 LLVMContext *Context = DAG.getContext();
5432 DebugLoc dl = Op.getDebugLoc();
5433 EVT VT = Op.getValueType();
5436 EltVT = VT.getVectorElementType();
5437 std::vector<Constant*> CV;
5438 if (EltVT == MVT::f64) {
5439 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5443 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5449 Constant *C = ConstantVector::get(CV);
5450 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5451 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5452 PseudoSourceValue::getConstantPool(), 0,
5454 if (VT.isVector()) {
5455 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5456 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5457 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5459 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5461 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5465 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5466 LLVMContext *Context = DAG.getContext();
5467 SDValue Op0 = Op.getOperand(0);
5468 SDValue Op1 = Op.getOperand(1);
5469 DebugLoc dl = Op.getDebugLoc();
5470 EVT VT = Op.getValueType();
5471 EVT SrcVT = Op1.getValueType();
5473 // If second operand is smaller, extend it first.
5474 if (SrcVT.bitsLT(VT)) {
5475 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5478 // And if it is bigger, shrink it first.
5479 if (SrcVT.bitsGT(VT)) {
5480 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5484 // At this point the operands and the result should have the same
5485 // type, and that won't be f80 since that is not custom lowered.
5487 // First get the sign bit of second operand.
5488 std::vector<Constant*> CV;
5489 if (SrcVT == MVT::f64) {
5490 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5491 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5493 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5494 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5495 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5496 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5498 Constant *C = ConstantVector::get(CV);
5499 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5500 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5501 PseudoSourceValue::getConstantPool(), 0,
5503 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5505 // Shift sign bit right or left if the two operands have different types.
5506 if (SrcVT.bitsGT(VT)) {
5507 // Op0 is MVT::f32, Op1 is MVT::f64.
5508 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5509 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5510 DAG.getConstant(32, MVT::i32));
5511 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5512 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5513 DAG.getIntPtrConstant(0));
5516 // Clear first operand sign bit.
5518 if (VT == MVT::f64) {
5519 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5520 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5522 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5523 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5524 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5525 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5527 C = ConstantVector::get(CV);
5528 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5529 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5530 PseudoSourceValue::getConstantPool(), 0,
5532 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5534 // Or the value with the sign bit.
5535 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5538 /// Emit nodes that will be selected as "test Op0,Op0", or something
5540 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5541 SelectionDAG &DAG) {
5542 DebugLoc dl = Op.getDebugLoc();
5544 // CF and OF aren't always set the way we want. Determine which
5545 // of these we need.
5546 bool NeedCF = false;
5547 bool NeedOF = false;
5549 case X86::COND_A: case X86::COND_AE:
5550 case X86::COND_B: case X86::COND_BE:
5553 case X86::COND_G: case X86::COND_GE:
5554 case X86::COND_L: case X86::COND_LE:
5555 case X86::COND_O: case X86::COND_NO:
5561 // See if we can use the EFLAGS value from the operand instead of
5562 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5563 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5564 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5565 unsigned Opcode = 0;
5566 unsigned NumOperands = 0;
5567 switch (Op.getNode()->getOpcode()) {
5569 // Due to an isel shortcoming, be conservative if this add is likely to
5570 // be selected as part of a load-modify-store instruction. When the root
5571 // node in a match is a store, isel doesn't know how to remap non-chain
5572 // non-flag uses of other nodes in the match, such as the ADD in this
5573 // case. This leads to the ADD being left around and reselected, with
5574 // the result being two adds in the output.
5575 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5576 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5577 if (UI->getOpcode() == ISD::STORE)
5579 if (ConstantSDNode *C =
5580 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5581 // An add of one will be selected as an INC.
5582 if (C->getAPIntValue() == 1) {
5583 Opcode = X86ISD::INC;
5587 // An add of negative one (subtract of one) will be selected as a DEC.
5588 if (C->getAPIntValue().isAllOnesValue()) {
5589 Opcode = X86ISD::DEC;
5594 // Otherwise use a regular EFLAGS-setting add.
5595 Opcode = X86ISD::ADD;
5599 // If the primary and result isn't used, don't bother using X86ISD::AND,
5600 // because a TEST instruction will be better.
5601 bool NonFlagUse = false;
5602 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5603 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5604 if (UI->getOpcode() != ISD::BRCOND &&
5605 UI->getOpcode() != ISD::SELECT &&
5606 UI->getOpcode() != ISD::SETCC) {
5617 // Due to the ISEL shortcoming noted above, be conservative if this op is
5618 // likely to be selected as part of a load-modify-store instruction.
5619 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5620 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5621 if (UI->getOpcode() == ISD::STORE)
5623 // Otherwise use a regular EFLAGS-setting instruction.
5624 switch (Op.getNode()->getOpcode()) {
5625 case ISD::SUB: Opcode = X86ISD::SUB; break;
5626 case ISD::OR: Opcode = X86ISD::OR; break;
5627 case ISD::XOR: Opcode = X86ISD::XOR; break;
5628 case ISD::AND: Opcode = X86ISD::AND; break;
5629 default: llvm_unreachable("unexpected operator!");
5640 return SDValue(Op.getNode(), 1);
5646 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5647 SmallVector<SDValue, 4> Ops;
5648 for (unsigned i = 0; i != NumOperands; ++i)
5649 Ops.push_back(Op.getOperand(i));
5650 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5651 DAG.ReplaceAllUsesWith(Op, New);
5652 return SDValue(New.getNode(), 1);
5656 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5657 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5658 DAG.getConstant(0, Op.getValueType()));
5661 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5663 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5664 SelectionDAG &DAG) {
5665 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5666 if (C->getAPIntValue() == 0)
5667 return EmitTest(Op0, X86CC, DAG);
5669 DebugLoc dl = Op0.getDebugLoc();
5670 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5673 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5674 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5675 SDValue Op0 = Op.getOperand(0);
5676 SDValue Op1 = Op.getOperand(1);
5677 DebugLoc dl = Op.getDebugLoc();
5678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5680 // Lower (X & (1 << N)) == 0 to BT(X, N).
5681 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5682 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5683 if (Op0.getOpcode() == ISD::AND &&
5685 Op1.getOpcode() == ISD::Constant &&
5686 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5687 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5689 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5690 if (ConstantSDNode *Op010C =
5691 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5692 if (Op010C->getZExtValue() == 1) {
5693 LHS = Op0.getOperand(0);
5694 RHS = Op0.getOperand(1).getOperand(1);
5696 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5697 if (ConstantSDNode *Op000C =
5698 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5699 if (Op000C->getZExtValue() == 1) {
5700 LHS = Op0.getOperand(1);
5701 RHS = Op0.getOperand(0).getOperand(1);
5703 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5704 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5705 SDValue AndLHS = Op0.getOperand(0);
5706 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5707 LHS = AndLHS.getOperand(0);
5708 RHS = AndLHS.getOperand(1);
5712 if (LHS.getNode()) {
5713 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5714 // instruction. Since the shift amount is in-range-or-undefined, we know
5715 // that doing a bittest on the i16 value is ok. We extend to i32 because
5716 // the encoding for the i16 version is larger than the i32 version.
5717 if (LHS.getValueType() == MVT::i8)
5718 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5720 // If the operand types disagree, extend the shift amount to match. Since
5721 // BT ignores high bits (like shifts) we can use anyextend.
5722 if (LHS.getValueType() != RHS.getValueType())
5723 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5725 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5726 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5727 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5728 DAG.getConstant(Cond, MVT::i8), BT);
5732 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5733 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5734 if (X86CC == X86::COND_INVALID)
5737 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5738 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5739 DAG.getConstant(X86CC, MVT::i8), Cond);
5742 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5744 SDValue Op0 = Op.getOperand(0);
5745 SDValue Op1 = Op.getOperand(1);
5746 SDValue CC = Op.getOperand(2);
5747 EVT VT = Op.getValueType();
5748 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5749 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5750 DebugLoc dl = Op.getDebugLoc();
5754 EVT VT0 = Op0.getValueType();
5755 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5756 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5759 switch (SetCCOpcode) {
5762 case ISD::SETEQ: SSECC = 0; break;
5764 case ISD::SETGT: Swap = true; // Fallthrough
5766 case ISD::SETOLT: SSECC = 1; break;
5768 case ISD::SETGE: Swap = true; // Fallthrough
5770 case ISD::SETOLE: SSECC = 2; break;
5771 case ISD::SETUO: SSECC = 3; break;
5773 case ISD::SETNE: SSECC = 4; break;
5774 case ISD::SETULE: Swap = true;
5775 case ISD::SETUGE: SSECC = 5; break;
5776 case ISD::SETULT: Swap = true;
5777 case ISD::SETUGT: SSECC = 6; break;
5778 case ISD::SETO: SSECC = 7; break;
5781 std::swap(Op0, Op1);
5783 // In the two special cases we can't handle, emit two comparisons.
5785 if (SetCCOpcode == ISD::SETUEQ) {
5787 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5788 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5789 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5791 else if (SetCCOpcode == ISD::SETONE) {
5793 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5794 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5795 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5797 llvm_unreachable("Illegal FP comparison");
5799 // Handle all other FP comparisons here.
5800 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5803 // We are handling one of the integer comparisons here. Since SSE only has
5804 // GT and EQ comparisons for integer, swapping operands and multiple
5805 // operations may be required for some comparisons.
5806 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5807 bool Swap = false, Invert = false, FlipSigns = false;
5809 switch (VT.getSimpleVT().SimpleTy) {
5812 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5814 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5816 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5817 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5820 switch (SetCCOpcode) {
5822 case ISD::SETNE: Invert = true;
5823 case ISD::SETEQ: Opc = EQOpc; break;
5824 case ISD::SETLT: Swap = true;
5825 case ISD::SETGT: Opc = GTOpc; break;
5826 case ISD::SETGE: Swap = true;
5827 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5828 case ISD::SETULT: Swap = true;
5829 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5830 case ISD::SETUGE: Swap = true;
5831 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5834 std::swap(Op0, Op1);
5836 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5837 // bits of the inputs before performing those operations.
5839 EVT EltVT = VT.getVectorElementType();
5840 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5842 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5843 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5845 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5846 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5849 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5851 // If the logical-not of the result is required, perform that now.
5853 Result = DAG.getNOT(dl, Result, VT);
5858 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5859 static bool isX86LogicalCmp(SDValue Op) {
5860 unsigned Opc = Op.getNode()->getOpcode();
5861 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5863 if (Op.getResNo() == 1 &&
5864 (Opc == X86ISD::ADD ||
5865 Opc == X86ISD::SUB ||
5866 Opc == X86ISD::SMUL ||
5867 Opc == X86ISD::UMUL ||
5868 Opc == X86ISD::INC ||
5869 Opc == X86ISD::DEC ||
5870 Opc == X86ISD::OR ||
5871 Opc == X86ISD::XOR ||
5872 Opc == X86ISD::AND))
5878 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5879 bool addTest = true;
5880 SDValue Cond = Op.getOperand(0);
5881 DebugLoc dl = Op.getDebugLoc();
5884 if (Cond.getOpcode() == ISD::SETCC) {
5885 SDValue NewCond = LowerSETCC(Cond, DAG);
5886 if (NewCond.getNode())
5890 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5891 // setting operand in place of the X86ISD::SETCC.
5892 if (Cond.getOpcode() == X86ISD::SETCC) {
5893 CC = Cond.getOperand(0);
5895 SDValue Cmp = Cond.getOperand(1);
5896 unsigned Opc = Cmp.getOpcode();
5897 EVT VT = Op.getValueType();
5899 bool IllegalFPCMov = false;
5900 if (VT.isFloatingPoint() && !VT.isVector() &&
5901 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5902 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5904 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5905 Opc == X86ISD::BT) { // FIXME
5912 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5913 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5916 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5917 SmallVector<SDValue, 4> Ops;
5918 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5919 // condition is true.
5920 Ops.push_back(Op.getOperand(2));
5921 Ops.push_back(Op.getOperand(1));
5923 Ops.push_back(Cond);
5924 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5927 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5928 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5929 // from the AND / OR.
5930 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5931 Opc = Op.getOpcode();
5932 if (Opc != ISD::OR && Opc != ISD::AND)
5934 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5935 Op.getOperand(0).hasOneUse() &&
5936 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5937 Op.getOperand(1).hasOneUse());
5940 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5941 // 1 and that the SETCC node has a single use.
5942 static bool isXor1OfSetCC(SDValue Op) {
5943 if (Op.getOpcode() != ISD::XOR)
5945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5946 if (N1C && N1C->getAPIntValue() == 1) {
5947 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5948 Op.getOperand(0).hasOneUse();
5953 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5954 bool addTest = true;
5955 SDValue Chain = Op.getOperand(0);
5956 SDValue Cond = Op.getOperand(1);
5957 SDValue Dest = Op.getOperand(2);
5958 DebugLoc dl = Op.getDebugLoc();
5961 if (Cond.getOpcode() == ISD::SETCC) {
5962 SDValue NewCond = LowerSETCC(Cond, DAG);
5963 if (NewCond.getNode())
5967 // FIXME: LowerXALUO doesn't handle these!!
5968 else if (Cond.getOpcode() == X86ISD::ADD ||
5969 Cond.getOpcode() == X86ISD::SUB ||
5970 Cond.getOpcode() == X86ISD::SMUL ||
5971 Cond.getOpcode() == X86ISD::UMUL)
5972 Cond = LowerXALUO(Cond, DAG);
5975 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5976 // setting operand in place of the X86ISD::SETCC.
5977 if (Cond.getOpcode() == X86ISD::SETCC) {
5978 CC = Cond.getOperand(0);
5980 SDValue Cmp = Cond.getOperand(1);
5981 unsigned Opc = Cmp.getOpcode();
5982 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5983 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5987 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5991 // These can only come from an arithmetic instruction with overflow,
5992 // e.g. SADDO, UADDO.
5993 Cond = Cond.getNode()->getOperand(1);
6000 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6001 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6002 if (CondOpc == ISD::OR) {
6003 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6004 // two branches instead of an explicit OR instruction with a
6006 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6007 isX86LogicalCmp(Cmp)) {
6008 CC = Cond.getOperand(0).getOperand(0);
6009 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6010 Chain, Dest, CC, Cmp);
6011 CC = Cond.getOperand(1).getOperand(0);
6015 } else { // ISD::AND
6016 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6017 // two branches instead of an explicit AND instruction with a
6018 // separate test. However, we only do this if this block doesn't
6019 // have a fall-through edge, because this requires an explicit
6020 // jmp when the condition is false.
6021 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6022 isX86LogicalCmp(Cmp) &&
6023 Op.getNode()->hasOneUse()) {
6024 X86::CondCode CCode =
6025 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6026 CCode = X86::GetOppositeBranchCondition(CCode);
6027 CC = DAG.getConstant(CCode, MVT::i8);
6028 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6029 // Look for an unconditional branch following this conditional branch.
6030 // We need this because we need to reverse the successors in order
6031 // to implement FCMP_OEQ.
6032 if (User.getOpcode() == ISD::BR) {
6033 SDValue FalseBB = User.getOperand(1);
6035 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6036 assert(NewBR == User);
6039 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6040 Chain, Dest, CC, Cmp);
6041 X86::CondCode CCode =
6042 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6043 CCode = X86::GetOppositeBranchCondition(CCode);
6044 CC = DAG.getConstant(CCode, MVT::i8);
6050 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6051 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6052 // It should be transformed during dag combiner except when the condition
6053 // is set by a arithmetics with overflow node.
6054 X86::CondCode CCode =
6055 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6056 CCode = X86::GetOppositeBranchCondition(CCode);
6057 CC = DAG.getConstant(CCode, MVT::i8);
6058 Cond = Cond.getOperand(0).getOperand(1);
6064 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6065 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6067 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6068 Chain, Dest, CC, Cond);
6072 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6073 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6074 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6075 // that the guard pages used by the OS virtual memory manager are allocated in
6076 // correct sequence.
6078 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6079 SelectionDAG &DAG) {
6080 assert(Subtarget->isTargetCygMing() &&
6081 "This should be used only on Cygwin/Mingw targets");
6082 DebugLoc dl = Op.getDebugLoc();
6085 SDValue Chain = Op.getOperand(0);
6086 SDValue Size = Op.getOperand(1);
6087 // FIXME: Ensure alignment here
6091 EVT IntPtr = getPointerTy();
6092 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6094 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6096 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6097 Flag = Chain.getValue(1);
6099 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6100 SDValue Ops[] = { Chain,
6101 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6102 DAG.getRegister(X86::EAX, IntPtr),
6103 DAG.getRegister(X86StackPtr, SPTy),
6105 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6106 Flag = Chain.getValue(1);
6108 Chain = DAG.getCALLSEQ_END(Chain,
6109 DAG.getIntPtrConstant(0, true),
6110 DAG.getIntPtrConstant(0, true),
6113 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6115 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6116 return DAG.getMergeValues(Ops1, 2, dl);
6120 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6122 SDValue Dst, SDValue Src,
6123 SDValue Size, unsigned Align,
6125 uint64_t DstSVOff) {
6126 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6128 // If not DWORD aligned or size is more than the threshold, call the library.
6129 // The libc version is likely to be faster for these cases. It can use the
6130 // address value and run time information about the CPU.
6131 if ((Align & 3) != 0 ||
6133 ConstantSize->getZExtValue() >
6134 getSubtarget()->getMaxInlineSizeThreshold()) {
6135 SDValue InFlag(0, 0);
6137 // Check to see if there is a specialized entry-point for memory zeroing.
6138 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6140 if (const char *bzeroEntry = V &&
6141 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6142 EVT IntPtr = getPointerTy();
6143 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6144 TargetLowering::ArgListTy Args;
6145 TargetLowering::ArgListEntry Entry;
6147 Entry.Ty = IntPtrTy;
6148 Args.push_back(Entry);
6150 Args.push_back(Entry);
6151 std::pair<SDValue,SDValue> CallResult =
6152 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6153 false, false, false, false,
6154 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6155 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6156 return CallResult.second;
6159 // Otherwise have the target-independent code call memset.
6163 uint64_t SizeVal = ConstantSize->getZExtValue();
6164 SDValue InFlag(0, 0);
6167 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6168 unsigned BytesLeft = 0;
6169 bool TwoRepStos = false;
6172 uint64_t Val = ValC->getZExtValue() & 255;
6174 // If the value is a constant, then we can potentially use larger sets.
6175 switch (Align & 3) {
6176 case 2: // WORD aligned
6179 Val = (Val << 8) | Val;
6181 case 0: // DWORD aligned
6184 Val = (Val << 8) | Val;
6185 Val = (Val << 16) | Val;
6186 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6189 Val = (Val << 32) | Val;
6192 default: // Byte aligned
6195 Count = DAG.getIntPtrConstant(SizeVal);
6199 if (AVT.bitsGT(MVT::i8)) {
6200 unsigned UBytes = AVT.getSizeInBits() / 8;
6201 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6202 BytesLeft = SizeVal % UBytes;
6205 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6207 InFlag = Chain.getValue(1);
6210 Count = DAG.getIntPtrConstant(SizeVal);
6211 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6212 InFlag = Chain.getValue(1);
6215 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6218 InFlag = Chain.getValue(1);
6219 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6222 InFlag = Chain.getValue(1);
6224 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6225 SmallVector<SDValue, 8> Ops;
6226 Ops.push_back(Chain);
6227 Ops.push_back(DAG.getValueType(AVT));
6228 Ops.push_back(InFlag);
6229 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6232 InFlag = Chain.getValue(1);
6234 EVT CVT = Count.getValueType();
6235 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6236 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6237 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6240 InFlag = Chain.getValue(1);
6241 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6243 Ops.push_back(Chain);
6244 Ops.push_back(DAG.getValueType(MVT::i8));
6245 Ops.push_back(InFlag);
6246 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6247 } else if (BytesLeft) {
6248 // Handle the last 1 - 7 bytes.
6249 unsigned Offset = SizeVal - BytesLeft;
6250 EVT AddrVT = Dst.getValueType();
6251 EVT SizeVT = Size.getValueType();
6253 Chain = DAG.getMemset(Chain, dl,
6254 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6255 DAG.getConstant(Offset, AddrVT)),
6257 DAG.getConstant(BytesLeft, SizeVT),
6258 Align, DstSV, DstSVOff + Offset);
6261 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6266 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6267 SDValue Chain, SDValue Dst, SDValue Src,
6268 SDValue Size, unsigned Align,
6270 const Value *DstSV, uint64_t DstSVOff,
6271 const Value *SrcSV, uint64_t SrcSVOff) {
6272 // This requires the copy size to be a constant, preferrably
6273 // within a subtarget-specific limit.
6274 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6277 uint64_t SizeVal = ConstantSize->getZExtValue();
6278 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6281 /// If not DWORD aligned, call the library.
6282 if ((Align & 3) != 0)
6287 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6290 unsigned UBytes = AVT.getSizeInBits() / 8;
6291 unsigned CountVal = SizeVal / UBytes;
6292 SDValue Count = DAG.getIntPtrConstant(CountVal);
6293 unsigned BytesLeft = SizeVal % UBytes;
6295 SDValue InFlag(0, 0);
6296 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6299 InFlag = Chain.getValue(1);
6300 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6303 InFlag = Chain.getValue(1);
6304 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6307 InFlag = Chain.getValue(1);
6309 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6310 SmallVector<SDValue, 8> Ops;
6311 Ops.push_back(Chain);
6312 Ops.push_back(DAG.getValueType(AVT));
6313 Ops.push_back(InFlag);
6314 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6316 SmallVector<SDValue, 4> Results;
6317 Results.push_back(RepMovs);
6319 // Handle the last 1 - 7 bytes.
6320 unsigned Offset = SizeVal - BytesLeft;
6321 EVT DstVT = Dst.getValueType();
6322 EVT SrcVT = Src.getValueType();
6323 EVT SizeVT = Size.getValueType();
6324 Results.push_back(DAG.getMemcpy(Chain, dl,
6325 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6326 DAG.getConstant(Offset, DstVT)),
6327 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6328 DAG.getConstant(Offset, SrcVT)),
6329 DAG.getConstant(BytesLeft, SizeVT),
6330 Align, AlwaysInline,
6331 DstSV, DstSVOff + Offset,
6332 SrcSV, SrcSVOff + Offset));
6335 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6336 &Results[0], Results.size());
6339 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6340 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6341 DebugLoc dl = Op.getDebugLoc();
6343 if (!Subtarget->is64Bit()) {
6344 // vastart just stores the address of the VarArgsFrameIndex slot into the
6345 // memory location argument.
6346 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6347 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6351 // gp_offset (0 - 6 * 8)
6352 // fp_offset (48 - 48 + 8 * 16)
6353 // overflow_arg_area (point to parameters coming in memory).
6355 SmallVector<SDValue, 8> MemOps;
6356 SDValue FIN = Op.getOperand(1);
6358 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6359 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6361 MemOps.push_back(Store);
6364 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6365 FIN, DAG.getIntPtrConstant(4));
6366 Store = DAG.getStore(Op.getOperand(0), dl,
6367 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6369 MemOps.push_back(Store);
6371 // Store ptr to overflow_arg_area
6372 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6373 FIN, DAG.getIntPtrConstant(4));
6374 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6375 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6376 MemOps.push_back(Store);
6378 // Store ptr to reg_save_area.
6379 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6380 FIN, DAG.getIntPtrConstant(8));
6381 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6382 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6383 MemOps.push_back(Store);
6384 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6385 &MemOps[0], MemOps.size());
6388 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6389 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6390 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6391 SDValue Chain = Op.getOperand(0);
6392 SDValue SrcPtr = Op.getOperand(1);
6393 SDValue SrcSV = Op.getOperand(2);
6395 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6399 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6400 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6401 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6402 SDValue Chain = Op.getOperand(0);
6403 SDValue DstPtr = Op.getOperand(1);
6404 SDValue SrcPtr = Op.getOperand(2);
6405 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6406 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6407 DebugLoc dl = Op.getDebugLoc();
6409 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6410 DAG.getIntPtrConstant(24), 8, false,
6411 DstSV, 0, SrcSV, 0);
6415 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6416 DebugLoc dl = Op.getDebugLoc();
6417 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6419 default: return SDValue(); // Don't custom lower most intrinsics.
6420 // Comparison intrinsics.
6421 case Intrinsic::x86_sse_comieq_ss:
6422 case Intrinsic::x86_sse_comilt_ss:
6423 case Intrinsic::x86_sse_comile_ss:
6424 case Intrinsic::x86_sse_comigt_ss:
6425 case Intrinsic::x86_sse_comige_ss:
6426 case Intrinsic::x86_sse_comineq_ss:
6427 case Intrinsic::x86_sse_ucomieq_ss:
6428 case Intrinsic::x86_sse_ucomilt_ss:
6429 case Intrinsic::x86_sse_ucomile_ss:
6430 case Intrinsic::x86_sse_ucomigt_ss:
6431 case Intrinsic::x86_sse_ucomige_ss:
6432 case Intrinsic::x86_sse_ucomineq_ss:
6433 case Intrinsic::x86_sse2_comieq_sd:
6434 case Intrinsic::x86_sse2_comilt_sd:
6435 case Intrinsic::x86_sse2_comile_sd:
6436 case Intrinsic::x86_sse2_comigt_sd:
6437 case Intrinsic::x86_sse2_comige_sd:
6438 case Intrinsic::x86_sse2_comineq_sd:
6439 case Intrinsic::x86_sse2_ucomieq_sd:
6440 case Intrinsic::x86_sse2_ucomilt_sd:
6441 case Intrinsic::x86_sse2_ucomile_sd:
6442 case Intrinsic::x86_sse2_ucomigt_sd:
6443 case Intrinsic::x86_sse2_ucomige_sd:
6444 case Intrinsic::x86_sse2_ucomineq_sd: {
6446 ISD::CondCode CC = ISD::SETCC_INVALID;
6449 case Intrinsic::x86_sse_comieq_ss:
6450 case Intrinsic::x86_sse2_comieq_sd:
6454 case Intrinsic::x86_sse_comilt_ss:
6455 case Intrinsic::x86_sse2_comilt_sd:
6459 case Intrinsic::x86_sse_comile_ss:
6460 case Intrinsic::x86_sse2_comile_sd:
6464 case Intrinsic::x86_sse_comigt_ss:
6465 case Intrinsic::x86_sse2_comigt_sd:
6469 case Intrinsic::x86_sse_comige_ss:
6470 case Intrinsic::x86_sse2_comige_sd:
6474 case Intrinsic::x86_sse_comineq_ss:
6475 case Intrinsic::x86_sse2_comineq_sd:
6479 case Intrinsic::x86_sse_ucomieq_ss:
6480 case Intrinsic::x86_sse2_ucomieq_sd:
6481 Opc = X86ISD::UCOMI;
6484 case Intrinsic::x86_sse_ucomilt_ss:
6485 case Intrinsic::x86_sse2_ucomilt_sd:
6486 Opc = X86ISD::UCOMI;
6489 case Intrinsic::x86_sse_ucomile_ss:
6490 case Intrinsic::x86_sse2_ucomile_sd:
6491 Opc = X86ISD::UCOMI;
6494 case Intrinsic::x86_sse_ucomigt_ss:
6495 case Intrinsic::x86_sse2_ucomigt_sd:
6496 Opc = X86ISD::UCOMI;
6499 case Intrinsic::x86_sse_ucomige_ss:
6500 case Intrinsic::x86_sse2_ucomige_sd:
6501 Opc = X86ISD::UCOMI;
6504 case Intrinsic::x86_sse_ucomineq_ss:
6505 case Intrinsic::x86_sse2_ucomineq_sd:
6506 Opc = X86ISD::UCOMI;
6511 SDValue LHS = Op.getOperand(1);
6512 SDValue RHS = Op.getOperand(2);
6513 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6514 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6515 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6516 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6517 DAG.getConstant(X86CC, MVT::i8), Cond);
6518 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6520 // ptest intrinsics. The intrinsic these come from are designed to return
6521 // an integer value, not just an instruction so lower it to the ptest
6522 // pattern and a setcc for the result.
6523 case Intrinsic::x86_sse41_ptestz:
6524 case Intrinsic::x86_sse41_ptestc:
6525 case Intrinsic::x86_sse41_ptestnzc:{
6528 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6529 case Intrinsic::x86_sse41_ptestz:
6531 X86CC = X86::COND_E;
6533 case Intrinsic::x86_sse41_ptestc:
6535 X86CC = X86::COND_B;
6537 case Intrinsic::x86_sse41_ptestnzc:
6539 X86CC = X86::COND_A;
6543 SDValue LHS = Op.getOperand(1);
6544 SDValue RHS = Op.getOperand(2);
6545 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6546 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6547 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6548 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6551 // Fix vector shift instructions where the last operand is a non-immediate
6553 case Intrinsic::x86_sse2_pslli_w:
6554 case Intrinsic::x86_sse2_pslli_d:
6555 case Intrinsic::x86_sse2_pslli_q:
6556 case Intrinsic::x86_sse2_psrli_w:
6557 case Intrinsic::x86_sse2_psrli_d:
6558 case Intrinsic::x86_sse2_psrli_q:
6559 case Intrinsic::x86_sse2_psrai_w:
6560 case Intrinsic::x86_sse2_psrai_d:
6561 case Intrinsic::x86_mmx_pslli_w:
6562 case Intrinsic::x86_mmx_pslli_d:
6563 case Intrinsic::x86_mmx_pslli_q:
6564 case Intrinsic::x86_mmx_psrli_w:
6565 case Intrinsic::x86_mmx_psrli_d:
6566 case Intrinsic::x86_mmx_psrli_q:
6567 case Intrinsic::x86_mmx_psrai_w:
6568 case Intrinsic::x86_mmx_psrai_d: {
6569 SDValue ShAmt = Op.getOperand(2);
6570 if (isa<ConstantSDNode>(ShAmt))
6573 unsigned NewIntNo = 0;
6574 EVT ShAmtVT = MVT::v4i32;
6576 case Intrinsic::x86_sse2_pslli_w:
6577 NewIntNo = Intrinsic::x86_sse2_psll_w;
6579 case Intrinsic::x86_sse2_pslli_d:
6580 NewIntNo = Intrinsic::x86_sse2_psll_d;
6582 case Intrinsic::x86_sse2_pslli_q:
6583 NewIntNo = Intrinsic::x86_sse2_psll_q;
6585 case Intrinsic::x86_sse2_psrli_w:
6586 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6588 case Intrinsic::x86_sse2_psrli_d:
6589 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6591 case Intrinsic::x86_sse2_psrli_q:
6592 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6594 case Intrinsic::x86_sse2_psrai_w:
6595 NewIntNo = Intrinsic::x86_sse2_psra_w;
6597 case Intrinsic::x86_sse2_psrai_d:
6598 NewIntNo = Intrinsic::x86_sse2_psra_d;
6601 ShAmtVT = MVT::v2i32;
6603 case Intrinsic::x86_mmx_pslli_w:
6604 NewIntNo = Intrinsic::x86_mmx_psll_w;
6606 case Intrinsic::x86_mmx_pslli_d:
6607 NewIntNo = Intrinsic::x86_mmx_psll_d;
6609 case Intrinsic::x86_mmx_pslli_q:
6610 NewIntNo = Intrinsic::x86_mmx_psll_q;
6612 case Intrinsic::x86_mmx_psrli_w:
6613 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6615 case Intrinsic::x86_mmx_psrli_d:
6616 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6618 case Intrinsic::x86_mmx_psrli_q:
6619 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6621 case Intrinsic::x86_mmx_psrai_w:
6622 NewIntNo = Intrinsic::x86_mmx_psra_w;
6624 case Intrinsic::x86_mmx_psrai_d:
6625 NewIntNo = Intrinsic::x86_mmx_psra_d;
6627 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6633 // The vector shift intrinsics with scalars uses 32b shift amounts but
6634 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6638 ShOps[1] = DAG.getConstant(0, MVT::i32);
6639 if (ShAmtVT == MVT::v4i32) {
6640 ShOps[2] = DAG.getUNDEF(MVT::i32);
6641 ShOps[3] = DAG.getUNDEF(MVT::i32);
6642 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6644 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6647 EVT VT = Op.getValueType();
6648 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6649 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6650 DAG.getConstant(NewIntNo, MVT::i32),
6651 Op.getOperand(1), ShAmt);
6656 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6657 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6658 DebugLoc dl = Op.getDebugLoc();
6661 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6663 DAG.getConstant(TD->getPointerSize(),
6664 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6665 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6666 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6671 // Just load the return address.
6672 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6673 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6674 RetAddrFI, NULL, 0);
6677 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6678 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6679 MFI->setFrameAddressIsTaken(true);
6680 EVT VT = Op.getValueType();
6681 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6682 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6683 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6684 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6686 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6690 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6691 SelectionDAG &DAG) {
6692 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6695 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6697 MachineFunction &MF = DAG.getMachineFunction();
6698 SDValue Chain = Op.getOperand(0);
6699 SDValue Offset = Op.getOperand(1);
6700 SDValue Handler = Op.getOperand(2);
6701 DebugLoc dl = Op.getDebugLoc();
6703 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6705 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6707 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6708 DAG.getIntPtrConstant(-TD->getPointerSize()));
6709 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6710 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6711 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6712 MF.getRegInfo().addLiveOut(StoreAddrReg);
6714 return DAG.getNode(X86ISD::EH_RETURN, dl,
6716 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6719 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6720 SelectionDAG &DAG) {
6721 SDValue Root = Op.getOperand(0);
6722 SDValue Trmp = Op.getOperand(1); // trampoline
6723 SDValue FPtr = Op.getOperand(2); // nested function
6724 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6725 DebugLoc dl = Op.getDebugLoc();
6727 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6729 const X86InstrInfo *TII =
6730 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6732 if (Subtarget->is64Bit()) {
6733 SDValue OutChains[6];
6735 // Large code-model.
6737 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6738 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6740 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6741 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6743 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6745 // Load the pointer to the nested function into R11.
6746 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6747 SDValue Addr = Trmp;
6748 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6751 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6752 DAG.getConstant(2, MVT::i64));
6753 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6755 // Load the 'nest' parameter value into R10.
6756 // R10 is specified in X86CallingConv.td
6757 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6758 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6759 DAG.getConstant(10, MVT::i64));
6760 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6761 Addr, TrmpAddr, 10);
6763 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6764 DAG.getConstant(12, MVT::i64));
6765 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6767 // Jump to the nested function.
6768 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6769 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6770 DAG.getConstant(20, MVT::i64));
6771 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6772 Addr, TrmpAddr, 20);
6774 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6775 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6776 DAG.getConstant(22, MVT::i64));
6777 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6781 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6782 return DAG.getMergeValues(Ops, 2, dl);
6784 const Function *Func =
6785 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6786 CallingConv::ID CC = Func->getCallingConv();
6791 llvm_unreachable("Unsupported calling convention");
6792 case CallingConv::C:
6793 case CallingConv::X86_StdCall: {
6794 // Pass 'nest' parameter in ECX.
6795 // Must be kept in sync with X86CallingConv.td
6798 // Check that ECX wasn't needed by an 'inreg' parameter.
6799 const FunctionType *FTy = Func->getFunctionType();
6800 const AttrListPtr &Attrs = Func->getAttributes();
6802 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6803 unsigned InRegCount = 0;
6806 for (FunctionType::param_iterator I = FTy->param_begin(),
6807 E = FTy->param_end(); I != E; ++I, ++Idx)
6808 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6809 // FIXME: should only count parameters that are lowered to integers.
6810 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6812 if (InRegCount > 2) {
6813 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6818 case CallingConv::X86_FastCall:
6819 case CallingConv::Fast:
6820 // Pass 'nest' parameter in EAX.
6821 // Must be kept in sync with X86CallingConv.td
6826 SDValue OutChains[4];
6829 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6830 DAG.getConstant(10, MVT::i32));
6831 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6833 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6834 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6835 OutChains[0] = DAG.getStore(Root, dl,
6836 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6839 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6840 DAG.getConstant(1, MVT::i32));
6841 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6843 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6844 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6845 DAG.getConstant(5, MVT::i32));
6846 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6847 TrmpAddr, 5, false, 1);
6849 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6850 DAG.getConstant(6, MVT::i32));
6851 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6854 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6855 return DAG.getMergeValues(Ops, 2, dl);
6859 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6861 The rounding mode is in bits 11:10 of FPSR, and has the following
6868 FLT_ROUNDS, on the other hand, expects the following:
6875 To perform the conversion, we do:
6876 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6879 MachineFunction &MF = DAG.getMachineFunction();
6880 const TargetMachine &TM = MF.getTarget();
6881 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6882 unsigned StackAlignment = TFI.getStackAlignment();
6883 EVT VT = Op.getValueType();
6884 DebugLoc dl = Op.getDebugLoc();
6886 // Save FP Control Word to stack slot
6887 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
6888 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6890 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6891 DAG.getEntryNode(), StackSlot);
6893 // Load FP Control Word from stack slot
6894 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6896 // Transform as necessary
6898 DAG.getNode(ISD::SRL, dl, MVT::i16,
6899 DAG.getNode(ISD::AND, dl, MVT::i16,
6900 CWD, DAG.getConstant(0x800, MVT::i16)),
6901 DAG.getConstant(11, MVT::i8));
6903 DAG.getNode(ISD::SRL, dl, MVT::i16,
6904 DAG.getNode(ISD::AND, dl, MVT::i16,
6905 CWD, DAG.getConstant(0x400, MVT::i16)),
6906 DAG.getConstant(9, MVT::i8));
6909 DAG.getNode(ISD::AND, dl, MVT::i16,
6910 DAG.getNode(ISD::ADD, dl, MVT::i16,
6911 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6912 DAG.getConstant(1, MVT::i16)),
6913 DAG.getConstant(3, MVT::i16));
6916 return DAG.getNode((VT.getSizeInBits() < 16 ?
6917 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6920 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6921 EVT VT = Op.getValueType();
6923 unsigned NumBits = VT.getSizeInBits();
6924 DebugLoc dl = Op.getDebugLoc();
6926 Op = Op.getOperand(0);
6927 if (VT == MVT::i8) {
6928 // Zero extend to i32 since there is not an i8 bsr.
6930 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6933 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6934 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6935 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6937 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6938 SmallVector<SDValue, 4> Ops;
6940 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6941 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6942 Ops.push_back(Op.getValue(1));
6943 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6945 // Finally xor with NumBits-1.
6946 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6949 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6953 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6954 EVT VT = Op.getValueType();
6956 unsigned NumBits = VT.getSizeInBits();
6957 DebugLoc dl = Op.getDebugLoc();
6959 Op = Op.getOperand(0);
6960 if (VT == MVT::i8) {
6962 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6965 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6966 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6967 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6969 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6970 SmallVector<SDValue, 4> Ops;
6972 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6973 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6974 Ops.push_back(Op.getValue(1));
6975 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6978 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6982 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6983 EVT VT = Op.getValueType();
6984 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6985 DebugLoc dl = Op.getDebugLoc();
6987 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6988 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6989 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6990 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6991 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6993 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6994 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6995 // return AloBlo + AloBhi + AhiBlo;
6997 SDValue A = Op.getOperand(0);
6998 SDValue B = Op.getOperand(1);
7000 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7001 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7002 A, DAG.getConstant(32, MVT::i32));
7003 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7004 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7005 B, DAG.getConstant(32, MVT::i32));
7006 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7007 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7009 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7010 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7012 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7013 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7015 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7016 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7017 AloBhi, DAG.getConstant(32, MVT::i32));
7018 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7019 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7020 AhiBlo, DAG.getConstant(32, MVT::i32));
7021 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7022 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7027 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7028 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7029 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7030 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7031 // has only one use.
7032 SDNode *N = Op.getNode();
7033 SDValue LHS = N->getOperand(0);
7034 SDValue RHS = N->getOperand(1);
7035 unsigned BaseOp = 0;
7037 DebugLoc dl = Op.getDebugLoc();
7039 switch (Op.getOpcode()) {
7040 default: llvm_unreachable("Unknown ovf instruction!");
7042 // A subtract of one will be selected as a INC. Note that INC doesn't
7043 // set CF, so we can't do this for UADDO.
7044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7045 if (C->getAPIntValue() == 1) {
7046 BaseOp = X86ISD::INC;
7050 BaseOp = X86ISD::ADD;
7054 BaseOp = X86ISD::ADD;
7058 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7059 // set CF, so we can't do this for USUBO.
7060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7061 if (C->getAPIntValue() == 1) {
7062 BaseOp = X86ISD::DEC;
7066 BaseOp = X86ISD::SUB;
7070 BaseOp = X86ISD::SUB;
7074 BaseOp = X86ISD::SMUL;
7078 BaseOp = X86ISD::UMUL;
7083 // Also sets EFLAGS.
7084 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7085 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7088 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7089 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7091 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7095 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7096 EVT T = Op.getValueType();
7097 DebugLoc dl = Op.getDebugLoc();
7100 switch(T.getSimpleVT().SimpleTy) {
7102 assert(false && "Invalid value type!");
7103 case MVT::i8: Reg = X86::AL; size = 1; break;
7104 case MVT::i16: Reg = X86::AX; size = 2; break;
7105 case MVT::i32: Reg = X86::EAX; size = 4; break;
7107 assert(Subtarget->is64Bit() && "Node not type legal!");
7108 Reg = X86::RAX; size = 8;
7111 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7112 Op.getOperand(2), SDValue());
7113 SDValue Ops[] = { cpIn.getValue(0),
7116 DAG.getTargetConstant(size, MVT::i8),
7118 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7119 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7121 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7125 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7126 SelectionDAG &DAG) {
7127 assert(Subtarget->is64Bit() && "Result not type legalized?");
7128 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7129 SDValue TheChain = Op.getOperand(0);
7130 DebugLoc dl = Op.getDebugLoc();
7131 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7132 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7133 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7135 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7136 DAG.getConstant(32, MVT::i8));
7138 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7141 return DAG.getMergeValues(Ops, 2, dl);
7144 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7145 SDNode *Node = Op.getNode();
7146 DebugLoc dl = Node->getDebugLoc();
7147 EVT T = Node->getValueType(0);
7148 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7149 DAG.getConstant(0, T), Node->getOperand(2));
7150 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7151 cast<AtomicSDNode>(Node)->getMemoryVT(),
7152 Node->getOperand(0),
7153 Node->getOperand(1), negOp,
7154 cast<AtomicSDNode>(Node)->getSrcValue(),
7155 cast<AtomicSDNode>(Node)->getAlignment());
7158 /// LowerOperation - Provide custom lowering hooks for some operations.
7160 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7161 switch (Op.getOpcode()) {
7162 default: llvm_unreachable("Should not custom lower this!");
7163 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7164 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7165 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7166 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7167 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7168 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7169 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7171 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7172 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7173 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7174 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7175 case ISD::SHL_PARTS:
7176 case ISD::SRA_PARTS:
7177 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7178 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7179 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7180 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7181 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7182 case ISD::FABS: return LowerFABS(Op, DAG);
7183 case ISD::FNEG: return LowerFNEG(Op, DAG);
7184 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7185 case ISD::SETCC: return LowerSETCC(Op, DAG);
7186 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7187 case ISD::SELECT: return LowerSELECT(Op, DAG);
7188 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7189 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7190 case ISD::VASTART: return LowerVASTART(Op, DAG);
7191 case ISD::VAARG: return LowerVAARG(Op, DAG);
7192 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7193 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7194 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7195 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7196 case ISD::FRAME_TO_ARGS_OFFSET:
7197 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7198 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7199 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7200 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7201 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7202 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7203 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7204 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7210 case ISD::UMULO: return LowerXALUO(Op, DAG);
7211 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7215 void X86TargetLowering::
7216 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7217 SelectionDAG &DAG, unsigned NewOp) {
7218 EVT T = Node->getValueType(0);
7219 DebugLoc dl = Node->getDebugLoc();
7220 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7222 SDValue Chain = Node->getOperand(0);
7223 SDValue In1 = Node->getOperand(1);
7224 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7225 Node->getOperand(2), DAG.getIntPtrConstant(0));
7226 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7227 Node->getOperand(2), DAG.getIntPtrConstant(1));
7228 SDValue Ops[] = { Chain, In1, In2L, In2H };
7229 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7231 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7232 cast<MemSDNode>(Node)->getMemOperand());
7233 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7234 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7235 Results.push_back(Result.getValue(2));
7238 /// ReplaceNodeResults - Replace a node with an illegal result type
7239 /// with a new node built out of custom code.
7240 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7241 SmallVectorImpl<SDValue>&Results,
7242 SelectionDAG &DAG) {
7243 DebugLoc dl = N->getDebugLoc();
7244 switch (N->getOpcode()) {
7246 assert(false && "Do not know how to custom type legalize this operation!");
7248 case ISD::FP_TO_SINT: {
7249 std::pair<SDValue,SDValue> Vals =
7250 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7251 SDValue FIST = Vals.first, StackSlot = Vals.second;
7252 if (FIST.getNode() != 0) {
7253 EVT VT = N->getValueType(0);
7254 // Return a load from the stack slot.
7255 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7259 case ISD::READCYCLECOUNTER: {
7260 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7261 SDValue TheChain = N->getOperand(0);
7262 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7263 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7265 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7267 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7268 SDValue Ops[] = { eax, edx };
7269 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7270 Results.push_back(edx.getValue(1));
7277 EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7278 Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7281 case ISD::ATOMIC_CMP_SWAP: {
7282 EVT T = N->getValueType(0);
7283 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7284 SDValue cpInL, cpInH;
7285 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7286 DAG.getConstant(0, MVT::i32));
7287 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7288 DAG.getConstant(1, MVT::i32));
7289 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7290 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7292 SDValue swapInL, swapInH;
7293 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7294 DAG.getConstant(0, MVT::i32));
7295 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7296 DAG.getConstant(1, MVT::i32));
7297 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7299 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7300 swapInL.getValue(1));
7301 SDValue Ops[] = { swapInH.getValue(0),
7303 swapInH.getValue(1) };
7304 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7305 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7306 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7307 MVT::i32, Result.getValue(1));
7308 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7309 MVT::i32, cpOutL.getValue(2));
7310 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7311 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7312 Results.push_back(cpOutH.getValue(1));
7315 case ISD::ATOMIC_LOAD_ADD:
7316 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7318 case ISD::ATOMIC_LOAD_AND:
7319 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7321 case ISD::ATOMIC_LOAD_NAND:
7322 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7324 case ISD::ATOMIC_LOAD_OR:
7325 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7327 case ISD::ATOMIC_LOAD_SUB:
7328 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7330 case ISD::ATOMIC_LOAD_XOR:
7331 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7333 case ISD::ATOMIC_SWAP:
7334 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7339 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7341 default: return NULL;
7342 case X86ISD::BSF: return "X86ISD::BSF";
7343 case X86ISD::BSR: return "X86ISD::BSR";
7344 case X86ISD::SHLD: return "X86ISD::SHLD";
7345 case X86ISD::SHRD: return "X86ISD::SHRD";
7346 case X86ISD::FAND: return "X86ISD::FAND";
7347 case X86ISD::FOR: return "X86ISD::FOR";
7348 case X86ISD::FXOR: return "X86ISD::FXOR";
7349 case X86ISD::FSRL: return "X86ISD::FSRL";
7350 case X86ISD::FILD: return "X86ISD::FILD";
7351 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7352 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7353 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7354 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7355 case X86ISD::FLD: return "X86ISD::FLD";
7356 case X86ISD::FST: return "X86ISD::FST";
7357 case X86ISD::CALL: return "X86ISD::CALL";
7358 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7359 case X86ISD::BT: return "X86ISD::BT";
7360 case X86ISD::CMP: return "X86ISD::CMP";
7361 case X86ISD::COMI: return "X86ISD::COMI";
7362 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7363 case X86ISD::SETCC: return "X86ISD::SETCC";
7364 case X86ISD::CMOV: return "X86ISD::CMOV";
7365 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7366 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7367 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7368 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7369 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7370 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7371 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7372 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7373 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7374 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7375 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7376 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7377 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7378 case X86ISD::FMAX: return "X86ISD::FMAX";
7379 case X86ISD::FMIN: return "X86ISD::FMIN";
7380 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7381 case X86ISD::FRCP: return "X86ISD::FRCP";
7382 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7383 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7384 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7385 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7386 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7387 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7388 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7389 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7390 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7391 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7392 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7393 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7394 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7395 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7396 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7397 case X86ISD::VSHL: return "X86ISD::VSHL";
7398 case X86ISD::VSRL: return "X86ISD::VSRL";
7399 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7400 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7401 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7402 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7403 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7404 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7405 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7406 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7407 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7408 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7409 case X86ISD::ADD: return "X86ISD::ADD";
7410 case X86ISD::SUB: return "X86ISD::SUB";
7411 case X86ISD::SMUL: return "X86ISD::SMUL";
7412 case X86ISD::UMUL: return "X86ISD::UMUL";
7413 case X86ISD::INC: return "X86ISD::INC";
7414 case X86ISD::DEC: return "X86ISD::DEC";
7415 case X86ISD::OR: return "X86ISD::OR";
7416 case X86ISD::XOR: return "X86ISD::XOR";
7417 case X86ISD::AND: return "X86ISD::AND";
7418 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7419 case X86ISD::PTEST: return "X86ISD::PTEST";
7420 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7424 // isLegalAddressingMode - Return true if the addressing mode represented
7425 // by AM is legal for this target, for a load/store of the specified type.
7426 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7427 const Type *Ty) const {
7428 // X86 supports extremely general addressing modes.
7429 CodeModel::Model M = getTargetMachine().getCodeModel();
7431 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7432 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7437 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7439 // If a reference to this global requires an extra load, we can't fold it.
7440 if (isGlobalStubReference(GVFlags))
7443 // If BaseGV requires a register for the PIC base, we cannot also have a
7444 // BaseReg specified.
7445 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7448 // If lower 4G is not available, then we must use rip-relative addressing.
7449 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7459 // These scales always work.
7464 // These scales are formed with basereg+scalereg. Only accept if there is
7469 default: // Other stuff never works.
7477 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7478 if (!Ty1->isInteger() || !Ty2->isInteger())
7480 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7481 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7482 if (NumBits1 <= NumBits2)
7484 return Subtarget->is64Bit() || NumBits1 < 64;
7487 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7488 if (!VT1.isInteger() || !VT2.isInteger())
7490 unsigned NumBits1 = VT1.getSizeInBits();
7491 unsigned NumBits2 = VT2.getSizeInBits();
7492 if (NumBits1 <= NumBits2)
7494 return Subtarget->is64Bit() || NumBits1 < 64;
7497 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7498 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7499 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7500 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7503 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7504 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7505 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7508 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7509 // i16 instructions are longer (0x66 prefix) and potentially slower.
7510 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7513 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7514 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7515 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7516 /// are assumed to be legal.
7518 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7520 // Only do shuffles on 128-bit vector types for now.
7521 if (VT.getSizeInBits() == 64)
7524 // FIXME: pshufb, blends, shifts.
7525 return (VT.getVectorNumElements() == 2 ||
7526 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7527 isMOVLMask(M, VT) ||
7528 isSHUFPMask(M, VT) ||
7529 isPSHUFDMask(M, VT) ||
7530 isPSHUFHWMask(M, VT) ||
7531 isPSHUFLWMask(M, VT) ||
7532 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7533 isUNPCKLMask(M, VT) ||
7534 isUNPCKHMask(M, VT) ||
7535 isUNPCKL_v_undef_Mask(M, VT) ||
7536 isUNPCKH_v_undef_Mask(M, VT));
7540 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7542 unsigned NumElts = VT.getVectorNumElements();
7543 // FIXME: This collection of masks seems suspect.
7546 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7547 return (isMOVLMask(Mask, VT) ||
7548 isCommutedMOVLMask(Mask, VT, true) ||
7549 isSHUFPMask(Mask, VT) ||
7550 isCommutedSHUFPMask(Mask, VT));
7555 //===----------------------------------------------------------------------===//
7556 // X86 Scheduler Hooks
7557 //===----------------------------------------------------------------------===//
7559 // private utility function
7561 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7562 MachineBasicBlock *MBB,
7570 TargetRegisterClass *RC,
7571 bool invSrc) const {
7572 // For the atomic bitwise operator, we generate
7575 // ld t1 = [bitinstr.addr]
7576 // op t2 = t1, [bitinstr.val]
7578 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7580 // fallthrough -->nextMBB
7581 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7582 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7583 MachineFunction::iterator MBBIter = MBB;
7586 /// First build the CFG
7587 MachineFunction *F = MBB->getParent();
7588 MachineBasicBlock *thisMBB = MBB;
7589 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7590 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7591 F->insert(MBBIter, newMBB);
7592 F->insert(MBBIter, nextMBB);
7594 // Move all successors to thisMBB to nextMBB
7595 nextMBB->transferSuccessors(thisMBB);
7597 // Update thisMBB to fall through to newMBB
7598 thisMBB->addSuccessor(newMBB);
7600 // newMBB jumps to itself and fall through to nextMBB
7601 newMBB->addSuccessor(nextMBB);
7602 newMBB->addSuccessor(newMBB);
7604 // Insert instructions into newMBB based on incoming instruction
7605 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7606 "unexpected number of operands");
7607 DebugLoc dl = bInstr->getDebugLoc();
7608 MachineOperand& destOper = bInstr->getOperand(0);
7609 MachineOperand* argOpers[2 + X86AddrNumOperands];
7610 int numArgs = bInstr->getNumOperands() - 1;
7611 for (int i=0; i < numArgs; ++i)
7612 argOpers[i] = &bInstr->getOperand(i+1);
7614 // x86 address has 4 operands: base, index, scale, and displacement
7615 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7616 int valArgIndx = lastAddrIndx + 1;
7618 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7619 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7620 for (int i=0; i <= lastAddrIndx; ++i)
7621 (*MIB).addOperand(*argOpers[i]);
7623 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7625 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7630 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7631 assert((argOpers[valArgIndx]->isReg() ||
7632 argOpers[valArgIndx]->isImm()) &&
7634 if (argOpers[valArgIndx]->isReg())
7635 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7637 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7639 (*MIB).addOperand(*argOpers[valArgIndx]);
7641 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7644 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7645 for (int i=0; i <= lastAddrIndx; ++i)
7646 (*MIB).addOperand(*argOpers[i]);
7648 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7649 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7650 bInstr->memoperands_end());
7652 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7656 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7658 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7662 // private utility function: 64 bit atomics on 32 bit host.
7664 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7665 MachineBasicBlock *MBB,
7670 bool invSrc) const {
7671 // For the atomic bitwise operator, we generate
7672 // thisMBB (instructions are in pairs, except cmpxchg8b)
7673 // ld t1,t2 = [bitinstr.addr]
7675 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7676 // op t5, t6 <- out1, out2, [bitinstr.val]
7677 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7678 // mov ECX, EBX <- t5, t6
7679 // mov EAX, EDX <- t1, t2
7680 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7681 // mov t3, t4 <- EAX, EDX
7683 // result in out1, out2
7684 // fallthrough -->nextMBB
7686 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7687 const unsigned LoadOpc = X86::MOV32rm;
7688 const unsigned copyOpc = X86::MOV32rr;
7689 const unsigned NotOpc = X86::NOT32r;
7690 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7691 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7692 MachineFunction::iterator MBBIter = MBB;
7695 /// First build the CFG
7696 MachineFunction *F = MBB->getParent();
7697 MachineBasicBlock *thisMBB = MBB;
7698 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7699 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7700 F->insert(MBBIter, newMBB);
7701 F->insert(MBBIter, nextMBB);
7703 // Move all successors to thisMBB to nextMBB
7704 nextMBB->transferSuccessors(thisMBB);
7706 // Update thisMBB to fall through to newMBB
7707 thisMBB->addSuccessor(newMBB);
7709 // newMBB jumps to itself and fall through to nextMBB
7710 newMBB->addSuccessor(nextMBB);
7711 newMBB->addSuccessor(newMBB);
7713 DebugLoc dl = bInstr->getDebugLoc();
7714 // Insert instructions into newMBB based on incoming instruction
7715 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7716 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7717 "unexpected number of operands");
7718 MachineOperand& dest1Oper = bInstr->getOperand(0);
7719 MachineOperand& dest2Oper = bInstr->getOperand(1);
7720 MachineOperand* argOpers[2 + X86AddrNumOperands];
7721 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7722 argOpers[i] = &bInstr->getOperand(i+2);
7724 // x86 address has 4 operands: base, index, scale, and displacement
7725 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7727 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7728 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7729 for (int i=0; i <= lastAddrIndx; ++i)
7730 (*MIB).addOperand(*argOpers[i]);
7731 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7732 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7733 // add 4 to displacement.
7734 for (int i=0; i <= lastAddrIndx-2; ++i)
7735 (*MIB).addOperand(*argOpers[i]);
7736 MachineOperand newOp3 = *(argOpers[3]);
7738 newOp3.setImm(newOp3.getImm()+4);
7740 newOp3.setOffset(newOp3.getOffset()+4);
7741 (*MIB).addOperand(newOp3);
7742 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7744 // t3/4 are defined later, at the bottom of the loop
7745 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7746 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7747 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7748 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7749 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7750 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7752 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7753 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7755 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7756 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7762 int valArgIndx = lastAddrIndx + 1;
7763 assert((argOpers[valArgIndx]->isReg() ||
7764 argOpers[valArgIndx]->isImm()) &&
7766 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7767 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7768 if (argOpers[valArgIndx]->isReg())
7769 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7771 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7772 if (regOpcL != X86::MOV32rr)
7774 (*MIB).addOperand(*argOpers[valArgIndx]);
7775 assert(argOpers[valArgIndx + 1]->isReg() ==
7776 argOpers[valArgIndx]->isReg());
7777 assert(argOpers[valArgIndx + 1]->isImm() ==
7778 argOpers[valArgIndx]->isImm());
7779 if (argOpers[valArgIndx + 1]->isReg())
7780 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7782 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7783 if (regOpcH != X86::MOV32rr)
7785 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7787 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7789 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7792 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7794 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7797 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7798 for (int i=0; i <= lastAddrIndx; ++i)
7799 (*MIB).addOperand(*argOpers[i]);
7801 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7802 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7803 bInstr->memoperands_end());
7805 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7806 MIB.addReg(X86::EAX);
7807 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7808 MIB.addReg(X86::EDX);
7811 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7813 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7817 // private utility function
7819 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7820 MachineBasicBlock *MBB,
7821 unsigned cmovOpc) const {
7822 // For the atomic min/max operator, we generate
7825 // ld t1 = [min/max.addr]
7826 // mov t2 = [min/max.val]
7828 // cmov[cond] t2 = t1
7830 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7832 // fallthrough -->nextMBB
7834 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7835 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7836 MachineFunction::iterator MBBIter = MBB;
7839 /// First build the CFG
7840 MachineFunction *F = MBB->getParent();
7841 MachineBasicBlock *thisMBB = MBB;
7842 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7843 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7844 F->insert(MBBIter, newMBB);
7845 F->insert(MBBIter, nextMBB);
7847 // Move all successors of thisMBB to nextMBB
7848 nextMBB->transferSuccessors(thisMBB);
7850 // Update thisMBB to fall through to newMBB
7851 thisMBB->addSuccessor(newMBB);
7853 // newMBB jumps to newMBB and fall through to nextMBB
7854 newMBB->addSuccessor(nextMBB);
7855 newMBB->addSuccessor(newMBB);
7857 DebugLoc dl = mInstr->getDebugLoc();
7858 // Insert instructions into newMBB based on incoming instruction
7859 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7860 "unexpected number of operands");
7861 MachineOperand& destOper = mInstr->getOperand(0);
7862 MachineOperand* argOpers[2 + X86AddrNumOperands];
7863 int numArgs = mInstr->getNumOperands() - 1;
7864 for (int i=0; i < numArgs; ++i)
7865 argOpers[i] = &mInstr->getOperand(i+1);
7867 // x86 address has 4 operands: base, index, scale, and displacement
7868 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7869 int valArgIndx = lastAddrIndx + 1;
7871 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7872 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7873 for (int i=0; i <= lastAddrIndx; ++i)
7874 (*MIB).addOperand(*argOpers[i]);
7876 // We only support register and immediate values
7877 assert((argOpers[valArgIndx]->isReg() ||
7878 argOpers[valArgIndx]->isImm()) &&
7881 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7882 if (argOpers[valArgIndx]->isReg())
7883 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7885 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7886 (*MIB).addOperand(*argOpers[valArgIndx]);
7888 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7891 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7896 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7897 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7901 // Cmp and exchange if none has modified the memory location
7902 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7903 for (int i=0; i <= lastAddrIndx; ++i)
7904 (*MIB).addOperand(*argOpers[i]);
7906 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7907 (*MIB).setMemRefs(mInstr->memoperands_begin(),
7908 mInstr->memoperands_end());
7910 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7911 MIB.addReg(X86::EAX);
7914 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7916 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7920 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7921 // all of this code can be replaced with that in the .td file.
7923 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7924 unsigned numArgs, bool memArg) const {
7926 MachineFunction *F = BB->getParent();
7927 DebugLoc dl = MI->getDebugLoc();
7928 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7932 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
7934 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
7936 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7938 for (unsigned i = 0; i < numArgs; ++i) {
7939 MachineOperand &Op = MI->getOperand(i+1);
7941 if (!(Op.isReg() && Op.isImplicit()))
7945 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7948 F->DeleteMachineInstr(MI);
7954 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7956 MachineBasicBlock *MBB) const {
7957 // Emit code to save XMM registers to the stack. The ABI says that the
7958 // number of registers to save is given in %al, so it's theoretically
7959 // possible to do an indirect jump trick to avoid saving all of them,
7960 // however this code takes a simpler approach and just executes all
7961 // of the stores if %al is non-zero. It's less code, and it's probably
7962 // easier on the hardware branch predictor, and stores aren't all that
7963 // expensive anyway.
7965 // Create the new basic blocks. One block contains all the XMM stores,
7966 // and one block is the final destination regardless of whether any
7967 // stores were performed.
7968 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7969 MachineFunction *F = MBB->getParent();
7970 MachineFunction::iterator MBBIter = MBB;
7972 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
7973 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
7974 F->insert(MBBIter, XMMSaveMBB);
7975 F->insert(MBBIter, EndMBB);
7978 // Move any original successors of MBB to the end block.
7979 EndMBB->transferSuccessors(MBB);
7980 // The original block will now fall through to the XMM save block.
7981 MBB->addSuccessor(XMMSaveMBB);
7982 // The XMMSaveMBB will fall through to the end block.
7983 XMMSaveMBB->addSuccessor(EndMBB);
7985 // Now add the instructions.
7986 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7987 DebugLoc DL = MI->getDebugLoc();
7989 unsigned CountReg = MI->getOperand(0).getReg();
7990 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
7991 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
7993 if (!Subtarget->isTargetWin64()) {
7994 // If %al is 0, branch around the XMM save block.
7995 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
7996 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
7997 MBB->addSuccessor(EndMBB);
8000 // In the XMM save block, save all the XMM argument registers.
8001 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8002 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8003 MachineMemOperand *MMO =
8004 F->getMachineMemOperand(
8005 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8006 MachineMemOperand::MOStore, Offset,
8007 /*Size=*/16, /*Align=*/16);
8008 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8009 .addFrameIndex(RegSaveFrameIndex)
8010 .addImm(/*Scale=*/1)
8011 .addReg(/*IndexReg=*/0)
8012 .addImm(/*Disp=*/Offset)
8013 .addReg(/*Segment=*/0)
8014 .addReg(MI->getOperand(i).getReg())
8015 .addMemOperand(MMO);
8018 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8024 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8025 MachineBasicBlock *BB,
8026 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8027 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8028 DebugLoc DL = MI->getDebugLoc();
8030 // To "insert" a SELECT_CC instruction, we actually have to insert the
8031 // diamond control-flow pattern. The incoming instruction knows the
8032 // destination vreg to set, the condition code register to branch on, the
8033 // true/false values to select between, and a branch opcode to use.
8034 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8035 MachineFunction::iterator It = BB;
8041 // cmpTY ccX, r1, r2
8043 // fallthrough --> copy0MBB
8044 MachineBasicBlock *thisMBB = BB;
8045 MachineFunction *F = BB->getParent();
8046 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8047 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8049 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8050 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8051 F->insert(It, copy0MBB);
8052 F->insert(It, sinkMBB);
8053 // Update machine-CFG edges by first adding all successors of the current
8054 // block to the new block which will contain the Phi node for the select.
8055 // Also inform sdisel of the edge changes.
8056 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8057 E = BB->succ_end(); I != E; ++I) {
8058 EM->insert(std::make_pair(*I, sinkMBB));
8059 sinkMBB->addSuccessor(*I);
8061 // Next, remove all successors of the current block, and add the true
8062 // and fallthrough blocks as its successors.
8063 while (!BB->succ_empty())
8064 BB->removeSuccessor(BB->succ_begin());
8065 // Add the true and fallthrough blocks as its successors.
8066 BB->addSuccessor(copy0MBB);
8067 BB->addSuccessor(sinkMBB);
8070 // %FalseValue = ...
8071 // # fallthrough to sinkMBB
8074 // Update machine-CFG edges
8075 BB->addSuccessor(sinkMBB);
8078 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8081 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8082 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8083 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8085 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8091 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8092 MachineBasicBlock *BB,
8093 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8094 switch (MI->getOpcode()) {
8095 default: assert(false && "Unexpected instr type to insert");
8097 case X86::CMOV_V1I64:
8098 case X86::CMOV_FR32:
8099 case X86::CMOV_FR64:
8100 case X86::CMOV_V4F32:
8101 case X86::CMOV_V2F64:
8102 case X86::CMOV_V2I64:
8103 return EmitLoweredSelect(MI, BB, EM);
8105 case X86::FP32_TO_INT16_IN_MEM:
8106 case X86::FP32_TO_INT32_IN_MEM:
8107 case X86::FP32_TO_INT64_IN_MEM:
8108 case X86::FP64_TO_INT16_IN_MEM:
8109 case X86::FP64_TO_INT32_IN_MEM:
8110 case X86::FP64_TO_INT64_IN_MEM:
8111 case X86::FP80_TO_INT16_IN_MEM:
8112 case X86::FP80_TO_INT32_IN_MEM:
8113 case X86::FP80_TO_INT64_IN_MEM: {
8114 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8115 DebugLoc DL = MI->getDebugLoc();
8117 // Change the floating point control register to use "round towards zero"
8118 // mode when truncating to an integer value.
8119 MachineFunction *F = BB->getParent();
8120 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8121 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8123 // Load the old value of the high byte of the control word...
8125 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8126 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8129 // Set the high part to be round to zero...
8130 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8133 // Reload the modified control word now...
8134 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8136 // Restore the memory image of control word to original value
8137 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8140 // Get the X86 opcode to use.
8142 switch (MI->getOpcode()) {
8143 default: llvm_unreachable("illegal opcode!");
8144 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8145 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8146 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8147 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8148 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8149 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8150 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8151 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8152 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8156 MachineOperand &Op = MI->getOperand(0);
8158 AM.BaseType = X86AddressMode::RegBase;
8159 AM.Base.Reg = Op.getReg();
8161 AM.BaseType = X86AddressMode::FrameIndexBase;
8162 AM.Base.FrameIndex = Op.getIndex();
8164 Op = MI->getOperand(1);
8166 AM.Scale = Op.getImm();
8167 Op = MI->getOperand(2);
8169 AM.IndexReg = Op.getImm();
8170 Op = MI->getOperand(3);
8171 if (Op.isGlobal()) {
8172 AM.GV = Op.getGlobal();
8174 AM.Disp = Op.getImm();
8176 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8177 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8179 // Reload the original control word now.
8180 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8182 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8185 // String/text processing lowering.
8186 case X86::PCMPISTRM128REG:
8187 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8188 case X86::PCMPISTRM128MEM:
8189 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8190 case X86::PCMPESTRM128REG:
8191 return EmitPCMP(MI, BB, 5, false /* in mem */);
8192 case X86::PCMPESTRM128MEM:
8193 return EmitPCMP(MI, BB, 5, true /* in mem */);
8196 case X86::ATOMAND32:
8197 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8198 X86::AND32ri, X86::MOV32rm,
8199 X86::LCMPXCHG32, X86::MOV32rr,
8200 X86::NOT32r, X86::EAX,
8201 X86::GR32RegisterClass);
8203 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8204 X86::OR32ri, X86::MOV32rm,
8205 X86::LCMPXCHG32, X86::MOV32rr,
8206 X86::NOT32r, X86::EAX,
8207 X86::GR32RegisterClass);
8208 case X86::ATOMXOR32:
8209 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8210 X86::XOR32ri, X86::MOV32rm,
8211 X86::LCMPXCHG32, X86::MOV32rr,
8212 X86::NOT32r, X86::EAX,
8213 X86::GR32RegisterClass);
8214 case X86::ATOMNAND32:
8215 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8216 X86::AND32ri, X86::MOV32rm,
8217 X86::LCMPXCHG32, X86::MOV32rr,
8218 X86::NOT32r, X86::EAX,
8219 X86::GR32RegisterClass, true);
8220 case X86::ATOMMIN32:
8221 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8222 case X86::ATOMMAX32:
8223 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8224 case X86::ATOMUMIN32:
8225 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8226 case X86::ATOMUMAX32:
8227 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8229 case X86::ATOMAND16:
8230 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8231 X86::AND16ri, X86::MOV16rm,
8232 X86::LCMPXCHG16, X86::MOV16rr,
8233 X86::NOT16r, X86::AX,
8234 X86::GR16RegisterClass);
8236 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8237 X86::OR16ri, X86::MOV16rm,
8238 X86::LCMPXCHG16, X86::MOV16rr,
8239 X86::NOT16r, X86::AX,
8240 X86::GR16RegisterClass);
8241 case X86::ATOMXOR16:
8242 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8243 X86::XOR16ri, X86::MOV16rm,
8244 X86::LCMPXCHG16, X86::MOV16rr,
8245 X86::NOT16r, X86::AX,
8246 X86::GR16RegisterClass);
8247 case X86::ATOMNAND16:
8248 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8249 X86::AND16ri, X86::MOV16rm,
8250 X86::LCMPXCHG16, X86::MOV16rr,
8251 X86::NOT16r, X86::AX,
8252 X86::GR16RegisterClass, true);
8253 case X86::ATOMMIN16:
8254 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8255 case X86::ATOMMAX16:
8256 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8257 case X86::ATOMUMIN16:
8258 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8259 case X86::ATOMUMAX16:
8260 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8263 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8264 X86::AND8ri, X86::MOV8rm,
8265 X86::LCMPXCHG8, X86::MOV8rr,
8266 X86::NOT8r, X86::AL,
8267 X86::GR8RegisterClass);
8269 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8270 X86::OR8ri, X86::MOV8rm,
8271 X86::LCMPXCHG8, X86::MOV8rr,
8272 X86::NOT8r, X86::AL,
8273 X86::GR8RegisterClass);
8275 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8276 X86::XOR8ri, X86::MOV8rm,
8277 X86::LCMPXCHG8, X86::MOV8rr,
8278 X86::NOT8r, X86::AL,
8279 X86::GR8RegisterClass);
8280 case X86::ATOMNAND8:
8281 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8282 X86::AND8ri, X86::MOV8rm,
8283 X86::LCMPXCHG8, X86::MOV8rr,
8284 X86::NOT8r, X86::AL,
8285 X86::GR8RegisterClass, true);
8286 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8287 // This group is for 64-bit host.
8288 case X86::ATOMAND64:
8289 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8290 X86::AND64ri32, X86::MOV64rm,
8291 X86::LCMPXCHG64, X86::MOV64rr,
8292 X86::NOT64r, X86::RAX,
8293 X86::GR64RegisterClass);
8295 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8296 X86::OR64ri32, X86::MOV64rm,
8297 X86::LCMPXCHG64, X86::MOV64rr,
8298 X86::NOT64r, X86::RAX,
8299 X86::GR64RegisterClass);
8300 case X86::ATOMXOR64:
8301 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8302 X86::XOR64ri32, X86::MOV64rm,
8303 X86::LCMPXCHG64, X86::MOV64rr,
8304 X86::NOT64r, X86::RAX,
8305 X86::GR64RegisterClass);
8306 case X86::ATOMNAND64:
8307 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8308 X86::AND64ri32, X86::MOV64rm,
8309 X86::LCMPXCHG64, X86::MOV64rr,
8310 X86::NOT64r, X86::RAX,
8311 X86::GR64RegisterClass, true);
8312 case X86::ATOMMIN64:
8313 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8314 case X86::ATOMMAX64:
8315 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8316 case X86::ATOMUMIN64:
8317 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8318 case X86::ATOMUMAX64:
8319 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8321 // This group does 64-bit operations on a 32-bit host.
8322 case X86::ATOMAND6432:
8323 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8324 X86::AND32rr, X86::AND32rr,
8325 X86::AND32ri, X86::AND32ri,
8327 case X86::ATOMOR6432:
8328 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8329 X86::OR32rr, X86::OR32rr,
8330 X86::OR32ri, X86::OR32ri,
8332 case X86::ATOMXOR6432:
8333 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8334 X86::XOR32rr, X86::XOR32rr,
8335 X86::XOR32ri, X86::XOR32ri,
8337 case X86::ATOMNAND6432:
8338 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8339 X86::AND32rr, X86::AND32rr,
8340 X86::AND32ri, X86::AND32ri,
8342 case X86::ATOMADD6432:
8343 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8344 X86::ADD32rr, X86::ADC32rr,
8345 X86::ADD32ri, X86::ADC32ri,
8347 case X86::ATOMSUB6432:
8348 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8349 X86::SUB32rr, X86::SBB32rr,
8350 X86::SUB32ri, X86::SBB32ri,
8352 case X86::ATOMSWAP6432:
8353 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8354 X86::MOV32rr, X86::MOV32rr,
8355 X86::MOV32ri, X86::MOV32ri,
8357 case X86::VASTART_SAVE_XMM_REGS:
8358 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8362 //===----------------------------------------------------------------------===//
8363 // X86 Optimization Hooks
8364 //===----------------------------------------------------------------------===//
8366 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8370 const SelectionDAG &DAG,
8371 unsigned Depth) const {
8372 unsigned Opc = Op.getOpcode();
8373 assert((Opc >= ISD::BUILTIN_OP_END ||
8374 Opc == ISD::INTRINSIC_WO_CHAIN ||
8375 Opc == ISD::INTRINSIC_W_CHAIN ||
8376 Opc == ISD::INTRINSIC_VOID) &&
8377 "Should use MaskedValueIsZero if you don't know whether Op"
8378 " is a target node!");
8380 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8392 // These nodes' second result is a boolean.
8393 if (Op.getResNo() == 0)
8397 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8398 Mask.getBitWidth() - 1);
8403 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8404 /// node is a GlobalAddress + offset.
8405 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8406 GlobalValue* &GA, int64_t &Offset) const{
8407 if (N->getOpcode() == X86ISD::Wrapper) {
8408 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8409 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8410 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8414 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8417 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8418 EVT EltVT, LoadSDNode *&LDBase,
8419 unsigned &LastLoadedElt,
8420 SelectionDAG &DAG, MachineFrameInfo *MFI,
8421 const TargetLowering &TLI) {
8423 LastLoadedElt = -1U;
8424 for (unsigned i = 0; i < NumElems; ++i) {
8425 if (N->getMaskElt(i) < 0) {
8431 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8432 if (!Elt.getNode() ||
8433 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8436 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8438 LDBase = cast<LoadSDNode>(Elt.getNode());
8442 if (Elt.getOpcode() == ISD::UNDEF)
8445 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8446 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8453 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8454 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8455 /// if the load addresses are consecutive, non-overlapping, and in the right
8456 /// order. In the case of v2i64, it will see if it can rewrite the
8457 /// shuffle to be an appropriate build vector so it can take advantage of
8458 // performBuildVectorCombine.
8459 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8460 const TargetLowering &TLI) {
8461 DebugLoc dl = N->getDebugLoc();
8462 EVT VT = N->getValueType(0);
8463 EVT EltVT = VT.getVectorElementType();
8464 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8465 unsigned NumElems = VT.getVectorNumElements();
8467 if (VT.getSizeInBits() != 128)
8470 // Try to combine a vector_shuffle into a 128-bit load.
8471 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8472 LoadSDNode *LD = NULL;
8473 unsigned LastLoadedElt;
8474 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8478 if (LastLoadedElt == NumElems - 1) {
8479 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8480 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8481 LD->getSrcValue(), LD->getSrcValueOffset(),
8483 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8484 LD->getSrcValue(), LD->getSrcValueOffset(),
8485 LD->isVolatile(), LD->getAlignment());
8486 } else if (NumElems == 4 && LastLoadedElt == 1) {
8487 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8488 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8489 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8490 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8495 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8496 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8497 const X86Subtarget *Subtarget) {
8498 DebugLoc DL = N->getDebugLoc();
8499 SDValue Cond = N->getOperand(0);
8500 // Get the LHS/RHS of the select.
8501 SDValue LHS = N->getOperand(1);
8502 SDValue RHS = N->getOperand(2);
8504 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8505 // instructions have the peculiarity that if either operand is a NaN,
8506 // they chose what we call the RHS operand (and as such are not symmetric).
8507 // It happens that this matches the semantics of the common C idiom
8508 // x<y?x:y and related forms, so we can recognize these cases.
8509 if (Subtarget->hasSSE2() &&
8510 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8511 Cond.getOpcode() == ISD::SETCC) {
8512 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8514 unsigned Opcode = 0;
8515 // Check for x CC y ? x : y.
8516 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8520 // This can be a min if we can prove that at least one of the operands
8522 if (!FiniteOnlyFPMath()) {
8523 if (DAG.isKnownNeverNaN(RHS)) {
8524 // Put the potential NaN in the RHS so that SSE will preserve it.
8525 std::swap(LHS, RHS);
8526 } else if (!DAG.isKnownNeverNaN(LHS))
8529 Opcode = X86ISD::FMIN;
8532 // This can be a min if we can prove that at least one of the operands
8534 if (!FiniteOnlyFPMath()) {
8535 if (DAG.isKnownNeverNaN(LHS)) {
8536 // Put the potential NaN in the RHS so that SSE will preserve it.
8537 std::swap(LHS, RHS);
8538 } else if (!DAG.isKnownNeverNaN(RHS))
8541 Opcode = X86ISD::FMIN;
8544 // This can be a min, but if either operand is a NaN we need it to
8545 // preserve the original LHS.
8546 std::swap(LHS, RHS);
8550 Opcode = X86ISD::FMIN;
8554 // This can be a max if we can prove that at least one of the operands
8556 if (!FiniteOnlyFPMath()) {
8557 if (DAG.isKnownNeverNaN(LHS)) {
8558 // Put the potential NaN in the RHS so that SSE will preserve it.
8559 std::swap(LHS, RHS);
8560 } else if (!DAG.isKnownNeverNaN(RHS))
8563 Opcode = X86ISD::FMAX;
8566 // This can be a max if we can prove that at least one of the operands
8568 if (!FiniteOnlyFPMath()) {
8569 if (DAG.isKnownNeverNaN(RHS)) {
8570 // Put the potential NaN in the RHS so that SSE will preserve it.
8571 std::swap(LHS, RHS);
8572 } else if (!DAG.isKnownNeverNaN(LHS))
8575 Opcode = X86ISD::FMAX;
8578 // This can be a max, but if either operand is a NaN we need it to
8579 // preserve the original LHS.
8580 std::swap(LHS, RHS);
8584 Opcode = X86ISD::FMAX;
8587 // Check for x CC y ? y : x -- a min/max with reversed arms.
8588 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8592 // This can be a min if we can prove that at least one of the operands
8594 if (!FiniteOnlyFPMath()) {
8595 if (DAG.isKnownNeverNaN(RHS)) {
8596 // Put the potential NaN in the RHS so that SSE will preserve it.
8597 std::swap(LHS, RHS);
8598 } else if (!DAG.isKnownNeverNaN(LHS))
8601 Opcode = X86ISD::FMIN;
8604 // This can be a min if we can prove that at least one of the operands
8606 if (!FiniteOnlyFPMath()) {
8607 if (DAG.isKnownNeverNaN(LHS)) {
8608 // Put the potential NaN in the RHS so that SSE will preserve it.
8609 std::swap(LHS, RHS);
8610 } else if (!DAG.isKnownNeverNaN(RHS))
8613 Opcode = X86ISD::FMIN;
8616 // This can be a min, but if either operand is a NaN we need it to
8617 // preserve the original LHS.
8618 std::swap(LHS, RHS);
8622 Opcode = X86ISD::FMIN;
8626 // This can be a max if we can prove that at least one of the operands
8628 if (!FiniteOnlyFPMath()) {
8629 if (DAG.isKnownNeverNaN(LHS)) {
8630 // Put the potential NaN in the RHS so that SSE will preserve it.
8631 std::swap(LHS, RHS);
8632 } else if (!DAG.isKnownNeverNaN(RHS))
8635 Opcode = X86ISD::FMAX;
8638 // This can be a max if we can prove that at least one of the operands
8640 if (!FiniteOnlyFPMath()) {
8641 if (DAG.isKnownNeverNaN(RHS)) {
8642 // Put the potential NaN in the RHS so that SSE will preserve it.
8643 std::swap(LHS, RHS);
8644 } else if (!DAG.isKnownNeverNaN(LHS))
8647 Opcode = X86ISD::FMAX;
8650 // This can be a max, but if either operand is a NaN we need it to
8651 // preserve the original LHS.
8652 std::swap(LHS, RHS);
8656 Opcode = X86ISD::FMAX;
8662 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8665 // If this is a select between two integer constants, try to do some
8667 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8668 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8669 // Don't do this for crazy integer types.
8670 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8671 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8672 // so that TrueC (the true value) is larger than FalseC.
8673 bool NeedsCondInvert = false;
8675 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8676 // Efficiently invertible.
8677 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8678 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8679 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8680 NeedsCondInvert = true;
8681 std::swap(TrueC, FalseC);
8684 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8685 if (FalseC->getAPIntValue() == 0 &&
8686 TrueC->getAPIntValue().isPowerOf2()) {
8687 if (NeedsCondInvert) // Invert the condition if needed.
8688 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8689 DAG.getConstant(1, Cond.getValueType()));
8691 // Zero extend the condition if needed.
8692 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8694 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8695 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8696 DAG.getConstant(ShAmt, MVT::i8));
8699 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8700 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8701 if (NeedsCondInvert) // Invert the condition if needed.
8702 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8703 DAG.getConstant(1, Cond.getValueType()));
8705 // Zero extend the condition if needed.
8706 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8707 FalseC->getValueType(0), Cond);
8708 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8709 SDValue(FalseC, 0));
8712 // Optimize cases that will turn into an LEA instruction. This requires
8713 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8714 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8715 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8716 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8718 bool isFastMultiplier = false;
8720 switch ((unsigned char)Diff) {
8722 case 1: // result = add base, cond
8723 case 2: // result = lea base( , cond*2)
8724 case 3: // result = lea base(cond, cond*2)
8725 case 4: // result = lea base( , cond*4)
8726 case 5: // result = lea base(cond, cond*4)
8727 case 8: // result = lea base( , cond*8)
8728 case 9: // result = lea base(cond, cond*8)
8729 isFastMultiplier = true;
8734 if (isFastMultiplier) {
8735 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8736 if (NeedsCondInvert) // Invert the condition if needed.
8737 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8738 DAG.getConstant(1, Cond.getValueType()));
8740 // Zero extend the condition if needed.
8741 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8743 // Scale the condition by the difference.
8745 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8746 DAG.getConstant(Diff, Cond.getValueType()));
8748 // Add the base if non-zero.
8749 if (FalseC->getAPIntValue() != 0)
8750 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8751 SDValue(FalseC, 0));
8761 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8762 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8763 TargetLowering::DAGCombinerInfo &DCI) {
8764 DebugLoc DL = N->getDebugLoc();
8766 // If the flag operand isn't dead, don't touch this CMOV.
8767 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8770 // If this is a select between two integer constants, try to do some
8771 // optimizations. Note that the operands are ordered the opposite of SELECT
8773 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8774 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8775 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8776 // larger than FalseC (the false value).
8777 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8779 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8780 CC = X86::GetOppositeBranchCondition(CC);
8781 std::swap(TrueC, FalseC);
8784 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8785 // This is efficient for any integer data type (including i8/i16) and
8787 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8788 SDValue Cond = N->getOperand(3);
8789 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8790 DAG.getConstant(CC, MVT::i8), Cond);
8792 // Zero extend the condition if needed.
8793 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8795 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8796 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8797 DAG.getConstant(ShAmt, MVT::i8));
8798 if (N->getNumValues() == 2) // Dead flag value?
8799 return DCI.CombineTo(N, Cond, SDValue());
8803 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8804 // for any integer data type, including i8/i16.
8805 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8806 SDValue Cond = N->getOperand(3);
8807 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8808 DAG.getConstant(CC, MVT::i8), Cond);
8810 // Zero extend the condition if needed.
8811 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8812 FalseC->getValueType(0), Cond);
8813 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8814 SDValue(FalseC, 0));
8816 if (N->getNumValues() == 2) // Dead flag value?
8817 return DCI.CombineTo(N, Cond, SDValue());
8821 // Optimize cases that will turn into an LEA instruction. This requires
8822 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8823 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8824 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8825 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8827 bool isFastMultiplier = false;
8829 switch ((unsigned char)Diff) {
8831 case 1: // result = add base, cond
8832 case 2: // result = lea base( , cond*2)
8833 case 3: // result = lea base(cond, cond*2)
8834 case 4: // result = lea base( , cond*4)
8835 case 5: // result = lea base(cond, cond*4)
8836 case 8: // result = lea base( , cond*8)
8837 case 9: // result = lea base(cond, cond*8)
8838 isFastMultiplier = true;
8843 if (isFastMultiplier) {
8844 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8845 SDValue Cond = N->getOperand(3);
8846 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8847 DAG.getConstant(CC, MVT::i8), Cond);
8848 // Zero extend the condition if needed.
8849 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8851 // Scale the condition by the difference.
8853 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8854 DAG.getConstant(Diff, Cond.getValueType()));
8856 // Add the base if non-zero.
8857 if (FalseC->getAPIntValue() != 0)
8858 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8859 SDValue(FalseC, 0));
8860 if (N->getNumValues() == 2) // Dead flag value?
8861 return DCI.CombineTo(N, Cond, SDValue());
8871 /// PerformMulCombine - Optimize a single multiply with constant into two
8872 /// in order to implement it with two cheaper instructions, e.g.
8873 /// LEA + SHL, LEA + LEA.
8874 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8875 TargetLowering::DAGCombinerInfo &DCI) {
8876 if (DAG.getMachineFunction().
8877 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8880 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8883 EVT VT = N->getValueType(0);
8887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8890 uint64_t MulAmt = C->getZExtValue();
8891 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8894 uint64_t MulAmt1 = 0;
8895 uint64_t MulAmt2 = 0;
8896 if ((MulAmt % 9) == 0) {
8898 MulAmt2 = MulAmt / 9;
8899 } else if ((MulAmt % 5) == 0) {
8901 MulAmt2 = MulAmt / 5;
8902 } else if ((MulAmt % 3) == 0) {
8904 MulAmt2 = MulAmt / 3;
8907 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8908 DebugLoc DL = N->getDebugLoc();
8910 if (isPowerOf2_64(MulAmt2) &&
8911 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8912 // If second multiplifer is pow2, issue it first. We want the multiply by
8913 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8915 std::swap(MulAmt1, MulAmt2);
8918 if (isPowerOf2_64(MulAmt1))
8919 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8920 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8922 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8923 DAG.getConstant(MulAmt1, VT));
8925 if (isPowerOf2_64(MulAmt2))
8926 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8927 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8929 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8930 DAG.getConstant(MulAmt2, VT));
8932 // Do not add new nodes to DAG combiner worklist.
8933 DCI.CombineTo(N, NewMul, false);
8939 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8941 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8942 const X86Subtarget *Subtarget) {
8943 // On X86 with SSE2 support, we can transform this to a vector shift if
8944 // all elements are shifted by the same amount. We can't do this in legalize
8945 // because the a constant vector is typically transformed to a constant pool
8946 // so we have no knowledge of the shift amount.
8947 if (!Subtarget->hasSSE2())
8950 EVT VT = N->getValueType(0);
8951 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8954 SDValue ShAmtOp = N->getOperand(1);
8955 EVT EltVT = VT.getVectorElementType();
8956 DebugLoc DL = N->getDebugLoc();
8957 SDValue BaseShAmt = SDValue();
8958 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8959 unsigned NumElts = VT.getVectorNumElements();
8961 for (; i != NumElts; ++i) {
8962 SDValue Arg = ShAmtOp.getOperand(i);
8963 if (Arg.getOpcode() == ISD::UNDEF) continue;
8967 for (; i != NumElts; ++i) {
8968 SDValue Arg = ShAmtOp.getOperand(i);
8969 if (Arg.getOpcode() == ISD::UNDEF) continue;
8970 if (Arg != BaseShAmt) {
8974 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8975 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8976 SDValue InVec = ShAmtOp.getOperand(0);
8977 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8978 unsigned NumElts = InVec.getValueType().getVectorNumElements();
8980 for (; i != NumElts; ++i) {
8981 SDValue Arg = InVec.getOperand(i);
8982 if (Arg.getOpcode() == ISD::UNDEF) continue;
8986 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
8987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
8988 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
8989 if (C->getZExtValue() == SplatIdx)
8990 BaseShAmt = InVec.getOperand(1);
8993 if (BaseShAmt.getNode() == 0)
8994 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8995 DAG.getIntPtrConstant(0));
8999 // The shift amount is an i32.
9000 if (EltVT.bitsGT(MVT::i32))
9001 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9002 else if (EltVT.bitsLT(MVT::i32))
9003 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9005 // The shift amount is identical so we can do a vector shift.
9006 SDValue ValOp = N->getOperand(0);
9007 switch (N->getOpcode()) {
9009 llvm_unreachable("Unknown shift opcode!");
9012 if (VT == MVT::v2i64)
9013 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9014 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9016 if (VT == MVT::v4i32)
9017 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9018 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9020 if (VT == MVT::v8i16)
9021 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9022 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9026 if (VT == MVT::v4i32)
9027 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9028 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9030 if (VT == MVT::v8i16)
9031 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9032 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9036 if (VT == MVT::v2i64)
9037 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9038 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9040 if (VT == MVT::v4i32)
9041 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9042 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9044 if (VT == MVT::v8i16)
9045 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9046 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9053 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9054 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9055 const X86Subtarget *Subtarget) {
9056 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9057 // the FP state in cases where an emms may be missing.
9058 // A preferable solution to the general problem is to figure out the right
9059 // places to insert EMMS. This qualifies as a quick hack.
9061 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9062 StoreSDNode *St = cast<StoreSDNode>(N);
9063 EVT VT = St->getValue().getValueType();
9064 if (VT.getSizeInBits() != 64)
9067 const Function *F = DAG.getMachineFunction().getFunction();
9068 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9069 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9070 && Subtarget->hasSSE2();
9071 if ((VT.isVector() ||
9072 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9073 isa<LoadSDNode>(St->getValue()) &&
9074 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9075 St->getChain().hasOneUse() && !St->isVolatile()) {
9076 SDNode* LdVal = St->getValue().getNode();
9078 int TokenFactorIndex = -1;
9079 SmallVector<SDValue, 8> Ops;
9080 SDNode* ChainVal = St->getChain().getNode();
9081 // Must be a store of a load. We currently handle two cases: the load
9082 // is a direct child, and it's under an intervening TokenFactor. It is
9083 // possible to dig deeper under nested TokenFactors.
9084 if (ChainVal == LdVal)
9085 Ld = cast<LoadSDNode>(St->getChain());
9086 else if (St->getValue().hasOneUse() &&
9087 ChainVal->getOpcode() == ISD::TokenFactor) {
9088 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9089 if (ChainVal->getOperand(i).getNode() == LdVal) {
9090 TokenFactorIndex = i;
9091 Ld = cast<LoadSDNode>(St->getValue());
9093 Ops.push_back(ChainVal->getOperand(i));
9097 if (!Ld || !ISD::isNormalLoad(Ld))
9100 // If this is not the MMX case, i.e. we are just turning i64 load/store
9101 // into f64 load/store, avoid the transformation if there are multiple
9102 // uses of the loaded value.
9103 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9106 DebugLoc LdDL = Ld->getDebugLoc();
9107 DebugLoc StDL = N->getDebugLoc();
9108 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9109 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9111 if (Subtarget->is64Bit() || F64IsLegal) {
9112 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9113 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9114 Ld->getBasePtr(), Ld->getSrcValue(),
9115 Ld->getSrcValueOffset(), Ld->isVolatile(),
9116 Ld->getAlignment());
9117 SDValue NewChain = NewLd.getValue(1);
9118 if (TokenFactorIndex != -1) {
9119 Ops.push_back(NewChain);
9120 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9123 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9124 St->getSrcValue(), St->getSrcValueOffset(),
9125 St->isVolatile(), St->getAlignment());
9128 // Otherwise, lower to two pairs of 32-bit loads / stores.
9129 SDValue LoAddr = Ld->getBasePtr();
9130 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9131 DAG.getConstant(4, MVT::i32));
9133 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9134 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9135 Ld->isVolatile(), Ld->getAlignment());
9136 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9137 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9139 MinAlign(Ld->getAlignment(), 4));
9141 SDValue NewChain = LoLd.getValue(1);
9142 if (TokenFactorIndex != -1) {
9143 Ops.push_back(LoLd);
9144 Ops.push_back(HiLd);
9145 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9149 LoAddr = St->getBasePtr();
9150 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9151 DAG.getConstant(4, MVT::i32));
9153 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9154 St->getSrcValue(), St->getSrcValueOffset(),
9155 St->isVolatile(), St->getAlignment());
9156 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9158 St->getSrcValueOffset() + 4,
9160 MinAlign(St->getAlignment(), 4));
9161 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9166 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9167 /// X86ISD::FXOR nodes.
9168 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9169 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9170 // F[X]OR(0.0, x) -> x
9171 // F[X]OR(x, 0.0) -> x
9172 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9173 if (C->getValueAPF().isPosZero())
9174 return N->getOperand(1);
9175 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9176 if (C->getValueAPF().isPosZero())
9177 return N->getOperand(0);
9181 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9182 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9183 // FAND(0.0, x) -> 0.0
9184 // FAND(x, 0.0) -> 0.0
9185 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9186 if (C->getValueAPF().isPosZero())
9187 return N->getOperand(0);
9188 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9189 if (C->getValueAPF().isPosZero())
9190 return N->getOperand(1);
9194 static SDValue PerformBTCombine(SDNode *N,
9196 TargetLowering::DAGCombinerInfo &DCI) {
9197 // BT ignores high bits in the bit index operand.
9198 SDValue Op1 = N->getOperand(1);
9199 if (Op1.hasOneUse()) {
9200 unsigned BitWidth = Op1.getValueSizeInBits();
9201 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9202 APInt KnownZero, KnownOne;
9203 TargetLowering::TargetLoweringOpt TLO(DAG);
9204 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9205 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9206 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9207 DCI.CommitTargetLoweringOpt(TLO);
9212 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9213 SDValue Op = N->getOperand(0);
9214 if (Op.getOpcode() == ISD::BIT_CONVERT)
9215 Op = Op.getOperand(0);
9216 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9217 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9218 VT.getVectorElementType().getSizeInBits() ==
9219 OpVT.getVectorElementType().getSizeInBits()) {
9220 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9225 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9226 // Locked instructions, in turn, have implicit fence semantics (all memory
9227 // operations are flushed before issuing the locked instruction, and the
9228 // are not buffered), so we can fold away the common pattern of
9229 // fence-atomic-fence.
9230 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9231 SDValue atomic = N->getOperand(0);
9232 switch (atomic.getOpcode()) {
9233 case ISD::ATOMIC_CMP_SWAP:
9234 case ISD::ATOMIC_SWAP:
9235 case ISD::ATOMIC_LOAD_ADD:
9236 case ISD::ATOMIC_LOAD_SUB:
9237 case ISD::ATOMIC_LOAD_AND:
9238 case ISD::ATOMIC_LOAD_OR:
9239 case ISD::ATOMIC_LOAD_XOR:
9240 case ISD::ATOMIC_LOAD_NAND:
9241 case ISD::ATOMIC_LOAD_MIN:
9242 case ISD::ATOMIC_LOAD_MAX:
9243 case ISD::ATOMIC_LOAD_UMIN:
9244 case ISD::ATOMIC_LOAD_UMAX:
9250 SDValue fence = atomic.getOperand(0);
9251 if (fence.getOpcode() != ISD::MEMBARRIER)
9254 switch (atomic.getOpcode()) {
9255 case ISD::ATOMIC_CMP_SWAP:
9256 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9257 atomic.getOperand(1), atomic.getOperand(2),
9258 atomic.getOperand(3));
9259 case ISD::ATOMIC_SWAP:
9260 case ISD::ATOMIC_LOAD_ADD:
9261 case ISD::ATOMIC_LOAD_SUB:
9262 case ISD::ATOMIC_LOAD_AND:
9263 case ISD::ATOMIC_LOAD_OR:
9264 case ISD::ATOMIC_LOAD_XOR:
9265 case ISD::ATOMIC_LOAD_NAND:
9266 case ISD::ATOMIC_LOAD_MIN:
9267 case ISD::ATOMIC_LOAD_MAX:
9268 case ISD::ATOMIC_LOAD_UMIN:
9269 case ISD::ATOMIC_LOAD_UMAX:
9270 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9271 atomic.getOperand(1), atomic.getOperand(2));
9277 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9278 DAGCombinerInfo &DCI) const {
9279 SelectionDAG &DAG = DCI.DAG;
9280 switch (N->getOpcode()) {
9282 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9283 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9284 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9285 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9288 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9289 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9291 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9292 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9293 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9294 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9295 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9301 //===----------------------------------------------------------------------===//
9302 // X86 Inline Assembly Support
9303 //===----------------------------------------------------------------------===//
9305 static bool LowerToBSwap(CallInst *CI) {
9306 // FIXME: this should verify that we are targetting a 486 or better. If not,
9307 // we will turn this bswap into something that will be lowered to logical ops
9308 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9309 // so don't worry about this.
9311 // Verify this is a simple bswap.
9312 if (CI->getNumOperands() != 2 ||
9313 CI->getType() != CI->getOperand(1)->getType() ||
9314 !CI->getType()->isInteger())
9317 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9318 if (!Ty || Ty->getBitWidth() % 16 != 0)
9321 // Okay, we can do this xform, do so now.
9322 const Type *Tys[] = { Ty };
9323 Module *M = CI->getParent()->getParent()->getParent();
9324 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9326 Value *Op = CI->getOperand(1);
9327 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9329 CI->replaceAllUsesWith(Op);
9330 CI->eraseFromParent();
9334 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9335 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9336 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9338 std::string AsmStr = IA->getAsmString();
9340 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9341 std::vector<std::string> AsmPieces;
9342 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9344 switch (AsmPieces.size()) {
9345 default: return false;
9347 AsmStr = AsmPieces[0];
9349 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9352 if (AsmPieces.size() == 2 &&
9353 (AsmPieces[0] == "bswap" ||
9354 AsmPieces[0] == "bswapq" ||
9355 AsmPieces[0] == "bswapl") &&
9356 (AsmPieces[1] == "$0" ||
9357 AsmPieces[1] == "${0:q}")) {
9358 // No need to check constraints, nothing other than the equivalent of
9359 // "=r,0" would be valid here.
9360 return LowerToBSwap(CI);
9362 // rorw $$8, ${0:w} --> llvm.bswap.i16
9363 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
9364 AsmPieces.size() == 3 &&
9365 AsmPieces[0] == "rorw" &&
9366 AsmPieces[1] == "$$8," &&
9367 AsmPieces[2] == "${0:w}" &&
9368 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9369 return LowerToBSwap(CI);
9373 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9374 Constraints.size() >= 2 &&
9375 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9376 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9377 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9378 std::vector<std::string> Words;
9379 SplitString(AsmPieces[0], Words, " \t");
9380 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9382 SplitString(AsmPieces[1], Words, " \t");
9383 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9385 SplitString(AsmPieces[2], Words, " \t,");
9386 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9387 Words[2] == "%edx") {
9388 return LowerToBSwap(CI);
9400 /// getConstraintType - Given a constraint letter, return the type of
9401 /// constraint it is for this target.
9402 X86TargetLowering::ConstraintType
9403 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9404 if (Constraint.size() == 1) {
9405 switch (Constraint[0]) {
9417 return C_RegisterClass;
9425 return TargetLowering::getConstraintType(Constraint);
9428 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9429 /// with another that has more specific requirements based on the type of the
9430 /// corresponding operand.
9431 const char *X86TargetLowering::
9432 LowerXConstraint(EVT ConstraintVT) const {
9433 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9434 // 'f' like normal targets.
9435 if (ConstraintVT.isFloatingPoint()) {
9436 if (Subtarget->hasSSE2())
9438 if (Subtarget->hasSSE1())
9442 return TargetLowering::LowerXConstraint(ConstraintVT);
9445 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9446 /// vector. If it is invalid, don't add anything to Ops.
9447 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9450 std::vector<SDValue>&Ops,
9451 SelectionDAG &DAG) const {
9452 SDValue Result(0, 0);
9454 switch (Constraint) {
9457 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9458 if (C->getZExtValue() <= 31) {
9459 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9466 if (C->getZExtValue() <= 63) {
9467 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9474 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9475 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9481 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9482 if (C->getZExtValue() <= 255) {
9483 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9489 // 32-bit signed value
9490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9491 const ConstantInt *CI = C->getConstantIntValue();
9492 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9493 C->getSExtValue())) {
9494 // Widen to 64 bits here to get it sign extended.
9495 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9498 // FIXME gcc accepts some relocatable values here too, but only in certain
9499 // memory models; it's complicated.
9504 // 32-bit unsigned value
9505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9506 const ConstantInt *CI = C->getConstantIntValue();
9507 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9508 C->getZExtValue())) {
9509 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9513 // FIXME gcc accepts some relocatable values here too, but only in certain
9514 // memory models; it's complicated.
9518 // Literal immediates are always ok.
9519 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9520 // Widen to 64 bits here to get it sign extended.
9521 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9525 // If we are in non-pic codegen mode, we allow the address of a global (with
9526 // an optional displacement) to be used with 'i'.
9527 GlobalAddressSDNode *GA = 0;
9530 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9532 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9533 Offset += GA->getOffset();
9535 } else if (Op.getOpcode() == ISD::ADD) {
9536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9537 Offset += C->getZExtValue();
9538 Op = Op.getOperand(0);
9541 } else if (Op.getOpcode() == ISD::SUB) {
9542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9543 Offset += -C->getZExtValue();
9544 Op = Op.getOperand(0);
9549 // Otherwise, this isn't something we can handle, reject it.
9553 GlobalValue *GV = GA->getGlobal();
9554 // If we require an extra load to get this address, as in PIC mode, we
9556 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9557 getTargetMachine())))
9561 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9563 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9569 if (Result.getNode()) {
9570 Ops.push_back(Result);
9573 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9577 std::vector<unsigned> X86TargetLowering::
9578 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9580 if (Constraint.size() == 1) {
9581 // FIXME: not handling fp-stack yet!
9582 switch (Constraint[0]) { // GCC X86 Constraint Letters
9583 default: break; // Unknown constraint letter
9584 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9585 if (Subtarget->is64Bit()) {
9587 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9588 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9589 X86::R10D,X86::R11D,X86::R12D,
9590 X86::R13D,X86::R14D,X86::R15D,
9591 X86::EBP, X86::ESP, 0);
9592 else if (VT == MVT::i16)
9593 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9594 X86::SI, X86::DI, X86::R8W,X86::R9W,
9595 X86::R10W,X86::R11W,X86::R12W,
9596 X86::R13W,X86::R14W,X86::R15W,
9597 X86::BP, X86::SP, 0);
9598 else if (VT == MVT::i8)
9599 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9600 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9601 X86::R10B,X86::R11B,X86::R12B,
9602 X86::R13B,X86::R14B,X86::R15B,
9603 X86::BPL, X86::SPL, 0);
9605 else if (VT == MVT::i64)
9606 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9607 X86::RSI, X86::RDI, X86::R8, X86::R9,
9608 X86::R10, X86::R11, X86::R12,
9609 X86::R13, X86::R14, X86::R15,
9610 X86::RBP, X86::RSP, 0);
9614 // 32-bit fallthrough
9617 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9618 else if (VT == MVT::i16)
9619 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9620 else if (VT == MVT::i8)
9621 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9622 else if (VT == MVT::i64)
9623 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9628 return std::vector<unsigned>();
9631 std::pair<unsigned, const TargetRegisterClass*>
9632 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9634 // First, see if this is a constraint that directly corresponds to an LLVM
9636 if (Constraint.size() == 1) {
9637 // GCC Constraint Letters
9638 switch (Constraint[0]) {
9640 case 'r': // GENERAL_REGS
9641 case 'l': // INDEX_REGS
9643 return std::make_pair(0U, X86::GR8RegisterClass);
9645 return std::make_pair(0U, X86::GR16RegisterClass);
9646 if (VT == MVT::i32 || !Subtarget->is64Bit())
9647 return std::make_pair(0U, X86::GR32RegisterClass);
9648 return std::make_pair(0U, X86::GR64RegisterClass);
9649 case 'R': // LEGACY_REGS
9651 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9653 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9654 if (VT == MVT::i32 || !Subtarget->is64Bit())
9655 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9656 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9657 case 'f': // FP Stack registers.
9658 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9659 // value to the correct fpstack register class.
9660 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9661 return std::make_pair(0U, X86::RFP32RegisterClass);
9662 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9663 return std::make_pair(0U, X86::RFP64RegisterClass);
9664 return std::make_pair(0U, X86::RFP80RegisterClass);
9665 case 'y': // MMX_REGS if MMX allowed.
9666 if (!Subtarget->hasMMX()) break;
9667 return std::make_pair(0U, X86::VR64RegisterClass);
9668 case 'Y': // SSE_REGS if SSE2 allowed
9669 if (!Subtarget->hasSSE2()) break;
9671 case 'x': // SSE_REGS if SSE1 allowed
9672 if (!Subtarget->hasSSE1()) break;
9674 switch (VT.getSimpleVT().SimpleTy) {
9676 // Scalar SSE types.
9679 return std::make_pair(0U, X86::FR32RegisterClass);
9682 return std::make_pair(0U, X86::FR64RegisterClass);
9690 return std::make_pair(0U, X86::VR128RegisterClass);
9696 // Use the default implementation in TargetLowering to convert the register
9697 // constraint into a member of a register class.
9698 std::pair<unsigned, const TargetRegisterClass*> Res;
9699 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9701 // Not found as a standard register?
9702 if (Res.second == 0) {
9703 // Map st(0) -> st(7) -> ST0
9704 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9705 tolower(Constraint[1]) == 's' &&
9706 tolower(Constraint[2]) == 't' &&
9707 Constraint[3] == '(' &&
9708 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9709 Constraint[5] == ')' &&
9710 Constraint[6] == '}') {
9712 Res.first = X86::ST0+Constraint[4]-'0';
9713 Res.second = X86::RFP80RegisterClass;
9717 // GCC allows "st(0)" to be called just plain "st".
9718 if (StringRef("{st}").equals_lower(Constraint)) {
9719 Res.first = X86::ST0;
9720 Res.second = X86::RFP80RegisterClass;
9725 if (StringRef("{flags}").equals_lower(Constraint)) {
9726 Res.first = X86::EFLAGS;
9727 Res.second = X86::CCRRegisterClass;
9731 // 'A' means EAX + EDX.
9732 if (Constraint == "A") {
9733 Res.first = X86::EAX;
9734 Res.second = X86::GR32_ADRegisterClass;
9740 // Otherwise, check to see if this is a register class of the wrong value
9741 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9742 // turn into {ax},{dx}.
9743 if (Res.second->hasType(VT))
9744 return Res; // Correct type already, nothing to do.
9746 // All of the single-register GCC register classes map their values onto
9747 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9748 // really want an 8-bit or 32-bit register, map to the appropriate register
9749 // class and return the appropriate register.
9750 if (Res.second == X86::GR16RegisterClass) {
9751 if (VT == MVT::i8) {
9752 unsigned DestReg = 0;
9753 switch (Res.first) {
9755 case X86::AX: DestReg = X86::AL; break;
9756 case X86::DX: DestReg = X86::DL; break;
9757 case X86::CX: DestReg = X86::CL; break;
9758 case X86::BX: DestReg = X86::BL; break;
9761 Res.first = DestReg;
9762 Res.second = X86::GR8RegisterClass;
9764 } else if (VT == MVT::i32) {
9765 unsigned DestReg = 0;
9766 switch (Res.first) {
9768 case X86::AX: DestReg = X86::EAX; break;
9769 case X86::DX: DestReg = X86::EDX; break;
9770 case X86::CX: DestReg = X86::ECX; break;
9771 case X86::BX: DestReg = X86::EBX; break;
9772 case X86::SI: DestReg = X86::ESI; break;
9773 case X86::DI: DestReg = X86::EDI; break;
9774 case X86::BP: DestReg = X86::EBP; break;
9775 case X86::SP: DestReg = X86::ESP; break;
9778 Res.first = DestReg;
9779 Res.second = X86::GR32RegisterClass;
9781 } else if (VT == MVT::i64) {
9782 unsigned DestReg = 0;
9783 switch (Res.first) {
9785 case X86::AX: DestReg = X86::RAX; break;
9786 case X86::DX: DestReg = X86::RDX; break;
9787 case X86::CX: DestReg = X86::RCX; break;
9788 case X86::BX: DestReg = X86::RBX; break;
9789 case X86::SI: DestReg = X86::RSI; break;
9790 case X86::DI: DestReg = X86::RDI; break;
9791 case X86::BP: DestReg = X86::RBP; break;
9792 case X86::SP: DestReg = X86::RSP; break;
9795 Res.first = DestReg;
9796 Res.second = X86::GR64RegisterClass;
9799 } else if (Res.second == X86::FR32RegisterClass ||
9800 Res.second == X86::FR64RegisterClass ||
9801 Res.second == X86::VR128RegisterClass) {
9802 // Handle references to XMM physical registers that got mapped into the
9803 // wrong class. This can happen with constraints like {xmm0} where the
9804 // target independent register mapper will just pick the first match it can
9805 // find, ignoring the required type.
9807 Res.second = X86::FR32RegisterClass;
9808 else if (VT == MVT::f64)
9809 Res.second = X86::FR64RegisterClass;
9810 else if (X86::VR128RegisterClass->hasType(VT))
9811 Res.second = X86::VR128RegisterClass;
9817 //===----------------------------------------------------------------------===//
9818 // X86 Widen vector type
9819 //===----------------------------------------------------------------------===//
9821 /// getWidenVectorType: given a vector type, returns the type to widen
9822 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9823 /// If there is no vector type that we want to widen to, returns MVT::Other
9824 /// When and where to widen is target dependent based on the cost of
9825 /// scalarizing vs using the wider vector type.
9827 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9828 assert(VT.isVector());
9829 if (isTypeLegal(VT))
9832 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9833 // type based on element type. This would speed up our search (though
9834 // it may not be worth it since the size of the list is relatively
9836 EVT EltVT = VT.getVectorElementType();
9837 unsigned NElts = VT.getVectorNumElements();
9839 // On X86, it make sense to widen any vector wider than 1
9843 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9844 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9845 EVT SVT = (MVT::SimpleValueType)nVT;
9847 if (isTypeLegal(SVT) &&
9848 SVT.getVectorElementType() == EltVT &&
9849 SVT.getVectorNumElements() > NElts)