1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/VariadicFunction.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
81 SelectionDAG &DAG, SDLoc dl,
82 unsigned vectorWidth) {
83 assert((vectorWidth == 128 || vectorWidth == 256) &&
84 "Unsupported vector width");
85 EVT VT = Vec.getValueType();
86 EVT ElVT = VT.getVectorElementType();
87 unsigned Factor = VT.getSizeInBits()/vectorWidth;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getUNDEF(ResultVT);
95 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
96 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
98 // This is the index of the first element of the vectorWidth-bit chunk
100 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
103 // If the input is a buildvector just emit a smaller one.
104 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
105 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
106 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
109 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
110 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
113 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
114 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
115 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
116 /// instructions or a simple subregister reference. Idx is an index in the
117 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
118 /// lowering EXTRACT_VECTOR_ELT operations easier.
119 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
120 SelectionDAG &DAG, SDLoc dl) {
121 assert((Vec.getValueType().is256BitVector() ||
122 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
123 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
126 /// Generate a DAG to grab 256-bits from a 512-bit vector.
127 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
128 SelectionDAG &DAG, SDLoc dl) {
129 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
133 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
134 unsigned IdxVal, SelectionDAG &DAG,
135 SDLoc dl, unsigned vectorWidth) {
136 assert((vectorWidth == 128 || vectorWidth == 256) &&
137 "Unsupported vector width");
138 // Inserting UNDEF is Result
139 if (Vec.getOpcode() == ISD::UNDEF)
141 EVT VT = Vec.getValueType();
142 EVT ElVT = VT.getVectorElementType();
143 EVT ResultVT = Result.getValueType();
145 // Insert the relevant vectorWidth bits.
146 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
148 // This is the index of the first element of the vectorWidth-bit chunk
150 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
153 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
154 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
157 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
158 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
159 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
160 /// simple superregister reference. Idx is an index in the 128 bits
161 /// we want. It need not be aligned to a 128-bit boundary. That makes
162 /// lowering INSERT_VECTOR_ELT operations easier.
163 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
164 SelectionDAG &DAG,SDLoc dl) {
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
170 SelectionDAG &DAG, SDLoc dl) {
171 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
172 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
175 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
176 /// instructions. This is used because creating CONCAT_VECTOR nodes of
177 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
178 /// large BUILD_VECTORS.
179 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
180 unsigned NumElems, SelectionDAG &DAG,
182 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
183 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
186 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
187 unsigned NumElems, SelectionDAG &DAG,
189 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
190 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
193 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
194 const X86Subtarget &STI)
195 : TargetLowering(TM), Subtarget(&STI) {
196 X86ScalarSSEf64 = Subtarget->hasSSE2();
197 X86ScalarSSEf32 = Subtarget->hasSSE1();
198 TD = getDataLayout();
200 // Set up the TargetLowering object.
201 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
203 // X86 is weird. It always uses i8 for shift amounts and setcc results.
204 setBooleanContents(ZeroOrOneBooleanContent);
205 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
206 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
208 // For 64-bit, since we have so many registers, use the ILP scheduler.
209 // For 32-bit, use the register pressure specific scheduling.
210 // For Atom, always use ILP scheduling.
211 if (Subtarget->isAtom())
212 setSchedulingPreference(Sched::ILP);
213 else if (Subtarget->is64Bit())
214 setSchedulingPreference(Sched::ILP);
216 setSchedulingPreference(Sched::RegPressure);
217 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
218 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
220 // Bypass expensive divides on Atom when compiling with O2.
221 if (TM.getOptLevel() >= CodeGenOpt::Default) {
222 if (Subtarget->hasSlowDivide32())
223 addBypassSlowDiv(32, 8);
224 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
225 addBypassSlowDiv(64, 16);
228 if (Subtarget->isTargetKnownWindowsMSVC()) {
229 // Setup Windows compiler runtime calls.
230 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
231 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
232 setLibcallName(RTLIB::SREM_I64, "_allrem");
233 setLibcallName(RTLIB::UREM_I64, "_aullrem");
234 setLibcallName(RTLIB::MUL_I64, "_allmul");
235 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
236 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
237 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
238 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
239 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
241 // The _ftol2 runtime function has an unusual calling conv, which
242 // is modeled by a special pseudo-instruction.
243 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
244 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
245 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
246 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
249 if (Subtarget->isTargetDarwin()) {
250 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
251 setUseUnderscoreSetJmp(false);
252 setUseUnderscoreLongJmp(false);
253 } else if (Subtarget->isTargetWindowsGNU()) {
254 // MS runtime is weird: it exports _setjmp, but longjmp!
255 setUseUnderscoreSetJmp(true);
256 setUseUnderscoreLongJmp(false);
258 setUseUnderscoreSetJmp(true);
259 setUseUnderscoreLongJmp(true);
262 // Set up the register classes.
263 addRegisterClass(MVT::i8, &X86::GR8RegClass);
264 addRegisterClass(MVT::i16, &X86::GR16RegClass);
265 addRegisterClass(MVT::i32, &X86::GR32RegClass);
266 if (Subtarget->is64Bit())
267 addRegisterClass(MVT::i64, &X86::GR64RegClass);
269 for (MVT VT : MVT::integer_valuetypes())
270 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
272 // We don't accept any truncstore of integer registers.
273 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
274 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
275 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
276 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
277 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
278 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
280 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
282 // SETOEQ and SETUNE require checking two conditions.
283 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
284 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
285 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
286 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
287 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
288 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
290 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
292 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
293 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
294 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
298 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
299 } else if (!TM.Options.UseSoftFloat) {
300 // We have an algorithm for SSE2->double, and we turn this into a
301 // 64-bit FILD followed by conditional FADD for other targets.
302 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
303 // We have an algorithm for SSE2, and we turn this into a 64-bit
304 // FILD for other targets.
305 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
308 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
310 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
311 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
313 if (!TM.Options.UseSoftFloat) {
314 // SSE has no i16 to fp conversion, only i32
315 if (X86ScalarSSEf32) {
316 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
317 // f32 and f64 cases are Legal, f80 case is not
318 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
320 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
321 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
324 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
325 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
328 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
329 // are Legal, f80 is custom lowered.
330 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
333 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
335 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
336 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
338 if (X86ScalarSSEf32) {
339 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
340 // f32 and f64 cases are Legal, f80 case is not
341 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
343 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
344 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
347 // Handle FP_TO_UINT by promoting the destination to a larger signed
349 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
350 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
351 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
353 if (Subtarget->is64Bit()) {
354 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
355 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
356 } else if (!TM.Options.UseSoftFloat) {
357 // Since AVX is a superset of SSE3, only check for SSE here.
358 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
359 // Expand FP_TO_UINT into a select.
360 // FIXME: We would like to use a Custom expander here eventually to do
361 // the optimal thing for SSE vs. the default expansion in the legalizer.
362 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
364 // With SSE3 we can use fisttpll to convert to a signed i64; without
365 // SSE, we're stuck with a fistpll.
366 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
369 if (isTargetFTOL()) {
370 // Use the _ftol2 runtime function, which has a pseudo-instruction
371 // to handle its weird calling convention.
372 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
375 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
376 if (!X86ScalarSSEf64) {
377 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
378 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
379 if (Subtarget->is64Bit()) {
380 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
381 // Without SSE, i64->f64 goes through memory.
382 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
386 // Scalar integer divide and remainder are lowered to use operations that
387 // produce two results, to match the available instructions. This exposes
388 // the two-result form to trivial CSE, which is able to combine x/y and x%y
389 // into a single instruction.
391 // Scalar integer multiply-high is also lowered to use two-result
392 // operations, to match the available instructions. However, plain multiply
393 // (low) operations are left as Legal, as there are single-result
394 // instructions for this in x86. Using the two-result multiply instructions
395 // when both high and low results are needed must be arranged by dagcombine.
396 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
398 setOperationAction(ISD::MULHS, VT, Expand);
399 setOperationAction(ISD::MULHU, VT, Expand);
400 setOperationAction(ISD::SDIV, VT, Expand);
401 setOperationAction(ISD::UDIV, VT, Expand);
402 setOperationAction(ISD::SREM, VT, Expand);
403 setOperationAction(ISD::UREM, VT, Expand);
405 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
406 setOperationAction(ISD::ADDC, VT, Custom);
407 setOperationAction(ISD::ADDE, VT, Custom);
408 setOperationAction(ISD::SUBC, VT, Custom);
409 setOperationAction(ISD::SUBE, VT, Custom);
412 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
413 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
414 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
415 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
416 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
417 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
418 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
419 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
420 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
421 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
422 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
423 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
424 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
425 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
426 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
427 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
430 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
431 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
432 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
433 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
434 setOperationAction(ISD::FREM , MVT::f32 , Expand);
435 setOperationAction(ISD::FREM , MVT::f64 , Expand);
436 setOperationAction(ISD::FREM , MVT::f80 , Expand);
437 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
439 // Promote the i8 variants and force them on up to i32 which has a shorter
441 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
442 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
443 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
444 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
445 if (Subtarget->hasBMI()) {
446 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
447 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
448 if (Subtarget->is64Bit())
449 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
451 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
452 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
457 if (Subtarget->hasLZCNT()) {
458 // When promoting the i8 variants, force them to i32 for a shorter
460 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
461 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
462 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
463 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
464 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
466 if (Subtarget->is64Bit())
467 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
469 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
470 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
471 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
473 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
474 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
481 // Special handling for half-precision floating point conversions.
482 // If we don't have F16C support, then lower half float conversions
483 // into library calls.
484 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
485 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
486 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
489 // There's never any support for operations beyond MVT::f32.
490 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
491 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
492 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
493 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
495 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
496 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
497 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
498 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
499 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
500 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
502 if (Subtarget->hasPOPCNT()) {
503 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
505 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
506 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
507 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
508 if (Subtarget->is64Bit())
509 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
512 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
514 if (!Subtarget->hasMOVBE())
515 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
517 // These should be promoted to a larger select which is supported.
518 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
519 // X86 wants to expand cmov itself.
520 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
521 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
522 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
523 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
524 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
525 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
528 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
529 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
530 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
531 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
532 if (Subtarget->is64Bit()) {
533 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
534 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
536 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
537 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
538 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
539 // support continuation, user-level threading, and etc.. As a result, no
540 // other SjLj exception interfaces are implemented and please don't build
541 // your own exception handling based on them.
542 // LLVM/Clang supports zero-cost DWARF exception handling.
543 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
544 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
547 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
550 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
551 if (Subtarget->is64Bit())
552 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
553 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
554 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
557 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
558 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
559 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
560 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
562 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
563 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
564 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
565 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
566 if (Subtarget->is64Bit()) {
567 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
568 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
569 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
572 if (Subtarget->hasSSE1())
573 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
575 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
577 // Expand certain atomics
578 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
580 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
582 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
585 if (Subtarget->hasCmpxchg16b()) {
586 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
589 // FIXME - use subtarget debug flags
590 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
591 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
592 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
595 if (Subtarget->is64Bit()) {
596 setExceptionPointerRegister(X86::RAX);
597 setExceptionSelectorRegister(X86::RDX);
599 setExceptionPointerRegister(X86::EAX);
600 setExceptionSelectorRegister(X86::EDX);
602 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
603 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
605 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
606 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
608 setOperationAction(ISD::TRAP, MVT::Other, Legal);
609 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
611 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
612 setOperationAction(ISD::VASTART , MVT::Other, Custom);
613 setOperationAction(ISD::VAEND , MVT::Other, Expand);
614 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
615 // TargetInfo::X86_64ABIBuiltinVaList
616 setOperationAction(ISD::VAARG , MVT::Other, Custom);
617 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
619 // TargetInfo::CharPtrBuiltinVaList
620 setOperationAction(ISD::VAARG , MVT::Other, Expand);
621 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
624 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
625 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
627 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
629 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
630 // f32 and f64 use SSE.
631 // Set up the FP register classes.
632 addRegisterClass(MVT::f32, &X86::FR32RegClass);
633 addRegisterClass(MVT::f64, &X86::FR64RegClass);
635 // Use ANDPD to simulate FABS.
636 setOperationAction(ISD::FABS , MVT::f64, Custom);
637 setOperationAction(ISD::FABS , MVT::f32, Custom);
639 // Use XORP to simulate FNEG.
640 setOperationAction(ISD::FNEG , MVT::f64, Custom);
641 setOperationAction(ISD::FNEG , MVT::f32, Custom);
643 // Use ANDPD and ORPD to simulate FCOPYSIGN.
644 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
645 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
647 // Lower this to FGETSIGNx86 plus an AND.
648 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
649 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
651 // We don't support sin/cos/fmod
652 setOperationAction(ISD::FSIN , MVT::f64, Expand);
653 setOperationAction(ISD::FCOS , MVT::f64, Expand);
654 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
655 setOperationAction(ISD::FSIN , MVT::f32, Expand);
656 setOperationAction(ISD::FCOS , MVT::f32, Expand);
657 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
659 // Expand FP immediates into loads from the stack, except for the special
661 addLegalFPImmediate(APFloat(+0.0)); // xorpd
662 addLegalFPImmediate(APFloat(+0.0f)); // xorps
663 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
664 // Use SSE for f32, x87 for f64.
665 // Set up the FP register classes.
666 addRegisterClass(MVT::f32, &X86::FR32RegClass);
667 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
669 // Use ANDPS to simulate FABS.
670 setOperationAction(ISD::FABS , MVT::f32, Custom);
672 // Use XORP to simulate FNEG.
673 setOperationAction(ISD::FNEG , MVT::f32, Custom);
675 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
677 // Use ANDPS and ORPS to simulate FCOPYSIGN.
678 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
679 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
681 // We don't support sin/cos/fmod
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Special cases we handle for FP constants.
687 addLegalFPImmediate(APFloat(+0.0f)); // xorps
688 addLegalFPImmediate(APFloat(+0.0)); // FLD0
689 addLegalFPImmediate(APFloat(+1.0)); // FLD1
690 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
691 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
693 if (!TM.Options.UnsafeFPMath) {
694 setOperationAction(ISD::FSIN , MVT::f64, Expand);
695 setOperationAction(ISD::FCOS , MVT::f64, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
698 } else if (!TM.Options.UseSoftFloat) {
699 // f32 and f64 in x87.
700 // Set up the FP register classes.
701 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
702 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
704 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FSIN , MVT::f32, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FCOS , MVT::f32, Expand);
714 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
717 addLegalFPImmediate(APFloat(+0.0)); // FLD0
718 addLegalFPImmediate(APFloat(+1.0)); // FLD1
719 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
720 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
722 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
723 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
724 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
727 // We don't support FMA.
728 setOperationAction(ISD::FMA, MVT::f64, Expand);
729 setOperationAction(ISD::FMA, MVT::f32, Expand);
731 // Long double always uses X87.
732 if (!TM.Options.UseSoftFloat) {
733 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
734 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
737 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
738 addLegalFPImmediate(TmpFlt); // FLD0
740 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
743 APFloat TmpFlt2(+1.0);
744 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
746 addLegalFPImmediate(TmpFlt2); // FLD1
747 TmpFlt2.changeSign();
748 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
751 if (!TM.Options.UnsafeFPMath) {
752 setOperationAction(ISD::FSIN , MVT::f80, Expand);
753 setOperationAction(ISD::FCOS , MVT::f80, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
757 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
758 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
760 setOperationAction(ISD::FRINT, MVT::f80, Expand);
761 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
762 setOperationAction(ISD::FMA, MVT::f80, Expand);
765 // Always use a library call for pow.
766 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
767 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
768 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
770 setOperationAction(ISD::FLOG, MVT::f80, Expand);
771 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
772 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
773 setOperationAction(ISD::FEXP, MVT::f80, Expand);
774 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
775 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
776 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
778 // First set operation action for all vector types to either promote
779 // (for widening) or expand (for scalarization). Then we will selectively
780 // turn on ones that can be effectively codegen'd.
781 for (MVT VT : MVT::vector_valuetypes()) {
782 setOperationAction(ISD::ADD , VT, Expand);
783 setOperationAction(ISD::SUB , VT, Expand);
784 setOperationAction(ISD::FADD, VT, Expand);
785 setOperationAction(ISD::FNEG, VT, Expand);
786 setOperationAction(ISD::FSUB, VT, Expand);
787 setOperationAction(ISD::MUL , VT, Expand);
788 setOperationAction(ISD::FMUL, VT, Expand);
789 setOperationAction(ISD::SDIV, VT, Expand);
790 setOperationAction(ISD::UDIV, VT, Expand);
791 setOperationAction(ISD::FDIV, VT, Expand);
792 setOperationAction(ISD::SREM, VT, Expand);
793 setOperationAction(ISD::UREM, VT, Expand);
794 setOperationAction(ISD::LOAD, VT, Expand);
795 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
797 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
798 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
799 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
800 setOperationAction(ISD::FABS, VT, Expand);
801 setOperationAction(ISD::FSIN, VT, Expand);
802 setOperationAction(ISD::FSINCOS, VT, Expand);
803 setOperationAction(ISD::FCOS, VT, Expand);
804 setOperationAction(ISD::FSINCOS, VT, Expand);
805 setOperationAction(ISD::FREM, VT, Expand);
806 setOperationAction(ISD::FMA, VT, Expand);
807 setOperationAction(ISD::FPOWI, VT, Expand);
808 setOperationAction(ISD::FSQRT, VT, Expand);
809 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
810 setOperationAction(ISD::FFLOOR, VT, Expand);
811 setOperationAction(ISD::FCEIL, VT, Expand);
812 setOperationAction(ISD::FTRUNC, VT, Expand);
813 setOperationAction(ISD::FRINT, VT, Expand);
814 setOperationAction(ISD::FNEARBYINT, VT, Expand);
815 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
816 setOperationAction(ISD::MULHS, VT, Expand);
817 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
818 setOperationAction(ISD::MULHU, VT, Expand);
819 setOperationAction(ISD::SDIVREM, VT, Expand);
820 setOperationAction(ISD::UDIVREM, VT, Expand);
821 setOperationAction(ISD::FPOW, VT, Expand);
822 setOperationAction(ISD::CTPOP, VT, Expand);
823 setOperationAction(ISD::CTTZ, VT, Expand);
824 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
825 setOperationAction(ISD::CTLZ, VT, Expand);
826 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
827 setOperationAction(ISD::SHL, VT, Expand);
828 setOperationAction(ISD::SRA, VT, Expand);
829 setOperationAction(ISD::SRL, VT, Expand);
830 setOperationAction(ISD::ROTL, VT, Expand);
831 setOperationAction(ISD::ROTR, VT, Expand);
832 setOperationAction(ISD::BSWAP, VT, Expand);
833 setOperationAction(ISD::SETCC, VT, Expand);
834 setOperationAction(ISD::FLOG, VT, Expand);
835 setOperationAction(ISD::FLOG2, VT, Expand);
836 setOperationAction(ISD::FLOG10, VT, Expand);
837 setOperationAction(ISD::FEXP, VT, Expand);
838 setOperationAction(ISD::FEXP2, VT, Expand);
839 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
840 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
841 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
842 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
843 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
844 setOperationAction(ISD::TRUNCATE, VT, Expand);
845 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
846 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
847 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
848 setOperationAction(ISD::VSELECT, VT, Expand);
849 setOperationAction(ISD::SELECT_CC, VT, Expand);
850 for (MVT InnerVT : MVT::vector_valuetypes()) {
851 setTruncStoreAction(InnerVT, VT, Expand);
853 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
854 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
856 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
857 // types, we have to deal with them whether we ask for Expansion or not.
858 // Setting Expand causes its own optimisation problems though, so leave
860 if (VT.getVectorElementType() == MVT::i1)
861 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
865 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
866 // with -msoft-float, disable use of MMX as well.
867 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
868 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
869 // No operations on x86mmx supported, everything uses intrinsics.
872 // MMX-sized vectors (other than x86mmx) are expected to be expanded
873 // into smaller operations.
874 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
875 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
876 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
877 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
878 setOperationAction(ISD::AND, MVT::v8i8, Expand);
879 setOperationAction(ISD::AND, MVT::v4i16, Expand);
880 setOperationAction(ISD::AND, MVT::v2i32, Expand);
881 setOperationAction(ISD::AND, MVT::v1i64, Expand);
882 setOperationAction(ISD::OR, MVT::v8i8, Expand);
883 setOperationAction(ISD::OR, MVT::v4i16, Expand);
884 setOperationAction(ISD::OR, MVT::v2i32, Expand);
885 setOperationAction(ISD::OR, MVT::v1i64, Expand);
886 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
887 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
888 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
889 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
890 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
891 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
892 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
895 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
896 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
897 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
898 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
899 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
900 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
901 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
902 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
904 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
905 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
907 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
908 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
909 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
910 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
911 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
912 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
913 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
914 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
917 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
919 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
920 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
923 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
924 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
926 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
927 // registers cannot be used even for integer operations.
928 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
929 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
930 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
931 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
933 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
934 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
935 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
936 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
937 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
938 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
939 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
940 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
941 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
942 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Only provide customized ctpop vector bit twiddling for vector types we
968 // know to perform better than using the popcnt instructions on each vector
969 // element. If popcnt isn't supported, always provide the custom version.
970 if (!Subtarget->hasPOPCNT()) {
971 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
972 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
975 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
976 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
977 MVT VT = (MVT::SimpleValueType)i;
978 // Do not attempt to custom lower non-power-of-2 vectors
979 if (!isPowerOf2_32(VT.getVectorNumElements()))
981 // Do not attempt to custom lower non-128-bit vectors
982 if (!VT.is128BitVector())
984 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
986 setOperationAction(ISD::VSELECT, VT, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
990 // We support custom legalizing of sext and anyext loads for specific
991 // memory vector types which we can load as a scalar (or sequence of
992 // scalars) and extend in-register to a legal 128-bit vector type. For sext
993 // loads these must work with a single scalar load.
994 for (MVT VT : MVT::integer_vector_valuetypes()) {
995 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
996 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
997 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
998 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
999 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1000 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1001 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1002 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1003 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1006 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1007 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1010 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1011 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1013 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1015 if (Subtarget->is64Bit()) {
1016 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1020 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1021 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1022 MVT VT = (MVT::SimpleValueType)i;
1024 // Do not attempt to promote non-128-bit vectors
1025 if (!VT.is128BitVector())
1028 setOperationAction(ISD::AND, VT, Promote);
1029 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1030 setOperationAction(ISD::OR, VT, Promote);
1031 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1032 setOperationAction(ISD::XOR, VT, Promote);
1033 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1034 setOperationAction(ISD::LOAD, VT, Promote);
1035 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1036 setOperationAction(ISD::SELECT, VT, Promote);
1037 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1040 // Custom lower v2i64 and v2f64 selects.
1041 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1042 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1043 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1044 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1046 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1047 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1049 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1050 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1051 // As there is no 64-bit GPR available, we need build a special custom
1052 // sequence to convert from v2i32 to v2f32.
1053 if (!Subtarget->is64Bit())
1054 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1056 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1057 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1059 for (MVT VT : MVT::fp_vector_valuetypes())
1060 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1062 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1063 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1064 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1067 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1068 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1069 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1070 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1071 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1072 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1073 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1074 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1075 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1076 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1077 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1079 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1080 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1081 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1082 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1083 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1084 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1085 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1086 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1087 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1088 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1090 // FIXME: Do we need to handle scalar-to-vector here?
1091 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1093 // We directly match byte blends in the backend as they match the VSELECT
1095 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1097 // SSE41 brings specific instructions for doing vector sign extend even in
1098 // cases where we don't have SRA.
1099 for (MVT VT : MVT::integer_vector_valuetypes()) {
1100 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1101 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1102 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1105 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1106 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1107 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1108 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1109 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1110 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1111 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1113 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1114 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1115 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1116 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1117 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1118 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1120 // i8 and i16 vectors are custom because the source register and source
1121 // source memory operand types are not the same width. f32 vectors are
1122 // custom since the immediate controlling the insert encodes additional
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1134 // FIXME: these should be Legal, but that's only for the case where
1135 // the index is constant. For now custom expand to deal with that.
1136 if (Subtarget->is64Bit()) {
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1142 if (Subtarget->hasSSE2()) {
1143 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1149 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1150 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1152 // In the customized shift lowering, the legal cases in AVX2 will be
1154 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1160 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1163 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1164 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1171 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1172 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1186 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1199 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1201 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1202 // even though v8i16 is a legal type.
1203 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1204 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1207 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1209 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1211 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1214 for (MVT VT : MVT::fp_vector_valuetypes())
1215 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1238 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1239 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1240 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1241 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1245 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1246 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1248 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1249 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1250 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1251 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1252 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1253 setOperationAction(ISD::FMA, MVT::f32, Legal);
1254 setOperationAction(ISD::FMA, MVT::f64, Legal);
1257 if (Subtarget->hasInt256()) {
1258 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1259 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1260 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1261 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1263 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1264 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1265 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1266 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1268 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1269 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1270 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1271 // Don't lower v32i8 because there is no 128-bit byte mul
1273 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1274 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1275 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1276 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1278 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1279 // when we have a 256bit-wide blend with immediate.
1280 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1282 // Only provide customized ctpop vector bit twiddling for vector types we
1283 // know to perform better than using the popcnt instructions on each
1284 // vector element. If popcnt isn't supported, always provide the custom
1286 if (!Subtarget->hasPOPCNT())
1287 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1289 // Custom CTPOP always performs better on natively supported v8i32
1290 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1292 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1293 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1294 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1295 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1296 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1297 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1298 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1300 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1301 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1302 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1303 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1304 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1307 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1308 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1309 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1310 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1312 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1315 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1317 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1318 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1320 // Don't lower v32i8 because there is no 128-bit byte mul
1323 // In the customized shift lowering, the legal cases in AVX2 will be
1325 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1329 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1331 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1333 // Custom lower several nodes for 256-bit types.
1334 for (MVT VT : MVT::vector_valuetypes()) {
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::VSELECT, VT, Custom);
1351 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1353 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1354 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1355 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1358 if (Subtarget->hasInt256())
1359 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1362 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1363 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1364 MVT VT = (MVT::SimpleValueType)i;
1366 // Do not attempt to promote non-256-bit vectors
1367 if (!VT.is256BitVector())
1370 setOperationAction(ISD::AND, VT, Promote);
1371 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1372 setOperationAction(ISD::OR, VT, Promote);
1373 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1374 setOperationAction(ISD::XOR, VT, Promote);
1375 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1376 setOperationAction(ISD::LOAD, VT, Promote);
1377 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1378 setOperationAction(ISD::SELECT, VT, Promote);
1379 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1383 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1384 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1385 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1386 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1387 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1389 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1390 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1391 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1393 for (MVT VT : MVT::fp_vector_valuetypes())
1394 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1396 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1397 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1398 setOperationAction(ISD::XOR, MVT::i1, Legal);
1399 setOperationAction(ISD::OR, MVT::i1, Legal);
1400 setOperationAction(ISD::AND, MVT::i1, Legal);
1401 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1402 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1403 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1404 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1405 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1407 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1414 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1415 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1416 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1417 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1418 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1419 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1420 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1421 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1424 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1425 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1427 if (Subtarget->is64Bit()) {
1428 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1429 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1431 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1433 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1434 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1435 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1436 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1438 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1439 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1440 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1441 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1442 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1443 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1444 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1445 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1446 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1448 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1449 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1450 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1451 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1452 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1453 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1454 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1455 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1457 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1459 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1460 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1462 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1463 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1464 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1465 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1466 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1467 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1468 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1469 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1470 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1471 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1475 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1476 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1477 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1478 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1480 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1481 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1483 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1485 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1486 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1487 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1488 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1489 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1490 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1491 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1492 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1495 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1496 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1498 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1499 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1501 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1503 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1504 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1506 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1507 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1509 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1510 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1512 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1513 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1514 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1515 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1516 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1517 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1519 if (Subtarget->hasCDI()) {
1520 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1521 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1524 // Custom lower several nodes.
1525 for (MVT VT : MVT::vector_valuetypes()) {
1526 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1527 // Extract subvector is special because the value type
1528 // (result) is 256/128-bit but the source is 512-bit wide.
1529 if (VT.is128BitVector() || VT.is256BitVector()) {
1530 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1532 if (VT.getVectorElementType() == MVT::i1)
1533 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1535 // Do not attempt to custom lower other non-512-bit vectors
1536 if (!VT.is512BitVector())
1539 if ( EltSize >= 32) {
1540 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1541 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1542 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1543 setOperationAction(ISD::VSELECT, VT, Legal);
1544 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1545 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1546 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1547 setOperationAction(ISD::MLOAD, VT, Legal);
1548 setOperationAction(ISD::MSTORE, VT, Legal);
1551 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1552 MVT VT = (MVT::SimpleValueType)i;
1554 // Do not attempt to promote non-512-bit vectors.
1555 if (!VT.is512BitVector())
1558 setOperationAction(ISD::SELECT, VT, Promote);
1559 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1563 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1564 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1565 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1567 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1568 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1570 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1571 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1572 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1573 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1574 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1575 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1576 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1577 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1578 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1580 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1581 const MVT VT = (MVT::SimpleValueType)i;
1583 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1585 // Do not attempt to promote non-512-bit vectors.
1586 if (!VT.is512BitVector())
1590 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1591 setOperationAction(ISD::VSELECT, VT, Legal);
1596 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1597 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1598 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1600 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1601 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1602 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1604 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1605 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1606 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1607 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1608 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1609 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1612 // We want to custom lower some of our intrinsics.
1613 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1614 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1615 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1616 if (!Subtarget->is64Bit())
1617 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1619 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1620 // handle type legalization for these operations here.
1622 // FIXME: We really should do custom legalization for addition and
1623 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1624 // than generic legalization for 64-bit multiplication-with-overflow, though.
1625 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1626 // Add/Sub/Mul with overflow operations are custom lowered.
1628 setOperationAction(ISD::SADDO, VT, Custom);
1629 setOperationAction(ISD::UADDO, VT, Custom);
1630 setOperationAction(ISD::SSUBO, VT, Custom);
1631 setOperationAction(ISD::USUBO, VT, Custom);
1632 setOperationAction(ISD::SMULO, VT, Custom);
1633 setOperationAction(ISD::UMULO, VT, Custom);
1637 if (!Subtarget->is64Bit()) {
1638 // These libcalls are not available in 32-bit.
1639 setLibcallName(RTLIB::SHL_I128, nullptr);
1640 setLibcallName(RTLIB::SRL_I128, nullptr);
1641 setLibcallName(RTLIB::SRA_I128, nullptr);
1644 // Combine sin / cos into one node or libcall if possible.
1645 if (Subtarget->hasSinCos()) {
1646 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1647 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1648 if (Subtarget->isTargetDarwin()) {
1649 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1650 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1651 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1652 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1656 if (Subtarget->isTargetWin64()) {
1657 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1658 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1659 setOperationAction(ISD::SREM, MVT::i128, Custom);
1660 setOperationAction(ISD::UREM, MVT::i128, Custom);
1661 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1662 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1665 // We have target-specific dag combine patterns for the following nodes:
1666 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1667 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1668 setTargetDAGCombine(ISD::BITCAST);
1669 setTargetDAGCombine(ISD::VSELECT);
1670 setTargetDAGCombine(ISD::SELECT);
1671 setTargetDAGCombine(ISD::SHL);
1672 setTargetDAGCombine(ISD::SRA);
1673 setTargetDAGCombine(ISD::SRL);
1674 setTargetDAGCombine(ISD::OR);
1675 setTargetDAGCombine(ISD::AND);
1676 setTargetDAGCombine(ISD::ADD);
1677 setTargetDAGCombine(ISD::FADD);
1678 setTargetDAGCombine(ISD::FSUB);
1679 setTargetDAGCombine(ISD::FMA);
1680 setTargetDAGCombine(ISD::SUB);
1681 setTargetDAGCombine(ISD::LOAD);
1682 setTargetDAGCombine(ISD::MLOAD);
1683 setTargetDAGCombine(ISD::STORE);
1684 setTargetDAGCombine(ISD::MSTORE);
1685 setTargetDAGCombine(ISD::ZERO_EXTEND);
1686 setTargetDAGCombine(ISD::ANY_EXTEND);
1687 setTargetDAGCombine(ISD::SIGN_EXTEND);
1688 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1689 setTargetDAGCombine(ISD::TRUNCATE);
1690 setTargetDAGCombine(ISD::SINT_TO_FP);
1691 setTargetDAGCombine(ISD::SETCC);
1692 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1693 setTargetDAGCombine(ISD::BUILD_VECTOR);
1694 setTargetDAGCombine(ISD::MUL);
1695 setTargetDAGCombine(ISD::XOR);
1697 computeRegisterProperties(Subtarget->getRegisterInfo());
1699 // On Darwin, -Os means optimize for size without hurting performance,
1700 // do not reduce the limit.
1701 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1702 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1703 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1704 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1705 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1706 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1707 setPrefLoopAlignment(4); // 2^4 bytes.
1709 // Predictable cmov don't hurt on atom because it's in-order.
1710 PredictableSelectIsExpensive = !Subtarget->isAtom();
1711 EnableExtLdPromotion = true;
1712 setPrefFunctionAlignment(4); // 2^4 bytes.
1714 verifyIntrinsicTables();
1717 // This has so far only been implemented for 64-bit MachO.
1718 bool X86TargetLowering::useLoadStackGuardNode() const {
1719 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1722 TargetLoweringBase::LegalizeTypeAction
1723 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1724 if (ExperimentalVectorWideningLegalization &&
1725 VT.getVectorNumElements() != 1 &&
1726 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1727 return TypeWidenVector;
1729 return TargetLoweringBase::getPreferredVectorAction(VT);
1732 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1734 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1736 const unsigned NumElts = VT.getVectorNumElements();
1737 const EVT EltVT = VT.getVectorElementType();
1738 if (VT.is512BitVector()) {
1739 if (Subtarget->hasAVX512())
1740 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1741 EltVT == MVT::f32 || EltVT == MVT::f64)
1743 case 8: return MVT::v8i1;
1744 case 16: return MVT::v16i1;
1746 if (Subtarget->hasBWI())
1747 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1749 case 32: return MVT::v32i1;
1750 case 64: return MVT::v64i1;
1754 if (VT.is256BitVector() || VT.is128BitVector()) {
1755 if (Subtarget->hasVLX())
1756 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1757 EltVT == MVT::f32 || EltVT == MVT::f64)
1759 case 2: return MVT::v2i1;
1760 case 4: return MVT::v4i1;
1761 case 8: return MVT::v8i1;
1763 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1764 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1766 case 8: return MVT::v8i1;
1767 case 16: return MVT::v16i1;
1768 case 32: return MVT::v32i1;
1772 return VT.changeVectorElementTypeToInteger();
1775 /// Helper for getByValTypeAlignment to determine
1776 /// the desired ByVal argument alignment.
1777 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1780 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1781 if (VTy->getBitWidth() == 128)
1783 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1784 unsigned EltAlign = 0;
1785 getMaxByValAlign(ATy->getElementType(), EltAlign);
1786 if (EltAlign > MaxAlign)
1787 MaxAlign = EltAlign;
1788 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1789 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1790 unsigned EltAlign = 0;
1791 getMaxByValAlign(STy->getElementType(i), EltAlign);
1792 if (EltAlign > MaxAlign)
1793 MaxAlign = EltAlign;
1800 /// Return the desired alignment for ByVal aggregate
1801 /// function arguments in the caller parameter area. For X86, aggregates
1802 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1803 /// are at 4-byte boundaries.
1804 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1805 if (Subtarget->is64Bit()) {
1806 // Max of 8 and alignment of type.
1807 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1814 if (Subtarget->hasSSE1())
1815 getMaxByValAlign(Ty, Align);
1819 /// Returns the target specific optimal type for load
1820 /// and store operations as a result of memset, memcpy, and memmove
1821 /// lowering. If DstAlign is zero that means it's safe to destination
1822 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1823 /// means there isn't a need to check it against alignment requirement,
1824 /// probably because the source does not need to be loaded. If 'IsMemset' is
1825 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1826 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1827 /// source is constant so it does not need to be loaded.
1828 /// It returns EVT::Other if the type should be determined using generic
1829 /// target-independent logic.
1831 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1832 unsigned DstAlign, unsigned SrcAlign,
1833 bool IsMemset, bool ZeroMemset,
1835 MachineFunction &MF) const {
1836 const Function *F = MF.getFunction();
1837 if ((!IsMemset || ZeroMemset) &&
1838 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1840 (Subtarget->isUnalignedMemAccessFast() ||
1841 ((DstAlign == 0 || DstAlign >= 16) &&
1842 (SrcAlign == 0 || SrcAlign >= 16)))) {
1844 if (Subtarget->hasInt256())
1846 if (Subtarget->hasFp256())
1849 if (Subtarget->hasSSE2())
1851 if (Subtarget->hasSSE1())
1853 } else if (!MemcpyStrSrc && Size >= 8 &&
1854 !Subtarget->is64Bit() &&
1855 Subtarget->hasSSE2()) {
1856 // Do not use f64 to lower memcpy if source is string constant. It's
1857 // better to use i32 to avoid the loads.
1861 if (Subtarget->is64Bit() && Size >= 8)
1866 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1868 return X86ScalarSSEf32;
1869 else if (VT == MVT::f64)
1870 return X86ScalarSSEf64;
1875 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1880 *Fast = Subtarget->isUnalignedMemAccessFast();
1884 /// Return the entry encoding for a jump table in the
1885 /// current function. The returned value is a member of the
1886 /// MachineJumpTableInfo::JTEntryKind enum.
1887 unsigned X86TargetLowering::getJumpTableEncoding() const {
1888 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1890 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1891 Subtarget->isPICStyleGOT())
1892 return MachineJumpTableInfo::EK_Custom32;
1894 // Otherwise, use the normal jump table encoding heuristics.
1895 return TargetLowering::getJumpTableEncoding();
1899 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1900 const MachineBasicBlock *MBB,
1901 unsigned uid,MCContext &Ctx) const{
1902 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1903 Subtarget->isPICStyleGOT());
1904 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1906 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1907 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1910 /// Returns relocation base for the given PIC jumptable.
1911 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1912 SelectionDAG &DAG) const {
1913 if (!Subtarget->is64Bit())
1914 // This doesn't have SDLoc associated with it, but is not really the
1915 // same as a Register.
1916 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1920 /// This returns the relocation base for the given PIC jumptable,
1921 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1922 const MCExpr *X86TargetLowering::
1923 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1924 MCContext &Ctx) const {
1925 // X86-64 uses RIP relative addressing based on the jump table label.
1926 if (Subtarget->isPICStyleRIPRel())
1927 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1929 // Otherwise, the reference is relative to the PIC base.
1930 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1933 std::pair<const TargetRegisterClass *, uint8_t>
1934 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1936 const TargetRegisterClass *RRC = nullptr;
1938 switch (VT.SimpleTy) {
1940 return TargetLowering::findRepresentativeClass(TRI, VT);
1941 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1942 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1945 RRC = &X86::VR64RegClass;
1947 case MVT::f32: case MVT::f64:
1948 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1949 case MVT::v4f32: case MVT::v2f64:
1950 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1952 RRC = &X86::VR128RegClass;
1955 return std::make_pair(RRC, Cost);
1958 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1959 unsigned &Offset) const {
1960 if (!Subtarget->isTargetLinux())
1963 if (Subtarget->is64Bit()) {
1964 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1966 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1978 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1979 unsigned DestAS) const {
1980 assert(SrcAS != DestAS && "Expected different address spaces!");
1982 return SrcAS < 256 && DestAS < 256;
1985 //===----------------------------------------------------------------------===//
1986 // Return Value Calling Convention Implementation
1987 //===----------------------------------------------------------------------===//
1989 #include "X86GenCallingConv.inc"
1992 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1993 MachineFunction &MF, bool isVarArg,
1994 const SmallVectorImpl<ISD::OutputArg> &Outs,
1995 LLVMContext &Context) const {
1996 SmallVector<CCValAssign, 16> RVLocs;
1997 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1998 return CCInfo.CheckReturn(Outs, RetCC_X86);
2001 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2002 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2007 X86TargetLowering::LowerReturn(SDValue Chain,
2008 CallingConv::ID CallConv, bool isVarArg,
2009 const SmallVectorImpl<ISD::OutputArg> &Outs,
2010 const SmallVectorImpl<SDValue> &OutVals,
2011 SDLoc dl, SelectionDAG &DAG) const {
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2015 SmallVector<CCValAssign, 16> RVLocs;
2016 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2017 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2020 SmallVector<SDValue, 6> RetOps;
2021 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2022 // Operand #1 = Bytes To Pop
2023 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2026 // Copy the result values into the output registers.
2027 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2028 CCValAssign &VA = RVLocs[i];
2029 assert(VA.isRegLoc() && "Can only return in registers!");
2030 SDValue ValToCopy = OutVals[i];
2031 EVT ValVT = ValToCopy.getValueType();
2033 // Promote values to the appropriate types.
2034 if (VA.getLocInfo() == CCValAssign::SExt)
2035 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2036 else if (VA.getLocInfo() == CCValAssign::ZExt)
2037 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2038 else if (VA.getLocInfo() == CCValAssign::AExt)
2039 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2040 else if (VA.getLocInfo() == CCValAssign::BCvt)
2041 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2043 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2044 "Unexpected FP-extend for return value.");
2046 // If this is x86-64, and we disabled SSE, we can't return FP values,
2047 // or SSE or MMX vectors.
2048 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2049 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2050 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2051 report_fatal_error("SSE register return with SSE disabled");
2053 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2054 // llvm-gcc has never done it right and no one has noticed, so this
2055 // should be OK for now.
2056 if (ValVT == MVT::f64 &&
2057 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2058 report_fatal_error("SSE2 register return with SSE2 disabled");
2060 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2061 // the RET instruction and handled by the FP Stackifier.
2062 if (VA.getLocReg() == X86::FP0 ||
2063 VA.getLocReg() == X86::FP1) {
2064 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2065 // change the value to the FP stack register class.
2066 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2067 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2068 RetOps.push_back(ValToCopy);
2069 // Don't emit a copytoreg.
2073 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2074 // which is returned in RAX / RDX.
2075 if (Subtarget->is64Bit()) {
2076 if (ValVT == MVT::x86mmx) {
2077 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2078 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2079 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2081 // If we don't have SSE2 available, convert to v4f32 so the generated
2082 // register is legal.
2083 if (!Subtarget->hasSSE2())
2084 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2089 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2090 Flag = Chain.getValue(1);
2091 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2094 // The x86-64 ABIs require that for returning structs by value we copy
2095 // the sret argument into %rax/%eax (depending on ABI) for the return.
2096 // Win32 requires us to put the sret argument to %eax as well.
2097 // We saved the argument into a virtual register in the entry block,
2098 // so now we copy the value out and into %rax/%eax.
2100 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2101 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2102 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2103 // either case FuncInfo->setSRetReturnReg() will have been called.
2104 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2105 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
2106 "No need for an sret register");
2107 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2110 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2111 X86::RAX : X86::EAX;
2112 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2113 Flag = Chain.getValue(1);
2115 // RAX/EAX now acts like a return value.
2116 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2119 RetOps[0] = Chain; // Update chain.
2121 // Add the flag if we have it.
2123 RetOps.push_back(Flag);
2125 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2128 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2129 if (N->getNumValues() != 1)
2131 if (!N->hasNUsesOfValue(1, 0))
2134 SDValue TCChain = Chain;
2135 SDNode *Copy = *N->use_begin();
2136 if (Copy->getOpcode() == ISD::CopyToReg) {
2137 // If the copy has a glue operand, we conservatively assume it isn't safe to
2138 // perform a tail call.
2139 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2141 TCChain = Copy->getOperand(0);
2142 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2145 bool HasRet = false;
2146 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2148 if (UI->getOpcode() != X86ISD::RET_FLAG)
2150 // If we are returning more than one value, we can definitely
2151 // not make a tail call see PR19530
2152 if (UI->getNumOperands() > 4)
2154 if (UI->getNumOperands() == 4 &&
2155 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2168 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2169 ISD::NodeType ExtendKind) const {
2171 // TODO: Is this also valid on 32-bit?
2172 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2173 ReturnMVT = MVT::i8;
2175 ReturnMVT = MVT::i32;
2177 EVT MinVT = getRegisterType(Context, ReturnMVT);
2178 return VT.bitsLT(MinVT) ? MinVT : VT;
2181 /// Lower the result values of a call into the
2182 /// appropriate copies out of appropriate physical registers.
2185 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2186 CallingConv::ID CallConv, bool isVarArg,
2187 const SmallVectorImpl<ISD::InputArg> &Ins,
2188 SDLoc dl, SelectionDAG &DAG,
2189 SmallVectorImpl<SDValue> &InVals) const {
2191 // Assign locations to each value returned by this call.
2192 SmallVector<CCValAssign, 16> RVLocs;
2193 bool Is64Bit = Subtarget->is64Bit();
2194 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2196 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2198 // Copy all of the result registers out of their specified physreg.
2199 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2200 CCValAssign &VA = RVLocs[i];
2201 EVT CopyVT = VA.getValVT();
2203 // If this is x86-64, and we disabled SSE, we can't return FP values
2204 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2205 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2206 report_fatal_error("SSE register return with SSE disabled");
2209 // If we prefer to use the value in xmm registers, copy it out as f80 and
2210 // use a truncate to move it from fp stack reg to xmm reg.
2211 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2212 isScalarFPTypeInSSEReg(VA.getValVT()))
2215 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2216 CopyVT, InFlag).getValue(1);
2217 SDValue Val = Chain.getValue(0);
2219 if (CopyVT != VA.getValVT())
2220 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2221 // This truncation won't change the value.
2222 DAG.getIntPtrConstant(1));
2224 InFlag = Chain.getValue(2);
2225 InVals.push_back(Val);
2231 //===----------------------------------------------------------------------===//
2232 // C & StdCall & Fast Calling Convention implementation
2233 //===----------------------------------------------------------------------===//
2234 // StdCall calling convention seems to be standard for many Windows' API
2235 // routines and around. It differs from C calling convention just a little:
2236 // callee should clean up the stack, not caller. Symbols should be also
2237 // decorated in some fancy way :) It doesn't support any vector arguments.
2238 // For info on fast calling convention see Fast Calling Convention (tail call)
2239 // implementation LowerX86_32FastCCCallTo.
2241 /// CallIsStructReturn - Determines whether a call uses struct return
2243 enum StructReturnType {
2248 static StructReturnType
2249 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2251 return NotStructReturn;
2253 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2254 if (!Flags.isSRet())
2255 return NotStructReturn;
2256 if (Flags.isInReg())
2257 return RegStructReturn;
2258 return StackStructReturn;
2261 /// Determines whether a function uses struct return semantics.
2262 static StructReturnType
2263 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2265 return NotStructReturn;
2267 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2268 if (!Flags.isSRet())
2269 return NotStructReturn;
2270 if (Flags.isInReg())
2271 return RegStructReturn;
2272 return StackStructReturn;
2275 /// Make a copy of an aggregate at address specified by "Src" to address
2276 /// "Dst" with size and alignment information specified by the specific
2277 /// parameter attribute. The copy will be passed as a byval function parameter.
2279 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2280 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2282 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2284 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2285 /*isVolatile*/false, /*AlwaysInline=*/true,
2286 MachinePointerInfo(), MachinePointerInfo());
2289 /// Return true if the calling convention is one that
2290 /// supports tail call optimization.
2291 static bool IsTailCallConvention(CallingConv::ID CC) {
2292 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2293 CC == CallingConv::HiPE);
2296 /// \brief Return true if the calling convention is a C calling convention.
2297 static bool IsCCallConvention(CallingConv::ID CC) {
2298 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2299 CC == CallingConv::X86_64_SysV);
2302 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2303 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2307 CallingConv::ID CalleeCC = CS.getCallingConv();
2308 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2314 /// Return true if the function is being made into
2315 /// a tailcall target by changing its ABI.
2316 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2317 bool GuaranteedTailCallOpt) {
2318 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2322 X86TargetLowering::LowerMemArgument(SDValue Chain,
2323 CallingConv::ID CallConv,
2324 const SmallVectorImpl<ISD::InputArg> &Ins,
2325 SDLoc dl, SelectionDAG &DAG,
2326 const CCValAssign &VA,
2327 MachineFrameInfo *MFI,
2329 // Create the nodes corresponding to a load from this parameter slot.
2330 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2331 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2332 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2333 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2336 // If value is passed by pointer we have address passed instead of the value
2338 if (VA.getLocInfo() == CCValAssign::Indirect)
2339 ValVT = VA.getLocVT();
2341 ValVT = VA.getValVT();
2343 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2344 // changed with more analysis.
2345 // In case of tail call optimization mark all arguments mutable. Since they
2346 // could be overwritten by lowering of arguments in case of a tail call.
2347 if (Flags.isByVal()) {
2348 unsigned Bytes = Flags.getByValSize();
2349 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2350 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2351 return DAG.getFrameIndex(FI, getPointerTy());
2353 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2354 VA.getLocMemOffset(), isImmutable);
2355 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2356 return DAG.getLoad(ValVT, dl, Chain, FIN,
2357 MachinePointerInfo::getFixedStack(FI),
2358 false, false, false, 0);
2362 // FIXME: Get this from tablegen.
2363 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2364 const X86Subtarget *Subtarget) {
2365 assert(Subtarget->is64Bit());
2367 if (Subtarget->isCallingConvWin64(CallConv)) {
2368 static const MCPhysReg GPR64ArgRegsWin64[] = {
2369 X86::RCX, X86::RDX, X86::R8, X86::R9
2371 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2374 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2375 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2377 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2380 // FIXME: Get this from tablegen.
2381 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2382 CallingConv::ID CallConv,
2383 const X86Subtarget *Subtarget) {
2384 assert(Subtarget->is64Bit());
2385 if (Subtarget->isCallingConvWin64(CallConv)) {
2386 // The XMM registers which might contain var arg parameters are shadowed
2387 // in their paired GPR. So we only need to save the GPR to their home
2389 // TODO: __vectorcall will change this.
2393 const Function *Fn = MF.getFunction();
2394 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2395 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2396 "SSE register cannot be used when SSE is disabled!");
2397 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2398 !Subtarget->hasSSE1())
2399 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2403 static const MCPhysReg XMMArgRegs64Bit[] = {
2404 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2405 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2407 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2411 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2412 CallingConv::ID CallConv,
2414 const SmallVectorImpl<ISD::InputArg> &Ins,
2417 SmallVectorImpl<SDValue> &InVals)
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2422 const Function* Fn = MF.getFunction();
2423 if (Fn->hasExternalLinkage() &&
2424 Subtarget->isTargetCygMing() &&
2425 Fn->getName() == "main")
2426 FuncInfo->setForceFramePointer(true);
2428 MachineFrameInfo *MFI = MF.getFrameInfo();
2429 bool Is64Bit = Subtarget->is64Bit();
2430 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2432 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2433 "Var args not supported with calling convention fastcc, ghc or hipe");
2435 // Assign locations to all of the incoming arguments.
2436 SmallVector<CCValAssign, 16> ArgLocs;
2437 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2439 // Allocate shadow area for Win64
2441 CCInfo.AllocateStack(32, 8);
2443 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2445 unsigned LastVal = ~0U;
2447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2448 CCValAssign &VA = ArgLocs[i];
2449 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2451 assert(VA.getValNo() != LastVal &&
2452 "Don't support value assigned to multiple locs yet");
2454 LastVal = VA.getValNo();
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2458 const TargetRegisterClass *RC;
2459 if (RegVT == MVT::i32)
2460 RC = &X86::GR32RegClass;
2461 else if (Is64Bit && RegVT == MVT::i64)
2462 RC = &X86::GR64RegClass;
2463 else if (RegVT == MVT::f32)
2464 RC = &X86::FR32RegClass;
2465 else if (RegVT == MVT::f64)
2466 RC = &X86::FR64RegClass;
2467 else if (RegVT.is512BitVector())
2468 RC = &X86::VR512RegClass;
2469 else if (RegVT.is256BitVector())
2470 RC = &X86::VR256RegClass;
2471 else if (RegVT.is128BitVector())
2472 RC = &X86::VR128RegClass;
2473 else if (RegVT == MVT::x86mmx)
2474 RC = &X86::VR64RegClass;
2475 else if (RegVT == MVT::i1)
2476 RC = &X86::VK1RegClass;
2477 else if (RegVT == MVT::v8i1)
2478 RC = &X86::VK8RegClass;
2479 else if (RegVT == MVT::v16i1)
2480 RC = &X86::VK16RegClass;
2481 else if (RegVT == MVT::v32i1)
2482 RC = &X86::VK32RegClass;
2483 else if (RegVT == MVT::v64i1)
2484 RC = &X86::VK64RegClass;
2486 llvm_unreachable("Unknown argument type!");
2488 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2489 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2492 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2494 if (VA.getLocInfo() == CCValAssign::SExt)
2495 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2496 DAG.getValueType(VA.getValVT()));
2497 else if (VA.getLocInfo() == CCValAssign::ZExt)
2498 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2499 DAG.getValueType(VA.getValVT()));
2500 else if (VA.getLocInfo() == CCValAssign::BCvt)
2501 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2503 if (VA.isExtInLoc()) {
2504 // Handle MMX values passed in XMM regs.
2505 if (RegVT.isVector())
2506 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 assert(VA.isMemLoc());
2512 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2515 // If value is passed via pointer - do a load.
2516 if (VA.getLocInfo() == CCValAssign::Indirect)
2517 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2518 MachinePointerInfo(), false, false, false, 0);
2520 InVals.push_back(ArgValue);
2523 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2524 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2525 // The x86-64 ABIs require that for returning structs by value we copy
2526 // the sret argument into %rax/%eax (depending on ABI) for the return.
2527 // Win32 requires us to put the sret argument to %eax as well.
2528 // Save the argument into a virtual register so that we can access it
2529 // from the return points.
2530 if (Ins[i].Flags.isSRet()) {
2531 unsigned Reg = FuncInfo->getSRetReturnReg();
2533 MVT PtrTy = getPointerTy();
2534 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2535 FuncInfo->setSRetReturnReg(Reg);
2537 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2544 unsigned StackSize = CCInfo.getNextStackOffset();
2545 // Align stack specially for tail calls.
2546 if (FuncIsMadeTailCallSafe(CallConv,
2547 MF.getTarget().Options.GuaranteedTailCallOpt))
2548 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2550 // If the function takes variable number of arguments, make a frame index for
2551 // the start of the first vararg value... for expansion of llvm.va_start. We
2552 // can skip this if there are no va_start calls.
2553 if (MFI->hasVAStart() &&
2554 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2555 CallConv != CallingConv::X86_ThisCall))) {
2556 FuncInfo->setVarArgsFrameIndex(
2557 MFI->CreateFixedObject(1, StackSize, true));
2560 // Figure out if XMM registers are in use.
2561 assert(!(MF.getTarget().Options.UseSoftFloat &&
2562 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2563 "SSE register cannot be used when SSE is disabled!");
2565 // 64-bit calling conventions support varargs and register parameters, so we
2566 // have to do extra work to spill them in the prologue.
2567 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2568 // Find the first unallocated argument registers.
2569 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2570 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2571 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2572 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2573 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2574 "SSE register cannot be used when SSE is disabled!");
2576 // Gather all the live in physical registers.
2577 SmallVector<SDValue, 6> LiveGPRs;
2578 SmallVector<SDValue, 8> LiveXMMRegs;
2580 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2581 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2583 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2585 if (!ArgXMMs.empty()) {
2586 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2587 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2588 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2589 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2590 LiveXMMRegs.push_back(
2591 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2596 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2597 // Get to the caller-allocated home save location. Add 8 to account
2598 // for the return address.
2599 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2600 FuncInfo->setRegSaveFrameIndex(
2601 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2602 // Fixup to set vararg frame on shadow area (4 x i64).
2604 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2606 // For X86-64, if there are vararg parameters that are passed via
2607 // registers, then we must store them to their spots on the stack so
2608 // they may be loaded by deferencing the result of va_next.
2609 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2610 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2611 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2612 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2615 // Store the integer parameter registers.
2616 SmallVector<SDValue, 8> MemOps;
2617 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2619 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2620 for (SDValue Val : LiveGPRs) {
2621 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2622 DAG.getIntPtrConstant(Offset));
2624 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2625 MachinePointerInfo::getFixedStack(
2626 FuncInfo->getRegSaveFrameIndex(), Offset),
2628 MemOps.push_back(Store);
2632 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2633 // Now store the XMM (fp + vector) parameter registers.
2634 SmallVector<SDValue, 12> SaveXMMOps;
2635 SaveXMMOps.push_back(Chain);
2636 SaveXMMOps.push_back(ALVal);
2637 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2638 FuncInfo->getRegSaveFrameIndex()));
2639 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2640 FuncInfo->getVarArgsFPOffset()));
2641 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2643 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2644 MVT::Other, SaveXMMOps));
2647 if (!MemOps.empty())
2648 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2651 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2652 // Find the largest legal vector type.
2653 MVT VecVT = MVT::Other;
2654 // FIXME: Only some x86_32 calling conventions support AVX512.
2655 if (Subtarget->hasAVX512() &&
2656 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2657 CallConv == CallingConv::Intel_OCL_BI)))
2658 VecVT = MVT::v16f32;
2659 else if (Subtarget->hasAVX())
2661 else if (Subtarget->hasSSE2())
2664 // We forward some GPRs and some vector types.
2665 SmallVector<MVT, 2> RegParmTypes;
2666 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2667 RegParmTypes.push_back(IntVT);
2668 if (VecVT != MVT::Other)
2669 RegParmTypes.push_back(VecVT);
2671 // Compute the set of forwarded registers. The rest are scratch.
2672 SmallVectorImpl<ForwardedRegister> &Forwards =
2673 FuncInfo->getForwardedMustTailRegParms();
2674 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2676 // Conservatively forward AL on x86_64, since it might be used for varargs.
2677 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2678 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2679 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2682 // Copy all forwards from physical to virtual registers.
2683 for (ForwardedRegister &F : Forwards) {
2684 // FIXME: Can we use a less constrained schedule?
2685 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2686 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2687 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2691 // Some CCs need callee pop.
2692 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2693 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2694 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2696 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2697 // If this is an sret function, the return should pop the hidden pointer.
2698 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2699 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2700 argsAreStructReturn(Ins) == StackStructReturn)
2701 FuncInfo->setBytesToPopOnReturn(4);
2705 // RegSaveFrameIndex is X86-64 only.
2706 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2707 if (CallConv == CallingConv::X86_FastCall ||
2708 CallConv == CallingConv::X86_ThisCall)
2709 // fastcc functions can't have varargs.
2710 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2713 FuncInfo->setArgumentStackSize(StackSize);
2719 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2720 SDValue StackPtr, SDValue Arg,
2721 SDLoc dl, SelectionDAG &DAG,
2722 const CCValAssign &VA,
2723 ISD::ArgFlagsTy Flags) const {
2724 unsigned LocMemOffset = VA.getLocMemOffset();
2725 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2726 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2727 if (Flags.isByVal())
2728 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2730 return DAG.getStore(Chain, dl, Arg, PtrOff,
2731 MachinePointerInfo::getStack(LocMemOffset),
2735 /// Emit a load of return address if tail call
2736 /// optimization is performed and it is required.
2738 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2739 SDValue &OutRetAddr, SDValue Chain,
2740 bool IsTailCall, bool Is64Bit,
2741 int FPDiff, SDLoc dl) const {
2742 // Adjust the Return address stack slot.
2743 EVT VT = getPointerTy();
2744 OutRetAddr = getReturnAddressFrameIndex(DAG);
2746 // Load the "old" Return address.
2747 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2748 false, false, false, 0);
2749 return SDValue(OutRetAddr.getNode(), 1);
2752 /// Emit a store of the return address if tail call
2753 /// optimization is performed and it is required (FPDiff!=0).
2754 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2755 SDValue Chain, SDValue RetAddrFrIdx,
2756 EVT PtrVT, unsigned SlotSize,
2757 int FPDiff, SDLoc dl) {
2758 // Store the return address to the appropriate stack slot.
2759 if (!FPDiff) return Chain;
2760 // Calculate the new stack slot for the return address.
2761 int NewReturnAddrFI =
2762 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2764 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2765 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2766 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2772 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2773 SmallVectorImpl<SDValue> &InVals) const {
2774 SelectionDAG &DAG = CLI.DAG;
2776 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2777 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2778 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2779 SDValue Chain = CLI.Chain;
2780 SDValue Callee = CLI.Callee;
2781 CallingConv::ID CallConv = CLI.CallConv;
2782 bool &isTailCall = CLI.IsTailCall;
2783 bool isVarArg = CLI.IsVarArg;
2785 MachineFunction &MF = DAG.getMachineFunction();
2786 bool Is64Bit = Subtarget->is64Bit();
2787 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2788 StructReturnType SR = callIsStructReturn(Outs);
2789 bool IsSibcall = false;
2790 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2792 if (MF.getTarget().Options.DisableTailCalls)
2795 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2797 // Force this to be a tail call. The verifier rules are enough to ensure
2798 // that we can lower this successfully without moving the return address
2801 } else if (isTailCall) {
2802 // Check if it's really possible to do a tail call.
2803 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2804 isVarArg, SR != NotStructReturn,
2805 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2806 Outs, OutVals, Ins, DAG);
2808 // Sibcalls are automatically detected tailcalls which do not require
2810 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2817 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2818 "Var args not supported with calling convention fastcc, ghc or hipe");
2820 // Analyze operands of the call, assigning locations to each operand.
2821 SmallVector<CCValAssign, 16> ArgLocs;
2822 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2824 // Allocate shadow area for Win64
2826 CCInfo.AllocateStack(32, 8);
2828 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2830 // Get a count of how many bytes are to be pushed on the stack.
2831 unsigned NumBytes = CCInfo.getNextStackOffset();
2833 // This is a sibcall. The memory operands are available in caller's
2834 // own caller's stack.
2836 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2837 IsTailCallConvention(CallConv))
2838 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2841 if (isTailCall && !IsSibcall && !IsMustTail) {
2842 // Lower arguments at fp - stackoffset + fpdiff.
2843 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2845 FPDiff = NumBytesCallerPushed - NumBytes;
2847 // Set the delta of movement of the returnaddr stackslot.
2848 // But only set if delta is greater than previous delta.
2849 if (FPDiff < X86Info->getTCReturnAddrDelta())
2850 X86Info->setTCReturnAddrDelta(FPDiff);
2853 unsigned NumBytesToPush = NumBytes;
2854 unsigned NumBytesToPop = NumBytes;
2856 // If we have an inalloca argument, all stack space has already been allocated
2857 // for us and be right at the top of the stack. We don't support multiple
2858 // arguments passed in memory when using inalloca.
2859 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2861 if (!ArgLocs.back().isMemLoc())
2862 report_fatal_error("cannot use inalloca attribute on a register "
2864 if (ArgLocs.back().getLocMemOffset() != 0)
2865 report_fatal_error("any parameter with the inalloca attribute must be "
2866 "the only memory argument");
2870 Chain = DAG.getCALLSEQ_START(
2871 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2873 SDValue RetAddrFrIdx;
2874 // Load return address for tail calls.
2875 if (isTailCall && FPDiff)
2876 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2877 Is64Bit, FPDiff, dl);
2879 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2880 SmallVector<SDValue, 8> MemOpChains;
2883 // Walk the register/memloc assignments, inserting copies/loads. In the case
2884 // of tail call optimization arguments are handle later.
2885 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2886 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2887 // Skip inalloca arguments, they have already been written.
2888 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2889 if (Flags.isInAlloca())
2892 CCValAssign &VA = ArgLocs[i];
2893 EVT RegVT = VA.getLocVT();
2894 SDValue Arg = OutVals[i];
2895 bool isByVal = Flags.isByVal();
2897 // Promote the value if needed.
2898 switch (VA.getLocInfo()) {
2899 default: llvm_unreachable("Unknown loc info!");
2900 case CCValAssign::Full: break;
2901 case CCValAssign::SExt:
2902 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2904 case CCValAssign::ZExt:
2905 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2907 case CCValAssign::AExt:
2908 if (RegVT.is128BitVector()) {
2909 // Special case: passing MMX values in XMM registers.
2910 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2911 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2912 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2914 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2916 case CCValAssign::BCvt:
2917 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2919 case CCValAssign::Indirect: {
2920 // Store the argument.
2921 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2922 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2923 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2924 MachinePointerInfo::getFixedStack(FI),
2931 if (VA.isRegLoc()) {
2932 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2933 if (isVarArg && IsWin64) {
2934 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2935 // shadow reg if callee is a varargs function.
2936 unsigned ShadowReg = 0;
2937 switch (VA.getLocReg()) {
2938 case X86::XMM0: ShadowReg = X86::RCX; break;
2939 case X86::XMM1: ShadowReg = X86::RDX; break;
2940 case X86::XMM2: ShadowReg = X86::R8; break;
2941 case X86::XMM3: ShadowReg = X86::R9; break;
2944 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2946 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2947 assert(VA.isMemLoc());
2948 if (!StackPtr.getNode())
2949 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2951 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2952 dl, DAG, VA, Flags));
2956 if (!MemOpChains.empty())
2957 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2959 if (Subtarget->isPICStyleGOT()) {
2960 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2964 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2966 // If we are tail calling and generating PIC/GOT style code load the
2967 // address of the callee into ECX. The value in ecx is used as target of
2968 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2969 // for tail calls on PIC/GOT architectures. Normally we would just put the
2970 // address of GOT into ebx and then call target@PLT. But for tail calls
2971 // ebx would be restored (since ebx is callee saved) before jumping to the
2974 // Note: The actual moving to ECX is done further down.
2975 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2976 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2977 !G->getGlobal()->hasProtectedVisibility())
2978 Callee = LowerGlobalAddress(Callee, DAG);
2979 else if (isa<ExternalSymbolSDNode>(Callee))
2980 Callee = LowerExternalSymbol(Callee, DAG);
2984 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2985 // From AMD64 ABI document:
2986 // For calls that may call functions that use varargs or stdargs
2987 // (prototype-less calls or calls to functions containing ellipsis (...) in
2988 // the declaration) %al is used as hidden argument to specify the number
2989 // of SSE registers used. The contents of %al do not need to match exactly
2990 // the number of registers, but must be an ubound on the number of SSE
2991 // registers used and is in the range 0 - 8 inclusive.
2993 // Count the number of XMM registers allocated.
2994 static const MCPhysReg XMMArgRegs[] = {
2995 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2996 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2998 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2999 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3000 && "SSE registers cannot be used when SSE is disabled");
3002 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3003 DAG.getConstant(NumXMMRegs, MVT::i8)));
3006 if (isVarArg && IsMustTail) {
3007 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3008 for (const auto &F : Forwards) {
3009 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3010 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3014 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3015 // don't need this because the eligibility check rejects calls that require
3016 // shuffling arguments passed in memory.
3017 if (!IsSibcall && isTailCall) {
3018 // Force all the incoming stack arguments to be loaded from the stack
3019 // before any new outgoing arguments are stored to the stack, because the
3020 // outgoing stack slots may alias the incoming argument stack slots, and
3021 // the alias isn't otherwise explicit. This is slightly more conservative
3022 // than necessary, because it means that each store effectively depends
3023 // on every argument instead of just those arguments it would clobber.
3024 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3026 SmallVector<SDValue, 8> MemOpChains2;
3029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3030 CCValAssign &VA = ArgLocs[i];
3033 assert(VA.isMemLoc());
3034 SDValue Arg = OutVals[i];
3035 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3036 // Skip inalloca arguments. They don't require any work.
3037 if (Flags.isInAlloca())
3039 // Create frame index.
3040 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3041 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3042 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3043 FIN = DAG.getFrameIndex(FI, getPointerTy());
3045 if (Flags.isByVal()) {
3046 // Copy relative to framepointer.
3047 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3048 if (!StackPtr.getNode())
3049 StackPtr = DAG.getCopyFromReg(Chain, dl,
3050 RegInfo->getStackRegister(),
3052 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3054 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3058 // Store relative to framepointer.
3059 MemOpChains2.push_back(
3060 DAG.getStore(ArgChain, dl, Arg, FIN,
3061 MachinePointerInfo::getFixedStack(FI),
3066 if (!MemOpChains2.empty())
3067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3069 // Store the return address to the appropriate stack slot.
3070 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3071 getPointerTy(), RegInfo->getSlotSize(),
3075 // Build a sequence of copy-to-reg nodes chained together with token chain
3076 // and flag operands which copy the outgoing args into registers.
3078 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3079 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3080 RegsToPass[i].second, InFlag);
3081 InFlag = Chain.getValue(1);
3084 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3085 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3086 // In the 64-bit large code model, we have to make all calls
3087 // through a register, since the call instruction's 32-bit
3088 // pc-relative offset may not be large enough to hold the whole
3090 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3091 // If the callee is a GlobalAddress node (quite common, every direct call
3092 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3094 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3096 // We should use extra load for direct calls to dllimported functions in
3098 const GlobalValue *GV = G->getGlobal();
3099 if (!GV->hasDLLImportStorageClass()) {
3100 unsigned char OpFlags = 0;
3101 bool ExtraLoad = false;
3102 unsigned WrapperKind = ISD::DELETED_NODE;
3104 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3105 // external symbols most go through the PLT in PIC mode. If the symbol
3106 // has hidden or protected visibility, or if it is static or local, then
3107 // we don't need to use the PLT - we can directly call it.
3108 if (Subtarget->isTargetELF() &&
3109 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3110 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3120 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3121 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3122 // If the function is marked as non-lazy, generate an indirect call
3123 // which loads from the GOT directly. This avoids runtime overhead
3124 // at the cost of eager binding (and one extra byte of encoding).
3125 OpFlags = X86II::MO_GOTPCREL;
3126 WrapperKind = X86ISD::WrapperRIP;
3130 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3131 G->getOffset(), OpFlags);
3133 // Add a wrapper if needed.
3134 if (WrapperKind != ISD::DELETED_NODE)
3135 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3136 // Add extra indirection if needed.
3138 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3139 MachinePointerInfo::getGOT(),
3140 false, false, false, 0);
3142 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3143 unsigned char OpFlags = 0;
3145 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3146 // external symbols should go through the PLT.
3147 if (Subtarget->isTargetELF() &&
3148 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3149 OpFlags = X86II::MO_PLT;
3150 } else if (Subtarget->isPICStyleStubAny() &&
3151 (!Subtarget->getTargetTriple().isMacOSX() ||
3152 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3153 // PC-relative references to external symbols should go through $stub,
3154 // unless we're building with the leopard linker or later, which
3155 // automatically synthesizes these stubs.
3156 OpFlags = X86II::MO_DARWIN_STUB;
3159 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3161 } else if (Subtarget->isTarget64BitILP32() &&
3162 Callee->getValueType(0) == MVT::i32) {
3163 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3164 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3167 // Returns a chain & a flag for retval copy to use.
3168 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3169 SmallVector<SDValue, 8> Ops;
3171 if (!IsSibcall && isTailCall) {
3172 Chain = DAG.getCALLSEQ_END(Chain,
3173 DAG.getIntPtrConstant(NumBytesToPop, true),
3174 DAG.getIntPtrConstant(0, true), InFlag, dl);
3175 InFlag = Chain.getValue(1);
3178 Ops.push_back(Chain);
3179 Ops.push_back(Callee);
3182 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3184 // Add argument registers to the end of the list so that they are known live
3186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3187 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3188 RegsToPass[i].second.getValueType()));
3190 // Add a register mask operand representing the call-preserved registers.
3191 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3192 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3193 assert(Mask && "Missing call preserved mask for calling convention");
3194 Ops.push_back(DAG.getRegisterMask(Mask));
3196 if (InFlag.getNode())
3197 Ops.push_back(InFlag);
3201 //// If this is the first return lowered for this function, add the regs
3202 //// to the liveout set for the function.
3203 // This isn't right, although it's probably harmless on x86; liveouts
3204 // should be computed from returns not tail calls. Consider a void
3205 // function making a tail call to a function returning int.
3206 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3209 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3210 InFlag = Chain.getValue(1);
3212 // Create the CALLSEQ_END node.
3213 unsigned NumBytesForCalleeToPop;
3214 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3215 DAG.getTarget().Options.GuaranteedTailCallOpt))
3216 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3217 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3218 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3219 SR == StackStructReturn)
3220 // If this is a call to a struct-return function, the callee
3221 // pops the hidden struct pointer, so we have to push it back.
3222 // This is common for Darwin/X86, Linux & Mingw32 targets.
3223 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3224 NumBytesForCalleeToPop = 4;
3226 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3228 // Returns a flag for retval copy to use.
3230 Chain = DAG.getCALLSEQ_END(Chain,
3231 DAG.getIntPtrConstant(NumBytesToPop, true),
3232 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3235 InFlag = Chain.getValue(1);
3238 // Handle result values, copying them out of physregs into vregs that we
3240 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3241 Ins, dl, DAG, InVals);
3244 //===----------------------------------------------------------------------===//
3245 // Fast Calling Convention (tail call) implementation
3246 //===----------------------------------------------------------------------===//
3248 // Like std call, callee cleans arguments, convention except that ECX is
3249 // reserved for storing the tail called function address. Only 2 registers are
3250 // free for argument passing (inreg). Tail call optimization is performed
3252 // * tailcallopt is enabled
3253 // * caller/callee are fastcc
3254 // On X86_64 architecture with GOT-style position independent code only local
3255 // (within module) calls are supported at the moment.
3256 // To keep the stack aligned according to platform abi the function
3257 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3258 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3259 // If a tail called function callee has more arguments than the caller the
3260 // caller needs to make sure that there is room to move the RETADDR to. This is
3261 // achieved by reserving an area the size of the argument delta right after the
3262 // original RETADDR, but before the saved framepointer or the spilled registers
3263 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3275 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3276 /// for a 16 byte align requirement.
3278 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3279 SelectionDAG& DAG) const {
3280 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3281 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3282 unsigned StackAlignment = TFI.getStackAlignment();
3283 uint64_t AlignMask = StackAlignment - 1;
3284 int64_t Offset = StackSize;
3285 unsigned SlotSize = RegInfo->getSlotSize();
3286 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3287 // Number smaller than 12 so just add the difference.
3288 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3290 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3291 Offset = ((~AlignMask) & Offset) + StackAlignment +
3292 (StackAlignment-SlotSize);
3297 /// MatchingStackOffset - Return true if the given stack call argument is
3298 /// already available in the same position (relatively) of the caller's
3299 /// incoming argument stack.
3301 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3302 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3303 const X86InstrInfo *TII) {
3304 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3306 if (Arg.getOpcode() == ISD::CopyFromReg) {
3307 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3308 if (!TargetRegisterInfo::isVirtualRegister(VR))
3310 MachineInstr *Def = MRI->getVRegDef(VR);
3313 if (!Flags.isByVal()) {
3314 if (!TII->isLoadFromStackSlot(Def, FI))
3317 unsigned Opcode = Def->getOpcode();
3318 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3319 Opcode == X86::LEA64_32r) &&
3320 Def->getOperand(1).isFI()) {
3321 FI = Def->getOperand(1).getIndex();
3322 Bytes = Flags.getByValSize();
3326 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3327 if (Flags.isByVal())
3328 // ByVal argument is passed in as a pointer but it's now being
3329 // dereferenced. e.g.
3330 // define @foo(%struct.X* %A) {
3331 // tail call @bar(%struct.X* byval %A)
3334 SDValue Ptr = Ld->getBasePtr();
3335 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3338 FI = FINode->getIndex();
3339 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3340 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3341 FI = FINode->getIndex();
3342 Bytes = Flags.getByValSize();
3346 assert(FI != INT_MAX);
3347 if (!MFI->isFixedObjectIndex(FI))
3349 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3352 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3353 /// for tail call optimization. Targets which want to do tail call
3354 /// optimization should implement this function.
3356 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3357 CallingConv::ID CalleeCC,
3359 bool isCalleeStructRet,
3360 bool isCallerStructRet,
3362 const SmallVectorImpl<ISD::OutputArg> &Outs,
3363 const SmallVectorImpl<SDValue> &OutVals,
3364 const SmallVectorImpl<ISD::InputArg> &Ins,
3365 SelectionDAG &DAG) const {
3366 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3369 // If -tailcallopt is specified, make fastcc functions tail-callable.
3370 const MachineFunction &MF = DAG.getMachineFunction();
3371 const Function *CallerF = MF.getFunction();
3373 // If the function return type is x86_fp80 and the callee return type is not,
3374 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3375 // perform a tailcall optimization here.
3376 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3379 CallingConv::ID CallerCC = CallerF->getCallingConv();
3380 bool CCMatch = CallerCC == CalleeCC;
3381 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3382 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3384 // Win64 functions have extra shadow space for argument homing. Don't do the
3385 // sibcall if the caller and callee have mismatched expectations for this
3387 if (IsCalleeWin64 != IsCallerWin64)
3390 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3391 if (IsTailCallConvention(CalleeCC) && CCMatch)
3396 // Look for obvious safe cases to perform tail call optimization that do not
3397 // require ABI changes. This is what gcc calls sibcall.
3399 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3400 // emit a special epilogue.
3401 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3402 if (RegInfo->needsStackRealignment(MF))
3405 // Also avoid sibcall optimization if either caller or callee uses struct
3406 // return semantics.
3407 if (isCalleeStructRet || isCallerStructRet)
3410 // An stdcall/thiscall caller is expected to clean up its arguments; the
3411 // callee isn't going to do that.
3412 // FIXME: this is more restrictive than needed. We could produce a tailcall
3413 // when the stack adjustment matches. For example, with a thiscall that takes
3414 // only one argument.
3415 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3416 CallerCC == CallingConv::X86_ThisCall))
3419 // Do not sibcall optimize vararg calls unless all arguments are passed via
3421 if (isVarArg && !Outs.empty()) {
3423 // Optimizing for varargs on Win64 is unlikely to be safe without
3424 // additional testing.
3425 if (IsCalleeWin64 || IsCallerWin64)
3428 SmallVector<CCValAssign, 16> ArgLocs;
3429 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3432 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3433 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3434 if (!ArgLocs[i].isRegLoc())
3438 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3439 // stack. Therefore, if it's not used by the call it is not safe to optimize
3440 // this into a sibcall.
3441 bool Unused = false;
3442 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3449 SmallVector<CCValAssign, 16> RVLocs;
3450 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3452 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3453 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3454 CCValAssign &VA = RVLocs[i];
3455 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3460 // If the calling conventions do not match, then we'd better make sure the
3461 // results are returned in the same way as what the caller expects.
3463 SmallVector<CCValAssign, 16> RVLocs1;
3464 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3466 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3468 SmallVector<CCValAssign, 16> RVLocs2;
3469 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3471 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3473 if (RVLocs1.size() != RVLocs2.size())
3475 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3476 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3478 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3480 if (RVLocs1[i].isRegLoc()) {
3481 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3484 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3490 // If the callee takes no arguments then go on to check the results of the
3492 if (!Outs.empty()) {
3493 // Check if stack adjustment is needed. For now, do not do this if any
3494 // argument is passed on the stack.
3495 SmallVector<CCValAssign, 16> ArgLocs;
3496 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3499 // Allocate shadow area for Win64
3501 CCInfo.AllocateStack(32, 8);
3503 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3504 if (CCInfo.getNextStackOffset()) {
3505 MachineFunction &MF = DAG.getMachineFunction();
3506 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3509 // Check if the arguments are already laid out in the right way as
3510 // the caller's fixed stack objects.
3511 MachineFrameInfo *MFI = MF.getFrameInfo();
3512 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3513 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3514 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3515 CCValAssign &VA = ArgLocs[i];
3516 SDValue Arg = OutVals[i];
3517 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3518 if (VA.getLocInfo() == CCValAssign::Indirect)
3520 if (!VA.isRegLoc()) {
3521 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3528 // If the tailcall address may be in a register, then make sure it's
3529 // possible to register allocate for it. In 32-bit, the call address can
3530 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3531 // callee-saved registers are restored. These happen to be the same
3532 // registers used to pass 'inreg' arguments so watch out for those.
3533 if (!Subtarget->is64Bit() &&
3534 ((!isa<GlobalAddressSDNode>(Callee) &&
3535 !isa<ExternalSymbolSDNode>(Callee)) ||
3536 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3537 unsigned NumInRegs = 0;
3538 // In PIC we need an extra register to formulate the address computation
3540 unsigned MaxInRegs =
3541 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3543 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3544 CCValAssign &VA = ArgLocs[i];
3547 unsigned Reg = VA.getLocReg();
3550 case X86::EAX: case X86::EDX: case X86::ECX:
3551 if (++NumInRegs == MaxInRegs)
3563 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3564 const TargetLibraryInfo *libInfo) const {
3565 return X86::createFastISel(funcInfo, libInfo);
3568 //===----------------------------------------------------------------------===//
3569 // Other Lowering Hooks
3570 //===----------------------------------------------------------------------===//
3572 static bool MayFoldLoad(SDValue Op) {
3573 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3576 static bool MayFoldIntoStore(SDValue Op) {
3577 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3580 static bool isTargetShuffle(unsigned Opcode) {
3582 default: return false;
3583 case X86ISD::BLENDI:
3584 case X86ISD::PSHUFB:
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3589 case X86ISD::PALIGNR:
3590 case X86ISD::MOVLHPS:
3591 case X86ISD::MOVLHPD:
3592 case X86ISD::MOVHLPS:
3593 case X86ISD::MOVLPS:
3594 case X86ISD::MOVLPD:
3595 case X86ISD::MOVSHDUP:
3596 case X86ISD::MOVSLDUP:
3597 case X86ISD::MOVDDUP:
3600 case X86ISD::UNPCKL:
3601 case X86ISD::UNPCKH:
3602 case X86ISD::VPERMILPI:
3603 case X86ISD::VPERM2X128:
3604 case X86ISD::VPERMI:
3609 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3610 SDValue V1, unsigned TargetMask,
3611 SelectionDAG &DAG) {
3613 default: llvm_unreachable("Unknown x86 shuffle node");
3614 case X86ISD::PSHUFD:
3615 case X86ISD::PSHUFHW:
3616 case X86ISD::PSHUFLW:
3617 case X86ISD::VPERMILPI:
3618 case X86ISD::VPERMI:
3619 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3623 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3624 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3626 default: llvm_unreachable("Unknown x86 shuffle node");
3627 case X86ISD::MOVLHPS:
3628 case X86ISD::MOVLHPD:
3629 case X86ISD::MOVHLPS:
3630 case X86ISD::MOVLPS:
3631 case X86ISD::MOVLPD:
3634 case X86ISD::UNPCKL:
3635 case X86ISD::UNPCKH:
3636 return DAG.getNode(Opc, dl, VT, V1, V2);
3640 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3641 MachineFunction &MF = DAG.getMachineFunction();
3642 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3643 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3644 int ReturnAddrIndex = FuncInfo->getRAIndex();
3646 if (ReturnAddrIndex == 0) {
3647 // Set up a frame object for the return address.
3648 unsigned SlotSize = RegInfo->getSlotSize();
3649 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3652 FuncInfo->setRAIndex(ReturnAddrIndex);
3655 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3658 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3659 bool hasSymbolicDisplacement) {
3660 // Offset should fit into 32 bit immediate field.
3661 if (!isInt<32>(Offset))
3664 // If we don't have a symbolic displacement - we don't have any extra
3666 if (!hasSymbolicDisplacement)
3669 // FIXME: Some tweaks might be needed for medium code model.
3670 if (M != CodeModel::Small && M != CodeModel::Kernel)
3673 // For small code model we assume that latest object is 16MB before end of 31
3674 // bits boundary. We may also accept pretty large negative constants knowing
3675 // that all objects are in the positive half of address space.
3676 if (M == CodeModel::Small && Offset < 16*1024*1024)
3679 // For kernel code model we know that all object resist in the negative half
3680 // of 32bits address space. We may not accept negative offsets, since they may
3681 // be just off and we may accept pretty large positive ones.
3682 if (M == CodeModel::Kernel && Offset >= 0)
3688 /// isCalleePop - Determines whether the callee is required to pop its
3689 /// own arguments. Callee pop is necessary to support tail calls.
3690 bool X86::isCalleePop(CallingConv::ID CallingConv,
3691 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3692 switch (CallingConv) {
3695 case CallingConv::X86_StdCall:
3696 case CallingConv::X86_FastCall:
3697 case CallingConv::X86_ThisCall:
3699 case CallingConv::Fast:
3700 case CallingConv::GHC:
3701 case CallingConv::HiPE:
3708 /// \brief Return true if the condition is an unsigned comparison operation.
3709 static bool isX86CCUnsigned(unsigned X86CC) {
3711 default: llvm_unreachable("Invalid integer condition!");
3712 case X86::COND_E: return true;
3713 case X86::COND_G: return false;
3714 case X86::COND_GE: return false;
3715 case X86::COND_L: return false;
3716 case X86::COND_LE: return false;
3717 case X86::COND_NE: return true;
3718 case X86::COND_B: return true;
3719 case X86::COND_A: return true;
3720 case X86::COND_BE: return true;
3721 case X86::COND_AE: return true;
3723 llvm_unreachable("covered switch fell through?!");
3726 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3727 /// specific condition code, returning the condition code and the LHS/RHS of the
3728 /// comparison to make.
3729 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3730 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3732 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3733 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3734 // X > -1 -> X == 0, jump !sign.
3735 RHS = DAG.getConstant(0, RHS.getValueType());
3736 return X86::COND_NS;
3738 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3739 // X < 0 -> X == 0, jump on sign.
3742 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3744 RHS = DAG.getConstant(0, RHS.getValueType());
3745 return X86::COND_LE;
3749 switch (SetCCOpcode) {
3750 default: llvm_unreachable("Invalid integer condition!");
3751 case ISD::SETEQ: return X86::COND_E;
3752 case ISD::SETGT: return X86::COND_G;
3753 case ISD::SETGE: return X86::COND_GE;
3754 case ISD::SETLT: return X86::COND_L;
3755 case ISD::SETLE: return X86::COND_LE;
3756 case ISD::SETNE: return X86::COND_NE;
3757 case ISD::SETULT: return X86::COND_B;
3758 case ISD::SETUGT: return X86::COND_A;
3759 case ISD::SETULE: return X86::COND_BE;
3760 case ISD::SETUGE: return X86::COND_AE;
3764 // First determine if it is required or is profitable to flip the operands.
3766 // If LHS is a foldable load, but RHS is not, flip the condition.
3767 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3768 !ISD::isNON_EXTLoad(RHS.getNode())) {
3769 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3770 std::swap(LHS, RHS);
3773 switch (SetCCOpcode) {
3779 std::swap(LHS, RHS);
3783 // On a floating point condition, the flags are set as follows:
3785 // 0 | 0 | 0 | X > Y
3786 // 0 | 0 | 1 | X < Y
3787 // 1 | 0 | 0 | X == Y
3788 // 1 | 1 | 1 | unordered
3789 switch (SetCCOpcode) {
3790 default: llvm_unreachable("Condcode should be pre-legalized away");
3792 case ISD::SETEQ: return X86::COND_E;
3793 case ISD::SETOLT: // flipped
3795 case ISD::SETGT: return X86::COND_A;
3796 case ISD::SETOLE: // flipped
3798 case ISD::SETGE: return X86::COND_AE;
3799 case ISD::SETUGT: // flipped
3801 case ISD::SETLT: return X86::COND_B;
3802 case ISD::SETUGE: // flipped
3804 case ISD::SETLE: return X86::COND_BE;
3806 case ISD::SETNE: return X86::COND_NE;
3807 case ISD::SETUO: return X86::COND_P;
3808 case ISD::SETO: return X86::COND_NP;
3810 case ISD::SETUNE: return X86::COND_INVALID;
3814 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3815 /// code. Current x86 isa includes the following FP cmov instructions:
3816 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3817 static bool hasFPCMov(unsigned X86CC) {
3833 /// isFPImmLegal - Returns true if the target can instruction select the
3834 /// specified FP immediate natively. If false, the legalizer will
3835 /// materialize the FP immediate as a load from a constant pool.
3836 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3837 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3838 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3844 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3845 ISD::LoadExtType ExtTy,
3847 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3848 // relocation target a movq or addq instruction: don't let the load shrink.
3849 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3850 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3851 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3852 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3856 /// \brief Returns true if it is beneficial to convert a load of a constant
3857 /// to just the constant itself.
3858 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3860 assert(Ty->isIntegerTy());
3862 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3863 if (BitSize == 0 || BitSize > 64)
3868 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3869 unsigned Index) const {
3870 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3873 return (Index == 0 || Index == ResVT.getVectorNumElements());
3876 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3877 // Speculate cttz only if we can directly use TZCNT.
3878 return Subtarget->hasBMI();
3881 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3882 // Speculate ctlz only if we can directly use LZCNT.
3883 return Subtarget->hasLZCNT();
3886 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3887 /// the specified range (L, H].
3888 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3889 return (Val < 0) || (Val >= Low && Val < Hi);
3892 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3893 /// specified value.
3894 static bool isUndefOrEqual(int Val, int CmpVal) {
3895 return (Val < 0 || Val == CmpVal);
3898 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3899 /// from position Pos and ending in Pos+Size, falls within the specified
3900 /// sequential range (Low, Low+Size]. or is undef.
3901 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3902 unsigned Pos, unsigned Size, int Low) {
3903 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3904 if (!isUndefOrEqual(Mask[i], Low))
3909 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3910 /// the two vector operands have swapped position.
3911 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3912 unsigned NumElems) {
3913 for (unsigned i = 0; i != NumElems; ++i) {
3917 else if (idx < (int)NumElems)
3918 Mask[i] = idx + NumElems;
3920 Mask[i] = idx - NumElems;
3924 /// isVEXTRACTIndex - Return true if the specified
3925 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3926 /// suitable for instruction that extract 128 or 256 bit vectors
3927 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3928 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3929 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3932 // The index should be aligned on a vecWidth-bit boundary.
3934 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3936 MVT VT = N->getSimpleValueType(0);
3937 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3938 bool Result = (Index * ElSize) % vecWidth == 0;
3943 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3944 /// operand specifies a subvector insert that is suitable for input to
3945 /// insertion of 128 or 256-bit subvectors
3946 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3947 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3948 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3950 // The index should be aligned on a vecWidth-bit boundary.
3952 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3954 MVT VT = N->getSimpleValueType(0);
3955 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3956 bool Result = (Index * ElSize) % vecWidth == 0;
3961 bool X86::isVINSERT128Index(SDNode *N) {
3962 return isVINSERTIndex(N, 128);
3965 bool X86::isVINSERT256Index(SDNode *N) {
3966 return isVINSERTIndex(N, 256);
3969 bool X86::isVEXTRACT128Index(SDNode *N) {
3970 return isVEXTRACTIndex(N, 128);
3973 bool X86::isVEXTRACT256Index(SDNode *N) {
3974 return isVEXTRACTIndex(N, 256);
3977 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3978 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3979 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3980 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3983 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3985 MVT VecVT = N->getOperand(0).getSimpleValueType();
3986 MVT ElVT = VecVT.getVectorElementType();
3988 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3989 return Index / NumElemsPerChunk;
3992 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3993 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3994 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3995 llvm_unreachable("Illegal insert subvector for VINSERT");
3998 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4000 MVT VecVT = N->getSimpleValueType(0);
4001 MVT ElVT = VecVT.getVectorElementType();
4003 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4004 return Index / NumElemsPerChunk;
4007 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4008 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4009 /// and VINSERTI128 instructions.
4010 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4011 return getExtractVEXTRACTImmediate(N, 128);
4014 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4015 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4016 /// and VINSERTI64x4 instructions.
4017 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4018 return getExtractVEXTRACTImmediate(N, 256);
4021 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4022 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4023 /// and VINSERTI128 instructions.
4024 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4025 return getInsertVINSERTImmediate(N, 128);
4028 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4029 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4030 /// and VINSERTI64x4 instructions.
4031 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4032 return getInsertVINSERTImmediate(N, 256);
4035 /// isZero - Returns true if Elt is a constant integer zero
4036 static bool isZero(SDValue V) {
4037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4038 return C && C->isNullValue();
4041 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4043 bool X86::isZeroNode(SDValue Elt) {
4046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4047 return CFP->getValueAPF().isPosZero();
4051 /// getZeroVector - Returns a vector of specified type with all zero elements.
4053 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4054 SelectionDAG &DAG, SDLoc dl) {
4055 assert(VT.isVector() && "Expected a vector type");
4057 // Always build SSE zero vectors as <4 x i32> bitcasted
4058 // to their dest type. This ensures they get CSE'd.
4060 if (VT.is128BitVector()) { // SSE
4061 if (Subtarget->hasSSE2()) { // SSE2
4062 SDValue Cst = DAG.getConstant(0, MVT::i32);
4063 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4065 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
4066 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4068 } else if (VT.is256BitVector()) { // AVX
4069 if (Subtarget->hasInt256()) { // AVX2
4070 SDValue Cst = DAG.getConstant(0, MVT::i32);
4071 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4074 // 256-bit logic and arithmetic instructions in AVX are all
4075 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4076 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
4077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4080 } else if (VT.is512BitVector()) { // AVX-512
4081 SDValue Cst = DAG.getConstant(0, MVT::i32);
4082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4083 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4085 } else if (VT.getScalarType() == MVT::i1) {
4086 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4087 SDValue Cst = DAG.getConstant(0, MVT::i1);
4088 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4089 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4091 llvm_unreachable("Unexpected vector type");
4093 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4096 /// getOnesVector - Returns a vector of specified type with all bits set.
4097 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4098 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4099 /// Then bitcast to their original type, ensuring they get CSE'd.
4100 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4102 assert(VT.isVector() && "Expected a vector type");
4104 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
4106 if (VT.is256BitVector()) {
4107 if (HasInt256) { // AVX2
4108 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4109 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4111 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4112 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4114 } else if (VT.is128BitVector()) {
4115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4117 llvm_unreachable("Unexpected vector type");
4119 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4122 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4123 /// operation of specified width.
4124 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4126 unsigned NumElems = VT.getVectorNumElements();
4127 SmallVector<int, 8> Mask;
4128 Mask.push_back(NumElems);
4129 for (unsigned i = 1; i != NumElems; ++i)
4131 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4134 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4135 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4137 unsigned NumElems = VT.getVectorNumElements();
4138 SmallVector<int, 8> Mask;
4139 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4141 Mask.push_back(i + NumElems);
4143 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4146 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4147 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4149 unsigned NumElems = VT.getVectorNumElements();
4150 SmallVector<int, 8> Mask;
4151 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4152 Mask.push_back(i + Half);
4153 Mask.push_back(i + NumElems + Half);
4155 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4158 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4159 /// vector of zero or undef vector. This produces a shuffle where the low
4160 /// element of V2 is swizzled into the zero/undef vector, landing at element
4161 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4162 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4164 const X86Subtarget *Subtarget,
4165 SelectionDAG &DAG) {
4166 MVT VT = V2.getSimpleValueType();
4168 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4169 unsigned NumElems = VT.getVectorNumElements();
4170 SmallVector<int, 16> MaskVec;
4171 for (unsigned i = 0; i != NumElems; ++i)
4172 // If this is the insertion idx, put the low elt of V2 here.
4173 MaskVec.push_back(i == Idx ? NumElems : i);
4174 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4177 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4178 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4179 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4180 /// shuffles which use a single input multiple times, and in those cases it will
4181 /// adjust the mask to only have indices within that single input.
4182 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4183 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4184 unsigned NumElems = VT.getVectorNumElements();
4188 bool IsFakeUnary = false;
4189 switch(N->getOpcode()) {
4190 case X86ISD::BLENDI:
4191 ImmN = N->getOperand(N->getNumOperands()-1);
4192 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4195 ImmN = N->getOperand(N->getNumOperands()-1);
4196 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4197 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4199 case X86ISD::UNPCKH:
4200 DecodeUNPCKHMask(VT, Mask);
4201 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4203 case X86ISD::UNPCKL:
4204 DecodeUNPCKLMask(VT, Mask);
4205 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4207 case X86ISD::MOVHLPS:
4208 DecodeMOVHLPSMask(NumElems, Mask);
4209 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4211 case X86ISD::MOVLHPS:
4212 DecodeMOVLHPSMask(NumElems, Mask);
4213 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4215 case X86ISD::PALIGNR:
4216 ImmN = N->getOperand(N->getNumOperands()-1);
4217 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4219 case X86ISD::PSHUFD:
4220 case X86ISD::VPERMILPI:
4221 ImmN = N->getOperand(N->getNumOperands()-1);
4222 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4225 case X86ISD::PSHUFHW:
4226 ImmN = N->getOperand(N->getNumOperands()-1);
4227 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4230 case X86ISD::PSHUFLW:
4231 ImmN = N->getOperand(N->getNumOperands()-1);
4232 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4235 case X86ISD::PSHUFB: {
4237 SDValue MaskNode = N->getOperand(1);
4238 while (MaskNode->getOpcode() == ISD::BITCAST)
4239 MaskNode = MaskNode->getOperand(0);
4241 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4242 // If we have a build-vector, then things are easy.
4243 EVT VT = MaskNode.getValueType();
4244 assert(VT.isVector() &&
4245 "Can't produce a non-vector with a build_vector!");
4246 if (!VT.isInteger())
4249 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4251 SmallVector<uint64_t, 32> RawMask;
4252 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4253 SDValue Op = MaskNode->getOperand(i);
4254 if (Op->getOpcode() == ISD::UNDEF) {
4255 RawMask.push_back((uint64_t)SM_SentinelUndef);
4258 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4261 APInt MaskElement = CN->getAPIntValue();
4263 // We now have to decode the element which could be any integer size and
4264 // extract each byte of it.
4265 for (int j = 0; j < NumBytesPerElement; ++j) {
4266 // Note that this is x86 and so always little endian: the low byte is
4267 // the first byte of the mask.
4268 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4269 MaskElement = MaskElement.lshr(8);
4272 DecodePSHUFBMask(RawMask, Mask);
4276 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4280 SDValue Ptr = MaskLoad->getBasePtr();
4281 if (Ptr->getOpcode() == X86ISD::Wrapper)
4282 Ptr = Ptr->getOperand(0);
4284 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4285 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4288 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4289 DecodePSHUFBMask(C, Mask);
4297 case X86ISD::VPERMI:
4298 ImmN = N->getOperand(N->getNumOperands()-1);
4299 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4304 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4306 case X86ISD::VPERM2X128:
4307 ImmN = N->getOperand(N->getNumOperands()-1);
4308 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4309 if (Mask.empty()) return false;
4311 case X86ISD::MOVSLDUP:
4312 DecodeMOVSLDUPMask(VT, Mask);
4315 case X86ISD::MOVSHDUP:
4316 DecodeMOVSHDUPMask(VT, Mask);
4319 case X86ISD::MOVDDUP:
4320 DecodeMOVDDUPMask(VT, Mask);
4323 case X86ISD::MOVLHPD:
4324 case X86ISD::MOVLPD:
4325 case X86ISD::MOVLPS:
4326 // Not yet implemented
4328 default: llvm_unreachable("unknown target shuffle node");
4331 // If we have a fake unary shuffle, the shuffle mask is spread across two
4332 // inputs that are actually the same node. Re-map the mask to always point
4333 // into the first input.
4336 if (M >= (int)Mask.size())
4342 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4343 /// element of the result of the vector shuffle.
4344 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4347 return SDValue(); // Limit search depth.
4349 SDValue V = SDValue(N, 0);
4350 EVT VT = V.getValueType();
4351 unsigned Opcode = V.getOpcode();
4353 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4354 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4355 int Elt = SV->getMaskElt(Index);
4358 return DAG.getUNDEF(VT.getVectorElementType());
4360 unsigned NumElems = VT.getVectorNumElements();
4361 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4362 : SV->getOperand(1);
4363 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4366 // Recurse into target specific vector shuffles to find scalars.
4367 if (isTargetShuffle(Opcode)) {
4368 MVT ShufVT = V.getSimpleValueType();
4369 unsigned NumElems = ShufVT.getVectorNumElements();
4370 SmallVector<int, 16> ShuffleMask;
4373 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4376 int Elt = ShuffleMask[Index];
4378 return DAG.getUNDEF(ShufVT.getVectorElementType());
4380 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4382 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4386 // Actual nodes that may contain scalar elements
4387 if (Opcode == ISD::BITCAST) {
4388 V = V.getOperand(0);
4389 EVT SrcVT = V.getValueType();
4390 unsigned NumElems = VT.getVectorNumElements();
4392 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4396 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4397 return (Index == 0) ? V.getOperand(0)
4398 : DAG.getUNDEF(VT.getVectorElementType());
4400 if (V.getOpcode() == ISD::BUILD_VECTOR)
4401 return V.getOperand(Index);
4406 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4408 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4409 unsigned NumNonZero, unsigned NumZero,
4411 const X86Subtarget* Subtarget,
4412 const TargetLowering &TLI) {
4419 for (unsigned i = 0; i < 16; ++i) {
4420 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4421 if (ThisIsNonZero && First) {
4423 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4425 V = DAG.getUNDEF(MVT::v8i16);
4430 SDValue ThisElt, LastElt;
4431 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4432 if (LastIsNonZero) {
4433 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4434 MVT::i16, Op.getOperand(i-1));
4436 if (ThisIsNonZero) {
4437 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4438 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4439 ThisElt, DAG.getConstant(8, MVT::i8));
4441 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4445 if (ThisElt.getNode())
4446 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4447 DAG.getIntPtrConstant(i/2));
4451 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4454 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4456 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4457 unsigned NumNonZero, unsigned NumZero,
4459 const X86Subtarget* Subtarget,
4460 const TargetLowering &TLI) {
4467 for (unsigned i = 0; i < 8; ++i) {
4468 bool isNonZero = (NonZeros & (1 << i)) != 0;
4472 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4474 V = DAG.getUNDEF(MVT::v8i16);
4477 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4478 MVT::v8i16, V, Op.getOperand(i),
4479 DAG.getIntPtrConstant(i));
4486 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4487 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4488 const X86Subtarget *Subtarget,
4489 const TargetLowering &TLI) {
4490 // Find all zeroable elements.
4491 std::bitset<4> Zeroable;
4492 for (int i=0; i < 4; ++i) {
4493 SDValue Elt = Op->getOperand(i);
4494 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4496 assert(Zeroable.size() - Zeroable.count() > 1 &&
4497 "We expect at least two non-zero elements!");
4499 // We only know how to deal with build_vector nodes where elements are either
4500 // zeroable or extract_vector_elt with constant index.
4501 SDValue FirstNonZero;
4502 unsigned FirstNonZeroIdx;
4503 for (unsigned i=0; i < 4; ++i) {
4506 SDValue Elt = Op->getOperand(i);
4507 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4508 !isa<ConstantSDNode>(Elt.getOperand(1)))
4510 // Make sure that this node is extracting from a 128-bit vector.
4511 MVT VT = Elt.getOperand(0).getSimpleValueType();
4512 if (!VT.is128BitVector())
4514 if (!FirstNonZero.getNode()) {
4516 FirstNonZeroIdx = i;
4520 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4521 SDValue V1 = FirstNonZero.getOperand(0);
4522 MVT VT = V1.getSimpleValueType();
4524 // See if this build_vector can be lowered as a blend with zero.
4526 unsigned EltMaskIdx, EltIdx;
4528 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4529 if (Zeroable[EltIdx]) {
4530 // The zero vector will be on the right hand side.
4531 Mask[EltIdx] = EltIdx+4;
4535 Elt = Op->getOperand(EltIdx);
4536 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4537 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4538 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4540 Mask[EltIdx] = EltIdx;
4544 // Let the shuffle legalizer deal with blend operations.
4545 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4546 if (V1.getSimpleValueType() != VT)
4547 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4548 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4551 // See if we can lower this build_vector to a INSERTPS.
4552 if (!Subtarget->hasSSE41())
4555 SDValue V2 = Elt.getOperand(0);
4556 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4559 bool CanFold = true;
4560 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4564 SDValue Current = Op->getOperand(i);
4565 SDValue SrcVector = Current->getOperand(0);
4568 CanFold = SrcVector == V1 &&
4569 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4575 assert(V1.getNode() && "Expected at least two non-zero elements!");
4576 if (V1.getSimpleValueType() != MVT::v4f32)
4577 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4578 if (V2.getSimpleValueType() != MVT::v4f32)
4579 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4581 // Ok, we can emit an INSERTPS instruction.
4582 unsigned ZMask = Zeroable.to_ulong();
4584 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4585 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4586 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
4587 DAG.getIntPtrConstant(InsertPSMask));
4588 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
4591 /// Return a vector logical shift node.
4592 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4593 unsigned NumBits, SelectionDAG &DAG,
4594 const TargetLowering &TLI, SDLoc dl) {
4595 assert(VT.is128BitVector() && "Unknown type for VShift");
4596 MVT ShVT = MVT::v2i64;
4597 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4598 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4599 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4600 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4601 SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);
4602 return DAG.getNode(ISD::BITCAST, dl, VT,
4603 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4607 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4609 // Check if the scalar load can be widened into a vector load. And if
4610 // the address is "base + cst" see if the cst can be "absorbed" into
4611 // the shuffle mask.
4612 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4613 SDValue Ptr = LD->getBasePtr();
4614 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4616 EVT PVT = LD->getValueType(0);
4617 if (PVT != MVT::i32 && PVT != MVT::f32)
4622 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4623 FI = FINode->getIndex();
4625 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4626 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4627 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4628 Offset = Ptr.getConstantOperandVal(1);
4629 Ptr = Ptr.getOperand(0);
4634 // FIXME: 256-bit vector instructions don't require a strict alignment,
4635 // improve this code to support it better.
4636 unsigned RequiredAlign = VT.getSizeInBits()/8;
4637 SDValue Chain = LD->getChain();
4638 // Make sure the stack object alignment is at least 16 or 32.
4639 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4640 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4641 if (MFI->isFixedObjectIndex(FI)) {
4642 // Can't change the alignment. FIXME: It's possible to compute
4643 // the exact stack offset and reference FI + adjust offset instead.
4644 // If someone *really* cares about this. That's the way to implement it.
4647 MFI->setObjectAlignment(FI, RequiredAlign);
4651 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4652 // Ptr + (Offset & ~15).
4655 if ((Offset % RequiredAlign) & 3)
4657 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4659 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
4660 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4662 int EltNo = (Offset - StartOffset) >> 2;
4663 unsigned NumElems = VT.getVectorNumElements();
4665 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4666 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4667 LD->getPointerInfo().getWithOffset(StartOffset),
4668 false, false, false, 0);
4670 SmallVector<int, 8> Mask(NumElems, EltNo);
4672 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4678 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4679 /// elements can be replaced by a single large load which has the same value as
4680 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4682 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4684 /// FIXME: we'd also like to handle the case where the last elements are zero
4685 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4686 /// There's even a handy isZeroNode for that purpose.
4687 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4688 SDLoc &DL, SelectionDAG &DAG,
4689 bool isAfterLegalize) {
4690 unsigned NumElems = Elts.size();
4692 LoadSDNode *LDBase = nullptr;
4693 unsigned LastLoadedElt = -1U;
4695 // For each element in the initializer, see if we've found a load or an undef.
4696 // If we don't find an initial load element, or later load elements are
4697 // non-consecutive, bail out.
4698 for (unsigned i = 0; i < NumElems; ++i) {
4699 SDValue Elt = Elts[i];
4700 // Look through a bitcast.
4701 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4702 Elt = Elt.getOperand(0);
4703 if (!Elt.getNode() ||
4704 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4707 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4709 LDBase = cast<LoadSDNode>(Elt.getNode());
4713 if (Elt.getOpcode() == ISD::UNDEF)
4716 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4717 EVT LdVT = Elt.getValueType();
4718 // Each loaded element must be the correct fractional portion of the
4719 // requested vector load.
4720 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4722 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4727 // If we have found an entire vector of loads and undefs, then return a large
4728 // load of the entire vector width starting at the base pointer. If we found
4729 // consecutive loads for the low half, generate a vzext_load node.
4730 if (LastLoadedElt == NumElems - 1) {
4731 assert(LDBase && "Did not find base load for merging consecutive loads");
4732 EVT EltVT = LDBase->getValueType(0);
4733 // Ensure that the input vector size for the merged loads matches the
4734 // cumulative size of the input elements.
4735 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4738 if (isAfterLegalize &&
4739 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4742 SDValue NewLd = SDValue();
4744 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4745 LDBase->getPointerInfo(), LDBase->isVolatile(),
4746 LDBase->isNonTemporal(), LDBase->isInvariant(),
4747 LDBase->getAlignment());
4749 if (LDBase->hasAnyUseOfValue(1)) {
4750 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4752 SDValue(NewLd.getNode(), 1));
4753 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4754 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4755 SDValue(NewLd.getNode(), 1));
4761 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4762 //of a v4i32 / v4f32. It's probably worth generalizing.
4763 EVT EltVT = VT.getVectorElementType();
4764 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4765 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4766 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4767 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4769 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4770 LDBase->getPointerInfo(),
4771 LDBase->getAlignment(),
4772 false/*isVolatile*/, true/*ReadMem*/,
4775 // Make sure the newly-created LOAD is in the same position as LDBase in
4776 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4777 // update uses of LDBase's output chain to use the TokenFactor.
4778 if (LDBase->hasAnyUseOfValue(1)) {
4779 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4780 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4781 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4782 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4783 SDValue(ResNode.getNode(), 1));
4786 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4791 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4792 /// to generate a splat value for the following cases:
4793 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4794 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4795 /// a scalar load, or a constant.
4796 /// The VBROADCAST node is returned when a pattern is found,
4797 /// or SDValue() otherwise.
4798 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4799 SelectionDAG &DAG) {
4800 // VBROADCAST requires AVX.
4801 // TODO: Splats could be generated for non-AVX CPUs using SSE
4802 // instructions, but there's less potential gain for only 128-bit vectors.
4803 if (!Subtarget->hasAVX())
4806 MVT VT = Op.getSimpleValueType();
4809 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4810 "Unsupported vector type for broadcast.");
4815 switch (Op.getOpcode()) {
4817 // Unknown pattern found.
4820 case ISD::BUILD_VECTOR: {
4821 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4822 BitVector UndefElements;
4823 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4825 // We need a splat of a single value to use broadcast, and it doesn't
4826 // make any sense if the value is only in one element of the vector.
4827 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4831 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4832 Ld.getOpcode() == ISD::ConstantFP);
4834 // Make sure that all of the users of a non-constant load are from the
4835 // BUILD_VECTOR node.
4836 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4841 case ISD::VECTOR_SHUFFLE: {
4842 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4844 // Shuffles must have a splat mask where the first element is
4846 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4849 SDValue Sc = Op.getOperand(0);
4850 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4851 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4853 if (!Subtarget->hasInt256())
4856 // Use the register form of the broadcast instruction available on AVX2.
4857 if (VT.getSizeInBits() >= 256)
4858 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4859 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4862 Ld = Sc.getOperand(0);
4863 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4864 Ld.getOpcode() == ISD::ConstantFP);
4866 // The scalar_to_vector node and the suspected
4867 // load node must have exactly one user.
4868 // Constants may have multiple users.
4870 // AVX-512 has register version of the broadcast
4871 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4872 Ld.getValueType().getSizeInBits() >= 32;
4873 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
4880 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4881 bool IsGE256 = (VT.getSizeInBits() >= 256);
4883 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4884 // instruction to save 8 or more bytes of constant pool data.
4885 // TODO: If multiple splats are generated to load the same constant,
4886 // it may be detrimental to overall size. There needs to be a way to detect
4887 // that condition to know if this is truly a size win.
4888 const Function *F = DAG.getMachineFunction().getFunction();
4889 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
4891 // Handle broadcasting a single constant scalar from the constant pool
4893 // On Sandybridge (no AVX2), it is still better to load a constant vector
4894 // from the constant pool and not to broadcast it from a scalar.
4895 // But override that restriction when optimizing for size.
4896 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
4897 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
4898 EVT CVT = Ld.getValueType();
4899 assert(!CVT.isVector() && "Must not broadcast a vector type");
4901 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
4902 // For size optimization, also splat v2f64 and v2i64, and for size opt
4903 // with AVX2, also splat i8 and i16.
4904 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
4905 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4906 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
4907 const Constant *C = nullptr;
4908 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4909 C = CI->getConstantIntValue();
4910 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4911 C = CF->getConstantFPValue();
4913 assert(C && "Invalid constant type");
4915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4916 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
4917 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4918 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4919 MachinePointerInfo::getConstantPool(),
4920 false, false, false, Alignment);
4922 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4926 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
4928 // Handle AVX2 in-register broadcasts.
4929 if (!IsLoad && Subtarget->hasInt256() &&
4930 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
4931 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4933 // The scalar source must be a normal load.
4937 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4938 (Subtarget->hasVLX() && ScalarSize == 64))
4939 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4941 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4942 // double since there is no vbroadcastsd xmm
4943 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
4944 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
4945 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4948 // Unsupported broadcast.
4952 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
4953 /// underlying vector and index.
4955 /// Modifies \p ExtractedFromVec to the real vector and returns the real
4957 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
4959 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
4960 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
4963 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
4965 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
4967 // (extract_vector_elt (vector_shuffle<2,u,u,u>
4968 // (extract_subvector (v8f32 %vreg0), Constant<4>),
4971 // In this case the vector is the extract_subvector expression and the index
4972 // is 2, as specified by the shuffle.
4973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
4974 SDValue ShuffleVec = SVOp->getOperand(0);
4975 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
4976 assert(ShuffleVecVT.getVectorElementType() ==
4977 ExtractedFromVec.getSimpleValueType().getVectorElementType());
4979 int ShuffleIdx = SVOp->getMaskElt(Idx);
4980 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
4981 ExtractedFromVec = ShuffleVec;
4987 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
4988 MVT VT = Op.getSimpleValueType();
4990 // Skip if insert_vec_elt is not supported.
4991 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4992 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
4996 unsigned NumElems = Op.getNumOperands();
5000 SmallVector<unsigned, 4> InsertIndices;
5001 SmallVector<int, 8> Mask(NumElems, -1);
5003 for (unsigned i = 0; i != NumElems; ++i) {
5004 unsigned Opc = Op.getOperand(i).getOpcode();
5006 if (Opc == ISD::UNDEF)
5009 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5010 // Quit if more than 1 elements need inserting.
5011 if (InsertIndices.size() > 1)
5014 InsertIndices.push_back(i);
5018 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5019 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5020 // Quit if non-constant index.
5021 if (!isa<ConstantSDNode>(ExtIdx))
5023 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5025 // Quit if extracted from vector of different type.
5026 if (ExtractedFromVec.getValueType() != VT)
5029 if (!VecIn1.getNode())
5030 VecIn1 = ExtractedFromVec;
5031 else if (VecIn1 != ExtractedFromVec) {
5032 if (!VecIn2.getNode())
5033 VecIn2 = ExtractedFromVec;
5034 else if (VecIn2 != ExtractedFromVec)
5035 // Quit if more than 2 vectors to shuffle
5039 if (ExtractedFromVec == VecIn1)
5041 else if (ExtractedFromVec == VecIn2)
5042 Mask[i] = Idx + NumElems;
5045 if (!VecIn1.getNode())
5048 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5049 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5050 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5051 unsigned Idx = InsertIndices[i];
5052 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5053 DAG.getIntPtrConstant(Idx));
5059 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5061 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5063 MVT VT = Op.getSimpleValueType();
5064 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5065 "Unexpected type in LowerBUILD_VECTORvXi1!");
5068 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5070 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5071 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5074 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5075 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5076 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5077 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5080 bool AllContants = true;
5081 uint64_t Immediate = 0;
5082 int NonConstIdx = -1;
5083 bool IsSplat = true;
5084 unsigned NumNonConsts = 0;
5085 unsigned NumConsts = 0;
5086 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5087 SDValue In = Op.getOperand(idx);
5088 if (In.getOpcode() == ISD::UNDEF)
5090 if (!isa<ConstantSDNode>(In)) {
5091 AllContants = false;
5096 if (cast<ConstantSDNode>(In)->getZExtValue())
5097 Immediate |= (1ULL << idx);
5099 if (In != Op.getOperand(0))
5104 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5105 DAG.getConstant(Immediate, MVT::i16));
5106 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5107 DAG.getIntPtrConstant(0));
5110 if (NumNonConsts == 1 && NonConstIdx != 0) {
5113 SDValue VecAsImm = DAG.getConstant(Immediate,
5114 MVT::getIntegerVT(VT.getSizeInBits()));
5115 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5118 DstVec = DAG.getUNDEF(VT);
5119 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5120 Op.getOperand(NonConstIdx),
5121 DAG.getIntPtrConstant(NonConstIdx));
5123 if (!IsSplat && (NonConstIdx != 0))
5124 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5125 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5128 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5129 DAG.getConstant(-1, SelectVT),
5130 DAG.getConstant(0, SelectVT));
5132 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5133 DAG.getConstant((Immediate | 1), SelectVT),
5134 DAG.getConstant(Immediate, SelectVT));
5135 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5138 /// \brief Return true if \p N implements a horizontal binop and return the
5139 /// operands for the horizontal binop into V0 and V1.
5141 /// This is a helper function of PerformBUILD_VECTORCombine.
5142 /// This function checks that the build_vector \p N in input implements a
5143 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5144 /// operation to match.
5145 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5146 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5147 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5150 /// This function only analyzes elements of \p N whose indices are
5151 /// in range [BaseIdx, LastIdx).
5152 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5154 unsigned BaseIdx, unsigned LastIdx,
5155 SDValue &V0, SDValue &V1) {
5156 EVT VT = N->getValueType(0);
5158 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5159 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5160 "Invalid Vector in input!");
5162 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5163 bool CanFold = true;
5164 unsigned ExpectedVExtractIdx = BaseIdx;
5165 unsigned NumElts = LastIdx - BaseIdx;
5166 V0 = DAG.getUNDEF(VT);
5167 V1 = DAG.getUNDEF(VT);
5169 // Check if N implements a horizontal binop.
5170 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5171 SDValue Op = N->getOperand(i + BaseIdx);
5174 if (Op->getOpcode() == ISD::UNDEF) {
5175 // Update the expected vector extract index.
5176 if (i * 2 == NumElts)
5177 ExpectedVExtractIdx = BaseIdx;
5178 ExpectedVExtractIdx += 2;
5182 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5187 SDValue Op0 = Op.getOperand(0);
5188 SDValue Op1 = Op.getOperand(1);
5190 // Try to match the following pattern:
5191 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5192 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5193 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5194 Op0.getOperand(0) == Op1.getOperand(0) &&
5195 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5196 isa<ConstantSDNode>(Op1.getOperand(1)));
5200 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5201 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5203 if (i * 2 < NumElts) {
5204 if (V0.getOpcode() == ISD::UNDEF)
5205 V0 = Op0.getOperand(0);
5207 if (V1.getOpcode() == ISD::UNDEF)
5208 V1 = Op0.getOperand(0);
5209 if (i * 2 == NumElts)
5210 ExpectedVExtractIdx = BaseIdx;
5213 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5214 if (I0 == ExpectedVExtractIdx)
5215 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5216 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5217 // Try to match the following dag sequence:
5218 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5219 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5223 ExpectedVExtractIdx += 2;
5229 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5230 /// a concat_vector.
5232 /// This is a helper function of PerformBUILD_VECTORCombine.
5233 /// This function expects two 256-bit vectors called V0 and V1.
5234 /// At first, each vector is split into two separate 128-bit vectors.
5235 /// Then, the resulting 128-bit vectors are used to implement two
5236 /// horizontal binary operations.
5238 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5240 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5241 /// the two new horizontal binop.
5242 /// When Mode is set, the first horizontal binop dag node would take as input
5243 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5244 /// horizontal binop dag node would take as input the lower 128-bit of V1
5245 /// and the upper 128-bit of V1.
5247 /// HADD V0_LO, V0_HI
5248 /// HADD V1_LO, V1_HI
5250 /// Otherwise, the first horizontal binop dag node takes as input the lower
5251 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5252 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5254 /// HADD V0_LO, V1_LO
5255 /// HADD V0_HI, V1_HI
5257 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5258 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5259 /// the upper 128-bits of the result.
5260 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5261 SDLoc DL, SelectionDAG &DAG,
5262 unsigned X86Opcode, bool Mode,
5263 bool isUndefLO, bool isUndefHI) {
5264 EVT VT = V0.getValueType();
5265 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5266 "Invalid nodes in input!");
5268 unsigned NumElts = VT.getVectorNumElements();
5269 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5270 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5271 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5272 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5273 EVT NewVT = V0_LO.getValueType();
5275 SDValue LO = DAG.getUNDEF(NewVT);
5276 SDValue HI = DAG.getUNDEF(NewVT);
5279 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5280 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5281 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5282 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5283 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5285 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5286 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5287 V1_LO->getOpcode() != ISD::UNDEF))
5288 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5290 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5291 V1_HI->getOpcode() != ISD::UNDEF))
5292 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5295 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5298 /// \brief Try to fold a build_vector that performs an 'addsub' into the
5299 /// sequence of 'vadd + vsub + blendi'.
5300 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
5301 const X86Subtarget *Subtarget) {
5303 EVT VT = BV->getValueType(0);
5304 unsigned NumElts = VT.getVectorNumElements();
5305 SDValue InVec0 = DAG.getUNDEF(VT);
5306 SDValue InVec1 = DAG.getUNDEF(VT);
5308 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5309 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5311 // Odd-numbered elements in the input build vector are obtained from
5312 // adding two integer/float elements.
5313 // Even-numbered elements in the input build vector are obtained from
5314 // subtracting two integer/float elements.
5315 unsigned ExpectedOpcode = ISD::FSUB;
5316 unsigned NextExpectedOpcode = ISD::FADD;
5317 bool AddFound = false;
5318 bool SubFound = false;
5320 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5321 SDValue Op = BV->getOperand(i);
5323 // Skip 'undef' values.
5324 unsigned Opcode = Op.getOpcode();
5325 if (Opcode == ISD::UNDEF) {
5326 std::swap(ExpectedOpcode, NextExpectedOpcode);
5330 // Early exit if we found an unexpected opcode.
5331 if (Opcode != ExpectedOpcode)
5334 SDValue Op0 = Op.getOperand(0);
5335 SDValue Op1 = Op.getOperand(1);
5337 // Try to match the following pattern:
5338 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5339 // Early exit if we cannot match that sequence.
5340 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5341 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5342 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5343 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5344 Op0.getOperand(1) != Op1.getOperand(1))
5347 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5351 // We found a valid add/sub node. Update the information accordingly.
5357 // Update InVec0 and InVec1.
5358 if (InVec0.getOpcode() == ISD::UNDEF)
5359 InVec0 = Op0.getOperand(0);
5360 if (InVec1.getOpcode() == ISD::UNDEF)
5361 InVec1 = Op1.getOperand(0);
5363 // Make sure that operands in input to each add/sub node always
5364 // come from a same pair of vectors.
5365 if (InVec0 != Op0.getOperand(0)) {
5366 if (ExpectedOpcode == ISD::FSUB)
5369 // FADD is commutable. Try to commute the operands
5370 // and then test again.
5371 std::swap(Op0, Op1);
5372 if (InVec0 != Op0.getOperand(0))
5376 if (InVec1 != Op1.getOperand(0))
5379 // Update the pair of expected opcodes.
5380 std::swap(ExpectedOpcode, NextExpectedOpcode);
5383 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5384 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5385 InVec1.getOpcode() != ISD::UNDEF)
5386 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5391 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
5392 const X86Subtarget *Subtarget) {
5394 EVT VT = N->getValueType(0);
5395 unsigned NumElts = VT.getVectorNumElements();
5396 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
5397 SDValue InVec0, InVec1;
5399 // Try to match an ADDSUB.
5400 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
5401 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
5402 SDValue Value = matchAddSub(BV, DAG, Subtarget);
5403 if (Value.getNode())
5407 // Try to match horizontal ADD/SUB.
5408 unsigned NumUndefsLO = 0;
5409 unsigned NumUndefsHI = 0;
5410 unsigned Half = NumElts/2;
5412 // Count the number of UNDEF operands in the build_vector in input.
5413 for (unsigned i = 0, e = Half; i != e; ++i)
5414 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5417 for (unsigned i = Half, e = NumElts; i != e; ++i)
5418 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5421 // Early exit if this is either a build_vector of all UNDEFs or all the
5422 // operands but one are UNDEF.
5423 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5426 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5427 // Try to match an SSE3 float HADD/HSUB.
5428 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5429 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5431 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5432 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5433 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5434 // Try to match an SSSE3 integer HADD/HSUB.
5435 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5436 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5438 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5439 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5442 if (!Subtarget->hasAVX())
5445 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5446 // Try to match an AVX horizontal add/sub of packed single/double
5447 // precision floating point values from 256-bit vectors.
5448 SDValue InVec2, InVec3;
5449 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5450 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5451 ((InVec0.getOpcode() == ISD::UNDEF ||
5452 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5453 ((InVec1.getOpcode() == ISD::UNDEF ||
5454 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5455 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5457 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5458 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5459 ((InVec0.getOpcode() == ISD::UNDEF ||
5460 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5461 ((InVec1.getOpcode() == ISD::UNDEF ||
5462 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5463 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5464 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5465 // Try to match an AVX2 horizontal add/sub of signed integers.
5466 SDValue InVec2, InVec3;
5468 bool CanFold = true;
5470 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5471 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5472 ((InVec0.getOpcode() == ISD::UNDEF ||
5473 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5474 ((InVec1.getOpcode() == ISD::UNDEF ||
5475 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5476 X86Opcode = X86ISD::HADD;
5477 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5478 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5479 ((InVec0.getOpcode() == ISD::UNDEF ||
5480 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5481 ((InVec1.getOpcode() == ISD::UNDEF ||
5482 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5483 X86Opcode = X86ISD::HSUB;
5488 // Fold this build_vector into a single horizontal add/sub.
5489 // Do this only if the target has AVX2.
5490 if (Subtarget->hasAVX2())
5491 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5493 // Do not try to expand this build_vector into a pair of horizontal
5494 // add/sub if we can emit a pair of scalar add/sub.
5495 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5498 // Convert this build_vector into a pair of horizontal binop followed by
5500 bool isUndefLO = NumUndefsLO == Half;
5501 bool isUndefHI = NumUndefsHI == Half;
5502 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5503 isUndefLO, isUndefHI);
5507 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5508 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5510 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5511 X86Opcode = X86ISD::HADD;
5512 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5513 X86Opcode = X86ISD::HSUB;
5514 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5515 X86Opcode = X86ISD::FHADD;
5516 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5517 X86Opcode = X86ISD::FHSUB;
5521 // Don't try to expand this build_vector into a pair of horizontal add/sub
5522 // if we can simply emit a pair of scalar add/sub.
5523 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5526 // Convert this build_vector into two horizontal add/sub followed by
5528 bool isUndefLO = NumUndefsLO == Half;
5529 bool isUndefHI = NumUndefsHI == Half;
5530 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5531 isUndefLO, isUndefHI);
5538 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5541 MVT VT = Op.getSimpleValueType();
5542 MVT ExtVT = VT.getVectorElementType();
5543 unsigned NumElems = Op.getNumOperands();
5545 // Generate vectors for predicate vectors.
5546 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5547 return LowerBUILD_VECTORvXi1(Op, DAG);
5549 // Vectors containing all zeros can be matched by pxor and xorps later
5550 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5551 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5552 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5553 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5556 return getZeroVector(VT, Subtarget, DAG, dl);
5559 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5560 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5561 // vpcmpeqd on 256-bit vectors.
5562 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5563 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5566 if (!VT.is512BitVector())
5567 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5570 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5571 if (Broadcast.getNode())
5574 unsigned EVTBits = ExtVT.getSizeInBits();
5576 unsigned NumZero = 0;
5577 unsigned NumNonZero = 0;
5578 unsigned NonZeros = 0;
5579 bool IsAllConstants = true;
5580 SmallSet<SDValue, 8> Values;
5581 for (unsigned i = 0; i < NumElems; ++i) {
5582 SDValue Elt = Op.getOperand(i);
5583 if (Elt.getOpcode() == ISD::UNDEF)
5586 if (Elt.getOpcode() != ISD::Constant &&
5587 Elt.getOpcode() != ISD::ConstantFP)
5588 IsAllConstants = false;
5589 if (X86::isZeroNode(Elt))
5592 NonZeros |= (1 << i);
5597 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5598 if (NumNonZero == 0)
5599 return DAG.getUNDEF(VT);
5601 // Special case for single non-zero, non-undef, element.
5602 if (NumNonZero == 1) {
5603 unsigned Idx = countTrailingZeros(NonZeros);
5604 SDValue Item = Op.getOperand(Idx);
5606 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5607 // the value are obviously zero, truncate the value to i32 and do the
5608 // insertion that way. Only do this if the value is non-constant or if the
5609 // value is a constant being inserted into element 0. It is cheaper to do
5610 // a constant pool load than it is to do a movd + shuffle.
5611 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5612 (!IsAllConstants || Idx == 0)) {
5613 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5615 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5616 EVT VecVT = MVT::v4i32;
5618 // Truncate the value (which may itself be a constant) to i32, and
5619 // convert it to a vector with movd (S2V+shuffle to zero extend).
5620 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5621 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5623 ISD::BITCAST, dl, VT,
5624 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5628 // If we have a constant or non-constant insertion into the low element of
5629 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5630 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5631 // depending on what the source datatype is.
5634 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5636 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5637 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5638 if (VT.is256BitVector() || VT.is512BitVector()) {
5639 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5640 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5641 Item, DAG.getIntPtrConstant(0));
5643 assert(VT.is128BitVector() && "Expected an SSE value type!");
5644 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5645 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5646 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5649 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5650 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5651 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5652 if (VT.is256BitVector()) {
5653 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5654 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5656 assert(VT.is128BitVector() && "Expected an SSE value type!");
5657 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5659 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5663 // Is it a vector logical left shift?
5664 if (NumElems == 2 && Idx == 1 &&
5665 X86::isZeroNode(Op.getOperand(0)) &&
5666 !X86::isZeroNode(Op.getOperand(1))) {
5667 unsigned NumBits = VT.getSizeInBits();
5668 return getVShift(true, VT,
5669 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5670 VT, Op.getOperand(1)),
5671 NumBits/2, DAG, *this, dl);
5674 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5677 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5678 // is a non-constant being inserted into an element other than the low one,
5679 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5680 // movd/movss) to move this into the low element, then shuffle it into
5682 if (EVTBits == 32) {
5683 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5684 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5688 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5689 if (Values.size() == 1) {
5690 if (EVTBits == 32) {
5691 // Instead of a shuffle like this:
5692 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5693 // Check if it's possible to issue this instead.
5694 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5695 unsigned Idx = countTrailingZeros(NonZeros);
5696 SDValue Item = Op.getOperand(Idx);
5697 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5698 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5703 // A vector full of immediates; various special cases are already
5704 // handled, so this is best done with a single constant-pool load.
5708 // For AVX-length vectors, see if we can use a vector load to get all of the
5709 // elements, otherwise build the individual 128-bit pieces and use
5710 // shuffles to put them in place.
5711 if (VT.is256BitVector() || VT.is512BitVector()) {
5712 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5714 // Check for a build vector of consecutive loads.
5715 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5718 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5720 // Build both the lower and upper subvector.
5721 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5722 makeArrayRef(&V[0], NumElems/2));
5723 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5724 makeArrayRef(&V[NumElems / 2], NumElems/2));
5726 // Recreate the wider vector with the lower and upper part.
5727 if (VT.is256BitVector())
5728 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5729 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5732 // Let legalizer expand 2-wide build_vectors.
5733 if (EVTBits == 64) {
5734 if (NumNonZero == 1) {
5735 // One half is zero or undef.
5736 unsigned Idx = countTrailingZeros(NonZeros);
5737 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5738 Op.getOperand(Idx));
5739 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5744 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5745 if (EVTBits == 8 && NumElems == 16) {
5746 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5748 if (V.getNode()) return V;
5751 if (EVTBits == 16 && NumElems == 8) {
5752 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5754 if (V.getNode()) return V;
5757 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5758 if (EVTBits == 32 && NumElems == 4) {
5759 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
5764 // If element VT is == 32 bits, turn it into a number of shuffles.
5765 SmallVector<SDValue, 8> V(NumElems);
5766 if (NumElems == 4 && NumZero > 0) {
5767 for (unsigned i = 0; i < 4; ++i) {
5768 bool isZero = !(NonZeros & (1 << i));
5770 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5772 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5775 for (unsigned i = 0; i < 2; ++i) {
5776 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5779 V[i] = V[i*2]; // Must be a zero vector.
5782 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5785 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5788 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5793 bool Reverse1 = (NonZeros & 0x3) == 2;
5794 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5798 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5799 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5801 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5804 if (Values.size() > 1 && VT.is128BitVector()) {
5805 // Check for a build vector of consecutive loads.
5806 for (unsigned i = 0; i < NumElems; ++i)
5807 V[i] = Op.getOperand(i);
5809 // Check for elements which are consecutive loads.
5810 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
5814 // Check for a build vector from mostly shuffle plus few inserting.
5815 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5819 // For SSE 4.1, use insertps to put the high elements into the low element.
5820 if (Subtarget->hasSSE41()) {
5822 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5823 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5825 Result = DAG.getUNDEF(VT);
5827 for (unsigned i = 1; i < NumElems; ++i) {
5828 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5829 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5830 Op.getOperand(i), DAG.getIntPtrConstant(i));
5835 // Otherwise, expand into a number of unpckl*, start by extending each of
5836 // our (non-undef) elements to the full vector width with the element in the
5837 // bottom slot of the vector (which generates no code for SSE).
5838 for (unsigned i = 0; i < NumElems; ++i) {
5839 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5840 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5842 V[i] = DAG.getUNDEF(VT);
5845 // Next, we iteratively mix elements, e.g. for v4f32:
5846 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5847 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5848 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5849 unsigned EltStride = NumElems >> 1;
5850 while (EltStride != 0) {
5851 for (unsigned i = 0; i < EltStride; ++i) {
5852 // If V[i+EltStride] is undef and this is the first round of mixing,
5853 // then it is safe to just drop this shuffle: V[i] is already in the
5854 // right place, the one element (since it's the first round) being
5855 // inserted as undef can be dropped. This isn't safe for successive
5856 // rounds because they will permute elements within both vectors.
5857 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5858 EltStride == NumElems/2)
5861 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5870 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5871 // to create 256-bit vectors from two other 128-bit ones.
5872 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5874 MVT ResVT = Op.getSimpleValueType();
5876 assert((ResVT.is256BitVector() ||
5877 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5879 SDValue V1 = Op.getOperand(0);
5880 SDValue V2 = Op.getOperand(1);
5881 unsigned NumElems = ResVT.getVectorNumElements();
5882 if(ResVT.is256BitVector())
5883 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5885 if (Op.getNumOperands() == 4) {
5886 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5887 ResVT.getVectorNumElements()/2);
5888 SDValue V3 = Op.getOperand(2);
5889 SDValue V4 = Op.getOperand(3);
5890 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
5891 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
5893 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5896 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5897 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
5898 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
5899 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
5900 Op.getNumOperands() == 4)));
5902 // AVX can use the vinsertf128 instruction to create 256-bit vectors
5903 // from two other 128-bit ones.
5905 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
5906 return LowerAVXCONCAT_VECTORS(Op, DAG);
5910 //===----------------------------------------------------------------------===//
5911 // Vector shuffle lowering
5913 // This is an experimental code path for lowering vector shuffles on x86. It is
5914 // designed to handle arbitrary vector shuffles and blends, gracefully
5915 // degrading performance as necessary. It works hard to recognize idiomatic
5916 // shuffles and lower them to optimal instruction patterns without leaving
5917 // a framework that allows reasonably efficient handling of all vector shuffle
5919 //===----------------------------------------------------------------------===//
5921 /// \brief Tiny helper function to identify a no-op mask.
5923 /// This is a somewhat boring predicate function. It checks whether the mask
5924 /// array input, which is assumed to be a single-input shuffle mask of the kind
5925 /// used by the X86 shuffle instructions (not a fully general
5926 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
5927 /// in-place shuffle are 'no-op's.
5928 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
5929 for (int i = 0, Size = Mask.size(); i < Size; ++i)
5930 if (Mask[i] != -1 && Mask[i] != i)
5935 /// \brief Helper function to classify a mask as a single-input mask.
5937 /// This isn't a generic single-input test because in the vector shuffle
5938 /// lowering we canonicalize single inputs to be the first input operand. This
5939 /// means we can more quickly test for a single input by only checking whether
5940 /// an input from the second operand exists. We also assume that the size of
5941 /// mask corresponds to the size of the input vectors which isn't true in the
5942 /// fully general case.
5943 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
5945 if (M >= (int)Mask.size())
5950 /// \brief Test whether there are elements crossing 128-bit lanes in this
5953 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
5954 /// and we routinely test for these.
5955 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
5956 int LaneSize = 128 / VT.getScalarSizeInBits();
5957 int Size = Mask.size();
5958 for (int i = 0; i < Size; ++i)
5959 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
5964 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
5966 /// This checks a shuffle mask to see if it is performing the same
5967 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
5968 /// that it is also not lane-crossing. It may however involve a blend from the
5969 /// same lane of a second vector.
5971 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
5972 /// non-trivial to compute in the face of undef lanes. The representation is
5973 /// *not* suitable for use with existing 128-bit shuffles as it will contain
5974 /// entries from both V1 and V2 inputs to the wider mask.
5976 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
5977 SmallVectorImpl<int> &RepeatedMask) {
5978 int LaneSize = 128 / VT.getScalarSizeInBits();
5979 RepeatedMask.resize(LaneSize, -1);
5980 int Size = Mask.size();
5981 for (int i = 0; i < Size; ++i) {
5984 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
5985 // This entry crosses lanes, so there is no way to model this shuffle.
5988 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
5989 if (RepeatedMask[i % LaneSize] == -1)
5990 // This is the first non-undef entry in this slot of a 128-bit lane.
5991 RepeatedMask[i % LaneSize] =
5992 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
5993 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
5994 // Found a mismatch with the repeated mask.
6000 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6003 /// This is a fast way to test a shuffle mask against a fixed pattern:
6005 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6007 /// It returns true if the mask is exactly as wide as the argument list, and
6008 /// each element of the mask is either -1 (signifying undef) or the value given
6009 /// in the argument.
6010 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6011 ArrayRef<int> ExpectedMask) {
6012 if (Mask.size() != ExpectedMask.size())
6015 int Size = Mask.size();
6017 // If the values are build vectors, we can look through them to find
6018 // equivalent inputs that make the shuffles equivalent.
6019 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6020 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6022 for (int i = 0; i < Size; ++i)
6023 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6024 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6025 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6026 if (!MaskBV || !ExpectedBV ||
6027 MaskBV->getOperand(Mask[i] % Size) !=
6028 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6035 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6037 /// This helper function produces an 8-bit shuffle immediate corresponding to
6038 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6039 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6042 /// NB: We rely heavily on "undef" masks preserving the input lane.
6043 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6044 SelectionDAG &DAG) {
6045 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6046 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6047 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6048 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6049 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6052 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6053 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6054 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6055 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6056 return DAG.getConstant(Imm, MVT::i8);
6059 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6061 /// This is used as a fallback approach when first class blend instructions are
6062 /// unavailable. Currently it is only suitable for integer vectors, but could
6063 /// be generalized for floating point vectors if desirable.
6064 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6065 SDValue V2, ArrayRef<int> Mask,
6066 SelectionDAG &DAG) {
6067 assert(VT.isInteger() && "Only supports integer vector types!");
6068 MVT EltVT = VT.getScalarType();
6069 int NumEltBits = EltVT.getSizeInBits();
6070 SDValue Zero = DAG.getConstant(0, EltVT);
6071 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), EltVT);
6072 SmallVector<SDValue, 16> MaskOps;
6073 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6074 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6075 return SDValue(); // Shuffled input!
6076 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6079 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6080 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6081 // We have to cast V2 around.
6082 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6083 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6084 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6085 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6086 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6087 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6090 /// \brief Try to emit a blend instruction for a shuffle.
6092 /// This doesn't do any checks for the availability of instructions for blending
6093 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6094 /// be matched in the backend with the type given. What it does check for is
6095 /// that the shuffle mask is in fact a blend.
6096 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6097 SDValue V2, ArrayRef<int> Mask,
6098 const X86Subtarget *Subtarget,
6099 SelectionDAG &DAG) {
6100 unsigned BlendMask = 0;
6101 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6102 if (Mask[i] >= Size) {
6103 if (Mask[i] != i + Size)
6104 return SDValue(); // Shuffled V2 input!
6105 BlendMask |= 1u << i;
6108 if (Mask[i] >= 0 && Mask[i] != i)
6109 return SDValue(); // Shuffled V1 input!
6111 switch (VT.SimpleTy) {
6116 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6117 DAG.getConstant(BlendMask, MVT::i8));
6121 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6125 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6126 // that instruction.
6127 if (Subtarget->hasAVX2()) {
6128 // Scale the blend by the number of 32-bit dwords per element.
6129 int Scale = VT.getScalarSizeInBits() / 32;
6131 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6132 if (Mask[i] >= Size)
6133 for (int j = 0; j < Scale; ++j)
6134 BlendMask |= 1u << (i * Scale + j);
6136 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6137 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6138 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6139 return DAG.getNode(ISD::BITCAST, DL, VT,
6140 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6141 DAG.getConstant(BlendMask, MVT::i8)));
6145 // For integer shuffles we need to expand the mask and cast the inputs to
6146 // v8i16s prior to blending.
6147 int Scale = 8 / VT.getVectorNumElements();
6149 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6150 if (Mask[i] >= Size)
6151 for (int j = 0; j < Scale; ++j)
6152 BlendMask |= 1u << (i * Scale + j);
6154 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6155 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6156 return DAG.getNode(ISD::BITCAST, DL, VT,
6157 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6158 DAG.getConstant(BlendMask, MVT::i8)));
6162 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6163 SmallVector<int, 8> RepeatedMask;
6164 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6165 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6166 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6168 for (int i = 0; i < 8; ++i)
6169 if (RepeatedMask[i] >= 16)
6170 BlendMask |= 1u << i;
6171 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6172 DAG.getConstant(BlendMask, MVT::i8));
6178 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6179 "256-bit byte-blends require AVX2 support!");
6181 // Scale the blend by the number of bytes per element.
6182 int Scale = VT.getScalarSizeInBits() / 8;
6184 // This form of blend is always done on bytes. Compute the byte vector
6186 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6188 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6189 // mix of LLVM's code generator and the x86 backend. We tell the code
6190 // generator that boolean values in the elements of an x86 vector register
6191 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6192 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6193 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6194 // of the element (the remaining are ignored) and 0 in that high bit would
6195 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6196 // the LLVM model for boolean values in vector elements gets the relevant
6197 // bit set, it is set backwards and over constrained relative to x86's
6199 SmallVector<SDValue, 32> VSELECTMask;
6200 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6201 for (int j = 0; j < Scale; ++j)
6202 VSELECTMask.push_back(
6203 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6204 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));
6206 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6207 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6209 ISD::BITCAST, DL, VT,
6210 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6211 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6216 llvm_unreachable("Not a supported integer vector type!");
6220 /// \brief Try to lower as a blend of elements from two inputs followed by
6221 /// a single-input permutation.
6223 /// This matches the pattern where we can blend elements from two inputs and
6224 /// then reduce the shuffle to a single-input permutation.
6225 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6228 SelectionDAG &DAG) {
6229 // We build up the blend mask while checking whether a blend is a viable way
6230 // to reduce the shuffle.
6231 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6232 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6234 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6238 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6240 if (BlendMask[Mask[i] % Size] == -1)
6241 BlendMask[Mask[i] % Size] = Mask[i];
6242 else if (BlendMask[Mask[i] % Size] != Mask[i])
6243 return SDValue(); // Can't blend in the needed input!
6245 PermuteMask[i] = Mask[i] % Size;
6248 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6249 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6252 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6253 /// blends and permutes.
6255 /// This matches the extremely common pattern for handling combined
6256 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6257 /// operations. It will try to pick the best arrangement of shuffles and
6259 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6263 SelectionDAG &DAG) {
6264 // Shuffle the input elements into the desired positions in V1 and V2 and
6265 // blend them together.
6266 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6267 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6268 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6269 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6270 if (Mask[i] >= 0 && Mask[i] < Size) {
6271 V1Mask[i] = Mask[i];
6273 } else if (Mask[i] >= Size) {
6274 V2Mask[i] = Mask[i] - Size;
6275 BlendMask[i] = i + Size;
6278 // Try to lower with the simpler initial blend strategy unless one of the
6279 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6280 // shuffle may be able to fold with a load or other benefit. However, when
6281 // we'll have to do 2x as many shuffles in order to achieve this, blending
6282 // first is a better strategy.
6283 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6284 if (SDValue BlendPerm =
6285 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6288 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6289 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6290 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6293 /// \brief Try to lower a vector shuffle as a byte rotation.
6295 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6296 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6297 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6298 /// try to generically lower a vector shuffle through such an pattern. It
6299 /// does not check for the profitability of lowering either as PALIGNR or
6300 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6301 /// This matches shuffle vectors that look like:
6303 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6305 /// Essentially it concatenates V1 and V2, shifts right by some number of
6306 /// elements, and takes the low elements as the result. Note that while this is
6307 /// specified as a *right shift* because x86 is little-endian, it is a *left
6308 /// rotate* of the vector lanes.
6309 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6312 const X86Subtarget *Subtarget,
6313 SelectionDAG &DAG) {
6314 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6316 int NumElts = Mask.size();
6317 int NumLanes = VT.getSizeInBits() / 128;
6318 int NumLaneElts = NumElts / NumLanes;
6320 // We need to detect various ways of spelling a rotation:
6321 // [11, 12, 13, 14, 15, 0, 1, 2]
6322 // [-1, 12, 13, 14, -1, -1, 1, -1]
6323 // [-1, -1, -1, -1, -1, -1, 1, 2]
6324 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6325 // [-1, 4, 5, 6, -1, -1, 9, -1]
6326 // [-1, 4, 5, 6, -1, -1, -1, -1]
6329 for (int l = 0; l < NumElts; l += NumLaneElts) {
6330 for (int i = 0; i < NumLaneElts; ++i) {
6331 if (Mask[l + i] == -1)
6333 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6335 // Get the mod-Size index and lane correct it.
6336 int LaneIdx = (Mask[l + i] % NumElts) - l;
6337 // Make sure it was in this lane.
6338 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6341 // Determine where a rotated vector would have started.
6342 int StartIdx = i - LaneIdx;
6344 // The identity rotation isn't interesting, stop.
6347 // If we found the tail of a vector the rotation must be the missing
6348 // front. If we found the head of a vector, it must be how much of the
6350 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6353 Rotation = CandidateRotation;
6354 else if (Rotation != CandidateRotation)
6355 // The rotations don't match, so we can't match this mask.
6358 // Compute which value this mask is pointing at.
6359 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6361 // Compute which of the two target values this index should be assigned
6362 // to. This reflects whether the high elements are remaining or the low
6363 // elements are remaining.
6364 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6366 // Either set up this value if we've not encountered it before, or check
6367 // that it remains consistent.
6370 else if (TargetV != MaskV)
6371 // This may be a rotation, but it pulls from the inputs in some
6372 // unsupported interleaving.
6377 // Check that we successfully analyzed the mask, and normalize the results.
6378 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6379 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6385 // The actual rotate instruction rotates bytes, so we need to scale the
6386 // rotation based on how many bytes are in the vector lane.
6387 int Scale = 16 / NumLaneElts;
6389 // SSSE3 targets can use the palignr instruction.
6390 if (Subtarget->hasSSSE3()) {
6391 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6392 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6393 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6394 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6396 return DAG.getNode(ISD::BITCAST, DL, VT,
6397 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6398 DAG.getConstant(Rotation * Scale, MVT::i8)));
6401 assert(VT.getSizeInBits() == 128 &&
6402 "Rotate-based lowering only supports 128-bit lowering!");
6403 assert(Mask.size() <= 16 &&
6404 "Can shuffle at most 16 bytes in a 128-bit vector!");
6406 // Default SSE2 implementation
6407 int LoByteShift = 16 - Rotation * Scale;
6408 int HiByteShift = Rotation * Scale;
6410 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6411 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6412 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6414 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6415 DAG.getConstant(LoByteShift, MVT::i8));
6416 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6417 DAG.getConstant(HiByteShift, MVT::i8));
6418 return DAG.getNode(ISD::BITCAST, DL, VT,
6419 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6422 /// \brief Compute whether each element of a shuffle is zeroable.
6424 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6425 /// Either it is an undef element in the shuffle mask, the element of the input
6426 /// referenced is undef, or the element of the input referenced is known to be
6427 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6428 /// as many lanes with this technique as possible to simplify the remaining
6430 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6431 SDValue V1, SDValue V2) {
6432 SmallBitVector Zeroable(Mask.size(), false);
6434 while (V1.getOpcode() == ISD::BITCAST)
6435 V1 = V1->getOperand(0);
6436 while (V2.getOpcode() == ISD::BITCAST)
6437 V2 = V2->getOperand(0);
6439 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6440 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6442 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6444 // Handle the easy cases.
6445 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6450 // If this is an index into a build_vector node (which has the same number
6451 // of elements), dig out the input value and use it.
6452 SDValue V = M < Size ? V1 : V2;
6453 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6456 SDValue Input = V.getOperand(M % Size);
6457 // The UNDEF opcode check really should be dead code here, but not quite
6458 // worth asserting on (it isn't invalid, just unexpected).
6459 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6466 /// \brief Try to emit a bitmask instruction for a shuffle.
6468 /// This handles cases where we can model a blend exactly as a bitmask due to
6469 /// one of the inputs being zeroable.
6470 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6471 SDValue V2, ArrayRef<int> Mask,
6472 SelectionDAG &DAG) {
6473 MVT EltVT = VT.getScalarType();
6474 int NumEltBits = EltVT.getSizeInBits();
6475 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6476 SDValue Zero = DAG.getConstant(0, IntEltVT);
6477 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);
6478 if (EltVT.isFloatingPoint()) {
6479 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6480 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6482 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6483 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6485 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6488 if (Mask[i] % Size != i)
6489 return SDValue(); // Not a blend.
6491 V = Mask[i] < Size ? V1 : V2;
6492 else if (V != (Mask[i] < Size ? V1 : V2))
6493 return SDValue(); // Can only let one input through the mask.
6495 VMaskOps[i] = AllOnes;
6498 return SDValue(); // No non-zeroable elements!
6500 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6501 V = DAG.getNode(VT.isFloatingPoint()
6502 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6507 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6509 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6510 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6511 /// matches elements from one of the input vectors shuffled to the left or
6512 /// right with zeroable elements 'shifted in'. It handles both the strictly
6513 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6516 /// PSHL : (little-endian) left bit shift.
6517 /// [ zz, 0, zz, 2 ]
6518 /// [ -1, 4, zz, -1 ]
6519 /// PSRL : (little-endian) right bit shift.
6521 /// [ -1, -1, 7, zz]
6522 /// PSLLDQ : (little-endian) left byte shift
6523 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6524 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6525 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6526 /// PSRLDQ : (little-endian) right byte shift
6527 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6528 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6529 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6530 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6531 SDValue V2, ArrayRef<int> Mask,
6532 SelectionDAG &DAG) {
6533 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6535 int Size = Mask.size();
6536 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6538 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6539 for (int i = 0; i < Size; i += Scale)
6540 for (int j = 0; j < Shift; ++j)
6541 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6547 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6548 for (int i = 0; i != Size; i += Scale) {
6549 unsigned Pos = Left ? i + Shift : i;
6550 unsigned Low = Left ? i : i + Shift;
6551 unsigned Len = Scale - Shift;
6552 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6553 Low + (V == V1 ? 0 : Size)))
6557 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6558 bool ByteShift = ShiftEltBits > 64;
6559 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6560 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6561 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6563 // Normalize the scale for byte shifts to still produce an i64 element
6565 Scale = ByteShift ? Scale / 2 : Scale;
6567 // We need to round trip through the appropriate type for the shift.
6568 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6569 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6570 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6571 "Illegal integer vector type");
6572 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6574 V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8));
6575 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6578 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6579 // keep doubling the size of the integer elements up to that. We can
6580 // then shift the elements of the integer vector by whole multiples of
6581 // their width within the elements of the larger integer vector. Test each
6582 // multiple to see if we can find a match with the moved element indices
6583 // and that the shifted in elements are all zeroable.
6584 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6585 for (int Shift = 1; Shift != Scale; ++Shift)
6586 for (bool Left : {true, false})
6587 if (CheckZeros(Shift, Scale, Left))
6588 for (SDValue V : {V1, V2})
6589 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6596 /// \brief Lower a vector shuffle as a zero or any extension.
6598 /// Given a specific number of elements, element bit width, and extension
6599 /// stride, produce either a zero or any extension based on the available
6600 /// features of the subtarget.
6601 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6602 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6603 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6604 assert(Scale > 1 && "Need a scale to extend.");
6605 int NumElements = VT.getVectorNumElements();
6606 int EltBits = VT.getScalarSizeInBits();
6607 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6608 "Only 8, 16, and 32 bit elements can be extended.");
6609 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6611 // Found a valid zext mask! Try various lowering strategies based on the
6612 // input type and available ISA extensions.
6613 if (Subtarget->hasSSE41()) {
6614 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6615 NumElements / Scale);
6616 return DAG.getNode(ISD::BITCAST, DL, VT,
6617 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6620 // For any extends we can cheat for larger element sizes and use shuffle
6621 // instructions that can fold with a load and/or copy.
6622 if (AnyExt && EltBits == 32) {
6623 int PSHUFDMask[4] = {0, -1, 1, -1};
6625 ISD::BITCAST, DL, VT,
6626 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6627 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6628 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
6630 if (AnyExt && EltBits == 16 && Scale > 2) {
6631 int PSHUFDMask[4] = {0, -1, 0, -1};
6632 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6633 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6634 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
6635 int PSHUFHWMask[4] = {1, -1, -1, -1};
6637 ISD::BITCAST, DL, VT,
6638 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6639 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6640 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
6643 // If this would require more than 2 unpack instructions to expand, use
6644 // pshufb when available. We can only use more than 2 unpack instructions
6645 // when zero extending i8 elements which also makes it easier to use pshufb.
6646 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6647 assert(NumElements == 16 && "Unexpected byte vector width!");
6648 SDValue PSHUFBMask[16];
6649 for (int i = 0; i < 16; ++i)
6651 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
6652 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6653 return DAG.getNode(ISD::BITCAST, DL, VT,
6654 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6655 DAG.getNode(ISD::BUILD_VECTOR, DL,
6656 MVT::v16i8, PSHUFBMask)));
6659 // Otherwise emit a sequence of unpacks.
6661 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6662 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6663 : getZeroVector(InputVT, Subtarget, DAG, DL);
6664 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6665 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6669 } while (Scale > 1);
6670 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6673 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6675 /// This routine will try to do everything in its power to cleverly lower
6676 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6677 /// check for the profitability of this lowering, it tries to aggressively
6678 /// match this pattern. It will use all of the micro-architectural details it
6679 /// can to emit an efficient lowering. It handles both blends with all-zero
6680 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6681 /// masking out later).
6683 /// The reason we have dedicated lowering for zext-style shuffles is that they
6684 /// are both incredibly common and often quite performance sensitive.
6685 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6686 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6687 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6688 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6690 int Bits = VT.getSizeInBits();
6691 int NumElements = VT.getVectorNumElements();
6692 assert(VT.getScalarSizeInBits() <= 32 &&
6693 "Exceeds 32-bit integer zero extension limit");
6694 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6696 // Define a helper function to check a particular ext-scale and lower to it if
6698 auto Lower = [&](int Scale) -> SDValue {
6701 for (int i = 0; i < NumElements; ++i) {
6703 continue; // Valid anywhere but doesn't tell us anything.
6704 if (i % Scale != 0) {
6705 // Each of the extended elements need to be zeroable.
6709 // We no longer are in the anyext case.
6714 // Each of the base elements needs to be consecutive indices into the
6715 // same input vector.
6716 SDValue V = Mask[i] < NumElements ? V1 : V2;
6719 else if (InputV != V)
6720 return SDValue(); // Flip-flopping inputs.
6722 if (Mask[i] % NumElements != i / Scale)
6723 return SDValue(); // Non-consecutive strided elements.
6726 // If we fail to find an input, we have a zero-shuffle which should always
6727 // have already been handled.
6728 // FIXME: Maybe handle this here in case during blending we end up with one?
6732 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6733 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6736 // The widest scale possible for extending is to a 64-bit integer.
6737 assert(Bits % 64 == 0 &&
6738 "The number of bits in a vector must be divisible by 64 on x86!");
6739 int NumExtElements = Bits / 64;
6741 // Each iteration, try extending the elements half as much, but into twice as
6743 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6744 assert(NumElements % NumExtElements == 0 &&
6745 "The input vector size must be divisible by the extended size.");
6746 if (SDValue V = Lower(NumElements / NumExtElements))
6750 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6754 // Returns one of the source operands if the shuffle can be reduced to a
6755 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6756 auto CanZExtLowHalf = [&]() {
6757 for (int i = NumElements / 2; i != NumElements; ++i)
6760 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6762 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6767 if (SDValue V = CanZExtLowHalf()) {
6768 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6769 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6770 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6773 // No viable ext lowering found.
6777 /// \brief Try to get a scalar value for a specific element of a vector.
6779 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6780 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6781 SelectionDAG &DAG) {
6782 MVT VT = V.getSimpleValueType();
6783 MVT EltVT = VT.getVectorElementType();
6784 while (V.getOpcode() == ISD::BITCAST)
6785 V = V.getOperand(0);
6786 // If the bitcasts shift the element size, we can't extract an equivalent
6788 MVT NewVT = V.getSimpleValueType();
6789 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6792 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6793 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
6794 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
6799 /// \brief Helper to test for a load that can be folded with x86 shuffles.
6801 /// This is particularly important because the set of instructions varies
6802 /// significantly based on whether the operand is a load or not.
6803 static bool isShuffleFoldableLoad(SDValue V) {
6804 while (V.getOpcode() == ISD::BITCAST)
6805 V = V.getOperand(0);
6807 return ISD::isNON_EXTLoad(V.getNode());
6810 /// \brief Try to lower insertion of a single element into a zero vector.
6812 /// This is a common pattern that we have especially efficient patterns to lower
6813 /// across all subtarget feature sets.
6814 static SDValue lowerVectorShuffleAsElementInsertion(
6815 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6816 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6817 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6819 MVT EltVT = VT.getVectorElementType();
6821 int V2Index = std::find_if(Mask.begin(), Mask.end(),
6822 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6824 bool IsV1Zeroable = true;
6825 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6826 if (i != V2Index && !Zeroable[i]) {
6827 IsV1Zeroable = false;
6831 // Check for a single input from a SCALAR_TO_VECTOR node.
6832 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
6833 // all the smarts here sunk into that routine. However, the current
6834 // lowering of BUILD_VECTOR makes that nearly impossible until the old
6835 // vector shuffle lowering is dead.
6836 if (SDValue V2S = getScalarValueForVectorElement(
6837 V2, Mask[V2Index] - Mask.size(), DAG)) {
6838 // We need to zext the scalar if it is smaller than an i32.
6839 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
6840 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
6841 // Using zext to expand a narrow element won't work for non-zero
6846 // Zero-extend directly to i32.
6848 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
6850 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
6851 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
6852 EltVT == MVT::i16) {
6853 // Either not inserting from the low element of the input or the input
6854 // element size is too small to use VZEXT_MOVL to clear the high bits.
6858 if (!IsV1Zeroable) {
6859 // If V1 can't be treated as a zero vector we have fewer options to lower
6860 // this. We can't support integer vectors or non-zero targets cheaply, and
6861 // the V1 elements can't be permuted in any way.
6862 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
6863 if (!VT.isFloatingPoint() || V2Index != 0)
6865 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
6866 V1Mask[V2Index] = -1;
6867 if (!isNoopShuffleMask(V1Mask))
6869 // This is essentially a special case blend operation, but if we have
6870 // general purpose blend operations, they are always faster. Bail and let
6871 // the rest of the lowering handle these as blends.
6872 if (Subtarget->hasSSE41())
6875 // Otherwise, use MOVSD or MOVSS.
6876 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
6877 "Only two types of floating point element types to handle!");
6878 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
6882 // This lowering only works for the low element with floating point vectors.
6883 if (VT.isFloatingPoint() && V2Index != 0)
6886 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
6888 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
6891 // If we have 4 or fewer lanes we can cheaply shuffle the element into
6892 // the desired position. Otherwise it is more efficient to do a vector
6893 // shift left. We know that we can do a vector shift left because all
6894 // the inputs are zero.
6895 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
6896 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
6897 V2Shuffle[V2Index] = 0;
6898 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
6900 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
6902 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
6904 V2Index * EltVT.getSizeInBits()/8,
6905 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
6906 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
6912 /// \brief Try to lower broadcast of a single element.
6914 /// For convenience, this code also bundles all of the subtarget feature set
6915 /// filtering. While a little annoying to re-dispatch on type here, there isn't
6916 /// a convenient way to factor it out.
6917 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
6919 const X86Subtarget *Subtarget,
6920 SelectionDAG &DAG) {
6921 if (!Subtarget->hasAVX())
6923 if (VT.isInteger() && !Subtarget->hasAVX2())
6926 // Check that the mask is a broadcast.
6927 int BroadcastIdx = -1;
6929 if (M >= 0 && BroadcastIdx == -1)
6931 else if (M >= 0 && M != BroadcastIdx)
6934 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
6935 "a sorted mask where the broadcast "
6938 // Go up the chain of (vector) values to try and find a scalar load that
6939 // we can combine with the broadcast.
6941 switch (V.getOpcode()) {
6942 case ISD::CONCAT_VECTORS: {
6943 int OperandSize = Mask.size() / V.getNumOperands();
6944 V = V.getOperand(BroadcastIdx / OperandSize);
6945 BroadcastIdx %= OperandSize;
6949 case ISD::INSERT_SUBVECTOR: {
6950 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
6951 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
6955 int BeginIdx = (int)ConstantIdx->getZExtValue();
6957 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
6958 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
6959 BroadcastIdx -= BeginIdx;
6970 // Check if this is a broadcast of a scalar. We special case lowering
6971 // for scalars so that we can more effectively fold with loads.
6972 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6973 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
6974 V = V.getOperand(BroadcastIdx);
6976 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
6978 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
6980 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
6981 // We can't broadcast from a vector register w/o AVX2, and we can only
6982 // broadcast from the zero-element of a vector register.
6986 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
6989 // Check for whether we can use INSERTPS to perform the shuffle. We only use
6990 // INSERTPS when the V1 elements are already in the correct locations
6991 // because otherwise we can just always use two SHUFPS instructions which
6992 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
6993 // perform INSERTPS if a single V1 element is out of place and all V2
6994 // elements are zeroable.
6995 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
6997 SelectionDAG &DAG) {
6998 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
6999 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7000 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7001 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7003 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7006 int V1DstIndex = -1;
7007 int V2DstIndex = -1;
7008 bool V1UsedInPlace = false;
7010 for (int i = 0; i < 4; ++i) {
7011 // Synthesize a zero mask from the zeroable elements (includes undefs).
7017 // Flag if we use any V1 inputs in place.
7019 V1UsedInPlace = true;
7023 // We can only insert a single non-zeroable element.
7024 if (V1DstIndex != -1 || V2DstIndex != -1)
7028 // V1 input out of place for insertion.
7031 // V2 input for insertion.
7036 // Don't bother if we have no (non-zeroable) element for insertion.
7037 if (V1DstIndex == -1 && V2DstIndex == -1)
7040 // Determine element insertion src/dst indices. The src index is from the
7041 // start of the inserted vector, not the start of the concatenated vector.
7042 unsigned V2SrcIndex = 0;
7043 if (V1DstIndex != -1) {
7044 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7045 // and don't use the original V2 at all.
7046 V2SrcIndex = Mask[V1DstIndex];
7047 V2DstIndex = V1DstIndex;
7050 V2SrcIndex = Mask[V2DstIndex] - 4;
7053 // If no V1 inputs are used in place, then the result is created only from
7054 // the zero mask and the V2 insertion - so remove V1 dependency.
7056 V1 = DAG.getUNDEF(MVT::v4f32);
7058 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7059 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7061 // Insert the V2 element into the desired position.
7063 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7064 DAG.getConstant(InsertPSMask, MVT::i8));
7067 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7068 /// UNPCK instruction.
7070 /// This specifically targets cases where we end up with alternating between
7071 /// the two inputs, and so can permute them into something that feeds a single
7072 /// UNPCK instruction. Note that this routine only targets integer vectors
7073 /// because for floating point vectors we have a generalized SHUFPS lowering
7074 /// strategy that handles everything that doesn't *exactly* match an unpack,
7075 /// making this clever lowering unnecessary.
7076 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7077 SDValue V2, ArrayRef<int> Mask,
7078 SelectionDAG &DAG) {
7079 assert(!VT.isFloatingPoint() &&
7080 "This routine only supports integer vectors.");
7081 assert(!isSingleInputShuffleMask(Mask) &&
7082 "This routine should only be used when blending two inputs.");
7083 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7085 int Size = Mask.size();
7087 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7088 return M >= 0 && M % Size < Size / 2;
7090 int NumHiInputs = std::count_if(
7091 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7093 bool UnpackLo = NumLoInputs >= NumHiInputs;
7095 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7096 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7097 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7099 for (int i = 0; i < Size; ++i) {
7103 // Each element of the unpack contains Scale elements from this mask.
7104 int UnpackIdx = i / Scale;
7106 // We only handle the case where V1 feeds the first slots of the unpack.
7107 // We rely on canonicalization to ensure this is the case.
7108 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7111 // Setup the mask for this input. The indexing is tricky as we have to
7112 // handle the unpack stride.
7113 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7114 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7118 // If we will have to shuffle both inputs to use the unpack, check whether
7119 // we can just unpack first and shuffle the result. If so, skip this unpack.
7120 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7121 !isNoopShuffleMask(V2Mask))
7124 // Shuffle the inputs into place.
7125 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7126 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7128 // Cast the inputs to the type we will use to unpack them.
7129 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7130 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7132 // Unpack the inputs and cast the result back to the desired type.
7133 return DAG.getNode(ISD::BITCAST, DL, VT,
7134 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7135 DL, UnpackVT, V1, V2));
7138 // We try each unpack from the largest to the smallest to try and find one
7139 // that fits this mask.
7140 int OrigNumElements = VT.getVectorNumElements();
7141 int OrigScalarSize = VT.getScalarSizeInBits();
7142 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7143 int Scale = ScalarSize / OrigScalarSize;
7144 int NumElements = OrigNumElements / Scale;
7145 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7146 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7150 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7152 if (NumLoInputs == 0 || NumHiInputs == 0) {
7153 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7154 "We have to have *some* inputs!");
7155 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7157 // FIXME: We could consider the total complexity of the permute of each
7158 // possible unpacking. Or at the least we should consider how many
7159 // half-crossings are created.
7160 // FIXME: We could consider commuting the unpacks.
7162 SmallVector<int, 32> PermMask;
7163 PermMask.assign(Size, -1);
7164 for (int i = 0; i < Size; ++i) {
7168 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7171 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7173 return DAG.getVectorShuffle(
7174 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7176 DAG.getUNDEF(VT), PermMask);
7182 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7184 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7185 /// support for floating point shuffles but not integer shuffles. These
7186 /// instructions will incur a domain crossing penalty on some chips though so
7187 /// it is better to avoid lowering through this for integer vectors where
7189 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7190 const X86Subtarget *Subtarget,
7191 SelectionDAG &DAG) {
7193 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7194 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7195 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7197 ArrayRef<int> Mask = SVOp->getMask();
7198 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7200 if (isSingleInputShuffleMask(Mask)) {
7201 // Use low duplicate instructions for masks that match their pattern.
7202 if (Subtarget->hasSSE3())
7203 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7204 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7206 // Straight shuffle of a single input vector. Simulate this by using the
7207 // single input as both of the "inputs" to this instruction..
7208 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7210 if (Subtarget->hasAVX()) {
7211 // If we have AVX, we can use VPERMILPS which will allow folding a load
7212 // into the shuffle.
7213 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7214 DAG.getConstant(SHUFPDMask, MVT::i8));
7217 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7218 DAG.getConstant(SHUFPDMask, MVT::i8));
7220 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7221 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7223 // If we have a single input, insert that into V1 if we can do so cheaply.
7224 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7225 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7226 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7228 // Try inverting the insertion since for v2 masks it is easy to do and we
7229 // can't reliably sort the mask one way or the other.
7230 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7231 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7232 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7233 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7237 // Try to use one of the special instruction patterns to handle two common
7238 // blend patterns if a zero-blend above didn't work.
7239 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7240 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7241 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7242 // We can either use a special instruction to load over the low double or
7243 // to move just the low double.
7245 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7247 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7249 if (Subtarget->hasSSE41())
7250 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7254 // Use dedicated unpack instructions for masks that match their pattern.
7255 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7256 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7257 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7258 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7260 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7261 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7262 DAG.getConstant(SHUFPDMask, MVT::i8));
7265 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7267 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7268 /// the integer unit to minimize domain crossing penalties. However, for blends
7269 /// it falls back to the floating point shuffle operation with appropriate bit
7271 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7272 const X86Subtarget *Subtarget,
7273 SelectionDAG &DAG) {
7275 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7276 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7277 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7278 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7279 ArrayRef<int> Mask = SVOp->getMask();
7280 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7282 if (isSingleInputShuffleMask(Mask)) {
7283 // Check for being able to broadcast a single element.
7284 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7285 Mask, Subtarget, DAG))
7288 // Straight shuffle of a single input vector. For everything from SSE2
7289 // onward this has a single fast instruction with no scary immediates.
7290 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7291 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7292 int WidenedMask[4] = {
7293 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7294 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7296 ISD::BITCAST, DL, MVT::v2i64,
7297 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7298 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7300 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7301 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7302 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7303 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7305 // If we have a blend of two PACKUS operations an the blend aligns with the
7306 // low and half halves, we can just merge the PACKUS operations. This is
7307 // particularly important as it lets us merge shuffles that this routine itself
7309 auto GetPackNode = [](SDValue V) {
7310 while (V.getOpcode() == ISD::BITCAST)
7311 V = V.getOperand(0);
7313 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7315 if (SDValue V1Pack = GetPackNode(V1))
7316 if (SDValue V2Pack = GetPackNode(V2))
7317 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7318 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7319 Mask[0] == 0 ? V1Pack.getOperand(0)
7320 : V1Pack.getOperand(1),
7321 Mask[1] == 2 ? V2Pack.getOperand(0)
7322 : V2Pack.getOperand(1)));
7324 // Try to use shift instructions.
7326 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7329 // When loading a scalar and then shuffling it into a vector we can often do
7330 // the insertion cheaply.
7331 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7332 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7334 // Try inverting the insertion since for v2 masks it is easy to do and we
7335 // can't reliably sort the mask one way or the other.
7336 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7337 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7338 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7341 // We have different paths for blend lowering, but they all must use the
7342 // *exact* same predicate.
7343 bool IsBlendSupported = Subtarget->hasSSE41();
7344 if (IsBlendSupported)
7345 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7349 // Use dedicated unpack instructions for masks that match their pattern.
7350 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7351 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7352 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7353 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7355 // Try to use byte rotation instructions.
7356 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7357 if (Subtarget->hasSSSE3())
7358 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7359 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7362 // If we have direct support for blends, we should lower by decomposing into
7363 // a permute. That will be faster than the domain cross.
7364 if (IsBlendSupported)
7365 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7368 // We implement this with SHUFPD which is pretty lame because it will likely
7369 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7370 // However, all the alternatives are still more cycles and newer chips don't
7371 // have this problem. It would be really nice if x86 had better shuffles here.
7372 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7373 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7374 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7375 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7378 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7380 /// This is used to disable more specialized lowerings when the shufps lowering
7381 /// will happen to be efficient.
7382 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7383 // This routine only handles 128-bit shufps.
7384 assert(Mask.size() == 4 && "Unsupported mask size!");
7386 // To lower with a single SHUFPS we need to have the low half and high half
7387 // each requiring a single input.
7388 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7390 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7396 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7398 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7399 /// It makes no assumptions about whether this is the *best* lowering, it simply
7401 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7402 ArrayRef<int> Mask, SDValue V1,
7403 SDValue V2, SelectionDAG &DAG) {
7404 SDValue LowV = V1, HighV = V2;
7405 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7408 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7410 if (NumV2Elements == 1) {
7412 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7415 // Compute the index adjacent to V2Index and in the same half by toggling
7417 int V2AdjIndex = V2Index ^ 1;
7419 if (Mask[V2AdjIndex] == -1) {
7420 // Handles all the cases where we have a single V2 element and an undef.
7421 // This will only ever happen in the high lanes because we commute the
7422 // vector otherwise.
7424 std::swap(LowV, HighV);
7425 NewMask[V2Index] -= 4;
7427 // Handle the case where the V2 element ends up adjacent to a V1 element.
7428 // To make this work, blend them together as the first step.
7429 int V1Index = V2AdjIndex;
7430 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7431 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7432 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7434 // Now proceed to reconstruct the final blend as we have the necessary
7435 // high or low half formed.
7442 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7443 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7445 } else if (NumV2Elements == 2) {
7446 if (Mask[0] < 4 && Mask[1] < 4) {
7447 // Handle the easy case where we have V1 in the low lanes and V2 in the
7451 } else if (Mask[2] < 4 && Mask[3] < 4) {
7452 // We also handle the reversed case because this utility may get called
7453 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7454 // arrange things in the right direction.
7460 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7461 // trying to place elements directly, just blend them and set up the final
7462 // shuffle to place them.
7464 // The first two blend mask elements are for V1, the second two are for
7466 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7467 Mask[2] < 4 ? Mask[2] : Mask[3],
7468 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7469 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7470 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7471 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7473 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7476 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7477 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7478 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7479 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7482 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7483 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7486 /// \brief Lower 4-lane 32-bit floating point shuffles.
7488 /// Uses instructions exclusively from the floating point unit to minimize
7489 /// domain crossing penalties, as these are sufficient to implement all v4f32
7491 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7492 const X86Subtarget *Subtarget,
7493 SelectionDAG &DAG) {
7495 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7496 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7497 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7498 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7499 ArrayRef<int> Mask = SVOp->getMask();
7500 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7503 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7505 if (NumV2Elements == 0) {
7506 // Check for being able to broadcast a single element.
7507 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7508 Mask, Subtarget, DAG))
7511 // Use even/odd duplicate instructions for masks that match their pattern.
7512 if (Subtarget->hasSSE3()) {
7513 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7514 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7515 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7516 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7519 if (Subtarget->hasAVX()) {
7520 // If we have AVX, we can use VPERMILPS which will allow folding a load
7521 // into the shuffle.
7522 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7523 getV4X86ShuffleImm8ForMask(Mask, DAG));
7526 // Otherwise, use a straight shuffle of a single input vector. We pass the
7527 // input vector to both operands to simulate this with a SHUFPS.
7528 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7529 getV4X86ShuffleImm8ForMask(Mask, DAG));
7532 // There are special ways we can lower some single-element blends. However, we
7533 // have custom ways we can lower more complex single-element blends below that
7534 // we defer to if both this and BLENDPS fail to match, so restrict this to
7535 // when the V2 input is targeting element 0 of the mask -- that is the fast
7537 if (NumV2Elements == 1 && Mask[0] >= 4)
7538 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7539 Mask, Subtarget, DAG))
7542 if (Subtarget->hasSSE41()) {
7543 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7547 // Use INSERTPS if we can complete the shuffle efficiently.
7548 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7551 if (!isSingleSHUFPSMask(Mask))
7552 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7553 DL, MVT::v4f32, V1, V2, Mask, DAG))
7557 // Use dedicated unpack instructions for masks that match their pattern.
7558 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7559 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7560 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7561 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7562 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7563 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7564 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7565 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7567 // Otherwise fall back to a SHUFPS lowering strategy.
7568 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7571 /// \brief Lower 4-lane i32 vector shuffles.
7573 /// We try to handle these with integer-domain shuffles where we can, but for
7574 /// blends we use the floating point domain blend instructions.
7575 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7576 const X86Subtarget *Subtarget,
7577 SelectionDAG &DAG) {
7579 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7580 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7581 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7582 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7583 ArrayRef<int> Mask = SVOp->getMask();
7584 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7586 // Whenever we can lower this as a zext, that instruction is strictly faster
7587 // than any alternative. It also allows us to fold memory operands into the
7588 // shuffle in many cases.
7589 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7590 Mask, Subtarget, DAG))
7594 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7596 if (NumV2Elements == 0) {
7597 // Check for being able to broadcast a single element.
7598 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7599 Mask, Subtarget, DAG))
7602 // Straight shuffle of a single input vector. For everything from SSE2
7603 // onward this has a single fast instruction with no scary immediates.
7604 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7605 // but we aren't actually going to use the UNPCK instruction because doing
7606 // so prevents folding a load into this instruction or making a copy.
7607 const int UnpackLoMask[] = {0, 0, 1, 1};
7608 const int UnpackHiMask[] = {2, 2, 3, 3};
7609 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7610 Mask = UnpackLoMask;
7611 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7612 Mask = UnpackHiMask;
7614 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7615 getV4X86ShuffleImm8ForMask(Mask, DAG));
7618 // Try to use shift instructions.
7620 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7623 // There are special ways we can lower some single-element blends.
7624 if (NumV2Elements == 1)
7625 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7626 Mask, Subtarget, DAG))
7629 // We have different paths for blend lowering, but they all must use the
7630 // *exact* same predicate.
7631 bool IsBlendSupported = Subtarget->hasSSE41();
7632 if (IsBlendSupported)
7633 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7637 if (SDValue Masked =
7638 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7641 // Use dedicated unpack instructions for masks that match their pattern.
7642 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7643 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7644 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7645 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7646 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7647 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7648 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7649 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7651 // Try to use byte rotation instructions.
7652 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7653 if (Subtarget->hasSSSE3())
7654 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7655 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7658 // If we have direct support for blends, we should lower by decomposing into
7659 // a permute. That will be faster than the domain cross.
7660 if (IsBlendSupported)
7661 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7664 // Try to lower by permuting the inputs into an unpack instruction.
7665 if (SDValue Unpack =
7666 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7669 // We implement this with SHUFPS because it can blend from two vectors.
7670 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7671 // up the inputs, bypassing domain shift penalties that we would encur if we
7672 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7674 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7675 DAG.getVectorShuffle(
7677 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7678 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7681 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7682 /// shuffle lowering, and the most complex part.
7684 /// The lowering strategy is to try to form pairs of input lanes which are
7685 /// targeted at the same half of the final vector, and then use a dword shuffle
7686 /// to place them onto the right half, and finally unpack the paired lanes into
7687 /// their final position.
7689 /// The exact breakdown of how to form these dword pairs and align them on the
7690 /// correct sides is really tricky. See the comments within the function for
7691 /// more of the details.
7693 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7694 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7695 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7696 /// vector, form the analogous 128-bit 8-element Mask.
7697 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7698 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7699 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7700 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7701 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7703 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7704 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7705 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7707 SmallVector<int, 4> LoInputs;
7708 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7709 [](int M) { return M >= 0; });
7710 std::sort(LoInputs.begin(), LoInputs.end());
7711 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7712 SmallVector<int, 4> HiInputs;
7713 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7714 [](int M) { return M >= 0; });
7715 std::sort(HiInputs.begin(), HiInputs.end());
7716 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7718 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7719 int NumHToL = LoInputs.size() - NumLToL;
7721 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7722 int NumHToH = HiInputs.size() - NumLToH;
7723 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7724 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7725 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7726 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7728 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7729 // such inputs we can swap two of the dwords across the half mark and end up
7730 // with <=2 inputs to each half in each half. Once there, we can fall through
7731 // to the generic code below. For example:
7733 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7734 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7736 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7737 // and an existing 2-into-2 on the other half. In this case we may have to
7738 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7739 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7740 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7741 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7742 // half than the one we target for fixing) will be fixed when we re-enter this
7743 // path. We will also combine away any sequence of PSHUFD instructions that
7744 // result into a single instruction. Here is an example of the tricky case:
7746 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7747 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7749 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7751 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7752 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7754 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7755 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7757 // The result is fine to be handled by the generic logic.
7758 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7759 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7760 int AOffset, int BOffset) {
7761 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7762 "Must call this with A having 3 or 1 inputs from the A half.");
7763 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7764 "Must call this with B having 1 or 3 inputs from the B half.");
7765 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7766 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7768 // Compute the index of dword with only one word among the three inputs in
7769 // a half by taking the sum of the half with three inputs and subtracting
7770 // the sum of the actual three inputs. The difference is the remaining
7773 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7774 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7775 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7776 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7777 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7778 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7779 int TripleNonInputIdx =
7780 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7781 TripleDWord = TripleNonInputIdx / 2;
7783 // We use xor with one to compute the adjacent DWord to whichever one the
7785 OneInputDWord = (OneInput / 2) ^ 1;
7787 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7788 // and BToA inputs. If there is also such a problem with the BToB and AToB
7789 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7790 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7791 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7792 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7793 // Compute how many inputs will be flipped by swapping these DWords. We
7795 // to balance this to ensure we don't form a 3-1 shuffle in the other
7797 int NumFlippedAToBInputs =
7798 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7799 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7800 int NumFlippedBToBInputs =
7801 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7802 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7803 if ((NumFlippedAToBInputs == 1 &&
7804 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7805 (NumFlippedBToBInputs == 1 &&
7806 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7807 // We choose whether to fix the A half or B half based on whether that
7808 // half has zero flipped inputs. At zero, we may not be able to fix it
7809 // with that half. We also bias towards fixing the B half because that
7810 // will more commonly be the high half, and we have to bias one way.
7811 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7812 ArrayRef<int> Inputs) {
7813 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7814 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7815 PinnedIdx ^ 1) != Inputs.end();
7816 // Determine whether the free index is in the flipped dword or the
7817 // unflipped dword based on where the pinned index is. We use this bit
7818 // in an xor to conditionally select the adjacent dword.
7819 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7820 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7821 FixFreeIdx) != Inputs.end();
7822 if (IsFixIdxInput == IsFixFreeIdxInput)
7824 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7825 FixFreeIdx) != Inputs.end();
7826 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7827 "We need to be changing the number of flipped inputs!");
7828 int PSHUFHalfMask[] = {0, 1, 2, 3};
7829 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7830 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7832 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7835 if (M != -1 && M == FixIdx)
7837 else if (M != -1 && M == FixFreeIdx)
7840 if (NumFlippedBToBInputs != 0) {
7842 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7843 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7845 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7847 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7848 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7853 int PSHUFDMask[] = {0, 1, 2, 3};
7854 PSHUFDMask[ADWord] = BDWord;
7855 PSHUFDMask[BDWord] = ADWord;
7856 V = DAG.getNode(ISD::BITCAST, DL, VT,
7857 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
7858 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
7859 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7861 // Adjust the mask to match the new locations of A and B.
7863 if (M != -1 && M/2 == ADWord)
7864 M = 2 * BDWord + M % 2;
7865 else if (M != -1 && M/2 == BDWord)
7866 M = 2 * ADWord + M % 2;
7868 // Recurse back into this routine to re-compute state now that this isn't
7869 // a 3 and 1 problem.
7870 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
7873 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7874 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7875 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7876 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7878 // At this point there are at most two inputs to the low and high halves from
7879 // each half. That means the inputs can always be grouped into dwords and
7880 // those dwords can then be moved to the correct half with a dword shuffle.
7881 // We use at most one low and one high word shuffle to collect these paired
7882 // inputs into dwords, and finally a dword shuffle to place them.
7883 int PSHUFLMask[4] = {-1, -1, -1, -1};
7884 int PSHUFHMask[4] = {-1, -1, -1, -1};
7885 int PSHUFDMask[4] = {-1, -1, -1, -1};
7887 // First fix the masks for all the inputs that are staying in their
7888 // original halves. This will then dictate the targets of the cross-half
7890 auto fixInPlaceInputs =
7891 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7892 MutableArrayRef<int> SourceHalfMask,
7893 MutableArrayRef<int> HalfMask, int HalfOffset) {
7894 if (InPlaceInputs.empty())
7896 if (InPlaceInputs.size() == 1) {
7897 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7898 InPlaceInputs[0] - HalfOffset;
7899 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7902 if (IncomingInputs.empty()) {
7903 // Just fix all of the in place inputs.
7904 for (int Input : InPlaceInputs) {
7905 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7906 PSHUFDMask[Input / 2] = Input / 2;
7911 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7912 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7913 InPlaceInputs[0] - HalfOffset;
7914 // Put the second input next to the first so that they are packed into
7915 // a dword. We find the adjacent index by toggling the low bit.
7916 int AdjIndex = InPlaceInputs[0] ^ 1;
7917 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7918 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7919 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7921 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7922 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7924 // Now gather the cross-half inputs and place them into a free dword of
7925 // their target half.
7926 // FIXME: This operation could almost certainly be simplified dramatically to
7927 // look more like the 3-1 fixing operation.
7928 auto moveInputsToRightHalf = [&PSHUFDMask](
7929 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7930 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7931 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7933 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7934 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7936 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7938 int LowWord = Word & ~1;
7939 int HighWord = Word | 1;
7940 return isWordClobbered(SourceHalfMask, LowWord) ||
7941 isWordClobbered(SourceHalfMask, HighWord);
7944 if (IncomingInputs.empty())
7947 if (ExistingInputs.empty()) {
7948 // Map any dwords with inputs from them into the right half.
7949 for (int Input : IncomingInputs) {
7950 // If the source half mask maps over the inputs, turn those into
7951 // swaps and use the swapped lane.
7952 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7953 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7954 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7955 Input - SourceOffset;
7956 // We have to swap the uses in our half mask in one sweep.
7957 for (int &M : HalfMask)
7958 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7960 else if (M == Input)
7961 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7963 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7964 Input - SourceOffset &&
7965 "Previous placement doesn't match!");
7967 // Note that this correctly re-maps both when we do a swap and when
7968 // we observe the other side of the swap above. We rely on that to
7969 // avoid swapping the members of the input list directly.
7970 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7973 // Map the input's dword into the correct half.
7974 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7975 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7977 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7979 "Previous placement doesn't match!");
7982 // And just directly shift any other-half mask elements to be same-half
7983 // as we will have mirrored the dword containing the element into the
7984 // same position within that half.
7985 for (int &M : HalfMask)
7986 if (M >= SourceOffset && M < SourceOffset + 4) {
7987 M = M - SourceOffset + DestOffset;
7988 assert(M >= 0 && "This should never wrap below zero!");
7993 // Ensure we have the input in a viable dword of its current half. This
7994 // is particularly tricky because the original position may be clobbered
7995 // by inputs being moved and *staying* in that half.
7996 if (IncomingInputs.size() == 1) {
7997 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7998 int InputFixed = std::find(std::begin(SourceHalfMask),
7999 std::end(SourceHalfMask), -1) -
8000 std::begin(SourceHalfMask) + SourceOffset;
8001 SourceHalfMask[InputFixed - SourceOffset] =
8002 IncomingInputs[0] - SourceOffset;
8003 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8005 IncomingInputs[0] = InputFixed;
8007 } else if (IncomingInputs.size() == 2) {
8008 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8009 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8010 // We have two non-adjacent or clobbered inputs we need to extract from
8011 // the source half. To do this, we need to map them into some adjacent
8012 // dword slot in the source mask.
8013 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8014 IncomingInputs[1] - SourceOffset};
8016 // If there is a free slot in the source half mask adjacent to one of
8017 // the inputs, place the other input in it. We use (Index XOR 1) to
8018 // compute an adjacent index.
8019 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8020 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8021 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8022 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8023 InputsFixed[1] = InputsFixed[0] ^ 1;
8024 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8025 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8026 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8027 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8028 InputsFixed[0] = InputsFixed[1] ^ 1;
8029 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8030 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8031 // The two inputs are in the same DWord but it is clobbered and the
8032 // adjacent DWord isn't used at all. Move both inputs to the free
8034 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8035 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8036 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8037 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8039 // The only way we hit this point is if there is no clobbering
8040 // (because there are no off-half inputs to this half) and there is no
8041 // free slot adjacent to one of the inputs. In this case, we have to
8042 // swap an input with a non-input.
8043 for (int i = 0; i < 4; ++i)
8044 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8045 "We can't handle any clobbers here!");
8046 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8047 "Cannot have adjacent inputs here!");
8049 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8050 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8052 // We also have to update the final source mask in this case because
8053 // it may need to undo the above swap.
8054 for (int &M : FinalSourceHalfMask)
8055 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8056 M = InputsFixed[1] + SourceOffset;
8057 else if (M == InputsFixed[1] + SourceOffset)
8058 M = (InputsFixed[0] ^ 1) + SourceOffset;
8060 InputsFixed[1] = InputsFixed[0] ^ 1;
8063 // Point everything at the fixed inputs.
8064 for (int &M : HalfMask)
8065 if (M == IncomingInputs[0])
8066 M = InputsFixed[0] + SourceOffset;
8067 else if (M == IncomingInputs[1])
8068 M = InputsFixed[1] + SourceOffset;
8070 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8071 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8074 llvm_unreachable("Unhandled input size!");
8077 // Now hoist the DWord down to the right half.
8078 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8079 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8080 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8081 for (int &M : HalfMask)
8082 for (int Input : IncomingInputs)
8084 M = FreeDWord * 2 + Input % 2;
8086 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8087 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8088 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8089 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8091 // Now enact all the shuffles we've computed to move the inputs into their
8093 if (!isNoopShuffleMask(PSHUFLMask))
8094 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8095 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8096 if (!isNoopShuffleMask(PSHUFHMask))
8097 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8098 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8099 if (!isNoopShuffleMask(PSHUFDMask))
8100 V = DAG.getNode(ISD::BITCAST, DL, VT,
8101 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8102 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8103 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8105 // At this point, each half should contain all its inputs, and we can then
8106 // just shuffle them into their final position.
8107 assert(std::count_if(LoMask.begin(), LoMask.end(),
8108 [](int M) { return M >= 4; }) == 0 &&
8109 "Failed to lift all the high half inputs to the low mask!");
8110 assert(std::count_if(HiMask.begin(), HiMask.end(),
8111 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8112 "Failed to lift all the low half inputs to the high mask!");
8114 // Do a half shuffle for the low mask.
8115 if (!isNoopShuffleMask(LoMask))
8116 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8117 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8119 // Do a half shuffle with the high mask after shifting its values down.
8120 for (int &M : HiMask)
8123 if (!isNoopShuffleMask(HiMask))
8124 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8125 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8130 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8131 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8132 SDValue V2, ArrayRef<int> Mask,
8133 SelectionDAG &DAG, bool &V1InUse,
8135 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8141 int Size = Mask.size();
8142 int Scale = 16 / Size;
8143 for (int i = 0; i < 16; ++i) {
8144 if (Mask[i / Scale] == -1) {
8145 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8147 const int ZeroMask = 0x80;
8148 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8150 int V2Idx = Mask[i / Scale] < Size
8152 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8153 if (Zeroable[i / Scale])
8154 V1Idx = V2Idx = ZeroMask;
8155 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
8156 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
8157 V1InUse |= (ZeroMask != V1Idx);
8158 V2InUse |= (ZeroMask != V2Idx);
8163 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8164 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8165 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8167 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8168 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8169 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8171 // If we need shuffled inputs from both, blend the two.
8173 if (V1InUse && V2InUse)
8174 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8176 V = V1InUse ? V1 : V2;
8178 // Cast the result back to the correct type.
8179 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8182 /// \brief Generic lowering of 8-lane i16 shuffles.
8184 /// This handles both single-input shuffles and combined shuffle/blends with
8185 /// two inputs. The single input shuffles are immediately delegated to
8186 /// a dedicated lowering routine.
8188 /// The blends are lowered in one of three fundamental ways. If there are few
8189 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8190 /// of the input is significantly cheaper when lowered as an interleaving of
8191 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8192 /// halves of the inputs separately (making them have relatively few inputs)
8193 /// and then concatenate them.
8194 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8195 const X86Subtarget *Subtarget,
8196 SelectionDAG &DAG) {
8198 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8199 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8200 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8202 ArrayRef<int> OrigMask = SVOp->getMask();
8203 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8204 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8205 MutableArrayRef<int> Mask(MaskStorage);
8207 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8209 // Whenever we can lower this as a zext, that instruction is strictly faster
8210 // than any alternative.
8211 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8212 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8215 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8217 auto isV2 = [](int M) { return M >= 8; };
8219 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8221 if (NumV2Inputs == 0) {
8222 // Check for being able to broadcast a single element.
8223 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8224 Mask, Subtarget, DAG))
8227 // Try to use shift instructions.
8229 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8232 // Use dedicated unpack instructions for masks that match their pattern.
8233 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8234 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8235 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8236 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8238 // Try to use byte rotation instructions.
8239 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8240 Mask, Subtarget, DAG))
8243 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8247 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8248 "All single-input shuffles should be canonicalized to be V1-input "
8251 // Try to use shift instructions.
8253 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8256 // There are special ways we can lower some single-element blends.
8257 if (NumV2Inputs == 1)
8258 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8259 Mask, Subtarget, DAG))
8262 // We have different paths for blend lowering, but they all must use the
8263 // *exact* same predicate.
8264 bool IsBlendSupported = Subtarget->hasSSE41();
8265 if (IsBlendSupported)
8266 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8270 if (SDValue Masked =
8271 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8274 // Use dedicated unpack instructions for masks that match their pattern.
8275 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8276 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8277 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8278 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8280 // Try to use byte rotation instructions.
8281 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8282 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8285 if (SDValue BitBlend =
8286 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8289 if (SDValue Unpack =
8290 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8293 // If we can't directly blend but can use PSHUFB, that will be better as it
8294 // can both shuffle and set up the inefficient blend.
8295 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8296 bool V1InUse, V2InUse;
8297 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8301 // We can always bit-blend if we have to so the fallback strategy is to
8302 // decompose into single-input permutes and blends.
8303 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8307 /// \brief Check whether a compaction lowering can be done by dropping even
8308 /// elements and compute how many times even elements must be dropped.
8310 /// This handles shuffles which take every Nth element where N is a power of
8311 /// two. Example shuffle masks:
8313 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8314 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8315 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8316 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8317 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8318 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8320 /// Any of these lanes can of course be undef.
8322 /// This routine only supports N <= 3.
8323 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8326 /// \returns N above, or the number of times even elements must be dropped if
8327 /// there is such a number. Otherwise returns zero.
8328 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8329 // Figure out whether we're looping over two inputs or just one.
8330 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8332 // The modulus for the shuffle vector entries is based on whether this is
8333 // a single input or not.
8334 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8335 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8336 "We should only be called with masks with a power-of-2 size!");
8338 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8340 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8341 // and 2^3 simultaneously. This is because we may have ambiguity with
8342 // partially undef inputs.
8343 bool ViableForN[3] = {true, true, true};
8345 for (int i = 0, e = Mask.size(); i < e; ++i) {
8346 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8351 bool IsAnyViable = false;
8352 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8353 if (ViableForN[j]) {
8356 // The shuffle mask must be equal to (i * 2^N) % M.
8357 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8360 ViableForN[j] = false;
8362 // Early exit if we exhaust the possible powers of two.
8367 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8371 // Return 0 as there is no viable power of two.
8375 /// \brief Generic lowering of v16i8 shuffles.
8377 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8378 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8379 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8380 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8382 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8383 const X86Subtarget *Subtarget,
8384 SelectionDAG &DAG) {
8386 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8387 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8388 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8389 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8390 ArrayRef<int> Mask = SVOp->getMask();
8391 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8393 // Try to use shift instructions.
8395 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8398 // Try to use byte rotation instructions.
8399 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8400 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8403 // Try to use a zext lowering.
8404 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8405 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8409 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8411 // For single-input shuffles, there are some nicer lowering tricks we can use.
8412 if (NumV2Elements == 0) {
8413 // Check for being able to broadcast a single element.
8414 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8415 Mask, Subtarget, DAG))
8418 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8419 // Notably, this handles splat and partial-splat shuffles more efficiently.
8420 // However, it only makes sense if the pre-duplication shuffle simplifies
8421 // things significantly. Currently, this means we need to be able to
8422 // express the pre-duplication shuffle as an i16 shuffle.
8424 // FIXME: We should check for other patterns which can be widened into an
8425 // i16 shuffle as well.
8426 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8427 for (int i = 0; i < 16; i += 2)
8428 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8433 auto tryToWidenViaDuplication = [&]() -> SDValue {
8434 if (!canWidenViaDuplication(Mask))
8436 SmallVector<int, 4> LoInputs;
8437 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8438 [](int M) { return M >= 0 && M < 8; });
8439 std::sort(LoInputs.begin(), LoInputs.end());
8440 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8442 SmallVector<int, 4> HiInputs;
8443 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8444 [](int M) { return M >= 8; });
8445 std::sort(HiInputs.begin(), HiInputs.end());
8446 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8449 bool TargetLo = LoInputs.size() >= HiInputs.size();
8450 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8451 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8453 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8454 SmallDenseMap<int, int, 8> LaneMap;
8455 for (int I : InPlaceInputs) {
8456 PreDupI16Shuffle[I/2] = I/2;
8459 int j = TargetLo ? 0 : 4, je = j + 4;
8460 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8461 // Check if j is already a shuffle of this input. This happens when
8462 // there are two adjacent bytes after we move the low one.
8463 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8464 // If we haven't yet mapped the input, search for a slot into which
8466 while (j < je && PreDupI16Shuffle[j] != -1)
8470 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8473 // Map this input with the i16 shuffle.
8474 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8477 // Update the lane map based on the mapping we ended up with.
8478 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8481 ISD::BITCAST, DL, MVT::v16i8,
8482 DAG.getVectorShuffle(MVT::v8i16, DL,
8483 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8484 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8486 // Unpack the bytes to form the i16s that will be shuffled into place.
8487 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8488 MVT::v16i8, V1, V1);
8490 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8491 for (int i = 0; i < 16; ++i)
8492 if (Mask[i] != -1) {
8493 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8494 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8495 if (PostDupI16Shuffle[i / 2] == -1)
8496 PostDupI16Shuffle[i / 2] = MappedMask;
8498 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8499 "Conflicting entrties in the original shuffle!");
8502 ISD::BITCAST, DL, MVT::v16i8,
8503 DAG.getVectorShuffle(MVT::v8i16, DL,
8504 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8505 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8507 if (SDValue V = tryToWidenViaDuplication())
8511 // Use dedicated unpack instructions for masks that match their pattern.
8512 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8513 0, 16, 1, 17, 2, 18, 3, 19,
8515 4, 20, 5, 21, 6, 22, 7, 23}))
8516 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8517 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8518 8, 24, 9, 25, 10, 26, 11, 27,
8520 12, 28, 13, 29, 14, 30, 15, 31}))
8521 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8523 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8524 // with PSHUFB. It is important to do this before we attempt to generate any
8525 // blends but after all of the single-input lowerings. If the single input
8526 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8527 // want to preserve that and we can DAG combine any longer sequences into
8528 // a PSHUFB in the end. But once we start blending from multiple inputs,
8529 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8530 // and there are *very* few patterns that would actually be faster than the
8531 // PSHUFB approach because of its ability to zero lanes.
8533 // FIXME: The only exceptions to the above are blends which are exact
8534 // interleavings with direct instructions supporting them. We currently don't
8535 // handle those well here.
8536 if (Subtarget->hasSSSE3()) {
8537 bool V1InUse = false;
8538 bool V2InUse = false;
8540 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8541 DAG, V1InUse, V2InUse);
8543 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8544 // do so. This avoids using them to handle blends-with-zero which is
8545 // important as a single pshufb is significantly faster for that.
8546 if (V1InUse && V2InUse) {
8547 if (Subtarget->hasSSE41())
8548 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8549 Mask, Subtarget, DAG))
8552 // We can use an unpack to do the blending rather than an or in some
8553 // cases. Even though the or may be (very minorly) more efficient, we
8554 // preference this lowering because there are common cases where part of
8555 // the complexity of the shuffles goes away when we do the final blend as
8557 // FIXME: It might be worth trying to detect if the unpack-feeding
8558 // shuffles will both be pshufb, in which case we shouldn't bother with
8560 if (SDValue Unpack =
8561 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8568 // There are special ways we can lower some single-element blends.
8569 if (NumV2Elements == 1)
8570 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8571 Mask, Subtarget, DAG))
8574 if (SDValue BitBlend =
8575 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8578 // Check whether a compaction lowering can be done. This handles shuffles
8579 // which take every Nth element for some even N. See the helper function for
8582 // We special case these as they can be particularly efficiently handled with
8583 // the PACKUSB instruction on x86 and they show up in common patterns of
8584 // rearranging bytes to truncate wide elements.
8585 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8586 // NumEvenDrops is the power of two stride of the elements. Another way of
8587 // thinking about it is that we need to drop the even elements this many
8588 // times to get the original input.
8589 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8591 // First we need to zero all the dropped bytes.
8592 assert(NumEvenDrops <= 3 &&
8593 "No support for dropping even elements more than 3 times.");
8594 // We use the mask type to pick which bytes are preserved based on how many
8595 // elements are dropped.
8596 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8597 SDValue ByteClearMask =
8598 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8599 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8600 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8602 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8604 // Now pack things back together.
8605 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8606 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8607 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8608 for (int i = 1; i < NumEvenDrops; ++i) {
8609 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8610 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8616 // Handle multi-input cases by blending single-input shuffles.
8617 if (NumV2Elements > 0)
8618 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8621 // The fallback path for single-input shuffles widens this into two v8i16
8622 // vectors with unpacks, shuffles those, and then pulls them back together
8626 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8627 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8628 for (int i = 0; i < 16; ++i)
8630 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8632 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8634 SDValue VLoHalf, VHiHalf;
8635 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8636 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8638 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8639 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8640 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8641 [](int M) { return M >= 0 && M % 2 == 1; })) {
8642 // Use a mask to drop the high bytes.
8643 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8644 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8645 DAG.getConstant(0x00FF, MVT::v8i16));
8647 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8648 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8650 // Squash the masks to point directly into VLoHalf.
8651 for (int &M : LoBlendMask)
8654 for (int &M : HiBlendMask)
8658 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8659 // VHiHalf so that we can blend them as i16s.
8660 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8661 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8662 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8663 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8666 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8667 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8669 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8672 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8674 /// This routine breaks down the specific type of 128-bit shuffle and
8675 /// dispatches to the lowering routines accordingly.
8676 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8677 MVT VT, const X86Subtarget *Subtarget,
8678 SelectionDAG &DAG) {
8679 switch (VT.SimpleTy) {
8681 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8683 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8685 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8687 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8689 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8691 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8694 llvm_unreachable("Unimplemented!");
8698 /// \brief Helper function to test whether a shuffle mask could be
8699 /// simplified by widening the elements being shuffled.
8701 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8702 /// leaves it in an unspecified state.
8704 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8705 /// shuffle masks. The latter have the special property of a '-2' representing
8706 /// a zero-ed lane of a vector.
8707 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8708 SmallVectorImpl<int> &WidenedMask) {
8709 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8710 // If both elements are undef, its trivial.
8711 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8712 WidenedMask.push_back(SM_SentinelUndef);
8716 // Check for an undef mask and a mask value properly aligned to fit with
8717 // a pair of values. If we find such a case, use the non-undef mask's value.
8718 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8719 WidenedMask.push_back(Mask[i + 1] / 2);
8722 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8723 WidenedMask.push_back(Mask[i] / 2);
8727 // When zeroing, we need to spread the zeroing across both lanes to widen.
8728 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8729 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8730 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8731 WidenedMask.push_back(SM_SentinelZero);
8737 // Finally check if the two mask values are adjacent and aligned with
8739 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8740 WidenedMask.push_back(Mask[i] / 2);
8744 // Otherwise we can't safely widen the elements used in this shuffle.
8747 assert(WidenedMask.size() == Mask.size() / 2 &&
8748 "Incorrect size of mask after widening the elements!");
8753 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8755 /// This routine just extracts two subvectors, shuffles them independently, and
8756 /// then concatenates them back together. This should work effectively with all
8757 /// AVX vector shuffle types.
8758 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8759 SDValue V2, ArrayRef<int> Mask,
8760 SelectionDAG &DAG) {
8761 assert(VT.getSizeInBits() >= 256 &&
8762 "Only for 256-bit or wider vector shuffles!");
8763 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8764 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8766 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8767 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8769 int NumElements = VT.getVectorNumElements();
8770 int SplitNumElements = NumElements / 2;
8771 MVT ScalarVT = VT.getScalarType();
8772 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8774 // Rather than splitting build-vectors, just build two narrower build
8775 // vectors. This helps shuffling with splats and zeros.
8776 auto SplitVector = [&](SDValue V) {
8777 while (V.getOpcode() == ISD::BITCAST)
8778 V = V->getOperand(0);
8780 MVT OrigVT = V.getSimpleValueType();
8781 int OrigNumElements = OrigVT.getVectorNumElements();
8782 int OrigSplitNumElements = OrigNumElements / 2;
8783 MVT OrigScalarVT = OrigVT.getScalarType();
8784 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8788 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8790 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8791 DAG.getIntPtrConstant(0));
8792 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8793 DAG.getIntPtrConstant(OrigSplitNumElements));
8796 SmallVector<SDValue, 16> LoOps, HiOps;
8797 for (int i = 0; i < OrigSplitNumElements; ++i) {
8798 LoOps.push_back(BV->getOperand(i));
8799 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
8801 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
8802 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
8804 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
8805 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
8808 SDValue LoV1, HiV1, LoV2, HiV2;
8809 std::tie(LoV1, HiV1) = SplitVector(V1);
8810 std::tie(LoV2, HiV2) = SplitVector(V2);
8812 // Now create two 4-way blends of these half-width vectors.
8813 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8814 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
8815 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
8816 for (int i = 0; i < SplitNumElements; ++i) {
8817 int M = HalfMask[i];
8818 if (M >= NumElements) {
8819 if (M >= NumElements + SplitNumElements)
8823 V2BlendMask.push_back(M - NumElements);
8824 V1BlendMask.push_back(-1);
8825 BlendMask.push_back(SplitNumElements + i);
8826 } else if (M >= 0) {
8827 if (M >= SplitNumElements)
8831 V2BlendMask.push_back(-1);
8832 V1BlendMask.push_back(M);
8833 BlendMask.push_back(i);
8835 V2BlendMask.push_back(-1);
8836 V1BlendMask.push_back(-1);
8837 BlendMask.push_back(-1);
8841 // Because the lowering happens after all combining takes place, we need to
8842 // manually combine these blend masks as much as possible so that we create
8843 // a minimal number of high-level vector shuffle nodes.
8845 // First try just blending the halves of V1 or V2.
8846 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
8847 return DAG.getUNDEF(SplitVT);
8848 if (!UseLoV2 && !UseHiV2)
8849 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8850 if (!UseLoV1 && !UseHiV1)
8851 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8853 SDValue V1Blend, V2Blend;
8854 if (UseLoV1 && UseHiV1) {
8856 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8858 // We only use half of V1 so map the usage down into the final blend mask.
8859 V1Blend = UseLoV1 ? LoV1 : HiV1;
8860 for (int i = 0; i < SplitNumElements; ++i)
8861 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
8862 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
8864 if (UseLoV2 && UseHiV2) {
8866 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8868 // We only use half of V2 so map the usage down into the final blend mask.
8869 V2Blend = UseLoV2 ? LoV2 : HiV2;
8870 for (int i = 0; i < SplitNumElements; ++i)
8871 if (BlendMask[i] >= SplitNumElements)
8872 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
8874 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8876 SDValue Lo = HalfBlend(LoMask);
8877 SDValue Hi = HalfBlend(HiMask);
8878 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8881 /// \brief Either split a vector in halves or decompose the shuffles and the
8884 /// This is provided as a good fallback for many lowerings of non-single-input
8885 /// shuffles with more than one 128-bit lane. In those cases, we want to select
8886 /// between splitting the shuffle into 128-bit components and stitching those
8887 /// back together vs. extracting the single-input shuffles and blending those
8889 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
8890 SDValue V2, ArrayRef<int> Mask,
8891 SelectionDAG &DAG) {
8892 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
8893 "lower single-input shuffles as it "
8894 "could then recurse on itself.");
8895 int Size = Mask.size();
8897 // If this can be modeled as a broadcast of two elements followed by a blend,
8898 // prefer that lowering. This is especially important because broadcasts can
8899 // often fold with memory operands.
8900 auto DoBothBroadcast = [&] {
8901 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
8904 if (V2BroadcastIdx == -1)
8905 V2BroadcastIdx = M - Size;
8906 else if (M - Size != V2BroadcastIdx)
8908 } else if (M >= 0) {
8909 if (V1BroadcastIdx == -1)
8911 else if (M != V1BroadcastIdx)
8916 if (DoBothBroadcast())
8917 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
8920 // If the inputs all stem from a single 128-bit lane of each input, then we
8921 // split them rather than blending because the split will decompose to
8922 // unusually few instructions.
8923 int LaneCount = VT.getSizeInBits() / 128;
8924 int LaneSize = Size / LaneCount;
8925 SmallBitVector LaneInputs[2];
8926 LaneInputs[0].resize(LaneCount, false);
8927 LaneInputs[1].resize(LaneCount, false);
8928 for (int i = 0; i < Size; ++i)
8930 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
8931 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
8932 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
8934 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
8935 // that the decomposed single-input shuffles don't end up here.
8936 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
8939 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
8940 /// a permutation and blend of those lanes.
8942 /// This essentially blends the out-of-lane inputs to each lane into the lane
8943 /// from a permuted copy of the vector. This lowering strategy results in four
8944 /// instructions in the worst case for a single-input cross lane shuffle which
8945 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
8946 /// of. Special cases for each particular shuffle pattern should be handled
8947 /// prior to trying this lowering.
8948 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
8949 SDValue V1, SDValue V2,
8951 SelectionDAG &DAG) {
8952 // FIXME: This should probably be generalized for 512-bit vectors as well.
8953 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8954 int LaneSize = Mask.size() / 2;
8956 // If there are only inputs from one 128-bit lane, splitting will in fact be
8957 // less expensive. The flags track wether the given lane contains an element
8958 // that crosses to another lane.
8959 bool LaneCrossing[2] = {false, false};
8960 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8961 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
8962 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
8963 if (!LaneCrossing[0] || !LaneCrossing[1])
8964 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
8966 if (isSingleInputShuffleMask(Mask)) {
8967 SmallVector<int, 32> FlippedBlendMask;
8968 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8969 FlippedBlendMask.push_back(
8970 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
8972 : Mask[i] % LaneSize +
8973 (i / LaneSize) * LaneSize + Size));
8975 // Flip the vector, and blend the results which should now be in-lane. The
8976 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
8977 // 5 for the high source. The value 3 selects the high half of source 2 and
8978 // the value 2 selects the low half of source 2. We only use source 2 to
8979 // allow folding it into a memory operand.
8980 unsigned PERMMask = 3 | 2 << 4;
8981 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
8982 V1, DAG.getConstant(PERMMask, MVT::i8));
8983 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
8986 // This now reduces to two single-input shuffles of V1 and V2 which at worst
8987 // will be handled by the above logic and a blend of the results, much like
8988 // other patterns in AVX.
8989 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
8992 /// \brief Handle lowering 2-lane 128-bit shuffles.
8993 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8994 SDValue V2, ArrayRef<int> Mask,
8995 const X86Subtarget *Subtarget,
8996 SelectionDAG &DAG) {
8997 // Blends are faster and handle all the non-lane-crossing cases.
8998 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9002 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9003 VT.getVectorNumElements() / 2);
9004 // Check for patterns which can be matched with a single insert of a 128-bit
9006 if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1}) ||
9007 isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9008 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9009 DAG.getIntPtrConstant(0));
9010 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9011 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9012 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9014 if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 6, 7})) {
9015 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9016 DAG.getIntPtrConstant(0));
9017 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9018 DAG.getIntPtrConstant(2));
9019 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9022 // Otherwise form a 128-bit permutation.
9023 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9024 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9025 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9026 DAG.getConstant(PermMask, MVT::i8));
9029 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9030 /// shuffling each lane.
9032 /// This will only succeed when the result of fixing the 128-bit lanes results
9033 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9034 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9035 /// the lane crosses early and then use simpler shuffles within each lane.
9037 /// FIXME: It might be worthwhile at some point to support this without
9038 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9039 /// in x86 only floating point has interesting non-repeating shuffles, and even
9040 /// those are still *marginally* more expensive.
9041 static SDValue lowerVectorShuffleByMerging128BitLanes(
9042 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9043 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9044 assert(!isSingleInputShuffleMask(Mask) &&
9045 "This is only useful with multiple inputs.");
9047 int Size = Mask.size();
9048 int LaneSize = 128 / VT.getScalarSizeInBits();
9049 int NumLanes = Size / LaneSize;
9050 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9052 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9053 // check whether the in-128-bit lane shuffles share a repeating pattern.
9054 SmallVector<int, 4> Lanes;
9055 Lanes.resize(NumLanes, -1);
9056 SmallVector<int, 4> InLaneMask;
9057 InLaneMask.resize(LaneSize, -1);
9058 for (int i = 0; i < Size; ++i) {
9062 int j = i / LaneSize;
9065 // First entry we've seen for this lane.
9066 Lanes[j] = Mask[i] / LaneSize;
9067 } else if (Lanes[j] != Mask[i] / LaneSize) {
9068 // This doesn't match the lane selected previously!
9072 // Check that within each lane we have a consistent shuffle mask.
9073 int k = i % LaneSize;
9074 if (InLaneMask[k] < 0) {
9075 InLaneMask[k] = Mask[i] % LaneSize;
9076 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9077 // This doesn't fit a repeating in-lane mask.
9082 // First shuffle the lanes into place.
9083 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9084 VT.getSizeInBits() / 64);
9085 SmallVector<int, 8> LaneMask;
9086 LaneMask.resize(NumLanes * 2, -1);
9087 for (int i = 0; i < NumLanes; ++i)
9088 if (Lanes[i] >= 0) {
9089 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9090 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9093 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9094 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9095 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9097 // Cast it back to the type we actually want.
9098 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9100 // Now do a simple shuffle that isn't lane crossing.
9101 SmallVector<int, 8> NewMask;
9102 NewMask.resize(Size, -1);
9103 for (int i = 0; i < Size; ++i)
9105 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9106 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9107 "Must not introduce lane crosses at this point!");
9109 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9112 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9115 /// This returns true if the elements from a particular input are already in the
9116 /// slot required by the given mask and require no permutation.
9117 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9118 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9119 int Size = Mask.size();
9120 for (int i = 0; i < Size; ++i)
9121 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9127 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9129 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9130 /// isn't available.
9131 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9132 const X86Subtarget *Subtarget,
9133 SelectionDAG &DAG) {
9135 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9136 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9138 ArrayRef<int> Mask = SVOp->getMask();
9139 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9141 SmallVector<int, 4> WidenedMask;
9142 if (canWidenShuffleElements(Mask, WidenedMask))
9143 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9146 if (isSingleInputShuffleMask(Mask)) {
9147 // Check for being able to broadcast a single element.
9148 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9149 Mask, Subtarget, DAG))
9152 // Use low duplicate instructions for masks that match their pattern.
9153 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9154 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9156 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9157 // Non-half-crossing single input shuffles can be lowerid with an
9158 // interleaved permutation.
9159 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9160 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9161 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9162 DAG.getConstant(VPERMILPMask, MVT::i8));
9165 // With AVX2 we have direct support for this permutation.
9166 if (Subtarget->hasAVX2())
9167 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9168 getV4X86ShuffleImm8ForMask(Mask, DAG));
9170 // Otherwise, fall back.
9171 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9175 // X86 has dedicated unpack instructions that can handle specific blend
9176 // operations: UNPCKH and UNPCKL.
9177 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9178 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9179 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9180 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9181 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9182 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9183 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9184 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9186 // If we have a single input to the zero element, insert that into V1 if we
9187 // can do so cheaply.
9189 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9190 if (NumV2Elements == 1 && Mask[0] >= 4)
9191 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9192 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9195 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9199 // Check if the blend happens to exactly fit that of SHUFPD.
9200 if ((Mask[0] == -1 || Mask[0] < 2) &&
9201 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9202 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9203 (Mask[3] == -1 || Mask[3] >= 6)) {
9204 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9205 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9206 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9207 DAG.getConstant(SHUFPDMask, MVT::i8));
9209 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9210 (Mask[1] == -1 || Mask[1] < 2) &&
9211 (Mask[2] == -1 || Mask[2] >= 6) &&
9212 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9213 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9214 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9215 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9216 DAG.getConstant(SHUFPDMask, MVT::i8));
9219 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9220 // shuffle. However, if we have AVX2 and either inputs are already in place,
9221 // we will be able to shuffle even across lanes the other input in a single
9222 // instruction so skip this pattern.
9223 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9224 isShuffleMaskInputInPlace(1, Mask))))
9225 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9226 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9229 // If we have AVX2 then we always want to lower with a blend because an v4 we
9230 // can fully permute the elements.
9231 if (Subtarget->hasAVX2())
9232 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9235 // Otherwise fall back on generic lowering.
9236 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9239 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9241 /// This routine is only called when we have AVX2 and thus a reasonable
9242 /// instruction set for v4i64 shuffling..
9243 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9244 const X86Subtarget *Subtarget,
9245 SelectionDAG &DAG) {
9247 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9248 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9249 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9250 ArrayRef<int> Mask = SVOp->getMask();
9251 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9252 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9254 SmallVector<int, 4> WidenedMask;
9255 if (canWidenShuffleElements(Mask, WidenedMask))
9256 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9259 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9263 // Check for being able to broadcast a single element.
9264 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9265 Mask, Subtarget, DAG))
9268 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9269 // use lower latency instructions that will operate on both 128-bit lanes.
9270 SmallVector<int, 2> RepeatedMask;
9271 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9272 if (isSingleInputShuffleMask(Mask)) {
9273 int PSHUFDMask[] = {-1, -1, -1, -1};
9274 for (int i = 0; i < 2; ++i)
9275 if (RepeatedMask[i] >= 0) {
9276 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9277 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9280 ISD::BITCAST, DL, MVT::v4i64,
9281 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9282 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9283 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9287 // AVX2 provides a direct instruction for permuting a single input across
9289 if (isSingleInputShuffleMask(Mask))
9290 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9291 getV4X86ShuffleImm8ForMask(Mask, DAG));
9293 // Try to use shift instructions.
9295 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9298 // Use dedicated unpack instructions for masks that match their pattern.
9299 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9300 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9301 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9302 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9303 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9304 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9305 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9306 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9308 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9309 // shuffle. However, if we have AVX2 and either inputs are already in place,
9310 // we will be able to shuffle even across lanes the other input in a single
9311 // instruction so skip this pattern.
9312 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9313 isShuffleMaskInputInPlace(1, Mask))))
9314 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9315 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9318 // Otherwise fall back on generic blend lowering.
9319 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9323 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9325 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9326 /// isn't available.
9327 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9328 const X86Subtarget *Subtarget,
9329 SelectionDAG &DAG) {
9331 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9332 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9334 ArrayRef<int> Mask = SVOp->getMask();
9335 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9337 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9341 // Check for being able to broadcast a single element.
9342 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9343 Mask, Subtarget, DAG))
9346 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9347 // options to efficiently lower the shuffle.
9348 SmallVector<int, 4> RepeatedMask;
9349 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9350 assert(RepeatedMask.size() == 4 &&
9351 "Repeated masks must be half the mask width!");
9353 // Use even/odd duplicate instructions for masks that match their pattern.
9354 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9355 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9356 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9357 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9359 if (isSingleInputShuffleMask(Mask))
9360 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9361 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9363 // Use dedicated unpack instructions for masks that match their pattern.
9364 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9365 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9366 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9367 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9368 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9369 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9370 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9371 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9373 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9374 // have already handled any direct blends. We also need to squash the
9375 // repeated mask into a simulated v4f32 mask.
9376 for (int i = 0; i < 4; ++i)
9377 if (RepeatedMask[i] >= 8)
9378 RepeatedMask[i] -= 4;
9379 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9382 // If we have a single input shuffle with different shuffle patterns in the
9383 // two 128-bit lanes use the variable mask to VPERMILPS.
9384 if (isSingleInputShuffleMask(Mask)) {
9385 SDValue VPermMask[8];
9386 for (int i = 0; i < 8; ++i)
9387 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9388 : DAG.getConstant(Mask[i], MVT::i32);
9389 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9391 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9392 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9394 if (Subtarget->hasAVX2())
9395 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9396 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9397 DAG.getNode(ISD::BUILD_VECTOR, DL,
9398 MVT::v8i32, VPermMask)),
9401 // Otherwise, fall back.
9402 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9406 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9408 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9409 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9412 // If we have AVX2 then we always want to lower with a blend because at v8 we
9413 // can fully permute the elements.
9414 if (Subtarget->hasAVX2())
9415 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9418 // Otherwise fall back on generic lowering.
9419 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9422 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9424 /// This routine is only called when we have AVX2 and thus a reasonable
9425 /// instruction set for v8i32 shuffling..
9426 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9427 const X86Subtarget *Subtarget,
9428 SelectionDAG &DAG) {
9430 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9431 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9432 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9433 ArrayRef<int> Mask = SVOp->getMask();
9434 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9435 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9437 // Whenever we can lower this as a zext, that instruction is strictly faster
9438 // than any alternative. It also allows us to fold memory operands into the
9439 // shuffle in many cases.
9440 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9441 Mask, Subtarget, DAG))
9444 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9448 // Check for being able to broadcast a single element.
9449 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9450 Mask, Subtarget, DAG))
9453 // If the shuffle mask is repeated in each 128-bit lane we can use more
9454 // efficient instructions that mirror the shuffles across the two 128-bit
9456 SmallVector<int, 4> RepeatedMask;
9457 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9458 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9459 if (isSingleInputShuffleMask(Mask))
9460 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9461 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9463 // Use dedicated unpack instructions for masks that match their pattern.
9464 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9465 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9466 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9467 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9468 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9469 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9470 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9471 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9474 // Try to use shift instructions.
9476 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9479 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9480 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9483 // If the shuffle patterns aren't repeated but it is a single input, directly
9484 // generate a cross-lane VPERMD instruction.
9485 if (isSingleInputShuffleMask(Mask)) {
9486 SDValue VPermMask[8];
9487 for (int i = 0; i < 8; ++i)
9488 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9489 : DAG.getConstant(Mask[i], MVT::i32);
9491 X86ISD::VPERMV, DL, MVT::v8i32,
9492 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9495 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9497 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9498 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9501 // Otherwise fall back on generic blend lowering.
9502 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9506 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9508 /// This routine is only called when we have AVX2 and thus a reasonable
9509 /// instruction set for v16i16 shuffling..
9510 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9511 const X86Subtarget *Subtarget,
9512 SelectionDAG &DAG) {
9514 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9515 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9516 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9517 ArrayRef<int> Mask = SVOp->getMask();
9518 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9519 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9521 // Whenever we can lower this as a zext, that instruction is strictly faster
9522 // than any alternative. It also allows us to fold memory operands into the
9523 // shuffle in many cases.
9524 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9525 Mask, Subtarget, DAG))
9528 // Check for being able to broadcast a single element.
9529 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9530 Mask, Subtarget, DAG))
9533 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9537 // Use dedicated unpack instructions for masks that match their pattern.
9538 if (isShuffleEquivalent(V1, V2, Mask,
9539 {// First 128-bit lane:
9540 0, 16, 1, 17, 2, 18, 3, 19,
9541 // Second 128-bit lane:
9542 8, 24, 9, 25, 10, 26, 11, 27}))
9543 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9544 if (isShuffleEquivalent(V1, V2, Mask,
9545 {// First 128-bit lane:
9546 4, 20, 5, 21, 6, 22, 7, 23,
9547 // Second 128-bit lane:
9548 12, 28, 13, 29, 14, 30, 15, 31}))
9549 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9551 // Try to use shift instructions.
9553 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9556 // Try to use byte rotation instructions.
9557 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9558 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9561 if (isSingleInputShuffleMask(Mask)) {
9562 // There are no generalized cross-lane shuffle operations available on i16
9564 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9565 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9568 SmallVector<int, 8> RepeatedMask;
9569 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9570 // As this is a single-input shuffle, the repeated mask should be
9571 // a strictly valid v8i16 mask that we can pass through to the v8i16
9572 // lowering to handle even the v16 case.
9573 return lowerV8I16GeneralSingleInputVectorShuffle(
9574 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9577 SDValue PSHUFBMask[32];
9578 for (int i = 0; i < 16; ++i) {
9579 if (Mask[i] == -1) {
9580 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9584 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9585 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9586 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9587 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9590 ISD::BITCAST, DL, MVT::v16i16,
9592 X86ISD::PSHUFB, DL, MVT::v32i8,
9593 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9594 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9597 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9599 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9600 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9603 // Otherwise fall back on generic lowering.
9604 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9607 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9609 /// This routine is only called when we have AVX2 and thus a reasonable
9610 /// instruction set for v32i8 shuffling..
9611 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9612 const X86Subtarget *Subtarget,
9613 SelectionDAG &DAG) {
9615 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9616 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9617 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9618 ArrayRef<int> Mask = SVOp->getMask();
9619 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9620 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9622 // Whenever we can lower this as a zext, that instruction is strictly faster
9623 // than any alternative. It also allows us to fold memory operands into the
9624 // shuffle in many cases.
9625 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9626 Mask, Subtarget, DAG))
9629 // Check for being able to broadcast a single element.
9630 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9631 Mask, Subtarget, DAG))
9634 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9638 // Use dedicated unpack instructions for masks that match their pattern.
9639 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9641 if (isShuffleEquivalent(
9643 {// First 128-bit lane:
9644 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9645 // Second 128-bit lane:
9646 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9647 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9648 if (isShuffleEquivalent(
9650 {// First 128-bit lane:
9651 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9652 // Second 128-bit lane:
9653 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9654 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9656 // Try to use shift instructions.
9658 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9661 // Try to use byte rotation instructions.
9662 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9663 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9666 if (isSingleInputShuffleMask(Mask)) {
9667 // There are no generalized cross-lane shuffle operations available on i8
9669 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9670 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9673 SDValue PSHUFBMask[32];
9674 for (int i = 0; i < 32; ++i)
9677 ? DAG.getUNDEF(MVT::i8)
9678 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9681 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9682 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9685 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9687 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9688 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9691 // Otherwise fall back on generic lowering.
9692 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9695 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9697 /// This routine either breaks down the specific type of a 256-bit x86 vector
9698 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9699 /// together based on the available instructions.
9700 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9701 MVT VT, const X86Subtarget *Subtarget,
9702 SelectionDAG &DAG) {
9704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9705 ArrayRef<int> Mask = SVOp->getMask();
9707 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9708 // check for those subtargets here and avoid much of the subtarget querying in
9709 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9710 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9711 // floating point types there eventually, just immediately cast everything to
9712 // a float and operate entirely in that domain.
9713 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9714 int ElementBits = VT.getScalarSizeInBits();
9715 if (ElementBits < 32)
9716 // No floating point type available, decompose into 128-bit vectors.
9717 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9719 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9720 VT.getVectorNumElements());
9721 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9722 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9723 return DAG.getNode(ISD::BITCAST, DL, VT,
9724 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9727 switch (VT.SimpleTy) {
9729 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9731 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9733 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9735 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9737 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9739 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9742 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9746 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9747 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9748 const X86Subtarget *Subtarget,
9749 SelectionDAG &DAG) {
9751 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9752 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9753 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9754 ArrayRef<int> Mask = SVOp->getMask();
9755 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9757 // X86 has dedicated unpack instructions that can handle specific blend
9758 // operations: UNPCKH and UNPCKL.
9759 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9760 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
9761 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9762 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
9764 // FIXME: Implement direct support for this type!
9765 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9768 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9769 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9770 const X86Subtarget *Subtarget,
9771 SelectionDAG &DAG) {
9773 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9774 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9775 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9776 ArrayRef<int> Mask = SVOp->getMask();
9777 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9779 // Use dedicated unpack instructions for masks that match their pattern.
9780 if (isShuffleEquivalent(V1, V2, Mask,
9781 {// First 128-bit lane.
9782 0, 16, 1, 17, 4, 20, 5, 21,
9783 // Second 128-bit lane.
9784 8, 24, 9, 25, 12, 28, 13, 29}))
9785 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
9786 if (isShuffleEquivalent(V1, V2, Mask,
9787 {// First 128-bit lane.
9788 2, 18, 3, 19, 6, 22, 7, 23,
9789 // Second 128-bit lane.
9790 10, 26, 11, 27, 14, 30, 15, 31}))
9791 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
9793 // FIXME: Implement direct support for this type!
9794 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9797 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9798 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9799 const X86Subtarget *Subtarget,
9800 SelectionDAG &DAG) {
9802 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9803 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9804 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9805 ArrayRef<int> Mask = SVOp->getMask();
9806 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9808 // X86 has dedicated unpack instructions that can handle specific blend
9809 // operations: UNPCKH and UNPCKL.
9810 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9811 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
9812 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9813 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
9815 // FIXME: Implement direct support for this type!
9816 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9819 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9820 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9821 const X86Subtarget *Subtarget,
9822 SelectionDAG &DAG) {
9824 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9825 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9826 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9827 ArrayRef<int> Mask = SVOp->getMask();
9828 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9830 // Use dedicated unpack instructions for masks that match their pattern.
9831 if (isShuffleEquivalent(V1, V2, Mask,
9832 {// First 128-bit lane.
9833 0, 16, 1, 17, 4, 20, 5, 21,
9834 // Second 128-bit lane.
9835 8, 24, 9, 25, 12, 28, 13, 29}))
9836 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
9837 if (isShuffleEquivalent(V1, V2, Mask,
9838 {// First 128-bit lane.
9839 2, 18, 3, 19, 6, 22, 7, 23,
9840 // Second 128-bit lane.
9841 10, 26, 11, 27, 14, 30, 15, 31}))
9842 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
9844 // FIXME: Implement direct support for this type!
9845 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
9848 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
9849 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9850 const X86Subtarget *Subtarget,
9851 SelectionDAG &DAG) {
9853 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9854 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9855 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9856 ArrayRef<int> Mask = SVOp->getMask();
9857 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9858 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
9860 // FIXME: Implement direct support for this type!
9861 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
9864 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
9865 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9866 const X86Subtarget *Subtarget,
9867 SelectionDAG &DAG) {
9869 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9870 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9871 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9872 ArrayRef<int> Mask = SVOp->getMask();
9873 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
9874 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
9876 // FIXME: Implement direct support for this type!
9877 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
9880 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
9882 /// This routine either breaks down the specific type of a 512-bit x86 vector
9883 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
9884 /// together based on the available instructions.
9885 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9886 MVT VT, const X86Subtarget *Subtarget,
9887 SelectionDAG &DAG) {
9889 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9890 ArrayRef<int> Mask = SVOp->getMask();
9891 assert(Subtarget->hasAVX512() &&
9892 "Cannot lower 512-bit vectors w/ basic ISA!");
9894 // Check for being able to broadcast a single element.
9895 if (SDValue Broadcast =
9896 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
9899 // Dispatch to each element type for lowering. If we don't have supprot for
9900 // specific element type shuffles at 512 bits, immediately split them and
9901 // lower them. Each lowering routine of a given type is allowed to assume that
9902 // the requisite ISA extensions for that element type are available.
9903 switch (VT.SimpleTy) {
9905 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9907 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9909 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9911 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9913 if (Subtarget->hasBWI())
9914 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9917 if (Subtarget->hasBWI())
9918 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9922 llvm_unreachable("Not a valid 512-bit x86 vector type!");
9925 // Otherwise fall back on splitting.
9926 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9929 /// \brief Top-level lowering for x86 vector shuffles.
9931 /// This handles decomposition, canonicalization, and lowering of all x86
9932 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9933 /// above in helper routines. The canonicalization attempts to widen shuffles
9934 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9935 /// s.t. only one of the two inputs needs to be tested, etc.
9936 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9937 SelectionDAG &DAG) {
9938 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9939 ArrayRef<int> Mask = SVOp->getMask();
9940 SDValue V1 = Op.getOperand(0);
9941 SDValue V2 = Op.getOperand(1);
9942 MVT VT = Op.getSimpleValueType();
9943 int NumElements = VT.getVectorNumElements();
9946 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9948 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9949 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9950 if (V1IsUndef && V2IsUndef)
9951 return DAG.getUNDEF(VT);
9953 // When we create a shuffle node we put the UNDEF node to second operand,
9954 // but in some cases the first operand may be transformed to UNDEF.
9955 // In this case we should just commute the node.
9957 return DAG.getCommutedVectorShuffle(*SVOp);
9959 // Check for non-undef masks pointing at an undef vector and make the masks
9960 // undef as well. This makes it easier to match the shuffle based solely on
9964 if (M >= NumElements) {
9965 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9966 for (int &M : NewMask)
9967 if (M >= NumElements)
9969 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9972 // We actually see shuffles that are entirely re-arrangements of a set of
9973 // zero inputs. This mostly happens while decomposing complex shuffles into
9974 // simple ones. Directly lower these as a buildvector of zeros.
9975 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9977 return getZeroVector(VT, Subtarget, DAG, dl);
9979 // Try to collapse shuffles into using a vector type with fewer elements but
9980 // wider element types. We cap this to not form integers or floating point
9981 // elements wider than 64 bits, but it might be interesting to form i128
9982 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
9983 SmallVector<int, 16> WidenedMask;
9984 if (VT.getScalarSizeInBits() < 64 &&
9985 canWidenShuffleElements(Mask, WidenedMask)) {
9986 MVT NewEltVT = VT.isFloatingPoint()
9987 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
9988 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
9989 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
9990 // Make sure that the new vector type is legal. For example, v2f64 isn't
9992 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
9993 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9994 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9995 return DAG.getNode(ISD::BITCAST, dl, VT,
9996 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10000 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10001 for (int M : SVOp->getMask())
10003 ++NumUndefElements;
10004 else if (M < NumElements)
10009 // Commute the shuffle as needed such that more elements come from V1 than
10010 // V2. This allows us to match the shuffle pattern strictly on how many
10011 // elements come from V1 without handling the symmetric cases.
10012 if (NumV2Elements > NumV1Elements)
10013 return DAG.getCommutedVectorShuffle(*SVOp);
10015 // When the number of V1 and V2 elements are the same, try to minimize the
10016 // number of uses of V2 in the low half of the vector. When that is tied,
10017 // ensure that the sum of indices for V1 is equal to or lower than the sum
10018 // indices for V2. When those are equal, try to ensure that the number of odd
10019 // indices for V1 is lower than the number of odd indices for V2.
10020 if (NumV1Elements == NumV2Elements) {
10021 int LowV1Elements = 0, LowV2Elements = 0;
10022 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10023 if (M >= NumElements)
10027 if (LowV2Elements > LowV1Elements) {
10028 return DAG.getCommutedVectorShuffle(*SVOp);
10029 } else if (LowV2Elements == LowV1Elements) {
10030 int SumV1Indices = 0, SumV2Indices = 0;
10031 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10032 if (SVOp->getMask()[i] >= NumElements)
10034 else if (SVOp->getMask()[i] >= 0)
10036 if (SumV2Indices < SumV1Indices) {
10037 return DAG.getCommutedVectorShuffle(*SVOp);
10038 } else if (SumV2Indices == SumV1Indices) {
10039 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10040 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10041 if (SVOp->getMask()[i] >= NumElements)
10042 NumV2OddIndices += i % 2;
10043 else if (SVOp->getMask()[i] >= 0)
10044 NumV1OddIndices += i % 2;
10045 if (NumV2OddIndices < NumV1OddIndices)
10046 return DAG.getCommutedVectorShuffle(*SVOp);
10051 // For each vector width, delegate to a specialized lowering routine.
10052 if (VT.getSizeInBits() == 128)
10053 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10055 if (VT.getSizeInBits() == 256)
10056 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10058 // Force AVX-512 vectors to be scalarized for now.
10059 // FIXME: Implement AVX-512 support!
10060 if (VT.getSizeInBits() == 512)
10061 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10063 llvm_unreachable("Unimplemented!");
10066 // This function assumes its argument is a BUILD_VECTOR of constants or
10067 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10069 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10070 unsigned &MaskValue) {
10072 unsigned NumElems = BuildVector->getNumOperands();
10073 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10074 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10075 unsigned NumElemsInLane = NumElems / NumLanes;
10077 // Blend for v16i16 should be symetric for the both lanes.
10078 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10079 SDValue EltCond = BuildVector->getOperand(i);
10080 SDValue SndLaneEltCond =
10081 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10083 int Lane1Cond = -1, Lane2Cond = -1;
10084 if (isa<ConstantSDNode>(EltCond))
10085 Lane1Cond = !isZero(EltCond);
10086 if (isa<ConstantSDNode>(SndLaneEltCond))
10087 Lane2Cond = !isZero(SndLaneEltCond);
10089 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10090 // Lane1Cond != 0, means we want the first argument.
10091 // Lane1Cond == 0, means we want the second argument.
10092 // The encoding of this argument is 0 for the first argument, 1
10093 // for the second. Therefore, invert the condition.
10094 MaskValue |= !Lane1Cond << i;
10095 else if (Lane1Cond < 0)
10096 MaskValue |= !Lane2Cond << i;
10103 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10104 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10105 const X86Subtarget *Subtarget,
10106 SelectionDAG &DAG) {
10107 SDValue Cond = Op.getOperand(0);
10108 SDValue LHS = Op.getOperand(1);
10109 SDValue RHS = Op.getOperand(2);
10111 MVT VT = Op.getSimpleValueType();
10113 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10115 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10117 // Only non-legal VSELECTs reach this lowering, convert those into generic
10118 // shuffles and re-use the shuffle lowering path for blends.
10119 SmallVector<int, 32> Mask;
10120 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10121 SDValue CondElt = CondBV->getOperand(i);
10123 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10125 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10128 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10129 // A vselect where all conditions and data are constants can be optimized into
10130 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10131 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10132 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10133 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10136 // Try to lower this to a blend-style vector shuffle. This can handle all
10137 // constant condition cases.
10138 SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG);
10139 if (BlendOp.getNode())
10142 // Variable blends are only legal from SSE4.1 onward.
10143 if (!Subtarget->hasSSE41())
10146 // Only some types will be legal on some subtargets. If we can emit a legal
10147 // VSELECT-matching blend, return Op, and but if we need to expand, return
10149 switch (Op.getSimpleValueType().SimpleTy) {
10151 // Most of the vector types have blends past SSE4.1.
10155 // The byte blends for AVX vectors were introduced only in AVX2.
10156 if (Subtarget->hasAVX2())
10163 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10164 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10167 // FIXME: We should custom lower this by fixing the condition and using i8
10173 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10174 MVT VT = Op.getSimpleValueType();
10177 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10180 if (VT.getSizeInBits() == 8) {
10181 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10182 Op.getOperand(0), Op.getOperand(1));
10183 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10184 DAG.getValueType(VT));
10185 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10188 if (VT.getSizeInBits() == 16) {
10189 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10190 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10192 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10193 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10194 DAG.getNode(ISD::BITCAST, dl,
10197 Op.getOperand(1)));
10198 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10199 Op.getOperand(0), Op.getOperand(1));
10200 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10201 DAG.getValueType(VT));
10202 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10205 if (VT == MVT::f32) {
10206 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10207 // the result back to FR32 register. It's only worth matching if the
10208 // result has a single use which is a store or a bitcast to i32. And in
10209 // the case of a store, it's not worth it if the index is a constant 0,
10210 // because a MOVSSmr can be used instead, which is smaller and faster.
10211 if (!Op.hasOneUse())
10213 SDNode *User = *Op.getNode()->use_begin();
10214 if ((User->getOpcode() != ISD::STORE ||
10215 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10216 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10217 (User->getOpcode() != ISD::BITCAST ||
10218 User->getValueType(0) != MVT::i32))
10220 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10221 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10224 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10227 if (VT == MVT::i32 || VT == MVT::i64) {
10228 // ExtractPS/pextrq works with constant index.
10229 if (isa<ConstantSDNode>(Op.getOperand(1)))
10235 /// Extract one bit from mask vector, like v16i1 or v8i1.
10236 /// AVX-512 feature.
10238 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10239 SDValue Vec = Op.getOperand(0);
10241 MVT VecVT = Vec.getSimpleValueType();
10242 SDValue Idx = Op.getOperand(1);
10243 MVT EltVT = Op.getSimpleValueType();
10245 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10246 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10247 "Unexpected vector type in ExtractBitFromMaskVector");
10249 // variable index can't be handled in mask registers,
10250 // extend vector to VR512
10251 if (!isa<ConstantSDNode>(Idx)) {
10252 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10253 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10254 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10255 ExtVT.getVectorElementType(), Ext, Idx);
10256 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10259 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10260 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10261 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10262 rc = getRegClassFor(MVT::v16i1);
10263 unsigned MaxSift = rc->getSize()*8 - 1;
10264 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10265 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10266 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10267 DAG.getConstant(MaxSift, MVT::i8));
10268 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10269 DAG.getIntPtrConstant(0));
10273 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10274 SelectionDAG &DAG) const {
10276 SDValue Vec = Op.getOperand(0);
10277 MVT VecVT = Vec.getSimpleValueType();
10278 SDValue Idx = Op.getOperand(1);
10280 if (Op.getSimpleValueType() == MVT::i1)
10281 return ExtractBitFromMaskVector(Op, DAG);
10283 if (!isa<ConstantSDNode>(Idx)) {
10284 if (VecVT.is512BitVector() ||
10285 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10286 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10289 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10290 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10291 MaskEltVT.getSizeInBits());
10293 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10294 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10295 getZeroVector(MaskVT, Subtarget, DAG, dl),
10296 Idx, DAG.getConstant(0, getPointerTy()));
10297 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10298 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10299 Perm, DAG.getConstant(0, getPointerTy()));
10304 // If this is a 256-bit vector result, first extract the 128-bit vector and
10305 // then extract the element from the 128-bit vector.
10306 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10308 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10309 // Get the 128-bit vector.
10310 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10311 MVT EltVT = VecVT.getVectorElementType();
10313 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10315 //if (IdxVal >= NumElems/2)
10316 // IdxVal -= NumElems/2;
10317 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10319 DAG.getConstant(IdxVal, MVT::i32));
10322 assert(VecVT.is128BitVector() && "Unexpected vector length");
10324 if (Subtarget->hasSSE41()) {
10325 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10330 MVT VT = Op.getSimpleValueType();
10331 // TODO: handle v16i8.
10332 if (VT.getSizeInBits() == 16) {
10333 SDValue Vec = Op.getOperand(0);
10334 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10336 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10337 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10338 DAG.getNode(ISD::BITCAST, dl,
10340 Op.getOperand(1)));
10341 // Transform it so it match pextrw which produces a 32-bit result.
10342 MVT EltVT = MVT::i32;
10343 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10344 Op.getOperand(0), Op.getOperand(1));
10345 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10346 DAG.getValueType(VT));
10347 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10350 if (VT.getSizeInBits() == 32) {
10351 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10355 // SHUFPS the element to the lowest double word, then movss.
10356 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10357 MVT VVT = Op.getOperand(0).getSimpleValueType();
10358 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10359 DAG.getUNDEF(VVT), Mask);
10360 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10361 DAG.getIntPtrConstant(0));
10364 if (VT.getSizeInBits() == 64) {
10365 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10366 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10367 // to match extract_elt for f64.
10368 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10372 // UNPCKHPD the element to the lowest double word, then movsd.
10373 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10374 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10375 int Mask[2] = { 1, -1 };
10376 MVT VVT = Op.getOperand(0).getSimpleValueType();
10377 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10378 DAG.getUNDEF(VVT), Mask);
10379 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10380 DAG.getIntPtrConstant(0));
10386 /// Insert one bit to mask vector, like v16i1 or v8i1.
10387 /// AVX-512 feature.
10389 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10391 SDValue Vec = Op.getOperand(0);
10392 SDValue Elt = Op.getOperand(1);
10393 SDValue Idx = Op.getOperand(2);
10394 MVT VecVT = Vec.getSimpleValueType();
10396 if (!isa<ConstantSDNode>(Idx)) {
10397 // Non constant index. Extend source and destination,
10398 // insert element and then truncate the result.
10399 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10400 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10401 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10402 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10403 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10404 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10407 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10408 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10409 if (Vec.getOpcode() == ISD::UNDEF)
10410 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10411 DAG.getConstant(IdxVal, MVT::i8));
10412 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10413 unsigned MaxSift = rc->getSize()*8 - 1;
10414 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10415 DAG.getConstant(MaxSift, MVT::i8));
10416 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10417 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10418 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10421 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10422 SelectionDAG &DAG) const {
10423 MVT VT = Op.getSimpleValueType();
10424 MVT EltVT = VT.getVectorElementType();
10426 if (EltVT == MVT::i1)
10427 return InsertBitToMaskVector(Op, DAG);
10430 SDValue N0 = Op.getOperand(0);
10431 SDValue N1 = Op.getOperand(1);
10432 SDValue N2 = Op.getOperand(2);
10433 if (!isa<ConstantSDNode>(N2))
10435 auto *N2C = cast<ConstantSDNode>(N2);
10436 unsigned IdxVal = N2C->getZExtValue();
10438 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10439 // into that, and then insert the subvector back into the result.
10440 if (VT.is256BitVector() || VT.is512BitVector()) {
10441 // Get the desired 128-bit vector half.
10442 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10444 // Insert the element into the desired half.
10445 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10446 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10448 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10449 DAG.getConstant(IdxIn128, MVT::i32));
10451 // Insert the changed part back to the 256-bit vector
10452 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10454 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10456 if (Subtarget->hasSSE41()) {
10457 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10459 if (VT == MVT::v8i16) {
10460 Opc = X86ISD::PINSRW;
10462 assert(VT == MVT::v16i8);
10463 Opc = X86ISD::PINSRB;
10466 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10468 if (N1.getValueType() != MVT::i32)
10469 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10470 if (N2.getValueType() != MVT::i32)
10471 N2 = DAG.getIntPtrConstant(IdxVal);
10472 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10475 if (EltVT == MVT::f32) {
10476 // Bits [7:6] of the constant are the source select. This will always be
10477 // zero here. The DAG Combiner may combine an extract_elt index into
10479 // bits. For example (insert (extract, 3), 2) could be matched by
10481 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10482 // Bits [5:4] of the constant are the destination select. This is the
10483 // value of the incoming immediate.
10484 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10485 // combine either bitwise AND or insert of float 0.0 to set these bits.
10486 N2 = DAG.getIntPtrConstant(IdxVal << 4);
10487 // Create this as a scalar to vector..
10488 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10489 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10492 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10493 // PINSR* works with constant index.
10498 if (EltVT == MVT::i8)
10501 if (EltVT.getSizeInBits() == 16) {
10502 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10503 // as its second argument.
10504 if (N1.getValueType() != MVT::i32)
10505 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10506 if (N2.getValueType() != MVT::i32)
10507 N2 = DAG.getIntPtrConstant(IdxVal);
10508 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10513 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10515 MVT OpVT = Op.getSimpleValueType();
10517 // If this is a 256-bit vector result, first insert into a 128-bit
10518 // vector and then insert into the 256-bit vector.
10519 if (!OpVT.is128BitVector()) {
10520 // Insert into a 128-bit vector.
10521 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10522 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10523 OpVT.getVectorNumElements() / SizeFactor);
10525 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10527 // Insert the 128-bit vector.
10528 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10531 if (OpVT == MVT::v1i64 &&
10532 Op.getOperand(0).getValueType() == MVT::i64)
10533 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10535 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10536 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10537 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10538 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10541 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10542 // a simple subregister reference or explicit instructions to grab
10543 // upper bits of a vector.
10544 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10545 SelectionDAG &DAG) {
10547 SDValue In = Op.getOperand(0);
10548 SDValue Idx = Op.getOperand(1);
10549 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10550 MVT ResVT = Op.getSimpleValueType();
10551 MVT InVT = In.getSimpleValueType();
10553 if (Subtarget->hasFp256()) {
10554 if (ResVT.is128BitVector() &&
10555 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10556 isa<ConstantSDNode>(Idx)) {
10557 return Extract128BitVector(In, IdxVal, DAG, dl);
10559 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10560 isa<ConstantSDNode>(Idx)) {
10561 return Extract256BitVector(In, IdxVal, DAG, dl);
10567 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10568 // simple superregister reference or explicit instructions to insert
10569 // the upper bits of a vector.
10570 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10571 SelectionDAG &DAG) {
10572 if (!Subtarget->hasAVX())
10576 SDValue Vec = Op.getOperand(0);
10577 SDValue SubVec = Op.getOperand(1);
10578 SDValue Idx = Op.getOperand(2);
10580 if (!isa<ConstantSDNode>(Idx))
10583 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10584 MVT OpVT = Op.getSimpleValueType();
10585 MVT SubVecVT = SubVec.getSimpleValueType();
10587 // Fold two 16-byte subvector loads into one 32-byte load:
10588 // (insert_subvector (insert_subvector undef, (load addr), 0),
10589 // (load addr + 16), Elts/2)
10591 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10592 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10593 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10594 !Subtarget->isUnalignedMem32Slow()) {
10595 SDValue SubVec2 = Vec.getOperand(1);
10596 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10597 if (Idx2->getZExtValue() == 0) {
10598 SDValue Ops[] = { SubVec2, SubVec };
10599 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10606 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10607 SubVecVT.is128BitVector())
10608 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10610 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10611 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10616 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10617 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10618 // one of the above mentioned nodes. It has to be wrapped because otherwise
10619 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10620 // be used to form addressing mode. These wrapped nodes will be selected
10623 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10624 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10626 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10627 // global base reg.
10628 unsigned char OpFlag = 0;
10629 unsigned WrapperKind = X86ISD::Wrapper;
10630 CodeModel::Model M = DAG.getTarget().getCodeModel();
10632 if (Subtarget->isPICStyleRIPRel() &&
10633 (M == CodeModel::Small || M == CodeModel::Kernel))
10634 WrapperKind = X86ISD::WrapperRIP;
10635 else if (Subtarget->isPICStyleGOT())
10636 OpFlag = X86II::MO_GOTOFF;
10637 else if (Subtarget->isPICStyleStubPIC())
10638 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10640 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10641 CP->getAlignment(),
10642 CP->getOffset(), OpFlag);
10644 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10645 // With PIC, the address is actually $g + Offset.
10647 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10648 DAG.getNode(X86ISD::GlobalBaseReg,
10649 SDLoc(), getPointerTy()),
10656 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10657 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10659 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10660 // global base reg.
10661 unsigned char OpFlag = 0;
10662 unsigned WrapperKind = X86ISD::Wrapper;
10663 CodeModel::Model M = DAG.getTarget().getCodeModel();
10665 if (Subtarget->isPICStyleRIPRel() &&
10666 (M == CodeModel::Small || M == CodeModel::Kernel))
10667 WrapperKind = X86ISD::WrapperRIP;
10668 else if (Subtarget->isPICStyleGOT())
10669 OpFlag = X86II::MO_GOTOFF;
10670 else if (Subtarget->isPICStyleStubPIC())
10671 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10673 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10676 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10678 // With PIC, the address is actually $g + Offset.
10680 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10681 DAG.getNode(X86ISD::GlobalBaseReg,
10682 SDLoc(), getPointerTy()),
10689 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10690 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10692 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10693 // global base reg.
10694 unsigned char OpFlag = 0;
10695 unsigned WrapperKind = X86ISD::Wrapper;
10696 CodeModel::Model M = DAG.getTarget().getCodeModel();
10698 if (Subtarget->isPICStyleRIPRel() &&
10699 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10700 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10701 OpFlag = X86II::MO_GOTPCREL;
10702 WrapperKind = X86ISD::WrapperRIP;
10703 } else if (Subtarget->isPICStyleGOT()) {
10704 OpFlag = X86II::MO_GOT;
10705 } else if (Subtarget->isPICStyleStubPIC()) {
10706 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10707 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10708 OpFlag = X86II::MO_DARWIN_NONLAZY;
10711 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10714 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10716 // With PIC, the address is actually $g + Offset.
10717 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10718 !Subtarget->is64Bit()) {
10719 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10720 DAG.getNode(X86ISD::GlobalBaseReg,
10721 SDLoc(), getPointerTy()),
10725 // For symbols that require a load from a stub to get the address, emit the
10727 if (isGlobalStubReference(OpFlag))
10728 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10729 MachinePointerInfo::getGOT(), false, false, false, 0);
10735 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10736 // Create the TargetBlockAddressAddress node.
10737 unsigned char OpFlags =
10738 Subtarget->ClassifyBlockAddressReference();
10739 CodeModel::Model M = DAG.getTarget().getCodeModel();
10740 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10741 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10743 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10746 if (Subtarget->isPICStyleRIPRel() &&
10747 (M == CodeModel::Small || M == CodeModel::Kernel))
10748 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10750 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10752 // With PIC, the address is actually $g + Offset.
10753 if (isGlobalRelativeToPICBase(OpFlags)) {
10754 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10755 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10763 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10764 int64_t Offset, SelectionDAG &DAG) const {
10765 // Create the TargetGlobalAddress node, folding in the constant
10766 // offset if it is legal.
10767 unsigned char OpFlags =
10768 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10769 CodeModel::Model M = DAG.getTarget().getCodeModel();
10771 if (OpFlags == X86II::MO_NO_FLAG &&
10772 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10773 // A direct static reference to a global.
10774 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10777 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10780 if (Subtarget->isPICStyleRIPRel() &&
10781 (M == CodeModel::Small || M == CodeModel::Kernel))
10782 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10784 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10786 // With PIC, the address is actually $g + Offset.
10787 if (isGlobalRelativeToPICBase(OpFlags)) {
10788 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10789 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10793 // For globals that require a load from a stub to get the address, emit the
10795 if (isGlobalStubReference(OpFlags))
10796 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10797 MachinePointerInfo::getGOT(), false, false, false, 0);
10799 // If there was a non-zero offset that we didn't fold, create an explicit
10800 // addition for it.
10802 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10803 DAG.getConstant(Offset, getPointerTy()));
10809 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10810 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10811 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10812 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10816 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10817 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10818 unsigned char OperandFlags, bool LocalDynamic = false) {
10819 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10820 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10822 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10823 GA->getValueType(0),
10827 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10831 SDValue Ops[] = { Chain, TGA, *InFlag };
10832 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10834 SDValue Ops[] = { Chain, TGA };
10835 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10838 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10839 MFI->setAdjustsStack(true);
10840 MFI->setHasCalls(true);
10842 SDValue Flag = Chain.getValue(1);
10843 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10846 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10848 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10851 SDLoc dl(GA); // ? function entry point might be better
10852 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10853 DAG.getNode(X86ISD::GlobalBaseReg,
10854 SDLoc(), PtrVT), InFlag);
10855 InFlag = Chain.getValue(1);
10857 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10860 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10862 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10864 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10865 X86::RAX, X86II::MO_TLSGD);
10868 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10874 // Get the start address of the TLS block for this module.
10875 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10876 .getInfo<X86MachineFunctionInfo>();
10877 MFI->incNumLocalDynamicTLSAccesses();
10881 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10882 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10885 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10886 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10887 InFlag = Chain.getValue(1);
10888 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10889 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10892 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10896 unsigned char OperandFlags = X86II::MO_DTPOFF;
10897 unsigned WrapperKind = X86ISD::Wrapper;
10898 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10899 GA->getValueType(0),
10900 GA->getOffset(), OperandFlags);
10901 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10903 // Add x@dtpoff with the base.
10904 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10907 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10908 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10909 const EVT PtrVT, TLSModel::Model model,
10910 bool is64Bit, bool isPIC) {
10913 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10914 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10915 is64Bit ? 257 : 256));
10917 SDValue ThreadPointer =
10918 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10919 MachinePointerInfo(Ptr), false, false, false, 0);
10921 unsigned char OperandFlags = 0;
10922 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10924 unsigned WrapperKind = X86ISD::Wrapper;
10925 if (model == TLSModel::LocalExec) {
10926 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10927 } else if (model == TLSModel::InitialExec) {
10929 OperandFlags = X86II::MO_GOTTPOFF;
10930 WrapperKind = X86ISD::WrapperRIP;
10932 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10935 llvm_unreachable("Unexpected model");
10938 // emit "addl x@ntpoff,%eax" (local exec)
10939 // or "addl x@indntpoff,%eax" (initial exec)
10940 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10942 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10943 GA->getOffset(), OperandFlags);
10944 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10946 if (model == TLSModel::InitialExec) {
10947 if (isPIC && !is64Bit) {
10948 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10949 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10953 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10954 MachinePointerInfo::getGOT(), false, false, false, 0);
10957 // The address of the thread local variable is the add of the thread
10958 // pointer with the offset of the variable.
10959 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10963 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10965 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10966 const GlobalValue *GV = GA->getGlobal();
10968 if (Subtarget->isTargetELF()) {
10969 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10972 case TLSModel::GeneralDynamic:
10973 if (Subtarget->is64Bit())
10974 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10975 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10976 case TLSModel::LocalDynamic:
10977 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10978 Subtarget->is64Bit());
10979 case TLSModel::InitialExec:
10980 case TLSModel::LocalExec:
10981 return LowerToTLSExecModel(
10982 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10983 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10985 llvm_unreachable("Unknown TLS model.");
10988 if (Subtarget->isTargetDarwin()) {
10989 // Darwin only has one model of TLS. Lower to that.
10990 unsigned char OpFlag = 0;
10991 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10992 X86ISD::WrapperRIP : X86ISD::Wrapper;
10994 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10995 // global base reg.
10996 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10997 !Subtarget->is64Bit();
10999 OpFlag = X86II::MO_TLVP_PIC_BASE;
11001 OpFlag = X86II::MO_TLVP;
11003 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11004 GA->getValueType(0),
11005 GA->getOffset(), OpFlag);
11006 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11008 // With PIC32, the address is actually $g + Offset.
11010 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11011 DAG.getNode(X86ISD::GlobalBaseReg,
11012 SDLoc(), getPointerTy()),
11015 // Lowering the machine isd will make sure everything is in the right
11017 SDValue Chain = DAG.getEntryNode();
11018 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11019 SDValue Args[] = { Chain, Offset };
11020 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11022 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11023 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11024 MFI->setAdjustsStack(true);
11026 // And our return value (tls address) is in the standard call return value
11028 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11029 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11030 Chain.getValue(1));
11033 if (Subtarget->isTargetKnownWindowsMSVC() ||
11034 Subtarget->isTargetWindowsGNU()) {
11035 // Just use the implicit TLS architecture
11036 // Need to generate someting similar to:
11037 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11039 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11040 // mov rcx, qword [rdx+rcx*8]
11041 // mov eax, .tls$:tlsvar
11042 // [rax+rcx] contains the address
11043 // Windows 64bit: gs:0x58
11044 // Windows 32bit: fs:__tls_array
11047 SDValue Chain = DAG.getEntryNode();
11049 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11050 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11051 // use its literal value of 0x2C.
11052 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11053 ? Type::getInt8PtrTy(*DAG.getContext(),
11055 : Type::getInt32PtrTy(*DAG.getContext(),
11059 Subtarget->is64Bit()
11060 ? DAG.getIntPtrConstant(0x58)
11061 : (Subtarget->isTargetWindowsGNU()
11062 ? DAG.getIntPtrConstant(0x2C)
11063 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11065 SDValue ThreadPointer =
11066 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11067 MachinePointerInfo(Ptr), false, false, false, 0);
11069 // Load the _tls_index variable
11070 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11071 if (Subtarget->is64Bit())
11072 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11073 IDX, MachinePointerInfo(), MVT::i32,
11074 false, false, false, 0);
11076 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11077 false, false, false, 0);
11079 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11081 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11083 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11084 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11085 false, false, false, 0);
11087 // Get the offset of start of .tls section
11088 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11089 GA->getValueType(0),
11090 GA->getOffset(), X86II::MO_SECREL);
11091 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11093 // The address of the thread local variable is the add of the thread
11094 // pointer with the offset of the variable.
11095 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11098 llvm_unreachable("TLS not implemented for this target.");
11101 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11102 /// and take a 2 x i32 value to shift plus a shift amount.
11103 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11104 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11105 MVT VT = Op.getSimpleValueType();
11106 unsigned VTBits = VT.getSizeInBits();
11108 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11109 SDValue ShOpLo = Op.getOperand(0);
11110 SDValue ShOpHi = Op.getOperand(1);
11111 SDValue ShAmt = Op.getOperand(2);
11112 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11113 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11115 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11116 DAG.getConstant(VTBits - 1, MVT::i8));
11117 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11118 DAG.getConstant(VTBits - 1, MVT::i8))
11119 : DAG.getConstant(0, VT);
11121 SDValue Tmp2, Tmp3;
11122 if (Op.getOpcode() == ISD::SHL_PARTS) {
11123 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11124 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11126 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11127 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11130 // If the shift amount is larger or equal than the width of a part we can't
11131 // rely on the results of shld/shrd. Insert a test and select the appropriate
11132 // values for large shift amounts.
11133 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11134 DAG.getConstant(VTBits, MVT::i8));
11135 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11136 AndNode, DAG.getConstant(0, MVT::i8));
11139 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11140 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11141 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11143 if (Op.getOpcode() == ISD::SHL_PARTS) {
11144 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11145 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11147 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11148 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11151 SDValue Ops[2] = { Lo, Hi };
11152 return DAG.getMergeValues(Ops, dl);
11155 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11156 SelectionDAG &DAG) const {
11157 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11160 if (SrcVT.isVector()) {
11161 if (SrcVT.getVectorElementType() == MVT::i1) {
11162 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11163 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11164 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11165 Op.getOperand(0)));
11170 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11171 "Unknown SINT_TO_FP to lower!");
11173 // These are really Legal; return the operand so the caller accepts it as
11175 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11177 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11178 Subtarget->is64Bit()) {
11182 unsigned Size = SrcVT.getSizeInBits()/8;
11183 MachineFunction &MF = DAG.getMachineFunction();
11184 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11185 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11186 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11188 MachinePointerInfo::getFixedStack(SSFI),
11190 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11193 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11195 SelectionDAG &DAG) const {
11199 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11201 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11203 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11205 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11207 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11208 MachineMemOperand *MMO;
11210 int SSFI = FI->getIndex();
11212 DAG.getMachineFunction()
11213 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11214 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11216 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11217 StackSlot = StackSlot.getOperand(1);
11219 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11220 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11222 Tys, Ops, SrcVT, MMO);
11225 Chain = Result.getValue(1);
11226 SDValue InFlag = Result.getValue(2);
11228 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11229 // shouldn't be necessary except that RFP cannot be live across
11230 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11231 MachineFunction &MF = DAG.getMachineFunction();
11232 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11233 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11234 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11235 Tys = DAG.getVTList(MVT::Other);
11237 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11239 MachineMemOperand *MMO =
11240 DAG.getMachineFunction()
11241 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11242 MachineMemOperand::MOStore, SSFISize, SSFISize);
11244 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11245 Ops, Op.getValueType(), MMO);
11246 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11247 MachinePointerInfo::getFixedStack(SSFI),
11248 false, false, false, 0);
11254 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11255 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11256 SelectionDAG &DAG) const {
11257 // This algorithm is not obvious. Here it is what we're trying to output:
11260 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11261 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11263 haddpd %xmm0, %xmm0
11265 pshufd $0x4e, %xmm0, %xmm1
11271 LLVMContext *Context = DAG.getContext();
11273 // Build some magic constants.
11274 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11275 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11276 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11278 SmallVector<Constant*,2> CV1;
11280 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11281 APInt(64, 0x4330000000000000ULL))));
11283 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11284 APInt(64, 0x4530000000000000ULL))));
11285 Constant *C1 = ConstantVector::get(CV1);
11286 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11288 // Load the 64-bit value into an XMM register.
11289 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11291 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11292 MachinePointerInfo::getConstantPool(),
11293 false, false, false, 16);
11294 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11295 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11298 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11299 MachinePointerInfo::getConstantPool(),
11300 false, false, false, 16);
11301 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11302 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11305 if (Subtarget->hasSSE3()) {
11306 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11307 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11309 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11310 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11312 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11313 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11317 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11318 DAG.getIntPtrConstant(0));
11321 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11322 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11323 SelectionDAG &DAG) const {
11325 // FP constant to bias correct the final result.
11326 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11329 // Load the 32-bit value into an XMM register.
11330 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11333 // Zero out the upper parts of the register.
11334 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11336 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11337 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11338 DAG.getIntPtrConstant(0));
11340 // Or the load with the bias.
11341 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11342 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11343 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11344 MVT::v2f64, Load)),
11345 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11346 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11347 MVT::v2f64, Bias)));
11348 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11349 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11350 DAG.getIntPtrConstant(0));
11352 // Subtract the bias.
11353 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11355 // Handle final rounding.
11356 EVT DestVT = Op.getValueType();
11358 if (DestVT.bitsLT(MVT::f64))
11359 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11360 DAG.getIntPtrConstant(0));
11361 if (DestVT.bitsGT(MVT::f64))
11362 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11364 // Handle final rounding.
11368 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11369 const X86Subtarget &Subtarget) {
11370 // The algorithm is the following:
11371 // #ifdef __SSE4_1__
11372 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11373 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11374 // (uint4) 0x53000000, 0xaa);
11376 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11377 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11379 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11380 // return (float4) lo + fhi;
11383 SDValue V = Op->getOperand(0);
11384 EVT VecIntVT = V.getValueType();
11385 bool Is128 = VecIntVT == MVT::v4i32;
11386 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11387 // If we convert to something else than the supported type, e.g., to v4f64,
11389 if (VecFloatVT != Op->getValueType(0))
11392 unsigned NumElts = VecIntVT.getVectorNumElements();
11393 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11394 "Unsupported custom type");
11395 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11397 // In the #idef/#else code, we have in common:
11398 // - The vector of constants:
11404 // Create the splat vector for 0x4b000000.
11405 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
11406 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11407 CstLow, CstLow, CstLow, CstLow};
11408 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11409 makeArrayRef(&CstLowArray[0], NumElts));
11410 // Create the splat vector for 0x53000000.
11411 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
11412 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11413 CstHigh, CstHigh, CstHigh, CstHigh};
11414 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11415 makeArrayRef(&CstHighArray[0], NumElts));
11417 // Create the right shift.
11418 SDValue CstShift = DAG.getConstant(16, MVT::i32);
11419 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11420 CstShift, CstShift, CstShift, CstShift};
11421 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11422 makeArrayRef(&CstShiftArray[0], NumElts));
11423 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11426 if (Subtarget.hasSSE41()) {
11427 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11428 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11429 SDValue VecCstLowBitcast =
11430 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11431 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11432 // Low will be bitcasted right away, so do not bother bitcasting back to its
11434 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11435 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
11436 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11437 // (uint4) 0x53000000, 0xaa);
11438 SDValue VecCstHighBitcast =
11439 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11440 SDValue VecShiftBitcast =
11441 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11442 // High will be bitcasted right away, so do not bother bitcasting back to
11443 // its original type.
11444 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11445 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
11447 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
11448 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11449 CstMask, CstMask, CstMask);
11450 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11451 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11452 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11454 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11455 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11458 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11459 SDValue CstFAdd = DAG.getConstantFP(
11460 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
11461 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11462 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11463 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11464 makeArrayRef(&CstFAddArray[0], NumElts));
11466 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11467 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11469 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11470 // return (float4) lo + fhi;
11471 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11472 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11475 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11476 SelectionDAG &DAG) const {
11477 SDValue N0 = Op.getOperand(0);
11478 MVT SVT = N0.getSimpleValueType();
11481 switch (SVT.SimpleTy) {
11483 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11488 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11489 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11490 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11494 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11496 llvm_unreachable(nullptr);
11499 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11500 SelectionDAG &DAG) const {
11501 SDValue N0 = Op.getOperand(0);
11504 if (Op.getValueType().isVector())
11505 return lowerUINT_TO_FP_vec(Op, DAG);
11507 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11508 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11509 // the optimization here.
11510 if (DAG.SignBitIsZero(N0))
11511 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11513 MVT SrcVT = N0.getSimpleValueType();
11514 MVT DstVT = Op.getSimpleValueType();
11515 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11516 return LowerUINT_TO_FP_i64(Op, DAG);
11517 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11518 return LowerUINT_TO_FP_i32(Op, DAG);
11519 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11522 // Make a 64-bit buffer, and use it to build an FILD.
11523 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11524 if (SrcVT == MVT::i32) {
11525 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11526 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11527 getPointerTy(), StackSlot, WordOff);
11528 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11529 StackSlot, MachinePointerInfo(),
11531 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11532 OffsetSlot, MachinePointerInfo(),
11534 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11538 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11539 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11540 StackSlot, MachinePointerInfo(),
11542 // For i64 source, we need to add the appropriate power of 2 if the input
11543 // was negative. This is the same as the optimization in
11544 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11545 // we must be careful to do the computation in x87 extended precision, not
11546 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11547 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11548 MachineMemOperand *MMO =
11549 DAG.getMachineFunction()
11550 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11551 MachineMemOperand::MOLoad, 8, 8);
11553 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11554 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11555 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11558 APInt FF(32, 0x5F800000ULL);
11560 // Check whether the sign bit is set.
11561 SDValue SignSet = DAG.getSetCC(dl,
11562 getSetCCResultType(*DAG.getContext(), MVT::i64),
11563 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11566 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11567 SDValue FudgePtr = DAG.getConstantPool(
11568 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11571 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11572 SDValue Zero = DAG.getIntPtrConstant(0);
11573 SDValue Four = DAG.getIntPtrConstant(4);
11574 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11576 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11578 // Load the value out, extending it from f32 to f80.
11579 // FIXME: Avoid the extend by constructing the right constant pool?
11580 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11581 FudgePtr, MachinePointerInfo::getConstantPool(),
11582 MVT::f32, false, false, false, 4);
11583 // Extend everything to 80 bits to force it to be done on x87.
11584 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11585 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11588 std::pair<SDValue,SDValue>
11589 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11590 bool IsSigned, bool IsReplace) const {
11593 EVT DstTy = Op.getValueType();
11595 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11596 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11600 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11601 DstTy.getSimpleVT() >= MVT::i16 &&
11602 "Unknown FP_TO_INT to lower!");
11604 // These are really Legal.
11605 if (DstTy == MVT::i32 &&
11606 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11607 return std::make_pair(SDValue(), SDValue());
11608 if (Subtarget->is64Bit() &&
11609 DstTy == MVT::i64 &&
11610 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11611 return std::make_pair(SDValue(), SDValue());
11613 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11614 // stack slot, or into the FTOL runtime function.
11615 MachineFunction &MF = DAG.getMachineFunction();
11616 unsigned MemSize = DstTy.getSizeInBits()/8;
11617 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11618 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11621 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11622 Opc = X86ISD::WIN_FTOL;
11624 switch (DstTy.getSimpleVT().SimpleTy) {
11625 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11626 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11627 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11628 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11631 SDValue Chain = DAG.getEntryNode();
11632 SDValue Value = Op.getOperand(0);
11633 EVT TheVT = Op.getOperand(0).getValueType();
11634 // FIXME This causes a redundant load/store if the SSE-class value is already
11635 // in memory, such as if it is on the callstack.
11636 if (isScalarFPTypeInSSEReg(TheVT)) {
11637 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11638 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11639 MachinePointerInfo::getFixedStack(SSFI),
11641 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11643 Chain, StackSlot, DAG.getValueType(TheVT)
11646 MachineMemOperand *MMO =
11647 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11648 MachineMemOperand::MOLoad, MemSize, MemSize);
11649 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11650 Chain = Value.getValue(1);
11651 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11652 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11655 MachineMemOperand *MMO =
11656 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11657 MachineMemOperand::MOStore, MemSize, MemSize);
11659 if (Opc != X86ISD::WIN_FTOL) {
11660 // Build the FP_TO_INT*_IN_MEM
11661 SDValue Ops[] = { Chain, Value, StackSlot };
11662 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11664 return std::make_pair(FIST, StackSlot);
11666 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11667 DAG.getVTList(MVT::Other, MVT::Glue),
11669 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11670 MVT::i32, ftol.getValue(1));
11671 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11672 MVT::i32, eax.getValue(2));
11673 SDValue Ops[] = { eax, edx };
11674 SDValue pair = IsReplace
11675 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11676 : DAG.getMergeValues(Ops, DL);
11677 return std::make_pair(pair, SDValue());
11681 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11682 const X86Subtarget *Subtarget) {
11683 MVT VT = Op->getSimpleValueType(0);
11684 SDValue In = Op->getOperand(0);
11685 MVT InVT = In.getSimpleValueType();
11688 // Optimize vectors in AVX mode:
11691 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11692 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11693 // Concat upper and lower parts.
11696 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11697 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11698 // Concat upper and lower parts.
11701 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11702 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11703 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11706 if (Subtarget->hasInt256())
11707 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11709 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11710 SDValue Undef = DAG.getUNDEF(InVT);
11711 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11712 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11713 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11715 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11716 VT.getVectorNumElements()/2);
11718 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11719 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11721 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11724 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11725 SelectionDAG &DAG) {
11726 MVT VT = Op->getSimpleValueType(0);
11727 SDValue In = Op->getOperand(0);
11728 MVT InVT = In.getSimpleValueType();
11730 unsigned int NumElts = VT.getVectorNumElements();
11731 if (NumElts != 8 && NumElts != 16)
11734 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11735 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11737 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11738 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11739 // Now we have only mask extension
11740 assert(InVT.getVectorElementType() == MVT::i1);
11741 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11742 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11743 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11744 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11745 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11746 MachinePointerInfo::getConstantPool(),
11747 false, false, false, Alignment);
11749 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11750 if (VT.is512BitVector())
11752 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11755 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11756 SelectionDAG &DAG) {
11757 if (Subtarget->hasFp256()) {
11758 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11766 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11767 SelectionDAG &DAG) {
11769 MVT VT = Op.getSimpleValueType();
11770 SDValue In = Op.getOperand(0);
11771 MVT SVT = In.getSimpleValueType();
11773 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11774 return LowerZERO_EXTEND_AVX512(Op, DAG);
11776 if (Subtarget->hasFp256()) {
11777 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11782 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11783 VT.getVectorNumElements() != SVT.getVectorNumElements());
11787 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11789 MVT VT = Op.getSimpleValueType();
11790 SDValue In = Op.getOperand(0);
11791 MVT InVT = In.getSimpleValueType();
11793 if (VT == MVT::i1) {
11794 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11795 "Invalid scalar TRUNCATE operation");
11796 if (InVT.getSizeInBits() >= 32)
11798 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11799 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11801 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11802 "Invalid TRUNCATE operation");
11804 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11805 if (VT.getVectorElementType().getSizeInBits() >=8)
11806 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11808 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11809 unsigned NumElts = InVT.getVectorNumElements();
11810 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11811 if (InVT.getSizeInBits() < 512) {
11812 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11813 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11817 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11818 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11819 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11820 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11821 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11822 MachinePointerInfo::getConstantPool(),
11823 false, false, false, Alignment);
11824 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11825 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11826 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11829 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11830 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11831 if (Subtarget->hasInt256()) {
11832 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11833 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11834 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11836 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11837 DAG.getIntPtrConstant(0));
11840 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11841 DAG.getIntPtrConstant(0));
11842 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11843 DAG.getIntPtrConstant(2));
11844 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11845 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11846 static const int ShufMask[] = {0, 2, 4, 6};
11847 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11850 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11851 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11852 if (Subtarget->hasInt256()) {
11853 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11855 SmallVector<SDValue,32> pshufbMask;
11856 for (unsigned i = 0; i < 2; ++i) {
11857 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11858 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11859 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11860 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11861 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11862 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11863 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11864 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11865 for (unsigned j = 0; j < 8; ++j)
11866 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11868 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11869 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11870 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11872 static const int ShufMask[] = {0, 2, -1, -1};
11873 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11875 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11876 DAG.getIntPtrConstant(0));
11877 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11880 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11881 DAG.getIntPtrConstant(0));
11883 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11884 DAG.getIntPtrConstant(4));
11886 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11887 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11889 // The PSHUFB mask:
11890 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11891 -1, -1, -1, -1, -1, -1, -1, -1};
11893 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11894 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11895 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11897 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11898 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11900 // The MOVLHPS Mask:
11901 static const int ShufMask2[] = {0, 1, 4, 5};
11902 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11903 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11906 // Handle truncation of V256 to V128 using shuffles.
11907 if (!VT.is128BitVector() || !InVT.is256BitVector())
11910 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11912 unsigned NumElems = VT.getVectorNumElements();
11913 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11915 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11916 // Prepare truncation shuffle mask
11917 for (unsigned i = 0; i != NumElems; ++i)
11918 MaskVec[i] = i * 2;
11919 SDValue V = DAG.getVectorShuffle(NVT, DL,
11920 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11921 DAG.getUNDEF(NVT), &MaskVec[0]);
11922 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11923 DAG.getIntPtrConstant(0));
11926 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11927 SelectionDAG &DAG) const {
11928 assert(!Op.getSimpleValueType().isVector());
11930 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11931 /*IsSigned=*/ true, /*IsReplace=*/ false);
11932 SDValue FIST = Vals.first, StackSlot = Vals.second;
11933 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11934 if (!FIST.getNode()) return Op;
11936 if (StackSlot.getNode())
11937 // Load the result.
11938 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11939 FIST, StackSlot, MachinePointerInfo(),
11940 false, false, false, 0);
11942 // The node is the result.
11946 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11947 SelectionDAG &DAG) const {
11948 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11949 /*IsSigned=*/ false, /*IsReplace=*/ false);
11950 SDValue FIST = Vals.first, StackSlot = Vals.second;
11951 assert(FIST.getNode() && "Unexpected failure");
11953 if (StackSlot.getNode())
11954 // Load the result.
11955 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11956 FIST, StackSlot, MachinePointerInfo(),
11957 false, false, false, 0);
11959 // The node is the result.
11963 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11965 MVT VT = Op.getSimpleValueType();
11966 SDValue In = Op.getOperand(0);
11967 MVT SVT = In.getSimpleValueType();
11969 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11971 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11972 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11973 In, DAG.getUNDEF(SVT)));
11976 /// The only differences between FABS and FNEG are the mask and the logic op.
11977 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
11978 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
11979 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
11980 "Wrong opcode for lowering FABS or FNEG.");
11982 bool IsFABS = (Op.getOpcode() == ISD::FABS);
11984 // If this is a FABS and it has an FNEG user, bail out to fold the combination
11985 // into an FNABS. We'll lower the FABS after that if it is still in use.
11987 for (SDNode *User : Op->uses())
11988 if (User->getOpcode() == ISD::FNEG)
11991 SDValue Op0 = Op.getOperand(0);
11992 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
11995 MVT VT = Op.getSimpleValueType();
11996 // Assume scalar op for initialization; update for vector if needed.
11997 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
11998 // generate a 16-byte vector constant and logic op even for the scalar case.
11999 // Using a 16-byte mask allows folding the load of the mask with
12000 // the logic op, so it can save (~4 bytes) on code size.
12002 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12003 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12004 // decide if we should generate a 16-byte constant mask when we only need 4 or
12005 // 8 bytes for the scalar case.
12006 if (VT.isVector()) {
12007 EltVT = VT.getVectorElementType();
12008 NumElts = VT.getVectorNumElements();
12011 unsigned EltBits = EltVT.getSizeInBits();
12012 LLVMContext *Context = DAG.getContext();
12013 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12015 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12016 Constant *C = ConstantInt::get(*Context, MaskElt);
12017 C = ConstantVector::getSplat(NumElts, C);
12018 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12019 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12020 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12021 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12022 MachinePointerInfo::getConstantPool(),
12023 false, false, false, Alignment);
12025 if (VT.isVector()) {
12026 // For a vector, cast operands to a vector type, perform the logic op,
12027 // and cast the result back to the original value type.
12028 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12029 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12030 SDValue Operand = IsFNABS ?
12031 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12032 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12033 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12034 return DAG.getNode(ISD::BITCAST, dl, VT,
12035 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12038 // If not vector, then scalar.
12039 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12040 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12041 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12044 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12045 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12046 LLVMContext *Context = DAG.getContext();
12047 SDValue Op0 = Op.getOperand(0);
12048 SDValue Op1 = Op.getOperand(1);
12050 MVT VT = Op.getSimpleValueType();
12051 MVT SrcVT = Op1.getSimpleValueType();
12053 // If second operand is smaller, extend it first.
12054 if (SrcVT.bitsLT(VT)) {
12055 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12058 // And if it is bigger, shrink it first.
12059 if (SrcVT.bitsGT(VT)) {
12060 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12064 // At this point the operands and the result should have the same
12065 // type, and that won't be f80 since that is not custom lowered.
12067 const fltSemantics &Sem =
12068 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12069 const unsigned SizeInBits = VT.getSizeInBits();
12071 SmallVector<Constant *, 4> CV(
12072 VT == MVT::f64 ? 2 : 4,
12073 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12075 // First, clear all bits but the sign bit from the second operand (sign).
12076 CV[0] = ConstantFP::get(*Context,
12077 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12078 Constant *C = ConstantVector::get(CV);
12079 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12080 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12081 MachinePointerInfo::getConstantPool(),
12082 false, false, false, 16);
12083 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12085 // Next, clear the sign bit from the first operand (magnitude).
12086 // If it's a constant, we can clear it here.
12087 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12088 APFloat APF = Op0CN->getValueAPF();
12089 // If the magnitude is a positive zero, the sign bit alone is enough.
12090 if (APF.isPosZero())
12093 CV[0] = ConstantFP::get(*Context, APF);
12095 CV[0] = ConstantFP::get(
12097 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12099 C = ConstantVector::get(CV);
12100 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12101 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12102 MachinePointerInfo::getConstantPool(),
12103 false, false, false, 16);
12104 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12105 if (!isa<ConstantFPSDNode>(Op0))
12106 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12108 // OR the magnitude value with the sign bit.
12109 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12112 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12113 SDValue N0 = Op.getOperand(0);
12115 MVT VT = Op.getSimpleValueType();
12117 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12118 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12119 DAG.getConstant(1, VT));
12120 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12123 // Check whether an OR'd tree is PTEST-able.
12124 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12125 SelectionDAG &DAG) {
12126 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12128 if (!Subtarget->hasSSE41())
12131 if (!Op->hasOneUse())
12134 SDNode *N = Op.getNode();
12137 SmallVector<SDValue, 8> Opnds;
12138 DenseMap<SDValue, unsigned> VecInMap;
12139 SmallVector<SDValue, 8> VecIns;
12140 EVT VT = MVT::Other;
12142 // Recognize a special case where a vector is casted into wide integer to
12144 Opnds.push_back(N->getOperand(0));
12145 Opnds.push_back(N->getOperand(1));
12147 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12148 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12149 // BFS traverse all OR'd operands.
12150 if (I->getOpcode() == ISD::OR) {
12151 Opnds.push_back(I->getOperand(0));
12152 Opnds.push_back(I->getOperand(1));
12153 // Re-evaluate the number of nodes to be traversed.
12154 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12158 // Quit if a non-EXTRACT_VECTOR_ELT
12159 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12162 // Quit if without a constant index.
12163 SDValue Idx = I->getOperand(1);
12164 if (!isa<ConstantSDNode>(Idx))
12167 SDValue ExtractedFromVec = I->getOperand(0);
12168 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12169 if (M == VecInMap.end()) {
12170 VT = ExtractedFromVec.getValueType();
12171 // Quit if not 128/256-bit vector.
12172 if (!VT.is128BitVector() && !VT.is256BitVector())
12174 // Quit if not the same type.
12175 if (VecInMap.begin() != VecInMap.end() &&
12176 VT != VecInMap.begin()->first.getValueType())
12178 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12179 VecIns.push_back(ExtractedFromVec);
12181 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12184 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12185 "Not extracted from 128-/256-bit vector.");
12187 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12189 for (DenseMap<SDValue, unsigned>::const_iterator
12190 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12191 // Quit if not all elements are used.
12192 if (I->second != FullMask)
12196 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12198 // Cast all vectors into TestVT for PTEST.
12199 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12200 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12202 // If more than one full vectors are evaluated, OR them first before PTEST.
12203 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12204 // Each iteration will OR 2 nodes and append the result until there is only
12205 // 1 node left, i.e. the final OR'd value of all vectors.
12206 SDValue LHS = VecIns[Slot];
12207 SDValue RHS = VecIns[Slot + 1];
12208 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12211 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12212 VecIns.back(), VecIns.back());
12215 /// \brief return true if \c Op has a use that doesn't just read flags.
12216 static bool hasNonFlagsUse(SDValue Op) {
12217 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12219 SDNode *User = *UI;
12220 unsigned UOpNo = UI.getOperandNo();
12221 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12222 // Look pass truncate.
12223 UOpNo = User->use_begin().getOperandNo();
12224 User = *User->use_begin();
12227 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12228 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12234 /// Emit nodes that will be selected as "test Op0,Op0", or something
12236 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12237 SelectionDAG &DAG) const {
12238 if (Op.getValueType() == MVT::i1) {
12239 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12240 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12241 DAG.getConstant(0, MVT::i8));
12243 // CF and OF aren't always set the way we want. Determine which
12244 // of these we need.
12245 bool NeedCF = false;
12246 bool NeedOF = false;
12249 case X86::COND_A: case X86::COND_AE:
12250 case X86::COND_B: case X86::COND_BE:
12253 case X86::COND_G: case X86::COND_GE:
12254 case X86::COND_L: case X86::COND_LE:
12255 case X86::COND_O: case X86::COND_NO: {
12256 // Check if we really need to set the
12257 // Overflow flag. If NoSignedWrap is present
12258 // that is not actually needed.
12259 switch (Op->getOpcode()) {
12264 const BinaryWithFlagsSDNode *BinNode =
12265 cast<BinaryWithFlagsSDNode>(Op.getNode());
12266 if (BinNode->hasNoSignedWrap())
12276 // See if we can use the EFLAGS value from the operand instead of
12277 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12278 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12279 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12280 // Emit a CMP with 0, which is the TEST pattern.
12281 //if (Op.getValueType() == MVT::i1)
12282 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12283 // DAG.getConstant(0, MVT::i1));
12284 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12285 DAG.getConstant(0, Op.getValueType()));
12287 unsigned Opcode = 0;
12288 unsigned NumOperands = 0;
12290 // Truncate operations may prevent the merge of the SETCC instruction
12291 // and the arithmetic instruction before it. Attempt to truncate the operands
12292 // of the arithmetic instruction and use a reduced bit-width instruction.
12293 bool NeedTruncation = false;
12294 SDValue ArithOp = Op;
12295 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12296 SDValue Arith = Op->getOperand(0);
12297 // Both the trunc and the arithmetic op need to have one user each.
12298 if (Arith->hasOneUse())
12299 switch (Arith.getOpcode()) {
12306 NeedTruncation = true;
12312 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12313 // which may be the result of a CAST. We use the variable 'Op', which is the
12314 // non-casted variable when we check for possible users.
12315 switch (ArithOp.getOpcode()) {
12317 // Due to an isel shortcoming, be conservative if this add is likely to be
12318 // selected as part of a load-modify-store instruction. When the root node
12319 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12320 // uses of other nodes in the match, such as the ADD in this case. This
12321 // leads to the ADD being left around and reselected, with the result being
12322 // two adds in the output. Alas, even if none our users are stores, that
12323 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12324 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12325 // climbing the DAG back to the root, and it doesn't seem to be worth the
12327 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12328 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12329 if (UI->getOpcode() != ISD::CopyToReg &&
12330 UI->getOpcode() != ISD::SETCC &&
12331 UI->getOpcode() != ISD::STORE)
12334 if (ConstantSDNode *C =
12335 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12336 // An add of one will be selected as an INC.
12337 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12338 Opcode = X86ISD::INC;
12343 // An add of negative one (subtract of one) will be selected as a DEC.
12344 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12345 Opcode = X86ISD::DEC;
12351 // Otherwise use a regular EFLAGS-setting add.
12352 Opcode = X86ISD::ADD;
12357 // If we have a constant logical shift that's only used in a comparison
12358 // against zero turn it into an equivalent AND. This allows turning it into
12359 // a TEST instruction later.
12360 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12361 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12362 EVT VT = Op.getValueType();
12363 unsigned BitWidth = VT.getSizeInBits();
12364 unsigned ShAmt = Op->getConstantOperandVal(1);
12365 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12367 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12368 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12369 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12370 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12372 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12373 DAG.getConstant(Mask, VT));
12374 DAG.ReplaceAllUsesWith(Op, New);
12380 // If the primary and result isn't used, don't bother using X86ISD::AND,
12381 // because a TEST instruction will be better.
12382 if (!hasNonFlagsUse(Op))
12388 // Due to the ISEL shortcoming noted above, be conservative if this op is
12389 // likely to be selected as part of a load-modify-store instruction.
12390 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12391 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12392 if (UI->getOpcode() == ISD::STORE)
12395 // Otherwise use a regular EFLAGS-setting instruction.
12396 switch (ArithOp.getOpcode()) {
12397 default: llvm_unreachable("unexpected operator!");
12398 case ISD::SUB: Opcode = X86ISD::SUB; break;
12399 case ISD::XOR: Opcode = X86ISD::XOR; break;
12400 case ISD::AND: Opcode = X86ISD::AND; break;
12402 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12403 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12404 if (EFLAGS.getNode())
12407 Opcode = X86ISD::OR;
12421 return SDValue(Op.getNode(), 1);
12427 // If we found that truncation is beneficial, perform the truncation and
12429 if (NeedTruncation) {
12430 EVT VT = Op.getValueType();
12431 SDValue WideVal = Op->getOperand(0);
12432 EVT WideVT = WideVal.getValueType();
12433 unsigned ConvertedOp = 0;
12434 // Use a target machine opcode to prevent further DAGCombine
12435 // optimizations that may separate the arithmetic operations
12436 // from the setcc node.
12437 switch (WideVal.getOpcode()) {
12439 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12440 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12441 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12442 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12443 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12448 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12449 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12450 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12451 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12457 // Emit a CMP with 0, which is the TEST pattern.
12458 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12459 DAG.getConstant(0, Op.getValueType()));
12461 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12462 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12464 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12465 DAG.ReplaceAllUsesWith(Op, New);
12466 return SDValue(New.getNode(), 1);
12469 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12471 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12472 SDLoc dl, SelectionDAG &DAG) const {
12473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12474 if (C->getAPIntValue() == 0)
12475 return EmitTest(Op0, X86CC, dl, DAG);
12477 if (Op0.getValueType() == MVT::i1)
12478 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12481 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12482 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12483 // Do the comparison at i32 if it's smaller, besides the Atom case.
12484 // This avoids subregister aliasing issues. Keep the smaller reference
12485 // if we're optimizing for size, however, as that'll allow better folding
12486 // of memory operations.
12487 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12488 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12489 Attribute::MinSize) &&
12490 !Subtarget->isAtom()) {
12491 unsigned ExtendOp =
12492 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12493 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12494 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12496 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12497 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12498 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12500 return SDValue(Sub.getNode(), 1);
12502 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12505 /// Convert a comparison if required by the subtarget.
12506 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12507 SelectionDAG &DAG) const {
12508 // If the subtarget does not support the FUCOMI instruction, floating-point
12509 // comparisons have to be converted.
12510 if (Subtarget->hasCMov() ||
12511 Cmp.getOpcode() != X86ISD::CMP ||
12512 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12513 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12516 // The instruction selector will select an FUCOM instruction instead of
12517 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12518 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12519 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12521 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12522 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12523 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12524 DAG.getConstant(8, MVT::i8));
12525 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12526 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12529 /// The minimum architected relative accuracy is 2^-12. We need one
12530 /// Newton-Raphson step to have a good float result (24 bits of precision).
12531 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12532 DAGCombinerInfo &DCI,
12533 unsigned &RefinementSteps,
12534 bool &UseOneConstNR) const {
12535 // FIXME: We should use instruction latency models to calculate the cost of
12536 // each potential sequence, but this is very hard to do reliably because
12537 // at least Intel's Core* chips have variable timing based on the number of
12538 // significant digits in the divisor and/or sqrt operand.
12539 if (!Subtarget->useSqrtEst())
12542 EVT VT = Op.getValueType();
12544 // SSE1 has rsqrtss and rsqrtps.
12545 // TODO: Add support for AVX512 (v16f32).
12546 // It is likely not profitable to do this for f64 because a double-precision
12547 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12548 // instructions: convert to single, rsqrtss, convert back to double, refine
12549 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12550 // along with FMA, this could be a throughput win.
12551 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12552 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12553 RefinementSteps = 1;
12554 UseOneConstNR = false;
12555 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12560 /// The minimum architected relative accuracy is 2^-12. We need one
12561 /// Newton-Raphson step to have a good float result (24 bits of precision).
12562 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12563 DAGCombinerInfo &DCI,
12564 unsigned &RefinementSteps) const {
12565 // FIXME: We should use instruction latency models to calculate the cost of
12566 // each potential sequence, but this is very hard to do reliably because
12567 // at least Intel's Core* chips have variable timing based on the number of
12568 // significant digits in the divisor.
12569 if (!Subtarget->useReciprocalEst())
12572 EVT VT = Op.getValueType();
12574 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12575 // TODO: Add support for AVX512 (v16f32).
12576 // It is likely not profitable to do this for f64 because a double-precision
12577 // reciprocal estimate with refinement on x86 prior to FMA requires
12578 // 15 instructions: convert to single, rcpss, convert back to double, refine
12579 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12580 // along with FMA, this could be a throughput win.
12581 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12582 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12583 RefinementSteps = ReciprocalEstimateRefinementSteps;
12584 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12589 static bool isAllOnes(SDValue V) {
12590 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12591 return C && C->isAllOnesValue();
12594 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12595 /// if it's possible.
12596 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12597 SDLoc dl, SelectionDAG &DAG) const {
12598 SDValue Op0 = And.getOperand(0);
12599 SDValue Op1 = And.getOperand(1);
12600 if (Op0.getOpcode() == ISD::TRUNCATE)
12601 Op0 = Op0.getOperand(0);
12602 if (Op1.getOpcode() == ISD::TRUNCATE)
12603 Op1 = Op1.getOperand(0);
12606 if (Op1.getOpcode() == ISD::SHL)
12607 std::swap(Op0, Op1);
12608 if (Op0.getOpcode() == ISD::SHL) {
12609 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12610 if (And00C->getZExtValue() == 1) {
12611 // If we looked past a truncate, check that it's only truncating away
12613 unsigned BitWidth = Op0.getValueSizeInBits();
12614 unsigned AndBitWidth = And.getValueSizeInBits();
12615 if (BitWidth > AndBitWidth) {
12617 DAG.computeKnownBits(Op0, Zeros, Ones);
12618 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12622 RHS = Op0.getOperand(1);
12624 } else if (Op1.getOpcode() == ISD::Constant) {
12625 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12626 uint64_t AndRHSVal = AndRHS->getZExtValue();
12627 SDValue AndLHS = Op0;
12629 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12630 LHS = AndLHS.getOperand(0);
12631 RHS = AndLHS.getOperand(1);
12634 // Use BT if the immediate can't be encoded in a TEST instruction.
12635 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12637 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12641 if (LHS.getNode()) {
12642 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12643 // instruction. Since the shift amount is in-range-or-undefined, we know
12644 // that doing a bittest on the i32 value is ok. We extend to i32 because
12645 // the encoding for the i16 version is larger than the i32 version.
12646 // Also promote i16 to i32 for performance / code size reason.
12647 if (LHS.getValueType() == MVT::i8 ||
12648 LHS.getValueType() == MVT::i16)
12649 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12651 // If the operand types disagree, extend the shift amount to match. Since
12652 // BT ignores high bits (like shifts) we can use anyextend.
12653 if (LHS.getValueType() != RHS.getValueType())
12654 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12656 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12657 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12658 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12659 DAG.getConstant(Cond, MVT::i8), BT);
12665 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12667 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12672 // SSE Condition code mapping:
12681 switch (SetCCOpcode) {
12682 default: llvm_unreachable("Unexpected SETCC condition");
12684 case ISD::SETEQ: SSECC = 0; break;
12686 case ISD::SETGT: Swap = true; // Fallthrough
12688 case ISD::SETOLT: SSECC = 1; break;
12690 case ISD::SETGE: Swap = true; // Fallthrough
12692 case ISD::SETOLE: SSECC = 2; break;
12693 case ISD::SETUO: SSECC = 3; break;
12695 case ISD::SETNE: SSECC = 4; break;
12696 case ISD::SETULE: Swap = true; // Fallthrough
12697 case ISD::SETUGE: SSECC = 5; break;
12698 case ISD::SETULT: Swap = true; // Fallthrough
12699 case ISD::SETUGT: SSECC = 6; break;
12700 case ISD::SETO: SSECC = 7; break;
12702 case ISD::SETONE: SSECC = 8; break;
12705 std::swap(Op0, Op1);
12710 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12711 // ones, and then concatenate the result back.
12712 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12713 MVT VT = Op.getSimpleValueType();
12715 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12716 "Unsupported value type for operation");
12718 unsigned NumElems = VT.getVectorNumElements();
12720 SDValue CC = Op.getOperand(2);
12722 // Extract the LHS vectors
12723 SDValue LHS = Op.getOperand(0);
12724 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12725 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12727 // Extract the RHS vectors
12728 SDValue RHS = Op.getOperand(1);
12729 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12730 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12732 // Issue the operation on the smaller types and concatenate the result back
12733 MVT EltVT = VT.getVectorElementType();
12734 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12735 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12736 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12737 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12740 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12741 const X86Subtarget *Subtarget) {
12742 SDValue Op0 = Op.getOperand(0);
12743 SDValue Op1 = Op.getOperand(1);
12744 SDValue CC = Op.getOperand(2);
12745 MVT VT = Op.getSimpleValueType();
12748 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
12749 Op.getValueType().getScalarType() == MVT::i1 &&
12750 "Cannot set masked compare for this operation");
12752 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12754 bool Unsigned = false;
12757 switch (SetCCOpcode) {
12758 default: llvm_unreachable("Unexpected SETCC condition");
12759 case ISD::SETNE: SSECC = 4; break;
12760 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12761 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12762 case ISD::SETLT: Swap = true; //fall-through
12763 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12764 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12765 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12766 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12767 case ISD::SETULE: Unsigned = true; //fall-through
12768 case ISD::SETLE: SSECC = 2; break;
12772 std::swap(Op0, Op1);
12774 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12775 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12776 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12777 DAG.getConstant(SSECC, MVT::i8));
12780 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12781 /// operand \p Op1. If non-trivial (for example because it's not constant)
12782 /// return an empty value.
12783 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12785 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12789 MVT VT = Op1.getSimpleValueType();
12790 MVT EVT = VT.getVectorElementType();
12791 unsigned n = VT.getVectorNumElements();
12792 SmallVector<SDValue, 8> ULTOp1;
12794 for (unsigned i = 0; i < n; ++i) {
12795 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12796 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12799 // Avoid underflow.
12800 APInt Val = Elt->getAPIntValue();
12804 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12807 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12810 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12811 SelectionDAG &DAG) {
12812 SDValue Op0 = Op.getOperand(0);
12813 SDValue Op1 = Op.getOperand(1);
12814 SDValue CC = Op.getOperand(2);
12815 MVT VT = Op.getSimpleValueType();
12816 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12817 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12822 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12823 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12826 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12827 unsigned Opc = X86ISD::CMPP;
12828 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12829 assert(VT.getVectorNumElements() <= 16);
12830 Opc = X86ISD::CMPM;
12832 // In the two special cases we can't handle, emit two comparisons.
12835 unsigned CombineOpc;
12836 if (SetCCOpcode == ISD::SETUEQ) {
12837 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12839 assert(SetCCOpcode == ISD::SETONE);
12840 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12843 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12844 DAG.getConstant(CC0, MVT::i8));
12845 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12846 DAG.getConstant(CC1, MVT::i8));
12847 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12849 // Handle all other FP comparisons here.
12850 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12851 DAG.getConstant(SSECC, MVT::i8));
12854 // Break 256-bit integer vector compare into smaller ones.
12855 if (VT.is256BitVector() && !Subtarget->hasInt256())
12856 return Lower256IntVSETCC(Op, DAG);
12858 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12859 EVT OpVT = Op1.getValueType();
12860 if (Subtarget->hasAVX512()) {
12861 if (Op1.getValueType().is512BitVector() ||
12862 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
12863 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12864 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12866 // In AVX-512 architecture setcc returns mask with i1 elements,
12867 // But there is no compare instruction for i8 and i16 elements in KNL.
12868 // We are not talking about 512-bit operands in this case, these
12869 // types are illegal.
12871 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12872 OpVT.getVectorElementType().getSizeInBits() >= 8))
12873 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12874 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12877 // We are handling one of the integer comparisons here. Since SSE only has
12878 // GT and EQ comparisons for integer, swapping operands and multiple
12879 // operations may be required for some comparisons.
12881 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12882 bool Subus = false;
12884 switch (SetCCOpcode) {
12885 default: llvm_unreachable("Unexpected SETCC condition");
12886 case ISD::SETNE: Invert = true;
12887 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12888 case ISD::SETLT: Swap = true;
12889 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12890 case ISD::SETGE: Swap = true;
12891 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12892 Invert = true; break;
12893 case ISD::SETULT: Swap = true;
12894 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12895 FlipSigns = true; break;
12896 case ISD::SETUGE: Swap = true;
12897 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12898 FlipSigns = true; Invert = true; break;
12901 // Special case: Use min/max operations for SETULE/SETUGE
12902 MVT VET = VT.getVectorElementType();
12904 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12905 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12908 switch (SetCCOpcode) {
12910 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12911 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12914 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12917 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12918 if (!MinMax && hasSubus) {
12919 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12921 // t = psubus Op0, Op1
12922 // pcmpeq t, <0..0>
12923 switch (SetCCOpcode) {
12925 case ISD::SETULT: {
12926 // If the comparison is against a constant we can turn this into a
12927 // setule. With psubus, setule does not require a swap. This is
12928 // beneficial because the constant in the register is no longer
12929 // destructed as the destination so it can be hoisted out of a loop.
12930 // Only do this pre-AVX since vpcmp* is no longer destructive.
12931 if (Subtarget->hasAVX())
12933 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12934 if (ULEOp1.getNode()) {
12936 Subus = true; Invert = false; Swap = false;
12940 // Psubus is better than flip-sign because it requires no inversion.
12941 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12942 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12946 Opc = X86ISD::SUBUS;
12952 std::swap(Op0, Op1);
12954 // Check that the operation in question is available (most are plain SSE2,
12955 // but PCMPGTQ and PCMPEQQ have different requirements).
12956 if (VT == MVT::v2i64) {
12957 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12958 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12960 // First cast everything to the right type.
12961 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12962 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12964 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12965 // bits of the inputs before performing those operations. The lower
12966 // compare is always unsigned.
12969 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12971 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12972 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12973 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12974 Sign, Zero, Sign, Zero);
12976 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12977 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12979 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12980 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12981 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12983 // Create masks for only the low parts/high parts of the 64 bit integers.
12984 static const int MaskHi[] = { 1, 1, 3, 3 };
12985 static const int MaskLo[] = { 0, 0, 2, 2 };
12986 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12987 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12988 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12990 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12991 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12994 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12996 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12999 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13000 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13001 // pcmpeqd + pshufd + pand.
13002 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13004 // First cast everything to the right type.
13005 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13006 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13009 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13011 // Make sure the lower and upper halves are both all-ones.
13012 static const int Mask[] = { 1, 0, 3, 2 };
13013 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13014 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13017 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13019 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13023 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13024 // bits of the inputs before performing those operations.
13026 EVT EltVT = VT.getVectorElementType();
13027 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13028 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13029 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13032 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13034 // If the logical-not of the result is required, perform that now.
13036 Result = DAG.getNOT(dl, Result, VT);
13039 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13042 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13043 getZeroVector(VT, Subtarget, DAG, dl));
13048 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13050 MVT VT = Op.getSimpleValueType();
13052 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13054 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13055 && "SetCC type must be 8-bit or 1-bit integer");
13056 SDValue Op0 = Op.getOperand(0);
13057 SDValue Op1 = Op.getOperand(1);
13059 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13061 // Optimize to BT if possible.
13062 // Lower (X & (1 << N)) == 0 to BT(X, N).
13063 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13064 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13065 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13066 Op1.getOpcode() == ISD::Constant &&
13067 cast<ConstantSDNode>(Op1)->isNullValue() &&
13068 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13069 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13070 if (NewSetCC.getNode()) {
13072 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13077 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13079 if (Op1.getOpcode() == ISD::Constant &&
13080 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13081 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13082 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13084 // If the input is a setcc, then reuse the input setcc or use a new one with
13085 // the inverted condition.
13086 if (Op0.getOpcode() == X86ISD::SETCC) {
13087 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13088 bool Invert = (CC == ISD::SETNE) ^
13089 cast<ConstantSDNode>(Op1)->isNullValue();
13093 CCode = X86::GetOppositeBranchCondition(CCode);
13094 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13095 DAG.getConstant(CCode, MVT::i8),
13096 Op0.getOperand(1));
13098 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13102 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13103 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13104 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13106 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13107 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13110 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13111 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13112 if (X86CC == X86::COND_INVALID)
13115 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13116 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13117 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13118 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13120 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13124 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13125 static bool isX86LogicalCmp(SDValue Op) {
13126 unsigned Opc = Op.getNode()->getOpcode();
13127 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13128 Opc == X86ISD::SAHF)
13130 if (Op.getResNo() == 1 &&
13131 (Opc == X86ISD::ADD ||
13132 Opc == X86ISD::SUB ||
13133 Opc == X86ISD::ADC ||
13134 Opc == X86ISD::SBB ||
13135 Opc == X86ISD::SMUL ||
13136 Opc == X86ISD::UMUL ||
13137 Opc == X86ISD::INC ||
13138 Opc == X86ISD::DEC ||
13139 Opc == X86ISD::OR ||
13140 Opc == X86ISD::XOR ||
13141 Opc == X86ISD::AND))
13144 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13150 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13151 if (V.getOpcode() != ISD::TRUNCATE)
13154 SDValue VOp0 = V.getOperand(0);
13155 unsigned InBits = VOp0.getValueSizeInBits();
13156 unsigned Bits = V.getValueSizeInBits();
13157 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13160 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13161 bool addTest = true;
13162 SDValue Cond = Op.getOperand(0);
13163 SDValue Op1 = Op.getOperand(1);
13164 SDValue Op2 = Op.getOperand(2);
13166 EVT VT = Op1.getValueType();
13169 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13170 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13171 // sequence later on.
13172 if (Cond.getOpcode() == ISD::SETCC &&
13173 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13174 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13175 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13176 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13177 int SSECC = translateX86FSETCC(
13178 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13181 if (Subtarget->hasAVX512()) {
13182 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13183 DAG.getConstant(SSECC, MVT::i8));
13184 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13186 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13187 DAG.getConstant(SSECC, MVT::i8));
13188 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13189 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13190 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13194 if (Cond.getOpcode() == ISD::SETCC) {
13195 SDValue NewCond = LowerSETCC(Cond, DAG);
13196 if (NewCond.getNode())
13200 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13201 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13202 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13203 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13204 if (Cond.getOpcode() == X86ISD::SETCC &&
13205 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13206 isZero(Cond.getOperand(1).getOperand(1))) {
13207 SDValue Cmp = Cond.getOperand(1);
13209 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13211 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13212 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13213 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13215 SDValue CmpOp0 = Cmp.getOperand(0);
13216 // Apply further optimizations for special cases
13217 // (select (x != 0), -1, 0) -> neg & sbb
13218 // (select (x == 0), 0, -1) -> neg & sbb
13219 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13220 if (YC->isNullValue() &&
13221 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13222 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13223 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13224 DAG.getConstant(0, CmpOp0.getValueType()),
13226 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13227 DAG.getConstant(X86::COND_B, MVT::i8),
13228 SDValue(Neg.getNode(), 1));
13232 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13233 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13234 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13236 SDValue Res = // Res = 0 or -1.
13237 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13238 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13240 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13241 Res = DAG.getNOT(DL, Res, Res.getValueType());
13243 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13244 if (!N2C || !N2C->isNullValue())
13245 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13250 // Look past (and (setcc_carry (cmp ...)), 1).
13251 if (Cond.getOpcode() == ISD::AND &&
13252 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13253 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13254 if (C && C->getAPIntValue() == 1)
13255 Cond = Cond.getOperand(0);
13258 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13259 // setting operand in place of the X86ISD::SETCC.
13260 unsigned CondOpcode = Cond.getOpcode();
13261 if (CondOpcode == X86ISD::SETCC ||
13262 CondOpcode == X86ISD::SETCC_CARRY) {
13263 CC = Cond.getOperand(0);
13265 SDValue Cmp = Cond.getOperand(1);
13266 unsigned Opc = Cmp.getOpcode();
13267 MVT VT = Op.getSimpleValueType();
13269 bool IllegalFPCMov = false;
13270 if (VT.isFloatingPoint() && !VT.isVector() &&
13271 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13272 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13274 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13275 Opc == X86ISD::BT) { // FIXME
13279 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13280 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13281 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13282 Cond.getOperand(0).getValueType() != MVT::i8)) {
13283 SDValue LHS = Cond.getOperand(0);
13284 SDValue RHS = Cond.getOperand(1);
13285 unsigned X86Opcode;
13288 switch (CondOpcode) {
13289 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13290 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13291 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13292 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13293 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13294 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13295 default: llvm_unreachable("unexpected overflowing operator");
13297 if (CondOpcode == ISD::UMULO)
13298 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13301 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13303 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13305 if (CondOpcode == ISD::UMULO)
13306 Cond = X86Op.getValue(2);
13308 Cond = X86Op.getValue(1);
13310 CC = DAG.getConstant(X86Cond, MVT::i8);
13315 // Look pass the truncate if the high bits are known zero.
13316 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13317 Cond = Cond.getOperand(0);
13319 // We know the result of AND is compared against zero. Try to match
13321 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13322 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13323 if (NewSetCC.getNode()) {
13324 CC = NewSetCC.getOperand(0);
13325 Cond = NewSetCC.getOperand(1);
13332 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13333 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13336 // a < b ? -1 : 0 -> RES = ~setcc_carry
13337 // a < b ? 0 : -1 -> RES = setcc_carry
13338 // a >= b ? -1 : 0 -> RES = setcc_carry
13339 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13340 if (Cond.getOpcode() == X86ISD::SUB) {
13341 Cond = ConvertCmpIfNecessary(Cond, DAG);
13342 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13344 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13345 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13346 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13347 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13348 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13349 return DAG.getNOT(DL, Res, Res.getValueType());
13354 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13355 // widen the cmov and push the truncate through. This avoids introducing a new
13356 // branch during isel and doesn't add any extensions.
13357 if (Op.getValueType() == MVT::i8 &&
13358 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13359 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13360 if (T1.getValueType() == T2.getValueType() &&
13361 // Blacklist CopyFromReg to avoid partial register stalls.
13362 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13363 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13364 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13365 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13369 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13370 // condition is true.
13371 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13372 SDValue Ops[] = { Op2, Op1, CC, Cond };
13373 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13376 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13377 SelectionDAG &DAG) {
13378 MVT VT = Op->getSimpleValueType(0);
13379 SDValue In = Op->getOperand(0);
13380 MVT InVT = In.getSimpleValueType();
13381 MVT VTElt = VT.getVectorElementType();
13382 MVT InVTElt = InVT.getVectorElementType();
13386 if ((InVTElt == MVT::i1) &&
13387 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13388 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13390 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13391 VTElt.getSizeInBits() <= 16)) ||
13393 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13394 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13396 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13397 VTElt.getSizeInBits() >= 32))))
13398 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13400 unsigned int NumElts = VT.getVectorNumElements();
13402 if (NumElts != 8 && NumElts != 16)
13405 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13406 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13407 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13408 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13411 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13412 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13414 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13415 Constant *C = ConstantInt::get(*DAG.getContext(),
13416 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13418 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13419 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13420 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13421 MachinePointerInfo::getConstantPool(),
13422 false, false, false, Alignment);
13423 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13424 if (VT.is512BitVector())
13426 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13429 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13430 SelectionDAG &DAG) {
13431 MVT VT = Op->getSimpleValueType(0);
13432 SDValue In = Op->getOperand(0);
13433 MVT InVT = In.getSimpleValueType();
13436 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13437 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13439 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13440 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13441 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13444 if (Subtarget->hasInt256())
13445 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13447 // Optimize vectors in AVX mode
13448 // Sign extend v8i16 to v8i32 and
13451 // Divide input vector into two parts
13452 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13453 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13454 // concat the vectors to original VT
13456 unsigned NumElems = InVT.getVectorNumElements();
13457 SDValue Undef = DAG.getUNDEF(InVT);
13459 SmallVector<int,8> ShufMask1(NumElems, -1);
13460 for (unsigned i = 0; i != NumElems/2; ++i)
13463 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13465 SmallVector<int,8> ShufMask2(NumElems, -1);
13466 for (unsigned i = 0; i != NumElems/2; ++i)
13467 ShufMask2[i] = i + NumElems/2;
13469 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13471 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13472 VT.getVectorNumElements()/2);
13474 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13475 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13477 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13480 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13481 // may emit an illegal shuffle but the expansion is still better than scalar
13482 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13483 // we'll emit a shuffle and a arithmetic shift.
13484 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13485 // TODO: It is possible to support ZExt by zeroing the undef values during
13486 // the shuffle phase or after the shuffle.
13487 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13488 SelectionDAG &DAG) {
13489 MVT RegVT = Op.getSimpleValueType();
13490 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13491 assert(RegVT.isInteger() &&
13492 "We only custom lower integer vector sext loads.");
13494 // Nothing useful we can do without SSE2 shuffles.
13495 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13497 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13499 EVT MemVT = Ld->getMemoryVT();
13500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13501 unsigned RegSz = RegVT.getSizeInBits();
13503 ISD::LoadExtType Ext = Ld->getExtensionType();
13505 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13506 && "Only anyext and sext are currently implemented.");
13507 assert(MemVT != RegVT && "Cannot extend to the same type");
13508 assert(MemVT.isVector() && "Must load a vector from memory");
13510 unsigned NumElems = RegVT.getVectorNumElements();
13511 unsigned MemSz = MemVT.getSizeInBits();
13512 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13514 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13515 // The only way in which we have a legal 256-bit vector result but not the
13516 // integer 256-bit operations needed to directly lower a sextload is if we
13517 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13518 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13519 // correctly legalized. We do this late to allow the canonical form of
13520 // sextload to persist throughout the rest of the DAG combiner -- it wants
13521 // to fold together any extensions it can, and so will fuse a sign_extend
13522 // of an sextload into a sextload targeting a wider value.
13524 if (MemSz == 128) {
13525 // Just switch this to a normal load.
13526 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13527 "it must be a legal 128-bit vector "
13529 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13530 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13531 Ld->isInvariant(), Ld->getAlignment());
13533 assert(MemSz < 128 &&
13534 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13535 // Do an sext load to a 128-bit vector type. We want to use the same
13536 // number of elements, but elements half as wide. This will end up being
13537 // recursively lowered by this routine, but will succeed as we definitely
13538 // have all the necessary features if we're using AVX1.
13540 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13541 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13543 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13544 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13545 Ld->isNonTemporal(), Ld->isInvariant(),
13546 Ld->getAlignment());
13549 // Replace chain users with the new chain.
13550 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13551 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13553 // Finally, do a normal sign-extend to the desired register.
13554 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13557 // All sizes must be a power of two.
13558 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13559 "Non-power-of-two elements are not custom lowered!");
13561 // Attempt to load the original value using scalar loads.
13562 // Find the largest scalar type that divides the total loaded size.
13563 MVT SclrLoadTy = MVT::i8;
13564 for (MVT Tp : MVT::integer_valuetypes()) {
13565 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13570 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13571 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13573 SclrLoadTy = MVT::f64;
13575 // Calculate the number of scalar loads that we need to perform
13576 // in order to load our vector from memory.
13577 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13579 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13580 "Can only lower sext loads with a single scalar load!");
13582 unsigned loadRegZize = RegSz;
13583 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13586 // Represent our vector as a sequence of elements which are the
13587 // largest scalar that we can load.
13588 EVT LoadUnitVecVT = EVT::getVectorVT(
13589 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13591 // Represent the data using the same element type that is stored in
13592 // memory. In practice, we ''widen'' MemVT.
13594 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13595 loadRegZize / MemVT.getScalarType().getSizeInBits());
13597 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13598 "Invalid vector type");
13600 // We can't shuffle using an illegal type.
13601 assert(TLI.isTypeLegal(WideVecVT) &&
13602 "We only lower types that form legal widened vector types");
13604 SmallVector<SDValue, 8> Chains;
13605 SDValue Ptr = Ld->getBasePtr();
13606 SDValue Increment =
13607 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13608 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13610 for (unsigned i = 0; i < NumLoads; ++i) {
13611 // Perform a single load.
13612 SDValue ScalarLoad =
13613 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13614 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13615 Ld->getAlignment());
13616 Chains.push_back(ScalarLoad.getValue(1));
13617 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13618 // another round of DAGCombining.
13620 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13622 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13623 ScalarLoad, DAG.getIntPtrConstant(i));
13625 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13628 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13630 // Bitcast the loaded value to a vector of the original element type, in
13631 // the size of the target vector type.
13632 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13633 unsigned SizeRatio = RegSz / MemSz;
13635 if (Ext == ISD::SEXTLOAD) {
13636 // If we have SSE4.1, we can directly emit a VSEXT node.
13637 if (Subtarget->hasSSE41()) {
13638 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13639 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13643 // Otherwise we'll shuffle the small elements in the high bits of the
13644 // larger type and perform an arithmetic shift. If the shift is not legal
13645 // it's better to scalarize.
13646 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13647 "We can't implement a sext load without an arithmetic right shift!");
13649 // Redistribute the loaded elements into the different locations.
13650 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13651 for (unsigned i = 0; i != NumElems; ++i)
13652 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13654 SDValue Shuff = DAG.getVectorShuffle(
13655 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13657 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13659 // Build the arithmetic shift.
13660 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13661 MemVT.getVectorElementType().getSizeInBits();
13663 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13665 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13669 // Redistribute the loaded elements into the different locations.
13670 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13671 for (unsigned i = 0; i != NumElems; ++i)
13672 ShuffleVec[i * SizeRatio] = i;
13674 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13675 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13677 // Bitcast to the requested type.
13678 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13679 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13683 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13684 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13685 // from the AND / OR.
13686 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13687 Opc = Op.getOpcode();
13688 if (Opc != ISD::OR && Opc != ISD::AND)
13690 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13691 Op.getOperand(0).hasOneUse() &&
13692 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13693 Op.getOperand(1).hasOneUse());
13696 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13697 // 1 and that the SETCC node has a single use.
13698 static bool isXor1OfSetCC(SDValue Op) {
13699 if (Op.getOpcode() != ISD::XOR)
13701 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13702 if (N1C && N1C->getAPIntValue() == 1) {
13703 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13704 Op.getOperand(0).hasOneUse();
13709 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13710 bool addTest = true;
13711 SDValue Chain = Op.getOperand(0);
13712 SDValue Cond = Op.getOperand(1);
13713 SDValue Dest = Op.getOperand(2);
13716 bool Inverted = false;
13718 if (Cond.getOpcode() == ISD::SETCC) {
13719 // Check for setcc([su]{add,sub,mul}o == 0).
13720 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13721 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13722 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13723 Cond.getOperand(0).getResNo() == 1 &&
13724 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13725 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13726 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13727 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13728 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13729 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13731 Cond = Cond.getOperand(0);
13733 SDValue NewCond = LowerSETCC(Cond, DAG);
13734 if (NewCond.getNode())
13739 // FIXME: LowerXALUO doesn't handle these!!
13740 else if (Cond.getOpcode() == X86ISD::ADD ||
13741 Cond.getOpcode() == X86ISD::SUB ||
13742 Cond.getOpcode() == X86ISD::SMUL ||
13743 Cond.getOpcode() == X86ISD::UMUL)
13744 Cond = LowerXALUO(Cond, DAG);
13747 // Look pass (and (setcc_carry (cmp ...)), 1).
13748 if (Cond.getOpcode() == ISD::AND &&
13749 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13750 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13751 if (C && C->getAPIntValue() == 1)
13752 Cond = Cond.getOperand(0);
13755 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13756 // setting operand in place of the X86ISD::SETCC.
13757 unsigned CondOpcode = Cond.getOpcode();
13758 if (CondOpcode == X86ISD::SETCC ||
13759 CondOpcode == X86ISD::SETCC_CARRY) {
13760 CC = Cond.getOperand(0);
13762 SDValue Cmp = Cond.getOperand(1);
13763 unsigned Opc = Cmp.getOpcode();
13764 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13765 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13769 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13773 // These can only come from an arithmetic instruction with overflow,
13774 // e.g. SADDO, UADDO.
13775 Cond = Cond.getNode()->getOperand(1);
13781 CondOpcode = Cond.getOpcode();
13782 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13783 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13784 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13785 Cond.getOperand(0).getValueType() != MVT::i8)) {
13786 SDValue LHS = Cond.getOperand(0);
13787 SDValue RHS = Cond.getOperand(1);
13788 unsigned X86Opcode;
13791 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13792 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13794 switch (CondOpcode) {
13795 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13799 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13802 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13803 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13805 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13807 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13810 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13811 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13812 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13813 default: llvm_unreachable("unexpected overflowing operator");
13816 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13817 if (CondOpcode == ISD::UMULO)
13818 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13821 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13823 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13825 if (CondOpcode == ISD::UMULO)
13826 Cond = X86Op.getValue(2);
13828 Cond = X86Op.getValue(1);
13830 CC = DAG.getConstant(X86Cond, MVT::i8);
13834 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13835 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13836 if (CondOpc == ISD::OR) {
13837 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13838 // two branches instead of an explicit OR instruction with a
13840 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13841 isX86LogicalCmp(Cmp)) {
13842 CC = Cond.getOperand(0).getOperand(0);
13843 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13844 Chain, Dest, CC, Cmp);
13845 CC = Cond.getOperand(1).getOperand(0);
13849 } else { // ISD::AND
13850 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13851 // two branches instead of an explicit AND instruction with a
13852 // separate test. However, we only do this if this block doesn't
13853 // have a fall-through edge, because this requires an explicit
13854 // jmp when the condition is false.
13855 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13856 isX86LogicalCmp(Cmp) &&
13857 Op.getNode()->hasOneUse()) {
13858 X86::CondCode CCode =
13859 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13860 CCode = X86::GetOppositeBranchCondition(CCode);
13861 CC = DAG.getConstant(CCode, MVT::i8);
13862 SDNode *User = *Op.getNode()->use_begin();
13863 // Look for an unconditional branch following this conditional branch.
13864 // We need this because we need to reverse the successors in order
13865 // to implement FCMP_OEQ.
13866 if (User->getOpcode() == ISD::BR) {
13867 SDValue FalseBB = User->getOperand(1);
13869 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13870 assert(NewBR == User);
13874 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13875 Chain, Dest, CC, Cmp);
13876 X86::CondCode CCode =
13877 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13878 CCode = X86::GetOppositeBranchCondition(CCode);
13879 CC = DAG.getConstant(CCode, MVT::i8);
13885 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13886 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13887 // It should be transformed during dag combiner except when the condition
13888 // is set by a arithmetics with overflow node.
13889 X86::CondCode CCode =
13890 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13891 CCode = X86::GetOppositeBranchCondition(CCode);
13892 CC = DAG.getConstant(CCode, MVT::i8);
13893 Cond = Cond.getOperand(0).getOperand(1);
13895 } else if (Cond.getOpcode() == ISD::SETCC &&
13896 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13897 // For FCMP_OEQ, we can emit
13898 // two branches instead of an explicit AND instruction with a
13899 // separate test. However, we only do this if this block doesn't
13900 // have a fall-through edge, because this requires an explicit
13901 // jmp when the condition is false.
13902 if (Op.getNode()->hasOneUse()) {
13903 SDNode *User = *Op.getNode()->use_begin();
13904 // Look for an unconditional branch following this conditional branch.
13905 // We need this because we need to reverse the successors in order
13906 // to implement FCMP_OEQ.
13907 if (User->getOpcode() == ISD::BR) {
13908 SDValue FalseBB = User->getOperand(1);
13910 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13911 assert(NewBR == User);
13915 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13916 Cond.getOperand(0), Cond.getOperand(1));
13917 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13918 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13919 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13920 Chain, Dest, CC, Cmp);
13921 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13926 } else if (Cond.getOpcode() == ISD::SETCC &&
13927 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13928 // For FCMP_UNE, we can emit
13929 // two branches instead of an explicit AND instruction with a
13930 // separate test. However, we only do this if this block doesn't
13931 // have a fall-through edge, because this requires an explicit
13932 // jmp when the condition is false.
13933 if (Op.getNode()->hasOneUse()) {
13934 SDNode *User = *Op.getNode()->use_begin();
13935 // Look for an unconditional branch following this conditional branch.
13936 // We need this because we need to reverse the successors in order
13937 // to implement FCMP_UNE.
13938 if (User->getOpcode() == ISD::BR) {
13939 SDValue FalseBB = User->getOperand(1);
13941 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13942 assert(NewBR == User);
13945 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13946 Cond.getOperand(0), Cond.getOperand(1));
13947 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13948 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13949 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13950 Chain, Dest, CC, Cmp);
13951 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13961 // Look pass the truncate if the high bits are known zero.
13962 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13963 Cond = Cond.getOperand(0);
13965 // We know the result of AND is compared against zero. Try to match
13967 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13968 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13969 if (NewSetCC.getNode()) {
13970 CC = NewSetCC.getOperand(0);
13971 Cond = NewSetCC.getOperand(1);
13978 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13979 CC = DAG.getConstant(X86Cond, MVT::i8);
13980 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13982 Cond = ConvertCmpIfNecessary(Cond, DAG);
13983 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13984 Chain, Dest, CC, Cond);
13987 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13988 // Calls to _alloca are needed to probe the stack when allocating more than 4k
13989 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13990 // that the guard pages used by the OS virtual memory manager are allocated in
13991 // correct sequence.
13993 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13994 SelectionDAG &DAG) const {
13995 MachineFunction &MF = DAG.getMachineFunction();
13996 bool SplitStack = MF.shouldSplitStack();
13997 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14002 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14003 SDNode* Node = Op.getNode();
14005 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14006 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14007 " not tell us which reg is the stack pointer!");
14008 EVT VT = Node->getValueType(0);
14009 SDValue Tmp1 = SDValue(Node, 0);
14010 SDValue Tmp2 = SDValue(Node, 1);
14011 SDValue Tmp3 = Node->getOperand(2);
14012 SDValue Chain = Tmp1.getOperand(0);
14014 // Chain the dynamic stack allocation so that it doesn't modify the stack
14015 // pointer when other instructions are using the stack.
14016 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14019 SDValue Size = Tmp2.getOperand(1);
14020 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14021 Chain = SP.getValue(1);
14022 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14023 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14024 unsigned StackAlign = TFI.getStackAlignment();
14025 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14026 if (Align > StackAlign)
14027 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14028 DAG.getConstant(-(uint64_t)Align, VT));
14029 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14031 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14032 DAG.getIntPtrConstant(0, true), SDValue(),
14035 SDValue Ops[2] = { Tmp1, Tmp2 };
14036 return DAG.getMergeValues(Ops, dl);
14040 SDValue Chain = Op.getOperand(0);
14041 SDValue Size = Op.getOperand(1);
14042 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14043 EVT VT = Op.getNode()->getValueType(0);
14045 bool Is64Bit = Subtarget->is64Bit();
14046 EVT SPTy = getPointerTy();
14049 MachineRegisterInfo &MRI = MF.getRegInfo();
14052 // The 64 bit implementation of segmented stacks needs to clobber both r10
14053 // r11. This makes it impossible to use it along with nested parameters.
14054 const Function *F = MF.getFunction();
14056 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14058 if (I->hasNestAttr())
14059 report_fatal_error("Cannot use segmented stacks with functions that "
14060 "have nested arguments.");
14063 const TargetRegisterClass *AddrRegClass =
14064 getRegClassFor(getPointerTy());
14065 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14066 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14067 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14068 DAG.getRegister(Vreg, SPTy));
14069 SDValue Ops1[2] = { Value, Chain };
14070 return DAG.getMergeValues(Ops1, dl);
14073 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14075 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14076 Flag = Chain.getValue(1);
14077 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14079 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14081 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14082 unsigned SPReg = RegInfo->getStackRegister();
14083 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14084 Chain = SP.getValue(1);
14087 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14088 DAG.getConstant(-(uint64_t)Align, VT));
14089 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14092 SDValue Ops1[2] = { SP, Chain };
14093 return DAG.getMergeValues(Ops1, dl);
14097 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14098 MachineFunction &MF = DAG.getMachineFunction();
14099 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14101 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14104 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14105 // vastart just stores the address of the VarArgsFrameIndex slot into the
14106 // memory location argument.
14107 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14109 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14110 MachinePointerInfo(SV), false, false, 0);
14114 // gp_offset (0 - 6 * 8)
14115 // fp_offset (48 - 48 + 8 * 16)
14116 // overflow_arg_area (point to parameters coming in memory).
14118 SmallVector<SDValue, 8> MemOps;
14119 SDValue FIN = Op.getOperand(1);
14121 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14122 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14124 FIN, MachinePointerInfo(SV), false, false, 0);
14125 MemOps.push_back(Store);
14128 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14129 FIN, DAG.getIntPtrConstant(4));
14130 Store = DAG.getStore(Op.getOperand(0), DL,
14131 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14133 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14134 MemOps.push_back(Store);
14136 // Store ptr to overflow_arg_area
14137 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14138 FIN, DAG.getIntPtrConstant(4));
14139 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14141 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14142 MachinePointerInfo(SV, 8),
14144 MemOps.push_back(Store);
14146 // Store ptr to reg_save_area.
14147 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14148 FIN, DAG.getIntPtrConstant(8));
14149 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14151 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14152 MachinePointerInfo(SV, 16), false, false, 0);
14153 MemOps.push_back(Store);
14154 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14157 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14158 assert(Subtarget->is64Bit() &&
14159 "LowerVAARG only handles 64-bit va_arg!");
14160 assert((Subtarget->isTargetLinux() ||
14161 Subtarget->isTargetDarwin()) &&
14162 "Unhandled target in LowerVAARG");
14163 assert(Op.getNode()->getNumOperands() == 4);
14164 SDValue Chain = Op.getOperand(0);
14165 SDValue SrcPtr = Op.getOperand(1);
14166 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14167 unsigned Align = Op.getConstantOperandVal(3);
14170 EVT ArgVT = Op.getNode()->getValueType(0);
14171 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14172 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14175 // Decide which area this value should be read from.
14176 // TODO: Implement the AMD64 ABI in its entirety. This simple
14177 // selection mechanism works only for the basic types.
14178 if (ArgVT == MVT::f80) {
14179 llvm_unreachable("va_arg for f80 not yet implemented");
14180 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14181 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14182 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14183 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14185 llvm_unreachable("Unhandled argument type in LowerVAARG");
14188 if (ArgMode == 2) {
14189 // Sanity Check: Make sure using fp_offset makes sense.
14190 assert(!DAG.getTarget().Options.UseSoftFloat &&
14191 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14192 Attribute::NoImplicitFloat)) &&
14193 Subtarget->hasSSE1());
14196 // Insert VAARG_64 node into the DAG
14197 // VAARG_64 returns two values: Variable Argument Address, Chain
14198 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
14199 DAG.getConstant(ArgMode, MVT::i8),
14200 DAG.getConstant(Align, MVT::i32)};
14201 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14202 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14203 VTs, InstOps, MVT::i64,
14204 MachinePointerInfo(SV),
14206 /*Volatile=*/false,
14208 /*WriteMem=*/true);
14209 Chain = VAARG.getValue(1);
14211 // Load the next argument and return it
14212 return DAG.getLoad(ArgVT, dl,
14215 MachinePointerInfo(),
14216 false, false, false, 0);
14219 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14220 SelectionDAG &DAG) {
14221 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14222 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14223 SDValue Chain = Op.getOperand(0);
14224 SDValue DstPtr = Op.getOperand(1);
14225 SDValue SrcPtr = Op.getOperand(2);
14226 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14227 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14230 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14231 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14233 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14236 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14237 // amount is a constant. Takes immediate version of shift as input.
14238 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14239 SDValue SrcOp, uint64_t ShiftAmt,
14240 SelectionDAG &DAG) {
14241 MVT ElementType = VT.getVectorElementType();
14243 // Fold this packed shift into its first operand if ShiftAmt is 0.
14247 // Check for ShiftAmt >= element width
14248 if (ShiftAmt >= ElementType.getSizeInBits()) {
14249 if (Opc == X86ISD::VSRAI)
14250 ShiftAmt = ElementType.getSizeInBits() - 1;
14252 return DAG.getConstant(0, VT);
14255 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14256 && "Unknown target vector shift-by-constant node");
14258 // Fold this packed vector shift into a build vector if SrcOp is a
14259 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14260 if (VT == SrcOp.getSimpleValueType() &&
14261 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14262 SmallVector<SDValue, 8> Elts;
14263 unsigned NumElts = SrcOp->getNumOperands();
14264 ConstantSDNode *ND;
14267 default: llvm_unreachable(nullptr);
14268 case X86ISD::VSHLI:
14269 for (unsigned i=0; i!=NumElts; ++i) {
14270 SDValue CurrentOp = SrcOp->getOperand(i);
14271 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14272 Elts.push_back(CurrentOp);
14275 ND = cast<ConstantSDNode>(CurrentOp);
14276 const APInt &C = ND->getAPIntValue();
14277 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14280 case X86ISD::VSRLI:
14281 for (unsigned i=0; i!=NumElts; ++i) {
14282 SDValue CurrentOp = SrcOp->getOperand(i);
14283 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14284 Elts.push_back(CurrentOp);
14287 ND = cast<ConstantSDNode>(CurrentOp);
14288 const APInt &C = ND->getAPIntValue();
14289 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14292 case X86ISD::VSRAI:
14293 for (unsigned i=0; i!=NumElts; ++i) {
14294 SDValue CurrentOp = SrcOp->getOperand(i);
14295 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14296 Elts.push_back(CurrentOp);
14299 ND = cast<ConstantSDNode>(CurrentOp);
14300 const APInt &C = ND->getAPIntValue();
14301 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14306 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14309 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14312 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14313 // may or may not be a constant. Takes immediate version of shift as input.
14314 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14315 SDValue SrcOp, SDValue ShAmt,
14316 SelectionDAG &DAG) {
14317 MVT SVT = ShAmt.getSimpleValueType();
14318 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14320 // Catch shift-by-constant.
14321 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14322 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14323 CShAmt->getZExtValue(), DAG);
14325 // Change opcode to non-immediate version
14327 default: llvm_unreachable("Unknown target vector shift node");
14328 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14329 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14330 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14333 const X86Subtarget &Subtarget =
14334 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14335 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14336 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14337 // Let the shuffle legalizer expand this shift amount node.
14338 SDValue Op0 = ShAmt.getOperand(0);
14339 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14340 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14342 // Need to build a vector containing shift amount.
14343 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14344 SmallVector<SDValue, 4> ShOps;
14345 ShOps.push_back(ShAmt);
14346 if (SVT == MVT::i32) {
14347 ShOps.push_back(DAG.getConstant(0, SVT));
14348 ShOps.push_back(DAG.getUNDEF(SVT));
14350 ShOps.push_back(DAG.getUNDEF(SVT));
14352 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14353 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14356 // The return type has to be a 128-bit type with the same element
14357 // type as the input type.
14358 MVT EltVT = VT.getVectorElementType();
14359 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14361 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14362 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14365 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14366 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14367 /// necessary casting for \p Mask when lowering masking intrinsics.
14368 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14369 SDValue PreservedSrc,
14370 const X86Subtarget *Subtarget,
14371 SelectionDAG &DAG) {
14372 EVT VT = Op.getValueType();
14373 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14374 MVT::i1, VT.getVectorNumElements());
14375 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14376 Mask.getValueType().getSizeInBits());
14379 assert(MaskVT.isSimple() && "invalid mask type");
14381 if (isAllOnes(Mask))
14384 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14385 // are extracted by EXTRACT_SUBVECTOR.
14386 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14387 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14388 DAG.getIntPtrConstant(0));
14390 switch (Op.getOpcode()) {
14392 case X86ISD::PCMPEQM:
14393 case X86ISD::PCMPGTM:
14395 case X86ISD::CMPMU:
14396 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14398 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14399 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14400 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14403 /// \brief Creates an SDNode for a predicated scalar operation.
14404 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14405 /// The mask is comming as MVT::i8 and it should be truncated
14406 /// to MVT::i1 while lowering masking intrinsics.
14407 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14408 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14409 /// a scalar instruction.
14410 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14411 SDValue PreservedSrc,
14412 const X86Subtarget *Subtarget,
14413 SelectionDAG &DAG) {
14414 if (isAllOnes(Mask))
14417 EVT VT = Op.getValueType();
14419 // The mask should be of type MVT::i1
14420 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14422 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14423 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14424 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14427 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14428 SelectionDAG &DAG) {
14430 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14431 EVT VT = Op.getValueType();
14432 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14434 switch(IntrData->Type) {
14435 case INTR_TYPE_1OP:
14436 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14437 case INTR_TYPE_2OP:
14438 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14440 case INTR_TYPE_3OP:
14441 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14442 Op.getOperand(2), Op.getOperand(3));
14443 case INTR_TYPE_1OP_MASK_RM: {
14444 SDValue Src = Op.getOperand(1);
14445 SDValue Src0 = Op.getOperand(2);
14446 SDValue Mask = Op.getOperand(3);
14447 SDValue RoundingMode = Op.getOperand(4);
14448 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14450 Mask, Src0, Subtarget, DAG);
14452 case INTR_TYPE_SCALAR_MASK_RM: {
14453 SDValue Src1 = Op.getOperand(1);
14454 SDValue Src2 = Op.getOperand(2);
14455 SDValue Src0 = Op.getOperand(3);
14456 SDValue Mask = Op.getOperand(4);
14457 // There are 2 kinds of intrinsics in this group:
14458 // (1) With supress-all-exceptions (sae) - 6 operands
14459 // (2) With rounding mode and sae - 7 operands.
14460 if (Op.getNumOperands() == 6) {
14461 SDValue Sae = Op.getOperand(5);
14462 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14464 Mask, Src0, Subtarget, DAG);
14466 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14467 SDValue RoundingMode = Op.getOperand(5);
14468 SDValue Sae = Op.getOperand(6);
14469 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14470 RoundingMode, Sae),
14471 Mask, Src0, Subtarget, DAG);
14473 case INTR_TYPE_2OP_MASK: {
14474 SDValue Src1 = Op.getOperand(1);
14475 SDValue Src2 = Op.getOperand(2);
14476 SDValue PassThru = Op.getOperand(3);
14477 SDValue Mask = Op.getOperand(4);
14478 // We specify 2 possible opcodes for intrinsics with rounding modes.
14479 // First, we check if the intrinsic may have non-default rounding mode,
14480 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14481 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14482 if (IntrWithRoundingModeOpcode != 0) {
14483 SDValue Rnd = Op.getOperand(5);
14484 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14485 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14486 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14487 dl, Op.getValueType(),
14489 Mask, PassThru, Subtarget, DAG);
14492 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14494 Mask, PassThru, Subtarget, DAG);
14496 case FMA_OP_MASK: {
14497 SDValue Src1 = Op.getOperand(1);
14498 SDValue Src2 = Op.getOperand(2);
14499 SDValue Src3 = Op.getOperand(3);
14500 SDValue Mask = Op.getOperand(4);
14501 // We specify 2 possible opcodes for intrinsics with rounding modes.
14502 // First, we check if the intrinsic may have non-default rounding mode,
14503 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14504 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14505 if (IntrWithRoundingModeOpcode != 0) {
14506 SDValue Rnd = Op.getOperand(5);
14507 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14508 X86::STATIC_ROUNDING::CUR_DIRECTION)
14509 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14510 dl, Op.getValueType(),
14511 Src1, Src2, Src3, Rnd),
14512 Mask, Src1, Subtarget, DAG);
14514 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14515 dl, Op.getValueType(),
14517 Mask, Src1, Subtarget, DAG);
14520 case CMP_MASK_CC: {
14521 // Comparison intrinsics with masks.
14522 // Example of transformation:
14523 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14524 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14526 // (v8i1 (insert_subvector undef,
14527 // (v2i1 (and (PCMPEQM %a, %b),
14528 // (extract_subvector
14529 // (v8i1 (bitcast %mask)), 0))), 0))))
14530 EVT VT = Op.getOperand(1).getValueType();
14531 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14532 VT.getVectorNumElements());
14533 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14534 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14535 Mask.getValueType().getSizeInBits());
14537 if (IntrData->Type == CMP_MASK_CC) {
14538 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14539 Op.getOperand(2), Op.getOperand(3));
14541 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14542 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14545 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14546 DAG.getTargetConstant(0, MaskVT),
14548 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14549 DAG.getUNDEF(BitcastVT), CmpMask,
14550 DAG.getIntPtrConstant(0));
14551 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14553 case COMI: { // Comparison intrinsics
14554 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14555 SDValue LHS = Op.getOperand(1);
14556 SDValue RHS = Op.getOperand(2);
14557 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14558 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14559 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14560 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14561 DAG.getConstant(X86CC, MVT::i8), Cond);
14562 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14565 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14566 Op.getOperand(1), Op.getOperand(2), DAG);
14568 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
14569 Op.getSimpleValueType(),
14571 Op.getOperand(2), DAG),
14572 Op.getOperand(4), Op.getOperand(3), Subtarget,
14574 case COMPRESS_EXPAND_IN_REG: {
14575 SDValue Mask = Op.getOperand(3);
14576 SDValue DataToCompress = Op.getOperand(1);
14577 SDValue PassThru = Op.getOperand(2);
14578 if (isAllOnes(Mask)) // return data as is
14579 return Op.getOperand(1);
14580 EVT VT = Op.getValueType();
14581 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14582 VT.getVectorNumElements());
14583 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14584 Mask.getValueType().getSizeInBits());
14586 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14587 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14588 DAG.getIntPtrConstant(0));
14590 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
14594 SDValue Mask = Op.getOperand(3);
14595 EVT VT = Op.getValueType();
14596 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14597 VT.getVectorNumElements());
14598 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14599 Mask.getValueType().getSizeInBits());
14601 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14602 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14603 DAG.getIntPtrConstant(0));
14604 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
14613 default: return SDValue(); // Don't custom lower most intrinsics.
14615 case Intrinsic::x86_avx512_mask_valign_q_512:
14616 case Intrinsic::x86_avx512_mask_valign_d_512:
14617 // Vector source operands are swapped.
14618 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14619 Op.getValueType(), Op.getOperand(2),
14622 Op.getOperand(5), Op.getOperand(4),
14625 // ptest and testp intrinsics. The intrinsic these come from are designed to
14626 // return an integer value, not just an instruction so lower it to the ptest
14627 // or testp pattern and a setcc for the result.
14628 case Intrinsic::x86_sse41_ptestz:
14629 case Intrinsic::x86_sse41_ptestc:
14630 case Intrinsic::x86_sse41_ptestnzc:
14631 case Intrinsic::x86_avx_ptestz_256:
14632 case Intrinsic::x86_avx_ptestc_256:
14633 case Intrinsic::x86_avx_ptestnzc_256:
14634 case Intrinsic::x86_avx_vtestz_ps:
14635 case Intrinsic::x86_avx_vtestc_ps:
14636 case Intrinsic::x86_avx_vtestnzc_ps:
14637 case Intrinsic::x86_avx_vtestz_pd:
14638 case Intrinsic::x86_avx_vtestc_pd:
14639 case Intrinsic::x86_avx_vtestnzc_pd:
14640 case Intrinsic::x86_avx_vtestz_ps_256:
14641 case Intrinsic::x86_avx_vtestc_ps_256:
14642 case Intrinsic::x86_avx_vtestnzc_ps_256:
14643 case Intrinsic::x86_avx_vtestz_pd_256:
14644 case Intrinsic::x86_avx_vtestc_pd_256:
14645 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14646 bool IsTestPacked = false;
14649 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14650 case Intrinsic::x86_avx_vtestz_ps:
14651 case Intrinsic::x86_avx_vtestz_pd:
14652 case Intrinsic::x86_avx_vtestz_ps_256:
14653 case Intrinsic::x86_avx_vtestz_pd_256:
14654 IsTestPacked = true; // Fallthrough
14655 case Intrinsic::x86_sse41_ptestz:
14656 case Intrinsic::x86_avx_ptestz_256:
14658 X86CC = X86::COND_E;
14660 case Intrinsic::x86_avx_vtestc_ps:
14661 case Intrinsic::x86_avx_vtestc_pd:
14662 case Intrinsic::x86_avx_vtestc_ps_256:
14663 case Intrinsic::x86_avx_vtestc_pd_256:
14664 IsTestPacked = true; // Fallthrough
14665 case Intrinsic::x86_sse41_ptestc:
14666 case Intrinsic::x86_avx_ptestc_256:
14668 X86CC = X86::COND_B;
14670 case Intrinsic::x86_avx_vtestnzc_ps:
14671 case Intrinsic::x86_avx_vtestnzc_pd:
14672 case Intrinsic::x86_avx_vtestnzc_ps_256:
14673 case Intrinsic::x86_avx_vtestnzc_pd_256:
14674 IsTestPacked = true; // Fallthrough
14675 case Intrinsic::x86_sse41_ptestnzc:
14676 case Intrinsic::x86_avx_ptestnzc_256:
14678 X86CC = X86::COND_A;
14682 SDValue LHS = Op.getOperand(1);
14683 SDValue RHS = Op.getOperand(2);
14684 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14685 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14686 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14687 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14688 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14690 case Intrinsic::x86_avx512_kortestz_w:
14691 case Intrinsic::x86_avx512_kortestc_w: {
14692 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14693 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14694 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14695 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14696 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14697 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14698 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14701 case Intrinsic::x86_sse42_pcmpistria128:
14702 case Intrinsic::x86_sse42_pcmpestria128:
14703 case Intrinsic::x86_sse42_pcmpistric128:
14704 case Intrinsic::x86_sse42_pcmpestric128:
14705 case Intrinsic::x86_sse42_pcmpistrio128:
14706 case Intrinsic::x86_sse42_pcmpestrio128:
14707 case Intrinsic::x86_sse42_pcmpistris128:
14708 case Intrinsic::x86_sse42_pcmpestris128:
14709 case Intrinsic::x86_sse42_pcmpistriz128:
14710 case Intrinsic::x86_sse42_pcmpestriz128: {
14714 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14715 case Intrinsic::x86_sse42_pcmpistria128:
14716 Opcode = X86ISD::PCMPISTRI;
14717 X86CC = X86::COND_A;
14719 case Intrinsic::x86_sse42_pcmpestria128:
14720 Opcode = X86ISD::PCMPESTRI;
14721 X86CC = X86::COND_A;
14723 case Intrinsic::x86_sse42_pcmpistric128:
14724 Opcode = X86ISD::PCMPISTRI;
14725 X86CC = X86::COND_B;
14727 case Intrinsic::x86_sse42_pcmpestric128:
14728 Opcode = X86ISD::PCMPESTRI;
14729 X86CC = X86::COND_B;
14731 case Intrinsic::x86_sse42_pcmpistrio128:
14732 Opcode = X86ISD::PCMPISTRI;
14733 X86CC = X86::COND_O;
14735 case Intrinsic::x86_sse42_pcmpestrio128:
14736 Opcode = X86ISD::PCMPESTRI;
14737 X86CC = X86::COND_O;
14739 case Intrinsic::x86_sse42_pcmpistris128:
14740 Opcode = X86ISD::PCMPISTRI;
14741 X86CC = X86::COND_S;
14743 case Intrinsic::x86_sse42_pcmpestris128:
14744 Opcode = X86ISD::PCMPESTRI;
14745 X86CC = X86::COND_S;
14747 case Intrinsic::x86_sse42_pcmpistriz128:
14748 Opcode = X86ISD::PCMPISTRI;
14749 X86CC = X86::COND_E;
14751 case Intrinsic::x86_sse42_pcmpestriz128:
14752 Opcode = X86ISD::PCMPESTRI;
14753 X86CC = X86::COND_E;
14756 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14757 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14758 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14759 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14760 DAG.getConstant(X86CC, MVT::i8),
14761 SDValue(PCMP.getNode(), 1));
14762 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14765 case Intrinsic::x86_sse42_pcmpistri128:
14766 case Intrinsic::x86_sse42_pcmpestri128: {
14768 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14769 Opcode = X86ISD::PCMPISTRI;
14771 Opcode = X86ISD::PCMPESTRI;
14773 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14774 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14775 return DAG.getNode(Opcode, dl, VTs, NewOps);
14780 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14781 SDValue Src, SDValue Mask, SDValue Base,
14782 SDValue Index, SDValue ScaleOp, SDValue Chain,
14783 const X86Subtarget * Subtarget) {
14785 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14786 assert(C && "Invalid scale type");
14787 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14788 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14789 Index.getSimpleValueType().getVectorNumElements());
14791 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14793 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14795 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14796 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14797 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14798 SDValue Segment = DAG.getRegister(0, MVT::i32);
14799 if (Src.getOpcode() == ISD::UNDEF)
14800 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14801 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14802 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14803 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14804 return DAG.getMergeValues(RetOps, dl);
14807 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14808 SDValue Src, SDValue Mask, SDValue Base,
14809 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14811 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14812 assert(C && "Invalid scale type");
14813 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14814 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14815 SDValue Segment = DAG.getRegister(0, MVT::i32);
14816 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14817 Index.getSimpleValueType().getVectorNumElements());
14819 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14821 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14823 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14824 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14825 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14826 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14827 return SDValue(Res, 1);
14830 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14831 SDValue Mask, SDValue Base, SDValue Index,
14832 SDValue ScaleOp, SDValue Chain) {
14834 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14835 assert(C && "Invalid scale type");
14836 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14837 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14838 SDValue Segment = DAG.getRegister(0, MVT::i32);
14840 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14842 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14844 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14846 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14847 //SDVTList VTs = DAG.getVTList(MVT::Other);
14848 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14849 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14850 return SDValue(Res, 0);
14853 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14854 // read performance monitor counters (x86_rdpmc).
14855 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14856 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14857 SmallVectorImpl<SDValue> &Results) {
14858 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14859 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14862 // The ECX register is used to select the index of the performance counter
14864 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14866 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14868 // Reads the content of a 64-bit performance counter and returns it in the
14869 // registers EDX:EAX.
14870 if (Subtarget->is64Bit()) {
14871 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14872 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14875 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14876 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14879 Chain = HI.getValue(1);
14881 if (Subtarget->is64Bit()) {
14882 // The EAX register is loaded with the low-order 32 bits. The EDX register
14883 // is loaded with the supported high-order bits of the counter.
14884 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14885 DAG.getConstant(32, MVT::i8));
14886 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14887 Results.push_back(Chain);
14891 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14892 SDValue Ops[] = { LO, HI };
14893 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14894 Results.push_back(Pair);
14895 Results.push_back(Chain);
14898 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14899 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14900 // also used to custom lower READCYCLECOUNTER nodes.
14901 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14902 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14903 SmallVectorImpl<SDValue> &Results) {
14904 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14905 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14908 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14909 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14910 // and the EAX register is loaded with the low-order 32 bits.
14911 if (Subtarget->is64Bit()) {
14912 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14913 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14916 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14917 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14920 SDValue Chain = HI.getValue(1);
14922 if (Opcode == X86ISD::RDTSCP_DAG) {
14923 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14925 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14926 // the ECX register. Add 'ecx' explicitly to the chain.
14927 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14929 // Explicitly store the content of ECX at the location passed in input
14930 // to the 'rdtscp' intrinsic.
14931 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14932 MachinePointerInfo(), false, false, 0);
14935 if (Subtarget->is64Bit()) {
14936 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14937 // the EAX register is loaded with the low-order 32 bits.
14938 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14939 DAG.getConstant(32, MVT::i8));
14940 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14941 Results.push_back(Chain);
14945 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14946 SDValue Ops[] = { LO, HI };
14947 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14948 Results.push_back(Pair);
14949 Results.push_back(Chain);
14952 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14953 SelectionDAG &DAG) {
14954 SmallVector<SDValue, 2> Results;
14956 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14958 return DAG.getMergeValues(Results, DL);
14962 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14963 SelectionDAG &DAG) {
14964 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14966 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
14971 switch(IntrData->Type) {
14973 llvm_unreachable("Unknown Intrinsic Type");
14977 // Emit the node with the right value type.
14978 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14979 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
14981 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14982 // Otherwise return the value from Rand, which is always 0, casted to i32.
14983 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14984 DAG.getConstant(1, Op->getValueType(1)),
14985 DAG.getConstant(X86::COND_B, MVT::i32),
14986 SDValue(Result.getNode(), 1) };
14987 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14988 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14991 // Return { result, isValid, chain }.
14992 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14993 SDValue(Result.getNode(), 2));
14996 //gather(v1, mask, index, base, scale);
14997 SDValue Chain = Op.getOperand(0);
14998 SDValue Src = Op.getOperand(2);
14999 SDValue Base = Op.getOperand(3);
15000 SDValue Index = Op.getOperand(4);
15001 SDValue Mask = Op.getOperand(5);
15002 SDValue Scale = Op.getOperand(6);
15003 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15007 //scatter(base, mask, index, v1, scale);
15008 SDValue Chain = Op.getOperand(0);
15009 SDValue Base = Op.getOperand(2);
15010 SDValue Mask = Op.getOperand(3);
15011 SDValue Index = Op.getOperand(4);
15012 SDValue Src = Op.getOperand(5);
15013 SDValue Scale = Op.getOperand(6);
15014 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15017 SDValue Hint = Op.getOperand(6);
15019 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15020 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15021 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15022 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15023 SDValue Chain = Op.getOperand(0);
15024 SDValue Mask = Op.getOperand(2);
15025 SDValue Index = Op.getOperand(3);
15026 SDValue Base = Op.getOperand(4);
15027 SDValue Scale = Op.getOperand(5);
15028 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15030 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15032 SmallVector<SDValue, 2> Results;
15033 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15034 return DAG.getMergeValues(Results, dl);
15036 // Read Performance Monitoring Counters.
15038 SmallVector<SDValue, 2> Results;
15039 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15040 return DAG.getMergeValues(Results, dl);
15042 // XTEST intrinsics.
15044 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15045 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15046 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15047 DAG.getConstant(X86::COND_NE, MVT::i8),
15049 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15050 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15051 Ret, SDValue(InTrans.getNode(), 1));
15055 SmallVector<SDValue, 2> Results;
15056 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15057 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15058 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15059 DAG.getConstant(-1, MVT::i8));
15060 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15061 Op.getOperand(4), GenCF.getValue(1));
15062 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15063 Op.getOperand(5), MachinePointerInfo(),
15065 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15066 DAG.getConstant(X86::COND_B, MVT::i8),
15068 Results.push_back(SetCC);
15069 Results.push_back(Store);
15070 return DAG.getMergeValues(Results, dl);
15072 case COMPRESS_TO_MEM: {
15074 SDValue Mask = Op.getOperand(4);
15075 SDValue DataToCompress = Op.getOperand(3);
15076 SDValue Addr = Op.getOperand(2);
15077 SDValue Chain = Op.getOperand(0);
15079 if (isAllOnes(Mask)) // return just a store
15080 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15081 MachinePointerInfo(), false, false, 0);
15083 EVT VT = DataToCompress.getValueType();
15084 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15085 VT.getVectorNumElements());
15086 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15087 Mask.getValueType().getSizeInBits());
15088 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15089 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15090 DAG.getIntPtrConstant(0));
15092 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15093 DataToCompress, DAG.getUNDEF(VT));
15094 return DAG.getStore(Chain, dl, Compressed, Addr,
15095 MachinePointerInfo(), false, false, 0);
15097 case EXPAND_FROM_MEM: {
15099 SDValue Mask = Op.getOperand(4);
15100 SDValue PathThru = Op.getOperand(3);
15101 SDValue Addr = Op.getOperand(2);
15102 SDValue Chain = Op.getOperand(0);
15103 EVT VT = Op.getValueType();
15105 if (isAllOnes(Mask)) // return just a load
15106 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15108 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15109 VT.getVectorNumElements());
15110 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15111 Mask.getValueType().getSizeInBits());
15112 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15113 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15114 DAG.getIntPtrConstant(0));
15116 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15117 false, false, false, 0);
15119 SDValue Results[] = {
15120 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15122 return DAG.getMergeValues(Results, dl);
15127 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15128 SelectionDAG &DAG) const {
15129 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15130 MFI->setReturnAddressIsTaken(true);
15132 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15135 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15137 EVT PtrVT = getPointerTy();
15140 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15141 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15142 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15143 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15144 DAG.getNode(ISD::ADD, dl, PtrVT,
15145 FrameAddr, Offset),
15146 MachinePointerInfo(), false, false, false, 0);
15149 // Just load the return address.
15150 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15151 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15152 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15155 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15156 MachineFunction &MF = DAG.getMachineFunction();
15157 MachineFrameInfo *MFI = MF.getFrameInfo();
15158 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15159 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15160 EVT VT = Op.getValueType();
15162 MFI->setFrameAddressIsTaken(true);
15164 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15165 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15166 // is not possible to crawl up the stack without looking at the unwind codes
15168 int FrameAddrIndex = FuncInfo->getFAIndex();
15169 if (!FrameAddrIndex) {
15170 // Set up a frame object for the return address.
15171 unsigned SlotSize = RegInfo->getSlotSize();
15172 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15173 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15174 FuncInfo->setFAIndex(FrameAddrIndex);
15176 return DAG.getFrameIndex(FrameAddrIndex, VT);
15179 unsigned FrameReg =
15180 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15181 SDLoc dl(Op); // FIXME probably not meaningful
15182 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15183 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15184 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15185 "Invalid Frame Register!");
15186 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15188 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15189 MachinePointerInfo(),
15190 false, false, false, 0);
15194 // FIXME? Maybe this could be a TableGen attribute on some registers and
15195 // this table could be generated automatically from RegInfo.
15196 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15198 unsigned Reg = StringSwitch<unsigned>(RegName)
15199 .Case("esp", X86::ESP)
15200 .Case("rsp", X86::RSP)
15204 report_fatal_error("Invalid register name global variable");
15207 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15208 SelectionDAG &DAG) const {
15209 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15210 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15213 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15214 SDValue Chain = Op.getOperand(0);
15215 SDValue Offset = Op.getOperand(1);
15216 SDValue Handler = Op.getOperand(2);
15219 EVT PtrVT = getPointerTy();
15220 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15221 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15222 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15223 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15224 "Invalid Frame Register!");
15225 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15226 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15228 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15229 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15230 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15231 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15233 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15235 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15236 DAG.getRegister(StoreAddrReg, PtrVT));
15239 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15240 SelectionDAG &DAG) const {
15242 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15243 DAG.getVTList(MVT::i32, MVT::Other),
15244 Op.getOperand(0), Op.getOperand(1));
15247 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15248 SelectionDAG &DAG) const {
15250 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15251 Op.getOperand(0), Op.getOperand(1));
15254 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15255 return Op.getOperand(0);
15258 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15259 SelectionDAG &DAG) const {
15260 SDValue Root = Op.getOperand(0);
15261 SDValue Trmp = Op.getOperand(1); // trampoline
15262 SDValue FPtr = Op.getOperand(2); // nested function
15263 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15266 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15267 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15269 if (Subtarget->is64Bit()) {
15270 SDValue OutChains[6];
15272 // Large code-model.
15273 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15274 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15276 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15277 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15279 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15281 // Load the pointer to the nested function into R11.
15282 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15283 SDValue Addr = Trmp;
15284 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15285 Addr, MachinePointerInfo(TrmpAddr),
15288 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15289 DAG.getConstant(2, MVT::i64));
15290 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15291 MachinePointerInfo(TrmpAddr, 2),
15294 // Load the 'nest' parameter value into R10.
15295 // R10 is specified in X86CallingConv.td
15296 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15297 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15298 DAG.getConstant(10, MVT::i64));
15299 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15300 Addr, MachinePointerInfo(TrmpAddr, 10),
15303 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15304 DAG.getConstant(12, MVT::i64));
15305 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15306 MachinePointerInfo(TrmpAddr, 12),
15309 // Jump to the nested function.
15310 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15311 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15312 DAG.getConstant(20, MVT::i64));
15313 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15314 Addr, MachinePointerInfo(TrmpAddr, 20),
15317 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15318 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15319 DAG.getConstant(22, MVT::i64));
15320 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15321 MachinePointerInfo(TrmpAddr, 22),
15324 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15326 const Function *Func =
15327 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15328 CallingConv::ID CC = Func->getCallingConv();
15333 llvm_unreachable("Unsupported calling convention");
15334 case CallingConv::C:
15335 case CallingConv::X86_StdCall: {
15336 // Pass 'nest' parameter in ECX.
15337 // Must be kept in sync with X86CallingConv.td
15338 NestReg = X86::ECX;
15340 // Check that ECX wasn't needed by an 'inreg' parameter.
15341 FunctionType *FTy = Func->getFunctionType();
15342 const AttributeSet &Attrs = Func->getAttributes();
15344 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15345 unsigned InRegCount = 0;
15348 for (FunctionType::param_iterator I = FTy->param_begin(),
15349 E = FTy->param_end(); I != E; ++I, ++Idx)
15350 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15351 // FIXME: should only count parameters that are lowered to integers.
15352 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15354 if (InRegCount > 2) {
15355 report_fatal_error("Nest register in use - reduce number of inreg"
15361 case CallingConv::X86_FastCall:
15362 case CallingConv::X86_ThisCall:
15363 case CallingConv::Fast:
15364 // Pass 'nest' parameter in EAX.
15365 // Must be kept in sync with X86CallingConv.td
15366 NestReg = X86::EAX;
15370 SDValue OutChains[4];
15371 SDValue Addr, Disp;
15373 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15374 DAG.getConstant(10, MVT::i32));
15375 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15377 // This is storing the opcode for MOV32ri.
15378 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15379 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15380 OutChains[0] = DAG.getStore(Root, dl,
15381 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15382 Trmp, MachinePointerInfo(TrmpAddr),
15385 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15386 DAG.getConstant(1, MVT::i32));
15387 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15388 MachinePointerInfo(TrmpAddr, 1),
15391 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15392 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15393 DAG.getConstant(5, MVT::i32));
15394 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15395 MachinePointerInfo(TrmpAddr, 5),
15398 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15399 DAG.getConstant(6, MVT::i32));
15400 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15401 MachinePointerInfo(TrmpAddr, 6),
15404 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15408 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15409 SelectionDAG &DAG) const {
15411 The rounding mode is in bits 11:10 of FPSR, and has the following
15413 00 Round to nearest
15418 FLT_ROUNDS, on the other hand, expects the following:
15425 To perform the conversion, we do:
15426 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15429 MachineFunction &MF = DAG.getMachineFunction();
15430 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15431 unsigned StackAlignment = TFI.getStackAlignment();
15432 MVT VT = Op.getSimpleValueType();
15435 // Save FP Control Word to stack slot
15436 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15437 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15439 MachineMemOperand *MMO =
15440 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15441 MachineMemOperand::MOStore, 2, 2);
15443 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15444 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15445 DAG.getVTList(MVT::Other),
15446 Ops, MVT::i16, MMO);
15448 // Load FP Control Word from stack slot
15449 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15450 MachinePointerInfo(), false, false, false, 0);
15452 // Transform as necessary
15454 DAG.getNode(ISD::SRL, DL, MVT::i16,
15455 DAG.getNode(ISD::AND, DL, MVT::i16,
15456 CWD, DAG.getConstant(0x800, MVT::i16)),
15457 DAG.getConstant(11, MVT::i8));
15459 DAG.getNode(ISD::SRL, DL, MVT::i16,
15460 DAG.getNode(ISD::AND, DL, MVT::i16,
15461 CWD, DAG.getConstant(0x400, MVT::i16)),
15462 DAG.getConstant(9, MVT::i8));
15465 DAG.getNode(ISD::AND, DL, MVT::i16,
15466 DAG.getNode(ISD::ADD, DL, MVT::i16,
15467 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15468 DAG.getConstant(1, MVT::i16)),
15469 DAG.getConstant(3, MVT::i16));
15471 return DAG.getNode((VT.getSizeInBits() < 16 ?
15472 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15475 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15476 MVT VT = Op.getSimpleValueType();
15478 unsigned NumBits = VT.getSizeInBits();
15481 Op = Op.getOperand(0);
15482 if (VT == MVT::i8) {
15483 // Zero extend to i32 since there is not an i8 bsr.
15485 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15488 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15489 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15490 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15492 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15495 DAG.getConstant(NumBits+NumBits-1, OpVT),
15496 DAG.getConstant(X86::COND_E, MVT::i8),
15499 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15501 // Finally xor with NumBits-1.
15502 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15505 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15509 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15510 MVT VT = Op.getSimpleValueType();
15512 unsigned NumBits = VT.getSizeInBits();
15515 Op = Op.getOperand(0);
15516 if (VT == MVT::i8) {
15517 // Zero extend to i32 since there is not an i8 bsr.
15519 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15522 // Issue a bsr (scan bits in reverse).
15523 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15524 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15526 // And xor with NumBits-1.
15527 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15530 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15534 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15535 MVT VT = Op.getSimpleValueType();
15536 unsigned NumBits = VT.getSizeInBits();
15538 Op = Op.getOperand(0);
15540 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15541 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15542 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15544 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15547 DAG.getConstant(NumBits, VT),
15548 DAG.getConstant(X86::COND_E, MVT::i8),
15551 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15554 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15555 // ones, and then concatenate the result back.
15556 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15557 MVT VT = Op.getSimpleValueType();
15559 assert(VT.is256BitVector() && VT.isInteger() &&
15560 "Unsupported value type for operation");
15562 unsigned NumElems = VT.getVectorNumElements();
15565 // Extract the LHS vectors
15566 SDValue LHS = Op.getOperand(0);
15567 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15568 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15570 // Extract the RHS vectors
15571 SDValue RHS = Op.getOperand(1);
15572 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15573 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15575 MVT EltVT = VT.getVectorElementType();
15576 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15578 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15579 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15580 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15583 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15584 assert(Op.getSimpleValueType().is256BitVector() &&
15585 Op.getSimpleValueType().isInteger() &&
15586 "Only handle AVX 256-bit vector integer operation");
15587 return Lower256IntArith(Op, DAG);
15590 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15591 assert(Op.getSimpleValueType().is256BitVector() &&
15592 Op.getSimpleValueType().isInteger() &&
15593 "Only handle AVX 256-bit vector integer operation");
15594 return Lower256IntArith(Op, DAG);
15597 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15598 SelectionDAG &DAG) {
15600 MVT VT = Op.getSimpleValueType();
15602 // Decompose 256-bit ops into smaller 128-bit ops.
15603 if (VT.is256BitVector() && !Subtarget->hasInt256())
15604 return Lower256IntArith(Op, DAG);
15606 SDValue A = Op.getOperand(0);
15607 SDValue B = Op.getOperand(1);
15609 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15610 if (VT == MVT::v4i32) {
15611 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15612 "Should not custom lower when pmuldq is available!");
15614 // Extract the odd parts.
15615 static const int UnpackMask[] = { 1, -1, 3, -1 };
15616 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15617 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15619 // Multiply the even parts.
15620 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15621 // Now multiply odd parts.
15622 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15624 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15625 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15627 // Merge the two vectors back together with a shuffle. This expands into 2
15629 static const int ShufMask[] = { 0, 4, 2, 6 };
15630 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15633 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15634 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15636 // Ahi = psrlqi(a, 32);
15637 // Bhi = psrlqi(b, 32);
15639 // AloBlo = pmuludq(a, b);
15640 // AloBhi = pmuludq(a, Bhi);
15641 // AhiBlo = pmuludq(Ahi, b);
15643 // AloBhi = psllqi(AloBhi, 32);
15644 // AhiBlo = psllqi(AhiBlo, 32);
15645 // return AloBlo + AloBhi + AhiBlo;
15647 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15648 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15650 // Bit cast to 32-bit vectors for MULUDQ
15651 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15652 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15653 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15654 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15655 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15656 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15658 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15659 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15660 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15662 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15663 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15665 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15666 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15669 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15670 assert(Subtarget->isTargetWin64() && "Unexpected target");
15671 EVT VT = Op.getValueType();
15672 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15673 "Unexpected return type for lowering");
15677 switch (Op->getOpcode()) {
15678 default: llvm_unreachable("Unexpected request for libcall!");
15679 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15680 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15681 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15682 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15683 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15684 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15688 SDValue InChain = DAG.getEntryNode();
15690 TargetLowering::ArgListTy Args;
15691 TargetLowering::ArgListEntry Entry;
15692 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15693 EVT ArgVT = Op->getOperand(i).getValueType();
15694 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15695 "Unexpected argument type for lowering");
15696 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15697 Entry.Node = StackPtr;
15698 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15700 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15701 Entry.Ty = PointerType::get(ArgTy,0);
15702 Entry.isSExt = false;
15703 Entry.isZExt = false;
15704 Args.push_back(Entry);
15707 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15710 TargetLowering::CallLoweringInfo CLI(DAG);
15711 CLI.setDebugLoc(dl).setChain(InChain)
15712 .setCallee(getLibcallCallingConv(LC),
15713 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15714 Callee, std::move(Args), 0)
15715 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15717 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15718 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15721 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15722 SelectionDAG &DAG) {
15723 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15724 EVT VT = Op0.getValueType();
15727 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15728 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15730 // PMULxD operations multiply each even value (starting at 0) of LHS with
15731 // the related value of RHS and produce a widen result.
15732 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15733 // => <2 x i64> <ae|cg>
15735 // In other word, to have all the results, we need to perform two PMULxD:
15736 // 1. one with the even values.
15737 // 2. one with the odd values.
15738 // To achieve #2, with need to place the odd values at an even position.
15740 // Place the odd value at an even position (basically, shift all values 1
15741 // step to the left):
15742 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15743 // <a|b|c|d> => <b|undef|d|undef>
15744 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15745 // <e|f|g|h> => <f|undef|h|undef>
15746 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15748 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15750 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15751 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15753 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15754 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15755 // => <2 x i64> <ae|cg>
15756 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15757 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15758 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15759 // => <2 x i64> <bf|dh>
15760 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15761 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15763 // Shuffle it back into the right order.
15764 SDValue Highs, Lows;
15765 if (VT == MVT::v8i32) {
15766 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15767 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15768 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15769 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15771 const int HighMask[] = {1, 5, 3, 7};
15772 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15773 const int LowMask[] = {0, 4, 2, 6};
15774 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15777 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15778 // unsigned multiply.
15779 if (IsSigned && !Subtarget->hasSSE41()) {
15781 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15782 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15783 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15784 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15785 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15787 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15788 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15791 // The first result of MUL_LOHI is actually the low value, followed by the
15793 SDValue Ops[] = {Lows, Highs};
15794 return DAG.getMergeValues(Ops, dl);
15797 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15798 const X86Subtarget *Subtarget) {
15799 MVT VT = Op.getSimpleValueType();
15801 SDValue R = Op.getOperand(0);
15802 SDValue Amt = Op.getOperand(1);
15804 // Optimize shl/srl/sra with constant shift amount.
15805 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15806 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15807 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15809 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15810 (Subtarget->hasInt256() &&
15811 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15812 (Subtarget->hasAVX512() &&
15813 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15814 if (Op.getOpcode() == ISD::SHL)
15815 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15817 if (Op.getOpcode() == ISD::SRL)
15818 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15820 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15821 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15825 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
15826 unsigned NumElts = VT.getVectorNumElements();
15827 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
15829 if (Op.getOpcode() == ISD::SHL) {
15830 // Make a large shift.
15831 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
15833 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15834 // Zero out the rightmost bits.
15835 SmallVector<SDValue, 32> V(
15836 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), MVT::i8));
15837 return DAG.getNode(ISD::AND, dl, VT, SHL,
15838 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15840 if (Op.getOpcode() == ISD::SRL) {
15841 // Make a large shift.
15842 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
15844 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15845 // Zero out the leftmost bits.
15846 SmallVector<SDValue, 32> V(
15847 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, MVT::i8));
15848 return DAG.getNode(ISD::AND, dl, VT, SRL,
15849 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15851 if (Op.getOpcode() == ISD::SRA) {
15852 if (ShiftAmt == 7) {
15853 // R s>> 7 === R s< 0
15854 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15855 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15858 // R s>> a === ((R u>> a) ^ m) - m
15859 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15860 SmallVector<SDValue, 32> V(NumElts,
15861 DAG.getConstant(128 >> ShiftAmt, MVT::i8));
15862 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15863 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15864 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15867 llvm_unreachable("Unknown shift opcode.");
15872 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15873 if (!Subtarget->is64Bit() &&
15874 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15875 Amt.getOpcode() == ISD::BITCAST &&
15876 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15877 Amt = Amt.getOperand(0);
15878 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15879 VT.getVectorNumElements();
15880 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15881 uint64_t ShiftAmt = 0;
15882 for (unsigned i = 0; i != Ratio; ++i) {
15883 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15887 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15889 // Check remaining shift amounts.
15890 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15891 uint64_t ShAmt = 0;
15892 for (unsigned j = 0; j != Ratio; ++j) {
15893 ConstantSDNode *C =
15894 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15898 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15900 if (ShAmt != ShiftAmt)
15903 switch (Op.getOpcode()) {
15905 llvm_unreachable("Unknown shift opcode!");
15907 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15910 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15913 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15921 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15922 const X86Subtarget* Subtarget) {
15923 MVT VT = Op.getSimpleValueType();
15925 SDValue R = Op.getOperand(0);
15926 SDValue Amt = Op.getOperand(1);
15928 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15929 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15930 (Subtarget->hasInt256() &&
15931 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15932 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15933 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15935 EVT EltVT = VT.getVectorElementType();
15937 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
15938 // Check if this build_vector node is doing a splat.
15939 // If so, then set BaseShAmt equal to the splat value.
15940 BaseShAmt = BV->getSplatValue();
15941 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
15942 BaseShAmt = SDValue();
15944 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15945 Amt = Amt.getOperand(0);
15947 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
15948 if (SVN && SVN->isSplat()) {
15949 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
15950 SDValue InVec = Amt.getOperand(0);
15951 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15952 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
15953 "Unexpected shuffle index found!");
15954 BaseShAmt = InVec.getOperand(SplatIdx);
15955 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15956 if (ConstantSDNode *C =
15957 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15958 if (C->getZExtValue() == SplatIdx)
15959 BaseShAmt = InVec.getOperand(1);
15964 // Avoid introducing an extract element from a shuffle.
15965 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
15966 DAG.getIntPtrConstant(SplatIdx));
15970 if (BaseShAmt.getNode()) {
15971 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
15972 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
15973 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
15974 else if (EltVT.bitsLT(MVT::i32))
15975 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15977 switch (Op.getOpcode()) {
15979 llvm_unreachable("Unknown shift opcode!");
15981 switch (VT.SimpleTy) {
15982 default: return SDValue();
15991 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15994 switch (VT.SimpleTy) {
15995 default: return SDValue();
16002 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16005 switch (VT.SimpleTy) {
16006 default: return SDValue();
16015 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16021 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16022 if (!Subtarget->is64Bit() &&
16023 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16024 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16025 Amt.getOpcode() == ISD::BITCAST &&
16026 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16027 Amt = Amt.getOperand(0);
16028 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16029 VT.getVectorNumElements();
16030 std::vector<SDValue> Vals(Ratio);
16031 for (unsigned i = 0; i != Ratio; ++i)
16032 Vals[i] = Amt.getOperand(i);
16033 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16034 for (unsigned j = 0; j != Ratio; ++j)
16035 if (Vals[j] != Amt.getOperand(i + j))
16038 switch (Op.getOpcode()) {
16040 llvm_unreachable("Unknown shift opcode!");
16042 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16044 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16046 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16053 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16054 SelectionDAG &DAG) {
16055 MVT VT = Op.getSimpleValueType();
16057 SDValue R = Op.getOperand(0);
16058 SDValue Amt = Op.getOperand(1);
16061 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16062 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16064 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16068 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16072 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16074 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16075 if (Subtarget->hasInt256()) {
16076 if (Op.getOpcode() == ISD::SRL &&
16077 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16078 VT == MVT::v4i64 || VT == MVT::v8i32))
16080 if (Op.getOpcode() == ISD::SHL &&
16081 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16082 VT == MVT::v4i64 || VT == MVT::v8i32))
16084 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16088 // If possible, lower this packed shift into a vector multiply instead of
16089 // expanding it into a sequence of scalar shifts.
16090 // Do this only if the vector shift count is a constant build_vector.
16091 if (Op.getOpcode() == ISD::SHL &&
16092 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16093 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16094 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16095 SmallVector<SDValue, 8> Elts;
16096 EVT SVT = VT.getScalarType();
16097 unsigned SVTBits = SVT.getSizeInBits();
16098 const APInt &One = APInt(SVTBits, 1);
16099 unsigned NumElems = VT.getVectorNumElements();
16101 for (unsigned i=0; i !=NumElems; ++i) {
16102 SDValue Op = Amt->getOperand(i);
16103 if (Op->getOpcode() == ISD::UNDEF) {
16104 Elts.push_back(Op);
16108 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16109 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16110 uint64_t ShAmt = C.getZExtValue();
16111 if (ShAmt >= SVTBits) {
16112 Elts.push_back(DAG.getUNDEF(SVT));
16115 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16117 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16118 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16121 // Lower SHL with variable shift amount.
16122 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16123 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16125 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16126 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16127 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16128 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16131 // If possible, lower this shift as a sequence of two shifts by
16132 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16134 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16136 // Could be rewritten as:
16137 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16139 // The advantage is that the two shifts from the example would be
16140 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16141 // the vector shift into four scalar shifts plus four pairs of vector
16143 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16144 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16145 unsigned TargetOpcode = X86ISD::MOVSS;
16146 bool CanBeSimplified;
16147 // The splat value for the first packed shift (the 'X' from the example).
16148 SDValue Amt1 = Amt->getOperand(0);
16149 // The splat value for the second packed shift (the 'Y' from the example).
16150 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16151 Amt->getOperand(2);
16153 // See if it is possible to replace this node with a sequence of
16154 // two shifts followed by a MOVSS/MOVSD
16155 if (VT == MVT::v4i32) {
16156 // Check if it is legal to use a MOVSS.
16157 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16158 Amt2 == Amt->getOperand(3);
16159 if (!CanBeSimplified) {
16160 // Otherwise, check if we can still simplify this node using a MOVSD.
16161 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16162 Amt->getOperand(2) == Amt->getOperand(3);
16163 TargetOpcode = X86ISD::MOVSD;
16164 Amt2 = Amt->getOperand(2);
16167 // Do similar checks for the case where the machine value type
16169 CanBeSimplified = Amt1 == Amt->getOperand(1);
16170 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16171 CanBeSimplified = Amt2 == Amt->getOperand(i);
16173 if (!CanBeSimplified) {
16174 TargetOpcode = X86ISD::MOVSD;
16175 CanBeSimplified = true;
16176 Amt2 = Amt->getOperand(4);
16177 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16178 CanBeSimplified = Amt1 == Amt->getOperand(i);
16179 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16180 CanBeSimplified = Amt2 == Amt->getOperand(j);
16184 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16185 isa<ConstantSDNode>(Amt2)) {
16186 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16187 EVT CastVT = MVT::v4i32;
16189 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16190 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16192 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16193 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16194 if (TargetOpcode == X86ISD::MOVSD)
16195 CastVT = MVT::v2i64;
16196 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16197 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16198 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16200 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16204 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16205 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16208 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16209 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16211 // Turn 'a' into a mask suitable for VSELECT
16212 SDValue VSelM = DAG.getConstant(0x80, VT);
16213 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16214 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16216 SDValue CM1 = DAG.getConstant(0x0f, VT);
16217 SDValue CM2 = DAG.getConstant(0x3f, VT);
16219 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16220 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16221 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16222 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16223 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16226 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16227 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16228 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16230 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16231 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16232 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16233 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16234 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16237 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16238 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16239 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16241 // return VSELECT(r, r+r, a);
16242 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16243 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16247 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16248 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16249 // solution better.
16250 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16251 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16253 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16254 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16255 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16256 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16257 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16260 // Decompose 256-bit shifts into smaller 128-bit shifts.
16261 if (VT.is256BitVector()) {
16262 unsigned NumElems = VT.getVectorNumElements();
16263 MVT EltVT = VT.getVectorElementType();
16264 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16266 // Extract the two vectors
16267 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16268 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16270 // Recreate the shift amount vectors
16271 SDValue Amt1, Amt2;
16272 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16273 // Constant shift amount
16274 SmallVector<SDValue, 4> Amt1Csts;
16275 SmallVector<SDValue, 4> Amt2Csts;
16276 for (unsigned i = 0; i != NumElems/2; ++i)
16277 Amt1Csts.push_back(Amt->getOperand(i));
16278 for (unsigned i = NumElems/2; i != NumElems; ++i)
16279 Amt2Csts.push_back(Amt->getOperand(i));
16281 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16282 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16284 // Variable shift amount
16285 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16286 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16289 // Issue new vector shifts for the smaller types
16290 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16291 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16293 // Concatenate the result back
16294 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16300 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16301 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16302 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16303 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16304 // has only one use.
16305 SDNode *N = Op.getNode();
16306 SDValue LHS = N->getOperand(0);
16307 SDValue RHS = N->getOperand(1);
16308 unsigned BaseOp = 0;
16311 switch (Op.getOpcode()) {
16312 default: llvm_unreachable("Unknown ovf instruction!");
16314 // A subtract of one will be selected as a INC. Note that INC doesn't
16315 // set CF, so we can't do this for UADDO.
16316 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16318 BaseOp = X86ISD::INC;
16319 Cond = X86::COND_O;
16322 BaseOp = X86ISD::ADD;
16323 Cond = X86::COND_O;
16326 BaseOp = X86ISD::ADD;
16327 Cond = X86::COND_B;
16330 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16331 // set CF, so we can't do this for USUBO.
16332 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16334 BaseOp = X86ISD::DEC;
16335 Cond = X86::COND_O;
16338 BaseOp = X86ISD::SUB;
16339 Cond = X86::COND_O;
16342 BaseOp = X86ISD::SUB;
16343 Cond = X86::COND_B;
16346 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16347 Cond = X86::COND_O;
16349 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16350 if (N->getValueType(0) == MVT::i8) {
16351 BaseOp = X86ISD::UMUL8;
16352 Cond = X86::COND_O;
16355 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16357 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16360 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16361 DAG.getConstant(X86::COND_O, MVT::i32),
16362 SDValue(Sum.getNode(), 2));
16364 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16368 // Also sets EFLAGS.
16369 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16370 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16373 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16374 DAG.getConstant(Cond, MVT::i32),
16375 SDValue(Sum.getNode(), 1));
16377 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16380 /// Returns true if the operand type is exactly twice the native width, and
16381 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16382 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16383 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16384 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16385 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16388 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16389 else if (OpWidth == 128)
16390 return Subtarget->hasCmpxchg16b();
16395 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16396 return needsCmpXchgNb(SI->getValueOperand()->getType());
16399 // Note: this turns large loads into lock cmpxchg8b/16b.
16400 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16401 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16402 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16403 return needsCmpXchgNb(PTy->getElementType());
16406 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16407 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16408 const Type *MemType = AI->getType();
16410 // If the operand is too big, we must see if cmpxchg8/16b is available
16411 // and default to library calls otherwise.
16412 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16413 return needsCmpXchgNb(MemType);
16415 AtomicRMWInst::BinOp Op = AI->getOperation();
16418 llvm_unreachable("Unknown atomic operation");
16419 case AtomicRMWInst::Xchg:
16420 case AtomicRMWInst::Add:
16421 case AtomicRMWInst::Sub:
16422 // It's better to use xadd, xsub or xchg for these in all cases.
16424 case AtomicRMWInst::Or:
16425 case AtomicRMWInst::And:
16426 case AtomicRMWInst::Xor:
16427 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16428 // prefix to a normal instruction for these operations.
16429 return !AI->use_empty();
16430 case AtomicRMWInst::Nand:
16431 case AtomicRMWInst::Max:
16432 case AtomicRMWInst::Min:
16433 case AtomicRMWInst::UMax:
16434 case AtomicRMWInst::UMin:
16435 // These always require a non-trivial set of data operations on x86. We must
16436 // use a cmpxchg loop.
16441 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16442 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16443 // no-sse2). There isn't any reason to disable it if the target processor
16445 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16449 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16450 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16451 const Type *MemType = AI->getType();
16452 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16453 // there is no benefit in turning such RMWs into loads, and it is actually
16454 // harmful as it introduces a mfence.
16455 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16458 auto Builder = IRBuilder<>(AI);
16459 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16460 auto SynchScope = AI->getSynchScope();
16461 // We must restrict the ordering to avoid generating loads with Release or
16462 // ReleaseAcquire orderings.
16463 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16464 auto Ptr = AI->getPointerOperand();
16466 // Before the load we need a fence. Here is an example lifted from
16467 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16470 // x.store(1, relaxed);
16471 // r1 = y.fetch_add(0, release);
16473 // y.fetch_add(42, acquire);
16474 // r2 = x.load(relaxed);
16475 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16476 // lowered to just a load without a fence. A mfence flushes the store buffer,
16477 // making the optimization clearly correct.
16478 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16479 // otherwise, we might be able to be more agressive on relaxed idempotent
16480 // rmw. In practice, they do not look useful, so we don't try to be
16481 // especially clever.
16482 if (SynchScope == SingleThread) {
16483 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16484 // the IR level, so we must wrap it in an intrinsic.
16486 } else if (hasMFENCE(*Subtarget)) {
16487 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16488 Intrinsic::x86_sse2_mfence);
16489 Builder.CreateCall(MFence);
16491 // FIXME: it might make sense to use a locked operation here but on a
16492 // different cache-line to prevent cache-line bouncing. In practice it
16493 // is probably a small win, and x86 processors without mfence are rare
16494 // enough that we do not bother.
16498 // Finally we can emit the atomic load.
16499 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16500 AI->getType()->getPrimitiveSizeInBits());
16501 Loaded->setAtomic(Order, SynchScope);
16502 AI->replaceAllUsesWith(Loaded);
16503 AI->eraseFromParent();
16507 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16508 SelectionDAG &DAG) {
16510 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16511 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16512 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16513 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16515 // The only fence that needs an instruction is a sequentially-consistent
16516 // cross-thread fence.
16517 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16518 if (hasMFENCE(*Subtarget))
16519 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16521 SDValue Chain = Op.getOperand(0);
16522 SDValue Zero = DAG.getConstant(0, MVT::i32);
16524 DAG.getRegister(X86::ESP, MVT::i32), // Base
16525 DAG.getTargetConstant(1, MVT::i8), // Scale
16526 DAG.getRegister(0, MVT::i32), // Index
16527 DAG.getTargetConstant(0, MVT::i32), // Disp
16528 DAG.getRegister(0, MVT::i32), // Segment.
16532 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16533 return SDValue(Res, 0);
16536 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16537 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16540 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16541 SelectionDAG &DAG) {
16542 MVT T = Op.getSimpleValueType();
16546 switch(T.SimpleTy) {
16547 default: llvm_unreachable("Invalid value type!");
16548 case MVT::i8: Reg = X86::AL; size = 1; break;
16549 case MVT::i16: Reg = X86::AX; size = 2; break;
16550 case MVT::i32: Reg = X86::EAX; size = 4; break;
16552 assert(Subtarget->is64Bit() && "Node not type legal!");
16553 Reg = X86::RAX; size = 8;
16556 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16557 Op.getOperand(2), SDValue());
16558 SDValue Ops[] = { cpIn.getValue(0),
16561 DAG.getTargetConstant(size, MVT::i8),
16562 cpIn.getValue(1) };
16563 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16564 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16565 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16569 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16570 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16571 MVT::i32, cpOut.getValue(2));
16572 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16573 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16575 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16576 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16577 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16581 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16582 SelectionDAG &DAG) {
16583 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16584 MVT DstVT = Op.getSimpleValueType();
16586 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16587 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16588 if (DstVT != MVT::f64)
16589 // This conversion needs to be expanded.
16592 SDValue InVec = Op->getOperand(0);
16594 unsigned NumElts = SrcVT.getVectorNumElements();
16595 EVT SVT = SrcVT.getVectorElementType();
16597 // Widen the vector in input in the case of MVT::v2i32.
16598 // Example: from MVT::v2i32 to MVT::v4i32.
16599 SmallVector<SDValue, 16> Elts;
16600 for (unsigned i = 0, e = NumElts; i != e; ++i)
16601 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16602 DAG.getIntPtrConstant(i)));
16604 // Explicitly mark the extra elements as Undef.
16605 Elts.append(NumElts, DAG.getUNDEF(SVT));
16607 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16608 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16609 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16610 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16611 DAG.getIntPtrConstant(0));
16614 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16615 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16616 assert((DstVT == MVT::i64 ||
16617 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16618 "Unexpected custom BITCAST");
16619 // i64 <=> MMX conversions are Legal.
16620 if (SrcVT==MVT::i64 && DstVT.isVector())
16622 if (DstVT==MVT::i64 && SrcVT.isVector())
16624 // MMX <=> MMX conversions are Legal.
16625 if (SrcVT.isVector() && DstVT.isVector())
16627 // All other conversions need to be expanded.
16631 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
16632 SelectionDAG &DAG) {
16633 SDNode *Node = Op.getNode();
16636 Op = Op.getOperand(0);
16637 EVT VT = Op.getValueType();
16638 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16639 "CTPOP lowering only implemented for 128/256-bit wide vector types");
16641 unsigned NumElts = VT.getVectorNumElements();
16642 EVT EltVT = VT.getVectorElementType();
16643 unsigned Len = EltVT.getSizeInBits();
16645 // This is the vectorized version of the "best" algorithm from
16646 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
16647 // with a minor tweak to use a series of adds + shifts instead of vector
16648 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
16650 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
16651 // v8i32 => Always profitable
16653 // FIXME: There a couple of possible improvements:
16655 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
16656 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
16658 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
16659 "CTPOP not implemented for this vector element type.");
16661 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
16662 // extra legalization.
16663 bool NeedsBitcast = EltVT == MVT::i32;
16664 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
16666 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
16667 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
16668 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
16670 // v = v - ((v >> 1) & 0x55555555...)
16671 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
16672 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
16673 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
16675 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16677 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
16678 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
16680 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
16682 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
16683 if (VT != And.getValueType())
16684 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16685 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
16687 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
16688 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
16689 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
16690 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
16691 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
16693 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
16694 if (NeedsBitcast) {
16695 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16696 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
16697 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
16700 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
16701 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
16702 if (VT != AndRHS.getValueType()) {
16703 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
16704 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
16706 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
16708 // v = (v + (v >> 4)) & 0x0F0F0F0F...
16709 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
16710 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
16711 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
16712 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
16714 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
16715 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
16716 if (NeedsBitcast) {
16717 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
16718 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
16720 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
16721 if (VT != And.getValueType())
16722 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16724 // The algorithm mentioned above uses:
16725 // v = (v * 0x01010101...) >> (Len - 8)
16727 // Change it to use vector adds + vector shifts which yield faster results on
16728 // Haswell than using vector integer multiplication.
16730 // For i32 elements:
16731 // v = v + (v >> 8)
16732 // v = v + (v >> 16)
16734 // For i64 elements:
16735 // v = v + (v >> 8)
16736 // v = v + (v >> 16)
16737 // v = v + (v >> 32)
16740 SmallVector<SDValue, 8> Csts;
16741 for (unsigned i = 8; i <= Len/2; i *= 2) {
16742 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
16743 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
16744 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
16745 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
16749 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
16750 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
16751 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
16752 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
16753 if (NeedsBitcast) {
16754 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
16755 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
16757 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
16758 if (VT != And.getValueType())
16759 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16764 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16765 SDNode *Node = Op.getNode();
16767 EVT T = Node->getValueType(0);
16768 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16769 DAG.getConstant(0, T), Node->getOperand(2));
16770 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16771 cast<AtomicSDNode>(Node)->getMemoryVT(),
16772 Node->getOperand(0),
16773 Node->getOperand(1), negOp,
16774 cast<AtomicSDNode>(Node)->getMemOperand(),
16775 cast<AtomicSDNode>(Node)->getOrdering(),
16776 cast<AtomicSDNode>(Node)->getSynchScope());
16779 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16780 SDNode *Node = Op.getNode();
16782 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16784 // Convert seq_cst store -> xchg
16785 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16786 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16787 // (The only way to get a 16-byte store is cmpxchg16b)
16788 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16789 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16790 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16791 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16792 cast<AtomicSDNode>(Node)->getMemoryVT(),
16793 Node->getOperand(0),
16794 Node->getOperand(1), Node->getOperand(2),
16795 cast<AtomicSDNode>(Node)->getMemOperand(),
16796 cast<AtomicSDNode>(Node)->getOrdering(),
16797 cast<AtomicSDNode>(Node)->getSynchScope());
16798 return Swap.getValue(1);
16800 // Other atomic stores have a simple pattern.
16804 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16805 EVT VT = Op.getNode()->getSimpleValueType(0);
16807 // Let legalize expand this if it isn't a legal type yet.
16808 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16811 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16814 bool ExtraOp = false;
16815 switch (Op.getOpcode()) {
16816 default: llvm_unreachable("Invalid code");
16817 case ISD::ADDC: Opc = X86ISD::ADD; break;
16818 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16819 case ISD::SUBC: Opc = X86ISD::SUB; break;
16820 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16824 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16826 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16827 Op.getOperand(1), Op.getOperand(2));
16830 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16831 SelectionDAG &DAG) {
16832 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16834 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16835 // which returns the values as { float, float } (in XMM0) or
16836 // { double, double } (which is returned in XMM0, XMM1).
16838 SDValue Arg = Op.getOperand(0);
16839 EVT ArgVT = Arg.getValueType();
16840 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16842 TargetLowering::ArgListTy Args;
16843 TargetLowering::ArgListEntry Entry;
16847 Entry.isSExt = false;
16848 Entry.isZExt = false;
16849 Args.push_back(Entry);
16851 bool isF64 = ArgVT == MVT::f64;
16852 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16853 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16854 // the results are returned via SRet in memory.
16855 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16857 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16859 Type *RetTy = isF64
16860 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
16861 : (Type*)VectorType::get(ArgTy, 4);
16863 TargetLowering::CallLoweringInfo CLI(DAG);
16864 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16865 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16867 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16870 // Returned in xmm0 and xmm1.
16871 return CallResult.first;
16873 // Returned in bits 0:31 and 32:64 xmm0.
16874 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16875 CallResult.first, DAG.getIntPtrConstant(0));
16876 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16877 CallResult.first, DAG.getIntPtrConstant(1));
16878 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16879 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16882 /// LowerOperation - Provide custom lowering hooks for some operations.
16884 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16885 switch (Op.getOpcode()) {
16886 default: llvm_unreachable("Should not custom lower this!");
16887 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16888 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16889 return LowerCMP_SWAP(Op, Subtarget, DAG);
16890 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
16891 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16892 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16893 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16894 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16895 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
16896 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16897 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16898 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16899 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16900 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16901 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16902 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16903 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16904 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16905 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16906 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16907 case ISD::SHL_PARTS:
16908 case ISD::SRA_PARTS:
16909 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16910 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16911 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16912 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16913 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16914 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16915 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16916 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16917 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16918 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16919 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
16921 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
16922 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16923 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16924 case ISD::SETCC: return LowerSETCC(Op, DAG);
16925 case ISD::SELECT: return LowerSELECT(Op, DAG);
16926 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16927 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16928 case ISD::VASTART: return LowerVASTART(Op, DAG);
16929 case ISD::VAARG: return LowerVAARG(Op, DAG);
16930 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16931 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
16932 case ISD::INTRINSIC_VOID:
16933 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16934 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16935 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16936 case ISD::FRAME_TO_ARGS_OFFSET:
16937 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16938 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16939 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16940 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16941 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16942 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16943 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16944 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16945 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16946 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16947 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16948 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16949 case ISD::UMUL_LOHI:
16950 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16953 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16959 case ISD::UMULO: return LowerXALUO(Op, DAG);
16960 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16961 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16965 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16966 case ISD::ADD: return LowerADD(Op, DAG);
16967 case ISD::SUB: return LowerSUB(Op, DAG);
16968 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16972 /// ReplaceNodeResults - Replace a node with an illegal result type
16973 /// with a new node built out of custom code.
16974 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16975 SmallVectorImpl<SDValue>&Results,
16976 SelectionDAG &DAG) const {
16978 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16979 switch (N->getOpcode()) {
16981 llvm_unreachable("Do not know how to custom type legalize this operation!");
16982 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
16983 case X86ISD::FMINC:
16985 case X86ISD::FMAXC:
16986 case X86ISD::FMAX: {
16987 EVT VT = N->getValueType(0);
16988 if (VT != MVT::v2f32)
16989 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
16990 SDValue UNDEF = DAG.getUNDEF(VT);
16991 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
16992 N->getOperand(0), UNDEF);
16993 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
16994 N->getOperand(1), UNDEF);
16995 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
16998 case ISD::SIGN_EXTEND_INREG:
17003 // We don't want to expand or promote these.
17010 case ISD::UDIVREM: {
17011 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17012 Results.push_back(V);
17015 case ISD::FP_TO_SINT:
17016 case ISD::FP_TO_UINT: {
17017 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17019 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17022 std::pair<SDValue,SDValue> Vals =
17023 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17024 SDValue FIST = Vals.first, StackSlot = Vals.second;
17025 if (FIST.getNode()) {
17026 EVT VT = N->getValueType(0);
17027 // Return a load from the stack slot.
17028 if (StackSlot.getNode())
17029 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17030 MachinePointerInfo(),
17031 false, false, false, 0));
17033 Results.push_back(FIST);
17037 case ISD::UINT_TO_FP: {
17038 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17039 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17040 N->getValueType(0) != MVT::v2f32)
17042 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17044 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17046 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17047 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17048 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17049 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17050 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17051 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17054 case ISD::FP_ROUND: {
17055 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17057 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17058 Results.push_back(V);
17061 case ISD::INTRINSIC_W_CHAIN: {
17062 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17064 default : llvm_unreachable("Do not know how to custom type "
17065 "legalize this intrinsic operation!");
17066 case Intrinsic::x86_rdtsc:
17067 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17069 case Intrinsic::x86_rdtscp:
17070 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17072 case Intrinsic::x86_rdpmc:
17073 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17076 case ISD::READCYCLECOUNTER: {
17077 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17080 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17081 EVT T = N->getValueType(0);
17082 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17083 bool Regs64bit = T == MVT::i128;
17084 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17085 SDValue cpInL, cpInH;
17086 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17087 DAG.getConstant(0, HalfT));
17088 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17089 DAG.getConstant(1, HalfT));
17090 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17091 Regs64bit ? X86::RAX : X86::EAX,
17093 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17094 Regs64bit ? X86::RDX : X86::EDX,
17095 cpInH, cpInL.getValue(1));
17096 SDValue swapInL, swapInH;
17097 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17098 DAG.getConstant(0, HalfT));
17099 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17100 DAG.getConstant(1, HalfT));
17101 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17102 Regs64bit ? X86::RBX : X86::EBX,
17103 swapInL, cpInH.getValue(1));
17104 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17105 Regs64bit ? X86::RCX : X86::ECX,
17106 swapInH, swapInL.getValue(1));
17107 SDValue Ops[] = { swapInH.getValue(0),
17109 swapInH.getValue(1) };
17110 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17111 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17112 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17113 X86ISD::LCMPXCHG8_DAG;
17114 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17115 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17116 Regs64bit ? X86::RAX : X86::EAX,
17117 HalfT, Result.getValue(1));
17118 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17119 Regs64bit ? X86::RDX : X86::EDX,
17120 HalfT, cpOutL.getValue(2));
17121 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17123 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17124 MVT::i32, cpOutH.getValue(2));
17126 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17127 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17128 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17130 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17131 Results.push_back(Success);
17132 Results.push_back(EFLAGS.getValue(1));
17135 case ISD::ATOMIC_SWAP:
17136 case ISD::ATOMIC_LOAD_ADD:
17137 case ISD::ATOMIC_LOAD_SUB:
17138 case ISD::ATOMIC_LOAD_AND:
17139 case ISD::ATOMIC_LOAD_OR:
17140 case ISD::ATOMIC_LOAD_XOR:
17141 case ISD::ATOMIC_LOAD_NAND:
17142 case ISD::ATOMIC_LOAD_MIN:
17143 case ISD::ATOMIC_LOAD_MAX:
17144 case ISD::ATOMIC_LOAD_UMIN:
17145 case ISD::ATOMIC_LOAD_UMAX:
17146 case ISD::ATOMIC_LOAD: {
17147 // Delegate to generic TypeLegalization. Situations we can really handle
17148 // should have already been dealt with by AtomicExpandPass.cpp.
17151 case ISD::BITCAST: {
17152 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17153 EVT DstVT = N->getValueType(0);
17154 EVT SrcVT = N->getOperand(0)->getValueType(0);
17156 if (SrcVT != MVT::f64 ||
17157 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17160 unsigned NumElts = DstVT.getVectorNumElements();
17161 EVT SVT = DstVT.getVectorElementType();
17162 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17163 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17164 MVT::v2f64, N->getOperand(0));
17165 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17167 if (ExperimentalVectorWideningLegalization) {
17168 // If we are legalizing vectors by widening, we already have the desired
17169 // legal vector type, just return it.
17170 Results.push_back(ToVecInt);
17174 SmallVector<SDValue, 8> Elts;
17175 for (unsigned i = 0, e = NumElts; i != e; ++i)
17176 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17177 ToVecInt, DAG.getIntPtrConstant(i)));
17179 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17184 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17186 default: return nullptr;
17187 case X86ISD::BSF: return "X86ISD::BSF";
17188 case X86ISD::BSR: return "X86ISD::BSR";
17189 case X86ISD::SHLD: return "X86ISD::SHLD";
17190 case X86ISD::SHRD: return "X86ISD::SHRD";
17191 case X86ISD::FAND: return "X86ISD::FAND";
17192 case X86ISD::FANDN: return "X86ISD::FANDN";
17193 case X86ISD::FOR: return "X86ISD::FOR";
17194 case X86ISD::FXOR: return "X86ISD::FXOR";
17195 case X86ISD::FSRL: return "X86ISD::FSRL";
17196 case X86ISD::FILD: return "X86ISD::FILD";
17197 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17198 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17199 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17200 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17201 case X86ISD::FLD: return "X86ISD::FLD";
17202 case X86ISD::FST: return "X86ISD::FST";
17203 case X86ISD::CALL: return "X86ISD::CALL";
17204 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17205 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17206 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17207 case X86ISD::BT: return "X86ISD::BT";
17208 case X86ISD::CMP: return "X86ISD::CMP";
17209 case X86ISD::COMI: return "X86ISD::COMI";
17210 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17211 case X86ISD::CMPM: return "X86ISD::CMPM";
17212 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17213 case X86ISD::SETCC: return "X86ISD::SETCC";
17214 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17215 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17216 case X86ISD::CMOV: return "X86ISD::CMOV";
17217 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17218 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17219 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17220 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17221 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17222 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17223 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17224 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17225 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17226 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17227 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17228 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17229 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17230 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17231 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17232 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17233 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17234 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17235 case X86ISD::HADD: return "X86ISD::HADD";
17236 case X86ISD::HSUB: return "X86ISD::HSUB";
17237 case X86ISD::FHADD: return "X86ISD::FHADD";
17238 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17239 case X86ISD::UMAX: return "X86ISD::UMAX";
17240 case X86ISD::UMIN: return "X86ISD::UMIN";
17241 case X86ISD::SMAX: return "X86ISD::SMAX";
17242 case X86ISD::SMIN: return "X86ISD::SMIN";
17243 case X86ISD::FMAX: return "X86ISD::FMAX";
17244 case X86ISD::FMIN: return "X86ISD::FMIN";
17245 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17246 case X86ISD::FMINC: return "X86ISD::FMINC";
17247 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17248 case X86ISD::FRCP: return "X86ISD::FRCP";
17249 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17250 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17251 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17252 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17253 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17254 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17255 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17256 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17257 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17258 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17259 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17260 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17261 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17262 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17263 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17264 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17265 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17266 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17267 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17268 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17269 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17270 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17271 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17272 case X86ISD::VSHL: return "X86ISD::VSHL";
17273 case X86ISD::VSRL: return "X86ISD::VSRL";
17274 case X86ISD::VSRA: return "X86ISD::VSRA";
17275 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17276 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17277 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17278 case X86ISD::CMPP: return "X86ISD::CMPP";
17279 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17280 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17281 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17282 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17283 case X86ISD::ADD: return "X86ISD::ADD";
17284 case X86ISD::SUB: return "X86ISD::SUB";
17285 case X86ISD::ADC: return "X86ISD::ADC";
17286 case X86ISD::SBB: return "X86ISD::SBB";
17287 case X86ISD::SMUL: return "X86ISD::SMUL";
17288 case X86ISD::UMUL: return "X86ISD::UMUL";
17289 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17290 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17291 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17292 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17293 case X86ISD::INC: return "X86ISD::INC";
17294 case X86ISD::DEC: return "X86ISD::DEC";
17295 case X86ISD::OR: return "X86ISD::OR";
17296 case X86ISD::XOR: return "X86ISD::XOR";
17297 case X86ISD::AND: return "X86ISD::AND";
17298 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17299 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17300 case X86ISD::PTEST: return "X86ISD::PTEST";
17301 case X86ISD::TESTP: return "X86ISD::TESTP";
17302 case X86ISD::TESTM: return "X86ISD::TESTM";
17303 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17304 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17305 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17306 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17307 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17308 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17309 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17310 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17311 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17312 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17313 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17314 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17315 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17316 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17317 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17318 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17319 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17320 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17321 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17322 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17323 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17324 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17325 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17326 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17327 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17328 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17329 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17330 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17331 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17332 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17333 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17334 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17335 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17336 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17337 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17338 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17339 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17340 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17341 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17342 case X86ISD::SAHF: return "X86ISD::SAHF";
17343 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17344 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17345 case X86ISD::FMADD: return "X86ISD::FMADD";
17346 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17347 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17348 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17349 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17350 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17351 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17352 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17353 case X86ISD::XTEST: return "X86ISD::XTEST";
17354 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17355 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17356 case X86ISD::SELECT: return "X86ISD::SELECT";
17357 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17358 case X86ISD::RCP28: return "X86ISD::RCP28";
17359 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17360 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17361 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17362 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17363 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17367 // isLegalAddressingMode - Return true if the addressing mode represented
17368 // by AM is legal for this target, for a load/store of the specified type.
17369 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17371 // X86 supports extremely general addressing modes.
17372 CodeModel::Model M = getTargetMachine().getCodeModel();
17373 Reloc::Model R = getTargetMachine().getRelocationModel();
17375 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17376 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17381 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17383 // If a reference to this global requires an extra load, we can't fold it.
17384 if (isGlobalStubReference(GVFlags))
17387 // If BaseGV requires a register for the PIC base, we cannot also have a
17388 // BaseReg specified.
17389 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17392 // If lower 4G is not available, then we must use rip-relative addressing.
17393 if ((M != CodeModel::Small || R != Reloc::Static) &&
17394 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17398 switch (AM.Scale) {
17404 // These scales always work.
17409 // These scales are formed with basereg+scalereg. Only accept if there is
17414 default: // Other stuff never works.
17421 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17422 unsigned Bits = Ty->getScalarSizeInBits();
17424 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17425 // particularly cheaper than those without.
17429 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17430 // variable shifts just as cheap as scalar ones.
17431 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17434 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17435 // fully general vector.
17439 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17440 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17442 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17443 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17444 return NumBits1 > NumBits2;
17447 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17448 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17451 if (!isTypeLegal(EVT::getEVT(Ty1)))
17454 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17456 // Assuming the caller doesn't have a zeroext or signext return parameter,
17457 // truncation all the way down to i1 is valid.
17461 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17462 return isInt<32>(Imm);
17465 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17466 // Can also use sub to handle negated immediates.
17467 return isInt<32>(Imm);
17470 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17471 if (!VT1.isInteger() || !VT2.isInteger())
17473 unsigned NumBits1 = VT1.getSizeInBits();
17474 unsigned NumBits2 = VT2.getSizeInBits();
17475 return NumBits1 > NumBits2;
17478 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17479 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17480 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17483 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17484 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17485 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17488 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17489 EVT VT1 = Val.getValueType();
17490 if (isZExtFree(VT1, VT2))
17493 if (Val.getOpcode() != ISD::LOAD)
17496 if (!VT1.isSimple() || !VT1.isInteger() ||
17497 !VT2.isSimple() || !VT2.isInteger())
17500 switch (VT1.getSimpleVT().SimpleTy) {
17505 // X86 has 8, 16, and 32-bit zero-extending loads.
17512 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
17515 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17516 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17519 VT = VT.getScalarType();
17521 if (!VT.isSimple())
17524 switch (VT.getSimpleVT().SimpleTy) {
17535 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17536 // i16 instructions are longer (0x66 prefix) and potentially slower.
17537 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17540 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17541 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17542 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17543 /// are assumed to be legal.
17545 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17547 if (!VT.isSimple())
17550 // Very little shuffling can be done for 64-bit vectors right now.
17551 if (VT.getSizeInBits() == 64)
17554 // We only care that the types being shuffled are legal. The lowering can
17555 // handle any possible shuffle mask that results.
17556 return isTypeLegal(VT.getSimpleVT());
17560 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17562 // Just delegate to the generic legality, clear masks aren't special.
17563 return isShuffleMaskLegal(Mask, VT);
17566 //===----------------------------------------------------------------------===//
17567 // X86 Scheduler Hooks
17568 //===----------------------------------------------------------------------===//
17570 /// Utility function to emit xbegin specifying the start of an RTM region.
17571 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17572 const TargetInstrInfo *TII) {
17573 DebugLoc DL = MI->getDebugLoc();
17575 const BasicBlock *BB = MBB->getBasicBlock();
17576 MachineFunction::iterator I = MBB;
17579 // For the v = xbegin(), we generate
17590 MachineBasicBlock *thisMBB = MBB;
17591 MachineFunction *MF = MBB->getParent();
17592 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17593 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17594 MF->insert(I, mainMBB);
17595 MF->insert(I, sinkMBB);
17597 // Transfer the remainder of BB and its successor edges to sinkMBB.
17598 sinkMBB->splice(sinkMBB->begin(), MBB,
17599 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17600 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17604 // # fallthrough to mainMBB
17605 // # abortion to sinkMBB
17606 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17607 thisMBB->addSuccessor(mainMBB);
17608 thisMBB->addSuccessor(sinkMBB);
17612 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17613 mainMBB->addSuccessor(sinkMBB);
17616 // EAX is live into the sinkMBB
17617 sinkMBB->addLiveIn(X86::EAX);
17618 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17619 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17622 MI->eraseFromParent();
17626 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17627 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17628 // in the .td file.
17629 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17630 const TargetInstrInfo *TII) {
17632 switch (MI->getOpcode()) {
17633 default: llvm_unreachable("illegal opcode!");
17634 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17635 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17636 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17637 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17638 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17639 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17640 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17641 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17644 DebugLoc dl = MI->getDebugLoc();
17645 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17647 unsigned NumArgs = MI->getNumOperands();
17648 for (unsigned i = 1; i < NumArgs; ++i) {
17649 MachineOperand &Op = MI->getOperand(i);
17650 if (!(Op.isReg() && Op.isImplicit()))
17651 MIB.addOperand(Op);
17653 if (MI->hasOneMemOperand())
17654 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17656 BuildMI(*BB, MI, dl,
17657 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17658 .addReg(X86::XMM0);
17660 MI->eraseFromParent();
17664 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17665 // defs in an instruction pattern
17666 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17667 const TargetInstrInfo *TII) {
17669 switch (MI->getOpcode()) {
17670 default: llvm_unreachable("illegal opcode!");
17671 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17672 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17673 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17674 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17675 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17676 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17677 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17678 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17681 DebugLoc dl = MI->getDebugLoc();
17682 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17684 unsigned NumArgs = MI->getNumOperands(); // remove the results
17685 for (unsigned i = 1; i < NumArgs; ++i) {
17686 MachineOperand &Op = MI->getOperand(i);
17687 if (!(Op.isReg() && Op.isImplicit()))
17688 MIB.addOperand(Op);
17690 if (MI->hasOneMemOperand())
17691 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17693 BuildMI(*BB, MI, dl,
17694 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17697 MI->eraseFromParent();
17701 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17702 const X86Subtarget *Subtarget) {
17703 DebugLoc dl = MI->getDebugLoc();
17704 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17705 // Address into RAX/EAX, other two args into ECX, EDX.
17706 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17707 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17708 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17709 for (int i = 0; i < X86::AddrNumOperands; ++i)
17710 MIB.addOperand(MI->getOperand(i));
17712 unsigned ValOps = X86::AddrNumOperands;
17713 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17714 .addReg(MI->getOperand(ValOps).getReg());
17715 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17716 .addReg(MI->getOperand(ValOps+1).getReg());
17718 // The instruction doesn't actually take any operands though.
17719 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17721 MI->eraseFromParent(); // The pseudo is gone now.
17725 MachineBasicBlock *
17726 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
17727 MachineBasicBlock *MBB) const {
17728 // Emit va_arg instruction on X86-64.
17730 // Operands to this pseudo-instruction:
17731 // 0 ) Output : destination address (reg)
17732 // 1-5) Input : va_list address (addr, i64mem)
17733 // 6 ) ArgSize : Size (in bytes) of vararg type
17734 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17735 // 8 ) Align : Alignment of type
17736 // 9 ) EFLAGS (implicit-def)
17738 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17739 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17741 unsigned DestReg = MI->getOperand(0).getReg();
17742 MachineOperand &Base = MI->getOperand(1);
17743 MachineOperand &Scale = MI->getOperand(2);
17744 MachineOperand &Index = MI->getOperand(3);
17745 MachineOperand &Disp = MI->getOperand(4);
17746 MachineOperand &Segment = MI->getOperand(5);
17747 unsigned ArgSize = MI->getOperand(6).getImm();
17748 unsigned ArgMode = MI->getOperand(7).getImm();
17749 unsigned Align = MI->getOperand(8).getImm();
17751 // Memory Reference
17752 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17753 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17754 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17756 // Machine Information
17757 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17758 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17759 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17760 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17761 DebugLoc DL = MI->getDebugLoc();
17763 // struct va_list {
17766 // i64 overflow_area (address)
17767 // i64 reg_save_area (address)
17769 // sizeof(va_list) = 24
17770 // alignment(va_list) = 8
17772 unsigned TotalNumIntRegs = 6;
17773 unsigned TotalNumXMMRegs = 8;
17774 bool UseGPOffset = (ArgMode == 1);
17775 bool UseFPOffset = (ArgMode == 2);
17776 unsigned MaxOffset = TotalNumIntRegs * 8 +
17777 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17779 /* Align ArgSize to a multiple of 8 */
17780 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17781 bool NeedsAlign = (Align > 8);
17783 MachineBasicBlock *thisMBB = MBB;
17784 MachineBasicBlock *overflowMBB;
17785 MachineBasicBlock *offsetMBB;
17786 MachineBasicBlock *endMBB;
17788 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17789 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17790 unsigned OffsetReg = 0;
17792 if (!UseGPOffset && !UseFPOffset) {
17793 // If we only pull from the overflow region, we don't create a branch.
17794 // We don't need to alter control flow.
17795 OffsetDestReg = 0; // unused
17796 OverflowDestReg = DestReg;
17798 offsetMBB = nullptr;
17799 overflowMBB = thisMBB;
17802 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17803 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17804 // If not, pull from overflow_area. (branch to overflowMBB)
17809 // offsetMBB overflowMBB
17814 // Registers for the PHI in endMBB
17815 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17816 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17818 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17819 MachineFunction *MF = MBB->getParent();
17820 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17821 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17822 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17824 MachineFunction::iterator MBBIter = MBB;
17827 // Insert the new basic blocks
17828 MF->insert(MBBIter, offsetMBB);
17829 MF->insert(MBBIter, overflowMBB);
17830 MF->insert(MBBIter, endMBB);
17832 // Transfer the remainder of MBB and its successor edges to endMBB.
17833 endMBB->splice(endMBB->begin(), thisMBB,
17834 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17835 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17837 // Make offsetMBB and overflowMBB successors of thisMBB
17838 thisMBB->addSuccessor(offsetMBB);
17839 thisMBB->addSuccessor(overflowMBB);
17841 // endMBB is a successor of both offsetMBB and overflowMBB
17842 offsetMBB->addSuccessor(endMBB);
17843 overflowMBB->addSuccessor(endMBB);
17845 // Load the offset value into a register
17846 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17847 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17851 .addDisp(Disp, UseFPOffset ? 4 : 0)
17852 .addOperand(Segment)
17853 .setMemRefs(MMOBegin, MMOEnd);
17855 // Check if there is enough room left to pull this argument.
17856 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17858 .addImm(MaxOffset + 8 - ArgSizeA8);
17860 // Branch to "overflowMBB" if offset >= max
17861 // Fall through to "offsetMBB" otherwise
17862 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17863 .addMBB(overflowMBB);
17866 // In offsetMBB, emit code to use the reg_save_area.
17868 assert(OffsetReg != 0);
17870 // Read the reg_save_area address.
17871 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17872 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17877 .addOperand(Segment)
17878 .setMemRefs(MMOBegin, MMOEnd);
17880 // Zero-extend the offset
17881 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17882 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17885 .addImm(X86::sub_32bit);
17887 // Add the offset to the reg_save_area to get the final address.
17888 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17889 .addReg(OffsetReg64)
17890 .addReg(RegSaveReg);
17892 // Compute the offset for the next argument
17893 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17894 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17896 .addImm(UseFPOffset ? 16 : 8);
17898 // Store it back into the va_list.
17899 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17903 .addDisp(Disp, UseFPOffset ? 4 : 0)
17904 .addOperand(Segment)
17905 .addReg(NextOffsetReg)
17906 .setMemRefs(MMOBegin, MMOEnd);
17909 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
17914 // Emit code to use overflow area
17917 // Load the overflow_area address into a register.
17918 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17919 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17924 .addOperand(Segment)
17925 .setMemRefs(MMOBegin, MMOEnd);
17927 // If we need to align it, do so. Otherwise, just copy the address
17928 // to OverflowDestReg.
17930 // Align the overflow address
17931 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17932 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17934 // aligned_addr = (addr + (align-1)) & ~(align-1)
17935 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17936 .addReg(OverflowAddrReg)
17939 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17941 .addImm(~(uint64_t)(Align-1));
17943 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17944 .addReg(OverflowAddrReg);
17947 // Compute the next overflow address after this argument.
17948 // (the overflow address should be kept 8-byte aligned)
17949 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17950 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17951 .addReg(OverflowDestReg)
17952 .addImm(ArgSizeA8);
17954 // Store the new overflow address.
17955 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17960 .addOperand(Segment)
17961 .addReg(NextAddrReg)
17962 .setMemRefs(MMOBegin, MMOEnd);
17964 // If we branched, emit the PHI to the front of endMBB.
17966 BuildMI(*endMBB, endMBB->begin(), DL,
17967 TII->get(X86::PHI), DestReg)
17968 .addReg(OffsetDestReg).addMBB(offsetMBB)
17969 .addReg(OverflowDestReg).addMBB(overflowMBB);
17972 // Erase the pseudo instruction
17973 MI->eraseFromParent();
17978 MachineBasicBlock *
17979 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17981 MachineBasicBlock *MBB) const {
17982 // Emit code to save XMM registers to the stack. The ABI says that the
17983 // number of registers to save is given in %al, so it's theoretically
17984 // possible to do an indirect jump trick to avoid saving all of them,
17985 // however this code takes a simpler approach and just executes all
17986 // of the stores if %al is non-zero. It's less code, and it's probably
17987 // easier on the hardware branch predictor, and stores aren't all that
17988 // expensive anyway.
17990 // Create the new basic blocks. One block contains all the XMM stores,
17991 // and one block is the final destination regardless of whether any
17992 // stores were performed.
17993 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17994 MachineFunction *F = MBB->getParent();
17995 MachineFunction::iterator MBBIter = MBB;
17997 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17998 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17999 F->insert(MBBIter, XMMSaveMBB);
18000 F->insert(MBBIter, EndMBB);
18002 // Transfer the remainder of MBB and its successor edges to EndMBB.
18003 EndMBB->splice(EndMBB->begin(), MBB,
18004 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18005 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18007 // The original block will now fall through to the XMM save block.
18008 MBB->addSuccessor(XMMSaveMBB);
18009 // The XMMSaveMBB will fall through to the end block.
18010 XMMSaveMBB->addSuccessor(EndMBB);
18012 // Now add the instructions.
18013 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18014 DebugLoc DL = MI->getDebugLoc();
18016 unsigned CountReg = MI->getOperand(0).getReg();
18017 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18018 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18020 if (!Subtarget->isTargetWin64()) {
18021 // If %al is 0, branch around the XMM save block.
18022 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18023 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18024 MBB->addSuccessor(EndMBB);
18027 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18028 // that was just emitted, but clearly shouldn't be "saved".
18029 assert((MI->getNumOperands() <= 3 ||
18030 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18031 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18032 && "Expected last argument to be EFLAGS");
18033 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18034 // In the XMM save block, save all the XMM argument registers.
18035 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18036 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18037 MachineMemOperand *MMO =
18038 F->getMachineMemOperand(
18039 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18040 MachineMemOperand::MOStore,
18041 /*Size=*/16, /*Align=*/16);
18042 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18043 .addFrameIndex(RegSaveFrameIndex)
18044 .addImm(/*Scale=*/1)
18045 .addReg(/*IndexReg=*/0)
18046 .addImm(/*Disp=*/Offset)
18047 .addReg(/*Segment=*/0)
18048 .addReg(MI->getOperand(i).getReg())
18049 .addMemOperand(MMO);
18052 MI->eraseFromParent(); // The pseudo instruction is gone now.
18057 // The EFLAGS operand of SelectItr might be missing a kill marker
18058 // because there were multiple uses of EFLAGS, and ISel didn't know
18059 // which to mark. Figure out whether SelectItr should have had a
18060 // kill marker, and set it if it should. Returns the correct kill
18062 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18063 MachineBasicBlock* BB,
18064 const TargetRegisterInfo* TRI) {
18065 // Scan forward through BB for a use/def of EFLAGS.
18066 MachineBasicBlock::iterator miI(std::next(SelectItr));
18067 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18068 const MachineInstr& mi = *miI;
18069 if (mi.readsRegister(X86::EFLAGS))
18071 if (mi.definesRegister(X86::EFLAGS))
18072 break; // Should have kill-flag - update below.
18075 // If we hit the end of the block, check whether EFLAGS is live into a
18077 if (miI == BB->end()) {
18078 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18079 sEnd = BB->succ_end();
18080 sItr != sEnd; ++sItr) {
18081 MachineBasicBlock* succ = *sItr;
18082 if (succ->isLiveIn(X86::EFLAGS))
18087 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18088 // out. SelectMI should have a kill flag on EFLAGS.
18089 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18093 MachineBasicBlock *
18094 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18095 MachineBasicBlock *BB) const {
18096 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18097 DebugLoc DL = MI->getDebugLoc();
18099 // To "insert" a SELECT_CC instruction, we actually have to insert the
18100 // diamond control-flow pattern. The incoming instruction knows the
18101 // destination vreg to set, the condition code register to branch on, the
18102 // true/false values to select between, and a branch opcode to use.
18103 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18104 MachineFunction::iterator It = BB;
18110 // cmpTY ccX, r1, r2
18112 // fallthrough --> copy0MBB
18113 MachineBasicBlock *thisMBB = BB;
18114 MachineFunction *F = BB->getParent();
18115 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18116 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18117 F->insert(It, copy0MBB);
18118 F->insert(It, sinkMBB);
18120 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18121 // live into the sink and copy blocks.
18122 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18123 if (!MI->killsRegister(X86::EFLAGS) &&
18124 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18125 copy0MBB->addLiveIn(X86::EFLAGS);
18126 sinkMBB->addLiveIn(X86::EFLAGS);
18129 // Transfer the remainder of BB and its successor edges to sinkMBB.
18130 sinkMBB->splice(sinkMBB->begin(), BB,
18131 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18132 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18134 // Add the true and fallthrough blocks as its successors.
18135 BB->addSuccessor(copy0MBB);
18136 BB->addSuccessor(sinkMBB);
18138 // Create the conditional branch instruction.
18140 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18141 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18144 // %FalseValue = ...
18145 // # fallthrough to sinkMBB
18146 copy0MBB->addSuccessor(sinkMBB);
18149 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18151 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18152 TII->get(X86::PHI), MI->getOperand(0).getReg())
18153 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18154 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18156 MI->eraseFromParent(); // The pseudo instruction is gone now.
18160 MachineBasicBlock *
18161 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18162 MachineBasicBlock *BB) const {
18163 MachineFunction *MF = BB->getParent();
18164 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18165 DebugLoc DL = MI->getDebugLoc();
18166 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18168 assert(MF->shouldSplitStack());
18170 const bool Is64Bit = Subtarget->is64Bit();
18171 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18173 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18174 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18177 // ... [Till the alloca]
18178 // If stacklet is not large enough, jump to mallocMBB
18181 // Allocate by subtracting from RSP
18182 // Jump to continueMBB
18185 // Allocate by call to runtime
18189 // [rest of original BB]
18192 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18193 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18194 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18196 MachineRegisterInfo &MRI = MF->getRegInfo();
18197 const TargetRegisterClass *AddrRegClass =
18198 getRegClassFor(getPointerTy());
18200 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18201 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18202 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18203 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18204 sizeVReg = MI->getOperand(1).getReg(),
18205 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18207 MachineFunction::iterator MBBIter = BB;
18210 MF->insert(MBBIter, bumpMBB);
18211 MF->insert(MBBIter, mallocMBB);
18212 MF->insert(MBBIter, continueMBB);
18214 continueMBB->splice(continueMBB->begin(), BB,
18215 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18216 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18218 // Add code to the main basic block to check if the stack limit has been hit,
18219 // and if so, jump to mallocMBB otherwise to bumpMBB.
18220 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18221 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18222 .addReg(tmpSPVReg).addReg(sizeVReg);
18223 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18224 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18225 .addReg(SPLimitVReg);
18226 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18228 // bumpMBB simply decreases the stack pointer, since we know the current
18229 // stacklet has enough space.
18230 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18231 .addReg(SPLimitVReg);
18232 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18233 .addReg(SPLimitVReg);
18234 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18236 // Calls into a routine in libgcc to allocate more space from the heap.
18237 const uint32_t *RegMask =
18238 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
18240 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18242 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18243 .addExternalSymbol("__morestack_allocate_stack_space")
18244 .addRegMask(RegMask)
18245 .addReg(X86::RDI, RegState::Implicit)
18246 .addReg(X86::RAX, RegState::ImplicitDefine);
18247 } else if (Is64Bit) {
18248 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
18250 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18251 .addExternalSymbol("__morestack_allocate_stack_space")
18252 .addRegMask(RegMask)
18253 .addReg(X86::EDI, RegState::Implicit)
18254 .addReg(X86::EAX, RegState::ImplicitDefine);
18256 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18258 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18259 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18260 .addExternalSymbol("__morestack_allocate_stack_space")
18261 .addRegMask(RegMask)
18262 .addReg(X86::EAX, RegState::ImplicitDefine);
18266 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18269 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18270 .addReg(IsLP64 ? X86::RAX : X86::EAX);
18271 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18273 // Set up the CFG correctly.
18274 BB->addSuccessor(bumpMBB);
18275 BB->addSuccessor(mallocMBB);
18276 mallocMBB->addSuccessor(continueMBB);
18277 bumpMBB->addSuccessor(continueMBB);
18279 // Take care of the PHI nodes.
18280 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18281 MI->getOperand(0).getReg())
18282 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18283 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18285 // Delete the original pseudo instruction.
18286 MI->eraseFromParent();
18289 return continueMBB;
18292 MachineBasicBlock *
18293 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18294 MachineBasicBlock *BB) const {
18295 DebugLoc DL = MI->getDebugLoc();
18297 assert(!Subtarget->isTargetMachO());
18299 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
18301 MI->eraseFromParent(); // The pseudo instruction is gone now.
18305 MachineBasicBlock *
18306 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18307 MachineBasicBlock *BB) const {
18308 // This is pretty easy. We're taking the value that we received from
18309 // our load from the relocation, sticking it in either RDI (x86-64)
18310 // or EAX and doing an indirect call. The return value will then
18311 // be in the normal return register.
18312 MachineFunction *F = BB->getParent();
18313 const X86InstrInfo *TII = Subtarget->getInstrInfo();
18314 DebugLoc DL = MI->getDebugLoc();
18316 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18317 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18319 // Get a register mask for the lowered call.
18320 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18321 // proper register mask.
18322 const uint32_t *RegMask =
18323 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
18324 if (Subtarget->is64Bit()) {
18325 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18326 TII->get(X86::MOV64rm), X86::RDI)
18328 .addImm(0).addReg(0)
18329 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18330 MI->getOperand(3).getTargetFlags())
18332 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18333 addDirectMem(MIB, X86::RDI);
18334 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18335 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18336 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18337 TII->get(X86::MOV32rm), X86::EAX)
18339 .addImm(0).addReg(0)
18340 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18341 MI->getOperand(3).getTargetFlags())
18343 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18344 addDirectMem(MIB, X86::EAX);
18345 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18347 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18348 TII->get(X86::MOV32rm), X86::EAX)
18349 .addReg(TII->getGlobalBaseReg(F))
18350 .addImm(0).addReg(0)
18351 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18352 MI->getOperand(3).getTargetFlags())
18354 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18355 addDirectMem(MIB, X86::EAX);
18356 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18359 MI->eraseFromParent(); // The pseudo instruction is gone now.
18363 MachineBasicBlock *
18364 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18365 MachineBasicBlock *MBB) const {
18366 DebugLoc DL = MI->getDebugLoc();
18367 MachineFunction *MF = MBB->getParent();
18368 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18369 MachineRegisterInfo &MRI = MF->getRegInfo();
18371 const BasicBlock *BB = MBB->getBasicBlock();
18372 MachineFunction::iterator I = MBB;
18375 // Memory Reference
18376 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18377 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18380 unsigned MemOpndSlot = 0;
18382 unsigned CurOp = 0;
18384 DstReg = MI->getOperand(CurOp++).getReg();
18385 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18386 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18387 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18388 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18390 MemOpndSlot = CurOp;
18392 MVT PVT = getPointerTy();
18393 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18394 "Invalid Pointer Size!");
18396 // For v = setjmp(buf), we generate
18399 // buf[LabelOffset] = restoreMBB
18400 // SjLjSetup restoreMBB
18406 // v = phi(main, restore)
18409 // if base pointer being used, load it from frame
18412 MachineBasicBlock *thisMBB = MBB;
18413 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18414 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18415 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18416 MF->insert(I, mainMBB);
18417 MF->insert(I, sinkMBB);
18418 MF->push_back(restoreMBB);
18420 MachineInstrBuilder MIB;
18422 // Transfer the remainder of BB and its successor edges to sinkMBB.
18423 sinkMBB->splice(sinkMBB->begin(), MBB,
18424 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18425 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18428 unsigned PtrStoreOpc = 0;
18429 unsigned LabelReg = 0;
18430 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18431 Reloc::Model RM = MF->getTarget().getRelocationModel();
18432 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18433 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18435 // Prepare IP either in reg or imm.
18436 if (!UseImmLabel) {
18437 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18438 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18439 LabelReg = MRI.createVirtualRegister(PtrRC);
18440 if (Subtarget->is64Bit()) {
18441 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18445 .addMBB(restoreMBB)
18448 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18449 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18450 .addReg(XII->getGlobalBaseReg(MF))
18453 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18457 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18459 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18460 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18461 if (i == X86::AddrDisp)
18462 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18464 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18467 MIB.addReg(LabelReg);
18469 MIB.addMBB(restoreMBB);
18470 MIB.setMemRefs(MMOBegin, MMOEnd);
18472 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18473 .addMBB(restoreMBB);
18475 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18476 MIB.addRegMask(RegInfo->getNoPreservedMask());
18477 thisMBB->addSuccessor(mainMBB);
18478 thisMBB->addSuccessor(restoreMBB);
18482 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18483 mainMBB->addSuccessor(sinkMBB);
18486 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18487 TII->get(X86::PHI), DstReg)
18488 .addReg(mainDstReg).addMBB(mainMBB)
18489 .addReg(restoreDstReg).addMBB(restoreMBB);
18492 if (RegInfo->hasBasePointer(*MF)) {
18493 const bool Uses64BitFramePtr =
18494 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
18495 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
18496 X86FI->setRestoreBasePointer(MF);
18497 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
18498 unsigned BasePtr = RegInfo->getBaseRegister();
18499 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
18500 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
18501 FramePtr, true, X86FI->getRestoreBasePointerOffset())
18502 .setMIFlag(MachineInstr::FrameSetup);
18504 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18505 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
18506 restoreMBB->addSuccessor(sinkMBB);
18508 MI->eraseFromParent();
18512 MachineBasicBlock *
18513 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18514 MachineBasicBlock *MBB) const {
18515 DebugLoc DL = MI->getDebugLoc();
18516 MachineFunction *MF = MBB->getParent();
18517 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18518 MachineRegisterInfo &MRI = MF->getRegInfo();
18520 // Memory Reference
18521 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18522 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18524 MVT PVT = getPointerTy();
18525 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18526 "Invalid Pointer Size!");
18528 const TargetRegisterClass *RC =
18529 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18530 unsigned Tmp = MRI.createVirtualRegister(RC);
18531 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18532 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18533 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18534 unsigned SP = RegInfo->getStackRegister();
18536 MachineInstrBuilder MIB;
18538 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18539 const int64_t SPOffset = 2 * PVT.getStoreSize();
18541 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18542 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18545 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18546 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18547 MIB.addOperand(MI->getOperand(i));
18548 MIB.setMemRefs(MMOBegin, MMOEnd);
18550 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18551 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18552 if (i == X86::AddrDisp)
18553 MIB.addDisp(MI->getOperand(i), LabelOffset);
18555 MIB.addOperand(MI->getOperand(i));
18557 MIB.setMemRefs(MMOBegin, MMOEnd);
18559 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18560 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18561 if (i == X86::AddrDisp)
18562 MIB.addDisp(MI->getOperand(i), SPOffset);
18564 MIB.addOperand(MI->getOperand(i));
18566 MIB.setMemRefs(MMOBegin, MMOEnd);
18568 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18570 MI->eraseFromParent();
18574 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18575 // accumulator loops. Writing back to the accumulator allows the coalescer
18576 // to remove extra copies in the loop.
18577 MachineBasicBlock *
18578 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18579 MachineBasicBlock *MBB) const {
18580 MachineOperand &AddendOp = MI->getOperand(3);
18582 // Bail out early if the addend isn't a register - we can't switch these.
18583 if (!AddendOp.isReg())
18586 MachineFunction &MF = *MBB->getParent();
18587 MachineRegisterInfo &MRI = MF.getRegInfo();
18589 // Check whether the addend is defined by a PHI:
18590 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18591 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18592 if (!AddendDef.isPHI())
18595 // Look for the following pattern:
18597 // %addend = phi [%entry, 0], [%loop, %result]
18599 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18603 // %addend = phi [%entry, 0], [%loop, %result]
18605 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18607 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18608 assert(AddendDef.getOperand(i).isReg());
18609 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18610 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18611 if (&PHISrcInst == MI) {
18612 // Found a matching instruction.
18613 unsigned NewFMAOpc = 0;
18614 switch (MI->getOpcode()) {
18615 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18616 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18617 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18618 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18619 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18620 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18621 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18622 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18623 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18624 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18625 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18626 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18627 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18628 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18629 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18630 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18631 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
18632 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
18633 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
18634 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
18636 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18637 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18638 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18639 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18640 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18641 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18642 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18643 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18644 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
18645 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
18646 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
18647 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
18648 default: llvm_unreachable("Unrecognized FMA variant.");
18651 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
18652 MachineInstrBuilder MIB =
18653 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18654 .addOperand(MI->getOperand(0))
18655 .addOperand(MI->getOperand(3))
18656 .addOperand(MI->getOperand(2))
18657 .addOperand(MI->getOperand(1));
18658 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18659 MI->eraseFromParent();
18666 MachineBasicBlock *
18667 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18668 MachineBasicBlock *BB) const {
18669 switch (MI->getOpcode()) {
18670 default: llvm_unreachable("Unexpected instr type to insert");
18671 case X86::TAILJMPd64:
18672 case X86::TAILJMPr64:
18673 case X86::TAILJMPm64:
18674 case X86::TAILJMPd64_REX:
18675 case X86::TAILJMPr64_REX:
18676 case X86::TAILJMPm64_REX:
18677 llvm_unreachable("TAILJMP64 would not be touched here.");
18678 case X86::TCRETURNdi64:
18679 case X86::TCRETURNri64:
18680 case X86::TCRETURNmi64:
18682 case X86::WIN_ALLOCA:
18683 return EmitLoweredWinAlloca(MI, BB);
18684 case X86::SEG_ALLOCA_32:
18685 case X86::SEG_ALLOCA_64:
18686 return EmitLoweredSegAlloca(MI, BB);
18687 case X86::TLSCall_32:
18688 case X86::TLSCall_64:
18689 return EmitLoweredTLSCall(MI, BB);
18690 case X86::CMOV_GR8:
18691 case X86::CMOV_FR32:
18692 case X86::CMOV_FR64:
18693 case X86::CMOV_V4F32:
18694 case X86::CMOV_V2F64:
18695 case X86::CMOV_V2I64:
18696 case X86::CMOV_V8F32:
18697 case X86::CMOV_V4F64:
18698 case X86::CMOV_V4I64:
18699 case X86::CMOV_V16F32:
18700 case X86::CMOV_V8F64:
18701 case X86::CMOV_V8I64:
18702 case X86::CMOV_GR16:
18703 case X86::CMOV_GR32:
18704 case X86::CMOV_RFP32:
18705 case X86::CMOV_RFP64:
18706 case X86::CMOV_RFP80:
18707 return EmitLoweredSelect(MI, BB);
18709 case X86::FP32_TO_INT16_IN_MEM:
18710 case X86::FP32_TO_INT32_IN_MEM:
18711 case X86::FP32_TO_INT64_IN_MEM:
18712 case X86::FP64_TO_INT16_IN_MEM:
18713 case X86::FP64_TO_INT32_IN_MEM:
18714 case X86::FP64_TO_INT64_IN_MEM:
18715 case X86::FP80_TO_INT16_IN_MEM:
18716 case X86::FP80_TO_INT32_IN_MEM:
18717 case X86::FP80_TO_INT64_IN_MEM: {
18718 MachineFunction *F = BB->getParent();
18719 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18720 DebugLoc DL = MI->getDebugLoc();
18722 // Change the floating point control register to use "round towards zero"
18723 // mode when truncating to an integer value.
18724 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18725 addFrameReference(BuildMI(*BB, MI, DL,
18726 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18728 // Load the old value of the high byte of the control word...
18730 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18731 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18734 // Set the high part to be round to zero...
18735 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18738 // Reload the modified control word now...
18739 addFrameReference(BuildMI(*BB, MI, DL,
18740 TII->get(X86::FLDCW16m)), CWFrameIdx);
18742 // Restore the memory image of control word to original value
18743 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18746 // Get the X86 opcode to use.
18748 switch (MI->getOpcode()) {
18749 default: llvm_unreachable("illegal opcode!");
18750 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18751 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18752 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18753 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18754 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18755 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18756 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18757 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18758 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18762 MachineOperand &Op = MI->getOperand(0);
18764 AM.BaseType = X86AddressMode::RegBase;
18765 AM.Base.Reg = Op.getReg();
18767 AM.BaseType = X86AddressMode::FrameIndexBase;
18768 AM.Base.FrameIndex = Op.getIndex();
18770 Op = MI->getOperand(1);
18772 AM.Scale = Op.getImm();
18773 Op = MI->getOperand(2);
18775 AM.IndexReg = Op.getImm();
18776 Op = MI->getOperand(3);
18777 if (Op.isGlobal()) {
18778 AM.GV = Op.getGlobal();
18780 AM.Disp = Op.getImm();
18782 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18783 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18785 // Reload the original control word now.
18786 addFrameReference(BuildMI(*BB, MI, DL,
18787 TII->get(X86::FLDCW16m)), CWFrameIdx);
18789 MI->eraseFromParent(); // The pseudo instruction is gone now.
18792 // String/text processing lowering.
18793 case X86::PCMPISTRM128REG:
18794 case X86::VPCMPISTRM128REG:
18795 case X86::PCMPISTRM128MEM:
18796 case X86::VPCMPISTRM128MEM:
18797 case X86::PCMPESTRM128REG:
18798 case X86::VPCMPESTRM128REG:
18799 case X86::PCMPESTRM128MEM:
18800 case X86::VPCMPESTRM128MEM:
18801 assert(Subtarget->hasSSE42() &&
18802 "Target must have SSE4.2 or AVX features enabled");
18803 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
18805 // String/text processing lowering.
18806 case X86::PCMPISTRIREG:
18807 case X86::VPCMPISTRIREG:
18808 case X86::PCMPISTRIMEM:
18809 case X86::VPCMPISTRIMEM:
18810 case X86::PCMPESTRIREG:
18811 case X86::VPCMPESTRIREG:
18812 case X86::PCMPESTRIMEM:
18813 case X86::VPCMPESTRIMEM:
18814 assert(Subtarget->hasSSE42() &&
18815 "Target must have SSE4.2 or AVX features enabled");
18816 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
18818 // Thread synchronization.
18820 return EmitMonitor(MI, BB, Subtarget);
18824 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
18826 case X86::VASTART_SAVE_XMM_REGS:
18827 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18829 case X86::VAARG_64:
18830 return EmitVAARG64WithCustomInserter(MI, BB);
18832 case X86::EH_SjLj_SetJmp32:
18833 case X86::EH_SjLj_SetJmp64:
18834 return emitEHSjLjSetJmp(MI, BB);
18836 case X86::EH_SjLj_LongJmp32:
18837 case X86::EH_SjLj_LongJmp64:
18838 return emitEHSjLjLongJmp(MI, BB);
18840 case TargetOpcode::STATEPOINT:
18841 // As an implementation detail, STATEPOINT shares the STACKMAP format at
18842 // this point in the process. We diverge later.
18843 return emitPatchPoint(MI, BB);
18845 case TargetOpcode::STACKMAP:
18846 case TargetOpcode::PATCHPOINT:
18847 return emitPatchPoint(MI, BB);
18849 case X86::VFMADDPDr213r:
18850 case X86::VFMADDPSr213r:
18851 case X86::VFMADDSDr213r:
18852 case X86::VFMADDSSr213r:
18853 case X86::VFMSUBPDr213r:
18854 case X86::VFMSUBPSr213r:
18855 case X86::VFMSUBSDr213r:
18856 case X86::VFMSUBSSr213r:
18857 case X86::VFNMADDPDr213r:
18858 case X86::VFNMADDPSr213r:
18859 case X86::VFNMADDSDr213r:
18860 case X86::VFNMADDSSr213r:
18861 case X86::VFNMSUBPDr213r:
18862 case X86::VFNMSUBPSr213r:
18863 case X86::VFNMSUBSDr213r:
18864 case X86::VFNMSUBSSr213r:
18865 case X86::VFMADDSUBPDr213r:
18866 case X86::VFMADDSUBPSr213r:
18867 case X86::VFMSUBADDPDr213r:
18868 case X86::VFMSUBADDPSr213r:
18869 case X86::VFMADDPDr213rY:
18870 case X86::VFMADDPSr213rY:
18871 case X86::VFMSUBPDr213rY:
18872 case X86::VFMSUBPSr213rY:
18873 case X86::VFNMADDPDr213rY:
18874 case X86::VFNMADDPSr213rY:
18875 case X86::VFNMSUBPDr213rY:
18876 case X86::VFNMSUBPSr213rY:
18877 case X86::VFMADDSUBPDr213rY:
18878 case X86::VFMADDSUBPSr213rY:
18879 case X86::VFMSUBADDPDr213rY:
18880 case X86::VFMSUBADDPSr213rY:
18881 return emitFMA3Instr(MI, BB);
18885 //===----------------------------------------------------------------------===//
18886 // X86 Optimization Hooks
18887 //===----------------------------------------------------------------------===//
18889 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18892 const SelectionDAG &DAG,
18893 unsigned Depth) const {
18894 unsigned BitWidth = KnownZero.getBitWidth();
18895 unsigned Opc = Op.getOpcode();
18896 assert((Opc >= ISD::BUILTIN_OP_END ||
18897 Opc == ISD::INTRINSIC_WO_CHAIN ||
18898 Opc == ISD::INTRINSIC_W_CHAIN ||
18899 Opc == ISD::INTRINSIC_VOID) &&
18900 "Should use MaskedValueIsZero if you don't know whether Op"
18901 " is a target node!");
18903 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18917 // These nodes' second result is a boolean.
18918 if (Op.getResNo() == 0)
18921 case X86ISD::SETCC:
18922 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18924 case ISD::INTRINSIC_WO_CHAIN: {
18925 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18926 unsigned NumLoBits = 0;
18929 case Intrinsic::x86_sse_movmsk_ps:
18930 case Intrinsic::x86_avx_movmsk_ps_256:
18931 case Intrinsic::x86_sse2_movmsk_pd:
18932 case Intrinsic::x86_avx_movmsk_pd_256:
18933 case Intrinsic::x86_mmx_pmovmskb:
18934 case Intrinsic::x86_sse2_pmovmskb_128:
18935 case Intrinsic::x86_avx2_pmovmskb: {
18936 // High bits of movmskp{s|d}, pmovmskb are known zero.
18938 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18939 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18940 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18941 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18942 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18943 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18944 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18945 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18947 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18956 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18958 const SelectionDAG &,
18959 unsigned Depth) const {
18960 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18961 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18962 return Op.getValueType().getScalarType().getSizeInBits();
18968 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18969 /// node is a GlobalAddress + offset.
18970 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18971 const GlobalValue* &GA,
18972 int64_t &Offset) const {
18973 if (N->getOpcode() == X86ISD::Wrapper) {
18974 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18975 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18976 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18980 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18983 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18984 /// same as extracting the high 128-bit part of 256-bit vector and then
18985 /// inserting the result into the low part of a new 256-bit vector
18986 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18987 EVT VT = SVOp->getValueType(0);
18988 unsigned NumElems = VT.getVectorNumElements();
18990 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18991 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18992 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18993 SVOp->getMaskElt(j) >= 0)
18999 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19000 /// same as extracting the low 128-bit part of 256-bit vector and then
19001 /// inserting the result into the high part of a new 256-bit vector
19002 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19003 EVT VT = SVOp->getValueType(0);
19004 unsigned NumElems = VT.getVectorNumElements();
19006 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19007 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19008 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19009 SVOp->getMaskElt(j) >= 0)
19015 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19016 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19017 TargetLowering::DAGCombinerInfo &DCI,
19018 const X86Subtarget* Subtarget) {
19020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19021 SDValue V1 = SVOp->getOperand(0);
19022 SDValue V2 = SVOp->getOperand(1);
19023 EVT VT = SVOp->getValueType(0);
19024 unsigned NumElems = VT.getVectorNumElements();
19026 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19027 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19031 // V UNDEF BUILD_VECTOR UNDEF
19033 // CONCAT_VECTOR CONCAT_VECTOR
19036 // RESULT: V + zero extended
19038 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19039 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19040 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19043 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19046 // To match the shuffle mask, the first half of the mask should
19047 // be exactly the first vector, and all the rest a splat with the
19048 // first element of the second one.
19049 for (unsigned i = 0; i != NumElems/2; ++i)
19050 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19051 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19054 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19055 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19056 if (Ld->hasNUsesOfValue(1, 0)) {
19057 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19058 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19060 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19062 Ld->getPointerInfo(),
19063 Ld->getAlignment(),
19064 false/*isVolatile*/, true/*ReadMem*/,
19065 false/*WriteMem*/);
19067 // Make sure the newly-created LOAD is in the same position as Ld in
19068 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19069 // and update uses of Ld's output chain to use the TokenFactor.
19070 if (Ld->hasAnyUseOfValue(1)) {
19071 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19072 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19073 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19074 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19075 SDValue(ResNode.getNode(), 1));
19078 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19082 // Emit a zeroed vector and insert the desired subvector on its
19084 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19085 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19086 return DCI.CombineTo(N, InsV);
19089 //===--------------------------------------------------------------------===//
19090 // Combine some shuffles into subvector extracts and inserts:
19093 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19094 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19095 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19096 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19097 return DCI.CombineTo(N, InsV);
19100 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19101 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19102 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19103 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19104 return DCI.CombineTo(N, InsV);
19110 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19113 /// This is the leaf of the recursive combinine below. When we have found some
19114 /// chain of single-use x86 shuffle instructions and accumulated the combined
19115 /// shuffle mask represented by them, this will try to pattern match that mask
19116 /// into either a single instruction if there is a special purpose instruction
19117 /// for this operation, or into a PSHUFB instruction which is a fully general
19118 /// instruction but should only be used to replace chains over a certain depth.
19119 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19120 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19121 TargetLowering::DAGCombinerInfo &DCI,
19122 const X86Subtarget *Subtarget) {
19123 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19125 // Find the operand that enters the chain. Note that multiple uses are OK
19126 // here, we're not going to remove the operand we find.
19127 SDValue Input = Op.getOperand(0);
19128 while (Input.getOpcode() == ISD::BITCAST)
19129 Input = Input.getOperand(0);
19131 MVT VT = Input.getSimpleValueType();
19132 MVT RootVT = Root.getSimpleValueType();
19135 // Just remove no-op shuffle masks.
19136 if (Mask.size() == 1) {
19137 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19142 // Use the float domain if the operand type is a floating point type.
19143 bool FloatDomain = VT.isFloatingPoint();
19145 // For floating point shuffles, we don't have free copies in the shuffle
19146 // instructions or the ability to load as part of the instruction, so
19147 // canonicalize their shuffles to UNPCK or MOV variants.
19149 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19150 // vectors because it can have a load folded into it that UNPCK cannot. This
19151 // doesn't preclude something switching to the shorter encoding post-RA.
19153 // FIXME: Should teach these routines about AVX vector widths.
19154 if (FloatDomain && VT.getSizeInBits() == 128) {
19155 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19156 bool Lo = Mask.equals(0, 0);
19159 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19160 // is no slower than UNPCKLPD but has the option to fold the input operand
19161 // into even an unaligned memory load.
19162 if (Lo && Subtarget->hasSSE3()) {
19163 Shuffle = X86ISD::MOVDDUP;
19164 ShuffleVT = MVT::v2f64;
19166 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19167 // than the UNPCK variants.
19168 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19169 ShuffleVT = MVT::v4f32;
19171 if (Depth == 1 && Root->getOpcode() == Shuffle)
19172 return false; // Nothing to do!
19173 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19174 DCI.AddToWorklist(Op.getNode());
19175 if (Shuffle == X86ISD::MOVDDUP)
19176 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19178 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19179 DCI.AddToWorklist(Op.getNode());
19180 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19184 if (Subtarget->hasSSE3() &&
19185 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
19186 bool Lo = Mask.equals(0, 0, 2, 2);
19187 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19188 MVT ShuffleVT = MVT::v4f32;
19189 if (Depth == 1 && Root->getOpcode() == Shuffle)
19190 return false; // Nothing to do!
19191 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19192 DCI.AddToWorklist(Op.getNode());
19193 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19194 DCI.AddToWorklist(Op.getNode());
19195 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19199 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
19200 bool Lo = Mask.equals(0, 0, 1, 1);
19201 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19202 MVT ShuffleVT = MVT::v4f32;
19203 if (Depth == 1 && Root->getOpcode() == Shuffle)
19204 return false; // Nothing to do!
19205 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19206 DCI.AddToWorklist(Op.getNode());
19207 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19208 DCI.AddToWorklist(Op.getNode());
19209 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19215 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19216 // variants as none of these have single-instruction variants that are
19217 // superior to the UNPCK formulation.
19218 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19219 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19220 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19221 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19222 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19224 bool Lo = Mask[0] == 0;
19225 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19226 if (Depth == 1 && Root->getOpcode() == Shuffle)
19227 return false; // Nothing to do!
19229 switch (Mask.size()) {
19231 ShuffleVT = MVT::v8i16;
19234 ShuffleVT = MVT::v16i8;
19237 llvm_unreachable("Impossible mask size!");
19239 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19240 DCI.AddToWorklist(Op.getNode());
19241 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19242 DCI.AddToWorklist(Op.getNode());
19243 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19248 // Don't try to re-form single instruction chains under any circumstances now
19249 // that we've done encoding canonicalization for them.
19253 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19254 // can replace them with a single PSHUFB instruction profitably. Intel's
19255 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19256 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19257 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19258 SmallVector<SDValue, 16> PSHUFBMask;
19259 int NumBytes = VT.getSizeInBits() / 8;
19260 int Ratio = NumBytes / Mask.size();
19261 for (int i = 0; i < NumBytes; ++i) {
19262 if (Mask[i / Ratio] == SM_SentinelUndef) {
19263 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
19266 int M = Mask[i / Ratio] != SM_SentinelZero
19267 ? Ratio * Mask[i / Ratio] + i % Ratio
19269 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19271 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
19272 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
19273 DCI.AddToWorklist(Op.getNode());
19274 SDValue PSHUFBMaskOp =
19275 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
19276 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19277 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
19278 DCI.AddToWorklist(Op.getNode());
19279 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19284 // Failed to find any combines.
19288 /// \brief Fully generic combining of x86 shuffle instructions.
19290 /// This should be the last combine run over the x86 shuffle instructions. Once
19291 /// they have been fully optimized, this will recursively consider all chains
19292 /// of single-use shuffle instructions, build a generic model of the cumulative
19293 /// shuffle operation, and check for simpler instructions which implement this
19294 /// operation. We use this primarily for two purposes:
19296 /// 1) Collapse generic shuffles to specialized single instructions when
19297 /// equivalent. In most cases, this is just an encoding size win, but
19298 /// sometimes we will collapse multiple generic shuffles into a single
19299 /// special-purpose shuffle.
19300 /// 2) Look for sequences of shuffle instructions with 3 or more total
19301 /// instructions, and replace them with the slightly more expensive SSSE3
19302 /// PSHUFB instruction if available. We do this as the last combining step
19303 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19304 /// a suitable short sequence of other instructions. The PHUFB will either
19305 /// use a register or have to read from memory and so is slightly (but only
19306 /// slightly) more expensive than the other shuffle instructions.
19308 /// Because this is inherently a quadratic operation (for each shuffle in
19309 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19310 /// This should never be an issue in practice as the shuffle lowering doesn't
19311 /// produce sequences of more than 8 instructions.
19313 /// FIXME: We will currently miss some cases where the redundant shuffling
19314 /// would simplify under the threshold for PSHUFB formation because of
19315 /// combine-ordering. To fix this, we should do the redundant instruction
19316 /// combining in this recursive walk.
19317 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19318 ArrayRef<int> RootMask,
19319 int Depth, bool HasPSHUFB,
19321 TargetLowering::DAGCombinerInfo &DCI,
19322 const X86Subtarget *Subtarget) {
19323 // Bound the depth of our recursive combine because this is ultimately
19324 // quadratic in nature.
19328 // Directly rip through bitcasts to find the underlying operand.
19329 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19330 Op = Op.getOperand(0);
19332 MVT VT = Op.getSimpleValueType();
19333 if (!VT.isVector())
19334 return false; // Bail if we hit a non-vector.
19336 assert(Root.getSimpleValueType().isVector() &&
19337 "Shuffles operate on vector types!");
19338 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19339 "Can only combine shuffles of the same vector register size.");
19341 if (!isTargetShuffle(Op.getOpcode()))
19343 SmallVector<int, 16> OpMask;
19345 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19346 // We only can combine unary shuffles which we can decode the mask for.
19347 if (!HaveMask || !IsUnary)
19350 assert(VT.getVectorNumElements() == OpMask.size() &&
19351 "Different mask size from vector size!");
19352 assert(((RootMask.size() > OpMask.size() &&
19353 RootMask.size() % OpMask.size() == 0) ||
19354 (OpMask.size() > RootMask.size() &&
19355 OpMask.size() % RootMask.size() == 0) ||
19356 OpMask.size() == RootMask.size()) &&
19357 "The smaller number of elements must divide the larger.");
19358 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19359 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19360 assert(((RootRatio == 1 && OpRatio == 1) ||
19361 (RootRatio == 1) != (OpRatio == 1)) &&
19362 "Must not have a ratio for both incoming and op masks!");
19364 SmallVector<int, 16> Mask;
19365 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19367 // Merge this shuffle operation's mask into our accumulated mask. Note that
19368 // this shuffle's mask will be the first applied to the input, followed by the
19369 // root mask to get us all the way to the root value arrangement. The reason
19370 // for this order is that we are recursing up the operation chain.
19371 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19372 int RootIdx = i / RootRatio;
19373 if (RootMask[RootIdx] < 0) {
19374 // This is a zero or undef lane, we're done.
19375 Mask.push_back(RootMask[RootIdx]);
19379 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19380 int OpIdx = RootMaskedIdx / OpRatio;
19381 if (OpMask[OpIdx] < 0) {
19382 // The incoming lanes are zero or undef, it doesn't matter which ones we
19384 Mask.push_back(OpMask[OpIdx]);
19388 // Ok, we have non-zero lanes, map them through.
19389 Mask.push_back(OpMask[OpIdx] * OpRatio +
19390 RootMaskedIdx % OpRatio);
19393 // See if we can recurse into the operand to combine more things.
19394 switch (Op.getOpcode()) {
19395 case X86ISD::PSHUFB:
19397 case X86ISD::PSHUFD:
19398 case X86ISD::PSHUFHW:
19399 case X86ISD::PSHUFLW:
19400 if (Op.getOperand(0).hasOneUse() &&
19401 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19402 HasPSHUFB, DAG, DCI, Subtarget))
19406 case X86ISD::UNPCKL:
19407 case X86ISD::UNPCKH:
19408 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19409 // We can't check for single use, we have to check that this shuffle is the only user.
19410 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19411 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19412 HasPSHUFB, DAG, DCI, Subtarget))
19417 // Minor canonicalization of the accumulated shuffle mask to make it easier
19418 // to match below. All this does is detect masks with squential pairs of
19419 // elements, and shrink them to the half-width mask. It does this in a loop
19420 // so it will reduce the size of the mask to the minimal width mask which
19421 // performs an equivalent shuffle.
19422 SmallVector<int, 16> WidenedMask;
19423 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
19424 Mask = std::move(WidenedMask);
19425 WidenedMask.clear();
19428 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19432 /// \brief Get the PSHUF-style mask from PSHUF node.
19434 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19435 /// PSHUF-style masks that can be reused with such instructions.
19436 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19437 MVT VT = N.getSimpleValueType();
19438 SmallVector<int, 4> Mask;
19440 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
19444 // If we have more than 128-bits, only the low 128-bits of shuffle mask
19445 // matter. Check that the upper masks are repeats and remove them.
19446 if (VT.getSizeInBits() > 128) {
19447 int LaneElts = 128 / VT.getScalarSizeInBits();
19449 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
19450 for (int j = 0; j < LaneElts; ++j)
19451 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
19452 "Mask doesn't repeat in high 128-bit lanes!");
19454 Mask.resize(LaneElts);
19457 switch (N.getOpcode()) {
19458 case X86ISD::PSHUFD:
19460 case X86ISD::PSHUFLW:
19463 case X86ISD::PSHUFHW:
19464 Mask.erase(Mask.begin(), Mask.begin() + 4);
19465 for (int &M : Mask)
19469 llvm_unreachable("No valid shuffle instruction found!");
19473 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19475 /// We walk up the chain and look for a combinable shuffle, skipping over
19476 /// shuffles that we could hoist this shuffle's transformation past without
19477 /// altering anything.
19479 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19481 TargetLowering::DAGCombinerInfo &DCI) {
19482 assert(N.getOpcode() == X86ISD::PSHUFD &&
19483 "Called with something other than an x86 128-bit half shuffle!");
19486 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19487 // of the shuffles in the chain so that we can form a fresh chain to replace
19489 SmallVector<SDValue, 8> Chain;
19490 SDValue V = N.getOperand(0);
19491 for (; V.hasOneUse(); V = V.getOperand(0)) {
19492 switch (V.getOpcode()) {
19494 return SDValue(); // Nothing combined!
19497 // Skip bitcasts as we always know the type for the target specific
19501 case X86ISD::PSHUFD:
19502 // Found another dword shuffle.
19505 case X86ISD::PSHUFLW:
19506 // Check that the low words (being shuffled) are the identity in the
19507 // dword shuffle, and the high words are self-contained.
19508 if (Mask[0] != 0 || Mask[1] != 1 ||
19509 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19512 Chain.push_back(V);
19515 case X86ISD::PSHUFHW:
19516 // Check that the high words (being shuffled) are the identity in the
19517 // dword shuffle, and the low words are self-contained.
19518 if (Mask[2] != 2 || Mask[3] != 3 ||
19519 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19522 Chain.push_back(V);
19525 case X86ISD::UNPCKL:
19526 case X86ISD::UNPCKH:
19527 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19528 // shuffle into a preceding word shuffle.
19529 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
19530 V.getSimpleValueType().getScalarType() != MVT::i16)
19533 // Search for a half-shuffle which we can combine with.
19534 unsigned CombineOp =
19535 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19536 if (V.getOperand(0) != V.getOperand(1) ||
19537 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19539 Chain.push_back(V);
19540 V = V.getOperand(0);
19542 switch (V.getOpcode()) {
19544 return SDValue(); // Nothing to combine.
19546 case X86ISD::PSHUFLW:
19547 case X86ISD::PSHUFHW:
19548 if (V.getOpcode() == CombineOp)
19551 Chain.push_back(V);
19555 V = V.getOperand(0);
19559 } while (V.hasOneUse());
19562 // Break out of the loop if we break out of the switch.
19566 if (!V.hasOneUse())
19567 // We fell out of the loop without finding a viable combining instruction.
19570 // Merge this node's mask and our incoming mask.
19571 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19572 for (int &M : Mask)
19574 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19575 getV4X86ShuffleImm8ForMask(Mask, DAG));
19577 // Rebuild the chain around this new shuffle.
19578 while (!Chain.empty()) {
19579 SDValue W = Chain.pop_back_val();
19581 if (V.getValueType() != W.getOperand(0).getValueType())
19582 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
19584 switch (W.getOpcode()) {
19586 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
19588 case X86ISD::UNPCKL:
19589 case X86ISD::UNPCKH:
19590 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
19593 case X86ISD::PSHUFD:
19594 case X86ISD::PSHUFLW:
19595 case X86ISD::PSHUFHW:
19596 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
19600 if (V.getValueType() != N.getValueType())
19601 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
19603 // Return the new chain to replace N.
19607 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19609 /// We walk up the chain, skipping shuffles of the other half and looking
19610 /// through shuffles which switch halves trying to find a shuffle of the same
19611 /// pair of dwords.
19612 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19614 TargetLowering::DAGCombinerInfo &DCI) {
19616 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19617 "Called with something other than an x86 128-bit half shuffle!");
19619 unsigned CombineOpcode = N.getOpcode();
19621 // Walk up a single-use chain looking for a combinable shuffle.
19622 SDValue V = N.getOperand(0);
19623 for (; V.hasOneUse(); V = V.getOperand(0)) {
19624 switch (V.getOpcode()) {
19626 return false; // Nothing combined!
19629 // Skip bitcasts as we always know the type for the target specific
19633 case X86ISD::PSHUFLW:
19634 case X86ISD::PSHUFHW:
19635 if (V.getOpcode() == CombineOpcode)
19638 // Other-half shuffles are no-ops.
19641 // Break out of the loop if we break out of the switch.
19645 if (!V.hasOneUse())
19646 // We fell out of the loop without finding a viable combining instruction.
19649 // Combine away the bottom node as its shuffle will be accumulated into
19650 // a preceding shuffle.
19651 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19653 // Record the old value.
19656 // Merge this node's mask and our incoming mask (adjusted to account for all
19657 // the pshufd instructions encountered).
19658 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19659 for (int &M : Mask)
19661 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19662 getV4X86ShuffleImm8ForMask(Mask, DAG));
19664 // Check that the shuffles didn't cancel each other out. If not, we need to
19665 // combine to the new one.
19667 // Replace the combinable shuffle with the combined one, updating all users
19668 // so that we re-evaluate the chain here.
19669 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19674 /// \brief Try to combine x86 target specific shuffles.
19675 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19676 TargetLowering::DAGCombinerInfo &DCI,
19677 const X86Subtarget *Subtarget) {
19679 MVT VT = N.getSimpleValueType();
19680 SmallVector<int, 4> Mask;
19682 switch (N.getOpcode()) {
19683 case X86ISD::PSHUFD:
19684 case X86ISD::PSHUFLW:
19685 case X86ISD::PSHUFHW:
19686 Mask = getPSHUFShuffleMask(N);
19687 assert(Mask.size() == 4);
19693 // Nuke no-op shuffles that show up after combining.
19694 if (isNoopShuffleMask(Mask))
19695 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19697 // Look for simplifications involving one or two shuffle instructions.
19698 SDValue V = N.getOperand(0);
19699 switch (N.getOpcode()) {
19702 case X86ISD::PSHUFLW:
19703 case X86ISD::PSHUFHW:
19704 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
19706 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19707 return SDValue(); // We combined away this shuffle, so we're done.
19709 // See if this reduces to a PSHUFD which is no more expensive and can
19710 // combine with more operations. Note that it has to at least flip the
19711 // dwords as otherwise it would have been removed as a no-op.
19712 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
19713 int DMask[] = {0, 1, 2, 3};
19714 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19715 DMask[DOffset + 0] = DOffset + 1;
19716 DMask[DOffset + 1] = DOffset + 0;
19717 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
19718 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
19719 DCI.AddToWorklist(V.getNode());
19720 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
19721 getV4X86ShuffleImm8ForMask(DMask, DAG));
19722 DCI.AddToWorklist(V.getNode());
19723 return DAG.getNode(ISD::BITCAST, DL, VT, V);
19726 // Look for shuffle patterns which can be implemented as a single unpack.
19727 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19728 // only works when we have a PSHUFD followed by two half-shuffles.
19729 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19730 (V.getOpcode() == X86ISD::PSHUFLW ||
19731 V.getOpcode() == X86ISD::PSHUFHW) &&
19732 V.getOpcode() != N.getOpcode() &&
19734 SDValue D = V.getOperand(0);
19735 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19736 D = D.getOperand(0);
19737 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19738 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19739 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19740 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19741 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19743 for (int i = 0; i < 4; ++i) {
19744 WordMask[i + NOffset] = Mask[i] + NOffset;
19745 WordMask[i + VOffset] = VMask[i] + VOffset;
19747 // Map the word mask through the DWord mask.
19749 for (int i = 0; i < 8; ++i)
19750 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19751 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19752 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19753 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19754 std::begin(UnpackLoMask)) ||
19755 std::equal(std::begin(MappedMask), std::end(MappedMask),
19756 std::begin(UnpackHiMask))) {
19757 // We can replace all three shuffles with an unpack.
19758 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
19759 DCI.AddToWorklist(V.getNode());
19760 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19769 case X86ISD::PSHUFD:
19770 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19779 /// \brief Try to combine a shuffle into a target-specific add-sub node.
19781 /// We combine this directly on the abstract vector shuffle nodes so it is
19782 /// easier to generically match. We also insert dummy vector shuffle nodes for
19783 /// the operands which explicitly discard the lanes which are unused by this
19784 /// operation to try to flow through the rest of the combiner the fact that
19785 /// they're unused.
19786 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
19788 EVT VT = N->getValueType(0);
19790 // We only handle target-independent shuffles.
19791 // FIXME: It would be easy and harmless to use the target shuffle mask
19792 // extraction tool to support more.
19793 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
19796 auto *SVN = cast<ShuffleVectorSDNode>(N);
19797 ArrayRef<int> Mask = SVN->getMask();
19798 SDValue V1 = N->getOperand(0);
19799 SDValue V2 = N->getOperand(1);
19801 // We require the first shuffle operand to be the SUB node, and the second to
19802 // be the ADD node.
19803 // FIXME: We should support the commuted patterns.
19804 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
19807 // If there are other uses of these operations we can't fold them.
19808 if (!V1->hasOneUse() || !V2->hasOneUse())
19811 // Ensure that both operations have the same operands. Note that we can
19812 // commute the FADD operands.
19813 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
19814 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
19815 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
19818 // We're looking for blends between FADD and FSUB nodes. We insist on these
19819 // nodes being lined up in a specific expected pattern.
19820 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
19821 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
19822 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
19825 // Only specific types are legal at this point, assert so we notice if and
19826 // when these change.
19827 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
19828 VT == MVT::v4f64) &&
19829 "Unknown vector type encountered!");
19831 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
19834 /// PerformShuffleCombine - Performs several different shuffle combines.
19835 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19836 TargetLowering::DAGCombinerInfo &DCI,
19837 const X86Subtarget *Subtarget) {
19839 SDValue N0 = N->getOperand(0);
19840 SDValue N1 = N->getOperand(1);
19841 EVT VT = N->getValueType(0);
19843 // Don't create instructions with illegal types after legalize types has run.
19844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19845 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19848 // If we have legalized the vector types, look for blends of FADD and FSUB
19849 // nodes that we can fuse into an ADDSUB node.
19850 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
19851 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
19854 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19855 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19856 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19857 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19859 // During Type Legalization, when promoting illegal vector types,
19860 // the backend might introduce new shuffle dag nodes and bitcasts.
19862 // This code performs the following transformation:
19863 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19864 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19866 // We do this only if both the bitcast and the BINOP dag nodes have
19867 // one use. Also, perform this transformation only if the new binary
19868 // operation is legal. This is to avoid introducing dag nodes that
19869 // potentially need to be further expanded (or custom lowered) into a
19870 // less optimal sequence of dag nodes.
19871 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19872 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19873 N0.getOpcode() == ISD::BITCAST) {
19874 SDValue BC0 = N0.getOperand(0);
19875 EVT SVT = BC0.getValueType();
19876 unsigned Opcode = BC0.getOpcode();
19877 unsigned NumElts = VT.getVectorNumElements();
19879 if (BC0.hasOneUse() && SVT.isVector() &&
19880 SVT.getVectorNumElements() * 2 == NumElts &&
19881 TLI.isOperationLegal(Opcode, VT)) {
19882 bool CanFold = false;
19894 unsigned SVTNumElts = SVT.getVectorNumElements();
19895 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19896 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19897 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19898 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19899 CanFold = SVOp->getMaskElt(i) < 0;
19902 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19903 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19904 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19905 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19910 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19911 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19912 // consecutive, non-overlapping, and in the right order.
19913 SmallVector<SDValue, 16> Elts;
19914 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19915 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19917 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19921 if (isTargetShuffle(N->getOpcode())) {
19923 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19924 if (Shuffle.getNode())
19927 // Try recursively combining arbitrary sequences of x86 shuffle
19928 // instructions into higher-order shuffles. We do this after combining
19929 // specific PSHUF instruction sequences into their minimal form so that we
19930 // can evaluate how many specialized shuffle instructions are involved in
19931 // a particular chain.
19932 SmallVector<int, 1> NonceMask; // Just a placeholder.
19933 NonceMask.push_back(0);
19934 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19935 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19937 return SDValue(); // This routine will use CombineTo to replace N.
19943 /// PerformTruncateCombine - Converts truncate operation to
19944 /// a sequence of vector shuffle operations.
19945 /// It is possible when we truncate 256-bit vector to 128-bit vector
19946 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19947 TargetLowering::DAGCombinerInfo &DCI,
19948 const X86Subtarget *Subtarget) {
19952 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19953 /// specific shuffle of a load can be folded into a single element load.
19954 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19955 /// shuffles have been custom lowered so we need to handle those here.
19956 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19957 TargetLowering::DAGCombinerInfo &DCI) {
19958 if (DCI.isBeforeLegalizeOps())
19961 SDValue InVec = N->getOperand(0);
19962 SDValue EltNo = N->getOperand(1);
19964 if (!isa<ConstantSDNode>(EltNo))
19967 EVT OriginalVT = InVec.getValueType();
19969 if (InVec.getOpcode() == ISD::BITCAST) {
19970 // Don't duplicate a load with other uses.
19971 if (!InVec.hasOneUse())
19973 EVT BCVT = InVec.getOperand(0).getValueType();
19974 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
19976 InVec = InVec.getOperand(0);
19979 EVT CurrentVT = InVec.getValueType();
19981 if (!isTargetShuffle(InVec.getOpcode()))
19984 // Don't duplicate a load with other uses.
19985 if (!InVec.hasOneUse())
19988 SmallVector<int, 16> ShuffleMask;
19990 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
19991 ShuffleMask, UnaryShuffle))
19994 // Select the input vector, guarding against out of range extract vector.
19995 unsigned NumElems = CurrentVT.getVectorNumElements();
19996 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19997 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19998 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19999 : InVec.getOperand(1);
20001 // If inputs to shuffle are the same for both ops, then allow 2 uses
20002 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20003 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20005 if (LdNode.getOpcode() == ISD::BITCAST) {
20006 // Don't duplicate a load with other uses.
20007 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20010 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20011 LdNode = LdNode.getOperand(0);
20014 if (!ISD::isNormalLoad(LdNode.getNode()))
20017 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20019 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20022 EVT EltVT = N->getValueType(0);
20023 // If there's a bitcast before the shuffle, check if the load type and
20024 // alignment is valid.
20025 unsigned Align = LN0->getAlignment();
20026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20027 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20028 EltVT.getTypeForEVT(*DAG.getContext()));
20030 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20033 // All checks match so transform back to vector_shuffle so that DAG combiner
20034 // can finish the job
20037 // Create shuffle node taking into account the case that its a unary shuffle
20038 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20039 : InVec.getOperand(1);
20040 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20041 InVec.getOperand(0), Shuffle,
20043 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20044 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20048 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20049 /// special and don't usually play with other vector types, it's better to
20050 /// handle them early to be sure we emit efficient code by avoiding
20051 /// store-load conversions.
20052 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20053 if (N->getValueType(0) != MVT::x86mmx ||
20054 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20055 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20058 SDValue V = N->getOperand(0);
20059 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20060 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20061 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20062 N->getValueType(0), V.getOperand(0));
20067 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20068 /// generation and convert it from being a bunch of shuffles and extracts
20069 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20070 /// storing the value and loading scalars back, while for x64 we should
20071 /// use 64-bit extracts and shifts.
20072 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20073 TargetLowering::DAGCombinerInfo &DCI) {
20074 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20075 if (NewOp.getNode())
20078 SDValue InputVector = N->getOperand(0);
20080 // Detect mmx to i32 conversion through a v2i32 elt extract.
20081 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20082 N->getValueType(0) == MVT::i32 &&
20083 InputVector.getValueType() == MVT::v2i32) {
20085 // The bitcast source is a direct mmx result.
20086 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20087 if (MMXSrc.getValueType() == MVT::x86mmx)
20088 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20089 N->getValueType(0),
20090 InputVector.getNode()->getOperand(0));
20092 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20093 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20094 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20095 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20096 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20097 MMXSrcOp.getValueType() == MVT::v1i64 &&
20098 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20099 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20100 N->getValueType(0),
20101 MMXSrcOp.getOperand(0));
20104 // Only operate on vectors of 4 elements, where the alternative shuffling
20105 // gets to be more expensive.
20106 if (InputVector.getValueType() != MVT::v4i32)
20109 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20110 // single use which is a sign-extend or zero-extend, and all elements are
20112 SmallVector<SDNode *, 4> Uses;
20113 unsigned ExtractedElements = 0;
20114 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20115 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20116 if (UI.getUse().getResNo() != InputVector.getResNo())
20119 SDNode *Extract = *UI;
20120 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20123 if (Extract->getValueType(0) != MVT::i32)
20125 if (!Extract->hasOneUse())
20127 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20128 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20130 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20133 // Record which element was extracted.
20134 ExtractedElements |=
20135 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20137 Uses.push_back(Extract);
20140 // If not all the elements were used, this may not be worthwhile.
20141 if (ExtractedElements != 15)
20144 // Ok, we've now decided to do the transformation.
20145 // If 64-bit shifts are legal, use the extract-shift sequence,
20146 // otherwise bounce the vector off the cache.
20147 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20149 SDLoc dl(InputVector);
20151 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20152 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20153 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20154 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20155 DAG.getConstant(0, VecIdxTy));
20156 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20157 DAG.getConstant(1, VecIdxTy));
20159 SDValue ShAmt = DAG.getConstant(32,
20160 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20161 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20162 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20163 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20164 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20165 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20166 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20168 // Store the value to a temporary stack slot.
20169 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20170 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20171 MachinePointerInfo(), false, false, 0);
20173 EVT ElementType = InputVector.getValueType().getVectorElementType();
20174 unsigned EltSize = ElementType.getSizeInBits() / 8;
20176 // Replace each use (extract) with a load of the appropriate element.
20177 for (unsigned i = 0; i < 4; ++i) {
20178 uint64_t Offset = EltSize * i;
20179 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20181 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20182 StackPtr, OffsetVal);
20184 // Load the scalar.
20185 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20186 ScalarAddr, MachinePointerInfo(),
20187 false, false, false, 0);
20192 // Replace the extracts
20193 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20194 UE = Uses.end(); UI != UE; ++UI) {
20195 SDNode *Extract = *UI;
20197 SDValue Idx = Extract->getOperand(1);
20198 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20199 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20202 // The replacement was made in place; don't return anything.
20206 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20207 static std::pair<unsigned, bool>
20208 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20209 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20210 if (!VT.isVector())
20211 return std::make_pair(0, false);
20213 bool NeedSplit = false;
20214 switch (VT.getSimpleVT().SimpleTy) {
20215 default: return std::make_pair(0, false);
20218 if (!Subtarget->hasVLX())
20219 return std::make_pair(0, false);
20223 if (!Subtarget->hasBWI())
20224 return std::make_pair(0, false);
20228 if (!Subtarget->hasAVX512())
20229 return std::make_pair(0, false);
20234 if (!Subtarget->hasAVX2())
20236 if (!Subtarget->hasAVX())
20237 return std::make_pair(0, false);
20242 if (!Subtarget->hasSSE2())
20243 return std::make_pair(0, false);
20246 // SSE2 has only a small subset of the operations.
20247 bool hasUnsigned = Subtarget->hasSSE41() ||
20248 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20249 bool hasSigned = Subtarget->hasSSE41() ||
20250 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20252 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20255 // Check for x CC y ? x : y.
20256 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20257 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20262 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20265 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20268 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20271 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20273 // Check for x CC y ? y : x -- a min/max with reversed arms.
20274 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20275 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20280 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20283 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20286 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20289 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20293 return std::make_pair(Opc, NeedSplit);
20297 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20298 const X86Subtarget *Subtarget) {
20300 SDValue Cond = N->getOperand(0);
20301 SDValue LHS = N->getOperand(1);
20302 SDValue RHS = N->getOperand(2);
20304 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20305 SDValue CondSrc = Cond->getOperand(0);
20306 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20307 Cond = CondSrc->getOperand(0);
20310 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20313 // A vselect where all conditions and data are constants can be optimized into
20314 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20315 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20316 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20319 unsigned MaskValue = 0;
20320 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20323 MVT VT = N->getSimpleValueType(0);
20324 unsigned NumElems = VT.getVectorNumElements();
20325 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20326 for (unsigned i = 0; i < NumElems; ++i) {
20327 // Be sure we emit undef where we can.
20328 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20329 ShuffleMask[i] = -1;
20331 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20334 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20335 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
20337 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20340 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20342 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20343 TargetLowering::DAGCombinerInfo &DCI,
20344 const X86Subtarget *Subtarget) {
20346 SDValue Cond = N->getOperand(0);
20347 // Get the LHS/RHS of the select.
20348 SDValue LHS = N->getOperand(1);
20349 SDValue RHS = N->getOperand(2);
20350 EVT VT = LHS.getValueType();
20351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20353 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20354 // instructions match the semantics of the common C idiom x<y?x:y but not
20355 // x<=y?x:y, because of how they handle negative zero (which can be
20356 // ignored in unsafe-math mode).
20357 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
20358 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20359 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
20360 (Subtarget->hasSSE2() ||
20361 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20362 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20364 unsigned Opcode = 0;
20365 // Check for x CC y ? x : y.
20366 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20367 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20371 // Converting this to a min would handle NaNs incorrectly, and swapping
20372 // the operands would cause it to handle comparisons between positive
20373 // and negative zero incorrectly.
20374 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20375 if (!DAG.getTarget().Options.UnsafeFPMath &&
20376 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20378 std::swap(LHS, RHS);
20380 Opcode = X86ISD::FMIN;
20383 // Converting this to a min would handle comparisons between positive
20384 // and negative zero incorrectly.
20385 if (!DAG.getTarget().Options.UnsafeFPMath &&
20386 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20388 Opcode = X86ISD::FMIN;
20391 // Converting this to a min would handle both negative zeros and NaNs
20392 // incorrectly, but we can swap the operands to fix both.
20393 std::swap(LHS, RHS);
20397 Opcode = X86ISD::FMIN;
20401 // Converting this to a max would handle comparisons between positive
20402 // and negative zero incorrectly.
20403 if (!DAG.getTarget().Options.UnsafeFPMath &&
20404 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20406 Opcode = X86ISD::FMAX;
20409 // Converting this to a max would handle NaNs incorrectly, and swapping
20410 // the operands would cause it to handle comparisons between positive
20411 // and negative zero incorrectly.
20412 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20413 if (!DAG.getTarget().Options.UnsafeFPMath &&
20414 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20416 std::swap(LHS, RHS);
20418 Opcode = X86ISD::FMAX;
20421 // Converting this to a max would handle both negative zeros and NaNs
20422 // incorrectly, but we can swap the operands to fix both.
20423 std::swap(LHS, RHS);
20427 Opcode = X86ISD::FMAX;
20430 // Check for x CC y ? y : x -- a min/max with reversed arms.
20431 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20432 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20436 // Converting this to a min would handle comparisons between positive
20437 // and negative zero incorrectly, and swapping the operands would
20438 // cause it to handle NaNs incorrectly.
20439 if (!DAG.getTarget().Options.UnsafeFPMath &&
20440 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20441 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20443 std::swap(LHS, RHS);
20445 Opcode = X86ISD::FMIN;
20448 // Converting this to a min would handle NaNs incorrectly.
20449 if (!DAG.getTarget().Options.UnsafeFPMath &&
20450 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20452 Opcode = X86ISD::FMIN;
20455 // Converting this to a min would handle both negative zeros and NaNs
20456 // incorrectly, but we can swap the operands to fix both.
20457 std::swap(LHS, RHS);
20461 Opcode = X86ISD::FMIN;
20465 // Converting this to a max would handle NaNs incorrectly.
20466 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20468 Opcode = X86ISD::FMAX;
20471 // Converting this to a max would handle comparisons between positive
20472 // and negative zero incorrectly, and swapping the operands would
20473 // cause it to handle NaNs incorrectly.
20474 if (!DAG.getTarget().Options.UnsafeFPMath &&
20475 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20476 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20478 std::swap(LHS, RHS);
20480 Opcode = X86ISD::FMAX;
20483 // Converting this to a max would handle both negative zeros and NaNs
20484 // incorrectly, but we can swap the operands to fix both.
20485 std::swap(LHS, RHS);
20489 Opcode = X86ISD::FMAX;
20495 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20498 EVT CondVT = Cond.getValueType();
20499 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20500 CondVT.getVectorElementType() == MVT::i1) {
20501 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20502 // lowering on KNL. In this case we convert it to
20503 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20504 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20505 // Since SKX these selects have a proper lowering.
20506 EVT OpVT = LHS.getValueType();
20507 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20508 (OpVT.getVectorElementType() == MVT::i8 ||
20509 OpVT.getVectorElementType() == MVT::i16) &&
20510 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20511 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20512 DCI.AddToWorklist(Cond.getNode());
20513 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20516 // If this is a select between two integer constants, try to do some
20518 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20519 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20520 // Don't do this for crazy integer types.
20521 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20522 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20523 // so that TrueC (the true value) is larger than FalseC.
20524 bool NeedsCondInvert = false;
20526 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20527 // Efficiently invertible.
20528 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20529 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20530 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20531 NeedsCondInvert = true;
20532 std::swap(TrueC, FalseC);
20535 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20536 if (FalseC->getAPIntValue() == 0 &&
20537 TrueC->getAPIntValue().isPowerOf2()) {
20538 if (NeedsCondInvert) // Invert the condition if needed.
20539 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20540 DAG.getConstant(1, Cond.getValueType()));
20542 // Zero extend the condition if needed.
20543 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20545 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20546 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20547 DAG.getConstant(ShAmt, MVT::i8));
20550 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20551 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20552 if (NeedsCondInvert) // Invert the condition if needed.
20553 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20554 DAG.getConstant(1, Cond.getValueType()));
20556 // Zero extend the condition if needed.
20557 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20558 FalseC->getValueType(0), Cond);
20559 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20560 SDValue(FalseC, 0));
20563 // Optimize cases that will turn into an LEA instruction. This requires
20564 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20565 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20566 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20567 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20569 bool isFastMultiplier = false;
20571 switch ((unsigned char)Diff) {
20573 case 1: // result = add base, cond
20574 case 2: // result = lea base( , cond*2)
20575 case 3: // result = lea base(cond, cond*2)
20576 case 4: // result = lea base( , cond*4)
20577 case 5: // result = lea base(cond, cond*4)
20578 case 8: // result = lea base( , cond*8)
20579 case 9: // result = lea base(cond, cond*8)
20580 isFastMultiplier = true;
20585 if (isFastMultiplier) {
20586 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20587 if (NeedsCondInvert) // Invert the condition if needed.
20588 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20589 DAG.getConstant(1, Cond.getValueType()));
20591 // Zero extend the condition if needed.
20592 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20594 // Scale the condition by the difference.
20596 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20597 DAG.getConstant(Diff, Cond.getValueType()));
20599 // Add the base if non-zero.
20600 if (FalseC->getAPIntValue() != 0)
20601 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20602 SDValue(FalseC, 0));
20609 // Canonicalize max and min:
20610 // (x > y) ? x : y -> (x >= y) ? x : y
20611 // (x < y) ? x : y -> (x <= y) ? x : y
20612 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20613 // the need for an extra compare
20614 // against zero. e.g.
20615 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20617 // testl %edi, %edi
20619 // cmovgl %edi, %eax
20623 // cmovsl %eax, %edi
20624 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20625 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20626 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20627 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20632 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20633 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20634 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20635 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20640 // Early exit check
20641 if (!TLI.isTypeLegal(VT))
20644 // Match VSELECTs into subs with unsigned saturation.
20645 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20646 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20647 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20648 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20649 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20651 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20652 // left side invert the predicate to simplify logic below.
20654 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20656 CC = ISD::getSetCCInverse(CC, true);
20657 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20661 if (Other.getNode() && Other->getNumOperands() == 2 &&
20662 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20663 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20664 SDValue CondRHS = Cond->getOperand(1);
20666 // Look for a general sub with unsigned saturation first.
20667 // x >= y ? x-y : 0 --> subus x, y
20668 // x > y ? x-y : 0 --> subus x, y
20669 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20670 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20671 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20673 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20674 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20675 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20676 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20677 // If the RHS is a constant we have to reverse the const
20678 // canonicalization.
20679 // x > C-1 ? x+-C : 0 --> subus x, C
20680 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20681 CondRHSConst->getAPIntValue() ==
20682 (-OpRHSConst->getAPIntValue() - 1))
20683 return DAG.getNode(
20684 X86ISD::SUBUS, DL, VT, OpLHS,
20685 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20687 // Another special case: If C was a sign bit, the sub has been
20688 // canonicalized into a xor.
20689 // FIXME: Would it be better to use computeKnownBits to determine
20690 // whether it's safe to decanonicalize the xor?
20691 // x s< 0 ? x^C : 0 --> subus x, C
20692 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20693 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20694 OpRHSConst->getAPIntValue().isSignBit())
20695 // Note that we have to rebuild the RHS constant here to ensure we
20696 // don't rely on particular values of undef lanes.
20697 return DAG.getNode(
20698 X86ISD::SUBUS, DL, VT, OpLHS,
20699 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20704 // Try to match a min/max vector operation.
20705 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20706 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20707 unsigned Opc = ret.first;
20708 bool NeedSplit = ret.second;
20710 if (Opc && NeedSplit) {
20711 unsigned NumElems = VT.getVectorNumElements();
20712 // Extract the LHS vectors
20713 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20714 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20716 // Extract the RHS vectors
20717 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20718 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20720 // Create min/max for each subvector
20721 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20722 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20724 // Merge the result
20725 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20727 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20730 // Simplify vector selection if condition value type matches vselect
20732 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
20733 assert(Cond.getValueType().isVector() &&
20734 "vector select expects a vector selector!");
20736 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20737 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20739 // Try invert the condition if true value is not all 1s and false value
20741 if (!TValIsAllOnes && !FValIsAllZeros &&
20742 // Check if the selector will be produced by CMPP*/PCMP*
20743 Cond.getOpcode() == ISD::SETCC &&
20744 // Check if SETCC has already been promoted
20745 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
20746 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20747 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20749 if (TValIsAllZeros || FValIsAllOnes) {
20750 SDValue CC = Cond.getOperand(2);
20751 ISD::CondCode NewCC =
20752 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20753 Cond.getOperand(0).getValueType().isInteger());
20754 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20755 std::swap(LHS, RHS);
20756 TValIsAllOnes = FValIsAllOnes;
20757 FValIsAllZeros = TValIsAllZeros;
20761 if (TValIsAllOnes || FValIsAllZeros) {
20764 if (TValIsAllOnes && FValIsAllZeros)
20766 else if (TValIsAllOnes)
20767 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20768 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20769 else if (FValIsAllZeros)
20770 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20771 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20773 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20777 // We should generate an X86ISD::BLENDI from a vselect if its argument
20778 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20779 // constants. This specific pattern gets generated when we split a
20780 // selector for a 512 bit vector in a machine without AVX512 (but with
20781 // 256-bit vectors), during legalization:
20783 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20785 // Iff we find this pattern and the build_vectors are built from
20786 // constants, we translate the vselect into a shuffle_vector that we
20787 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20788 if ((N->getOpcode() == ISD::VSELECT ||
20789 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
20790 !DCI.isBeforeLegalize()) {
20791 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20792 if (Shuffle.getNode())
20796 // If this is a *dynamic* select (non-constant condition) and we can match
20797 // this node with one of the variable blend instructions, restructure the
20798 // condition so that the blends can use the high bit of each element and use
20799 // SimplifyDemandedBits to simplify the condition operand.
20800 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20801 !DCI.isBeforeLegalize() &&
20802 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
20803 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20805 // Don't optimize vector selects that map to mask-registers.
20809 // We can only handle the cases where VSELECT is directly legal on the
20810 // subtarget. We custom lower VSELECT nodes with constant conditions and
20811 // this makes it hard to see whether a dynamic VSELECT will correctly
20812 // lower, so we both check the operation's status and explicitly handle the
20813 // cases where a *dynamic* blend will fail even though a constant-condition
20814 // blend could be custom lowered.
20815 // FIXME: We should find a better way to handle this class of problems.
20816 // Potentially, we should combine constant-condition vselect nodes
20817 // pre-legalization into shuffles and not mark as many types as custom
20819 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
20821 // FIXME: We don't support i16-element blends currently. We could and
20822 // should support them by making *all* the bits in the condition be set
20823 // rather than just the high bit and using an i8-element blend.
20824 if (VT.getScalarType() == MVT::i16)
20826 // Dynamic blending was only available from SSE4.1 onward.
20827 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
20829 // Byte blends are only available in AVX2
20830 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
20831 !Subtarget->hasAVX2())
20834 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20835 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20837 APInt KnownZero, KnownOne;
20838 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20839 DCI.isBeforeLegalizeOps());
20840 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20841 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
20843 // If we changed the computation somewhere in the DAG, this change
20844 // will affect all users of Cond.
20845 // Make sure it is fine and update all the nodes so that we do not
20846 // use the generic VSELECT anymore. Otherwise, we may perform
20847 // wrong optimizations as we messed up with the actual expectation
20848 // for the vector boolean values.
20849 if (Cond != TLO.Old) {
20850 // Check all uses of that condition operand to check whether it will be
20851 // consumed by non-BLEND instructions, which may depend on all bits are
20853 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
20855 if (I->getOpcode() != ISD::VSELECT)
20856 // TODO: Add other opcodes eventually lowered into BLEND.
20859 // Update all the users of the condition, before committing the change,
20860 // so that the VSELECT optimizations that expect the correct vector
20861 // boolean value will not be triggered.
20862 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
20864 DAG.ReplaceAllUsesOfValueWith(
20866 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
20867 Cond, I->getOperand(1), I->getOperand(2)));
20868 DCI.CommitTargetLoweringOpt(TLO);
20871 // At this point, only Cond is changed. Change the condition
20872 // just for N to keep the opportunity to optimize all other
20873 // users their own way.
20874 DAG.ReplaceAllUsesOfValueWith(
20876 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
20877 TLO.New, N->getOperand(1), N->getOperand(2)));
20885 // Check whether a boolean test is testing a boolean value generated by
20886 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20889 // Simplify the following patterns:
20890 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20891 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20892 // to (Op EFLAGS Cond)
20894 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20895 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20896 // to (Op EFLAGS !Cond)
20898 // where Op could be BRCOND or CMOV.
20900 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20901 // Quit if not CMP and SUB with its value result used.
20902 if (Cmp.getOpcode() != X86ISD::CMP &&
20903 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20906 // Quit if not used as a boolean value.
20907 if (CC != X86::COND_E && CC != X86::COND_NE)
20910 // Check CMP operands. One of them should be 0 or 1 and the other should be
20911 // an SetCC or extended from it.
20912 SDValue Op1 = Cmp.getOperand(0);
20913 SDValue Op2 = Cmp.getOperand(1);
20916 const ConstantSDNode* C = nullptr;
20917 bool needOppositeCond = (CC == X86::COND_E);
20918 bool checkAgainstTrue = false; // Is it a comparison against 1?
20920 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20922 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20924 else // Quit if all operands are not constants.
20927 if (C->getZExtValue() == 1) {
20928 needOppositeCond = !needOppositeCond;
20929 checkAgainstTrue = true;
20930 } else if (C->getZExtValue() != 0)
20931 // Quit if the constant is neither 0 or 1.
20934 bool truncatedToBoolWithAnd = false;
20935 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20936 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20937 SetCC.getOpcode() == ISD::TRUNCATE ||
20938 SetCC.getOpcode() == ISD::AND) {
20939 if (SetCC.getOpcode() == ISD::AND) {
20941 ConstantSDNode *CS;
20942 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20943 CS->getZExtValue() == 1)
20945 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20946 CS->getZExtValue() == 1)
20950 SetCC = SetCC.getOperand(OpIdx);
20951 truncatedToBoolWithAnd = true;
20953 SetCC = SetCC.getOperand(0);
20956 switch (SetCC.getOpcode()) {
20957 case X86ISD::SETCC_CARRY:
20958 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20959 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20960 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20961 // truncated to i1 using 'and'.
20962 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20964 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20965 "Invalid use of SETCC_CARRY!");
20967 case X86ISD::SETCC:
20968 // Set the condition code or opposite one if necessary.
20969 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20970 if (needOppositeCond)
20971 CC = X86::GetOppositeBranchCondition(CC);
20972 return SetCC.getOperand(1);
20973 case X86ISD::CMOV: {
20974 // Check whether false/true value has canonical one, i.e. 0 or 1.
20975 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20976 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20977 // Quit if true value is not a constant.
20980 // Quit if false value is not a constant.
20982 SDValue Op = SetCC.getOperand(0);
20983 // Skip 'zext' or 'trunc' node.
20984 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20985 Op.getOpcode() == ISD::TRUNCATE)
20986 Op = Op.getOperand(0);
20987 // A special case for rdrand/rdseed, where 0 is set if false cond is
20989 if ((Op.getOpcode() != X86ISD::RDRAND &&
20990 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20993 // Quit if false value is not the constant 0 or 1.
20994 bool FValIsFalse = true;
20995 if (FVal && FVal->getZExtValue() != 0) {
20996 if (FVal->getZExtValue() != 1)
20998 // If FVal is 1, opposite cond is needed.
20999 needOppositeCond = !needOppositeCond;
21000 FValIsFalse = false;
21002 // Quit if TVal is not the constant opposite of FVal.
21003 if (FValIsFalse && TVal->getZExtValue() != 1)
21005 if (!FValIsFalse && TVal->getZExtValue() != 0)
21007 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21008 if (needOppositeCond)
21009 CC = X86::GetOppositeBranchCondition(CC);
21010 return SetCC.getOperand(3);
21017 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21018 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21019 TargetLowering::DAGCombinerInfo &DCI,
21020 const X86Subtarget *Subtarget) {
21023 // If the flag operand isn't dead, don't touch this CMOV.
21024 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21027 SDValue FalseOp = N->getOperand(0);
21028 SDValue TrueOp = N->getOperand(1);
21029 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21030 SDValue Cond = N->getOperand(3);
21032 if (CC == X86::COND_E || CC == X86::COND_NE) {
21033 switch (Cond.getOpcode()) {
21037 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21038 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21039 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21045 Flags = checkBoolTestSetCCCombine(Cond, CC);
21046 if (Flags.getNode() &&
21047 // Extra check as FCMOV only supports a subset of X86 cond.
21048 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21049 SDValue Ops[] = { FalseOp, TrueOp,
21050 DAG.getConstant(CC, MVT::i8), Flags };
21051 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21054 // If this is a select between two integer constants, try to do some
21055 // optimizations. Note that the operands are ordered the opposite of SELECT
21057 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21058 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21059 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21060 // larger than FalseC (the false value).
21061 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21062 CC = X86::GetOppositeBranchCondition(CC);
21063 std::swap(TrueC, FalseC);
21064 std::swap(TrueOp, FalseOp);
21067 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21068 // This is efficient for any integer data type (including i8/i16) and
21070 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21071 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21072 DAG.getConstant(CC, MVT::i8), Cond);
21074 // Zero extend the condition if needed.
21075 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21077 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21078 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21079 DAG.getConstant(ShAmt, MVT::i8));
21080 if (N->getNumValues() == 2) // Dead flag value?
21081 return DCI.CombineTo(N, Cond, SDValue());
21085 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21086 // for any integer data type, including i8/i16.
21087 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21088 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21089 DAG.getConstant(CC, MVT::i8), Cond);
21091 // Zero extend the condition if needed.
21092 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21093 FalseC->getValueType(0), Cond);
21094 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21095 SDValue(FalseC, 0));
21097 if (N->getNumValues() == 2) // Dead flag value?
21098 return DCI.CombineTo(N, Cond, SDValue());
21102 // Optimize cases that will turn into an LEA instruction. This requires
21103 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21104 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21105 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21106 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21108 bool isFastMultiplier = false;
21110 switch ((unsigned char)Diff) {
21112 case 1: // result = add base, cond
21113 case 2: // result = lea base( , cond*2)
21114 case 3: // result = lea base(cond, cond*2)
21115 case 4: // result = lea base( , cond*4)
21116 case 5: // result = lea base(cond, cond*4)
21117 case 8: // result = lea base( , cond*8)
21118 case 9: // result = lea base(cond, cond*8)
21119 isFastMultiplier = true;
21124 if (isFastMultiplier) {
21125 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21126 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21127 DAG.getConstant(CC, MVT::i8), Cond);
21128 // Zero extend the condition if needed.
21129 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21131 // Scale the condition by the difference.
21133 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21134 DAG.getConstant(Diff, Cond.getValueType()));
21136 // Add the base if non-zero.
21137 if (FalseC->getAPIntValue() != 0)
21138 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21139 SDValue(FalseC, 0));
21140 if (N->getNumValues() == 2) // Dead flag value?
21141 return DCI.CombineTo(N, Cond, SDValue());
21148 // Handle these cases:
21149 // (select (x != c), e, c) -> select (x != c), e, x),
21150 // (select (x == c), c, e) -> select (x == c), x, e)
21151 // where the c is an integer constant, and the "select" is the combination
21152 // of CMOV and CMP.
21154 // The rationale for this change is that the conditional-move from a constant
21155 // needs two instructions, however, conditional-move from a register needs
21156 // only one instruction.
21158 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21159 // some instruction-combining opportunities. This opt needs to be
21160 // postponed as late as possible.
21162 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21163 // the DCI.xxxx conditions are provided to postpone the optimization as
21164 // late as possible.
21166 ConstantSDNode *CmpAgainst = nullptr;
21167 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21168 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21169 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21171 if (CC == X86::COND_NE &&
21172 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21173 CC = X86::GetOppositeBranchCondition(CC);
21174 std::swap(TrueOp, FalseOp);
21177 if (CC == X86::COND_E &&
21178 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21179 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21180 DAG.getConstant(CC, MVT::i8), Cond };
21181 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21189 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21190 const X86Subtarget *Subtarget) {
21191 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21193 default: return SDValue();
21194 // SSE/AVX/AVX2 blend intrinsics.
21195 case Intrinsic::x86_avx2_pblendvb:
21196 case Intrinsic::x86_avx2_pblendw:
21197 case Intrinsic::x86_avx2_pblendd_128:
21198 case Intrinsic::x86_avx2_pblendd_256:
21199 // Don't try to simplify this intrinsic if we don't have AVX2.
21200 if (!Subtarget->hasAVX2())
21203 case Intrinsic::x86_avx_blend_pd_256:
21204 case Intrinsic::x86_avx_blend_ps_256:
21205 case Intrinsic::x86_avx_blendv_pd_256:
21206 case Intrinsic::x86_avx_blendv_ps_256:
21207 // Don't try to simplify this intrinsic if we don't have AVX.
21208 if (!Subtarget->hasAVX())
21211 case Intrinsic::x86_sse41_pblendw:
21212 case Intrinsic::x86_sse41_blendpd:
21213 case Intrinsic::x86_sse41_blendps:
21214 case Intrinsic::x86_sse41_blendvps:
21215 case Intrinsic::x86_sse41_blendvpd:
21216 case Intrinsic::x86_sse41_pblendvb: {
21217 SDValue Op0 = N->getOperand(1);
21218 SDValue Op1 = N->getOperand(2);
21219 SDValue Mask = N->getOperand(3);
21221 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21222 if (!Subtarget->hasSSE41())
21225 // fold (blend A, A, Mask) -> A
21228 // fold (blend A, B, allZeros) -> A
21229 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21231 // fold (blend A, B, allOnes) -> B
21232 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21235 // Simplify the case where the mask is a constant i32 value.
21236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21237 if (C->isNullValue())
21239 if (C->isAllOnesValue())
21246 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21247 case Intrinsic::x86_sse2_psrai_w:
21248 case Intrinsic::x86_sse2_psrai_d:
21249 case Intrinsic::x86_avx2_psrai_w:
21250 case Intrinsic::x86_avx2_psrai_d:
21251 case Intrinsic::x86_sse2_psra_w:
21252 case Intrinsic::x86_sse2_psra_d:
21253 case Intrinsic::x86_avx2_psra_w:
21254 case Intrinsic::x86_avx2_psra_d: {
21255 SDValue Op0 = N->getOperand(1);
21256 SDValue Op1 = N->getOperand(2);
21257 EVT VT = Op0.getValueType();
21258 assert(VT.isVector() && "Expected a vector type!");
21260 if (isa<BuildVectorSDNode>(Op1))
21261 Op1 = Op1.getOperand(0);
21263 if (!isa<ConstantSDNode>(Op1))
21266 EVT SVT = VT.getVectorElementType();
21267 unsigned SVTBits = SVT.getSizeInBits();
21269 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21270 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21271 uint64_t ShAmt = C.getZExtValue();
21273 // Don't try to convert this shift into a ISD::SRA if the shift
21274 // count is bigger than or equal to the element size.
21275 if (ShAmt >= SVTBits)
21278 // Trivial case: if the shift count is zero, then fold this
21279 // into the first operand.
21283 // Replace this packed shift intrinsic with a target independent
21285 SDValue Splat = DAG.getConstant(C, VT);
21286 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21291 /// PerformMulCombine - Optimize a single multiply with constant into two
21292 /// in order to implement it with two cheaper instructions, e.g.
21293 /// LEA + SHL, LEA + LEA.
21294 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21295 TargetLowering::DAGCombinerInfo &DCI) {
21296 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21299 EVT VT = N->getValueType(0);
21300 if (VT != MVT::i64 && VT != MVT::i32)
21303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21306 uint64_t MulAmt = C->getZExtValue();
21307 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21310 uint64_t MulAmt1 = 0;
21311 uint64_t MulAmt2 = 0;
21312 if ((MulAmt % 9) == 0) {
21314 MulAmt2 = MulAmt / 9;
21315 } else if ((MulAmt % 5) == 0) {
21317 MulAmt2 = MulAmt / 5;
21318 } else if ((MulAmt % 3) == 0) {
21320 MulAmt2 = MulAmt / 3;
21323 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21326 if (isPowerOf2_64(MulAmt2) &&
21327 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21328 // If second multiplifer is pow2, issue it first. We want the multiply by
21329 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21331 std::swap(MulAmt1, MulAmt2);
21334 if (isPowerOf2_64(MulAmt1))
21335 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21336 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21338 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21339 DAG.getConstant(MulAmt1, VT));
21341 if (isPowerOf2_64(MulAmt2))
21342 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21343 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21345 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21346 DAG.getConstant(MulAmt2, VT));
21348 // Do not add new nodes to DAG combiner worklist.
21349 DCI.CombineTo(N, NewMul, false);
21354 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21355 SDValue N0 = N->getOperand(0);
21356 SDValue N1 = N->getOperand(1);
21357 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21358 EVT VT = N0.getValueType();
21360 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21361 // since the result of setcc_c is all zero's or all ones.
21362 if (VT.isInteger() && !VT.isVector() &&
21363 N1C && N0.getOpcode() == ISD::AND &&
21364 N0.getOperand(1).getOpcode() == ISD::Constant) {
21365 SDValue N00 = N0.getOperand(0);
21366 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21367 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21368 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21369 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21370 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21371 APInt ShAmt = N1C->getAPIntValue();
21372 Mask = Mask.shl(ShAmt);
21374 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21375 N00, DAG.getConstant(Mask, VT));
21379 // Hardware support for vector shifts is sparse which makes us scalarize the
21380 // vector operations in many cases. Also, on sandybridge ADD is faster than
21382 // (shl V, 1) -> add V,V
21383 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21384 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21385 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21386 // We shift all of the values by one. In many cases we do not have
21387 // hardware support for this operation. This is better expressed as an ADD
21389 if (N1SplatC->getZExtValue() == 1)
21390 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21396 /// \brief Returns a vector of 0s if the node in input is a vector logical
21397 /// shift by a constant amount which is known to be bigger than or equal
21398 /// to the vector element size in bits.
21399 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21400 const X86Subtarget *Subtarget) {
21401 EVT VT = N->getValueType(0);
21403 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21404 (!Subtarget->hasInt256() ||
21405 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21408 SDValue Amt = N->getOperand(1);
21410 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21411 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21412 APInt ShiftAmt = AmtSplat->getAPIntValue();
21413 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21415 // SSE2/AVX2 logical shifts always return a vector of 0s
21416 // if the shift amount is bigger than or equal to
21417 // the element size. The constant shift amount will be
21418 // encoded as a 8-bit immediate.
21419 if (ShiftAmt.trunc(8).uge(MaxAmount))
21420 return getZeroVector(VT, Subtarget, DAG, DL);
21426 /// PerformShiftCombine - Combine shifts.
21427 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21428 TargetLowering::DAGCombinerInfo &DCI,
21429 const X86Subtarget *Subtarget) {
21430 if (N->getOpcode() == ISD::SHL) {
21431 SDValue V = PerformSHLCombine(N, DAG);
21432 if (V.getNode()) return V;
21435 if (N->getOpcode() != ISD::SRA) {
21436 // Try to fold this logical shift into a zero vector.
21437 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21438 if (V.getNode()) return V;
21444 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21445 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21446 // and friends. Likewise for OR -> CMPNEQSS.
21447 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21448 TargetLowering::DAGCombinerInfo &DCI,
21449 const X86Subtarget *Subtarget) {
21452 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21453 // we're requiring SSE2 for both.
21454 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21455 SDValue N0 = N->getOperand(0);
21456 SDValue N1 = N->getOperand(1);
21457 SDValue CMP0 = N0->getOperand(1);
21458 SDValue CMP1 = N1->getOperand(1);
21461 // The SETCCs should both refer to the same CMP.
21462 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21465 SDValue CMP00 = CMP0->getOperand(0);
21466 SDValue CMP01 = CMP0->getOperand(1);
21467 EVT VT = CMP00.getValueType();
21469 if (VT == MVT::f32 || VT == MVT::f64) {
21470 bool ExpectingFlags = false;
21471 // Check for any users that want flags:
21472 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21473 !ExpectingFlags && UI != UE; ++UI)
21474 switch (UI->getOpcode()) {
21479 ExpectingFlags = true;
21481 case ISD::CopyToReg:
21482 case ISD::SIGN_EXTEND:
21483 case ISD::ZERO_EXTEND:
21484 case ISD::ANY_EXTEND:
21488 if (!ExpectingFlags) {
21489 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21490 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21492 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21493 X86::CondCode tmp = cc0;
21498 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21499 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21500 // FIXME: need symbolic constants for these magic numbers.
21501 // See X86ATTInstPrinter.cpp:printSSECC().
21502 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21503 if (Subtarget->hasAVX512()) {
21504 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21505 CMP01, DAG.getConstant(x86cc, MVT::i8));
21506 if (N->getValueType(0) != MVT::i1)
21507 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21511 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21512 CMP00.getValueType(), CMP00, CMP01,
21513 DAG.getConstant(x86cc, MVT::i8));
21515 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21516 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21518 if (is64BitFP && !Subtarget->is64Bit()) {
21519 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21520 // 64-bit integer, since that's not a legal type. Since
21521 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21522 // bits, but can do this little dance to extract the lowest 32 bits
21523 // and work with those going forward.
21524 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21526 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21528 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21529 Vector32, DAG.getIntPtrConstant(0));
21533 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21534 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21535 DAG.getConstant(1, IntVT));
21536 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21537 return OneBitOfTruth;
21545 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21546 /// so it can be folded inside ANDNP.
21547 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21548 EVT VT = N->getValueType(0);
21550 // Match direct AllOnes for 128 and 256-bit vectors
21551 if (ISD::isBuildVectorAllOnes(N))
21554 // Look through a bit convert.
21555 if (N->getOpcode() == ISD::BITCAST)
21556 N = N->getOperand(0).getNode();
21558 // Sometimes the operand may come from a insert_subvector building a 256-bit
21560 if (VT.is256BitVector() &&
21561 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21562 SDValue V1 = N->getOperand(0);
21563 SDValue V2 = N->getOperand(1);
21565 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21566 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21567 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21568 ISD::isBuildVectorAllOnes(V2.getNode()))
21575 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21576 // register. In most cases we actually compare or select YMM-sized registers
21577 // and mixing the two types creates horrible code. This method optimizes
21578 // some of the transition sequences.
21579 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21580 TargetLowering::DAGCombinerInfo &DCI,
21581 const X86Subtarget *Subtarget) {
21582 EVT VT = N->getValueType(0);
21583 if (!VT.is256BitVector())
21586 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21587 N->getOpcode() == ISD::ZERO_EXTEND ||
21588 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21590 SDValue Narrow = N->getOperand(0);
21591 EVT NarrowVT = Narrow->getValueType(0);
21592 if (!NarrowVT.is128BitVector())
21595 if (Narrow->getOpcode() != ISD::XOR &&
21596 Narrow->getOpcode() != ISD::AND &&
21597 Narrow->getOpcode() != ISD::OR)
21600 SDValue N0 = Narrow->getOperand(0);
21601 SDValue N1 = Narrow->getOperand(1);
21604 // The Left side has to be a trunc.
21605 if (N0.getOpcode() != ISD::TRUNCATE)
21608 // The type of the truncated inputs.
21609 EVT WideVT = N0->getOperand(0)->getValueType(0);
21613 // The right side has to be a 'trunc' or a constant vector.
21614 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21615 ConstantSDNode *RHSConstSplat = nullptr;
21616 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21617 RHSConstSplat = RHSBV->getConstantSplatNode();
21618 if (!RHSTrunc && !RHSConstSplat)
21621 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21623 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21626 // Set N0 and N1 to hold the inputs to the new wide operation.
21627 N0 = N0->getOperand(0);
21628 if (RHSConstSplat) {
21629 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21630 SDValue(RHSConstSplat, 0));
21631 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21632 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21633 } else if (RHSTrunc) {
21634 N1 = N1->getOperand(0);
21637 // Generate the wide operation.
21638 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21639 unsigned Opcode = N->getOpcode();
21641 case ISD::ANY_EXTEND:
21643 case ISD::ZERO_EXTEND: {
21644 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21645 APInt Mask = APInt::getAllOnesValue(InBits);
21646 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21647 return DAG.getNode(ISD::AND, DL, VT,
21648 Op, DAG.getConstant(Mask, VT));
21650 case ISD::SIGN_EXTEND:
21651 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21652 Op, DAG.getValueType(NarrowVT));
21654 llvm_unreachable("Unexpected opcode");
21658 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
21659 TargetLowering::DAGCombinerInfo &DCI,
21660 const X86Subtarget *Subtarget) {
21661 SDValue N0 = N->getOperand(0);
21662 SDValue N1 = N->getOperand(1);
21665 // A vector zext_in_reg may be represented as a shuffle,
21666 // feeding into a bitcast (this represents anyext) feeding into
21667 // an and with a mask.
21668 // We'd like to try to combine that into a shuffle with zero
21669 // plus a bitcast, removing the and.
21670 if (N0.getOpcode() != ISD::BITCAST ||
21671 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
21674 // The other side of the AND should be a splat of 2^C, where C
21675 // is the number of bits in the source type.
21676 if (N1.getOpcode() == ISD::BITCAST)
21677 N1 = N1.getOperand(0);
21678 if (N1.getOpcode() != ISD::BUILD_VECTOR)
21680 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
21682 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
21683 EVT SrcType = Shuffle->getValueType(0);
21685 // We expect a single-source shuffle
21686 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
21689 unsigned SrcSize = SrcType.getScalarSizeInBits();
21691 APInt SplatValue, SplatUndef;
21692 unsigned SplatBitSize;
21694 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
21695 SplatBitSize, HasAnyUndefs))
21698 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
21699 // Make sure the splat matches the mask we expect
21700 if (SplatBitSize > ResSize ||
21701 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
21704 // Make sure the input and output size make sense
21705 if (SrcSize >= ResSize || ResSize % SrcSize)
21708 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
21709 // The number of u's between each two values depends on the ratio between
21710 // the source and dest type.
21711 unsigned ZextRatio = ResSize / SrcSize;
21712 bool IsZext = true;
21713 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
21714 if (i % ZextRatio) {
21715 if (Shuffle->getMaskElt(i) > 0) {
21721 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
21722 // Expected element number
21732 // Ok, perform the transformation - replace the shuffle with
21733 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
21734 // (instead of undef) where the k elements come from the zero vector.
21735 SmallVector<int, 8> Mask;
21736 unsigned NumElems = SrcType.getVectorNumElements();
21737 for (unsigned i = 0; i < NumElems; ++i)
21739 Mask.push_back(NumElems);
21741 Mask.push_back(i / ZextRatio);
21743 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
21744 Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);
21745 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
21748 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21749 TargetLowering::DAGCombinerInfo &DCI,
21750 const X86Subtarget *Subtarget) {
21751 if (DCI.isBeforeLegalizeOps())
21754 SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget);
21755 if (Zext.getNode())
21758 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21762 EVT VT = N->getValueType(0);
21763 SDValue N0 = N->getOperand(0);
21764 SDValue N1 = N->getOperand(1);
21767 // Create BEXTR instructions
21768 // BEXTR is ((X >> imm) & (2**size-1))
21769 if (VT == MVT::i32 || VT == MVT::i64) {
21770 // Check for BEXTR.
21771 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21772 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21773 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21774 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21775 if (MaskNode && ShiftNode) {
21776 uint64_t Mask = MaskNode->getZExtValue();
21777 uint64_t Shift = ShiftNode->getZExtValue();
21778 if (isMask_64(Mask)) {
21779 uint64_t MaskSize = countPopulation(Mask);
21780 if (Shift + MaskSize <= VT.getSizeInBits())
21781 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21782 DAG.getConstant(Shift | (MaskSize << 8), VT));
21790 // Want to form ANDNP nodes:
21791 // 1) In the hopes of then easily combining them with OR and AND nodes
21792 // to form PBLEND/PSIGN.
21793 // 2) To match ANDN packed intrinsics
21794 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21797 // Check LHS for vnot
21798 if (N0.getOpcode() == ISD::XOR &&
21799 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21800 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21801 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21803 // Check RHS for vnot
21804 if (N1.getOpcode() == ISD::XOR &&
21805 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21806 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21807 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21812 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21813 TargetLowering::DAGCombinerInfo &DCI,
21814 const X86Subtarget *Subtarget) {
21815 if (DCI.isBeforeLegalizeOps())
21818 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21822 SDValue N0 = N->getOperand(0);
21823 SDValue N1 = N->getOperand(1);
21824 EVT VT = N->getValueType(0);
21826 // look for psign/blend
21827 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21828 if (!Subtarget->hasSSSE3() ||
21829 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21832 // Canonicalize pandn to RHS
21833 if (N0.getOpcode() == X86ISD::ANDNP)
21835 // or (and (m, y), (pandn m, x))
21836 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21837 SDValue Mask = N1.getOperand(0);
21838 SDValue X = N1.getOperand(1);
21840 if (N0.getOperand(0) == Mask)
21841 Y = N0.getOperand(1);
21842 if (N0.getOperand(1) == Mask)
21843 Y = N0.getOperand(0);
21845 // Check to see if the mask appeared in both the AND and ANDNP and
21849 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21850 // Look through mask bitcast.
21851 if (Mask.getOpcode() == ISD::BITCAST)
21852 Mask = Mask.getOperand(0);
21853 if (X.getOpcode() == ISD::BITCAST)
21854 X = X.getOperand(0);
21855 if (Y.getOpcode() == ISD::BITCAST)
21856 Y = Y.getOperand(0);
21858 EVT MaskVT = Mask.getValueType();
21860 // Validate that the Mask operand is a vector sra node.
21861 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21862 // there is no psrai.b
21863 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21864 unsigned SraAmt = ~0;
21865 if (Mask.getOpcode() == ISD::SRA) {
21866 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21867 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21868 SraAmt = AmtConst->getZExtValue();
21869 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21870 SDValue SraC = Mask.getOperand(1);
21871 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21873 if ((SraAmt + 1) != EltBits)
21878 // Now we know we at least have a plendvb with the mask val. See if
21879 // we can form a psignb/w/d.
21880 // psign = x.type == y.type == mask.type && y = sub(0, x);
21881 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21882 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21883 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21884 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21885 "Unsupported VT for PSIGN");
21886 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21887 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21889 // PBLENDVB only available on SSE 4.1
21890 if (!Subtarget->hasSSE41())
21893 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21895 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21896 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21897 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21898 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21899 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21903 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21906 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21907 MachineFunction &MF = DAG.getMachineFunction();
21909 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
21911 // SHLD/SHRD instructions have lower register pressure, but on some
21912 // platforms they have higher latency than the equivalent
21913 // series of shifts/or that would otherwise be generated.
21914 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21915 // have higher latencies and we are not optimizing for size.
21916 if (!OptForSize && Subtarget->isSHLDSlow())
21919 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21921 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21923 if (!N0.hasOneUse() || !N1.hasOneUse())
21926 SDValue ShAmt0 = N0.getOperand(1);
21927 if (ShAmt0.getValueType() != MVT::i8)
21929 SDValue ShAmt1 = N1.getOperand(1);
21930 if (ShAmt1.getValueType() != MVT::i8)
21932 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21933 ShAmt0 = ShAmt0.getOperand(0);
21934 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21935 ShAmt1 = ShAmt1.getOperand(0);
21938 unsigned Opc = X86ISD::SHLD;
21939 SDValue Op0 = N0.getOperand(0);
21940 SDValue Op1 = N1.getOperand(0);
21941 if (ShAmt0.getOpcode() == ISD::SUB) {
21942 Opc = X86ISD::SHRD;
21943 std::swap(Op0, Op1);
21944 std::swap(ShAmt0, ShAmt1);
21947 unsigned Bits = VT.getSizeInBits();
21948 if (ShAmt1.getOpcode() == ISD::SUB) {
21949 SDValue Sum = ShAmt1.getOperand(0);
21950 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21951 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21952 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21953 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21954 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21955 return DAG.getNode(Opc, DL, VT,
21957 DAG.getNode(ISD::TRUNCATE, DL,
21960 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21961 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21963 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21964 return DAG.getNode(Opc, DL, VT,
21965 N0.getOperand(0), N1.getOperand(0),
21966 DAG.getNode(ISD::TRUNCATE, DL,
21973 // Generate NEG and CMOV for integer abs.
21974 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21975 EVT VT = N->getValueType(0);
21977 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21978 // 8-bit integer abs to NEG and CMOV.
21979 if (VT.isInteger() && VT.getSizeInBits() == 8)
21982 SDValue N0 = N->getOperand(0);
21983 SDValue N1 = N->getOperand(1);
21986 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21987 // and change it to SUB and CMOV.
21988 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21989 N0.getOpcode() == ISD::ADD &&
21990 N0.getOperand(1) == N1 &&
21991 N1.getOpcode() == ISD::SRA &&
21992 N1.getOperand(0) == N0.getOperand(0))
21993 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21994 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21995 // Generate SUB & CMOV.
21996 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21997 DAG.getConstant(0, VT), N0.getOperand(0));
21999 SDValue Ops[] = { N0.getOperand(0), Neg,
22000 DAG.getConstant(X86::COND_GE, MVT::i8),
22001 SDValue(Neg.getNode(), 1) };
22002 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22007 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22008 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22009 TargetLowering::DAGCombinerInfo &DCI,
22010 const X86Subtarget *Subtarget) {
22011 if (DCI.isBeforeLegalizeOps())
22014 if (Subtarget->hasCMov()) {
22015 SDValue RV = performIntegerAbsCombine(N, DAG);
22023 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22024 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22025 TargetLowering::DAGCombinerInfo &DCI,
22026 const X86Subtarget *Subtarget) {
22027 LoadSDNode *Ld = cast<LoadSDNode>(N);
22028 EVT RegVT = Ld->getValueType(0);
22029 EVT MemVT = Ld->getMemoryVT();
22031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22033 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22034 // into two 16-byte operations.
22035 ISD::LoadExtType Ext = Ld->getExtensionType();
22036 unsigned Alignment = Ld->getAlignment();
22037 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22038 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22039 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22040 unsigned NumElems = RegVT.getVectorNumElements();
22044 SDValue Ptr = Ld->getBasePtr();
22045 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22047 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22049 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22050 Ld->getPointerInfo(), Ld->isVolatile(),
22051 Ld->isNonTemporal(), Ld->isInvariant(),
22053 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22054 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22055 Ld->getPointerInfo(), Ld->isVolatile(),
22056 Ld->isNonTemporal(), Ld->isInvariant(),
22057 std::min(16U, Alignment));
22058 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22060 Load2.getValue(1));
22062 SDValue NewVec = DAG.getUNDEF(RegVT);
22063 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22064 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22065 return DCI.CombineTo(N, NewVec, TF, true);
22071 /// PerformMLOADCombine - Resolve extending loads
22072 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22073 TargetLowering::DAGCombinerInfo &DCI,
22074 const X86Subtarget *Subtarget) {
22075 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22076 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22079 EVT VT = Mld->getValueType(0);
22080 unsigned NumElems = VT.getVectorNumElements();
22081 EVT LdVT = Mld->getMemoryVT();
22084 assert(LdVT != VT && "Cannot extend to the same type");
22085 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22086 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22087 // From, To sizes and ElemCount must be pow of two
22088 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22089 "Unexpected size for extending masked load");
22091 unsigned SizeRatio = ToSz / FromSz;
22092 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22094 // Create a type on which we perform the shuffle
22095 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22096 LdVT.getScalarType(), NumElems*SizeRatio);
22097 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22099 // Convert Src0 value
22100 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22101 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22102 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22103 for (unsigned i = 0; i != NumElems; ++i)
22104 ShuffleVec[i] = i * SizeRatio;
22106 // Can't shuffle using an illegal type.
22107 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22108 && "WideVecVT should be legal");
22109 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22110 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22112 // Prepare the new mask
22114 SDValue Mask = Mld->getMask();
22115 if (Mask.getValueType() == VT) {
22116 // Mask and original value have the same type
22117 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22118 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22119 for (unsigned i = 0; i != NumElems; ++i)
22120 ShuffleVec[i] = i * SizeRatio;
22121 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22122 ShuffleVec[i] = NumElems*SizeRatio;
22123 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22124 DAG.getConstant(0, WideVecVT),
22128 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22129 unsigned WidenNumElts = NumElems*SizeRatio;
22130 unsigned MaskNumElts = VT.getVectorNumElements();
22131 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22134 unsigned NumConcat = WidenNumElts / MaskNumElts;
22135 SmallVector<SDValue, 16> Ops(NumConcat);
22136 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22138 for (unsigned i = 1; i != NumConcat; ++i)
22141 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22144 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22145 Mld->getBasePtr(), NewMask, WideSrc0,
22146 Mld->getMemoryVT(), Mld->getMemOperand(),
22148 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22149 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22152 /// PerformMSTORECombine - Resolve truncating stores
22153 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22154 const X86Subtarget *Subtarget) {
22155 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22156 if (!Mst->isTruncatingStore())
22159 EVT VT = Mst->getValue().getValueType();
22160 unsigned NumElems = VT.getVectorNumElements();
22161 EVT StVT = Mst->getMemoryVT();
22164 assert(StVT != VT && "Cannot truncate to the same type");
22165 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22166 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22168 // From, To sizes and ElemCount must be pow of two
22169 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22170 "Unexpected size for truncating masked store");
22171 // We are going to use the original vector elt for storing.
22172 // Accumulated smaller vector elements must be a multiple of the store size.
22173 assert (((NumElems * FromSz) % ToSz) == 0 &&
22174 "Unexpected ratio for truncating masked store");
22176 unsigned SizeRatio = FromSz / ToSz;
22177 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22179 // Create a type on which we perform the shuffle
22180 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22181 StVT.getScalarType(), NumElems*SizeRatio);
22183 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22185 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
22186 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22187 for (unsigned i = 0; i != NumElems; ++i)
22188 ShuffleVec[i] = i * SizeRatio;
22190 // Can't shuffle using an illegal type.
22191 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22192 && "WideVecVT should be legal");
22194 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22195 DAG.getUNDEF(WideVecVT),
22199 SDValue Mask = Mst->getMask();
22200 if (Mask.getValueType() == VT) {
22201 // Mask and original value have the same type
22202 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22203 for (unsigned i = 0; i != NumElems; ++i)
22204 ShuffleVec[i] = i * SizeRatio;
22205 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22206 ShuffleVec[i] = NumElems*SizeRatio;
22207 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22208 DAG.getConstant(0, WideVecVT),
22212 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22213 unsigned WidenNumElts = NumElems*SizeRatio;
22214 unsigned MaskNumElts = VT.getVectorNumElements();
22215 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22218 unsigned NumConcat = WidenNumElts / MaskNumElts;
22219 SmallVector<SDValue, 16> Ops(NumConcat);
22220 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22222 for (unsigned i = 1; i != NumConcat; ++i)
22225 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22228 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
22229 NewMask, StVT, Mst->getMemOperand(), false);
22231 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22232 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22233 const X86Subtarget *Subtarget) {
22234 StoreSDNode *St = cast<StoreSDNode>(N);
22235 EVT VT = St->getValue().getValueType();
22236 EVT StVT = St->getMemoryVT();
22238 SDValue StoredVal = St->getOperand(1);
22239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22241 // If we are saving a concatenation of two XMM registers and 32-byte stores
22242 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
22243 unsigned Alignment = St->getAlignment();
22244 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22245 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22246 StVT == VT && !IsAligned) {
22247 unsigned NumElems = VT.getVectorNumElements();
22251 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22252 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22254 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22255 SDValue Ptr0 = St->getBasePtr();
22256 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22258 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22259 St->getPointerInfo(), St->isVolatile(),
22260 St->isNonTemporal(), Alignment);
22261 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22262 St->getPointerInfo(), St->isVolatile(),
22263 St->isNonTemporal(),
22264 std::min(16U, Alignment));
22265 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22268 // Optimize trunc store (of multiple scalars) to shuffle and store.
22269 // First, pack all of the elements in one place. Next, store to memory
22270 // in fewer chunks.
22271 if (St->isTruncatingStore() && VT.isVector()) {
22272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22273 unsigned NumElems = VT.getVectorNumElements();
22274 assert(StVT != VT && "Cannot truncate to the same type");
22275 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22276 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22278 // From, To sizes and ElemCount must be pow of two
22279 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22280 // We are going to use the original vector elt for storing.
22281 // Accumulated smaller vector elements must be a multiple of the store size.
22282 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22284 unsigned SizeRatio = FromSz / ToSz;
22286 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22288 // Create a type on which we perform the shuffle
22289 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22290 StVT.getScalarType(), NumElems*SizeRatio);
22292 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22294 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22295 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22296 for (unsigned i = 0; i != NumElems; ++i)
22297 ShuffleVec[i] = i * SizeRatio;
22299 // Can't shuffle using an illegal type.
22300 if (!TLI.isTypeLegal(WideVecVT))
22303 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22304 DAG.getUNDEF(WideVecVT),
22306 // At this point all of the data is stored at the bottom of the
22307 // register. We now need to save it to mem.
22309 // Find the largest store unit
22310 MVT StoreType = MVT::i8;
22311 for (MVT Tp : MVT::integer_valuetypes()) {
22312 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22316 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22317 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22318 (64 <= NumElems * ToSz))
22319 StoreType = MVT::f64;
22321 // Bitcast the original vector into a vector of store-size units
22322 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22323 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22324 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22325 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22326 SmallVector<SDValue, 8> Chains;
22327 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22328 TLI.getPointerTy());
22329 SDValue Ptr = St->getBasePtr();
22331 // Perform one or more big stores into memory.
22332 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22333 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22334 StoreType, ShuffWide,
22335 DAG.getIntPtrConstant(i));
22336 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22337 St->getPointerInfo(), St->isVolatile(),
22338 St->isNonTemporal(), St->getAlignment());
22339 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22340 Chains.push_back(Ch);
22343 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22346 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22347 // the FP state in cases where an emms may be missing.
22348 // A preferable solution to the general problem is to figure out the right
22349 // places to insert EMMS. This qualifies as a quick hack.
22351 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22352 if (VT.getSizeInBits() != 64)
22355 const Function *F = DAG.getMachineFunction().getFunction();
22356 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
22357 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22358 && Subtarget->hasSSE2();
22359 if ((VT.isVector() ||
22360 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22361 isa<LoadSDNode>(St->getValue()) &&
22362 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22363 St->getChain().hasOneUse() && !St->isVolatile()) {
22364 SDNode* LdVal = St->getValue().getNode();
22365 LoadSDNode *Ld = nullptr;
22366 int TokenFactorIndex = -1;
22367 SmallVector<SDValue, 8> Ops;
22368 SDNode* ChainVal = St->getChain().getNode();
22369 // Must be a store of a load. We currently handle two cases: the load
22370 // is a direct child, and it's under an intervening TokenFactor. It is
22371 // possible to dig deeper under nested TokenFactors.
22372 if (ChainVal == LdVal)
22373 Ld = cast<LoadSDNode>(St->getChain());
22374 else if (St->getValue().hasOneUse() &&
22375 ChainVal->getOpcode() == ISD::TokenFactor) {
22376 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22377 if (ChainVal->getOperand(i).getNode() == LdVal) {
22378 TokenFactorIndex = i;
22379 Ld = cast<LoadSDNode>(St->getValue());
22381 Ops.push_back(ChainVal->getOperand(i));
22385 if (!Ld || !ISD::isNormalLoad(Ld))
22388 // If this is not the MMX case, i.e. we are just turning i64 load/store
22389 // into f64 load/store, avoid the transformation if there are multiple
22390 // uses of the loaded value.
22391 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22396 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22397 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22399 if (Subtarget->is64Bit() || F64IsLegal) {
22400 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22401 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22402 Ld->getPointerInfo(), Ld->isVolatile(),
22403 Ld->isNonTemporal(), Ld->isInvariant(),
22404 Ld->getAlignment());
22405 SDValue NewChain = NewLd.getValue(1);
22406 if (TokenFactorIndex != -1) {
22407 Ops.push_back(NewChain);
22408 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22410 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22411 St->getPointerInfo(),
22412 St->isVolatile(), St->isNonTemporal(),
22413 St->getAlignment());
22416 // Otherwise, lower to two pairs of 32-bit loads / stores.
22417 SDValue LoAddr = Ld->getBasePtr();
22418 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22419 DAG.getConstant(4, MVT::i32));
22421 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22422 Ld->getPointerInfo(),
22423 Ld->isVolatile(), Ld->isNonTemporal(),
22424 Ld->isInvariant(), Ld->getAlignment());
22425 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22426 Ld->getPointerInfo().getWithOffset(4),
22427 Ld->isVolatile(), Ld->isNonTemporal(),
22429 MinAlign(Ld->getAlignment(), 4));
22431 SDValue NewChain = LoLd.getValue(1);
22432 if (TokenFactorIndex != -1) {
22433 Ops.push_back(LoLd);
22434 Ops.push_back(HiLd);
22435 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22438 LoAddr = St->getBasePtr();
22439 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22440 DAG.getConstant(4, MVT::i32));
22442 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22443 St->getPointerInfo(),
22444 St->isVolatile(), St->isNonTemporal(),
22445 St->getAlignment());
22446 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22447 St->getPointerInfo().getWithOffset(4),
22449 St->isNonTemporal(),
22450 MinAlign(St->getAlignment(), 4));
22451 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22456 /// Return 'true' if this vector operation is "horizontal"
22457 /// and return the operands for the horizontal operation in LHS and RHS. A
22458 /// horizontal operation performs the binary operation on successive elements
22459 /// of its first operand, then on successive elements of its second operand,
22460 /// returning the resulting values in a vector. For example, if
22461 /// A = < float a0, float a1, float a2, float a3 >
22463 /// B = < float b0, float b1, float b2, float b3 >
22464 /// then the result of doing a horizontal operation on A and B is
22465 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22466 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22467 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22468 /// set to A, RHS to B, and the routine returns 'true'.
22469 /// Note that the binary operation should have the property that if one of the
22470 /// operands is UNDEF then the result is UNDEF.
22471 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22472 // Look for the following pattern: if
22473 // A = < float a0, float a1, float a2, float a3 >
22474 // B = < float b0, float b1, float b2, float b3 >
22476 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22477 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22478 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22479 // which is A horizontal-op B.
22481 // At least one of the operands should be a vector shuffle.
22482 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22483 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22486 MVT VT = LHS.getSimpleValueType();
22488 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22489 "Unsupported vector type for horizontal add/sub");
22491 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22492 // operate independently on 128-bit lanes.
22493 unsigned NumElts = VT.getVectorNumElements();
22494 unsigned NumLanes = VT.getSizeInBits()/128;
22495 unsigned NumLaneElts = NumElts / NumLanes;
22496 assert((NumLaneElts % 2 == 0) &&
22497 "Vector type should have an even number of elements in each lane");
22498 unsigned HalfLaneElts = NumLaneElts/2;
22500 // View LHS in the form
22501 // LHS = VECTOR_SHUFFLE A, B, LMask
22502 // If LHS is not a shuffle then pretend it is the shuffle
22503 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22504 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22507 SmallVector<int, 16> LMask(NumElts);
22508 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22509 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22510 A = LHS.getOperand(0);
22511 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22512 B = LHS.getOperand(1);
22513 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22514 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22516 if (LHS.getOpcode() != ISD::UNDEF)
22518 for (unsigned i = 0; i != NumElts; ++i)
22522 // Likewise, view RHS in the form
22523 // RHS = VECTOR_SHUFFLE C, D, RMask
22525 SmallVector<int, 16> RMask(NumElts);
22526 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22527 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22528 C = RHS.getOperand(0);
22529 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22530 D = RHS.getOperand(1);
22531 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22532 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22534 if (RHS.getOpcode() != ISD::UNDEF)
22536 for (unsigned i = 0; i != NumElts; ++i)
22540 // Check that the shuffles are both shuffling the same vectors.
22541 if (!(A == C && B == D) && !(A == D && B == C))
22544 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22545 if (!A.getNode() && !B.getNode())
22548 // If A and B occur in reverse order in RHS, then "swap" them (which means
22549 // rewriting the mask).
22551 CommuteVectorShuffleMask(RMask, NumElts);
22553 // At this point LHS and RHS are equivalent to
22554 // LHS = VECTOR_SHUFFLE A, B, LMask
22555 // RHS = VECTOR_SHUFFLE A, B, RMask
22556 // Check that the masks correspond to performing a horizontal operation.
22557 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22558 for (unsigned i = 0; i != NumLaneElts; ++i) {
22559 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22561 // Ignore any UNDEF components.
22562 if (LIdx < 0 || RIdx < 0 ||
22563 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22564 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22567 // Check that successive elements are being operated on. If not, this is
22568 // not a horizontal operation.
22569 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22570 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22571 if (!(LIdx == Index && RIdx == Index + 1) &&
22572 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22577 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22578 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22582 /// Do target-specific dag combines on floating point adds.
22583 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22584 const X86Subtarget *Subtarget) {
22585 EVT VT = N->getValueType(0);
22586 SDValue LHS = N->getOperand(0);
22587 SDValue RHS = N->getOperand(1);
22589 // Try to synthesize horizontal adds from adds of shuffles.
22590 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22591 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22592 isHorizontalBinOp(LHS, RHS, true))
22593 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22597 /// Do target-specific dag combines on floating point subs.
22598 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22599 const X86Subtarget *Subtarget) {
22600 EVT VT = N->getValueType(0);
22601 SDValue LHS = N->getOperand(0);
22602 SDValue RHS = N->getOperand(1);
22604 // Try to synthesize horizontal subs from subs of shuffles.
22605 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22606 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22607 isHorizontalBinOp(LHS, RHS, false))
22608 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22612 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
22613 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22614 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22616 // F[X]OR(0.0, x) -> x
22617 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22618 if (C->getValueAPF().isPosZero())
22619 return N->getOperand(1);
22621 // F[X]OR(x, 0.0) -> x
22622 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22623 if (C->getValueAPF().isPosZero())
22624 return N->getOperand(0);
22628 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
22629 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22630 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22632 // Only perform optimizations if UnsafeMath is used.
22633 if (!DAG.getTarget().Options.UnsafeFPMath)
22636 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22637 // into FMINC and FMAXC, which are Commutative operations.
22638 unsigned NewOp = 0;
22639 switch (N->getOpcode()) {
22640 default: llvm_unreachable("unknown opcode");
22641 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22642 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22645 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22646 N->getOperand(0), N->getOperand(1));
22649 /// Do target-specific dag combines on X86ISD::FAND nodes.
22650 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22651 // FAND(0.0, x) -> 0.0
22652 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22653 if (C->getValueAPF().isPosZero())
22654 return N->getOperand(0);
22656 // FAND(x, 0.0) -> 0.0
22657 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22658 if (C->getValueAPF().isPosZero())
22659 return N->getOperand(1);
22664 /// Do target-specific dag combines on X86ISD::FANDN nodes
22665 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22666 // FANDN(0.0, x) -> x
22667 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22668 if (C->getValueAPF().isPosZero())
22669 return N->getOperand(1);
22671 // FANDN(x, 0.0) -> 0.0
22672 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22673 if (C->getValueAPF().isPosZero())
22674 return N->getOperand(1);
22679 static SDValue PerformBTCombine(SDNode *N,
22681 TargetLowering::DAGCombinerInfo &DCI) {
22682 // BT ignores high bits in the bit index operand.
22683 SDValue Op1 = N->getOperand(1);
22684 if (Op1.hasOneUse()) {
22685 unsigned BitWidth = Op1.getValueSizeInBits();
22686 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22687 APInt KnownZero, KnownOne;
22688 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22689 !DCI.isBeforeLegalizeOps());
22690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22691 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22692 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22693 DCI.CommitTargetLoweringOpt(TLO);
22698 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22699 SDValue Op = N->getOperand(0);
22700 if (Op.getOpcode() == ISD::BITCAST)
22701 Op = Op.getOperand(0);
22702 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22703 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22704 VT.getVectorElementType().getSizeInBits() ==
22705 OpVT.getVectorElementType().getSizeInBits()) {
22706 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22711 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22712 const X86Subtarget *Subtarget) {
22713 EVT VT = N->getValueType(0);
22714 if (!VT.isVector())
22717 SDValue N0 = N->getOperand(0);
22718 SDValue N1 = N->getOperand(1);
22719 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22722 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22723 // both SSE and AVX2 since there is no sign-extended shift right
22724 // operation on a vector with 64-bit elements.
22725 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22726 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22727 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22728 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22729 SDValue N00 = N0.getOperand(0);
22731 // EXTLOAD has a better solution on AVX2,
22732 // it may be replaced with X86ISD::VSEXT node.
22733 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22734 if (!ISD::isNormalLoad(N00.getNode()))
22737 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22738 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22740 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22746 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22747 TargetLowering::DAGCombinerInfo &DCI,
22748 const X86Subtarget *Subtarget) {
22749 SDValue N0 = N->getOperand(0);
22750 EVT VT = N->getValueType(0);
22752 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
22753 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
22754 // This exposes the sext to the sdivrem lowering, so that it directly extends
22755 // from AH (which we otherwise need to do contortions to access).
22756 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
22757 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
22759 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
22760 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
22761 N0.getOperand(0), N0.getOperand(1));
22762 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
22763 return R.getValue(1);
22766 if (!DCI.isBeforeLegalizeOps())
22769 if (!Subtarget->hasFp256())
22772 if (VT.isVector() && VT.getSizeInBits() == 256) {
22773 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22781 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22782 const X86Subtarget* Subtarget) {
22784 EVT VT = N->getValueType(0);
22786 // Let legalize expand this if it isn't a legal type yet.
22787 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22790 EVT ScalarVT = VT.getScalarType();
22791 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22792 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22795 SDValue A = N->getOperand(0);
22796 SDValue B = N->getOperand(1);
22797 SDValue C = N->getOperand(2);
22799 bool NegA = (A.getOpcode() == ISD::FNEG);
22800 bool NegB = (B.getOpcode() == ISD::FNEG);
22801 bool NegC = (C.getOpcode() == ISD::FNEG);
22803 // Negative multiplication when NegA xor NegB
22804 bool NegMul = (NegA != NegB);
22806 A = A.getOperand(0);
22808 B = B.getOperand(0);
22810 C = C.getOperand(0);
22814 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22816 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22818 return DAG.getNode(Opcode, dl, VT, A, B, C);
22821 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22822 TargetLowering::DAGCombinerInfo &DCI,
22823 const X86Subtarget *Subtarget) {
22824 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22825 // (and (i32 x86isd::setcc_carry), 1)
22826 // This eliminates the zext. This transformation is necessary because
22827 // ISD::SETCC is always legalized to i8.
22829 SDValue N0 = N->getOperand(0);
22830 EVT VT = N->getValueType(0);
22832 if (N0.getOpcode() == ISD::AND &&
22834 N0.getOperand(0).hasOneUse()) {
22835 SDValue N00 = N0.getOperand(0);
22836 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22837 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22838 if (!C || C->getZExtValue() != 1)
22840 return DAG.getNode(ISD::AND, dl, VT,
22841 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22842 N00.getOperand(0), N00.getOperand(1)),
22843 DAG.getConstant(1, VT));
22847 if (N0.getOpcode() == ISD::TRUNCATE &&
22849 N0.getOperand(0).hasOneUse()) {
22850 SDValue N00 = N0.getOperand(0);
22851 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22852 return DAG.getNode(ISD::AND, dl, VT,
22853 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22854 N00.getOperand(0), N00.getOperand(1)),
22855 DAG.getConstant(1, VT));
22858 if (VT.is256BitVector()) {
22859 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22864 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
22865 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
22866 // This exposes the zext to the udivrem lowering, so that it directly extends
22867 // from AH (which we otherwise need to do contortions to access).
22868 if (N0.getOpcode() == ISD::UDIVREM &&
22869 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
22870 (VT == MVT::i32 || VT == MVT::i64)) {
22871 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
22872 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
22873 N0.getOperand(0), N0.getOperand(1));
22874 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
22875 return R.getValue(1);
22881 // Optimize x == -y --> x+y == 0
22882 // x != -y --> x+y != 0
22883 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22884 const X86Subtarget* Subtarget) {
22885 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22886 SDValue LHS = N->getOperand(0);
22887 SDValue RHS = N->getOperand(1);
22888 EVT VT = N->getValueType(0);
22891 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22893 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22894 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22895 LHS.getValueType(), RHS, LHS.getOperand(1));
22896 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22897 addV, DAG.getConstant(0, addV.getValueType()), CC);
22899 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22901 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22902 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22903 RHS.getValueType(), LHS, RHS.getOperand(1));
22904 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22905 addV, DAG.getConstant(0, addV.getValueType()), CC);
22908 if (VT.getScalarType() == MVT::i1) {
22909 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22910 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22911 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22912 if (!IsSEXT0 && !IsVZero0)
22914 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22915 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22916 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22918 if (!IsSEXT1 && !IsVZero1)
22921 if (IsSEXT0 && IsVZero1) {
22922 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22923 if (CC == ISD::SETEQ)
22924 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22925 return LHS.getOperand(0);
22927 if (IsSEXT1 && IsVZero0) {
22928 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22929 if (CC == ISD::SETEQ)
22930 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22931 return RHS.getOperand(0);
22938 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
22939 SelectionDAG &DAG) {
22941 MVT VT = Load->getSimpleValueType(0);
22942 MVT EVT = VT.getVectorElementType();
22943 SDValue Addr = Load->getOperand(1);
22944 SDValue NewAddr = DAG.getNode(
22945 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
22946 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
22949 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
22950 DAG.getMachineFunction().getMachineMemOperand(
22951 Load->getMemOperand(), 0, EVT.getStoreSize()));
22955 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22956 const X86Subtarget *Subtarget) {
22958 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22959 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22960 "X86insertps is only defined for v4x32");
22962 SDValue Ld = N->getOperand(1);
22963 if (MayFoldLoad(Ld)) {
22964 // Extract the countS bits from the immediate so we can get the proper
22965 // address when narrowing the vector load to a specific element.
22966 // When the second source op is a memory address, insertps doesn't use
22967 // countS and just gets an f32 from that address.
22968 unsigned DestIndex =
22969 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22971 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22973 // Create this as a scalar to vector to match the instruction pattern.
22974 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22975 // countS bits are ignored when loading from memory on insertps, which
22976 // means we don't need to explicitly set them to 0.
22977 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22978 LoadScalarToVector, N->getOperand(2));
22983 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
22984 SDValue V0 = N->getOperand(0);
22985 SDValue V1 = N->getOperand(1);
22987 EVT VT = N->getValueType(0);
22989 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
22990 // operands and changing the mask to 1. This saves us a bunch of
22991 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
22992 // x86InstrInfo knows how to commute this back after instruction selection
22993 // if it would help register allocation.
22995 // TODO: If optimizing for size or a processor that doesn't suffer from
22996 // partial register update stalls, this should be transformed into a MOVSD
22997 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
22999 if (VT == MVT::v2f64)
23000 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23001 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23002 SDValue NewMask = DAG.getConstant(1, MVT::i8);
23003 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23009 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23010 // as "sbb reg,reg", since it can be extended without zext and produces
23011 // an all-ones bit which is more useful than 0/1 in some cases.
23012 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23015 return DAG.getNode(ISD::AND, DL, VT,
23016 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23017 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23018 DAG.getConstant(1, VT));
23019 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23020 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23021 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23022 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23025 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23026 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23027 TargetLowering::DAGCombinerInfo &DCI,
23028 const X86Subtarget *Subtarget) {
23030 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23031 SDValue EFLAGS = N->getOperand(1);
23033 if (CC == X86::COND_A) {
23034 // Try to convert COND_A into COND_B in an attempt to facilitate
23035 // materializing "setb reg".
23037 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23038 // cannot take an immediate as its first operand.
23040 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23041 EFLAGS.getValueType().isInteger() &&
23042 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23043 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23044 EFLAGS.getNode()->getVTList(),
23045 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23046 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23047 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23051 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23052 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23054 if (CC == X86::COND_B)
23055 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23059 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23060 if (Flags.getNode()) {
23061 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23062 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23068 // Optimize branch condition evaluation.
23070 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23071 TargetLowering::DAGCombinerInfo &DCI,
23072 const X86Subtarget *Subtarget) {
23074 SDValue Chain = N->getOperand(0);
23075 SDValue Dest = N->getOperand(1);
23076 SDValue EFLAGS = N->getOperand(3);
23077 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23081 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23082 if (Flags.getNode()) {
23083 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23084 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23091 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23092 SelectionDAG &DAG) {
23093 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23094 // optimize away operation when it's from a constant.
23096 // The general transformation is:
23097 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23098 // AND(VECTOR_CMP(x,y), constant2)
23099 // constant2 = UNARYOP(constant)
23101 // Early exit if this isn't a vector operation, the operand of the
23102 // unary operation isn't a bitwise AND, or if the sizes of the operations
23103 // aren't the same.
23104 EVT VT = N->getValueType(0);
23105 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23106 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23107 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23110 // Now check that the other operand of the AND is a constant. We could
23111 // make the transformation for non-constant splats as well, but it's unclear
23112 // that would be a benefit as it would not eliminate any operations, just
23113 // perform one more step in scalar code before moving to the vector unit.
23114 if (BuildVectorSDNode *BV =
23115 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23116 // Bail out if the vector isn't a constant.
23117 if (!BV->isConstant())
23120 // Everything checks out. Build up the new and improved node.
23122 EVT IntVT = BV->getValueType(0);
23123 // Create a new constant of the appropriate type for the transformed
23125 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23126 // The AND node needs bitcasts to/from an integer vector type around it.
23127 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23128 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23129 N->getOperand(0)->getOperand(0), MaskConst);
23130 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23137 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23138 const X86Subtarget *Subtarget) {
23139 // First try to optimize away the conversion entirely when it's
23140 // conditionally from a constant. Vectors only.
23141 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23142 if (Res != SDValue())
23145 // Now move on to more general possibilities.
23146 SDValue Op0 = N->getOperand(0);
23147 EVT InVT = Op0->getValueType(0);
23149 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23150 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23152 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23153 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23154 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23157 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23158 // a 32-bit target where SSE doesn't support i64->FP operations.
23159 if (Op0.getOpcode() == ISD::LOAD) {
23160 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23161 EVT VT = Ld->getValueType(0);
23162 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23163 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23164 !Subtarget->is64Bit() && VT == MVT::i64) {
23165 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
23166 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
23167 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23174 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23175 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23176 X86TargetLowering::DAGCombinerInfo &DCI) {
23177 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23178 // the result is either zero or one (depending on the input carry bit).
23179 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23180 if (X86::isZeroNode(N->getOperand(0)) &&
23181 X86::isZeroNode(N->getOperand(1)) &&
23182 // We don't have a good way to replace an EFLAGS use, so only do this when
23184 SDValue(N, 1).use_empty()) {
23186 EVT VT = N->getValueType(0);
23187 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23188 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23189 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23190 DAG.getConstant(X86::COND_B,MVT::i8),
23192 DAG.getConstant(1, VT));
23193 return DCI.CombineTo(N, Res1, CarryOut);
23199 // fold (add Y, (sete X, 0)) -> adc 0, Y
23200 // (add Y, (setne X, 0)) -> sbb -1, Y
23201 // (sub (sete X, 0), Y) -> sbb 0, Y
23202 // (sub (setne X, 0), Y) -> adc -1, Y
23203 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23206 // Look through ZExts.
23207 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23208 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23211 SDValue SetCC = Ext.getOperand(0);
23212 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23215 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23216 if (CC != X86::COND_E && CC != X86::COND_NE)
23219 SDValue Cmp = SetCC.getOperand(1);
23220 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23221 !X86::isZeroNode(Cmp.getOperand(1)) ||
23222 !Cmp.getOperand(0).getValueType().isInteger())
23225 SDValue CmpOp0 = Cmp.getOperand(0);
23226 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23227 DAG.getConstant(1, CmpOp0.getValueType()));
23229 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23230 if (CC == X86::COND_NE)
23231 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23232 DL, OtherVal.getValueType(), OtherVal,
23233 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23234 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23235 DL, OtherVal.getValueType(), OtherVal,
23236 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23239 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23240 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23241 const X86Subtarget *Subtarget) {
23242 EVT VT = N->getValueType(0);
23243 SDValue Op0 = N->getOperand(0);
23244 SDValue Op1 = N->getOperand(1);
23246 // Try to synthesize horizontal adds from adds of shuffles.
23247 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23248 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23249 isHorizontalBinOp(Op0, Op1, true))
23250 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23252 return OptimizeConditionalInDecrement(N, DAG);
23255 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23256 const X86Subtarget *Subtarget) {
23257 SDValue Op0 = N->getOperand(0);
23258 SDValue Op1 = N->getOperand(1);
23260 // X86 can't encode an immediate LHS of a sub. See if we can push the
23261 // negation into a preceding instruction.
23262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23263 // If the RHS of the sub is a XOR with one use and a constant, invert the
23264 // immediate. Then add one to the LHS of the sub so we can turn
23265 // X-Y -> X+~Y+1, saving one register.
23266 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23267 isa<ConstantSDNode>(Op1.getOperand(1))) {
23268 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23269 EVT VT = Op0.getValueType();
23270 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23272 DAG.getConstant(~XorC, VT));
23273 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23274 DAG.getConstant(C->getAPIntValue()+1, VT));
23278 // Try to synthesize horizontal adds from adds of shuffles.
23279 EVT VT = N->getValueType(0);
23280 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23281 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23282 isHorizontalBinOp(Op0, Op1, true))
23283 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23285 return OptimizeConditionalInDecrement(N, DAG);
23288 /// performVZEXTCombine - Performs build vector combines
23289 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23290 TargetLowering::DAGCombinerInfo &DCI,
23291 const X86Subtarget *Subtarget) {
23293 MVT VT = N->getSimpleValueType(0);
23294 SDValue Op = N->getOperand(0);
23295 MVT OpVT = Op.getSimpleValueType();
23296 MVT OpEltVT = OpVT.getVectorElementType();
23297 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
23299 // (vzext (bitcast (vzext (x)) -> (vzext x)
23301 while (V.getOpcode() == ISD::BITCAST)
23302 V = V.getOperand(0);
23304 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
23305 MVT InnerVT = V.getSimpleValueType();
23306 MVT InnerEltVT = InnerVT.getVectorElementType();
23308 // If the element sizes match exactly, we can just do one larger vzext. This
23309 // is always an exact type match as vzext operates on integer types.
23310 if (OpEltVT == InnerEltVT) {
23311 assert(OpVT == InnerVT && "Types must match for vzext!");
23312 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
23315 // The only other way we can combine them is if only a single element of the
23316 // inner vzext is used in the input to the outer vzext.
23317 if (InnerEltVT.getSizeInBits() < InputBits)
23320 // In this case, the inner vzext is completely dead because we're going to
23321 // only look at bits inside of the low element. Just do the outer vzext on
23322 // a bitcast of the input to the inner.
23323 return DAG.getNode(X86ISD::VZEXT, DL, VT,
23324 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
23327 // Check if we can bypass extracting and re-inserting an element of an input
23328 // vector. Essentialy:
23329 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
23330 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23331 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
23332 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
23333 SDValue ExtractedV = V.getOperand(0);
23334 SDValue OrigV = ExtractedV.getOperand(0);
23335 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
23336 if (ExtractIdx->getZExtValue() == 0) {
23337 MVT OrigVT = OrigV.getSimpleValueType();
23338 // Extract a subvector if necessary...
23339 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
23340 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
23341 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
23342 OrigVT.getVectorNumElements() / Ratio);
23343 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
23344 DAG.getIntPtrConstant(0));
23346 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
23347 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
23354 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23355 DAGCombinerInfo &DCI) const {
23356 SelectionDAG &DAG = DCI.DAG;
23357 switch (N->getOpcode()) {
23359 case ISD::EXTRACT_VECTOR_ELT:
23360 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23363 case X86ISD::SHRUNKBLEND:
23364 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23365 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
23366 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23367 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23368 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23369 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23370 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23373 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23374 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23375 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23376 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23377 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23378 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
23379 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23380 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
23381 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
23382 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23383 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23385 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23387 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23388 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23389 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23390 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23391 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23392 case ISD::ANY_EXTEND:
23393 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23394 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23395 case ISD::SIGN_EXTEND_INREG:
23396 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23397 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23398 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23399 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23400 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23401 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23402 case X86ISD::SHUFP: // Handle all target specific shuffles
23403 case X86ISD::PALIGNR:
23404 case X86ISD::UNPCKH:
23405 case X86ISD::UNPCKL:
23406 case X86ISD::MOVHLPS:
23407 case X86ISD::MOVLHPS:
23408 case X86ISD::PSHUFB:
23409 case X86ISD::PSHUFD:
23410 case X86ISD::PSHUFHW:
23411 case X86ISD::PSHUFLW:
23412 case X86ISD::MOVSS:
23413 case X86ISD::MOVSD:
23414 case X86ISD::VPERMILPI:
23415 case X86ISD::VPERM2X128:
23416 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23417 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23418 case ISD::INTRINSIC_WO_CHAIN:
23419 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23420 case X86ISD::INSERTPS: {
23421 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
23422 return PerformINSERTPSCombine(N, DAG, Subtarget);
23425 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
23426 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23432 /// isTypeDesirableForOp - Return true if the target has native support for
23433 /// the specified value type and it is 'desirable' to use the type for the
23434 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23435 /// instruction encodings are longer and some i16 instructions are slow.
23436 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23437 if (!isTypeLegal(VT))
23439 if (VT != MVT::i16)
23446 case ISD::SIGN_EXTEND:
23447 case ISD::ZERO_EXTEND:
23448 case ISD::ANY_EXTEND:
23461 /// IsDesirableToPromoteOp - This method query the target whether it is
23462 /// beneficial for dag combiner to promote the specified node. If true, it
23463 /// should return the desired promotion type by reference.
23464 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23465 EVT VT = Op.getValueType();
23466 if (VT != MVT::i16)
23469 bool Promote = false;
23470 bool Commute = false;
23471 switch (Op.getOpcode()) {
23474 LoadSDNode *LD = cast<LoadSDNode>(Op);
23475 // If the non-extending load has a single use and it's not live out, then it
23476 // might be folded.
23477 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23478 Op.hasOneUse()*/) {
23479 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23480 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23481 // The only case where we'd want to promote LOAD (rather then it being
23482 // promoted as an operand is when it's only use is liveout.
23483 if (UI->getOpcode() != ISD::CopyToReg)
23490 case ISD::SIGN_EXTEND:
23491 case ISD::ZERO_EXTEND:
23492 case ISD::ANY_EXTEND:
23497 SDValue N0 = Op.getOperand(0);
23498 // Look out for (store (shl (load), x)).
23499 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23512 SDValue N0 = Op.getOperand(0);
23513 SDValue N1 = Op.getOperand(1);
23514 if (!Commute && MayFoldLoad(N1))
23516 // Avoid disabling potential load folding opportunities.
23517 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23519 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23529 //===----------------------------------------------------------------------===//
23530 // X86 Inline Assembly Support
23531 //===----------------------------------------------------------------------===//
23534 // Helper to match a string separated by whitespace.
23535 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23536 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23538 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23539 StringRef piece(*args[i]);
23540 if (!s.startswith(piece)) // Check if the piece matches.
23543 s = s.substr(piece.size());
23544 StringRef::size_type pos = s.find_first_not_of(" \t");
23545 if (pos == 0) // We matched a prefix.
23553 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23556 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23558 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23559 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23560 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23561 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23563 if (AsmPieces.size() == 3)
23565 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23572 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23573 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23575 std::string AsmStr = IA->getAsmString();
23577 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23578 if (!Ty || Ty->getBitWidth() % 16 != 0)
23581 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23582 SmallVector<StringRef, 4> AsmPieces;
23583 SplitString(AsmStr, AsmPieces, ";\n");
23585 switch (AsmPieces.size()) {
23586 default: return false;
23588 // FIXME: this should verify that we are targeting a 486 or better. If not,
23589 // we will turn this bswap into something that will be lowered to logical
23590 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23591 // lower so don't worry about this.
23593 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23594 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23595 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23596 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23597 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23598 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23599 // No need to check constraints, nothing other than the equivalent of
23600 // "=r,0" would be valid here.
23601 return IntrinsicLowering::LowerToByteSwap(CI);
23604 // rorw $$8, ${0:w} --> llvm.bswap.i16
23605 if (CI->getType()->isIntegerTy(16) &&
23606 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23607 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23608 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23610 const std::string &ConstraintsStr = IA->getConstraintString();
23611 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23612 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23613 if (clobbersFlagRegisters(AsmPieces))
23614 return IntrinsicLowering::LowerToByteSwap(CI);
23618 if (CI->getType()->isIntegerTy(32) &&
23619 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23620 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23621 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23622 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23624 const std::string &ConstraintsStr = IA->getConstraintString();
23625 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23626 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23627 if (clobbersFlagRegisters(AsmPieces))
23628 return IntrinsicLowering::LowerToByteSwap(CI);
23631 if (CI->getType()->isIntegerTy(64)) {
23632 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23633 if (Constraints.size() >= 2 &&
23634 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23635 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23636 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23637 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23638 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23639 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23640 return IntrinsicLowering::LowerToByteSwap(CI);
23648 /// getConstraintType - Given a constraint letter, return the type of
23649 /// constraint it is for this target.
23650 X86TargetLowering::ConstraintType
23651 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23652 if (Constraint.size() == 1) {
23653 switch (Constraint[0]) {
23664 return C_RegisterClass;
23688 return TargetLowering::getConstraintType(Constraint);
23691 /// Examine constraint type and operand type and determine a weight value.
23692 /// This object must already have been set up with the operand type
23693 /// and the current alternative constraint selected.
23694 TargetLowering::ConstraintWeight
23695 X86TargetLowering::getSingleConstraintMatchWeight(
23696 AsmOperandInfo &info, const char *constraint) const {
23697 ConstraintWeight weight = CW_Invalid;
23698 Value *CallOperandVal = info.CallOperandVal;
23699 // If we don't have a value, we can't do a match,
23700 // but allow it at the lowest weight.
23701 if (!CallOperandVal)
23703 Type *type = CallOperandVal->getType();
23704 // Look at the constraint type.
23705 switch (*constraint) {
23707 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23718 if (CallOperandVal->getType()->isIntegerTy())
23719 weight = CW_SpecificReg;
23724 if (type->isFloatingPointTy())
23725 weight = CW_SpecificReg;
23728 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23729 weight = CW_SpecificReg;
23733 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23734 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23735 weight = CW_Register;
23738 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23739 if (C->getZExtValue() <= 31)
23740 weight = CW_Constant;
23744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23745 if (C->getZExtValue() <= 63)
23746 weight = CW_Constant;
23750 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23751 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23752 weight = CW_Constant;
23756 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23757 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23758 weight = CW_Constant;
23762 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23763 if (C->getZExtValue() <= 3)
23764 weight = CW_Constant;
23768 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23769 if (C->getZExtValue() <= 0xff)
23770 weight = CW_Constant;
23775 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23776 weight = CW_Constant;
23780 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23781 if ((C->getSExtValue() >= -0x80000000LL) &&
23782 (C->getSExtValue() <= 0x7fffffffLL))
23783 weight = CW_Constant;
23787 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23788 if (C->getZExtValue() <= 0xffffffff)
23789 weight = CW_Constant;
23796 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23797 /// with another that has more specific requirements based on the type of the
23798 /// corresponding operand.
23799 const char *X86TargetLowering::
23800 LowerXConstraint(EVT ConstraintVT) const {
23801 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23802 // 'f' like normal targets.
23803 if (ConstraintVT.isFloatingPoint()) {
23804 if (Subtarget->hasSSE2())
23806 if (Subtarget->hasSSE1())
23810 return TargetLowering::LowerXConstraint(ConstraintVT);
23813 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23814 /// vector. If it is invalid, don't add anything to Ops.
23815 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23816 std::string &Constraint,
23817 std::vector<SDValue>&Ops,
23818 SelectionDAG &DAG) const {
23821 // Only support length 1 constraints for now.
23822 if (Constraint.length() > 1) return;
23824 char ConstraintLetter = Constraint[0];
23825 switch (ConstraintLetter) {
23828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23829 if (C->getZExtValue() <= 31) {
23830 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23836 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23837 if (C->getZExtValue() <= 63) {
23838 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23844 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23845 if (isInt<8>(C->getSExtValue())) {
23846 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23853 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
23854 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
23855 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
23861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23862 if (C->getZExtValue() <= 3) {
23863 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23869 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23870 if (C->getZExtValue() <= 255) {
23871 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23878 if (C->getZExtValue() <= 127) {
23879 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23885 // 32-bit signed value
23886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23887 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23888 C->getSExtValue())) {
23889 // Widen to 64 bits here to get it sign extended.
23890 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23893 // FIXME gcc accepts some relocatable values here too, but only in certain
23894 // memory models; it's complicated.
23899 // 32-bit unsigned value
23900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23901 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23902 C->getZExtValue())) {
23903 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23907 // FIXME gcc accepts some relocatable values here too, but only in certain
23908 // memory models; it's complicated.
23912 // Literal immediates are always ok.
23913 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23914 // Widen to 64 bits here to get it sign extended.
23915 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23919 // In any sort of PIC mode addresses need to be computed at runtime by
23920 // adding in a register or some sort of table lookup. These can't
23921 // be used as immediates.
23922 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23925 // If we are in non-pic codegen mode, we allow the address of a global (with
23926 // an optional displacement) to be used with 'i'.
23927 GlobalAddressSDNode *GA = nullptr;
23928 int64_t Offset = 0;
23930 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23932 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23933 Offset += GA->getOffset();
23935 } else if (Op.getOpcode() == ISD::ADD) {
23936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23937 Offset += C->getZExtValue();
23938 Op = Op.getOperand(0);
23941 } else if (Op.getOpcode() == ISD::SUB) {
23942 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23943 Offset += -C->getZExtValue();
23944 Op = Op.getOperand(0);
23949 // Otherwise, this isn't something we can handle, reject it.
23953 const GlobalValue *GV = GA->getGlobal();
23954 // If we require an extra load to get this address, as in PIC mode, we
23955 // can't accept it.
23956 if (isGlobalStubReference(
23957 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23960 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23961 GA->getValueType(0), Offset);
23966 if (Result.getNode()) {
23967 Ops.push_back(Result);
23970 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23973 std::pair<unsigned, const TargetRegisterClass *>
23974 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
23975 const std::string &Constraint,
23977 // First, see if this is a constraint that directly corresponds to an LLVM
23979 if (Constraint.size() == 1) {
23980 // GCC Constraint Letters
23981 switch (Constraint[0]) {
23983 // TODO: Slight differences here in allocation order and leaving
23984 // RIP in the class. Do they matter any more here than they do
23985 // in the normal allocation?
23986 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23987 if (Subtarget->is64Bit()) {
23988 if (VT == MVT::i32 || VT == MVT::f32)
23989 return std::make_pair(0U, &X86::GR32RegClass);
23990 if (VT == MVT::i16)
23991 return std::make_pair(0U, &X86::GR16RegClass);
23992 if (VT == MVT::i8 || VT == MVT::i1)
23993 return std::make_pair(0U, &X86::GR8RegClass);
23994 if (VT == MVT::i64 || VT == MVT::f64)
23995 return std::make_pair(0U, &X86::GR64RegClass);
23998 // 32-bit fallthrough
23999 case 'Q': // Q_REGS
24000 if (VT == MVT::i32 || VT == MVT::f32)
24001 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24002 if (VT == MVT::i16)
24003 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24004 if (VT == MVT::i8 || VT == MVT::i1)
24005 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24006 if (VT == MVT::i64)
24007 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24009 case 'r': // GENERAL_REGS
24010 case 'l': // INDEX_REGS
24011 if (VT == MVT::i8 || VT == MVT::i1)
24012 return std::make_pair(0U, &X86::GR8RegClass);
24013 if (VT == MVT::i16)
24014 return std::make_pair(0U, &X86::GR16RegClass);
24015 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24016 return std::make_pair(0U, &X86::GR32RegClass);
24017 return std::make_pair(0U, &X86::GR64RegClass);
24018 case 'R': // LEGACY_REGS
24019 if (VT == MVT::i8 || VT == MVT::i1)
24020 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24021 if (VT == MVT::i16)
24022 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24023 if (VT == MVT::i32 || !Subtarget->is64Bit())
24024 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24025 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24026 case 'f': // FP Stack registers.
24027 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24028 // value to the correct fpstack register class.
24029 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24030 return std::make_pair(0U, &X86::RFP32RegClass);
24031 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24032 return std::make_pair(0U, &X86::RFP64RegClass);
24033 return std::make_pair(0U, &X86::RFP80RegClass);
24034 case 'y': // MMX_REGS if MMX allowed.
24035 if (!Subtarget->hasMMX()) break;
24036 return std::make_pair(0U, &X86::VR64RegClass);
24037 case 'Y': // SSE_REGS if SSE2 allowed
24038 if (!Subtarget->hasSSE2()) break;
24040 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24041 if (!Subtarget->hasSSE1()) break;
24043 switch (VT.SimpleTy) {
24045 // Scalar SSE types.
24048 return std::make_pair(0U, &X86::FR32RegClass);
24051 return std::make_pair(0U, &X86::FR64RegClass);
24059 return std::make_pair(0U, &X86::VR128RegClass);
24067 return std::make_pair(0U, &X86::VR256RegClass);
24072 return std::make_pair(0U, &X86::VR512RegClass);
24078 // Use the default implementation in TargetLowering to convert the register
24079 // constraint into a member of a register class.
24080 std::pair<unsigned, const TargetRegisterClass*> Res;
24081 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24083 // Not found as a standard register?
24085 // Map st(0) -> st(7) -> ST0
24086 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24087 tolower(Constraint[1]) == 's' &&
24088 tolower(Constraint[2]) == 't' &&
24089 Constraint[3] == '(' &&
24090 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24091 Constraint[5] == ')' &&
24092 Constraint[6] == '}') {
24094 Res.first = X86::FP0+Constraint[4]-'0';
24095 Res.second = &X86::RFP80RegClass;
24099 // GCC allows "st(0)" to be called just plain "st".
24100 if (StringRef("{st}").equals_lower(Constraint)) {
24101 Res.first = X86::FP0;
24102 Res.second = &X86::RFP80RegClass;
24107 if (StringRef("{flags}").equals_lower(Constraint)) {
24108 Res.first = X86::EFLAGS;
24109 Res.second = &X86::CCRRegClass;
24113 // 'A' means EAX + EDX.
24114 if (Constraint == "A") {
24115 Res.first = X86::EAX;
24116 Res.second = &X86::GR32_ADRegClass;
24122 // Otherwise, check to see if this is a register class of the wrong value
24123 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24124 // turn into {ax},{dx}.
24125 if (Res.second->hasType(VT))
24126 return Res; // Correct type already, nothing to do.
24128 // All of the single-register GCC register classes map their values onto
24129 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24130 // really want an 8-bit or 32-bit register, map to the appropriate register
24131 // class and return the appropriate register.
24132 if (Res.second == &X86::GR16RegClass) {
24133 if (VT == MVT::i8 || VT == MVT::i1) {
24134 unsigned DestReg = 0;
24135 switch (Res.first) {
24137 case X86::AX: DestReg = X86::AL; break;
24138 case X86::DX: DestReg = X86::DL; break;
24139 case X86::CX: DestReg = X86::CL; break;
24140 case X86::BX: DestReg = X86::BL; break;
24143 Res.first = DestReg;
24144 Res.second = &X86::GR8RegClass;
24146 } else if (VT == MVT::i32 || VT == MVT::f32) {
24147 unsigned DestReg = 0;
24148 switch (Res.first) {
24150 case X86::AX: DestReg = X86::EAX; break;
24151 case X86::DX: DestReg = X86::EDX; break;
24152 case X86::CX: DestReg = X86::ECX; break;
24153 case X86::BX: DestReg = X86::EBX; break;
24154 case X86::SI: DestReg = X86::ESI; break;
24155 case X86::DI: DestReg = X86::EDI; break;
24156 case X86::BP: DestReg = X86::EBP; break;
24157 case X86::SP: DestReg = X86::ESP; break;
24160 Res.first = DestReg;
24161 Res.second = &X86::GR32RegClass;
24163 } else if (VT == MVT::i64 || VT == MVT::f64) {
24164 unsigned DestReg = 0;
24165 switch (Res.first) {
24167 case X86::AX: DestReg = X86::RAX; break;
24168 case X86::DX: DestReg = X86::RDX; break;
24169 case X86::CX: DestReg = X86::RCX; break;
24170 case X86::BX: DestReg = X86::RBX; break;
24171 case X86::SI: DestReg = X86::RSI; break;
24172 case X86::DI: DestReg = X86::RDI; break;
24173 case X86::BP: DestReg = X86::RBP; break;
24174 case X86::SP: DestReg = X86::RSP; break;
24177 Res.first = DestReg;
24178 Res.second = &X86::GR64RegClass;
24181 } else if (Res.second == &X86::FR32RegClass ||
24182 Res.second == &X86::FR64RegClass ||
24183 Res.second == &X86::VR128RegClass ||
24184 Res.second == &X86::VR256RegClass ||
24185 Res.second == &X86::FR32XRegClass ||
24186 Res.second == &X86::FR64XRegClass ||
24187 Res.second == &X86::VR128XRegClass ||
24188 Res.second == &X86::VR256XRegClass ||
24189 Res.second == &X86::VR512RegClass) {
24190 // Handle references to XMM physical registers that got mapped into the
24191 // wrong class. This can happen with constraints like {xmm0} where the
24192 // target independent register mapper will just pick the first match it can
24193 // find, ignoring the required type.
24195 if (VT == MVT::f32 || VT == MVT::i32)
24196 Res.second = &X86::FR32RegClass;
24197 else if (VT == MVT::f64 || VT == MVT::i64)
24198 Res.second = &X86::FR64RegClass;
24199 else if (X86::VR128RegClass.hasType(VT))
24200 Res.second = &X86::VR128RegClass;
24201 else if (X86::VR256RegClass.hasType(VT))
24202 Res.second = &X86::VR256RegClass;
24203 else if (X86::VR512RegClass.hasType(VT))
24204 Res.second = &X86::VR512RegClass;
24210 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24212 // Scaling factors are not free at all.
24213 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24214 // will take 2 allocations in the out of order engine instead of 1
24215 // for plain addressing mode, i.e. inst (reg1).
24217 // vaddps (%rsi,%drx), %ymm0, %ymm1
24218 // Requires two allocations (one for the load, one for the computation)
24220 // vaddps (%rsi), %ymm0, %ymm1
24221 // Requires just 1 allocation, i.e., freeing allocations for other operations
24222 // and having less micro operations to execute.
24224 // For some X86 architectures, this is even worse because for instance for
24225 // stores, the complex addressing mode forces the instruction to use the
24226 // "load" ports instead of the dedicated "store" port.
24227 // E.g., on Haswell:
24228 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24229 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24230 if (isLegalAddressingMode(AM, Ty))
24231 // Scale represents reg2 * scale, thus account for 1
24232 // as soon as we use a second register.
24233 return AM.Scale != 0;
24237 bool X86TargetLowering::isTargetFTOL() const {
24238 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();