1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1611 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1612 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1613 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1614 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1615 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1616 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1617 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1618 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1619 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1620 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1621 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1622 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1623 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1624 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1625 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1629 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1630 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1631 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1632 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1633 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1634 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1635 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1636 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1638 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1639 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1640 if (Subtarget->hasVLX())
1641 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1643 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1644 const MVT VT = (MVT::SimpleValueType)i;
1646 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1648 // Do not attempt to promote non-512-bit vectors.
1649 if (!VT.is512BitVector())
1653 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1654 setOperationAction(ISD::VSELECT, VT, Legal);
1659 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1660 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1661 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1663 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1664 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1665 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1666 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1667 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1668 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1669 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1671 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1672 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1676 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1677 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1678 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1679 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1680 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1681 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1682 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1683 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1685 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1686 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1687 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1688 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1689 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1690 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1691 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1692 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1695 // We want to custom lower some of our intrinsics.
1696 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1697 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1698 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1699 if (!Subtarget->is64Bit())
1700 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1702 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1703 // handle type legalization for these operations here.
1705 // FIXME: We really should do custom legalization for addition and
1706 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1707 // than generic legalization for 64-bit multiplication-with-overflow, though.
1708 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1709 // Add/Sub/Mul with overflow operations are custom lowered.
1711 setOperationAction(ISD::SADDO, VT, Custom);
1712 setOperationAction(ISD::UADDO, VT, Custom);
1713 setOperationAction(ISD::SSUBO, VT, Custom);
1714 setOperationAction(ISD::USUBO, VT, Custom);
1715 setOperationAction(ISD::SMULO, VT, Custom);
1716 setOperationAction(ISD::UMULO, VT, Custom);
1719 if (!Subtarget->is64Bit()) {
1720 // These libcalls are not available in 32-bit.
1721 setLibcallName(RTLIB::SHL_I128, nullptr);
1722 setLibcallName(RTLIB::SRL_I128, nullptr);
1723 setLibcallName(RTLIB::SRA_I128, nullptr);
1726 // Combine sin / cos into one node or libcall if possible.
1727 if (Subtarget->hasSinCos()) {
1728 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1729 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1730 if (Subtarget->isTargetDarwin()) {
1731 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1732 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1734 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1738 if (Subtarget->isTargetWin64()) {
1739 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1740 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1741 setOperationAction(ISD::SREM, MVT::i128, Custom);
1742 setOperationAction(ISD::UREM, MVT::i128, Custom);
1743 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1744 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1747 // We have target-specific dag combine patterns for the following nodes:
1748 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1749 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1750 setTargetDAGCombine(ISD::BITCAST);
1751 setTargetDAGCombine(ISD::VSELECT);
1752 setTargetDAGCombine(ISD::SELECT);
1753 setTargetDAGCombine(ISD::SHL);
1754 setTargetDAGCombine(ISD::SRA);
1755 setTargetDAGCombine(ISD::SRL);
1756 setTargetDAGCombine(ISD::OR);
1757 setTargetDAGCombine(ISD::AND);
1758 setTargetDAGCombine(ISD::ADD);
1759 setTargetDAGCombine(ISD::FADD);
1760 setTargetDAGCombine(ISD::FSUB);
1761 setTargetDAGCombine(ISD::FMA);
1762 setTargetDAGCombine(ISD::SUB);
1763 setTargetDAGCombine(ISD::LOAD);
1764 setTargetDAGCombine(ISD::MLOAD);
1765 setTargetDAGCombine(ISD::STORE);
1766 setTargetDAGCombine(ISD::MSTORE);
1767 setTargetDAGCombine(ISD::ZERO_EXTEND);
1768 setTargetDAGCombine(ISD::ANY_EXTEND);
1769 setTargetDAGCombine(ISD::SIGN_EXTEND);
1770 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1771 setTargetDAGCombine(ISD::SINT_TO_FP);
1772 setTargetDAGCombine(ISD::UINT_TO_FP);
1773 setTargetDAGCombine(ISD::SETCC);
1774 setTargetDAGCombine(ISD::BUILD_VECTOR);
1775 setTargetDAGCombine(ISD::MUL);
1776 setTargetDAGCombine(ISD::XOR);
1778 computeRegisterProperties(Subtarget->getRegisterInfo());
1780 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1781 MaxStoresPerMemsetOptSize = 8;
1782 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1783 MaxStoresPerMemcpyOptSize = 4;
1784 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1785 MaxStoresPerMemmoveOptSize = 4;
1786 setPrefLoopAlignment(4); // 2^4 bytes.
1788 // Predictable cmov don't hurt on atom because it's in-order.
1789 PredictableSelectIsExpensive = !Subtarget->isAtom();
1790 EnableExtLdPromotion = true;
1791 setPrefFunctionAlignment(4); // 2^4 bytes.
1793 verifyIntrinsicTables();
1796 // This has so far only been implemented for 64-bit MachO.
1797 bool X86TargetLowering::useLoadStackGuardNode() const {
1798 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1801 TargetLoweringBase::LegalizeTypeAction
1802 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1803 if (ExperimentalVectorWideningLegalization &&
1804 VT.getVectorNumElements() != 1 &&
1805 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1806 return TypeWidenVector;
1808 return TargetLoweringBase::getPreferredVectorAction(VT);
1811 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1814 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1816 const unsigned NumElts = VT.getVectorNumElements();
1817 const EVT EltVT = VT.getVectorElementType();
1818 if (VT.is512BitVector()) {
1819 if (Subtarget->hasAVX512())
1820 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1821 EltVT == MVT::f32 || EltVT == MVT::f64)
1823 case 8: return MVT::v8i1;
1824 case 16: return MVT::v16i1;
1826 if (Subtarget->hasBWI())
1827 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1829 case 32: return MVT::v32i1;
1830 case 64: return MVT::v64i1;
1834 if (VT.is256BitVector() || VT.is128BitVector()) {
1835 if (Subtarget->hasVLX())
1836 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1837 EltVT == MVT::f32 || EltVT == MVT::f64)
1839 case 2: return MVT::v2i1;
1840 case 4: return MVT::v4i1;
1841 case 8: return MVT::v8i1;
1843 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1844 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1846 case 8: return MVT::v8i1;
1847 case 16: return MVT::v16i1;
1848 case 32: return MVT::v32i1;
1852 return VT.changeVectorElementTypeToInteger();
1855 /// Helper for getByValTypeAlignment to determine
1856 /// the desired ByVal argument alignment.
1857 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1860 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1861 if (VTy->getBitWidth() == 128)
1863 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1864 unsigned EltAlign = 0;
1865 getMaxByValAlign(ATy->getElementType(), EltAlign);
1866 if (EltAlign > MaxAlign)
1867 MaxAlign = EltAlign;
1868 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1869 for (auto *EltTy : STy->elements()) {
1870 unsigned EltAlign = 0;
1871 getMaxByValAlign(EltTy, EltAlign);
1872 if (EltAlign > MaxAlign)
1873 MaxAlign = EltAlign;
1880 /// Return the desired alignment for ByVal aggregate
1881 /// function arguments in the caller parameter area. For X86, aggregates
1882 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1883 /// are at 4-byte boundaries.
1884 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1885 const DataLayout &DL) const {
1886 if (Subtarget->is64Bit()) {
1887 // Max of 8 and alignment of type.
1888 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1895 if (Subtarget->hasSSE1())
1896 getMaxByValAlign(Ty, Align);
1900 /// Returns the target specific optimal type for load
1901 /// and store operations as a result of memset, memcpy, and memmove
1902 /// lowering. If DstAlign is zero that means it's safe to destination
1903 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1904 /// means there isn't a need to check it against alignment requirement,
1905 /// probably because the source does not need to be loaded. If 'IsMemset' is
1906 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1907 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1908 /// source is constant so it does not need to be loaded.
1909 /// It returns EVT::Other if the type should be determined using generic
1910 /// target-independent logic.
1912 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1913 unsigned DstAlign, unsigned SrcAlign,
1914 bool IsMemset, bool ZeroMemset,
1916 MachineFunction &MF) const {
1917 const Function *F = MF.getFunction();
1918 if ((!IsMemset || ZeroMemset) &&
1919 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1921 (!Subtarget->isUnalignedMem16Slow() ||
1922 ((DstAlign == 0 || DstAlign >= 16) &&
1923 (SrcAlign == 0 || SrcAlign >= 16)))) {
1925 // FIXME: Check if unaligned 32-byte accesses are slow.
1926 if (Subtarget->hasInt256())
1928 if (Subtarget->hasFp256())
1931 if (Subtarget->hasSSE2())
1933 if (Subtarget->hasSSE1())
1935 } else if (!MemcpyStrSrc && Size >= 8 &&
1936 !Subtarget->is64Bit() &&
1937 Subtarget->hasSSE2()) {
1938 // Do not use f64 to lower memcpy if source is string constant. It's
1939 // better to use i32 to avoid the loads.
1943 // This is a compromise. If we reach here, unaligned accesses may be slow on
1944 // this target. However, creating smaller, aligned accesses could be even
1945 // slower and would certainly be a lot more code.
1946 if (Subtarget->is64Bit() && Size >= 8)
1951 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1953 return X86ScalarSSEf32;
1954 else if (VT == MVT::f64)
1955 return X86ScalarSSEf64;
1960 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1965 switch (VT.getSizeInBits()) {
1967 // 8-byte and under are always assumed to be fast.
1971 *Fast = !Subtarget->isUnalignedMem16Slow();
1974 *Fast = !Subtarget->isUnalignedMem32Slow();
1976 // TODO: What about AVX-512 (512-bit) accesses?
1979 // Misaligned accesses of any size are always allowed.
1983 /// Return the entry encoding for a jump table in the
1984 /// current function. The returned value is a member of the
1985 /// MachineJumpTableInfo::JTEntryKind enum.
1986 unsigned X86TargetLowering::getJumpTableEncoding() const {
1987 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1989 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1990 Subtarget->isPICStyleGOT())
1991 return MachineJumpTableInfo::EK_Custom32;
1993 // Otherwise, use the normal jump table encoding heuristics.
1994 return TargetLowering::getJumpTableEncoding();
1997 bool X86TargetLowering::useSoftFloat() const {
1998 return Subtarget->useSoftFloat();
2002 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2003 const MachineBasicBlock *MBB,
2004 unsigned uid,MCContext &Ctx) const{
2005 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2006 Subtarget->isPICStyleGOT());
2007 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2009 return MCSymbolRefExpr::create(MBB->getSymbol(),
2010 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2013 /// Returns relocation base for the given PIC jumptable.
2014 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2015 SelectionDAG &DAG) const {
2016 if (!Subtarget->is64Bit())
2017 // This doesn't have SDLoc associated with it, but is not really the
2018 // same as a Register.
2019 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2020 getPointerTy(DAG.getDataLayout()));
2024 /// This returns the relocation base for the given PIC jumptable,
2025 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2026 const MCExpr *X86TargetLowering::
2027 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2028 MCContext &Ctx) const {
2029 // X86-64 uses RIP relative addressing based on the jump table label.
2030 if (Subtarget->isPICStyleRIPRel())
2031 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2033 // Otherwise, the reference is relative to the PIC base.
2034 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2037 std::pair<const TargetRegisterClass *, uint8_t>
2038 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2040 const TargetRegisterClass *RRC = nullptr;
2042 switch (VT.SimpleTy) {
2044 return TargetLowering::findRepresentativeClass(TRI, VT);
2045 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2046 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2049 RRC = &X86::VR64RegClass;
2051 case MVT::f32: case MVT::f64:
2052 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2053 case MVT::v4f32: case MVT::v2f64:
2054 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2056 RRC = &X86::VR128RegClass;
2059 return std::make_pair(RRC, Cost);
2062 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2063 unsigned &Offset) const {
2064 if (!Subtarget->isTargetLinux())
2067 if (Subtarget->is64Bit()) {
2068 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2070 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2082 /// Android provides a fixed TLS slot for the SafeStack pointer.
2083 /// See the definition of TLS_SLOT_SAFESTACK in
2084 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2085 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2086 unsigned &Offset) const {
2087 if (!Subtarget->isTargetAndroid())
2090 if (Subtarget->is64Bit()) {
2091 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2093 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2105 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2106 unsigned DestAS) const {
2107 assert(SrcAS != DestAS && "Expected different address spaces!");
2109 return SrcAS < 256 && DestAS < 256;
2112 //===----------------------------------------------------------------------===//
2113 // Return Value Calling Convention Implementation
2114 //===----------------------------------------------------------------------===//
2116 #include "X86GenCallingConv.inc"
2118 bool X86TargetLowering::CanLowerReturn(
2119 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2120 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2121 SmallVector<CCValAssign, 16> RVLocs;
2122 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2123 return CCInfo.CheckReturn(Outs, RetCC_X86);
2126 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2127 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2132 X86TargetLowering::LowerReturn(SDValue Chain,
2133 CallingConv::ID CallConv, bool isVarArg,
2134 const SmallVectorImpl<ISD::OutputArg> &Outs,
2135 const SmallVectorImpl<SDValue> &OutVals,
2136 SDLoc dl, SelectionDAG &DAG) const {
2137 MachineFunction &MF = DAG.getMachineFunction();
2138 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2140 SmallVector<CCValAssign, 16> RVLocs;
2141 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2142 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2145 SmallVector<SDValue, 6> RetOps;
2146 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2147 // Operand #1 = Bytes To Pop
2148 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2151 // Copy the result values into the output registers.
2152 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2153 CCValAssign &VA = RVLocs[i];
2154 assert(VA.isRegLoc() && "Can only return in registers!");
2155 SDValue ValToCopy = OutVals[i];
2156 EVT ValVT = ValToCopy.getValueType();
2158 // Promote values to the appropriate types.
2159 if (VA.getLocInfo() == CCValAssign::SExt)
2160 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2161 else if (VA.getLocInfo() == CCValAssign::ZExt)
2162 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2163 else if (VA.getLocInfo() == CCValAssign::AExt) {
2164 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2165 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2167 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2169 else if (VA.getLocInfo() == CCValAssign::BCvt)
2170 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2172 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2173 "Unexpected FP-extend for return value.");
2175 // If this is x86-64, and we disabled SSE, we can't return FP values,
2176 // or SSE or MMX vectors.
2177 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2178 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2179 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2180 report_fatal_error("SSE register return with SSE disabled");
2182 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2183 // llvm-gcc has never done it right and no one has noticed, so this
2184 // should be OK for now.
2185 if (ValVT == MVT::f64 &&
2186 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2187 report_fatal_error("SSE2 register return with SSE2 disabled");
2189 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2190 // the RET instruction and handled by the FP Stackifier.
2191 if (VA.getLocReg() == X86::FP0 ||
2192 VA.getLocReg() == X86::FP1) {
2193 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2194 // change the value to the FP stack register class.
2195 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2196 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2197 RetOps.push_back(ValToCopy);
2198 // Don't emit a copytoreg.
2202 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2203 // which is returned in RAX / RDX.
2204 if (Subtarget->is64Bit()) {
2205 if (ValVT == MVT::x86mmx) {
2206 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2207 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2208 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2210 // If we don't have SSE2 available, convert to v4f32 so the generated
2211 // register is legal.
2212 if (!Subtarget->hasSSE2())
2213 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2219 Flag = Chain.getValue(1);
2220 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2223 // All x86 ABIs require that for returning structs by value we copy
2224 // the sret argument into %rax/%eax (depending on ABI) for the return.
2225 // We saved the argument into a virtual register in the entry block,
2226 // so now we copy the value out and into %rax/%eax.
2228 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2229 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2230 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2231 // either case FuncInfo->setSRetReturnReg() will have been called.
2232 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2233 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2234 getPointerTy(MF.getDataLayout()));
2237 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2238 X86::RAX : X86::EAX;
2239 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2240 Flag = Chain.getValue(1);
2242 // RAX/EAX now acts like a return value.
2244 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2247 RetOps[0] = Chain; // Update chain.
2249 // Add the flag if we have it.
2251 RetOps.push_back(Flag);
2253 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2256 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2257 if (N->getNumValues() != 1)
2259 if (!N->hasNUsesOfValue(1, 0))
2262 SDValue TCChain = Chain;
2263 SDNode *Copy = *N->use_begin();
2264 if (Copy->getOpcode() == ISD::CopyToReg) {
2265 // If the copy has a glue operand, we conservatively assume it isn't safe to
2266 // perform a tail call.
2267 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2269 TCChain = Copy->getOperand(0);
2270 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2273 bool HasRet = false;
2274 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2276 if (UI->getOpcode() != X86ISD::RET_FLAG)
2278 // If we are returning more than one value, we can definitely
2279 // not make a tail call see PR19530
2280 if (UI->getNumOperands() > 4)
2282 if (UI->getNumOperands() == 4 &&
2283 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2296 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2297 ISD::NodeType ExtendKind) const {
2299 // TODO: Is this also valid on 32-bit?
2300 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2301 ReturnMVT = MVT::i8;
2303 ReturnMVT = MVT::i32;
2305 EVT MinVT = getRegisterType(Context, ReturnMVT);
2306 return VT.bitsLT(MinVT) ? MinVT : VT;
2309 /// Lower the result values of a call into the
2310 /// appropriate copies out of appropriate physical registers.
2313 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2314 CallingConv::ID CallConv, bool isVarArg,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 SmallVectorImpl<SDValue> &InVals) const {
2319 // Assign locations to each value returned by this call.
2320 SmallVector<CCValAssign, 16> RVLocs;
2321 bool Is64Bit = Subtarget->is64Bit();
2322 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2324 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2326 // Copy all of the result registers out of their specified physreg.
2327 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2328 CCValAssign &VA = RVLocs[i];
2329 EVT CopyVT = VA.getLocVT();
2331 // If this is x86-64, and we disabled SSE, we can't return FP values
2332 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2333 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2334 report_fatal_error("SSE register return with SSE disabled");
2337 // If we prefer to use the value in xmm registers, copy it out as f80 and
2338 // use a truncate to move it from fp stack reg to xmm reg.
2339 bool RoundAfterCopy = false;
2340 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2341 isScalarFPTypeInSSEReg(VA.getValVT())) {
2343 RoundAfterCopy = (CopyVT != VA.getLocVT());
2346 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2347 CopyVT, InFlag).getValue(1);
2348 SDValue Val = Chain.getValue(0);
2351 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2352 // This truncation won't change the value.
2353 DAG.getIntPtrConstant(1, dl));
2355 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2356 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2358 InFlag = Chain.getValue(2);
2359 InVals.push_back(Val);
2365 //===----------------------------------------------------------------------===//
2366 // C & StdCall & Fast Calling Convention implementation
2367 //===----------------------------------------------------------------------===//
2368 // StdCall calling convention seems to be standard for many Windows' API
2369 // routines and around. It differs from C calling convention just a little:
2370 // callee should clean up the stack, not caller. Symbols should be also
2371 // decorated in some fancy way :) It doesn't support any vector arguments.
2372 // For info on fast calling convention see Fast Calling Convention (tail call)
2373 // implementation LowerX86_32FastCCCallTo.
2375 /// CallIsStructReturn - Determines whether a call uses struct return
2377 enum StructReturnType {
2382 static StructReturnType
2383 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2385 return NotStructReturn;
2387 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2388 if (!Flags.isSRet())
2389 return NotStructReturn;
2390 if (Flags.isInReg())
2391 return RegStructReturn;
2392 return StackStructReturn;
2395 /// Determines whether a function uses struct return semantics.
2396 static StructReturnType
2397 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2399 return NotStructReturn;
2401 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2402 if (!Flags.isSRet())
2403 return NotStructReturn;
2404 if (Flags.isInReg())
2405 return RegStructReturn;
2406 return StackStructReturn;
2409 /// Make a copy of an aggregate at address specified by "Src" to address
2410 /// "Dst" with size and alignment information specified by the specific
2411 /// parameter attribute. The copy will be passed as a byval function parameter.
2413 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2414 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2416 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2418 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2419 /*isVolatile*/false, /*AlwaysInline=*/true,
2420 /*isTailCall*/false,
2421 MachinePointerInfo(), MachinePointerInfo());
2424 /// Return true if the calling convention is one that
2425 /// supports tail call optimization.
2426 static bool IsTailCallConvention(CallingConv::ID CC) {
2427 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2428 CC == CallingConv::HiPE);
2431 /// \brief Return true if the calling convention is a C calling convention.
2432 static bool IsCCallConvention(CallingConv::ID CC) {
2433 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2434 CC == CallingConv::X86_64_SysV);
2437 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2439 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2440 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2444 CallingConv::ID CalleeCC = CS.getCallingConv();
2445 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2451 /// Return true if the function is being made into
2452 /// a tailcall target by changing its ABI.
2453 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2454 bool GuaranteedTailCallOpt) {
2455 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2459 X86TargetLowering::LowerMemArgument(SDValue Chain,
2460 CallingConv::ID CallConv,
2461 const SmallVectorImpl<ISD::InputArg> &Ins,
2462 SDLoc dl, SelectionDAG &DAG,
2463 const CCValAssign &VA,
2464 MachineFrameInfo *MFI,
2466 // Create the nodes corresponding to a load from this parameter slot.
2467 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2468 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2469 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2470 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2473 // If value is passed by pointer we have address passed instead of the value
2475 bool ExtendedInMem = VA.isExtInLoc() &&
2476 VA.getValVT().getScalarType() == MVT::i1;
2478 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2479 ValVT = VA.getLocVT();
2481 ValVT = VA.getValVT();
2483 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2484 // changed with more analysis.
2485 // In case of tail call optimization mark all arguments mutable. Since they
2486 // could be overwritten by lowering of arguments in case of a tail call.
2487 if (Flags.isByVal()) {
2488 unsigned Bytes = Flags.getByValSize();
2489 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2490 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2491 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2493 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2494 VA.getLocMemOffset(), isImmutable);
2495 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2496 SDValue Val = DAG.getLoad(
2497 ValVT, dl, Chain, FIN,
2498 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2500 return ExtendedInMem ?
2501 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2505 // FIXME: Get this from tablegen.
2506 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2507 const X86Subtarget *Subtarget) {
2508 assert(Subtarget->is64Bit());
2510 if (Subtarget->isCallingConvWin64(CallConv)) {
2511 static const MCPhysReg GPR64ArgRegsWin64[] = {
2512 X86::RCX, X86::RDX, X86::R8, X86::R9
2514 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2517 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2518 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2520 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2523 // FIXME: Get this from tablegen.
2524 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2525 CallingConv::ID CallConv,
2526 const X86Subtarget *Subtarget) {
2527 assert(Subtarget->is64Bit());
2528 if (Subtarget->isCallingConvWin64(CallConv)) {
2529 // The XMM registers which might contain var arg parameters are shadowed
2530 // in their paired GPR. So we only need to save the GPR to their home
2532 // TODO: __vectorcall will change this.
2536 const Function *Fn = MF.getFunction();
2537 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2538 bool isSoftFloat = Subtarget->useSoftFloat();
2539 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2540 "SSE register cannot be used when SSE is disabled!");
2541 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2542 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2546 static const MCPhysReg XMMArgRegs64Bit[] = {
2547 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2548 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2550 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2553 SDValue X86TargetLowering::LowerFormalArguments(
2554 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2555 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2556 SmallVectorImpl<SDValue> &InVals) const {
2557 MachineFunction &MF = DAG.getMachineFunction();
2558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2559 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2561 const Function* Fn = MF.getFunction();
2562 if (Fn->hasExternalLinkage() &&
2563 Subtarget->isTargetCygMing() &&
2564 Fn->getName() == "main")
2565 FuncInfo->setForceFramePointer(true);
2567 MachineFrameInfo *MFI = MF.getFrameInfo();
2568 bool Is64Bit = Subtarget->is64Bit();
2569 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2571 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2572 "Var args not supported with calling convention fastcc, ghc or hipe");
2574 // Assign locations to all of the incoming arguments.
2575 SmallVector<CCValAssign, 16> ArgLocs;
2576 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2578 // Allocate shadow area for Win64
2580 CCInfo.AllocateStack(32, 8);
2582 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2584 unsigned LastVal = ~0U;
2586 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2587 CCValAssign &VA = ArgLocs[i];
2588 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2590 assert(VA.getValNo() != LastVal &&
2591 "Don't support value assigned to multiple locs yet");
2593 LastVal = VA.getValNo();
2595 if (VA.isRegLoc()) {
2596 EVT RegVT = VA.getLocVT();
2597 const TargetRegisterClass *RC;
2598 if (RegVT == MVT::i32)
2599 RC = &X86::GR32RegClass;
2600 else if (Is64Bit && RegVT == MVT::i64)
2601 RC = &X86::GR64RegClass;
2602 else if (RegVT == MVT::f32)
2603 RC = &X86::FR32RegClass;
2604 else if (RegVT == MVT::f64)
2605 RC = &X86::FR64RegClass;
2606 else if (RegVT.is512BitVector())
2607 RC = &X86::VR512RegClass;
2608 else if (RegVT.is256BitVector())
2609 RC = &X86::VR256RegClass;
2610 else if (RegVT.is128BitVector())
2611 RC = &X86::VR128RegClass;
2612 else if (RegVT == MVT::x86mmx)
2613 RC = &X86::VR64RegClass;
2614 else if (RegVT == MVT::i1)
2615 RC = &X86::VK1RegClass;
2616 else if (RegVT == MVT::v8i1)
2617 RC = &X86::VK8RegClass;
2618 else if (RegVT == MVT::v16i1)
2619 RC = &X86::VK16RegClass;
2620 else if (RegVT == MVT::v32i1)
2621 RC = &X86::VK32RegClass;
2622 else if (RegVT == MVT::v64i1)
2623 RC = &X86::VK64RegClass;
2625 llvm_unreachable("Unknown argument type!");
2627 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2628 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2630 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2631 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2633 if (VA.getLocInfo() == CCValAssign::SExt)
2634 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2635 DAG.getValueType(VA.getValVT()));
2636 else if (VA.getLocInfo() == CCValAssign::ZExt)
2637 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2638 DAG.getValueType(VA.getValVT()));
2639 else if (VA.getLocInfo() == CCValAssign::BCvt)
2640 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2642 if (VA.isExtInLoc()) {
2643 // Handle MMX values passed in XMM regs.
2644 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2645 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2647 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2650 assert(VA.isMemLoc());
2651 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2654 // If value is passed via pointer - do a load.
2655 if (VA.getLocInfo() == CCValAssign::Indirect)
2656 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2657 MachinePointerInfo(), false, false, false, 0);
2659 InVals.push_back(ArgValue);
2662 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2663 // All x86 ABIs require that for returning structs by value we copy the
2664 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2665 // the argument into a virtual register so that we can access it from the
2667 if (Ins[i].Flags.isSRet()) {
2668 unsigned Reg = FuncInfo->getSRetReturnReg();
2670 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2671 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2672 FuncInfo->setSRetReturnReg(Reg);
2674 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2675 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2680 unsigned StackSize = CCInfo.getNextStackOffset();
2681 // Align stack specially for tail calls.
2682 if (FuncIsMadeTailCallSafe(CallConv,
2683 MF.getTarget().Options.GuaranteedTailCallOpt))
2684 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2686 // If the function takes variable number of arguments, make a frame index for
2687 // the start of the first vararg value... for expansion of llvm.va_start. We
2688 // can skip this if there are no va_start calls.
2689 if (MFI->hasVAStart() &&
2690 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2691 CallConv != CallingConv::X86_ThisCall))) {
2692 FuncInfo->setVarArgsFrameIndex(
2693 MFI->CreateFixedObject(1, StackSize, true));
2696 MachineModuleInfo &MMI = MF.getMMI();
2697 const Function *WinEHParent = nullptr;
2698 if (MMI.hasWinEHFuncInfo(Fn))
2699 WinEHParent = MMI.getWinEHParent(Fn);
2700 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2702 // Figure out if XMM registers are in use.
2703 assert(!(Subtarget->useSoftFloat() &&
2704 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2705 "SSE register cannot be used when SSE is disabled!");
2707 // 64-bit calling conventions support varargs and register parameters, so we
2708 // have to do extra work to spill them in the prologue.
2709 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2710 // Find the first unallocated argument registers.
2711 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2712 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2713 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2714 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2715 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2716 "SSE register cannot be used when SSE is disabled!");
2718 // Gather all the live in physical registers.
2719 SmallVector<SDValue, 6> LiveGPRs;
2720 SmallVector<SDValue, 8> LiveXMMRegs;
2722 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2723 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2725 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2727 if (!ArgXMMs.empty()) {
2728 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2729 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2730 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2731 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2732 LiveXMMRegs.push_back(
2733 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2738 // Get to the caller-allocated home save location. Add 8 to account
2739 // for the return address.
2740 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2741 FuncInfo->setRegSaveFrameIndex(
2742 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2743 // Fixup to set vararg frame on shadow area (4 x i64).
2745 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2747 // For X86-64, if there are vararg parameters that are passed via
2748 // registers, then we must store them to their spots on the stack so
2749 // they may be loaded by deferencing the result of va_next.
2750 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2751 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2752 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2753 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2756 // Store the integer parameter registers.
2757 SmallVector<SDValue, 8> MemOps;
2758 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2759 getPointerTy(DAG.getDataLayout()));
2760 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2761 for (SDValue Val : LiveGPRs) {
2762 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2763 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2765 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2766 MachinePointerInfo::getFixedStack(
2767 DAG.getMachineFunction(),
2768 FuncInfo->getRegSaveFrameIndex(), Offset),
2770 MemOps.push_back(Store);
2774 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2775 // Now store the XMM (fp + vector) parameter registers.
2776 SmallVector<SDValue, 12> SaveXMMOps;
2777 SaveXMMOps.push_back(Chain);
2778 SaveXMMOps.push_back(ALVal);
2779 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2780 FuncInfo->getRegSaveFrameIndex(), dl));
2781 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2782 FuncInfo->getVarArgsFPOffset(), dl));
2783 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2785 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2786 MVT::Other, SaveXMMOps));
2789 if (!MemOps.empty())
2790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2793 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2794 // Find the largest legal vector type.
2795 MVT VecVT = MVT::Other;
2796 // FIXME: Only some x86_32 calling conventions support AVX512.
2797 if (Subtarget->hasAVX512() &&
2798 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2799 CallConv == CallingConv::Intel_OCL_BI)))
2800 VecVT = MVT::v16f32;
2801 else if (Subtarget->hasAVX())
2803 else if (Subtarget->hasSSE2())
2806 // We forward some GPRs and some vector types.
2807 SmallVector<MVT, 2> RegParmTypes;
2808 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2809 RegParmTypes.push_back(IntVT);
2810 if (VecVT != MVT::Other)
2811 RegParmTypes.push_back(VecVT);
2813 // Compute the set of forwarded registers. The rest are scratch.
2814 SmallVectorImpl<ForwardedRegister> &Forwards =
2815 FuncInfo->getForwardedMustTailRegParms();
2816 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2818 // Conservatively forward AL on x86_64, since it might be used for varargs.
2819 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2820 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2821 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2824 // Copy all forwards from physical to virtual registers.
2825 for (ForwardedRegister &F : Forwards) {
2826 // FIXME: Can we use a less constrained schedule?
2827 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2828 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2829 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2833 // Some CCs need callee pop.
2834 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2835 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2836 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2838 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2839 // If this is an sret function, the return should pop the hidden pointer.
2840 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2841 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2842 argsAreStructReturn(Ins) == StackStructReturn)
2843 FuncInfo->setBytesToPopOnReturn(4);
2847 // RegSaveFrameIndex is X86-64 only.
2848 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2849 if (CallConv == CallingConv::X86_FastCall ||
2850 CallConv == CallingConv::X86_ThisCall)
2851 // fastcc functions can't have varargs.
2852 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2855 FuncInfo->setArgumentStackSize(StackSize);
2857 if (IsWinEHParent) {
2859 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2860 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2861 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2862 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2863 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2864 MachinePointerInfo::getFixedStack(
2865 DAG.getMachineFunction(), UnwindHelpFI),
2866 /*isVolatile=*/true,
2867 /*isNonTemporal=*/false, /*Alignment=*/0);
2869 // Functions using Win32 EH are considered to have opaque SP adjustments
2870 // to force local variables to be addressed from the frame or base
2872 MFI->setHasOpaqueSPAdjustment(true);
2880 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2881 SDValue StackPtr, SDValue Arg,
2882 SDLoc dl, SelectionDAG &DAG,
2883 const CCValAssign &VA,
2884 ISD::ArgFlagsTy Flags) const {
2885 unsigned LocMemOffset = VA.getLocMemOffset();
2886 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2887 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2889 if (Flags.isByVal())
2890 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2892 return DAG.getStore(
2893 Chain, dl, Arg, PtrOff,
2894 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2898 /// Emit a load of return address if tail call
2899 /// optimization is performed and it is required.
2901 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2902 SDValue &OutRetAddr, SDValue Chain,
2903 bool IsTailCall, bool Is64Bit,
2904 int FPDiff, SDLoc dl) const {
2905 // Adjust the Return address stack slot.
2906 EVT VT = getPointerTy(DAG.getDataLayout());
2907 OutRetAddr = getReturnAddressFrameIndex(DAG);
2909 // Load the "old" Return address.
2910 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2911 false, false, false, 0);
2912 return SDValue(OutRetAddr.getNode(), 1);
2915 /// Emit a store of the return address if tail call
2916 /// optimization is performed and it is required (FPDiff!=0).
2917 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2918 SDValue Chain, SDValue RetAddrFrIdx,
2919 EVT PtrVT, unsigned SlotSize,
2920 int FPDiff, SDLoc dl) {
2921 // Store the return address to the appropriate stack slot.
2922 if (!FPDiff) return Chain;
2923 // Calculate the new stack slot for the return address.
2924 int NewReturnAddrFI =
2925 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2927 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2928 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2929 MachinePointerInfo::getFixedStack(
2930 DAG.getMachineFunction(), NewReturnAddrFI),
2935 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2936 /// operation of specified width.
2937 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2939 unsigned NumElems = VT.getVectorNumElements();
2940 SmallVector<int, 8> Mask;
2941 Mask.push_back(NumElems);
2942 for (unsigned i = 1; i != NumElems; ++i)
2944 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2948 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2949 SmallVectorImpl<SDValue> &InVals) const {
2950 SelectionDAG &DAG = CLI.DAG;
2952 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2953 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2954 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2955 SDValue Chain = CLI.Chain;
2956 SDValue Callee = CLI.Callee;
2957 CallingConv::ID CallConv = CLI.CallConv;
2958 bool &isTailCall = CLI.IsTailCall;
2959 bool isVarArg = CLI.IsVarArg;
2961 MachineFunction &MF = DAG.getMachineFunction();
2962 bool Is64Bit = Subtarget->is64Bit();
2963 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2964 StructReturnType SR = callIsStructReturn(Outs);
2965 bool IsSibcall = false;
2966 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2967 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2969 if (Attr.getValueAsString() == "true")
2972 if (Subtarget->isPICStyleGOT() &&
2973 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2974 // If we are using a GOT, disable tail calls to external symbols with
2975 // default visibility. Tail calling such a symbol requires using a GOT
2976 // relocation, which forces early binding of the symbol. This breaks code
2977 // that require lazy function symbol resolution. Using musttail or
2978 // GuaranteedTailCallOpt will override this.
2979 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2980 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2981 G->getGlobal()->hasDefaultVisibility()))
2985 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2987 // Force this to be a tail call. The verifier rules are enough to ensure
2988 // that we can lower this successfully without moving the return address
2991 } else if (isTailCall) {
2992 // Check if it's really possible to do a tail call.
2993 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2994 isVarArg, SR != NotStructReturn,
2995 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2996 Outs, OutVals, Ins, DAG);
2998 // Sibcalls are automatically detected tailcalls which do not require
3000 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3007 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3008 "Var args not supported with calling convention fastcc, ghc or hipe");
3010 // Analyze operands of the call, assigning locations to each operand.
3011 SmallVector<CCValAssign, 16> ArgLocs;
3012 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3014 // Allocate shadow area for Win64
3016 CCInfo.AllocateStack(32, 8);
3018 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3020 // Get a count of how many bytes are to be pushed on the stack.
3021 unsigned NumBytes = CCInfo.getNextStackOffset();
3023 // This is a sibcall. The memory operands are available in caller's
3024 // own caller's stack.
3026 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3027 IsTailCallConvention(CallConv))
3028 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3031 if (isTailCall && !IsSibcall && !IsMustTail) {
3032 // Lower arguments at fp - stackoffset + fpdiff.
3033 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3035 FPDiff = NumBytesCallerPushed - NumBytes;
3037 // Set the delta of movement of the returnaddr stackslot.
3038 // But only set if delta is greater than previous delta.
3039 if (FPDiff < X86Info->getTCReturnAddrDelta())
3040 X86Info->setTCReturnAddrDelta(FPDiff);
3043 unsigned NumBytesToPush = NumBytes;
3044 unsigned NumBytesToPop = NumBytes;
3046 // If we have an inalloca argument, all stack space has already been allocated
3047 // for us and be right at the top of the stack. We don't support multiple
3048 // arguments passed in memory when using inalloca.
3049 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3051 if (!ArgLocs.back().isMemLoc())
3052 report_fatal_error("cannot use inalloca attribute on a register "
3054 if (ArgLocs.back().getLocMemOffset() != 0)
3055 report_fatal_error("any parameter with the inalloca attribute must be "
3056 "the only memory argument");
3060 Chain = DAG.getCALLSEQ_START(
3061 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3063 SDValue RetAddrFrIdx;
3064 // Load return address for tail calls.
3065 if (isTailCall && FPDiff)
3066 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3067 Is64Bit, FPDiff, dl);
3069 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3070 SmallVector<SDValue, 8> MemOpChains;
3073 // Walk the register/memloc assignments, inserting copies/loads. In the case
3074 // of tail call optimization arguments are handle later.
3075 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3076 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3077 // Skip inalloca arguments, they have already been written.
3078 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3079 if (Flags.isInAlloca())
3082 CCValAssign &VA = ArgLocs[i];
3083 EVT RegVT = VA.getLocVT();
3084 SDValue Arg = OutVals[i];
3085 bool isByVal = Flags.isByVal();
3087 // Promote the value if needed.
3088 switch (VA.getLocInfo()) {
3089 default: llvm_unreachable("Unknown loc info!");
3090 case CCValAssign::Full: break;
3091 case CCValAssign::SExt:
3092 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3094 case CCValAssign::ZExt:
3095 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3097 case CCValAssign::AExt:
3098 if (Arg.getValueType().isVector() &&
3099 Arg.getValueType().getScalarType() == MVT::i1)
3100 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3101 else if (RegVT.is128BitVector()) {
3102 // Special case: passing MMX values in XMM registers.
3103 Arg = DAG.getBitcast(MVT::i64, Arg);
3104 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3105 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3107 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3109 case CCValAssign::BCvt:
3110 Arg = DAG.getBitcast(RegVT, Arg);
3112 case CCValAssign::Indirect: {
3113 // Store the argument.
3114 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3115 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3116 Chain = DAG.getStore(
3117 Chain, dl, Arg, SpillSlot,
3118 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3125 if (VA.isRegLoc()) {
3126 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3127 if (isVarArg && IsWin64) {
3128 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3129 // shadow reg if callee is a varargs function.
3130 unsigned ShadowReg = 0;
3131 switch (VA.getLocReg()) {
3132 case X86::XMM0: ShadowReg = X86::RCX; break;
3133 case X86::XMM1: ShadowReg = X86::RDX; break;
3134 case X86::XMM2: ShadowReg = X86::R8; break;
3135 case X86::XMM3: ShadowReg = X86::R9; break;
3138 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3140 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3141 assert(VA.isMemLoc());
3142 if (!StackPtr.getNode())
3143 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3144 getPointerTy(DAG.getDataLayout()));
3145 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3146 dl, DAG, VA, Flags));
3150 if (!MemOpChains.empty())
3151 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3153 if (Subtarget->isPICStyleGOT()) {
3154 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3157 RegsToPass.push_back(std::make_pair(
3158 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3159 getPointerTy(DAG.getDataLayout()))));
3161 // If we are tail calling and generating PIC/GOT style code load the
3162 // address of the callee into ECX. The value in ecx is used as target of
3163 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3164 // for tail calls on PIC/GOT architectures. Normally we would just put the
3165 // address of GOT into ebx and then call target@PLT. But for tail calls
3166 // ebx would be restored (since ebx is callee saved) before jumping to the
3169 // Note: The actual moving to ECX is done further down.
3170 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3171 if (G && !G->getGlobal()->hasLocalLinkage() &&
3172 G->getGlobal()->hasDefaultVisibility())
3173 Callee = LowerGlobalAddress(Callee, DAG);
3174 else if (isa<ExternalSymbolSDNode>(Callee))
3175 Callee = LowerExternalSymbol(Callee, DAG);
3179 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3180 // From AMD64 ABI document:
3181 // For calls that may call functions that use varargs or stdargs
3182 // (prototype-less calls or calls to functions containing ellipsis (...) in
3183 // the declaration) %al is used as hidden argument to specify the number
3184 // of SSE registers used. The contents of %al do not need to match exactly
3185 // the number of registers, but must be an ubound on the number of SSE
3186 // registers used and is in the range 0 - 8 inclusive.
3188 // Count the number of XMM registers allocated.
3189 static const MCPhysReg XMMArgRegs[] = {
3190 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3191 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3193 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3194 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3195 && "SSE registers cannot be used when SSE is disabled");
3197 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3198 DAG.getConstant(NumXMMRegs, dl,
3202 if (isVarArg && IsMustTail) {
3203 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3204 for (const auto &F : Forwards) {
3205 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3206 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3210 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3211 // don't need this because the eligibility check rejects calls that require
3212 // shuffling arguments passed in memory.
3213 if (!IsSibcall && isTailCall) {
3214 // Force all the incoming stack arguments to be loaded from the stack
3215 // before any new outgoing arguments are stored to the stack, because the
3216 // outgoing stack slots may alias the incoming argument stack slots, and
3217 // the alias isn't otherwise explicit. This is slightly more conservative
3218 // than necessary, because it means that each store effectively depends
3219 // on every argument instead of just those arguments it would clobber.
3220 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3222 SmallVector<SDValue, 8> MemOpChains2;
3225 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3226 CCValAssign &VA = ArgLocs[i];
3229 assert(VA.isMemLoc());
3230 SDValue Arg = OutVals[i];
3231 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3232 // Skip inalloca arguments. They don't require any work.
3233 if (Flags.isInAlloca())
3235 // Create frame index.
3236 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3237 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3238 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3239 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3241 if (Flags.isByVal()) {
3242 // Copy relative to framepointer.
3243 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3244 if (!StackPtr.getNode())
3245 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3246 getPointerTy(DAG.getDataLayout()));
3247 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3250 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3254 // Store relative to framepointer.
3255 MemOpChains2.push_back(DAG.getStore(
3256 ArgChain, dl, Arg, FIN,
3257 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3262 if (!MemOpChains2.empty())
3263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3265 // Store the return address to the appropriate stack slot.
3266 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3267 getPointerTy(DAG.getDataLayout()),
3268 RegInfo->getSlotSize(), FPDiff, dl);
3271 // Build a sequence of copy-to-reg nodes chained together with token chain
3272 // and flag operands which copy the outgoing args into registers.
3274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3275 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3276 RegsToPass[i].second, InFlag);
3277 InFlag = Chain.getValue(1);
3280 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3281 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3282 // In the 64-bit large code model, we have to make all calls
3283 // through a register, since the call instruction's 32-bit
3284 // pc-relative offset may not be large enough to hold the whole
3286 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3287 // If the callee is a GlobalAddress node (quite common, every direct call
3288 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3290 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3292 // We should use extra load for direct calls to dllimported functions in
3294 const GlobalValue *GV = G->getGlobal();
3295 if (!GV->hasDLLImportStorageClass()) {
3296 unsigned char OpFlags = 0;
3297 bool ExtraLoad = false;
3298 unsigned WrapperKind = ISD::DELETED_NODE;
3300 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3301 // external symbols most go through the PLT in PIC mode. If the symbol
3302 // has hidden or protected visibility, or if it is static or local, then
3303 // we don't need to use the PLT - we can directly call it.
3304 if (Subtarget->isTargetELF() &&
3305 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3306 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3307 OpFlags = X86II::MO_PLT;
3308 } else if (Subtarget->isPICStyleStubAny() &&
3309 !GV->isStrongDefinitionForLinker() &&
3310 (!Subtarget->getTargetTriple().isMacOSX() ||
3311 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3312 // PC-relative references to external symbols should go through $stub,
3313 // unless we're building with the leopard linker or later, which
3314 // automatically synthesizes these stubs.
3315 OpFlags = X86II::MO_DARWIN_STUB;
3316 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3317 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3318 // If the function is marked as non-lazy, generate an indirect call
3319 // which loads from the GOT directly. This avoids runtime overhead
3320 // at the cost of eager binding (and one extra byte of encoding).
3321 OpFlags = X86II::MO_GOTPCREL;
3322 WrapperKind = X86ISD::WrapperRIP;
3326 Callee = DAG.getTargetGlobalAddress(
3327 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3329 // Add a wrapper if needed.
3330 if (WrapperKind != ISD::DELETED_NODE)
3331 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3332 getPointerTy(DAG.getDataLayout()), Callee);
3333 // Add extra indirection if needed.
3335 Callee = DAG.getLoad(
3336 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3337 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3340 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3341 unsigned char OpFlags = 0;
3343 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3344 // external symbols should go through the PLT.
3345 if (Subtarget->isTargetELF() &&
3346 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3347 OpFlags = X86II::MO_PLT;
3348 } else if (Subtarget->isPICStyleStubAny() &&
3349 (!Subtarget->getTargetTriple().isMacOSX() ||
3350 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3351 // PC-relative references to external symbols should go through $stub,
3352 // unless we're building with the leopard linker or later, which
3353 // automatically synthesizes these stubs.
3354 OpFlags = X86II::MO_DARWIN_STUB;
3357 Callee = DAG.getTargetExternalSymbol(
3358 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3359 } else if (Subtarget->isTarget64BitILP32() &&
3360 Callee->getValueType(0) == MVT::i32) {
3361 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3362 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3365 // Returns a chain & a flag for retval copy to use.
3366 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3367 SmallVector<SDValue, 8> Ops;
3369 if (!IsSibcall && isTailCall) {
3370 Chain = DAG.getCALLSEQ_END(Chain,
3371 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3372 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3373 InFlag = Chain.getValue(1);
3376 Ops.push_back(Chain);
3377 Ops.push_back(Callee);
3380 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3382 // Add argument registers to the end of the list so that they are known live
3384 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3385 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3386 RegsToPass[i].second.getValueType()));
3388 // Add a register mask operand representing the call-preserved registers.
3389 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3390 assert(Mask && "Missing call preserved mask for calling convention");
3392 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3393 // the function clobbers all registers. If an exception is thrown, the runtime
3394 // will not restore CSRs.
3395 // FIXME: Model this more precisely so that we can register allocate across
3396 // the normal edge and spill and fill across the exceptional edge.
3397 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3398 const Function *CallerFn = MF.getFunction();
3399 EHPersonality Pers =
3400 CallerFn->hasPersonalityFn()
3401 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3402 : EHPersonality::Unknown;
3403 if (isMSVCEHPersonality(Pers))
3404 Mask = RegInfo->getNoPreservedMask();
3407 Ops.push_back(DAG.getRegisterMask(Mask));
3409 if (InFlag.getNode())
3410 Ops.push_back(InFlag);
3414 //// If this is the first return lowered for this function, add the regs
3415 //// to the liveout set for the function.
3416 // This isn't right, although it's probably harmless on x86; liveouts
3417 // should be computed from returns not tail calls. Consider a void
3418 // function making a tail call to a function returning int.
3419 MF.getFrameInfo()->setHasTailCall();
3420 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3423 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3424 InFlag = Chain.getValue(1);
3426 // Create the CALLSEQ_END node.
3427 unsigned NumBytesForCalleeToPop;
3428 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3429 DAG.getTarget().Options.GuaranteedTailCallOpt))
3430 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3431 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3432 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3433 SR == StackStructReturn)
3434 // If this is a call to a struct-return function, the callee
3435 // pops the hidden struct pointer, so we have to push it back.
3436 // This is common for Darwin/X86, Linux & Mingw32 targets.
3437 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3438 NumBytesForCalleeToPop = 4;
3440 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3442 // Returns a flag for retval copy to use.
3444 Chain = DAG.getCALLSEQ_END(Chain,
3445 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3446 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3449 InFlag = Chain.getValue(1);
3452 // Handle result values, copying them out of physregs into vregs that we
3454 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3455 Ins, dl, DAG, InVals);
3458 //===----------------------------------------------------------------------===//
3459 // Fast Calling Convention (tail call) implementation
3460 //===----------------------------------------------------------------------===//
3462 // Like std call, callee cleans arguments, convention except that ECX is
3463 // reserved for storing the tail called function address. Only 2 registers are
3464 // free for argument passing (inreg). Tail call optimization is performed
3466 // * tailcallopt is enabled
3467 // * caller/callee are fastcc
3468 // On X86_64 architecture with GOT-style position independent code only local
3469 // (within module) calls are supported at the moment.
3470 // To keep the stack aligned according to platform abi the function
3471 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3472 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3473 // If a tail called function callee has more arguments than the caller the
3474 // caller needs to make sure that there is room to move the RETADDR to. This is
3475 // achieved by reserving an area the size of the argument delta right after the
3476 // original RETADDR, but before the saved framepointer or the spilled registers
3477 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3489 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3492 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3493 SelectionDAG& DAG) const {
3494 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3495 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3496 unsigned StackAlignment = TFI.getStackAlignment();
3497 uint64_t AlignMask = StackAlignment - 1;
3498 int64_t Offset = StackSize;
3499 unsigned SlotSize = RegInfo->getSlotSize();
3500 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3501 // Number smaller than 12 so just add the difference.
3502 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3504 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3505 Offset = ((~AlignMask) & Offset) + StackAlignment +
3506 (StackAlignment-SlotSize);
3511 /// Return true if the given stack call argument is already available in the
3512 /// same position (relatively) of the caller's incoming argument stack.
3514 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3515 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3516 const X86InstrInfo *TII) {
3517 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3519 if (Arg.getOpcode() == ISD::CopyFromReg) {
3520 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3521 if (!TargetRegisterInfo::isVirtualRegister(VR))
3523 MachineInstr *Def = MRI->getVRegDef(VR);
3526 if (!Flags.isByVal()) {
3527 if (!TII->isLoadFromStackSlot(Def, FI))
3530 unsigned Opcode = Def->getOpcode();
3531 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3532 Opcode == X86::LEA64_32r) &&
3533 Def->getOperand(1).isFI()) {
3534 FI = Def->getOperand(1).getIndex();
3535 Bytes = Flags.getByValSize();
3539 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3540 if (Flags.isByVal())
3541 // ByVal argument is passed in as a pointer but it's now being
3542 // dereferenced. e.g.
3543 // define @foo(%struct.X* %A) {
3544 // tail call @bar(%struct.X* byval %A)
3547 SDValue Ptr = Ld->getBasePtr();
3548 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3551 FI = FINode->getIndex();
3552 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3553 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3554 FI = FINode->getIndex();
3555 Bytes = Flags.getByValSize();
3559 assert(FI != INT_MAX);
3560 if (!MFI->isFixedObjectIndex(FI))
3562 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3565 /// Check whether the call is eligible for tail call optimization. Targets
3566 /// that want to do tail call optimization should implement this function.
3567 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3568 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3569 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3570 const SmallVectorImpl<ISD::OutputArg> &Outs,
3571 const SmallVectorImpl<SDValue> &OutVals,
3572 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3573 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3576 // If -tailcallopt is specified, make fastcc functions tail-callable.
3577 const MachineFunction &MF = DAG.getMachineFunction();
3578 const Function *CallerF = MF.getFunction();
3580 // If the function return type is x86_fp80 and the callee return type is not,
3581 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3582 // perform a tailcall optimization here.
3583 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3586 CallingConv::ID CallerCC = CallerF->getCallingConv();
3587 bool CCMatch = CallerCC == CalleeCC;
3588 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3589 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3591 // Win64 functions have extra shadow space for argument homing. Don't do the
3592 // sibcall if the caller and callee have mismatched expectations for this
3594 if (IsCalleeWin64 != IsCallerWin64)
3597 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3598 if (IsTailCallConvention(CalleeCC) && CCMatch)
3603 // Look for obvious safe cases to perform tail call optimization that do not
3604 // require ABI changes. This is what gcc calls sibcall.
3606 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3607 // emit a special epilogue.
3608 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3609 if (RegInfo->needsStackRealignment(MF))
3612 // Also avoid sibcall optimization if either caller or callee uses struct
3613 // return semantics.
3614 if (isCalleeStructRet || isCallerStructRet)
3617 // An stdcall/thiscall caller is expected to clean up its arguments; the
3618 // callee isn't going to do that.
3619 // FIXME: this is more restrictive than needed. We could produce a tailcall
3620 // when the stack adjustment matches. For example, with a thiscall that takes
3621 // only one argument.
3622 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3623 CallerCC == CallingConv::X86_ThisCall))
3626 // Do not sibcall optimize vararg calls unless all arguments are passed via
3628 if (isVarArg && !Outs.empty()) {
3630 // Optimizing for varargs on Win64 is unlikely to be safe without
3631 // additional testing.
3632 if (IsCalleeWin64 || IsCallerWin64)
3635 SmallVector<CCValAssign, 16> ArgLocs;
3636 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3639 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3640 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3641 if (!ArgLocs[i].isRegLoc())
3645 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3646 // stack. Therefore, if it's not used by the call it is not safe to optimize
3647 // this into a sibcall.
3648 bool Unused = false;
3649 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3656 SmallVector<CCValAssign, 16> RVLocs;
3657 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3659 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3660 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3661 CCValAssign &VA = RVLocs[i];
3662 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3667 // If the calling conventions do not match, then we'd better make sure the
3668 // results are returned in the same way as what the caller expects.
3670 SmallVector<CCValAssign, 16> RVLocs1;
3671 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3673 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3675 SmallVector<CCValAssign, 16> RVLocs2;
3676 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3678 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3680 if (RVLocs1.size() != RVLocs2.size())
3682 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3683 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3685 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3687 if (RVLocs1[i].isRegLoc()) {
3688 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3691 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3697 // If the callee takes no arguments then go on to check the results of the
3699 if (!Outs.empty()) {
3700 // Check if stack adjustment is needed. For now, do not do this if any
3701 // argument is passed on the stack.
3702 SmallVector<CCValAssign, 16> ArgLocs;
3703 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3706 // Allocate shadow area for Win64
3708 CCInfo.AllocateStack(32, 8);
3710 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3711 if (CCInfo.getNextStackOffset()) {
3712 MachineFunction &MF = DAG.getMachineFunction();
3713 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3716 // Check if the arguments are already laid out in the right way as
3717 // the caller's fixed stack objects.
3718 MachineFrameInfo *MFI = MF.getFrameInfo();
3719 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3720 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3722 CCValAssign &VA = ArgLocs[i];
3723 SDValue Arg = OutVals[i];
3724 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3725 if (VA.getLocInfo() == CCValAssign::Indirect)
3727 if (!VA.isRegLoc()) {
3728 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3735 // If the tailcall address may be in a register, then make sure it's
3736 // possible to register allocate for it. In 32-bit, the call address can
3737 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3738 // callee-saved registers are restored. These happen to be the same
3739 // registers used to pass 'inreg' arguments so watch out for those.
3740 if (!Subtarget->is64Bit() &&
3741 ((!isa<GlobalAddressSDNode>(Callee) &&
3742 !isa<ExternalSymbolSDNode>(Callee)) ||
3743 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3744 unsigned NumInRegs = 0;
3745 // In PIC we need an extra register to formulate the address computation
3747 unsigned MaxInRegs =
3748 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3750 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3751 CCValAssign &VA = ArgLocs[i];
3754 unsigned Reg = VA.getLocReg();
3757 case X86::EAX: case X86::EDX: case X86::ECX:
3758 if (++NumInRegs == MaxInRegs)
3770 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3771 const TargetLibraryInfo *libInfo) const {
3772 return X86::createFastISel(funcInfo, libInfo);
3775 //===----------------------------------------------------------------------===//
3776 // Other Lowering Hooks
3777 //===----------------------------------------------------------------------===//
3779 static bool MayFoldLoad(SDValue Op) {
3780 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3783 static bool MayFoldIntoStore(SDValue Op) {
3784 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3787 static bool isTargetShuffle(unsigned Opcode) {
3789 default: return false;
3790 case X86ISD::BLENDI:
3791 case X86ISD::PSHUFB:
3792 case X86ISD::PSHUFD:
3793 case X86ISD::PSHUFHW:
3794 case X86ISD::PSHUFLW:
3796 case X86ISD::PALIGNR:
3797 case X86ISD::MOVLHPS:
3798 case X86ISD::MOVLHPD:
3799 case X86ISD::MOVHLPS:
3800 case X86ISD::MOVLPS:
3801 case X86ISD::MOVLPD:
3802 case X86ISD::MOVSHDUP:
3803 case X86ISD::MOVSLDUP:
3804 case X86ISD::MOVDDUP:
3807 case X86ISD::UNPCKL:
3808 case X86ISD::UNPCKH:
3809 case X86ISD::VPERMILPI:
3810 case X86ISD::VPERM2X128:
3811 case X86ISD::VPERMI:
3812 case X86ISD::VPERMV:
3813 case X86ISD::VPERMV3:
3818 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3819 SDValue V1, unsigned TargetMask,
3820 SelectionDAG &DAG) {
3822 default: llvm_unreachable("Unknown x86 shuffle node");
3823 case X86ISD::PSHUFD:
3824 case X86ISD::PSHUFHW:
3825 case X86ISD::PSHUFLW:
3826 case X86ISD::VPERMILPI:
3827 case X86ISD::VPERMI:
3828 return DAG.getNode(Opc, dl, VT, V1,
3829 DAG.getConstant(TargetMask, dl, MVT::i8));
3833 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3834 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3836 default: llvm_unreachable("Unknown x86 shuffle node");
3837 case X86ISD::MOVLHPS:
3838 case X86ISD::MOVLHPD:
3839 case X86ISD::MOVHLPS:
3840 case X86ISD::MOVLPS:
3841 case X86ISD::MOVLPD:
3844 case X86ISD::UNPCKL:
3845 case X86ISD::UNPCKH:
3846 return DAG.getNode(Opc, dl, VT, V1, V2);
3850 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3851 MachineFunction &MF = DAG.getMachineFunction();
3852 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3853 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3854 int ReturnAddrIndex = FuncInfo->getRAIndex();
3856 if (ReturnAddrIndex == 0) {
3857 // Set up a frame object for the return address.
3858 unsigned SlotSize = RegInfo->getSlotSize();
3859 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3862 FuncInfo->setRAIndex(ReturnAddrIndex);
3865 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3868 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3869 bool hasSymbolicDisplacement) {
3870 // Offset should fit into 32 bit immediate field.
3871 if (!isInt<32>(Offset))
3874 // If we don't have a symbolic displacement - we don't have any extra
3876 if (!hasSymbolicDisplacement)
3879 // FIXME: Some tweaks might be needed for medium code model.
3880 if (M != CodeModel::Small && M != CodeModel::Kernel)
3883 // For small code model we assume that latest object is 16MB before end of 31
3884 // bits boundary. We may also accept pretty large negative constants knowing
3885 // that all objects are in the positive half of address space.
3886 if (M == CodeModel::Small && Offset < 16*1024*1024)
3889 // For kernel code model we know that all object resist in the negative half
3890 // of 32bits address space. We may not accept negative offsets, since they may
3891 // be just off and we may accept pretty large positive ones.
3892 if (M == CodeModel::Kernel && Offset >= 0)
3898 /// Determines whether the callee is required to pop its own arguments.
3899 /// Callee pop is necessary to support tail calls.
3900 bool X86::isCalleePop(CallingConv::ID CallingConv,
3901 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3902 switch (CallingConv) {
3905 case CallingConv::X86_StdCall:
3906 case CallingConv::X86_FastCall:
3907 case CallingConv::X86_ThisCall:
3909 case CallingConv::Fast:
3910 case CallingConv::GHC:
3911 case CallingConv::HiPE:
3918 /// \brief Return true if the condition is an unsigned comparison operation.
3919 static bool isX86CCUnsigned(unsigned X86CC) {
3921 default: llvm_unreachable("Invalid integer condition!");
3922 case X86::COND_E: return true;
3923 case X86::COND_G: return false;
3924 case X86::COND_GE: return false;
3925 case X86::COND_L: return false;
3926 case X86::COND_LE: return false;
3927 case X86::COND_NE: return true;
3928 case X86::COND_B: return true;
3929 case X86::COND_A: return true;
3930 case X86::COND_BE: return true;
3931 case X86::COND_AE: return true;
3933 llvm_unreachable("covered switch fell through?!");
3936 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3937 /// condition code, returning the condition code and the LHS/RHS of the
3938 /// comparison to make.
3939 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3940 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3942 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3943 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3944 // X > -1 -> X == 0, jump !sign.
3945 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3946 return X86::COND_NS;
3948 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3949 // X < 0 -> X == 0, jump on sign.
3952 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3954 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3955 return X86::COND_LE;
3959 switch (SetCCOpcode) {
3960 default: llvm_unreachable("Invalid integer condition!");
3961 case ISD::SETEQ: return X86::COND_E;
3962 case ISD::SETGT: return X86::COND_G;
3963 case ISD::SETGE: return X86::COND_GE;
3964 case ISD::SETLT: return X86::COND_L;
3965 case ISD::SETLE: return X86::COND_LE;
3966 case ISD::SETNE: return X86::COND_NE;
3967 case ISD::SETULT: return X86::COND_B;
3968 case ISD::SETUGT: return X86::COND_A;
3969 case ISD::SETULE: return X86::COND_BE;
3970 case ISD::SETUGE: return X86::COND_AE;
3974 // First determine if it is required or is profitable to flip the operands.
3976 // If LHS is a foldable load, but RHS is not, flip the condition.
3977 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3978 !ISD::isNON_EXTLoad(RHS.getNode())) {
3979 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3980 std::swap(LHS, RHS);
3983 switch (SetCCOpcode) {
3989 std::swap(LHS, RHS);
3993 // On a floating point condition, the flags are set as follows:
3995 // 0 | 0 | 0 | X > Y
3996 // 0 | 0 | 1 | X < Y
3997 // 1 | 0 | 0 | X == Y
3998 // 1 | 1 | 1 | unordered
3999 switch (SetCCOpcode) {
4000 default: llvm_unreachable("Condcode should be pre-legalized away");
4002 case ISD::SETEQ: return X86::COND_E;
4003 case ISD::SETOLT: // flipped
4005 case ISD::SETGT: return X86::COND_A;
4006 case ISD::SETOLE: // flipped
4008 case ISD::SETGE: return X86::COND_AE;
4009 case ISD::SETUGT: // flipped
4011 case ISD::SETLT: return X86::COND_B;
4012 case ISD::SETUGE: // flipped
4014 case ISD::SETLE: return X86::COND_BE;
4016 case ISD::SETNE: return X86::COND_NE;
4017 case ISD::SETUO: return X86::COND_P;
4018 case ISD::SETO: return X86::COND_NP;
4020 case ISD::SETUNE: return X86::COND_INVALID;
4024 /// Is there a floating point cmov for the specific X86 condition code?
4025 /// Current x86 isa includes the following FP cmov instructions:
4026 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4027 static bool hasFPCMov(unsigned X86CC) {
4043 /// Returns true if the target can instruction select the
4044 /// specified FP immediate natively. If false, the legalizer will
4045 /// materialize the FP immediate as a load from a constant pool.
4046 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4047 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4048 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4054 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4055 ISD::LoadExtType ExtTy,
4057 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4058 // relocation target a movq or addq instruction: don't let the load shrink.
4059 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4060 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4061 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4062 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4066 /// \brief Returns true if it is beneficial to convert a load of a constant
4067 /// to just the constant itself.
4068 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4070 assert(Ty->isIntegerTy());
4072 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4073 if (BitSize == 0 || BitSize > 64)
4078 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4079 unsigned Index) const {
4080 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4083 return (Index == 0 || Index == ResVT.getVectorNumElements());
4086 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4087 // Speculate cttz only if we can directly use TZCNT.
4088 return Subtarget->hasBMI();
4091 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4092 // Speculate ctlz only if we can directly use LZCNT.
4093 return Subtarget->hasLZCNT();
4096 /// Return true if every element in Mask, beginning
4097 /// from position Pos and ending in Pos+Size is undef.
4098 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4099 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4105 /// Return true if Val is undef or if its value falls within the
4106 /// specified range (L, H].
4107 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4108 return (Val < 0) || (Val >= Low && Val < Hi);
4111 /// Val is either less than zero (undef) or equal to the specified value.
4112 static bool isUndefOrEqual(int Val, int CmpVal) {
4113 return (Val < 0 || Val == CmpVal);
4116 /// Return true if every element in Mask, beginning
4117 /// from position Pos and ending in Pos+Size, falls within the specified
4118 /// sequential range (Low, Low+Size]. or is undef.
4119 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4120 unsigned Pos, unsigned Size, int Low) {
4121 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4122 if (!isUndefOrEqual(Mask[i], Low))
4127 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4128 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4129 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4130 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4131 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4134 // The index should be aligned on a vecWidth-bit boundary.
4136 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4138 MVT VT = N->getSimpleValueType(0);
4139 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4140 bool Result = (Index * ElSize) % vecWidth == 0;
4145 /// Return true if the specified INSERT_SUBVECTOR
4146 /// operand specifies a subvector insert that is suitable for input to
4147 /// insertion of 128 or 256-bit subvectors
4148 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4149 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4150 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4152 // The index should be aligned on a vecWidth-bit boundary.
4154 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4156 MVT VT = N->getSimpleValueType(0);
4157 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4158 bool Result = (Index * ElSize) % vecWidth == 0;
4163 bool X86::isVINSERT128Index(SDNode *N) {
4164 return isVINSERTIndex(N, 128);
4167 bool X86::isVINSERT256Index(SDNode *N) {
4168 return isVINSERTIndex(N, 256);
4171 bool X86::isVEXTRACT128Index(SDNode *N) {
4172 return isVEXTRACTIndex(N, 128);
4175 bool X86::isVEXTRACT256Index(SDNode *N) {
4176 return isVEXTRACTIndex(N, 256);
4179 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4180 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4181 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4182 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4185 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4187 MVT VecVT = N->getOperand(0).getSimpleValueType();
4188 MVT ElVT = VecVT.getVectorElementType();
4190 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4191 return Index / NumElemsPerChunk;
4194 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4195 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4196 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4197 llvm_unreachable("Illegal insert subvector for VINSERT");
4200 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4202 MVT VecVT = N->getSimpleValueType(0);
4203 MVT ElVT = VecVT.getVectorElementType();
4205 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4206 return Index / NumElemsPerChunk;
4209 /// Return the appropriate immediate to extract the specified
4210 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4211 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4212 return getExtractVEXTRACTImmediate(N, 128);
4215 /// Return the appropriate immediate to extract the specified
4216 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4217 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4218 return getExtractVEXTRACTImmediate(N, 256);
4221 /// Return the appropriate immediate to insert at the specified
4222 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4223 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4224 return getInsertVINSERTImmediate(N, 128);
4227 /// Return the appropriate immediate to insert at the specified
4228 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4229 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4230 return getInsertVINSERTImmediate(N, 256);
4233 /// Returns true if Elt is a constant integer zero
4234 static bool isZero(SDValue V) {
4235 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4236 return C && C->isNullValue();
4239 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4240 bool X86::isZeroNode(SDValue Elt) {
4243 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4244 return CFP->getValueAPF().isPosZero();
4248 /// Returns a vector of specified type with all zero elements.
4249 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4250 SelectionDAG &DAG, SDLoc dl) {
4251 assert(VT.isVector() && "Expected a vector type");
4253 // Always build SSE zero vectors as <4 x i32> bitcasted
4254 // to their dest type. This ensures they get CSE'd.
4256 if (VT.is128BitVector()) { // SSE
4257 if (Subtarget->hasSSE2()) { // SSE2
4258 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4261 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4262 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4264 } else if (VT.is256BitVector()) { // AVX
4265 if (Subtarget->hasInt256()) { // AVX2
4266 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4267 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4268 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4270 // 256-bit logic and arithmetic instructions in AVX are all
4271 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4272 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4273 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4274 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4276 } else if (VT.is512BitVector()) { // AVX-512
4277 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4278 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4279 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4280 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4281 } else if (VT.getScalarType() == MVT::i1) {
4283 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4284 && "Unexpected vector type");
4285 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4286 && "Unexpected vector type");
4287 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4288 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4289 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4291 llvm_unreachable("Unexpected vector type");
4293 return DAG.getBitcast(VT, Vec);
4296 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4297 SelectionDAG &DAG, SDLoc dl,
4298 unsigned vectorWidth) {
4299 assert((vectorWidth == 128 || vectorWidth == 256) &&
4300 "Unsupported vector width");
4301 EVT VT = Vec.getValueType();
4302 EVT ElVT = VT.getVectorElementType();
4303 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4304 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4305 VT.getVectorNumElements()/Factor);
4307 // Extract from UNDEF is UNDEF.
4308 if (Vec.getOpcode() == ISD::UNDEF)
4309 return DAG.getUNDEF(ResultVT);
4311 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4312 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4314 // This is the index of the first element of the vectorWidth-bit chunk
4316 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4319 // If the input is a buildvector just emit a smaller one.
4320 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4321 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4322 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4325 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4326 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4329 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4330 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4331 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4332 /// instructions or a simple subregister reference. Idx is an index in the
4333 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4334 /// lowering EXTRACT_VECTOR_ELT operations easier.
4335 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4336 SelectionDAG &DAG, SDLoc dl) {
4337 assert((Vec.getValueType().is256BitVector() ||
4338 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4339 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4342 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4343 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4344 SelectionDAG &DAG, SDLoc dl) {
4345 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4346 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4349 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4350 unsigned IdxVal, SelectionDAG &DAG,
4351 SDLoc dl, unsigned vectorWidth) {
4352 assert((vectorWidth == 128 || vectorWidth == 256) &&
4353 "Unsupported vector width");
4354 // Inserting UNDEF is Result
4355 if (Vec.getOpcode() == ISD::UNDEF)
4357 EVT VT = Vec.getValueType();
4358 EVT ElVT = VT.getVectorElementType();
4359 EVT ResultVT = Result.getValueType();
4361 // Insert the relevant vectorWidth bits.
4362 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4364 // This is the index of the first element of the vectorWidth-bit chunk
4366 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4369 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4370 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4373 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4374 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4375 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4376 /// simple superregister reference. Idx is an index in the 128 bits
4377 /// we want. It need not be aligned to a 128-bit boundary. That makes
4378 /// lowering INSERT_VECTOR_ELT operations easier.
4379 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4380 SelectionDAG &DAG, SDLoc dl) {
4381 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4383 // For insertion into the zero index (low half) of a 256-bit vector, it is
4384 // more efficient to generate a blend with immediate instead of an insert*128.
4385 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4386 // extend the subvector to the size of the result vector. Make sure that
4387 // we are not recursing on that node by checking for undef here.
4388 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4389 Result.getOpcode() != ISD::UNDEF) {
4390 EVT ResultVT = Result.getValueType();
4391 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4392 SDValue Undef = DAG.getUNDEF(ResultVT);
4393 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4396 // The blend instruction, and therefore its mask, depend on the data type.
4397 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4398 if (ScalarType.isFloatingPoint()) {
4399 // Choose either vblendps (float) or vblendpd (double).
4400 unsigned ScalarSize = ScalarType.getSizeInBits();
4401 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4402 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4403 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4404 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4407 const X86Subtarget &Subtarget =
4408 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4410 // AVX2 is needed for 256-bit integer blend support.
4411 // Integers must be cast to 32-bit because there is only vpblendd;
4412 // vpblendw can't be used for this because it has a handicapped mask.
4414 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4415 // is still more efficient than using the wrong domain vinsertf128 that
4416 // will be created by InsertSubVector().
4417 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4419 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4420 Vec256 = DAG.getBitcast(CastVT, Vec256);
4421 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4422 return DAG.getBitcast(ResultVT, Vec256);
4425 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4428 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4429 SelectionDAG &DAG, SDLoc dl) {
4430 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4431 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4434 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4435 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4436 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4437 /// large BUILD_VECTORS.
4438 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4439 unsigned NumElems, SelectionDAG &DAG,
4441 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4442 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4445 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4446 unsigned NumElems, SelectionDAG &DAG,
4448 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4449 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4452 /// Returns a vector of specified type with all bits set.
4453 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4454 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4455 /// Then bitcast to their original type, ensuring they get CSE'd.
4456 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4457 SelectionDAG &DAG, SDLoc dl) {
4458 assert(VT.isVector() && "Expected a vector type");
4460 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4462 if (VT.is512BitVector()) {
4463 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4464 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4465 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4466 } else if (VT.is256BitVector()) {
4467 if (Subtarget->hasInt256()) { // AVX2
4468 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4469 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4471 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4472 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4474 } else if (VT.is128BitVector()) {
4475 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4477 llvm_unreachable("Unexpected vector type");
4479 return DAG.getBitcast(VT, Vec);
4482 /// Returns a vector_shuffle node for an unpackl operation.
4483 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4485 unsigned NumElems = VT.getVectorNumElements();
4486 SmallVector<int, 8> Mask;
4487 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4489 Mask.push_back(i + NumElems);
4491 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4494 /// Returns a vector_shuffle node for an unpackh operation.
4495 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4497 unsigned NumElems = VT.getVectorNumElements();
4498 SmallVector<int, 8> Mask;
4499 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4500 Mask.push_back(i + Half);
4501 Mask.push_back(i + NumElems + Half);
4503 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4506 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4507 /// This produces a shuffle where the low element of V2 is swizzled into the
4508 /// zero/undef vector, landing at element Idx.
4509 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4510 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4512 const X86Subtarget *Subtarget,
4513 SelectionDAG &DAG) {
4514 MVT VT = V2.getSimpleValueType();
4516 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4517 unsigned NumElems = VT.getVectorNumElements();
4518 SmallVector<int, 16> MaskVec;
4519 for (unsigned i = 0; i != NumElems; ++i)
4520 // If this is the insertion idx, put the low elt of V2 here.
4521 MaskVec.push_back(i == Idx ? NumElems : i);
4522 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4525 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4526 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4527 /// uses one source. Note that this will set IsUnary for shuffles which use a
4528 /// single input multiple times, and in those cases it will
4529 /// adjust the mask to only have indices within that single input.
4530 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4531 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4532 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4533 unsigned NumElems = VT.getVectorNumElements();
4537 bool IsFakeUnary = false;
4538 switch(N->getOpcode()) {
4539 case X86ISD::BLENDI:
4540 ImmN = N->getOperand(N->getNumOperands()-1);
4541 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4544 ImmN = N->getOperand(N->getNumOperands()-1);
4545 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4546 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4548 case X86ISD::UNPCKH:
4549 DecodeUNPCKHMask(VT, Mask);
4550 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4552 case X86ISD::UNPCKL:
4553 DecodeUNPCKLMask(VT, Mask);
4554 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4556 case X86ISD::MOVHLPS:
4557 DecodeMOVHLPSMask(NumElems, Mask);
4558 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4560 case X86ISD::MOVLHPS:
4561 DecodeMOVLHPSMask(NumElems, Mask);
4562 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4564 case X86ISD::PALIGNR:
4565 ImmN = N->getOperand(N->getNumOperands()-1);
4566 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4568 case X86ISD::PSHUFD:
4569 case X86ISD::VPERMILPI:
4570 ImmN = N->getOperand(N->getNumOperands()-1);
4571 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4574 case X86ISD::PSHUFHW:
4575 ImmN = N->getOperand(N->getNumOperands()-1);
4576 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4579 case X86ISD::PSHUFLW:
4580 ImmN = N->getOperand(N->getNumOperands()-1);
4581 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4584 case X86ISD::PSHUFB: {
4586 SDValue MaskNode = N->getOperand(1);
4587 while (MaskNode->getOpcode() == ISD::BITCAST)
4588 MaskNode = MaskNode->getOperand(0);
4590 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4591 // If we have a build-vector, then things are easy.
4592 EVT VT = MaskNode.getValueType();
4593 assert(VT.isVector() &&
4594 "Can't produce a non-vector with a build_vector!");
4595 if (!VT.isInteger())
4598 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4600 SmallVector<uint64_t, 32> RawMask;
4601 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4602 SDValue Op = MaskNode->getOperand(i);
4603 if (Op->getOpcode() == ISD::UNDEF) {
4604 RawMask.push_back((uint64_t)SM_SentinelUndef);
4607 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4610 APInt MaskElement = CN->getAPIntValue();
4612 // We now have to decode the element which could be any integer size and
4613 // extract each byte of it.
4614 for (int j = 0; j < NumBytesPerElement; ++j) {
4615 // Note that this is x86 and so always little endian: the low byte is
4616 // the first byte of the mask.
4617 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4618 MaskElement = MaskElement.lshr(8);
4621 DecodePSHUFBMask(RawMask, Mask);
4625 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4629 SDValue Ptr = MaskLoad->getBasePtr();
4630 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4631 Ptr->getOpcode() == X86ISD::WrapperRIP)
4632 Ptr = Ptr->getOperand(0);
4634 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4635 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4638 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4639 DecodePSHUFBMask(C, Mask);
4647 case X86ISD::VPERMI:
4648 ImmN = N->getOperand(N->getNumOperands()-1);
4649 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4654 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4656 case X86ISD::VPERM2X128:
4657 ImmN = N->getOperand(N->getNumOperands()-1);
4658 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4659 if (Mask.empty()) return false;
4660 // Mask only contains negative index if an element is zero.
4661 if (std::any_of(Mask.begin(), Mask.end(),
4662 [](int M){ return M == SM_SentinelZero; }))
4665 case X86ISD::MOVSLDUP:
4666 DecodeMOVSLDUPMask(VT, Mask);
4669 case X86ISD::MOVSHDUP:
4670 DecodeMOVSHDUPMask(VT, Mask);
4673 case X86ISD::MOVDDUP:
4674 DecodeMOVDDUPMask(VT, Mask);
4677 case X86ISD::MOVLHPD:
4678 case X86ISD::MOVLPD:
4679 case X86ISD::MOVLPS:
4680 // Not yet implemented
4682 case X86ISD::VPERMV: {
4684 SDValue MaskNode = N->getOperand(0);
4685 while (MaskNode->getOpcode() == ISD::BITCAST)
4686 MaskNode = MaskNode->getOperand(0);
4688 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4689 SmallVector<uint64_t, 32> RawMask;
4690 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4691 // If we have a build-vector, then things are easy.
4692 assert(MaskNode.getValueType().isInteger() &&
4693 MaskNode.getValueType().getVectorNumElements() ==
4694 VT.getVectorNumElements());
4696 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4697 SDValue Op = MaskNode->getOperand(i);
4698 if (Op->getOpcode() == ISD::UNDEF)
4699 RawMask.push_back((uint64_t)SM_SentinelUndef);
4700 else if (isa<ConstantSDNode>(Op)) {
4701 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4702 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4706 DecodeVPERMVMask(RawMask, Mask);
4709 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4710 unsigned NumEltsInMask = MaskNode->getNumOperands();
4711 MaskNode = MaskNode->getOperand(0);
4712 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4714 APInt MaskEltValue = CN->getAPIntValue();
4715 for (unsigned i = 0; i < NumEltsInMask; ++i)
4716 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4717 DecodeVPERMVMask(RawMask, Mask);
4720 // It may be a scalar load
4723 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4727 SDValue Ptr = MaskLoad->getBasePtr();
4728 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4729 Ptr->getOpcode() == X86ISD::WrapperRIP)
4730 Ptr = Ptr->getOperand(0);
4732 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4733 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4736 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4738 DecodeVPERMVMask(C, VT, Mask);
4745 case X86ISD::VPERMV3: {
4747 SDValue MaskNode = N->getOperand(1);
4748 while (MaskNode->getOpcode() == ISD::BITCAST)
4749 MaskNode = MaskNode->getOperand(1);
4751 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4752 // If we have a build-vector, then things are easy.
4753 assert(MaskNode.getValueType().isInteger() &&
4754 MaskNode.getValueType().getVectorNumElements() ==
4755 VT.getVectorNumElements());
4757 SmallVector<uint64_t, 32> RawMask;
4758 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4760 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4761 SDValue Op = MaskNode->getOperand(i);
4762 if (Op->getOpcode() == ISD::UNDEF)
4763 RawMask.push_back((uint64_t)SM_SentinelUndef);
4765 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4768 APInt MaskElement = CN->getAPIntValue();
4769 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4772 DecodeVPERMV3Mask(RawMask, Mask);
4776 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4780 SDValue Ptr = MaskLoad->getBasePtr();
4781 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4782 Ptr->getOpcode() == X86ISD::WrapperRIP)
4783 Ptr = Ptr->getOperand(0);
4785 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4786 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4789 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4791 DecodeVPERMV3Mask(C, VT, Mask);
4798 default: llvm_unreachable("unknown target shuffle node");
4801 // If we have a fake unary shuffle, the shuffle mask is spread across two
4802 // inputs that are actually the same node. Re-map the mask to always point
4803 // into the first input.
4806 if (M >= (int)Mask.size())
4812 /// Returns the scalar element that will make up the ith
4813 /// element of the result of the vector shuffle.
4814 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4817 return SDValue(); // Limit search depth.
4819 SDValue V = SDValue(N, 0);
4820 EVT VT = V.getValueType();
4821 unsigned Opcode = V.getOpcode();
4823 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4824 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4825 int Elt = SV->getMaskElt(Index);
4828 return DAG.getUNDEF(VT.getVectorElementType());
4830 unsigned NumElems = VT.getVectorNumElements();
4831 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4832 : SV->getOperand(1);
4833 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4836 // Recurse into target specific vector shuffles to find scalars.
4837 if (isTargetShuffle(Opcode)) {
4838 MVT ShufVT = V.getSimpleValueType();
4839 unsigned NumElems = ShufVT.getVectorNumElements();
4840 SmallVector<int, 16> ShuffleMask;
4843 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4846 int Elt = ShuffleMask[Index];
4848 return DAG.getUNDEF(ShufVT.getVectorElementType());
4850 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4852 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4856 // Actual nodes that may contain scalar elements
4857 if (Opcode == ISD::BITCAST) {
4858 V = V.getOperand(0);
4859 EVT SrcVT = V.getValueType();
4860 unsigned NumElems = VT.getVectorNumElements();
4862 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4866 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4867 return (Index == 0) ? V.getOperand(0)
4868 : DAG.getUNDEF(VT.getVectorElementType());
4870 if (V.getOpcode() == ISD::BUILD_VECTOR)
4871 return V.getOperand(Index);
4876 /// Custom lower build_vector of v16i8.
4877 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4878 unsigned NumNonZero, unsigned NumZero,
4880 const X86Subtarget* Subtarget,
4881 const TargetLowering &TLI) {
4889 // SSE4.1 - use PINSRB to insert each byte directly.
4890 if (Subtarget->hasSSE41()) {
4891 for (unsigned i = 0; i < 16; ++i) {
4892 bool isNonZero = (NonZeros & (1 << i)) != 0;
4896 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4898 V = DAG.getUNDEF(MVT::v16i8);
4901 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4902 MVT::v16i8, V, Op.getOperand(i),
4903 DAG.getIntPtrConstant(i, dl));
4910 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4911 for (unsigned i = 0; i < 16; ++i) {
4912 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4913 if (ThisIsNonZero && First) {
4915 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4917 V = DAG.getUNDEF(MVT::v8i16);
4922 SDValue ThisElt, LastElt;
4923 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4924 if (LastIsNonZero) {
4925 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4926 MVT::i16, Op.getOperand(i-1));
4928 if (ThisIsNonZero) {
4929 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4930 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4931 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4933 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4937 if (ThisElt.getNode())
4938 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4939 DAG.getIntPtrConstant(i/2, dl));
4943 return DAG.getBitcast(MVT::v16i8, V);
4946 /// Custom lower build_vector of v8i16.
4947 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4948 unsigned NumNonZero, unsigned NumZero,
4950 const X86Subtarget* Subtarget,
4951 const TargetLowering &TLI) {
4958 for (unsigned i = 0; i < 8; ++i) {
4959 bool isNonZero = (NonZeros & (1 << i)) != 0;
4963 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4965 V = DAG.getUNDEF(MVT::v8i16);
4968 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4969 MVT::v8i16, V, Op.getOperand(i),
4970 DAG.getIntPtrConstant(i, dl));
4977 /// Custom lower build_vector of v4i32 or v4f32.
4978 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4979 const X86Subtarget *Subtarget,
4980 const TargetLowering &TLI) {
4981 // Find all zeroable elements.
4982 std::bitset<4> Zeroable;
4983 for (int i=0; i < 4; ++i) {
4984 SDValue Elt = Op->getOperand(i);
4985 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4987 assert(Zeroable.size() - Zeroable.count() > 1 &&
4988 "We expect at least two non-zero elements!");
4990 // We only know how to deal with build_vector nodes where elements are either
4991 // zeroable or extract_vector_elt with constant index.
4992 SDValue FirstNonZero;
4993 unsigned FirstNonZeroIdx;
4994 for (unsigned i=0; i < 4; ++i) {
4997 SDValue Elt = Op->getOperand(i);
4998 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4999 !isa<ConstantSDNode>(Elt.getOperand(1)))
5001 // Make sure that this node is extracting from a 128-bit vector.
5002 MVT VT = Elt.getOperand(0).getSimpleValueType();
5003 if (!VT.is128BitVector())
5005 if (!FirstNonZero.getNode()) {
5007 FirstNonZeroIdx = i;
5011 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5012 SDValue V1 = FirstNonZero.getOperand(0);
5013 MVT VT = V1.getSimpleValueType();
5015 // See if this build_vector can be lowered as a blend with zero.
5017 unsigned EltMaskIdx, EltIdx;
5019 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5020 if (Zeroable[EltIdx]) {
5021 // The zero vector will be on the right hand side.
5022 Mask[EltIdx] = EltIdx+4;
5026 Elt = Op->getOperand(EltIdx);
5027 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5028 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5029 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5031 Mask[EltIdx] = EltIdx;
5035 // Let the shuffle legalizer deal with blend operations.
5036 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5037 if (V1.getSimpleValueType() != VT)
5038 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5039 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5042 // See if we can lower this build_vector to a INSERTPS.
5043 if (!Subtarget->hasSSE41())
5046 SDValue V2 = Elt.getOperand(0);
5047 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5050 bool CanFold = true;
5051 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5055 SDValue Current = Op->getOperand(i);
5056 SDValue SrcVector = Current->getOperand(0);
5059 CanFold = SrcVector == V1 &&
5060 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5066 assert(V1.getNode() && "Expected at least two non-zero elements!");
5067 if (V1.getSimpleValueType() != MVT::v4f32)
5068 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5069 if (V2.getSimpleValueType() != MVT::v4f32)
5070 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5072 // Ok, we can emit an INSERTPS instruction.
5073 unsigned ZMask = Zeroable.to_ulong();
5075 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5076 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5078 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5079 DAG.getIntPtrConstant(InsertPSMask, DL));
5080 return DAG.getBitcast(VT, Result);
5083 /// Return a vector logical shift node.
5084 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5085 unsigned NumBits, SelectionDAG &DAG,
5086 const TargetLowering &TLI, SDLoc dl) {
5087 assert(VT.is128BitVector() && "Unknown type for VShift");
5088 MVT ShVT = MVT::v2i64;
5089 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5090 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5091 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5092 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5093 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5094 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5098 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5100 // Check if the scalar load can be widened into a vector load. And if
5101 // the address is "base + cst" see if the cst can be "absorbed" into
5102 // the shuffle mask.
5103 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5104 SDValue Ptr = LD->getBasePtr();
5105 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5107 EVT PVT = LD->getValueType(0);
5108 if (PVT != MVT::i32 && PVT != MVT::f32)
5113 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5114 FI = FINode->getIndex();
5116 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5117 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5118 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5119 Offset = Ptr.getConstantOperandVal(1);
5120 Ptr = Ptr.getOperand(0);
5125 // FIXME: 256-bit vector instructions don't require a strict alignment,
5126 // improve this code to support it better.
5127 unsigned RequiredAlign = VT.getSizeInBits()/8;
5128 SDValue Chain = LD->getChain();
5129 // Make sure the stack object alignment is at least 16 or 32.
5130 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5131 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5132 if (MFI->isFixedObjectIndex(FI)) {
5133 // Can't change the alignment. FIXME: It's possible to compute
5134 // the exact stack offset and reference FI + adjust offset instead.
5135 // If someone *really* cares about this. That's the way to implement it.
5138 MFI->setObjectAlignment(FI, RequiredAlign);
5142 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5143 // Ptr + (Offset & ~15).
5146 if ((Offset % RequiredAlign) & 3)
5148 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5151 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5152 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5155 int EltNo = (Offset - StartOffset) >> 2;
5156 unsigned NumElems = VT.getVectorNumElements();
5158 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5159 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5160 LD->getPointerInfo().getWithOffset(StartOffset),
5161 false, false, false, 0);
5163 SmallVector<int, 8> Mask(NumElems, EltNo);
5165 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5171 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5172 /// elements can be replaced by a single large load which has the same value as
5173 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5175 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5177 /// FIXME: we'd also like to handle the case where the last elements are zero
5178 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5179 /// There's even a handy isZeroNode for that purpose.
5180 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5181 SDLoc &DL, SelectionDAG &DAG,
5182 bool isAfterLegalize) {
5183 unsigned NumElems = Elts.size();
5185 LoadSDNode *LDBase = nullptr;
5186 unsigned LastLoadedElt = -1U;
5188 // For each element in the initializer, see if we've found a load or an undef.
5189 // If we don't find an initial load element, or later load elements are
5190 // non-consecutive, bail out.
5191 for (unsigned i = 0; i < NumElems; ++i) {
5192 SDValue Elt = Elts[i];
5193 // Look through a bitcast.
5194 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5195 Elt = Elt.getOperand(0);
5196 if (!Elt.getNode() ||
5197 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5200 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5202 LDBase = cast<LoadSDNode>(Elt.getNode());
5206 if (Elt.getOpcode() == ISD::UNDEF)
5209 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5210 EVT LdVT = Elt.getValueType();
5211 // Each loaded element must be the correct fractional portion of the
5212 // requested vector load.
5213 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5215 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5220 // If we have found an entire vector of loads and undefs, then return a large
5221 // load of the entire vector width starting at the base pointer. If we found
5222 // consecutive loads for the low half, generate a vzext_load node.
5223 if (LastLoadedElt == NumElems - 1) {
5224 assert(LDBase && "Did not find base load for merging consecutive loads");
5225 EVT EltVT = LDBase->getValueType(0);
5226 // Ensure that the input vector size for the merged loads matches the
5227 // cumulative size of the input elements.
5228 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5231 if (isAfterLegalize &&
5232 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5235 SDValue NewLd = SDValue();
5237 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5238 LDBase->getPointerInfo(), LDBase->isVolatile(),
5239 LDBase->isNonTemporal(), LDBase->isInvariant(),
5240 LDBase->getAlignment());
5242 if (LDBase->hasAnyUseOfValue(1)) {
5243 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5245 SDValue(NewLd.getNode(), 1));
5246 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5247 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5248 SDValue(NewLd.getNode(), 1));
5254 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5255 //of a v4i32 / v4f32. It's probably worth generalizing.
5256 EVT EltVT = VT.getVectorElementType();
5257 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5258 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5259 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5260 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5262 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5263 LDBase->getPointerInfo(),
5264 LDBase->getAlignment(),
5265 false/*isVolatile*/, true/*ReadMem*/,
5268 // Make sure the newly-created LOAD is in the same position as LDBase in
5269 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5270 // update uses of LDBase's output chain to use the TokenFactor.
5271 if (LDBase->hasAnyUseOfValue(1)) {
5272 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5273 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5274 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5275 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5276 SDValue(ResNode.getNode(), 1));
5279 return DAG.getBitcast(VT, ResNode);
5284 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5285 /// to generate a splat value for the following cases:
5286 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5287 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5288 /// a scalar load, or a constant.
5289 /// The VBROADCAST node is returned when a pattern is found,
5290 /// or SDValue() otherwise.
5291 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5292 SelectionDAG &DAG) {
5293 // VBROADCAST requires AVX.
5294 // TODO: Splats could be generated for non-AVX CPUs using SSE
5295 // instructions, but there's less potential gain for only 128-bit vectors.
5296 if (!Subtarget->hasAVX())
5299 MVT VT = Op.getSimpleValueType();
5302 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5303 "Unsupported vector type for broadcast.");
5308 switch (Op.getOpcode()) {
5310 // Unknown pattern found.
5313 case ISD::BUILD_VECTOR: {
5314 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5315 BitVector UndefElements;
5316 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5318 // We need a splat of a single value to use broadcast, and it doesn't
5319 // make any sense if the value is only in one element of the vector.
5320 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5324 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5325 Ld.getOpcode() == ISD::ConstantFP);
5327 // Make sure that all of the users of a non-constant load are from the
5328 // BUILD_VECTOR node.
5329 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5334 case ISD::VECTOR_SHUFFLE: {
5335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5337 // Shuffles must have a splat mask where the first element is
5339 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5342 SDValue Sc = Op.getOperand(0);
5343 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5344 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5346 if (!Subtarget->hasInt256())
5349 // Use the register form of the broadcast instruction available on AVX2.
5350 if (VT.getSizeInBits() >= 256)
5351 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5352 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5355 Ld = Sc.getOperand(0);
5356 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5357 Ld.getOpcode() == ISD::ConstantFP);
5359 // The scalar_to_vector node and the suspected
5360 // load node must have exactly one user.
5361 // Constants may have multiple users.
5363 // AVX-512 has register version of the broadcast
5364 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5365 Ld.getValueType().getSizeInBits() >= 32;
5366 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5373 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5374 bool IsGE256 = (VT.getSizeInBits() >= 256);
5376 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5377 // instruction to save 8 or more bytes of constant pool data.
5378 // TODO: If multiple splats are generated to load the same constant,
5379 // it may be detrimental to overall size. There needs to be a way to detect
5380 // that condition to know if this is truly a size win.
5381 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5383 // Handle broadcasting a single constant scalar from the constant pool
5385 // On Sandybridge (no AVX2), it is still better to load a constant vector
5386 // from the constant pool and not to broadcast it from a scalar.
5387 // But override that restriction when optimizing for size.
5388 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5389 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5390 EVT CVT = Ld.getValueType();
5391 assert(!CVT.isVector() && "Must not broadcast a vector type");
5393 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5394 // For size optimization, also splat v2f64 and v2i64, and for size opt
5395 // with AVX2, also splat i8 and i16.
5396 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5397 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5398 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5399 const Constant *C = nullptr;
5400 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5401 C = CI->getConstantIntValue();
5402 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5403 C = CF->getConstantFPValue();
5405 assert(C && "Invalid constant type");
5407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5409 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5410 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5412 CVT, dl, DAG.getEntryNode(), CP,
5413 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5414 false, false, Alignment);
5416 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5420 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5422 // Handle AVX2 in-register broadcasts.
5423 if (!IsLoad && Subtarget->hasInt256() &&
5424 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5425 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5427 // The scalar source must be a normal load.
5431 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5432 (Subtarget->hasVLX() && ScalarSize == 64))
5433 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5435 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5436 // double since there is no vbroadcastsd xmm
5437 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5438 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5439 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5442 // Unsupported broadcast.
5446 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5447 /// underlying vector and index.
5449 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5451 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5453 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5454 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5457 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5459 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5461 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5462 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5465 // In this case the vector is the extract_subvector expression and the index
5466 // is 2, as specified by the shuffle.
5467 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5468 SDValue ShuffleVec = SVOp->getOperand(0);
5469 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5470 assert(ShuffleVecVT.getVectorElementType() ==
5471 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5473 int ShuffleIdx = SVOp->getMaskElt(Idx);
5474 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5475 ExtractedFromVec = ShuffleVec;
5481 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5482 MVT VT = Op.getSimpleValueType();
5484 // Skip if insert_vec_elt is not supported.
5485 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5486 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5490 unsigned NumElems = Op.getNumOperands();
5494 SmallVector<unsigned, 4> InsertIndices;
5495 SmallVector<int, 8> Mask(NumElems, -1);
5497 for (unsigned i = 0; i != NumElems; ++i) {
5498 unsigned Opc = Op.getOperand(i).getOpcode();
5500 if (Opc == ISD::UNDEF)
5503 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5504 // Quit if more than 1 elements need inserting.
5505 if (InsertIndices.size() > 1)
5508 InsertIndices.push_back(i);
5512 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5513 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5514 // Quit if non-constant index.
5515 if (!isa<ConstantSDNode>(ExtIdx))
5517 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5519 // Quit if extracted from vector of different type.
5520 if (ExtractedFromVec.getValueType() != VT)
5523 if (!VecIn1.getNode())
5524 VecIn1 = ExtractedFromVec;
5525 else if (VecIn1 != ExtractedFromVec) {
5526 if (!VecIn2.getNode())
5527 VecIn2 = ExtractedFromVec;
5528 else if (VecIn2 != ExtractedFromVec)
5529 // Quit if more than 2 vectors to shuffle
5533 if (ExtractedFromVec == VecIn1)
5535 else if (ExtractedFromVec == VecIn2)
5536 Mask[i] = Idx + NumElems;
5539 if (!VecIn1.getNode())
5542 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5543 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5544 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5545 unsigned Idx = InsertIndices[i];
5546 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5547 DAG.getIntPtrConstant(Idx, DL));
5553 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5554 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5555 Op.getScalarValueSizeInBits() == 1 &&
5556 "Can not convert non-constant vector");
5557 uint64_t Immediate = 0;
5558 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5559 SDValue In = Op.getOperand(idx);
5560 if (In.getOpcode() != ISD::UNDEF)
5561 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5565 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5566 return DAG.getConstant(Immediate, dl, VT);
5568 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5570 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5572 MVT VT = Op.getSimpleValueType();
5573 assert((VT.getVectorElementType() == MVT::i1) &&
5574 "Unexpected type in LowerBUILD_VECTORvXi1!");
5577 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5578 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5579 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5580 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5583 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5584 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5585 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5586 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5589 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5590 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5591 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5592 return DAG.getBitcast(VT, Imm);
5593 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5594 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5595 DAG.getIntPtrConstant(0, dl));
5598 // Vector has one or more non-const elements
5599 uint64_t Immediate = 0;
5600 SmallVector<unsigned, 16> NonConstIdx;
5601 bool IsSplat = true;
5602 bool HasConstElts = false;
5604 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5605 SDValue In = Op.getOperand(idx);
5606 if (In.getOpcode() == ISD::UNDEF)
5608 if (!isa<ConstantSDNode>(In))
5609 NonConstIdx.push_back(idx);
5611 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5612 HasConstElts = true;
5616 else if (In != Op.getOperand(SplatIdx))
5620 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5622 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5623 DAG.getConstant(1, dl, VT),
5624 DAG.getConstant(0, dl, VT));
5626 // insert elements one by one
5630 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5631 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5633 else if (HasConstElts)
5634 Imm = DAG.getConstant(0, dl, VT);
5636 Imm = DAG.getUNDEF(VT);
5637 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5638 DstVec = DAG.getBitcast(VT, Imm);
5640 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5641 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5642 DAG.getIntPtrConstant(0, dl));
5645 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5646 unsigned InsertIdx = NonConstIdx[i];
5647 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5648 Op.getOperand(InsertIdx),
5649 DAG.getIntPtrConstant(InsertIdx, dl));
5654 /// \brief Return true if \p N implements a horizontal binop and return the
5655 /// operands for the horizontal binop into V0 and V1.
5657 /// This is a helper function of LowerToHorizontalOp().
5658 /// This function checks that the build_vector \p N in input implements a
5659 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5660 /// operation to match.
5661 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5662 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5663 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5666 /// This function only analyzes elements of \p N whose indices are
5667 /// in range [BaseIdx, LastIdx).
5668 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5670 unsigned BaseIdx, unsigned LastIdx,
5671 SDValue &V0, SDValue &V1) {
5672 EVT VT = N->getValueType(0);
5674 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5675 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5676 "Invalid Vector in input!");
5678 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5679 bool CanFold = true;
5680 unsigned ExpectedVExtractIdx = BaseIdx;
5681 unsigned NumElts = LastIdx - BaseIdx;
5682 V0 = DAG.getUNDEF(VT);
5683 V1 = DAG.getUNDEF(VT);
5685 // Check if N implements a horizontal binop.
5686 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5687 SDValue Op = N->getOperand(i + BaseIdx);
5690 if (Op->getOpcode() == ISD::UNDEF) {
5691 // Update the expected vector extract index.
5692 if (i * 2 == NumElts)
5693 ExpectedVExtractIdx = BaseIdx;
5694 ExpectedVExtractIdx += 2;
5698 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5703 SDValue Op0 = Op.getOperand(0);
5704 SDValue Op1 = Op.getOperand(1);
5706 // Try to match the following pattern:
5707 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5708 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5709 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5710 Op0.getOperand(0) == Op1.getOperand(0) &&
5711 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5712 isa<ConstantSDNode>(Op1.getOperand(1)));
5716 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5717 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5719 if (i * 2 < NumElts) {
5720 if (V0.getOpcode() == ISD::UNDEF) {
5721 V0 = Op0.getOperand(0);
5722 if (V0.getValueType() != VT)
5726 if (V1.getOpcode() == ISD::UNDEF) {
5727 V1 = Op0.getOperand(0);
5728 if (V1.getValueType() != VT)
5731 if (i * 2 == NumElts)
5732 ExpectedVExtractIdx = BaseIdx;
5735 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5736 if (I0 == ExpectedVExtractIdx)
5737 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5738 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5739 // Try to match the following dag sequence:
5740 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5741 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5745 ExpectedVExtractIdx += 2;
5751 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5752 /// a concat_vector.
5754 /// This is a helper function of LowerToHorizontalOp().
5755 /// This function expects two 256-bit vectors called V0 and V1.
5756 /// At first, each vector is split into two separate 128-bit vectors.
5757 /// Then, the resulting 128-bit vectors are used to implement two
5758 /// horizontal binary operations.
5760 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5762 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5763 /// the two new horizontal binop.
5764 /// When Mode is set, the first horizontal binop dag node would take as input
5765 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5766 /// horizontal binop dag node would take as input the lower 128-bit of V1
5767 /// and the upper 128-bit of V1.
5769 /// HADD V0_LO, V0_HI
5770 /// HADD V1_LO, V1_HI
5772 /// Otherwise, the first horizontal binop dag node takes as input the lower
5773 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5774 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5776 /// HADD V0_LO, V1_LO
5777 /// HADD V0_HI, V1_HI
5779 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5780 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5781 /// the upper 128-bits of the result.
5782 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5783 SDLoc DL, SelectionDAG &DAG,
5784 unsigned X86Opcode, bool Mode,
5785 bool isUndefLO, bool isUndefHI) {
5786 EVT VT = V0.getValueType();
5787 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5788 "Invalid nodes in input!");
5790 unsigned NumElts = VT.getVectorNumElements();
5791 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5792 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5793 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5794 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5795 EVT NewVT = V0_LO.getValueType();
5797 SDValue LO = DAG.getUNDEF(NewVT);
5798 SDValue HI = DAG.getUNDEF(NewVT);
5801 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5802 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5803 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5804 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5805 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5807 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5808 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5809 V1_LO->getOpcode() != ISD::UNDEF))
5810 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5812 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5813 V1_HI->getOpcode() != ISD::UNDEF))
5814 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5817 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5820 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5822 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5823 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5824 EVT VT = BV->getValueType(0);
5825 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5826 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5830 unsigned NumElts = VT.getVectorNumElements();
5831 SDValue InVec0 = DAG.getUNDEF(VT);
5832 SDValue InVec1 = DAG.getUNDEF(VT);
5834 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5835 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5837 // Odd-numbered elements in the input build vector are obtained from
5838 // adding two integer/float elements.
5839 // Even-numbered elements in the input build vector are obtained from
5840 // subtracting two integer/float elements.
5841 unsigned ExpectedOpcode = ISD::FSUB;
5842 unsigned NextExpectedOpcode = ISD::FADD;
5843 bool AddFound = false;
5844 bool SubFound = false;
5846 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5847 SDValue Op = BV->getOperand(i);
5849 // Skip 'undef' values.
5850 unsigned Opcode = Op.getOpcode();
5851 if (Opcode == ISD::UNDEF) {
5852 std::swap(ExpectedOpcode, NextExpectedOpcode);
5856 // Early exit if we found an unexpected opcode.
5857 if (Opcode != ExpectedOpcode)
5860 SDValue Op0 = Op.getOperand(0);
5861 SDValue Op1 = Op.getOperand(1);
5863 // Try to match the following pattern:
5864 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5865 // Early exit if we cannot match that sequence.
5866 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5867 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5868 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5869 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5870 Op0.getOperand(1) != Op1.getOperand(1))
5873 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5877 // We found a valid add/sub node. Update the information accordingly.
5883 // Update InVec0 and InVec1.
5884 if (InVec0.getOpcode() == ISD::UNDEF) {
5885 InVec0 = Op0.getOperand(0);
5886 if (InVec0.getValueType() != VT)
5889 if (InVec1.getOpcode() == ISD::UNDEF) {
5890 InVec1 = Op1.getOperand(0);
5891 if (InVec1.getValueType() != VT)
5895 // Make sure that operands in input to each add/sub node always
5896 // come from a same pair of vectors.
5897 if (InVec0 != Op0.getOperand(0)) {
5898 if (ExpectedOpcode == ISD::FSUB)
5901 // FADD is commutable. Try to commute the operands
5902 // and then test again.
5903 std::swap(Op0, Op1);
5904 if (InVec0 != Op0.getOperand(0))
5908 if (InVec1 != Op1.getOperand(0))
5911 // Update the pair of expected opcodes.
5912 std::swap(ExpectedOpcode, NextExpectedOpcode);
5915 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5916 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5917 InVec1.getOpcode() != ISD::UNDEF)
5918 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5923 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5924 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5925 const X86Subtarget *Subtarget,
5926 SelectionDAG &DAG) {
5927 EVT VT = BV->getValueType(0);
5928 unsigned NumElts = VT.getVectorNumElements();
5929 unsigned NumUndefsLO = 0;
5930 unsigned NumUndefsHI = 0;
5931 unsigned Half = NumElts/2;
5933 // Count the number of UNDEF operands in the build_vector in input.
5934 for (unsigned i = 0, e = Half; i != e; ++i)
5935 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5938 for (unsigned i = Half, e = NumElts; i != e; ++i)
5939 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5942 // Early exit if this is either a build_vector of all UNDEFs or all the
5943 // operands but one are UNDEF.
5944 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5948 SDValue InVec0, InVec1;
5949 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5950 // Try to match an SSE3 float HADD/HSUB.
5951 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5952 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5954 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5955 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5956 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5957 // Try to match an SSSE3 integer HADD/HSUB.
5958 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5959 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5961 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5962 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5965 if (!Subtarget->hasAVX())
5968 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5969 // Try to match an AVX horizontal add/sub of packed single/double
5970 // precision floating point values from 256-bit vectors.
5971 SDValue InVec2, InVec3;
5972 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5973 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5974 ((InVec0.getOpcode() == ISD::UNDEF ||
5975 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5976 ((InVec1.getOpcode() == ISD::UNDEF ||
5977 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5978 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5980 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5981 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5982 ((InVec0.getOpcode() == ISD::UNDEF ||
5983 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5984 ((InVec1.getOpcode() == ISD::UNDEF ||
5985 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5986 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5987 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5988 // Try to match an AVX2 horizontal add/sub of signed integers.
5989 SDValue InVec2, InVec3;
5991 bool CanFold = true;
5993 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5994 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5995 ((InVec0.getOpcode() == ISD::UNDEF ||
5996 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5997 ((InVec1.getOpcode() == ISD::UNDEF ||
5998 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5999 X86Opcode = X86ISD::HADD;
6000 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6001 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6002 ((InVec0.getOpcode() == ISD::UNDEF ||
6003 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6004 ((InVec1.getOpcode() == ISD::UNDEF ||
6005 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6006 X86Opcode = X86ISD::HSUB;
6011 // Fold this build_vector into a single horizontal add/sub.
6012 // Do this only if the target has AVX2.
6013 if (Subtarget->hasAVX2())
6014 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6016 // Do not try to expand this build_vector into a pair of horizontal
6017 // add/sub if we can emit a pair of scalar add/sub.
6018 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6021 // Convert this build_vector into a pair of horizontal binop followed by
6023 bool isUndefLO = NumUndefsLO == Half;
6024 bool isUndefHI = NumUndefsHI == Half;
6025 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6026 isUndefLO, isUndefHI);
6030 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6031 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6033 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6034 X86Opcode = X86ISD::HADD;
6035 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6036 X86Opcode = X86ISD::HSUB;
6037 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6038 X86Opcode = X86ISD::FHADD;
6039 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6040 X86Opcode = X86ISD::FHSUB;
6044 // Don't try to expand this build_vector into a pair of horizontal add/sub
6045 // if we can simply emit a pair of scalar add/sub.
6046 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6049 // Convert this build_vector into two horizontal add/sub followed by
6051 bool isUndefLO = NumUndefsLO == Half;
6052 bool isUndefHI = NumUndefsHI == Half;
6053 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6054 isUndefLO, isUndefHI);
6061 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6064 MVT VT = Op.getSimpleValueType();
6065 MVT ExtVT = VT.getVectorElementType();
6066 unsigned NumElems = Op.getNumOperands();
6068 // Generate vectors for predicate vectors.
6069 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6070 return LowerBUILD_VECTORvXi1(Op, DAG);
6072 // Vectors containing all zeros can be matched by pxor and xorps later
6073 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6074 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6075 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6076 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6079 return getZeroVector(VT, Subtarget, DAG, dl);
6082 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6083 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6084 // vpcmpeqd on 256-bit vectors.
6085 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6086 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6089 if (!VT.is512BitVector())
6090 return getOnesVector(VT, Subtarget, DAG, dl);
6093 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6094 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6096 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6097 return HorizontalOp;
6098 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6101 unsigned EVTBits = ExtVT.getSizeInBits();
6103 unsigned NumZero = 0;
6104 unsigned NumNonZero = 0;
6105 unsigned NonZeros = 0;
6106 bool IsAllConstants = true;
6107 SmallSet<SDValue, 8> Values;
6108 for (unsigned i = 0; i < NumElems; ++i) {
6109 SDValue Elt = Op.getOperand(i);
6110 if (Elt.getOpcode() == ISD::UNDEF)
6113 if (Elt.getOpcode() != ISD::Constant &&
6114 Elt.getOpcode() != ISD::ConstantFP)
6115 IsAllConstants = false;
6116 if (X86::isZeroNode(Elt))
6119 NonZeros |= (1 << i);
6124 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6125 if (NumNonZero == 0)
6126 return DAG.getUNDEF(VT);
6128 // Special case for single non-zero, non-undef, element.
6129 if (NumNonZero == 1) {
6130 unsigned Idx = countTrailingZeros(NonZeros);
6131 SDValue Item = Op.getOperand(Idx);
6133 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6134 // the value are obviously zero, truncate the value to i32 and do the
6135 // insertion that way. Only do this if the value is non-constant or if the
6136 // value is a constant being inserted into element 0. It is cheaper to do
6137 // a constant pool load than it is to do a movd + shuffle.
6138 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6139 (!IsAllConstants || Idx == 0)) {
6140 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6142 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6143 EVT VecVT = MVT::v4i32;
6145 // Truncate the value (which may itself be a constant) to i32, and
6146 // convert it to a vector with movd (S2V+shuffle to zero extend).
6147 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6149 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6150 Item, Idx * 2, true, Subtarget, DAG));
6154 // If we have a constant or non-constant insertion into the low element of
6155 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6156 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6157 // depending on what the source datatype is.
6160 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6162 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6163 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6164 if (VT.is512BitVector()) {
6165 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6166 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6167 Item, DAG.getIntPtrConstant(0, dl));
6169 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6170 "Expected an SSE value type!");
6171 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6172 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6173 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6176 // We can't directly insert an i8 or i16 into a vector, so zero extend
6178 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6179 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6180 if (VT.is256BitVector()) {
6181 if (Subtarget->hasAVX()) {
6182 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6183 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6185 // Without AVX, we need to extend to a 128-bit vector and then
6186 // insert into the 256-bit vector.
6187 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6188 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6189 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6192 assert(VT.is128BitVector() && "Expected an SSE value type!");
6193 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6194 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6196 return DAG.getBitcast(VT, Item);
6200 // Is it a vector logical left shift?
6201 if (NumElems == 2 && Idx == 1 &&
6202 X86::isZeroNode(Op.getOperand(0)) &&
6203 !X86::isZeroNode(Op.getOperand(1))) {
6204 unsigned NumBits = VT.getSizeInBits();
6205 return getVShift(true, VT,
6206 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6207 VT, Op.getOperand(1)),
6208 NumBits/2, DAG, *this, dl);
6211 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6214 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6215 // is a non-constant being inserted into an element other than the low one,
6216 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6217 // movd/movss) to move this into the low element, then shuffle it into
6219 if (EVTBits == 32) {
6220 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6221 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6225 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6226 if (Values.size() == 1) {
6227 if (EVTBits == 32) {
6228 // Instead of a shuffle like this:
6229 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6230 // Check if it's possible to issue this instead.
6231 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6232 unsigned Idx = countTrailingZeros(NonZeros);
6233 SDValue Item = Op.getOperand(Idx);
6234 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6235 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6240 // A vector full of immediates; various special cases are already
6241 // handled, so this is best done with a single constant-pool load.
6245 // For AVX-length vectors, see if we can use a vector load to get all of the
6246 // elements, otherwise build the individual 128-bit pieces and use
6247 // shuffles to put them in place.
6248 if (VT.is256BitVector() || VT.is512BitVector()) {
6249 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6251 // Check for a build vector of consecutive loads.
6252 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6255 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6257 // Build both the lower and upper subvector.
6258 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6259 makeArrayRef(&V[0], NumElems/2));
6260 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6261 makeArrayRef(&V[NumElems / 2], NumElems/2));
6263 // Recreate the wider vector with the lower and upper part.
6264 if (VT.is256BitVector())
6265 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6266 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6269 // Let legalizer expand 2-wide build_vectors.
6270 if (EVTBits == 64) {
6271 if (NumNonZero == 1) {
6272 // One half is zero or undef.
6273 unsigned Idx = countTrailingZeros(NonZeros);
6274 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6275 Op.getOperand(Idx));
6276 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6281 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6282 if (EVTBits == 8 && NumElems == 16)
6283 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6287 if (EVTBits == 16 && NumElems == 8)
6288 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6292 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6293 if (EVTBits == 32 && NumElems == 4)
6294 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6297 // If element VT is == 32 bits, turn it into a number of shuffles.
6298 SmallVector<SDValue, 8> V(NumElems);
6299 if (NumElems == 4 && NumZero > 0) {
6300 for (unsigned i = 0; i < 4; ++i) {
6301 bool isZero = !(NonZeros & (1 << i));
6303 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6305 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6308 for (unsigned i = 0; i < 2; ++i) {
6309 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6312 V[i] = V[i*2]; // Must be a zero vector.
6315 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6318 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6321 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6326 bool Reverse1 = (NonZeros & 0x3) == 2;
6327 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6331 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6332 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6334 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6337 if (Values.size() > 1 && VT.is128BitVector()) {
6338 // Check for a build vector of consecutive loads.
6339 for (unsigned i = 0; i < NumElems; ++i)
6340 V[i] = Op.getOperand(i);
6342 // Check for elements which are consecutive loads.
6343 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6346 // Check for a build vector from mostly shuffle plus few inserting.
6347 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6350 // For SSE 4.1, use insertps to put the high elements into the low element.
6351 if (Subtarget->hasSSE41()) {
6353 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6354 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6356 Result = DAG.getUNDEF(VT);
6358 for (unsigned i = 1; i < NumElems; ++i) {
6359 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6360 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6361 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6366 // Otherwise, expand into a number of unpckl*, start by extending each of
6367 // our (non-undef) elements to the full vector width with the element in the
6368 // bottom slot of the vector (which generates no code for SSE).
6369 for (unsigned i = 0; i < NumElems; ++i) {
6370 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6371 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6373 V[i] = DAG.getUNDEF(VT);
6376 // Next, we iteratively mix elements, e.g. for v4f32:
6377 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6378 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6379 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6380 unsigned EltStride = NumElems >> 1;
6381 while (EltStride != 0) {
6382 for (unsigned i = 0; i < EltStride; ++i) {
6383 // If V[i+EltStride] is undef and this is the first round of mixing,
6384 // then it is safe to just drop this shuffle: V[i] is already in the
6385 // right place, the one element (since it's the first round) being
6386 // inserted as undef can be dropped. This isn't safe for successive
6387 // rounds because they will permute elements within both vectors.
6388 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6389 EltStride == NumElems/2)
6392 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6401 // 256-bit AVX can use the vinsertf128 instruction
6402 // to create 256-bit vectors from two other 128-bit ones.
6403 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6405 MVT ResVT = Op.getSimpleValueType();
6407 assert((ResVT.is256BitVector() ||
6408 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6410 SDValue V1 = Op.getOperand(0);
6411 SDValue V2 = Op.getOperand(1);
6412 unsigned NumElems = ResVT.getVectorNumElements();
6413 if (ResVT.is256BitVector())
6414 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6416 if (Op.getNumOperands() == 4) {
6417 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6418 ResVT.getVectorNumElements()/2);
6419 SDValue V3 = Op.getOperand(2);
6420 SDValue V4 = Op.getOperand(3);
6421 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6422 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6424 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6427 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6428 const X86Subtarget *Subtarget,
6429 SelectionDAG & DAG) {
6431 MVT ResVT = Op.getSimpleValueType();
6432 unsigned NumOfOperands = Op.getNumOperands();
6434 assert(isPowerOf2_32(NumOfOperands) &&
6435 "Unexpected number of operands in CONCAT_VECTORS");
6437 if (NumOfOperands > 2) {
6438 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6439 ResVT.getVectorNumElements()/2);
6440 SmallVector<SDValue, 2> Ops;
6441 for (unsigned i = 0; i < NumOfOperands/2; i++)
6442 Ops.push_back(Op.getOperand(i));
6443 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6445 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6446 Ops.push_back(Op.getOperand(i));
6447 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6448 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6451 SDValue V1 = Op.getOperand(0);
6452 SDValue V2 = Op.getOperand(1);
6453 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6454 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6456 if (IsZeroV1 && IsZeroV2)
6457 return getZeroVector(ResVT, Subtarget, DAG, dl);
6459 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6460 SDValue Undef = DAG.getUNDEF(ResVT);
6461 unsigned NumElems = ResVT.getVectorNumElements();
6462 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6464 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6465 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6469 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6470 // Zero the upper bits of V1
6471 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6472 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6475 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6478 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6479 const X86Subtarget *Subtarget,
6480 SelectionDAG &DAG) {
6481 MVT VT = Op.getSimpleValueType();
6482 if (VT.getVectorElementType() == MVT::i1)
6483 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6485 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6486 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6487 Op.getNumOperands() == 4)));
6489 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6490 // from two other 128-bit ones.
6492 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6493 return LowerAVXCONCAT_VECTORS(Op, DAG);
6496 //===----------------------------------------------------------------------===//
6497 // Vector shuffle lowering
6499 // This is an experimental code path for lowering vector shuffles on x86. It is
6500 // designed to handle arbitrary vector shuffles and blends, gracefully
6501 // degrading performance as necessary. It works hard to recognize idiomatic
6502 // shuffles and lower them to optimal instruction patterns without leaving
6503 // a framework that allows reasonably efficient handling of all vector shuffle
6505 //===----------------------------------------------------------------------===//
6507 /// \brief Tiny helper function to identify a no-op mask.
6509 /// This is a somewhat boring predicate function. It checks whether the mask
6510 /// array input, which is assumed to be a single-input shuffle mask of the kind
6511 /// used by the X86 shuffle instructions (not a fully general
6512 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6513 /// in-place shuffle are 'no-op's.
6514 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6515 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6516 if (Mask[i] != -1 && Mask[i] != i)
6521 /// \brief Helper function to classify a mask as a single-input mask.
6523 /// This isn't a generic single-input test because in the vector shuffle
6524 /// lowering we canonicalize single inputs to be the first input operand. This
6525 /// means we can more quickly test for a single input by only checking whether
6526 /// an input from the second operand exists. We also assume that the size of
6527 /// mask corresponds to the size of the input vectors which isn't true in the
6528 /// fully general case.
6529 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6531 if (M >= (int)Mask.size())
6536 /// \brief Test whether there are elements crossing 128-bit lanes in this
6539 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6540 /// and we routinely test for these.
6541 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6542 int LaneSize = 128 / VT.getScalarSizeInBits();
6543 int Size = Mask.size();
6544 for (int i = 0; i < Size; ++i)
6545 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6550 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6552 /// This checks a shuffle mask to see if it is performing the same
6553 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6554 /// that it is also not lane-crossing. It may however involve a blend from the
6555 /// same lane of a second vector.
6557 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6558 /// non-trivial to compute in the face of undef lanes. The representation is
6559 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6560 /// entries from both V1 and V2 inputs to the wider mask.
6562 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6563 SmallVectorImpl<int> &RepeatedMask) {
6564 int LaneSize = 128 / VT.getScalarSizeInBits();
6565 RepeatedMask.resize(LaneSize, -1);
6566 int Size = Mask.size();
6567 for (int i = 0; i < Size; ++i) {
6570 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6571 // This entry crosses lanes, so there is no way to model this shuffle.
6574 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6575 if (RepeatedMask[i % LaneSize] == -1)
6576 // This is the first non-undef entry in this slot of a 128-bit lane.
6577 RepeatedMask[i % LaneSize] =
6578 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6579 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6580 // Found a mismatch with the repeated mask.
6586 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6589 /// This is a fast way to test a shuffle mask against a fixed pattern:
6591 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6593 /// It returns true if the mask is exactly as wide as the argument list, and
6594 /// each element of the mask is either -1 (signifying undef) or the value given
6595 /// in the argument.
6596 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6597 ArrayRef<int> ExpectedMask) {
6598 if (Mask.size() != ExpectedMask.size())
6601 int Size = Mask.size();
6603 // If the values are build vectors, we can look through them to find
6604 // equivalent inputs that make the shuffles equivalent.
6605 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6606 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6608 for (int i = 0; i < Size; ++i)
6609 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6610 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6611 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6612 if (!MaskBV || !ExpectedBV ||
6613 MaskBV->getOperand(Mask[i] % Size) !=
6614 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6621 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6623 /// This helper function produces an 8-bit shuffle immediate corresponding to
6624 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6625 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6628 /// NB: We rely heavily on "undef" masks preserving the input lane.
6629 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6630 SelectionDAG &DAG) {
6631 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6632 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6633 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6634 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6635 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6638 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6639 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6640 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6641 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6642 return DAG.getConstant(Imm, DL, MVT::i8);
6645 /// \brief Compute whether each element of a shuffle is zeroable.
6647 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6648 /// Either it is an undef element in the shuffle mask, the element of the input
6649 /// referenced is undef, or the element of the input referenced is known to be
6650 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6651 /// as many lanes with this technique as possible to simplify the remaining
6653 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6654 SDValue V1, SDValue V2) {
6655 SmallBitVector Zeroable(Mask.size(), false);
6657 while (V1.getOpcode() == ISD::BITCAST)
6658 V1 = V1->getOperand(0);
6659 while (V2.getOpcode() == ISD::BITCAST)
6660 V2 = V2->getOperand(0);
6662 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6663 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6665 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6667 // Handle the easy cases.
6668 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6673 // If this is an index into a build_vector node (which has the same number
6674 // of elements), dig out the input value and use it.
6675 SDValue V = M < Size ? V1 : V2;
6676 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6679 SDValue Input = V.getOperand(M % Size);
6680 // The UNDEF opcode check really should be dead code here, but not quite
6681 // worth asserting on (it isn't invalid, just unexpected).
6682 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6689 // X86 has dedicated unpack instructions that can handle specific blend
6690 // operations: UNPCKH and UNPCKL.
6691 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6692 SDValue V1, SDValue V2,
6693 SelectionDAG &DAG) {
6694 int NumElts = VT.getVectorNumElements();
6697 bool UnpcklSwapped = true;
6698 bool UnpckhSwapped = true;
6699 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6701 for (int i = 0; i < NumElts; ++i) {
6702 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6704 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6705 int HiPos = LoPos + NumEltsInLane / 2;
6706 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6707 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6711 if (Mask[i] != LoPos)
6713 if (Mask[i] != HiPos)
6715 if (Mask[i] != LoPosSwapped)
6716 UnpcklSwapped = false;
6717 if (Mask[i] != HiPosSwapped)
6718 UnpckhSwapped = false;
6719 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6723 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6725 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6727 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6729 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6731 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6735 /// \brief Try to emit a bitmask instruction for a shuffle.
6737 /// This handles cases where we can model a blend exactly as a bitmask due to
6738 /// one of the inputs being zeroable.
6739 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6740 SDValue V2, ArrayRef<int> Mask,
6741 SelectionDAG &DAG) {
6742 MVT EltVT = VT.getScalarType();
6743 int NumEltBits = EltVT.getSizeInBits();
6744 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6745 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6746 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6748 if (EltVT.isFloatingPoint()) {
6749 Zero = DAG.getBitcast(EltVT, Zero);
6750 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6752 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6753 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6755 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6758 if (Mask[i] % Size != i)
6759 return SDValue(); // Not a blend.
6761 V = Mask[i] < Size ? V1 : V2;
6762 else if (V != (Mask[i] < Size ? V1 : V2))
6763 return SDValue(); // Can only let one input through the mask.
6765 VMaskOps[i] = AllOnes;
6768 return SDValue(); // No non-zeroable elements!
6770 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6771 V = DAG.getNode(VT.isFloatingPoint()
6772 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6777 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6779 /// This is used as a fallback approach when first class blend instructions are
6780 /// unavailable. Currently it is only suitable for integer vectors, but could
6781 /// be generalized for floating point vectors if desirable.
6782 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6783 SDValue V2, ArrayRef<int> Mask,
6784 SelectionDAG &DAG) {
6785 assert(VT.isInteger() && "Only supports integer vector types!");
6786 MVT EltVT = VT.getScalarType();
6787 int NumEltBits = EltVT.getSizeInBits();
6788 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6789 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6791 SmallVector<SDValue, 16> MaskOps;
6792 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6793 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6794 return SDValue(); // Shuffled input!
6795 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6798 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6799 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6800 // We have to cast V2 around.
6801 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6802 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6803 DAG.getBitcast(MaskVT, V1Mask),
6804 DAG.getBitcast(MaskVT, V2)));
6805 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6808 /// \brief Try to emit a blend instruction for a shuffle.
6810 /// This doesn't do any checks for the availability of instructions for blending
6811 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6812 /// be matched in the backend with the type given. What it does check for is
6813 /// that the shuffle mask is in fact a blend.
6814 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6815 SDValue V2, ArrayRef<int> Mask,
6816 const X86Subtarget *Subtarget,
6817 SelectionDAG &DAG) {
6818 unsigned BlendMask = 0;
6819 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6820 if (Mask[i] >= Size) {
6821 if (Mask[i] != i + Size)
6822 return SDValue(); // Shuffled V2 input!
6823 BlendMask |= 1u << i;
6826 if (Mask[i] >= 0 && Mask[i] != i)
6827 return SDValue(); // Shuffled V1 input!
6829 switch (VT.SimpleTy) {
6834 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6835 DAG.getConstant(BlendMask, DL, MVT::i8));
6839 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6843 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6844 // that instruction.
6845 if (Subtarget->hasAVX2()) {
6846 // Scale the blend by the number of 32-bit dwords per element.
6847 int Scale = VT.getScalarSizeInBits() / 32;
6849 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6850 if (Mask[i] >= Size)
6851 for (int j = 0; j < Scale; ++j)
6852 BlendMask |= 1u << (i * Scale + j);
6854 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6855 V1 = DAG.getBitcast(BlendVT, V1);
6856 V2 = DAG.getBitcast(BlendVT, V2);
6857 return DAG.getBitcast(
6858 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6859 DAG.getConstant(BlendMask, DL, MVT::i8)));
6863 // For integer shuffles we need to expand the mask and cast the inputs to
6864 // v8i16s prior to blending.
6865 int Scale = 8 / VT.getVectorNumElements();
6867 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6868 if (Mask[i] >= Size)
6869 for (int j = 0; j < Scale; ++j)
6870 BlendMask |= 1u << (i * Scale + j);
6872 V1 = DAG.getBitcast(MVT::v8i16, V1);
6873 V2 = DAG.getBitcast(MVT::v8i16, V2);
6874 return DAG.getBitcast(VT,
6875 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6876 DAG.getConstant(BlendMask, DL, MVT::i8)));
6880 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6881 SmallVector<int, 8> RepeatedMask;
6882 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6883 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6884 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6886 for (int i = 0; i < 8; ++i)
6887 if (RepeatedMask[i] >= 16)
6888 BlendMask |= 1u << i;
6889 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6890 DAG.getConstant(BlendMask, DL, MVT::i8));
6896 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6897 "256-bit byte-blends require AVX2 support!");
6899 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6900 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6903 // Scale the blend by the number of bytes per element.
6904 int Scale = VT.getScalarSizeInBits() / 8;
6906 // This form of blend is always done on bytes. Compute the byte vector
6908 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6910 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6911 // mix of LLVM's code generator and the x86 backend. We tell the code
6912 // generator that boolean values in the elements of an x86 vector register
6913 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6914 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6915 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6916 // of the element (the remaining are ignored) and 0 in that high bit would
6917 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6918 // the LLVM model for boolean values in vector elements gets the relevant
6919 // bit set, it is set backwards and over constrained relative to x86's
6921 SmallVector<SDValue, 32> VSELECTMask;
6922 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6923 for (int j = 0; j < Scale; ++j)
6924 VSELECTMask.push_back(
6925 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6926 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6929 V1 = DAG.getBitcast(BlendVT, V1);
6930 V2 = DAG.getBitcast(BlendVT, V2);
6931 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6932 DAG.getNode(ISD::BUILD_VECTOR, DL,
6933 BlendVT, VSELECTMask),
6938 llvm_unreachable("Not a supported integer vector type!");
6942 /// \brief Try to lower as a blend of elements from two inputs followed by
6943 /// a single-input permutation.
6945 /// This matches the pattern where we can blend elements from two inputs and
6946 /// then reduce the shuffle to a single-input permutation.
6947 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6950 SelectionDAG &DAG) {
6951 // We build up the blend mask while checking whether a blend is a viable way
6952 // to reduce the shuffle.
6953 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6954 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6956 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6960 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6962 if (BlendMask[Mask[i] % Size] == -1)
6963 BlendMask[Mask[i] % Size] = Mask[i];
6964 else if (BlendMask[Mask[i] % Size] != Mask[i])
6965 return SDValue(); // Can't blend in the needed input!
6967 PermuteMask[i] = Mask[i] % Size;
6970 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6971 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6974 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6975 /// blends and permutes.
6977 /// This matches the extremely common pattern for handling combined
6978 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6979 /// operations. It will try to pick the best arrangement of shuffles and
6981 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6985 SelectionDAG &DAG) {
6986 // Shuffle the input elements into the desired positions in V1 and V2 and
6987 // blend them together.
6988 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6989 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6990 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6991 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6992 if (Mask[i] >= 0 && Mask[i] < Size) {
6993 V1Mask[i] = Mask[i];
6995 } else if (Mask[i] >= Size) {
6996 V2Mask[i] = Mask[i] - Size;
6997 BlendMask[i] = i + Size;
7000 // Try to lower with the simpler initial blend strategy unless one of the
7001 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7002 // shuffle may be able to fold with a load or other benefit. However, when
7003 // we'll have to do 2x as many shuffles in order to achieve this, blending
7004 // first is a better strategy.
7005 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7006 if (SDValue BlendPerm =
7007 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7010 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7011 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7012 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7015 /// \brief Try to lower a vector shuffle as a byte rotation.
7017 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7018 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7019 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7020 /// try to generically lower a vector shuffle through such an pattern. It
7021 /// does not check for the profitability of lowering either as PALIGNR or
7022 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7023 /// This matches shuffle vectors that look like:
7025 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7027 /// Essentially it concatenates V1 and V2, shifts right by some number of
7028 /// elements, and takes the low elements as the result. Note that while this is
7029 /// specified as a *right shift* because x86 is little-endian, it is a *left
7030 /// rotate* of the vector lanes.
7031 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7034 const X86Subtarget *Subtarget,
7035 SelectionDAG &DAG) {
7036 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7038 int NumElts = Mask.size();
7039 int NumLanes = VT.getSizeInBits() / 128;
7040 int NumLaneElts = NumElts / NumLanes;
7042 // We need to detect various ways of spelling a rotation:
7043 // [11, 12, 13, 14, 15, 0, 1, 2]
7044 // [-1, 12, 13, 14, -1, -1, 1, -1]
7045 // [-1, -1, -1, -1, -1, -1, 1, 2]
7046 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7047 // [-1, 4, 5, 6, -1, -1, 9, -1]
7048 // [-1, 4, 5, 6, -1, -1, -1, -1]
7051 for (int l = 0; l < NumElts; l += NumLaneElts) {
7052 for (int i = 0; i < NumLaneElts; ++i) {
7053 if (Mask[l + i] == -1)
7055 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7057 // Get the mod-Size index and lane correct it.
7058 int LaneIdx = (Mask[l + i] % NumElts) - l;
7059 // Make sure it was in this lane.
7060 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7063 // Determine where a rotated vector would have started.
7064 int StartIdx = i - LaneIdx;
7066 // The identity rotation isn't interesting, stop.
7069 // If we found the tail of a vector the rotation must be the missing
7070 // front. If we found the head of a vector, it must be how much of the
7072 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7075 Rotation = CandidateRotation;
7076 else if (Rotation != CandidateRotation)
7077 // The rotations don't match, so we can't match this mask.
7080 // Compute which value this mask is pointing at.
7081 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7083 // Compute which of the two target values this index should be assigned
7084 // to. This reflects whether the high elements are remaining or the low
7085 // elements are remaining.
7086 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7088 // Either set up this value if we've not encountered it before, or check
7089 // that it remains consistent.
7092 else if (TargetV != MaskV)
7093 // This may be a rotation, but it pulls from the inputs in some
7094 // unsupported interleaving.
7099 // Check that we successfully analyzed the mask, and normalize the results.
7100 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7101 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7107 // The actual rotate instruction rotates bytes, so we need to scale the
7108 // rotation based on how many bytes are in the vector lane.
7109 int Scale = 16 / NumLaneElts;
7111 // SSSE3 targets can use the palignr instruction.
7112 if (Subtarget->hasSSSE3()) {
7113 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7114 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7115 Lo = DAG.getBitcast(AlignVT, Lo);
7116 Hi = DAG.getBitcast(AlignVT, Hi);
7118 return DAG.getBitcast(
7119 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7120 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7123 assert(VT.getSizeInBits() == 128 &&
7124 "Rotate-based lowering only supports 128-bit lowering!");
7125 assert(Mask.size() <= 16 &&
7126 "Can shuffle at most 16 bytes in a 128-bit vector!");
7128 // Default SSE2 implementation
7129 int LoByteShift = 16 - Rotation * Scale;
7130 int HiByteShift = Rotation * Scale;
7132 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7133 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7134 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7136 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7137 DAG.getConstant(LoByteShift, DL, MVT::i8));
7138 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7139 DAG.getConstant(HiByteShift, DL, MVT::i8));
7140 return DAG.getBitcast(VT,
7141 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7144 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7146 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7147 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7148 /// matches elements from one of the input vectors shuffled to the left or
7149 /// right with zeroable elements 'shifted in'. It handles both the strictly
7150 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7153 /// PSHL : (little-endian) left bit shift.
7154 /// [ zz, 0, zz, 2 ]
7155 /// [ -1, 4, zz, -1 ]
7156 /// PSRL : (little-endian) right bit shift.
7158 /// [ -1, -1, 7, zz]
7159 /// PSLLDQ : (little-endian) left byte shift
7160 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7161 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7162 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7163 /// PSRLDQ : (little-endian) right byte shift
7164 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7165 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7166 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7167 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7168 SDValue V2, ArrayRef<int> Mask,
7169 SelectionDAG &DAG) {
7170 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7172 int Size = Mask.size();
7173 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7175 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7176 for (int i = 0; i < Size; i += Scale)
7177 for (int j = 0; j < Shift; ++j)
7178 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7184 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7185 for (int i = 0; i != Size; i += Scale) {
7186 unsigned Pos = Left ? i + Shift : i;
7187 unsigned Low = Left ? i : i + Shift;
7188 unsigned Len = Scale - Shift;
7189 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7190 Low + (V == V1 ? 0 : Size)))
7194 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7195 bool ByteShift = ShiftEltBits > 64;
7196 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7197 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7198 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7200 // Normalize the scale for byte shifts to still produce an i64 element
7202 Scale = ByteShift ? Scale / 2 : Scale;
7204 // We need to round trip through the appropriate type for the shift.
7205 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7206 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7207 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7208 "Illegal integer vector type");
7209 V = DAG.getBitcast(ShiftVT, V);
7211 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7212 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7213 return DAG.getBitcast(VT, V);
7216 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7217 // keep doubling the size of the integer elements up to that. We can
7218 // then shift the elements of the integer vector by whole multiples of
7219 // their width within the elements of the larger integer vector. Test each
7220 // multiple to see if we can find a match with the moved element indices
7221 // and that the shifted in elements are all zeroable.
7222 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7223 for (int Shift = 1; Shift != Scale; ++Shift)
7224 for (bool Left : {true, false})
7225 if (CheckZeros(Shift, Scale, Left))
7226 for (SDValue V : {V1, V2})
7227 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7234 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7235 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7236 SDValue V2, ArrayRef<int> Mask,
7237 SelectionDAG &DAG) {
7238 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7239 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7241 int Size = Mask.size();
7242 int HalfSize = Size / 2;
7243 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7245 // Upper half must be undefined.
7246 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7249 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7250 // Remainder of lower half result is zero and upper half is all undef.
7251 auto LowerAsEXTRQ = [&]() {
7252 // Determine the extraction length from the part of the
7253 // lower half that isn't zeroable.
7255 for (; Len >= 0; --Len)
7256 if (!Zeroable[Len - 1])
7258 assert(Len > 0 && "Zeroable shuffle mask");
7260 // Attempt to match first Len sequential elements from the lower half.
7263 for (int i = 0; i != Len; ++i) {
7267 SDValue &V = (M < Size ? V1 : V2);
7270 // All mask elements must be in the lower half.
7274 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7285 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7286 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7287 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7288 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7289 DAG.getConstant(BitLen, DL, MVT::i8),
7290 DAG.getConstant(BitIdx, DL, MVT::i8));
7293 if (SDValue ExtrQ = LowerAsEXTRQ())
7296 // INSERTQ: Extract lowest Len elements from lower half of second source and
7297 // insert over first source, starting at Idx.
7298 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7299 auto LowerAsInsertQ = [&]() {
7300 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7303 // Attempt to match first source from mask before insertion point.
7304 if (isUndefInRange(Mask, 0, Idx)) {
7306 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7308 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7314 // Extend the extraction length looking to match both the insertion of
7315 // the second source and the remaining elements of the first.
7316 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7321 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7323 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7329 // Match the remaining elements of the lower half.
7330 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7332 } else if ((!Base || (Base == V1)) &&
7333 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7335 } else if ((!Base || (Base == V2)) &&
7336 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7343 // We may not have a base (first source) - this can safely be undefined.
7345 Base = DAG.getUNDEF(VT);
7347 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7348 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7349 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7350 DAG.getConstant(BitLen, DL, MVT::i8),
7351 DAG.getConstant(BitIdx, DL, MVT::i8));
7358 if (SDValue InsertQ = LowerAsInsertQ())
7364 /// \brief Lower a vector shuffle as a zero or any extension.
7366 /// Given a specific number of elements, element bit width, and extension
7367 /// stride, produce either a zero or any extension based on the available
7368 /// features of the subtarget. The extended elements are consecutive and
7369 /// begin and can start from an offseted element index in the input; to
7370 /// avoid excess shuffling the offset must either being in the bottom lane
7371 /// or at the start of a higher lane. All extended elements must be from
7373 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7374 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7375 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7376 assert(Scale > 1 && "Need a scale to extend.");
7377 int EltBits = VT.getScalarSizeInBits();
7378 int NumElements = VT.getVectorNumElements();
7379 int NumEltsPerLane = 128 / EltBits;
7380 int OffsetLane = Offset / NumEltsPerLane;
7381 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7382 "Only 8, 16, and 32 bit elements can be extended.");
7383 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7384 assert(0 <= Offset && "Extension offset must be positive.");
7385 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7386 "Extension offset must be in the first lane or start an upper lane.");
7388 // Check that an index is in same lane as the base offset.
7389 auto SafeOffset = [&](int Idx) {
7390 return OffsetLane == (Idx / NumEltsPerLane);
7393 // Shift along an input so that the offset base moves to the first element.
7394 auto ShuffleOffset = [&](SDValue V) {
7398 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7399 for (int i = 0; i * Scale < NumElements; ++i) {
7400 int SrcIdx = i + Offset;
7401 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7403 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7406 // Found a valid zext mask! Try various lowering strategies based on the
7407 // input type and available ISA extensions.
7408 if (Subtarget->hasSSE41()) {
7409 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7410 // PUNPCK will catch this in a later shuffle match.
7411 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7413 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7414 NumElements / Scale);
7415 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7416 return DAG.getBitcast(VT, InputV);
7419 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7421 // For any extends we can cheat for larger element sizes and use shuffle
7422 // instructions that can fold with a load and/or copy.
7423 if (AnyExt && EltBits == 32) {
7424 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7426 return DAG.getBitcast(
7427 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7428 DAG.getBitcast(MVT::v4i32, InputV),
7429 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7431 if (AnyExt && EltBits == 16 && Scale > 2) {
7432 int PSHUFDMask[4] = {Offset / 2, -1,
7433 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7434 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7435 DAG.getBitcast(MVT::v4i32, InputV),
7436 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7437 int PSHUFWMask[4] = {1, -1, -1, -1};
7438 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7439 return DAG.getBitcast(
7440 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7441 DAG.getBitcast(MVT::v8i16, InputV),
7442 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7445 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7447 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7448 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7449 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7451 int LoIdx = Offset * EltBits;
7452 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7453 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7454 DAG.getConstant(EltBits, DL, MVT::i8),
7455 DAG.getConstant(LoIdx, DL, MVT::i8)));
7457 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7458 !SafeOffset(Offset + 1))
7459 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7461 int HiIdx = (Offset + 1) * EltBits;
7462 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7463 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7464 DAG.getConstant(EltBits, DL, MVT::i8),
7465 DAG.getConstant(HiIdx, DL, MVT::i8)));
7466 return DAG.getNode(ISD::BITCAST, DL, VT,
7467 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7470 // If this would require more than 2 unpack instructions to expand, use
7471 // pshufb when available. We can only use more than 2 unpack instructions
7472 // when zero extending i8 elements which also makes it easier to use pshufb.
7473 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7474 assert(NumElements == 16 && "Unexpected byte vector width!");
7475 SDValue PSHUFBMask[16];
7476 for (int i = 0; i < 16; ++i) {
7477 int Idx = Offset + (i / Scale);
7478 PSHUFBMask[i] = DAG.getConstant(
7479 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7481 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7482 return DAG.getBitcast(VT,
7483 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7484 DAG.getNode(ISD::BUILD_VECTOR, DL,
7485 MVT::v16i8, PSHUFBMask)));
7488 // If we are extending from an (odd)offset, shuffle them by 1 element.
7490 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7491 for (int i = 1; i < NumElements; ++i)
7493 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7497 // Otherwise emit a sequence of unpacks.
7499 unsigned UnpackLoHi = X86ISD::UNPCKL;
7500 if (Offset >= (NumElements / 2)) {
7501 UnpackLoHi = X86ISD::UNPCKH;
7502 Offset -= (NumElements / 2);
7505 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7506 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7507 : getZeroVector(InputVT, Subtarget, DAG, DL);
7508 InputV = DAG.getBitcast(InputVT, InputV);
7509 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7513 } while (Scale > 1);
7514 return DAG.getBitcast(VT, InputV);
7517 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7519 /// This routine will try to do everything in its power to cleverly lower
7520 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7521 /// check for the profitability of this lowering, it tries to aggressively
7522 /// match this pattern. It will use all of the micro-architectural details it
7523 /// can to emit an efficient lowering. It handles both blends with all-zero
7524 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7525 /// masking out later).
7527 /// The reason we have dedicated lowering for zext-style shuffles is that they
7528 /// are both incredibly common and often quite performance sensitive.
7529 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7530 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7531 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7532 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7534 int Bits = VT.getSizeInBits();
7535 int NumLanes = Bits / 128;
7536 int NumElements = VT.getVectorNumElements();
7537 int NumEltsPerLane = NumElements / NumLanes;
7538 assert(VT.getScalarSizeInBits() <= 32 &&
7539 "Exceeds 32-bit integer zero extension limit");
7540 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7542 // Define a helper function to check a particular ext-scale and lower to it if
7544 auto Lower = [&](int Scale) -> SDValue {
7549 for (int i = 0; i < NumElements; ++i) {
7552 continue; // Valid anywhere but doesn't tell us anything.
7553 if (i % Scale != 0) {
7554 // Each of the extended elements need to be zeroable.
7558 // We no longer are in the anyext case.
7563 // Each of the base elements needs to be consecutive indices into the
7564 // same input vector.
7565 SDValue V = M < NumElements ? V1 : V2;
7566 M = M % NumElements;
7569 Offset = M - (i / Scale);
7570 } else if (InputV != V)
7571 return SDValue(); // Flip-flopping inputs.
7573 // Offset must start in the lowest 128-bit lane or at the start of an
7575 // FIXME: Is it ever worth allowing a negative base offset?
7576 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7577 (Offset % NumEltsPerLane) == 0))
7580 // If we are offsetting, all referenced entries must come from the same
7582 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7585 if ((M % NumElements) != (Offset + (i / Scale)))
7586 return SDValue(); // Non-consecutive strided elements.
7590 // If we fail to find an input, we have a zero-shuffle which should always
7591 // have already been handled.
7592 // FIXME: Maybe handle this here in case during blending we end up with one?
7596 // If we are offsetting, don't extend if we only match a single input, we
7597 // can always do better by using a basic PSHUF or PUNPCK.
7598 if (Offset != 0 && Matches < 2)
7601 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7602 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7605 // The widest scale possible for extending is to a 64-bit integer.
7606 assert(Bits % 64 == 0 &&
7607 "The number of bits in a vector must be divisible by 64 on x86!");
7608 int NumExtElements = Bits / 64;
7610 // Each iteration, try extending the elements half as much, but into twice as
7612 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7613 assert(NumElements % NumExtElements == 0 &&
7614 "The input vector size must be divisible by the extended size.");
7615 if (SDValue V = Lower(NumElements / NumExtElements))
7619 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7623 // Returns one of the source operands if the shuffle can be reduced to a
7624 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7625 auto CanZExtLowHalf = [&]() {
7626 for (int i = NumElements / 2; i != NumElements; ++i)
7629 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7631 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7636 if (SDValue V = CanZExtLowHalf()) {
7637 V = DAG.getBitcast(MVT::v2i64, V);
7638 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7639 return DAG.getBitcast(VT, V);
7642 // No viable ext lowering found.
7646 /// \brief Try to get a scalar value for a specific element of a vector.
7648 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7649 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7650 SelectionDAG &DAG) {
7651 MVT VT = V.getSimpleValueType();
7652 MVT EltVT = VT.getVectorElementType();
7653 while (V.getOpcode() == ISD::BITCAST)
7654 V = V.getOperand(0);
7655 // If the bitcasts shift the element size, we can't extract an equivalent
7657 MVT NewVT = V.getSimpleValueType();
7658 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7661 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7662 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7663 // Ensure the scalar operand is the same size as the destination.
7664 // FIXME: Add support for scalar truncation where possible.
7665 SDValue S = V.getOperand(Idx);
7666 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7667 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7673 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7675 /// This is particularly important because the set of instructions varies
7676 /// significantly based on whether the operand is a load or not.
7677 static bool isShuffleFoldableLoad(SDValue V) {
7678 while (V.getOpcode() == ISD::BITCAST)
7679 V = V.getOperand(0);
7681 return ISD::isNON_EXTLoad(V.getNode());
7684 /// \brief Try to lower insertion of a single element into a zero vector.
7686 /// This is a common pattern that we have especially efficient patterns to lower
7687 /// across all subtarget feature sets.
7688 static SDValue lowerVectorShuffleAsElementInsertion(
7689 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7690 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7691 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7693 MVT EltVT = VT.getVectorElementType();
7695 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7696 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7698 bool IsV1Zeroable = true;
7699 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7700 if (i != V2Index && !Zeroable[i]) {
7701 IsV1Zeroable = false;
7705 // Check for a single input from a SCALAR_TO_VECTOR node.
7706 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7707 // all the smarts here sunk into that routine. However, the current
7708 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7709 // vector shuffle lowering is dead.
7710 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7712 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7713 // We need to zext the scalar if it is smaller than an i32.
7714 V2S = DAG.getBitcast(EltVT, V2S);
7715 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7716 // Using zext to expand a narrow element won't work for non-zero
7721 // Zero-extend directly to i32.
7723 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7725 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7726 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7727 EltVT == MVT::i16) {
7728 // Either not inserting from the low element of the input or the input
7729 // element size is too small to use VZEXT_MOVL to clear the high bits.
7733 if (!IsV1Zeroable) {
7734 // If V1 can't be treated as a zero vector we have fewer options to lower
7735 // this. We can't support integer vectors or non-zero targets cheaply, and
7736 // the V1 elements can't be permuted in any way.
7737 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7738 if (!VT.isFloatingPoint() || V2Index != 0)
7740 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7741 V1Mask[V2Index] = -1;
7742 if (!isNoopShuffleMask(V1Mask))
7744 // This is essentially a special case blend operation, but if we have
7745 // general purpose blend operations, they are always faster. Bail and let
7746 // the rest of the lowering handle these as blends.
7747 if (Subtarget->hasSSE41())
7750 // Otherwise, use MOVSD or MOVSS.
7751 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7752 "Only two types of floating point element types to handle!");
7753 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7757 // This lowering only works for the low element with floating point vectors.
7758 if (VT.isFloatingPoint() && V2Index != 0)
7761 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7763 V2 = DAG.getBitcast(VT, V2);
7766 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7767 // the desired position. Otherwise it is more efficient to do a vector
7768 // shift left. We know that we can do a vector shift left because all
7769 // the inputs are zero.
7770 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7771 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7772 V2Shuffle[V2Index] = 0;
7773 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7775 V2 = DAG.getBitcast(MVT::v2i64, V2);
7777 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7778 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7779 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7780 DAG.getDataLayout(), VT)));
7781 V2 = DAG.getBitcast(VT, V2);
7787 /// \brief Try to lower broadcast of a single element.
7789 /// For convenience, this code also bundles all of the subtarget feature set
7790 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7791 /// a convenient way to factor it out.
7792 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7794 const X86Subtarget *Subtarget,
7795 SelectionDAG &DAG) {
7796 if (!Subtarget->hasAVX())
7798 if (VT.isInteger() && !Subtarget->hasAVX2())
7801 // Check that the mask is a broadcast.
7802 int BroadcastIdx = -1;
7804 if (M >= 0 && BroadcastIdx == -1)
7806 else if (M >= 0 && M != BroadcastIdx)
7809 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7810 "a sorted mask where the broadcast "
7813 // Go up the chain of (vector) values to find a scalar load that we can
7814 // combine with the broadcast.
7816 switch (V.getOpcode()) {
7817 case ISD::CONCAT_VECTORS: {
7818 int OperandSize = Mask.size() / V.getNumOperands();
7819 V = V.getOperand(BroadcastIdx / OperandSize);
7820 BroadcastIdx %= OperandSize;
7824 case ISD::INSERT_SUBVECTOR: {
7825 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7826 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7830 int BeginIdx = (int)ConstantIdx->getZExtValue();
7832 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7833 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7834 BroadcastIdx -= BeginIdx;
7845 // Check if this is a broadcast of a scalar. We special case lowering
7846 // for scalars so that we can more effectively fold with loads.
7847 // First, look through bitcast: if the original value has a larger element
7848 // type than the shuffle, the broadcast element is in essence truncated.
7849 // Make that explicit to ease folding.
7850 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7851 EVT EltVT = VT.getVectorElementType();
7852 SDValue V0 = V.getOperand(0);
7853 EVT V0VT = V0.getValueType();
7855 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7856 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7857 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7858 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7863 // Also check the simpler case, where we can directly reuse the scalar.
7864 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7865 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7866 V = V.getOperand(BroadcastIdx);
7868 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7869 // Only AVX2 has register broadcasts.
7870 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7872 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7873 // We can't broadcast from a vector register without AVX2, and we can only
7874 // broadcast from the zero-element of a vector register.
7878 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7881 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7882 // INSERTPS when the V1 elements are already in the correct locations
7883 // because otherwise we can just always use two SHUFPS instructions which
7884 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7885 // perform INSERTPS if a single V1 element is out of place and all V2
7886 // elements are zeroable.
7887 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7889 SelectionDAG &DAG) {
7890 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7891 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7892 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7893 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7895 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7898 int V1DstIndex = -1;
7899 int V2DstIndex = -1;
7900 bool V1UsedInPlace = false;
7902 for (int i = 0; i < 4; ++i) {
7903 // Synthesize a zero mask from the zeroable elements (includes undefs).
7909 // Flag if we use any V1 inputs in place.
7911 V1UsedInPlace = true;
7915 // We can only insert a single non-zeroable element.
7916 if (V1DstIndex != -1 || V2DstIndex != -1)
7920 // V1 input out of place for insertion.
7923 // V2 input for insertion.
7928 // Don't bother if we have no (non-zeroable) element for insertion.
7929 if (V1DstIndex == -1 && V2DstIndex == -1)
7932 // Determine element insertion src/dst indices. The src index is from the
7933 // start of the inserted vector, not the start of the concatenated vector.
7934 unsigned V2SrcIndex = 0;
7935 if (V1DstIndex != -1) {
7936 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7937 // and don't use the original V2 at all.
7938 V2SrcIndex = Mask[V1DstIndex];
7939 V2DstIndex = V1DstIndex;
7942 V2SrcIndex = Mask[V2DstIndex] - 4;
7945 // If no V1 inputs are used in place, then the result is created only from
7946 // the zero mask and the V2 insertion - so remove V1 dependency.
7948 V1 = DAG.getUNDEF(MVT::v4f32);
7950 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7951 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7953 // Insert the V2 element into the desired position.
7955 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7956 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7959 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7960 /// UNPCK instruction.
7962 /// This specifically targets cases where we end up with alternating between
7963 /// the two inputs, and so can permute them into something that feeds a single
7964 /// UNPCK instruction. Note that this routine only targets integer vectors
7965 /// because for floating point vectors we have a generalized SHUFPS lowering
7966 /// strategy that handles everything that doesn't *exactly* match an unpack,
7967 /// making this clever lowering unnecessary.
7968 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7969 SDValue V1, SDValue V2,
7971 SelectionDAG &DAG) {
7972 assert(!VT.isFloatingPoint() &&
7973 "This routine only supports integer vectors.");
7974 assert(!isSingleInputShuffleMask(Mask) &&
7975 "This routine should only be used when blending two inputs.");
7976 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7978 int Size = Mask.size();
7980 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7981 return M >= 0 && M % Size < Size / 2;
7983 int NumHiInputs = std::count_if(
7984 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7986 bool UnpackLo = NumLoInputs >= NumHiInputs;
7988 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7989 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7990 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7992 for (int i = 0; i < Size; ++i) {
7996 // Each element of the unpack contains Scale elements from this mask.
7997 int UnpackIdx = i / Scale;
7999 // We only handle the case where V1 feeds the first slots of the unpack.
8000 // We rely on canonicalization to ensure this is the case.
8001 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8004 // Setup the mask for this input. The indexing is tricky as we have to
8005 // handle the unpack stride.
8006 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8007 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8011 // If we will have to shuffle both inputs to use the unpack, check whether
8012 // we can just unpack first and shuffle the result. If so, skip this unpack.
8013 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8014 !isNoopShuffleMask(V2Mask))
8017 // Shuffle the inputs into place.
8018 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8019 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8021 // Cast the inputs to the type we will use to unpack them.
8022 V1 = DAG.getBitcast(UnpackVT, V1);
8023 V2 = DAG.getBitcast(UnpackVT, V2);
8025 // Unpack the inputs and cast the result back to the desired type.
8026 return DAG.getBitcast(
8027 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8031 // We try each unpack from the largest to the smallest to try and find one
8032 // that fits this mask.
8033 int OrigNumElements = VT.getVectorNumElements();
8034 int OrigScalarSize = VT.getScalarSizeInBits();
8035 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8036 int Scale = ScalarSize / OrigScalarSize;
8037 int NumElements = OrigNumElements / Scale;
8038 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8039 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8043 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8045 if (NumLoInputs == 0 || NumHiInputs == 0) {
8046 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8047 "We have to have *some* inputs!");
8048 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8050 // FIXME: We could consider the total complexity of the permute of each
8051 // possible unpacking. Or at the least we should consider how many
8052 // half-crossings are created.
8053 // FIXME: We could consider commuting the unpacks.
8055 SmallVector<int, 32> PermMask;
8056 PermMask.assign(Size, -1);
8057 for (int i = 0; i < Size; ++i) {
8061 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8064 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8066 return DAG.getVectorShuffle(
8067 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8069 DAG.getUNDEF(VT), PermMask);
8075 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8077 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8078 /// support for floating point shuffles but not integer shuffles. These
8079 /// instructions will incur a domain crossing penalty on some chips though so
8080 /// it is better to avoid lowering through this for integer vectors where
8082 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8083 const X86Subtarget *Subtarget,
8084 SelectionDAG &DAG) {
8086 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8087 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8088 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8089 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8090 ArrayRef<int> Mask = SVOp->getMask();
8091 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8093 if (isSingleInputShuffleMask(Mask)) {
8094 // Use low duplicate instructions for masks that match their pattern.
8095 if (Subtarget->hasSSE3())
8096 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8097 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8099 // Straight shuffle of a single input vector. Simulate this by using the
8100 // single input as both of the "inputs" to this instruction..
8101 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8103 if (Subtarget->hasAVX()) {
8104 // If we have AVX, we can use VPERMILPS which will allow folding a load
8105 // into the shuffle.
8106 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8107 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8110 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8111 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8113 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8114 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8116 // If we have a single input, insert that into V1 if we can do so cheaply.
8117 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8118 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8119 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8121 // Try inverting the insertion since for v2 masks it is easy to do and we
8122 // can't reliably sort the mask one way or the other.
8123 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8124 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8125 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8126 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8130 // Try to use one of the special instruction patterns to handle two common
8131 // blend patterns if a zero-blend above didn't work.
8132 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8133 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8134 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8135 // We can either use a special instruction to load over the low double or
8136 // to move just the low double.
8138 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8140 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8142 if (Subtarget->hasSSE41())
8143 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8147 // Use dedicated unpack instructions for masks that match their pattern.
8148 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8149 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8150 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8151 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8153 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8154 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8155 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8158 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8160 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8161 /// the integer unit to minimize domain crossing penalties. However, for blends
8162 /// it falls back to the floating point shuffle operation with appropriate bit
8164 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8165 const X86Subtarget *Subtarget,
8166 SelectionDAG &DAG) {
8168 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8169 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8170 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8172 ArrayRef<int> Mask = SVOp->getMask();
8173 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8175 if (isSingleInputShuffleMask(Mask)) {
8176 // Check for being able to broadcast a single element.
8177 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8178 Mask, Subtarget, DAG))
8181 // Straight shuffle of a single input vector. For everything from SSE2
8182 // onward this has a single fast instruction with no scary immediates.
8183 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8184 V1 = DAG.getBitcast(MVT::v4i32, V1);
8185 int WidenedMask[4] = {
8186 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8187 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8188 return DAG.getBitcast(
8190 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8191 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8193 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8194 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8195 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8196 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8198 // If we have a blend of two PACKUS operations an the blend aligns with the
8199 // low and half halves, we can just merge the PACKUS operations. This is
8200 // particularly important as it lets us merge shuffles that this routine itself
8202 auto GetPackNode = [](SDValue V) {
8203 while (V.getOpcode() == ISD::BITCAST)
8204 V = V.getOperand(0);
8206 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8208 if (SDValue V1Pack = GetPackNode(V1))
8209 if (SDValue V2Pack = GetPackNode(V2))
8210 return DAG.getBitcast(MVT::v2i64,
8211 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8212 Mask[0] == 0 ? V1Pack.getOperand(0)
8213 : V1Pack.getOperand(1),
8214 Mask[1] == 2 ? V2Pack.getOperand(0)
8215 : V2Pack.getOperand(1)));
8217 // Try to use shift instructions.
8219 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8222 // When loading a scalar and then shuffling it into a vector we can often do
8223 // the insertion cheaply.
8224 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8225 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8227 // Try inverting the insertion since for v2 masks it is easy to do and we
8228 // can't reliably sort the mask one way or the other.
8229 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8230 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8231 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8234 // We have different paths for blend lowering, but they all must use the
8235 // *exact* same predicate.
8236 bool IsBlendSupported = Subtarget->hasSSE41();
8237 if (IsBlendSupported)
8238 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8242 // Use dedicated unpack instructions for masks that match their pattern.
8243 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8244 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8245 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8246 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8248 // Try to use byte rotation instructions.
8249 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8250 if (Subtarget->hasSSSE3())
8251 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8252 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8255 // If we have direct support for blends, we should lower by decomposing into
8256 // a permute. That will be faster than the domain cross.
8257 if (IsBlendSupported)
8258 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8261 // We implement this with SHUFPD which is pretty lame because it will likely
8262 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8263 // However, all the alternatives are still more cycles and newer chips don't
8264 // have this problem. It would be really nice if x86 had better shuffles here.
8265 V1 = DAG.getBitcast(MVT::v2f64, V1);
8266 V2 = DAG.getBitcast(MVT::v2f64, V2);
8267 return DAG.getBitcast(MVT::v2i64,
8268 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8271 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8273 /// This is used to disable more specialized lowerings when the shufps lowering
8274 /// will happen to be efficient.
8275 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8276 // This routine only handles 128-bit shufps.
8277 assert(Mask.size() == 4 && "Unsupported mask size!");
8279 // To lower with a single SHUFPS we need to have the low half and high half
8280 // each requiring a single input.
8281 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8283 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8289 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8291 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8292 /// It makes no assumptions about whether this is the *best* lowering, it simply
8294 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8295 ArrayRef<int> Mask, SDValue V1,
8296 SDValue V2, SelectionDAG &DAG) {
8297 SDValue LowV = V1, HighV = V2;
8298 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8301 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8303 if (NumV2Elements == 1) {
8305 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8308 // Compute the index adjacent to V2Index and in the same half by toggling
8310 int V2AdjIndex = V2Index ^ 1;
8312 if (Mask[V2AdjIndex] == -1) {
8313 // Handles all the cases where we have a single V2 element and an undef.
8314 // This will only ever happen in the high lanes because we commute the
8315 // vector otherwise.
8317 std::swap(LowV, HighV);
8318 NewMask[V2Index] -= 4;
8320 // Handle the case where the V2 element ends up adjacent to a V1 element.
8321 // To make this work, blend them together as the first step.
8322 int V1Index = V2AdjIndex;
8323 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8324 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8325 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8327 // Now proceed to reconstruct the final blend as we have the necessary
8328 // high or low half formed.
8335 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8336 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8338 } else if (NumV2Elements == 2) {
8339 if (Mask[0] < 4 && Mask[1] < 4) {
8340 // Handle the easy case where we have V1 in the low lanes and V2 in the
8344 } else if (Mask[2] < 4 && Mask[3] < 4) {
8345 // We also handle the reversed case because this utility may get called
8346 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8347 // arrange things in the right direction.
8353 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8354 // trying to place elements directly, just blend them and set up the final
8355 // shuffle to place them.
8357 // The first two blend mask elements are for V1, the second two are for
8359 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8360 Mask[2] < 4 ? Mask[2] : Mask[3],
8361 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8362 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8363 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8364 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8366 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8369 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8370 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8371 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8372 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8375 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8376 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8379 /// \brief Lower 4-lane 32-bit floating point shuffles.
8381 /// Uses instructions exclusively from the floating point unit to minimize
8382 /// domain crossing penalties, as these are sufficient to implement all v4f32
8384 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8385 const X86Subtarget *Subtarget,
8386 SelectionDAG &DAG) {
8388 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8389 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8390 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8392 ArrayRef<int> Mask = SVOp->getMask();
8393 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8396 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8398 if (NumV2Elements == 0) {
8399 // Check for being able to broadcast a single element.
8400 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8401 Mask, Subtarget, DAG))
8404 // Use even/odd duplicate instructions for masks that match their pattern.
8405 if (Subtarget->hasSSE3()) {
8406 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8407 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8408 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8409 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8412 if (Subtarget->hasAVX()) {
8413 // If we have AVX, we can use VPERMILPS which will allow folding a load
8414 // into the shuffle.
8415 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8416 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8419 // Otherwise, use a straight shuffle of a single input vector. We pass the
8420 // input vector to both operands to simulate this with a SHUFPS.
8421 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8422 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8425 // There are special ways we can lower some single-element blends. However, we
8426 // have custom ways we can lower more complex single-element blends below that
8427 // we defer to if both this and BLENDPS fail to match, so restrict this to
8428 // when the V2 input is targeting element 0 of the mask -- that is the fast
8430 if (NumV2Elements == 1 && Mask[0] >= 4)
8431 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8432 Mask, Subtarget, DAG))
8435 if (Subtarget->hasSSE41()) {
8436 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8440 // Use INSERTPS if we can complete the shuffle efficiently.
8441 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8444 if (!isSingleSHUFPSMask(Mask))
8445 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8446 DL, MVT::v4f32, V1, V2, Mask, DAG))
8450 // Use dedicated unpack instructions for masks that match their pattern.
8451 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8452 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8453 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8454 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8455 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8456 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8457 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8458 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8460 // Otherwise fall back to a SHUFPS lowering strategy.
8461 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8464 /// \brief Lower 4-lane i32 vector shuffles.
8466 /// We try to handle these with integer-domain shuffles where we can, but for
8467 /// blends we use the floating point domain blend instructions.
8468 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8469 const X86Subtarget *Subtarget,
8470 SelectionDAG &DAG) {
8472 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8473 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8474 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8476 ArrayRef<int> Mask = SVOp->getMask();
8477 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8479 // Whenever we can lower this as a zext, that instruction is strictly faster
8480 // than any alternative. It also allows us to fold memory operands into the
8481 // shuffle in many cases.
8482 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8483 Mask, Subtarget, DAG))
8487 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8489 if (NumV2Elements == 0) {
8490 // Check for being able to broadcast a single element.
8491 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8492 Mask, Subtarget, DAG))
8495 // Straight shuffle of a single input vector. For everything from SSE2
8496 // onward this has a single fast instruction with no scary immediates.
8497 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8498 // but we aren't actually going to use the UNPCK instruction because doing
8499 // so prevents folding a load into this instruction or making a copy.
8500 const int UnpackLoMask[] = {0, 0, 1, 1};
8501 const int UnpackHiMask[] = {2, 2, 3, 3};
8502 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8503 Mask = UnpackLoMask;
8504 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8505 Mask = UnpackHiMask;
8507 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8508 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8511 // Try to use shift instructions.
8513 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8516 // There are special ways we can lower some single-element blends.
8517 if (NumV2Elements == 1)
8518 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8519 Mask, Subtarget, DAG))
8522 // We have different paths for blend lowering, but they all must use the
8523 // *exact* same predicate.
8524 bool IsBlendSupported = Subtarget->hasSSE41();
8525 if (IsBlendSupported)
8526 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8530 if (SDValue Masked =
8531 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8534 // Use dedicated unpack instructions for masks that match their pattern.
8535 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8536 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8537 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8538 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8539 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8540 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8541 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8542 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8544 // Try to use byte rotation instructions.
8545 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8546 if (Subtarget->hasSSSE3())
8547 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8548 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8551 // If we have direct support for blends, we should lower by decomposing into
8552 // a permute. That will be faster than the domain cross.
8553 if (IsBlendSupported)
8554 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8557 // Try to lower by permuting the inputs into an unpack instruction.
8558 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8562 // We implement this with SHUFPS because it can blend from two vectors.
8563 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8564 // up the inputs, bypassing domain shift penalties that we would encur if we
8565 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8567 return DAG.getBitcast(
8569 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8570 DAG.getBitcast(MVT::v4f32, V2), Mask));
8573 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8574 /// shuffle lowering, and the most complex part.
8576 /// The lowering strategy is to try to form pairs of input lanes which are
8577 /// targeted at the same half of the final vector, and then use a dword shuffle
8578 /// to place them onto the right half, and finally unpack the paired lanes into
8579 /// their final position.
8581 /// The exact breakdown of how to form these dword pairs and align them on the
8582 /// correct sides is really tricky. See the comments within the function for
8583 /// more of the details.
8585 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8586 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8587 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8588 /// vector, form the analogous 128-bit 8-element Mask.
8589 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8590 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8591 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8592 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8593 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8595 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8596 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8597 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8599 SmallVector<int, 4> LoInputs;
8600 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8601 [](int M) { return M >= 0; });
8602 std::sort(LoInputs.begin(), LoInputs.end());
8603 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8604 SmallVector<int, 4> HiInputs;
8605 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8606 [](int M) { return M >= 0; });
8607 std::sort(HiInputs.begin(), HiInputs.end());
8608 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8610 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8611 int NumHToL = LoInputs.size() - NumLToL;
8613 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8614 int NumHToH = HiInputs.size() - NumLToH;
8615 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8616 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8617 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8618 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8620 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8621 // such inputs we can swap two of the dwords across the half mark and end up
8622 // with <=2 inputs to each half in each half. Once there, we can fall through
8623 // to the generic code below. For example:
8625 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8626 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8628 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8629 // and an existing 2-into-2 on the other half. In this case we may have to
8630 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8631 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8632 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8633 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8634 // half than the one we target for fixing) will be fixed when we re-enter this
8635 // path. We will also combine away any sequence of PSHUFD instructions that
8636 // result into a single instruction. Here is an example of the tricky case:
8638 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8639 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8641 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8643 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8644 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8646 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8647 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8649 // The result is fine to be handled by the generic logic.
8650 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8651 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8652 int AOffset, int BOffset) {
8653 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8654 "Must call this with A having 3 or 1 inputs from the A half.");
8655 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8656 "Must call this with B having 1 or 3 inputs from the B half.");
8657 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8658 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8660 bool ThreeAInputs = AToAInputs.size() == 3;
8662 // Compute the index of dword with only one word among the three inputs in
8663 // a half by taking the sum of the half with three inputs and subtracting
8664 // the sum of the actual three inputs. The difference is the remaining
8667 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8668 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8669 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8670 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8671 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8672 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8673 int TripleNonInputIdx =
8674 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8675 TripleDWord = TripleNonInputIdx / 2;
8677 // We use xor with one to compute the adjacent DWord to whichever one the
8679 OneInputDWord = (OneInput / 2) ^ 1;
8681 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8682 // and BToA inputs. If there is also such a problem with the BToB and AToB
8683 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8684 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8685 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8686 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8687 // Compute how many inputs will be flipped by swapping these DWords. We
8689 // to balance this to ensure we don't form a 3-1 shuffle in the other
8691 int NumFlippedAToBInputs =
8692 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8693 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8694 int NumFlippedBToBInputs =
8695 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8696 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8697 if ((NumFlippedAToBInputs == 1 &&
8698 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8699 (NumFlippedBToBInputs == 1 &&
8700 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8701 // We choose whether to fix the A half or B half based on whether that
8702 // half has zero flipped inputs. At zero, we may not be able to fix it
8703 // with that half. We also bias towards fixing the B half because that
8704 // will more commonly be the high half, and we have to bias one way.
8705 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8706 ArrayRef<int> Inputs) {
8707 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8708 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8709 PinnedIdx ^ 1) != Inputs.end();
8710 // Determine whether the free index is in the flipped dword or the
8711 // unflipped dword based on where the pinned index is. We use this bit
8712 // in an xor to conditionally select the adjacent dword.
8713 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8714 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8715 FixFreeIdx) != Inputs.end();
8716 if (IsFixIdxInput == IsFixFreeIdxInput)
8718 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8719 FixFreeIdx) != Inputs.end();
8720 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8721 "We need to be changing the number of flipped inputs!");
8722 int PSHUFHalfMask[] = {0, 1, 2, 3};
8723 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8724 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8726 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8729 if (M != -1 && M == FixIdx)
8731 else if (M != -1 && M == FixFreeIdx)
8734 if (NumFlippedBToBInputs != 0) {
8736 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8737 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8739 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8740 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8741 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8746 int PSHUFDMask[] = {0, 1, 2, 3};
8747 PSHUFDMask[ADWord] = BDWord;
8748 PSHUFDMask[BDWord] = ADWord;
8751 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8752 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8754 // Adjust the mask to match the new locations of A and B.
8756 if (M != -1 && M/2 == ADWord)
8757 M = 2 * BDWord + M % 2;
8758 else if (M != -1 && M/2 == BDWord)
8759 M = 2 * ADWord + M % 2;
8761 // Recurse back into this routine to re-compute state now that this isn't
8762 // a 3 and 1 problem.
8763 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8766 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8767 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8768 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8769 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8771 // At this point there are at most two inputs to the low and high halves from
8772 // each half. That means the inputs can always be grouped into dwords and
8773 // those dwords can then be moved to the correct half with a dword shuffle.
8774 // We use at most one low and one high word shuffle to collect these paired
8775 // inputs into dwords, and finally a dword shuffle to place them.
8776 int PSHUFLMask[4] = {-1, -1, -1, -1};
8777 int PSHUFHMask[4] = {-1, -1, -1, -1};
8778 int PSHUFDMask[4] = {-1, -1, -1, -1};
8780 // First fix the masks for all the inputs that are staying in their
8781 // original halves. This will then dictate the targets of the cross-half
8783 auto fixInPlaceInputs =
8784 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8785 MutableArrayRef<int> SourceHalfMask,
8786 MutableArrayRef<int> HalfMask, int HalfOffset) {
8787 if (InPlaceInputs.empty())
8789 if (InPlaceInputs.size() == 1) {
8790 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8791 InPlaceInputs[0] - HalfOffset;
8792 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8795 if (IncomingInputs.empty()) {
8796 // Just fix all of the in place inputs.
8797 for (int Input : InPlaceInputs) {
8798 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8799 PSHUFDMask[Input / 2] = Input / 2;
8804 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8805 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8806 InPlaceInputs[0] - HalfOffset;
8807 // Put the second input next to the first so that they are packed into
8808 // a dword. We find the adjacent index by toggling the low bit.
8809 int AdjIndex = InPlaceInputs[0] ^ 1;
8810 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8811 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8812 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8814 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8815 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8817 // Now gather the cross-half inputs and place them into a free dword of
8818 // their target half.
8819 // FIXME: This operation could almost certainly be simplified dramatically to
8820 // look more like the 3-1 fixing operation.
8821 auto moveInputsToRightHalf = [&PSHUFDMask](
8822 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8823 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8824 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8826 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8827 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8829 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8831 int LowWord = Word & ~1;
8832 int HighWord = Word | 1;
8833 return isWordClobbered(SourceHalfMask, LowWord) ||
8834 isWordClobbered(SourceHalfMask, HighWord);
8837 if (IncomingInputs.empty())
8840 if (ExistingInputs.empty()) {
8841 // Map any dwords with inputs from them into the right half.
8842 for (int Input : IncomingInputs) {
8843 // If the source half mask maps over the inputs, turn those into
8844 // swaps and use the swapped lane.
8845 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8846 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8847 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8848 Input - SourceOffset;
8849 // We have to swap the uses in our half mask in one sweep.
8850 for (int &M : HalfMask)
8851 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8853 else if (M == Input)
8854 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8856 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8857 Input - SourceOffset &&
8858 "Previous placement doesn't match!");
8860 // Note that this correctly re-maps both when we do a swap and when
8861 // we observe the other side of the swap above. We rely on that to
8862 // avoid swapping the members of the input list directly.
8863 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8866 // Map the input's dword into the correct half.
8867 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8868 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8870 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8872 "Previous placement doesn't match!");
8875 // And just directly shift any other-half mask elements to be same-half
8876 // as we will have mirrored the dword containing the element into the
8877 // same position within that half.
8878 for (int &M : HalfMask)
8879 if (M >= SourceOffset && M < SourceOffset + 4) {
8880 M = M - SourceOffset + DestOffset;
8881 assert(M >= 0 && "This should never wrap below zero!");
8886 // Ensure we have the input in a viable dword of its current half. This
8887 // is particularly tricky because the original position may be clobbered
8888 // by inputs being moved and *staying* in that half.
8889 if (IncomingInputs.size() == 1) {
8890 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8891 int InputFixed = std::find(std::begin(SourceHalfMask),
8892 std::end(SourceHalfMask), -1) -
8893 std::begin(SourceHalfMask) + SourceOffset;
8894 SourceHalfMask[InputFixed - SourceOffset] =
8895 IncomingInputs[0] - SourceOffset;
8896 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8898 IncomingInputs[0] = InputFixed;
8900 } else if (IncomingInputs.size() == 2) {
8901 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8902 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8903 // We have two non-adjacent or clobbered inputs we need to extract from
8904 // the source half. To do this, we need to map them into some adjacent
8905 // dword slot in the source mask.
8906 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8907 IncomingInputs[1] - SourceOffset};
8909 // If there is a free slot in the source half mask adjacent to one of
8910 // the inputs, place the other input in it. We use (Index XOR 1) to
8911 // compute an adjacent index.
8912 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8913 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8914 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8915 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8916 InputsFixed[1] = InputsFixed[0] ^ 1;
8917 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8918 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8919 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8920 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8921 InputsFixed[0] = InputsFixed[1] ^ 1;
8922 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8923 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8924 // The two inputs are in the same DWord but it is clobbered and the
8925 // adjacent DWord isn't used at all. Move both inputs to the free
8927 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8928 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8929 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8930 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8932 // The only way we hit this point is if there is no clobbering
8933 // (because there are no off-half inputs to this half) and there is no
8934 // free slot adjacent to one of the inputs. In this case, we have to
8935 // swap an input with a non-input.
8936 for (int i = 0; i < 4; ++i)
8937 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8938 "We can't handle any clobbers here!");
8939 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8940 "Cannot have adjacent inputs here!");
8942 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8943 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8945 // We also have to update the final source mask in this case because
8946 // it may need to undo the above swap.
8947 for (int &M : FinalSourceHalfMask)
8948 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8949 M = InputsFixed[1] + SourceOffset;
8950 else if (M == InputsFixed[1] + SourceOffset)
8951 M = (InputsFixed[0] ^ 1) + SourceOffset;
8953 InputsFixed[1] = InputsFixed[0] ^ 1;
8956 // Point everything at the fixed inputs.
8957 for (int &M : HalfMask)
8958 if (M == IncomingInputs[0])
8959 M = InputsFixed[0] + SourceOffset;
8960 else if (M == IncomingInputs[1])
8961 M = InputsFixed[1] + SourceOffset;
8963 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8964 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8967 llvm_unreachable("Unhandled input size!");
8970 // Now hoist the DWord down to the right half.
8971 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8972 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8973 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8974 for (int &M : HalfMask)
8975 for (int Input : IncomingInputs)
8977 M = FreeDWord * 2 + Input % 2;
8979 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8980 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8981 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8982 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8984 // Now enact all the shuffles we've computed to move the inputs into their
8986 if (!isNoopShuffleMask(PSHUFLMask))
8987 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8988 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8989 if (!isNoopShuffleMask(PSHUFHMask))
8990 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8991 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8992 if (!isNoopShuffleMask(PSHUFDMask))
8995 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8996 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8998 // At this point, each half should contain all its inputs, and we can then
8999 // just shuffle them into their final position.
9000 assert(std::count_if(LoMask.begin(), LoMask.end(),
9001 [](int M) { return M >= 4; }) == 0 &&
9002 "Failed to lift all the high half inputs to the low mask!");
9003 assert(std::count_if(HiMask.begin(), HiMask.end(),
9004 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9005 "Failed to lift all the low half inputs to the high mask!");
9007 // Do a half shuffle for the low mask.
9008 if (!isNoopShuffleMask(LoMask))
9009 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9010 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9012 // Do a half shuffle with the high mask after shifting its values down.
9013 for (int &M : HiMask)
9016 if (!isNoopShuffleMask(HiMask))
9017 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9018 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9023 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9024 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9025 SDValue V2, ArrayRef<int> Mask,
9026 SelectionDAG &DAG, bool &V1InUse,
9028 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9034 int Size = Mask.size();
9035 int Scale = 16 / Size;
9036 for (int i = 0; i < 16; ++i) {
9037 if (Mask[i / Scale] == -1) {
9038 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9040 const int ZeroMask = 0x80;
9041 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9043 int V2Idx = Mask[i / Scale] < Size
9045 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9046 if (Zeroable[i / Scale])
9047 V1Idx = V2Idx = ZeroMask;
9048 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9049 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9050 V1InUse |= (ZeroMask != V1Idx);
9051 V2InUse |= (ZeroMask != V2Idx);
9056 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9057 DAG.getBitcast(MVT::v16i8, V1),
9058 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9060 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9061 DAG.getBitcast(MVT::v16i8, V2),
9062 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9064 // If we need shuffled inputs from both, blend the two.
9066 if (V1InUse && V2InUse)
9067 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9069 V = V1InUse ? V1 : V2;
9071 // Cast the result back to the correct type.
9072 return DAG.getBitcast(VT, V);
9075 /// \brief Generic lowering of 8-lane i16 shuffles.
9077 /// This handles both single-input shuffles and combined shuffle/blends with
9078 /// two inputs. The single input shuffles are immediately delegated to
9079 /// a dedicated lowering routine.
9081 /// The blends are lowered in one of three fundamental ways. If there are few
9082 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9083 /// of the input is significantly cheaper when lowered as an interleaving of
9084 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9085 /// halves of the inputs separately (making them have relatively few inputs)
9086 /// and then concatenate them.
9087 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9088 const X86Subtarget *Subtarget,
9089 SelectionDAG &DAG) {
9091 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9092 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9093 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9095 ArrayRef<int> OrigMask = SVOp->getMask();
9096 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9097 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9098 MutableArrayRef<int> Mask(MaskStorage);
9100 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9102 // Whenever we can lower this as a zext, that instruction is strictly faster
9103 // than any alternative.
9104 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9105 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9108 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9110 auto isV2 = [](int M) { return M >= 8; };
9112 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9114 if (NumV2Inputs == 0) {
9115 // Check for being able to broadcast a single element.
9116 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9117 Mask, Subtarget, DAG))
9120 // Try to use shift instructions.
9122 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9125 // Use dedicated unpack instructions for masks that match their pattern.
9126 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9127 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9128 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9129 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9131 // Try to use byte rotation instructions.
9132 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9133 Mask, Subtarget, DAG))
9136 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9140 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9141 "All single-input shuffles should be canonicalized to be V1-input "
9144 // Try to use shift instructions.
9146 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9149 // See if we can use SSE4A Extraction / Insertion.
9150 if (Subtarget->hasSSE4A())
9151 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9154 // There are special ways we can lower some single-element blends.
9155 if (NumV2Inputs == 1)
9156 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9157 Mask, Subtarget, DAG))
9160 // We have different paths for blend lowering, but they all must use the
9161 // *exact* same predicate.
9162 bool IsBlendSupported = Subtarget->hasSSE41();
9163 if (IsBlendSupported)
9164 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9168 if (SDValue Masked =
9169 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9172 // Use dedicated unpack instructions for masks that match their pattern.
9173 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9174 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9175 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9176 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9178 // Try to use byte rotation instructions.
9179 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9180 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9183 if (SDValue BitBlend =
9184 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9187 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9191 // If we can't directly blend but can use PSHUFB, that will be better as it
9192 // can both shuffle and set up the inefficient blend.
9193 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9194 bool V1InUse, V2InUse;
9195 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9199 // We can always bit-blend if we have to so the fallback strategy is to
9200 // decompose into single-input permutes and blends.
9201 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9205 /// \brief Check whether a compaction lowering can be done by dropping even
9206 /// elements and compute how many times even elements must be dropped.
9208 /// This handles shuffles which take every Nth element where N is a power of
9209 /// two. Example shuffle masks:
9211 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9212 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9213 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9214 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9215 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9216 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9218 /// Any of these lanes can of course be undef.
9220 /// This routine only supports N <= 3.
9221 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9224 /// \returns N above, or the number of times even elements must be dropped if
9225 /// there is such a number. Otherwise returns zero.
9226 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9227 // Figure out whether we're looping over two inputs or just one.
9228 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9230 // The modulus for the shuffle vector entries is based on whether this is
9231 // a single input or not.
9232 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9233 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9234 "We should only be called with masks with a power-of-2 size!");
9236 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9238 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9239 // and 2^3 simultaneously. This is because we may have ambiguity with
9240 // partially undef inputs.
9241 bool ViableForN[3] = {true, true, true};
9243 for (int i = 0, e = Mask.size(); i < e; ++i) {
9244 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9249 bool IsAnyViable = false;
9250 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9251 if (ViableForN[j]) {
9254 // The shuffle mask must be equal to (i * 2^N) % M.
9255 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9258 ViableForN[j] = false;
9260 // Early exit if we exhaust the possible powers of two.
9265 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9269 // Return 0 as there is no viable power of two.
9273 /// \brief Generic lowering of v16i8 shuffles.
9275 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9276 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9277 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9278 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9280 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9281 const X86Subtarget *Subtarget,
9282 SelectionDAG &DAG) {
9284 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9285 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9286 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9287 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9288 ArrayRef<int> Mask = SVOp->getMask();
9289 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9291 // Try to use shift instructions.
9293 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9296 // Try to use byte rotation instructions.
9297 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9298 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9301 // Try to use a zext lowering.
9302 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9303 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9306 // See if we can use SSE4A Extraction / Insertion.
9307 if (Subtarget->hasSSE4A())
9308 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9312 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9314 // For single-input shuffles, there are some nicer lowering tricks we can use.
9315 if (NumV2Elements == 0) {
9316 // Check for being able to broadcast a single element.
9317 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9318 Mask, Subtarget, DAG))
9321 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9322 // Notably, this handles splat and partial-splat shuffles more efficiently.
9323 // However, it only makes sense if the pre-duplication shuffle simplifies
9324 // things significantly. Currently, this means we need to be able to
9325 // express the pre-duplication shuffle as an i16 shuffle.
9327 // FIXME: We should check for other patterns which can be widened into an
9328 // i16 shuffle as well.
9329 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9330 for (int i = 0; i < 16; i += 2)
9331 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9336 auto tryToWidenViaDuplication = [&]() -> SDValue {
9337 if (!canWidenViaDuplication(Mask))
9339 SmallVector<int, 4> LoInputs;
9340 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9341 [](int M) { return M >= 0 && M < 8; });
9342 std::sort(LoInputs.begin(), LoInputs.end());
9343 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9345 SmallVector<int, 4> HiInputs;
9346 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9347 [](int M) { return M >= 8; });
9348 std::sort(HiInputs.begin(), HiInputs.end());
9349 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9352 bool TargetLo = LoInputs.size() >= HiInputs.size();
9353 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9354 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9356 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9357 SmallDenseMap<int, int, 8> LaneMap;
9358 for (int I : InPlaceInputs) {
9359 PreDupI16Shuffle[I/2] = I/2;
9362 int j = TargetLo ? 0 : 4, je = j + 4;
9363 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9364 // Check if j is already a shuffle of this input. This happens when
9365 // there are two adjacent bytes after we move the low one.
9366 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9367 // If we haven't yet mapped the input, search for a slot into which
9369 while (j < je && PreDupI16Shuffle[j] != -1)
9373 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9376 // Map this input with the i16 shuffle.
9377 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9380 // Update the lane map based on the mapping we ended up with.
9381 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9383 V1 = DAG.getBitcast(
9385 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9386 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9388 // Unpack the bytes to form the i16s that will be shuffled into place.
9389 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9390 MVT::v16i8, V1, V1);
9392 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9393 for (int i = 0; i < 16; ++i)
9394 if (Mask[i] != -1) {
9395 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9396 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9397 if (PostDupI16Shuffle[i / 2] == -1)
9398 PostDupI16Shuffle[i / 2] = MappedMask;
9400 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9401 "Conflicting entrties in the original shuffle!");
9403 return DAG.getBitcast(
9405 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9406 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9408 if (SDValue V = tryToWidenViaDuplication())
9412 if (SDValue Masked =
9413 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9416 // Use dedicated unpack instructions for masks that match their pattern.
9417 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9418 0, 16, 1, 17, 2, 18, 3, 19,
9420 4, 20, 5, 21, 6, 22, 7, 23}))
9421 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9422 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9423 8, 24, 9, 25, 10, 26, 11, 27,
9425 12, 28, 13, 29, 14, 30, 15, 31}))
9426 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9428 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9429 // with PSHUFB. It is important to do this before we attempt to generate any
9430 // blends but after all of the single-input lowerings. If the single input
9431 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9432 // want to preserve that and we can DAG combine any longer sequences into
9433 // a PSHUFB in the end. But once we start blending from multiple inputs,
9434 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9435 // and there are *very* few patterns that would actually be faster than the
9436 // PSHUFB approach because of its ability to zero lanes.
9438 // FIXME: The only exceptions to the above are blends which are exact
9439 // interleavings with direct instructions supporting them. We currently don't
9440 // handle those well here.
9441 if (Subtarget->hasSSSE3()) {
9442 bool V1InUse = false;
9443 bool V2InUse = false;
9445 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9446 DAG, V1InUse, V2InUse);
9448 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9449 // do so. This avoids using them to handle blends-with-zero which is
9450 // important as a single pshufb is significantly faster for that.
9451 if (V1InUse && V2InUse) {
9452 if (Subtarget->hasSSE41())
9453 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9454 Mask, Subtarget, DAG))
9457 // We can use an unpack to do the blending rather than an or in some
9458 // cases. Even though the or may be (very minorly) more efficient, we
9459 // preference this lowering because there are common cases where part of
9460 // the complexity of the shuffles goes away when we do the final blend as
9462 // FIXME: It might be worth trying to detect if the unpack-feeding
9463 // shuffles will both be pshufb, in which case we shouldn't bother with
9465 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9466 DL, MVT::v16i8, V1, V2, Mask, DAG))
9473 // There are special ways we can lower some single-element blends.
9474 if (NumV2Elements == 1)
9475 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9476 Mask, Subtarget, DAG))
9479 if (SDValue BitBlend =
9480 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9483 // Check whether a compaction lowering can be done. This handles shuffles
9484 // which take every Nth element for some even N. See the helper function for
9487 // We special case these as they can be particularly efficiently handled with
9488 // the PACKUSB instruction on x86 and they show up in common patterns of
9489 // rearranging bytes to truncate wide elements.
9490 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9491 // NumEvenDrops is the power of two stride of the elements. Another way of
9492 // thinking about it is that we need to drop the even elements this many
9493 // times to get the original input.
9494 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9496 // First we need to zero all the dropped bytes.
9497 assert(NumEvenDrops <= 3 &&
9498 "No support for dropping even elements more than 3 times.");
9499 // We use the mask type to pick which bytes are preserved based on how many
9500 // elements are dropped.
9501 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9502 SDValue ByteClearMask = DAG.getBitcast(
9503 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9504 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9506 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9508 // Now pack things back together.
9509 V1 = DAG.getBitcast(MVT::v8i16, V1);
9510 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9511 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9512 for (int i = 1; i < NumEvenDrops; ++i) {
9513 Result = DAG.getBitcast(MVT::v8i16, Result);
9514 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9520 // Handle multi-input cases by blending single-input shuffles.
9521 if (NumV2Elements > 0)
9522 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9525 // The fallback path for single-input shuffles widens this into two v8i16
9526 // vectors with unpacks, shuffles those, and then pulls them back together
9530 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9531 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9532 for (int i = 0; i < 16; ++i)
9534 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9536 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9538 SDValue VLoHalf, VHiHalf;
9539 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9540 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9542 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9543 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9544 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9545 [](int M) { return M >= 0 && M % 2 == 1; })) {
9546 // Use a mask to drop the high bytes.
9547 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9548 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9549 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9551 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9552 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9554 // Squash the masks to point directly into VLoHalf.
9555 for (int &M : LoBlendMask)
9558 for (int &M : HiBlendMask)
9562 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9563 // VHiHalf so that we can blend them as i16s.
9564 VLoHalf = DAG.getBitcast(
9565 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9566 VHiHalf = DAG.getBitcast(
9567 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9570 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9571 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9573 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9576 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9578 /// This routine breaks down the specific type of 128-bit shuffle and
9579 /// dispatches to the lowering routines accordingly.
9580 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9581 MVT VT, const X86Subtarget *Subtarget,
9582 SelectionDAG &DAG) {
9583 switch (VT.SimpleTy) {
9585 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9587 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9589 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9591 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9593 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9595 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9598 llvm_unreachable("Unimplemented!");
9602 /// \brief Helper function to test whether a shuffle mask could be
9603 /// simplified by widening the elements being shuffled.
9605 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9606 /// leaves it in an unspecified state.
9608 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9609 /// shuffle masks. The latter have the special property of a '-2' representing
9610 /// a zero-ed lane of a vector.
9611 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9612 SmallVectorImpl<int> &WidenedMask) {
9613 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9614 // If both elements are undef, its trivial.
9615 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9616 WidenedMask.push_back(SM_SentinelUndef);
9620 // Check for an undef mask and a mask value properly aligned to fit with
9621 // a pair of values. If we find such a case, use the non-undef mask's value.
9622 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9623 WidenedMask.push_back(Mask[i + 1] / 2);
9626 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9627 WidenedMask.push_back(Mask[i] / 2);
9631 // When zeroing, we need to spread the zeroing across both lanes to widen.
9632 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9633 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9634 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9635 WidenedMask.push_back(SM_SentinelZero);
9641 // Finally check if the two mask values are adjacent and aligned with
9643 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9644 WidenedMask.push_back(Mask[i] / 2);
9648 // Otherwise we can't safely widen the elements used in this shuffle.
9651 assert(WidenedMask.size() == Mask.size() / 2 &&
9652 "Incorrect size of mask after widening the elements!");
9657 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9659 /// This routine just extracts two subvectors, shuffles them independently, and
9660 /// then concatenates them back together. This should work effectively with all
9661 /// AVX vector shuffle types.
9662 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9663 SDValue V2, ArrayRef<int> Mask,
9664 SelectionDAG &DAG) {
9665 assert(VT.getSizeInBits() >= 256 &&
9666 "Only for 256-bit or wider vector shuffles!");
9667 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9668 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9670 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9671 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9673 int NumElements = VT.getVectorNumElements();
9674 int SplitNumElements = NumElements / 2;
9675 MVT ScalarVT = VT.getScalarType();
9676 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9678 // Rather than splitting build-vectors, just build two narrower build
9679 // vectors. This helps shuffling with splats and zeros.
9680 auto SplitVector = [&](SDValue V) {
9681 while (V.getOpcode() == ISD::BITCAST)
9682 V = V->getOperand(0);
9684 MVT OrigVT = V.getSimpleValueType();
9685 int OrigNumElements = OrigVT.getVectorNumElements();
9686 int OrigSplitNumElements = OrigNumElements / 2;
9687 MVT OrigScalarVT = OrigVT.getScalarType();
9688 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9692 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9694 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9695 DAG.getIntPtrConstant(0, DL));
9696 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9697 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9700 SmallVector<SDValue, 16> LoOps, HiOps;
9701 for (int i = 0; i < OrigSplitNumElements; ++i) {
9702 LoOps.push_back(BV->getOperand(i));
9703 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9705 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9706 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9708 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9709 DAG.getBitcast(SplitVT, HiV));
9712 SDValue LoV1, HiV1, LoV2, HiV2;
9713 std::tie(LoV1, HiV1) = SplitVector(V1);
9714 std::tie(LoV2, HiV2) = SplitVector(V2);
9716 // Now create two 4-way blends of these half-width vectors.
9717 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9718 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9719 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9720 for (int i = 0; i < SplitNumElements; ++i) {
9721 int M = HalfMask[i];
9722 if (M >= NumElements) {
9723 if (M >= NumElements + SplitNumElements)
9727 V2BlendMask.push_back(M - NumElements);
9728 V1BlendMask.push_back(-1);
9729 BlendMask.push_back(SplitNumElements + i);
9730 } else if (M >= 0) {
9731 if (M >= SplitNumElements)
9735 V2BlendMask.push_back(-1);
9736 V1BlendMask.push_back(M);
9737 BlendMask.push_back(i);
9739 V2BlendMask.push_back(-1);
9740 V1BlendMask.push_back(-1);
9741 BlendMask.push_back(-1);
9745 // Because the lowering happens after all combining takes place, we need to
9746 // manually combine these blend masks as much as possible so that we create
9747 // a minimal number of high-level vector shuffle nodes.
9749 // First try just blending the halves of V1 or V2.
9750 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9751 return DAG.getUNDEF(SplitVT);
9752 if (!UseLoV2 && !UseHiV2)
9753 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9754 if (!UseLoV1 && !UseHiV1)
9755 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9757 SDValue V1Blend, V2Blend;
9758 if (UseLoV1 && UseHiV1) {
9760 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9762 // We only use half of V1 so map the usage down into the final blend mask.
9763 V1Blend = UseLoV1 ? LoV1 : HiV1;
9764 for (int i = 0; i < SplitNumElements; ++i)
9765 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9766 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9768 if (UseLoV2 && UseHiV2) {
9770 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9772 // We only use half of V2 so map the usage down into the final blend mask.
9773 V2Blend = UseLoV2 ? LoV2 : HiV2;
9774 for (int i = 0; i < SplitNumElements; ++i)
9775 if (BlendMask[i] >= SplitNumElements)
9776 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9778 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9780 SDValue Lo = HalfBlend(LoMask);
9781 SDValue Hi = HalfBlend(HiMask);
9782 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9785 /// \brief Either split a vector in halves or decompose the shuffles and the
9788 /// This is provided as a good fallback for many lowerings of non-single-input
9789 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9790 /// between splitting the shuffle into 128-bit components and stitching those
9791 /// back together vs. extracting the single-input shuffles and blending those
9793 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9794 SDValue V2, ArrayRef<int> Mask,
9795 SelectionDAG &DAG) {
9796 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9797 "lower single-input shuffles as it "
9798 "could then recurse on itself.");
9799 int Size = Mask.size();
9801 // If this can be modeled as a broadcast of two elements followed by a blend,
9802 // prefer that lowering. This is especially important because broadcasts can
9803 // often fold with memory operands.
9804 auto DoBothBroadcast = [&] {
9805 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9808 if (V2BroadcastIdx == -1)
9809 V2BroadcastIdx = M - Size;
9810 else if (M - Size != V2BroadcastIdx)
9812 } else if (M >= 0) {
9813 if (V1BroadcastIdx == -1)
9815 else if (M != V1BroadcastIdx)
9820 if (DoBothBroadcast())
9821 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9824 // If the inputs all stem from a single 128-bit lane of each input, then we
9825 // split them rather than blending because the split will decompose to
9826 // unusually few instructions.
9827 int LaneCount = VT.getSizeInBits() / 128;
9828 int LaneSize = Size / LaneCount;
9829 SmallBitVector LaneInputs[2];
9830 LaneInputs[0].resize(LaneCount, false);
9831 LaneInputs[1].resize(LaneCount, false);
9832 for (int i = 0; i < Size; ++i)
9834 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9835 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9836 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9838 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9839 // that the decomposed single-input shuffles don't end up here.
9840 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9843 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9844 /// a permutation and blend of those lanes.
9846 /// This essentially blends the out-of-lane inputs to each lane into the lane
9847 /// from a permuted copy of the vector. This lowering strategy results in four
9848 /// instructions in the worst case for a single-input cross lane shuffle which
9849 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9850 /// of. Special cases for each particular shuffle pattern should be handled
9851 /// prior to trying this lowering.
9852 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9853 SDValue V1, SDValue V2,
9855 SelectionDAG &DAG) {
9856 // FIXME: This should probably be generalized for 512-bit vectors as well.
9857 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9858 int LaneSize = Mask.size() / 2;
9860 // If there are only inputs from one 128-bit lane, splitting will in fact be
9861 // less expensive. The flags track whether the given lane contains an element
9862 // that crosses to another lane.
9863 bool LaneCrossing[2] = {false, false};
9864 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9865 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9866 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9867 if (!LaneCrossing[0] || !LaneCrossing[1])
9868 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9870 if (isSingleInputShuffleMask(Mask)) {
9871 SmallVector<int, 32> FlippedBlendMask;
9872 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9873 FlippedBlendMask.push_back(
9874 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9876 : Mask[i] % LaneSize +
9877 (i / LaneSize) * LaneSize + Size));
9879 // Flip the vector, and blend the results which should now be in-lane. The
9880 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9881 // 5 for the high source. The value 3 selects the high half of source 2 and
9882 // the value 2 selects the low half of source 2. We only use source 2 to
9883 // allow folding it into a memory operand.
9884 unsigned PERMMask = 3 | 2 << 4;
9885 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9886 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9887 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9890 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9891 // will be handled by the above logic and a blend of the results, much like
9892 // other patterns in AVX.
9893 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9896 /// \brief Handle lowering 2-lane 128-bit shuffles.
9897 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9898 SDValue V2, ArrayRef<int> Mask,
9899 const X86Subtarget *Subtarget,
9900 SelectionDAG &DAG) {
9901 // TODO: If minimizing size and one of the inputs is a zero vector and the
9902 // the zero vector has only one use, we could use a VPERM2X128 to save the
9903 // instruction bytes needed to explicitly generate the zero vector.
9905 // Blends are faster and handle all the non-lane-crossing cases.
9906 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9910 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9911 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9913 // If either input operand is a zero vector, use VPERM2X128 because its mask
9914 // allows us to replace the zero input with an implicit zero.
9915 if (!IsV1Zero && !IsV2Zero) {
9916 // Check for patterns which can be matched with a single insert of a 128-bit
9918 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9919 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9920 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9921 VT.getVectorNumElements() / 2);
9922 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9923 DAG.getIntPtrConstant(0, DL));
9924 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9925 OnlyUsesV1 ? V1 : V2,
9926 DAG.getIntPtrConstant(0, DL));
9927 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9931 // Otherwise form a 128-bit permutation. After accounting for undefs,
9932 // convert the 64-bit shuffle mask selection values into 128-bit
9933 // selection bits by dividing the indexes by 2 and shifting into positions
9934 // defined by a vperm2*128 instruction's immediate control byte.
9936 // The immediate permute control byte looks like this:
9937 // [1:0] - select 128 bits from sources for low half of destination
9939 // [3] - zero low half of destination
9940 // [5:4] - select 128 bits from sources for high half of destination
9942 // [7] - zero high half of destination
9944 int MaskLO = Mask[0];
9945 if (MaskLO == SM_SentinelUndef)
9946 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9948 int MaskHI = Mask[2];
9949 if (MaskHI == SM_SentinelUndef)
9950 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9952 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9954 // If either input is a zero vector, replace it with an undef input.
9955 // Shuffle mask values < 4 are selecting elements of V1.
9956 // Shuffle mask values >= 4 are selecting elements of V2.
9957 // Adjust each half of the permute mask by clearing the half that was
9958 // selecting the zero vector and setting the zero mask bit.
9960 V1 = DAG.getUNDEF(VT);
9962 PermMask = (PermMask & 0xf0) | 0x08;
9964 PermMask = (PermMask & 0x0f) | 0x80;
9967 V2 = DAG.getUNDEF(VT);
9969 PermMask = (PermMask & 0xf0) | 0x08;
9971 PermMask = (PermMask & 0x0f) | 0x80;
9974 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9975 DAG.getConstant(PermMask, DL, MVT::i8));
9978 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9979 /// shuffling each lane.
9981 /// This will only succeed when the result of fixing the 128-bit lanes results
9982 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9983 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9984 /// the lane crosses early and then use simpler shuffles within each lane.
9986 /// FIXME: It might be worthwhile at some point to support this without
9987 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9988 /// in x86 only floating point has interesting non-repeating shuffles, and even
9989 /// those are still *marginally* more expensive.
9990 static SDValue lowerVectorShuffleByMerging128BitLanes(
9991 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9992 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9993 assert(!isSingleInputShuffleMask(Mask) &&
9994 "This is only useful with multiple inputs.");
9996 int Size = Mask.size();
9997 int LaneSize = 128 / VT.getScalarSizeInBits();
9998 int NumLanes = Size / LaneSize;
9999 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10001 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10002 // check whether the in-128-bit lane shuffles share a repeating pattern.
10003 SmallVector<int, 4> Lanes;
10004 Lanes.resize(NumLanes, -1);
10005 SmallVector<int, 4> InLaneMask;
10006 InLaneMask.resize(LaneSize, -1);
10007 for (int i = 0; i < Size; ++i) {
10011 int j = i / LaneSize;
10013 if (Lanes[j] < 0) {
10014 // First entry we've seen for this lane.
10015 Lanes[j] = Mask[i] / LaneSize;
10016 } else if (Lanes[j] != Mask[i] / LaneSize) {
10017 // This doesn't match the lane selected previously!
10021 // Check that within each lane we have a consistent shuffle mask.
10022 int k = i % LaneSize;
10023 if (InLaneMask[k] < 0) {
10024 InLaneMask[k] = Mask[i] % LaneSize;
10025 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10026 // This doesn't fit a repeating in-lane mask.
10031 // First shuffle the lanes into place.
10032 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10033 VT.getSizeInBits() / 64);
10034 SmallVector<int, 8> LaneMask;
10035 LaneMask.resize(NumLanes * 2, -1);
10036 for (int i = 0; i < NumLanes; ++i)
10037 if (Lanes[i] >= 0) {
10038 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10039 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10042 V1 = DAG.getBitcast(LaneVT, V1);
10043 V2 = DAG.getBitcast(LaneVT, V2);
10044 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10046 // Cast it back to the type we actually want.
10047 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10049 // Now do a simple shuffle that isn't lane crossing.
10050 SmallVector<int, 8> NewMask;
10051 NewMask.resize(Size, -1);
10052 for (int i = 0; i < Size; ++i)
10054 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10055 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10056 "Must not introduce lane crosses at this point!");
10058 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10061 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10064 /// This returns true if the elements from a particular input are already in the
10065 /// slot required by the given mask and require no permutation.
10066 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10067 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10068 int Size = Mask.size();
10069 for (int i = 0; i < Size; ++i)
10070 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10076 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10077 ArrayRef<int> Mask, SDValue V1,
10078 SDValue V2, SelectionDAG &DAG) {
10080 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10081 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10082 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10083 int NumElts = VT.getVectorNumElements();
10084 bool ShufpdMask = true;
10085 bool CommutableMask = true;
10086 unsigned Immediate = 0;
10087 for (int i = 0; i < NumElts; ++i) {
10090 int Val = (i & 6) + NumElts * (i & 1);
10091 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10092 if (Mask[i] < Val || Mask[i] > Val + 1)
10093 ShufpdMask = false;
10094 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10095 CommutableMask = false;
10096 Immediate |= (Mask[i] % 2) << i;
10099 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10100 DAG.getConstant(Immediate, DL, MVT::i8));
10101 if (CommutableMask)
10102 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10103 DAG.getConstant(Immediate, DL, MVT::i8));
10107 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10109 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10110 /// isn't available.
10111 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10112 const X86Subtarget *Subtarget,
10113 SelectionDAG &DAG) {
10115 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10116 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10117 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10118 ArrayRef<int> Mask = SVOp->getMask();
10119 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10121 SmallVector<int, 4> WidenedMask;
10122 if (canWidenShuffleElements(Mask, WidenedMask))
10123 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10126 if (isSingleInputShuffleMask(Mask)) {
10127 // Check for being able to broadcast a single element.
10128 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10129 Mask, Subtarget, DAG))
10132 // Use low duplicate instructions for masks that match their pattern.
10133 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10134 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10136 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10137 // Non-half-crossing single input shuffles can be lowerid with an
10138 // interleaved permutation.
10139 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10140 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10141 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10142 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10145 // With AVX2 we have direct support for this permutation.
10146 if (Subtarget->hasAVX2())
10147 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10148 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10150 // Otherwise, fall back.
10151 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10155 // X86 has dedicated unpack instructions that can handle specific blend
10156 // operations: UNPCKH and UNPCKL.
10157 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10158 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10159 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10160 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10161 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10162 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10163 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10164 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10166 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10170 // Check if the blend happens to exactly fit that of SHUFPD.
10172 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10175 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10176 // shuffle. However, if we have AVX2 and either inputs are already in place,
10177 // we will be able to shuffle even across lanes the other input in a single
10178 // instruction so skip this pattern.
10179 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10180 isShuffleMaskInputInPlace(1, Mask))))
10181 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10182 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10185 // If we have AVX2 then we always want to lower with a blend because an v4 we
10186 // can fully permute the elements.
10187 if (Subtarget->hasAVX2())
10188 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10191 // Otherwise fall back on generic lowering.
10192 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10195 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10197 /// This routine is only called when we have AVX2 and thus a reasonable
10198 /// instruction set for v4i64 shuffling..
10199 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10200 const X86Subtarget *Subtarget,
10201 SelectionDAG &DAG) {
10203 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10204 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10206 ArrayRef<int> Mask = SVOp->getMask();
10207 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10208 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10210 SmallVector<int, 4> WidenedMask;
10211 if (canWidenShuffleElements(Mask, WidenedMask))
10212 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10215 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10219 // Check for being able to broadcast a single element.
10220 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10221 Mask, Subtarget, DAG))
10224 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10225 // use lower latency instructions that will operate on both 128-bit lanes.
10226 SmallVector<int, 2> RepeatedMask;
10227 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10228 if (isSingleInputShuffleMask(Mask)) {
10229 int PSHUFDMask[] = {-1, -1, -1, -1};
10230 for (int i = 0; i < 2; ++i)
10231 if (RepeatedMask[i] >= 0) {
10232 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10233 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10235 return DAG.getBitcast(
10237 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10238 DAG.getBitcast(MVT::v8i32, V1),
10239 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10243 // AVX2 provides a direct instruction for permuting a single input across
10245 if (isSingleInputShuffleMask(Mask))
10246 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10247 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10249 // Try to use shift instructions.
10250 if (SDValue Shift =
10251 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10254 // Use dedicated unpack instructions for masks that match their pattern.
10255 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10256 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10257 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10258 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10259 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10260 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10261 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10262 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10264 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10265 // shuffle. However, if we have AVX2 and either inputs are already in place,
10266 // we will be able to shuffle even across lanes the other input in a single
10267 // instruction so skip this pattern.
10268 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10269 isShuffleMaskInputInPlace(1, Mask))))
10270 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10271 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10274 // Otherwise fall back on generic blend lowering.
10275 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10279 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10281 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10282 /// isn't available.
10283 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10284 const X86Subtarget *Subtarget,
10285 SelectionDAG &DAG) {
10287 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10288 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10289 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10290 ArrayRef<int> Mask = SVOp->getMask();
10291 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10293 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10297 // Check for being able to broadcast a single element.
10298 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10299 Mask, Subtarget, DAG))
10302 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10303 // options to efficiently lower the shuffle.
10304 SmallVector<int, 4> RepeatedMask;
10305 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10306 assert(RepeatedMask.size() == 4 &&
10307 "Repeated masks must be half the mask width!");
10309 // Use even/odd duplicate instructions for masks that match their pattern.
10310 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10311 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10312 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10313 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10315 if (isSingleInputShuffleMask(Mask))
10316 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10317 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10319 // Use dedicated unpack instructions for masks that match their pattern.
10320 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10321 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10322 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10323 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10324 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10325 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10326 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10327 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10329 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10330 // have already handled any direct blends. We also need to squash the
10331 // repeated mask into a simulated v4f32 mask.
10332 for (int i = 0; i < 4; ++i)
10333 if (RepeatedMask[i] >= 8)
10334 RepeatedMask[i] -= 4;
10335 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10338 // If we have a single input shuffle with different shuffle patterns in the
10339 // two 128-bit lanes use the variable mask to VPERMILPS.
10340 if (isSingleInputShuffleMask(Mask)) {
10341 SDValue VPermMask[8];
10342 for (int i = 0; i < 8; ++i)
10343 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10344 : DAG.getConstant(Mask[i], DL, MVT::i32);
10345 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10346 return DAG.getNode(
10347 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10348 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10350 if (Subtarget->hasAVX2())
10351 return DAG.getNode(
10352 X86ISD::VPERMV, DL, MVT::v8f32,
10353 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10354 MVT::v8i32, VPermMask)),
10357 // Otherwise, fall back.
10358 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10362 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10364 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10365 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10368 // If we have AVX2 then we always want to lower with a blend because at v8 we
10369 // can fully permute the elements.
10370 if (Subtarget->hasAVX2())
10371 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10374 // Otherwise fall back on generic lowering.
10375 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10378 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10380 /// This routine is only called when we have AVX2 and thus a reasonable
10381 /// instruction set for v8i32 shuffling..
10382 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10383 const X86Subtarget *Subtarget,
10384 SelectionDAG &DAG) {
10386 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10387 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10388 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10389 ArrayRef<int> Mask = SVOp->getMask();
10390 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10391 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10393 // Whenever we can lower this as a zext, that instruction is strictly faster
10394 // than any alternative. It also allows us to fold memory operands into the
10395 // shuffle in many cases.
10396 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10397 Mask, Subtarget, DAG))
10400 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10404 // Check for being able to broadcast a single element.
10405 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10406 Mask, Subtarget, DAG))
10409 // If the shuffle mask is repeated in each 128-bit lane we can use more
10410 // efficient instructions that mirror the shuffles across the two 128-bit
10412 SmallVector<int, 4> RepeatedMask;
10413 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10414 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10415 if (isSingleInputShuffleMask(Mask))
10416 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10417 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10419 // Use dedicated unpack instructions for masks that match their pattern.
10420 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10421 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10422 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10423 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10424 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10425 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10426 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10427 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10430 // Try to use shift instructions.
10431 if (SDValue Shift =
10432 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10435 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10436 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10439 // If the shuffle patterns aren't repeated but it is a single input, directly
10440 // generate a cross-lane VPERMD instruction.
10441 if (isSingleInputShuffleMask(Mask)) {
10442 SDValue VPermMask[8];
10443 for (int i = 0; i < 8; ++i)
10444 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10445 : DAG.getConstant(Mask[i], DL, MVT::i32);
10446 return DAG.getNode(
10447 X86ISD::VPERMV, DL, MVT::v8i32,
10448 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10451 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10453 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10454 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10457 // Otherwise fall back on generic blend lowering.
10458 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10462 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10464 /// This routine is only called when we have AVX2 and thus a reasonable
10465 /// instruction set for v16i16 shuffling..
10466 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10467 const X86Subtarget *Subtarget,
10468 SelectionDAG &DAG) {
10470 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10471 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10472 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10473 ArrayRef<int> Mask = SVOp->getMask();
10474 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10475 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10477 // Whenever we can lower this as a zext, that instruction is strictly faster
10478 // than any alternative. It also allows us to fold memory operands into the
10479 // shuffle in many cases.
10480 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10481 Mask, Subtarget, DAG))
10484 // Check for being able to broadcast a single element.
10485 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10486 Mask, Subtarget, DAG))
10489 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10493 // Use dedicated unpack instructions for masks that match their pattern.
10494 if (isShuffleEquivalent(V1, V2, Mask,
10495 {// First 128-bit lane:
10496 0, 16, 1, 17, 2, 18, 3, 19,
10497 // Second 128-bit lane:
10498 8, 24, 9, 25, 10, 26, 11, 27}))
10499 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10500 if (isShuffleEquivalent(V1, V2, Mask,
10501 {// First 128-bit lane:
10502 4, 20, 5, 21, 6, 22, 7, 23,
10503 // Second 128-bit lane:
10504 12, 28, 13, 29, 14, 30, 15, 31}))
10505 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10507 // Try to use shift instructions.
10508 if (SDValue Shift =
10509 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10512 // Try to use byte rotation instructions.
10513 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10514 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10517 if (isSingleInputShuffleMask(Mask)) {
10518 // There are no generalized cross-lane shuffle operations available on i16
10520 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10521 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10524 SmallVector<int, 8> RepeatedMask;
10525 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10526 // As this is a single-input shuffle, the repeated mask should be
10527 // a strictly valid v8i16 mask that we can pass through to the v8i16
10528 // lowering to handle even the v16 case.
10529 return lowerV8I16GeneralSingleInputVectorShuffle(
10530 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10533 SDValue PSHUFBMask[32];
10534 for (int i = 0; i < 16; ++i) {
10535 if (Mask[i] == -1) {
10536 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10540 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10541 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10542 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10543 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10545 return DAG.getBitcast(MVT::v16i16,
10546 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10547 DAG.getBitcast(MVT::v32i8, V1),
10548 DAG.getNode(ISD::BUILD_VECTOR, DL,
10549 MVT::v32i8, PSHUFBMask)));
10552 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10554 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10555 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10558 // Otherwise fall back on generic lowering.
10559 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10562 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10564 /// This routine is only called when we have AVX2 and thus a reasonable
10565 /// instruction set for v32i8 shuffling..
10566 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10567 const X86Subtarget *Subtarget,
10568 SelectionDAG &DAG) {
10570 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10571 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10573 ArrayRef<int> Mask = SVOp->getMask();
10574 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10575 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10577 // Whenever we can lower this as a zext, that instruction is strictly faster
10578 // than any alternative. It also allows us to fold memory operands into the
10579 // shuffle in many cases.
10580 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10581 Mask, Subtarget, DAG))
10584 // Check for being able to broadcast a single element.
10585 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10586 Mask, Subtarget, DAG))
10589 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10593 // Use dedicated unpack instructions for masks that match their pattern.
10594 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10596 if (isShuffleEquivalent(
10598 {// First 128-bit lane:
10599 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10600 // Second 128-bit lane:
10601 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10602 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10603 if (isShuffleEquivalent(
10605 {// First 128-bit lane:
10606 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10607 // Second 128-bit lane:
10608 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10609 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10611 // Try to use shift instructions.
10612 if (SDValue Shift =
10613 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10616 // Try to use byte rotation instructions.
10617 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10618 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10621 if (isSingleInputShuffleMask(Mask)) {
10622 // There are no generalized cross-lane shuffle operations available on i8
10624 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10625 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10628 SDValue PSHUFBMask[32];
10629 for (int i = 0; i < 32; ++i)
10632 ? DAG.getUNDEF(MVT::i8)
10633 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10636 return DAG.getNode(
10637 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10638 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10641 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10643 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10644 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10647 // Otherwise fall back on generic lowering.
10648 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10651 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10653 /// This routine either breaks down the specific type of a 256-bit x86 vector
10654 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10655 /// together based on the available instructions.
10656 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10657 MVT VT, const X86Subtarget *Subtarget,
10658 SelectionDAG &DAG) {
10660 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10661 ArrayRef<int> Mask = SVOp->getMask();
10663 // If we have a single input to the zero element, insert that into V1 if we
10664 // can do so cheaply.
10665 int NumElts = VT.getVectorNumElements();
10666 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10667 return M >= NumElts;
10670 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10671 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10672 DL, VT, V1, V2, Mask, Subtarget, DAG))
10675 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10676 // can check for those subtargets here and avoid much of the subtarget
10677 // querying in the per-vector-type lowering routines. With AVX1 we have
10678 // essentially *zero* ability to manipulate a 256-bit vector with integer
10679 // types. Since we'll use floating point types there eventually, just
10680 // immediately cast everything to a float and operate entirely in that domain.
10681 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10682 int ElementBits = VT.getScalarSizeInBits();
10683 if (ElementBits < 32)
10684 // No floating point type available, decompose into 128-bit vectors.
10685 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10687 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10688 VT.getVectorNumElements());
10689 V1 = DAG.getBitcast(FpVT, V1);
10690 V2 = DAG.getBitcast(FpVT, V2);
10691 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10694 switch (VT.SimpleTy) {
10696 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10698 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10700 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10702 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10704 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10706 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10709 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10713 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10714 ArrayRef<int> Mask, SDValue V1,
10715 SDValue V2, SelectionDAG &DAG) {
10717 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10719 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10720 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10722 SmallVector<SDValue, 32> VPermMask;
10723 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10724 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10725 DAG.getConstant(Mask[i], DL, MaskEltVT));
10726 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10728 if (isSingleInputShuffleMask(Mask))
10729 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10731 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10734 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10735 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10736 const X86Subtarget *Subtarget,
10737 SelectionDAG &DAG) {
10739 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10740 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10741 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10742 ArrayRef<int> Mask = SVOp->getMask();
10743 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10745 if (SDValue Unpck =
10746 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10749 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10752 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10753 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10754 const X86Subtarget *Subtarget,
10755 SelectionDAG &DAG) {
10757 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10758 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10759 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10760 ArrayRef<int> Mask = SVOp->getMask();
10761 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10763 if (SDValue Unpck =
10764 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10767 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10770 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10771 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10772 const X86Subtarget *Subtarget,
10773 SelectionDAG &DAG) {
10775 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10776 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10777 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10778 ArrayRef<int> Mask = SVOp->getMask();
10779 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10781 if (SDValue Unpck =
10782 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10785 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10788 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10789 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10790 const X86Subtarget *Subtarget,
10791 SelectionDAG &DAG) {
10793 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10794 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10795 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10796 ArrayRef<int> Mask = SVOp->getMask();
10797 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10799 if (SDValue Unpck =
10800 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10803 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10806 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10807 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10808 const X86Subtarget *Subtarget,
10809 SelectionDAG &DAG) {
10811 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10812 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10813 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10814 ArrayRef<int> Mask = SVOp->getMask();
10815 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10816 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10818 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10821 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10822 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10823 const X86Subtarget *Subtarget,
10824 SelectionDAG &DAG) {
10826 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10827 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10829 ArrayRef<int> Mask = SVOp->getMask();
10830 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10831 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10833 // FIXME: Implement direct support for this type!
10834 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10837 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10839 /// This routine either breaks down the specific type of a 512-bit x86 vector
10840 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10841 /// together based on the available instructions.
10842 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10843 MVT VT, const X86Subtarget *Subtarget,
10844 SelectionDAG &DAG) {
10846 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10847 ArrayRef<int> Mask = SVOp->getMask();
10848 assert(Subtarget->hasAVX512() &&
10849 "Cannot lower 512-bit vectors w/ basic ISA!");
10851 // Check for being able to broadcast a single element.
10852 if (SDValue Broadcast =
10853 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10856 // Dispatch to each element type for lowering. If we don't have supprot for
10857 // specific element type shuffles at 512 bits, immediately split them and
10858 // lower them. Each lowering routine of a given type is allowed to assume that
10859 // the requisite ISA extensions for that element type are available.
10860 switch (VT.SimpleTy) {
10862 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10864 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10866 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10870 if (Subtarget->hasBWI())
10871 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10874 if (Subtarget->hasBWI())
10875 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10879 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10882 // Otherwise fall back on splitting.
10883 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10886 // Lower vXi1 vector shuffles.
10887 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10888 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10889 // vector, shuffle and then truncate it back.
10890 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10891 MVT VT, const X86Subtarget *Subtarget,
10892 SelectionDAG &DAG) {
10894 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10895 ArrayRef<int> Mask = SVOp->getMask();
10896 assert(Subtarget->hasAVX512() &&
10897 "Cannot lower 512-bit vectors w/o basic ISA!");
10899 switch (VT.SimpleTy) {
10901 assert(false && "Expected a vector of i1 elements");
10904 ExtVT = MVT::v2i64;
10907 ExtVT = MVT::v4i32;
10910 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10913 ExtVT = MVT::v16i32;
10916 ExtVT = MVT::v32i16;
10919 ExtVT = MVT::v64i8;
10923 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10924 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10925 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10926 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10928 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10931 V2 = DAG.getUNDEF(ExtVT);
10932 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10933 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10934 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10935 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10937 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10938 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10939 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10941 /// \brief Top-level lowering for x86 vector shuffles.
10943 /// This handles decomposition, canonicalization, and lowering of all x86
10944 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10945 /// above in helper routines. The canonicalization attempts to widen shuffles
10946 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10947 /// s.t. only one of the two inputs needs to be tested, etc.
10948 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10949 SelectionDAG &DAG) {
10950 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10951 ArrayRef<int> Mask = SVOp->getMask();
10952 SDValue V1 = Op.getOperand(0);
10953 SDValue V2 = Op.getOperand(1);
10954 MVT VT = Op.getSimpleValueType();
10955 int NumElements = VT.getVectorNumElements();
10957 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10959 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10960 "Can't lower MMX shuffles");
10962 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10963 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10964 if (V1IsUndef && V2IsUndef)
10965 return DAG.getUNDEF(VT);
10967 // When we create a shuffle node we put the UNDEF node to second operand,
10968 // but in some cases the first operand may be transformed to UNDEF.
10969 // In this case we should just commute the node.
10971 return DAG.getCommutedVectorShuffle(*SVOp);
10973 // Check for non-undef masks pointing at an undef vector and make the masks
10974 // undef as well. This makes it easier to match the shuffle based solely on
10978 if (M >= NumElements) {
10979 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10980 for (int &M : NewMask)
10981 if (M >= NumElements)
10983 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10986 // We actually see shuffles that are entirely re-arrangements of a set of
10987 // zero inputs. This mostly happens while decomposing complex shuffles into
10988 // simple ones. Directly lower these as a buildvector of zeros.
10989 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10990 if (Zeroable.all())
10991 return getZeroVector(VT, Subtarget, DAG, dl);
10993 // Try to collapse shuffles into using a vector type with fewer elements but
10994 // wider element types. We cap this to not form integers or floating point
10995 // elements wider than 64 bits, but it might be interesting to form i128
10996 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10997 SmallVector<int, 16> WidenedMask;
10998 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
10999 canWidenShuffleElements(Mask, WidenedMask)) {
11000 MVT NewEltVT = VT.isFloatingPoint()
11001 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11002 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11003 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11004 // Make sure that the new vector type is legal. For example, v2f64 isn't
11006 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11007 V1 = DAG.getBitcast(NewVT, V1);
11008 V2 = DAG.getBitcast(NewVT, V2);
11009 return DAG.getBitcast(
11010 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11014 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11015 for (int M : SVOp->getMask())
11017 ++NumUndefElements;
11018 else if (M < NumElements)
11023 // Commute the shuffle as needed such that more elements come from V1 than
11024 // V2. This allows us to match the shuffle pattern strictly on how many
11025 // elements come from V1 without handling the symmetric cases.
11026 if (NumV2Elements > NumV1Elements)
11027 return DAG.getCommutedVectorShuffle(*SVOp);
11029 // When the number of V1 and V2 elements are the same, try to minimize the
11030 // number of uses of V2 in the low half of the vector. When that is tied,
11031 // ensure that the sum of indices for V1 is equal to or lower than the sum
11032 // indices for V2. When those are equal, try to ensure that the number of odd
11033 // indices for V1 is lower than the number of odd indices for V2.
11034 if (NumV1Elements == NumV2Elements) {
11035 int LowV1Elements = 0, LowV2Elements = 0;
11036 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11037 if (M >= NumElements)
11041 if (LowV2Elements > LowV1Elements) {
11042 return DAG.getCommutedVectorShuffle(*SVOp);
11043 } else if (LowV2Elements == LowV1Elements) {
11044 int SumV1Indices = 0, SumV2Indices = 0;
11045 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11046 if (SVOp->getMask()[i] >= NumElements)
11048 else if (SVOp->getMask()[i] >= 0)
11050 if (SumV2Indices < SumV1Indices) {
11051 return DAG.getCommutedVectorShuffle(*SVOp);
11052 } else if (SumV2Indices == SumV1Indices) {
11053 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11054 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11055 if (SVOp->getMask()[i] >= NumElements)
11056 NumV2OddIndices += i % 2;
11057 else if (SVOp->getMask()[i] >= 0)
11058 NumV1OddIndices += i % 2;
11059 if (NumV2OddIndices < NumV1OddIndices)
11060 return DAG.getCommutedVectorShuffle(*SVOp);
11065 // For each vector width, delegate to a specialized lowering routine.
11066 if (VT.getSizeInBits() == 128)
11067 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11069 if (VT.getSizeInBits() == 256)
11070 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11072 if (VT.getSizeInBits() == 512)
11073 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11076 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11077 llvm_unreachable("Unimplemented!");
11080 // This function assumes its argument is a BUILD_VECTOR of constants or
11081 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11083 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11084 unsigned &MaskValue) {
11086 unsigned NumElems = BuildVector->getNumOperands();
11087 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11088 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11089 unsigned NumElemsInLane = NumElems / NumLanes;
11091 // Blend for v16i16 should be symmetric for the both lanes.
11092 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11093 SDValue EltCond = BuildVector->getOperand(i);
11094 SDValue SndLaneEltCond =
11095 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11097 int Lane1Cond = -1, Lane2Cond = -1;
11098 if (isa<ConstantSDNode>(EltCond))
11099 Lane1Cond = !isZero(EltCond);
11100 if (isa<ConstantSDNode>(SndLaneEltCond))
11101 Lane2Cond = !isZero(SndLaneEltCond);
11103 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11104 // Lane1Cond != 0, means we want the first argument.
11105 // Lane1Cond == 0, means we want the second argument.
11106 // The encoding of this argument is 0 for the first argument, 1
11107 // for the second. Therefore, invert the condition.
11108 MaskValue |= !Lane1Cond << i;
11109 else if (Lane1Cond < 0)
11110 MaskValue |= !Lane2Cond << i;
11117 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11118 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11119 const X86Subtarget *Subtarget,
11120 SelectionDAG &DAG) {
11121 SDValue Cond = Op.getOperand(0);
11122 SDValue LHS = Op.getOperand(1);
11123 SDValue RHS = Op.getOperand(2);
11125 MVT VT = Op.getSimpleValueType();
11127 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11129 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11131 // Only non-legal VSELECTs reach this lowering, convert those into generic
11132 // shuffles and re-use the shuffle lowering path for blends.
11133 SmallVector<int, 32> Mask;
11134 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11135 SDValue CondElt = CondBV->getOperand(i);
11137 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11139 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11142 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11143 // A vselect where all conditions and data are constants can be optimized into
11144 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11145 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11146 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11147 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11150 // Try to lower this to a blend-style vector shuffle. This can handle all
11151 // constant condition cases.
11152 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11155 // Variable blends are only legal from SSE4.1 onward.
11156 if (!Subtarget->hasSSE41())
11159 // Only some types will be legal on some subtargets. If we can emit a legal
11160 // VSELECT-matching blend, return Op, and but if we need to expand, return
11162 switch (Op.getSimpleValueType().SimpleTy) {
11164 // Most of the vector types have blends past SSE4.1.
11168 // The byte blends for AVX vectors were introduced only in AVX2.
11169 if (Subtarget->hasAVX2())
11176 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11177 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11180 // FIXME: We should custom lower this by fixing the condition and using i8
11186 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11187 MVT VT = Op.getSimpleValueType();
11190 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11193 if (VT.getSizeInBits() == 8) {
11194 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11195 Op.getOperand(0), Op.getOperand(1));
11196 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11197 DAG.getValueType(VT));
11198 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11201 if (VT.getSizeInBits() == 16) {
11202 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11203 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11205 return DAG.getNode(
11206 ISD::TRUNCATE, dl, MVT::i16,
11207 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11208 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11209 Op.getOperand(1)));
11210 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11211 Op.getOperand(0), Op.getOperand(1));
11212 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11213 DAG.getValueType(VT));
11214 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11217 if (VT == MVT::f32) {
11218 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11219 // the result back to FR32 register. It's only worth matching if the
11220 // result has a single use which is a store or a bitcast to i32. And in
11221 // the case of a store, it's not worth it if the index is a constant 0,
11222 // because a MOVSSmr can be used instead, which is smaller and faster.
11223 if (!Op.hasOneUse())
11225 SDNode *User = *Op.getNode()->use_begin();
11226 if ((User->getOpcode() != ISD::STORE ||
11227 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11228 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11229 (User->getOpcode() != ISD::BITCAST ||
11230 User->getValueType(0) != MVT::i32))
11232 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11233 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11235 return DAG.getBitcast(MVT::f32, Extract);
11238 if (VT == MVT::i32 || VT == MVT::i64) {
11239 // ExtractPS/pextrq works with constant index.
11240 if (isa<ConstantSDNode>(Op.getOperand(1)))
11246 /// Extract one bit from mask vector, like v16i1 or v8i1.
11247 /// AVX-512 feature.
11249 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11250 SDValue Vec = Op.getOperand(0);
11252 MVT VecVT = Vec.getSimpleValueType();
11253 SDValue Idx = Op.getOperand(1);
11254 MVT EltVT = Op.getSimpleValueType();
11256 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11257 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11258 "Unexpected vector type in ExtractBitFromMaskVector");
11260 // variable index can't be handled in mask registers,
11261 // extend vector to VR512
11262 if (!isa<ConstantSDNode>(Idx)) {
11263 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11264 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11265 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11266 ExtVT.getVectorElementType(), Ext, Idx);
11267 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11270 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11271 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11272 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11273 rc = getRegClassFor(MVT::v16i1);
11274 unsigned MaxSift = rc->getSize()*8 - 1;
11275 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11276 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11277 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11278 DAG.getConstant(MaxSift, dl, MVT::i8));
11279 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11280 DAG.getIntPtrConstant(0, dl));
11284 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11285 SelectionDAG &DAG) const {
11287 SDValue Vec = Op.getOperand(0);
11288 MVT VecVT = Vec.getSimpleValueType();
11289 SDValue Idx = Op.getOperand(1);
11291 if (Op.getSimpleValueType() == MVT::i1)
11292 return ExtractBitFromMaskVector(Op, DAG);
11294 if (!isa<ConstantSDNode>(Idx)) {
11295 if (VecVT.is512BitVector() ||
11296 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11297 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11300 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11301 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11302 MaskEltVT.getSizeInBits());
11304 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11305 auto PtrVT = getPointerTy(DAG.getDataLayout());
11306 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11307 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11308 DAG.getConstant(0, dl, PtrVT));
11309 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11310 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11311 DAG.getConstant(0, dl, PtrVT));
11316 // If this is a 256-bit vector result, first extract the 128-bit vector and
11317 // then extract the element from the 128-bit vector.
11318 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11320 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11321 // Get the 128-bit vector.
11322 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11323 MVT EltVT = VecVT.getVectorElementType();
11325 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11327 //if (IdxVal >= NumElems/2)
11328 // IdxVal -= NumElems/2;
11329 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11330 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11331 DAG.getConstant(IdxVal, dl, MVT::i32));
11334 assert(VecVT.is128BitVector() && "Unexpected vector length");
11336 if (Subtarget->hasSSE41())
11337 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11340 MVT VT = Op.getSimpleValueType();
11341 // TODO: handle v16i8.
11342 if (VT.getSizeInBits() == 16) {
11343 SDValue Vec = Op.getOperand(0);
11344 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11346 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11347 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11348 DAG.getBitcast(MVT::v4i32, Vec),
11349 Op.getOperand(1)));
11350 // Transform it so it match pextrw which produces a 32-bit result.
11351 MVT EltVT = MVT::i32;
11352 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11353 Op.getOperand(0), Op.getOperand(1));
11354 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11355 DAG.getValueType(VT));
11356 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11359 if (VT.getSizeInBits() == 32) {
11360 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11364 // SHUFPS the element to the lowest double word, then movss.
11365 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11366 MVT VVT = Op.getOperand(0).getSimpleValueType();
11367 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11368 DAG.getUNDEF(VVT), Mask);
11369 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11370 DAG.getIntPtrConstant(0, dl));
11373 if (VT.getSizeInBits() == 64) {
11374 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11375 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11376 // to match extract_elt for f64.
11377 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11381 // UNPCKHPD the element to the lowest double word, then movsd.
11382 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11383 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11384 int Mask[2] = { 1, -1 };
11385 MVT VVT = Op.getOperand(0).getSimpleValueType();
11386 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11387 DAG.getUNDEF(VVT), Mask);
11388 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11389 DAG.getIntPtrConstant(0, dl));
11395 /// Insert one bit to mask vector, like v16i1 or v8i1.
11396 /// AVX-512 feature.
11398 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11400 SDValue Vec = Op.getOperand(0);
11401 SDValue Elt = Op.getOperand(1);
11402 SDValue Idx = Op.getOperand(2);
11403 MVT VecVT = Vec.getSimpleValueType();
11405 if (!isa<ConstantSDNode>(Idx)) {
11406 // Non constant index. Extend source and destination,
11407 // insert element and then truncate the result.
11408 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11409 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11410 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11411 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11412 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11413 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11416 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11417 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11419 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11420 DAG.getConstant(IdxVal, dl, MVT::i8));
11421 if (Vec.getOpcode() == ISD::UNDEF)
11423 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11426 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11427 SelectionDAG &DAG) const {
11428 MVT VT = Op.getSimpleValueType();
11429 MVT EltVT = VT.getVectorElementType();
11431 if (EltVT == MVT::i1)
11432 return InsertBitToMaskVector(Op, DAG);
11435 SDValue N0 = Op.getOperand(0);
11436 SDValue N1 = Op.getOperand(1);
11437 SDValue N2 = Op.getOperand(2);
11438 if (!isa<ConstantSDNode>(N2))
11440 auto *N2C = cast<ConstantSDNode>(N2);
11441 unsigned IdxVal = N2C->getZExtValue();
11443 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11444 // into that, and then insert the subvector back into the result.
11445 if (VT.is256BitVector() || VT.is512BitVector()) {
11446 // With a 256-bit vector, we can insert into the zero element efficiently
11447 // using a blend if we have AVX or AVX2 and the right data type.
11448 if (VT.is256BitVector() && IdxVal == 0) {
11449 // TODO: It is worthwhile to cast integer to floating point and back
11450 // and incur a domain crossing penalty if that's what we'll end up
11451 // doing anyway after extracting to a 128-bit vector.
11452 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11453 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11454 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11455 N2 = DAG.getIntPtrConstant(1, dl);
11456 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11460 // Get the desired 128-bit vector chunk.
11461 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11463 // Insert the element into the desired chunk.
11464 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11465 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11467 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11468 DAG.getConstant(IdxIn128, dl, MVT::i32));
11470 // Insert the changed part back into the bigger vector
11471 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11473 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11475 if (Subtarget->hasSSE41()) {
11476 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11478 if (VT == MVT::v8i16) {
11479 Opc = X86ISD::PINSRW;
11481 assert(VT == MVT::v16i8);
11482 Opc = X86ISD::PINSRB;
11485 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11487 if (N1.getValueType() != MVT::i32)
11488 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11489 if (N2.getValueType() != MVT::i32)
11490 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11491 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11494 if (EltVT == MVT::f32) {
11495 // Bits [7:6] of the constant are the source select. This will always be
11496 // zero here. The DAG Combiner may combine an extract_elt index into
11497 // these bits. For example (insert (extract, 3), 2) could be matched by
11498 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11499 // Bits [5:4] of the constant are the destination select. This is the
11500 // value of the incoming immediate.
11501 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11502 // combine either bitwise AND or insert of float 0.0 to set these bits.
11504 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11505 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11506 // If this is an insertion of 32-bits into the low 32-bits of
11507 // a vector, we prefer to generate a blend with immediate rather
11508 // than an insertps. Blends are simpler operations in hardware and so
11509 // will always have equal or better performance than insertps.
11510 // But if optimizing for size and there's a load folding opportunity,
11511 // generate insertps because blendps does not have a 32-bit memory
11513 N2 = DAG.getIntPtrConstant(1, dl);
11514 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11515 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11517 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11518 // Create this as a scalar to vector..
11519 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11520 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11523 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11524 // PINSR* works with constant index.
11529 if (EltVT == MVT::i8)
11532 if (EltVT.getSizeInBits() == 16) {
11533 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11534 // as its second argument.
11535 if (N1.getValueType() != MVT::i32)
11536 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11537 if (N2.getValueType() != MVT::i32)
11538 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11539 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11544 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11546 MVT OpVT = Op.getSimpleValueType();
11548 // If this is a 256-bit vector result, first insert into a 128-bit
11549 // vector and then insert into the 256-bit vector.
11550 if (!OpVT.is128BitVector()) {
11551 // Insert into a 128-bit vector.
11552 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11553 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11554 OpVT.getVectorNumElements() / SizeFactor);
11556 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11558 // Insert the 128-bit vector.
11559 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11562 if (OpVT == MVT::v1i64 &&
11563 Op.getOperand(0).getValueType() == MVT::i64)
11564 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11566 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11567 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11568 return DAG.getBitcast(
11569 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11572 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11573 // a simple subregister reference or explicit instructions to grab
11574 // upper bits of a vector.
11575 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11576 SelectionDAG &DAG) {
11578 SDValue In = Op.getOperand(0);
11579 SDValue Idx = Op.getOperand(1);
11580 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11581 MVT ResVT = Op.getSimpleValueType();
11582 MVT InVT = In.getSimpleValueType();
11584 if (Subtarget->hasFp256()) {
11585 if (ResVT.is128BitVector() &&
11586 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11587 isa<ConstantSDNode>(Idx)) {
11588 return Extract128BitVector(In, IdxVal, DAG, dl);
11590 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11591 isa<ConstantSDNode>(Idx)) {
11592 return Extract256BitVector(In, IdxVal, DAG, dl);
11598 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11599 // simple superregister reference or explicit instructions to insert
11600 // the upper bits of a vector.
11601 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11602 SelectionDAG &DAG) {
11603 if (!Subtarget->hasAVX())
11607 SDValue Vec = Op.getOperand(0);
11608 SDValue SubVec = Op.getOperand(1);
11609 SDValue Idx = Op.getOperand(2);
11611 if (!isa<ConstantSDNode>(Idx))
11614 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11615 MVT OpVT = Op.getSimpleValueType();
11616 MVT SubVecVT = SubVec.getSimpleValueType();
11618 // Fold two 16-byte subvector loads into one 32-byte load:
11619 // (insert_subvector (insert_subvector undef, (load addr), 0),
11620 // (load addr + 16), Elts/2)
11622 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11623 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11624 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11625 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11626 if (Idx2 && Idx2->getZExtValue() == 0) {
11627 SDValue SubVec2 = Vec.getOperand(1);
11628 // If needed, look through a bitcast to get to the load.
11629 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11630 SubVec2 = SubVec2.getOperand(0);
11632 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11634 unsigned Alignment = FirstLd->getAlignment();
11635 unsigned AS = FirstLd->getAddressSpace();
11636 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11637 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11638 OpVT, AS, Alignment, &Fast) && Fast) {
11639 SDValue Ops[] = { SubVec2, SubVec };
11640 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11647 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11648 SubVecVT.is128BitVector())
11649 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11651 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11652 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11654 if (OpVT.getVectorElementType() == MVT::i1) {
11655 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11657 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11658 SDValue Undef = DAG.getUNDEF(OpVT);
11659 unsigned NumElems = OpVT.getVectorNumElements();
11660 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11662 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11663 // Zero upper bits of the Vec
11664 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11665 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11667 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11669 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11670 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11673 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11675 // Zero upper bits of the Vec2
11676 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11677 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11678 // Zero lower bits of the Vec
11679 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11680 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11681 // Merge them together
11682 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11688 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11689 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11690 // one of the above mentioned nodes. It has to be wrapped because otherwise
11691 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11692 // be used to form addressing mode. These wrapped nodes will be selected
11695 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11696 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11698 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11699 // global base reg.
11700 unsigned char OpFlag = 0;
11701 unsigned WrapperKind = X86ISD::Wrapper;
11702 CodeModel::Model M = DAG.getTarget().getCodeModel();
11704 if (Subtarget->isPICStyleRIPRel() &&
11705 (M == CodeModel::Small || M == CodeModel::Kernel))
11706 WrapperKind = X86ISD::WrapperRIP;
11707 else if (Subtarget->isPICStyleGOT())
11708 OpFlag = X86II::MO_GOTOFF;
11709 else if (Subtarget->isPICStyleStubPIC())
11710 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11712 auto PtrVT = getPointerTy(DAG.getDataLayout());
11713 SDValue Result = DAG.getTargetConstantPool(
11714 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11716 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11717 // With PIC, the address is actually $g + Offset.
11720 DAG.getNode(ISD::ADD, DL, PtrVT,
11721 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11727 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11728 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11730 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11731 // global base reg.
11732 unsigned char OpFlag = 0;
11733 unsigned WrapperKind = X86ISD::Wrapper;
11734 CodeModel::Model M = DAG.getTarget().getCodeModel();
11736 if (Subtarget->isPICStyleRIPRel() &&
11737 (M == CodeModel::Small || M == CodeModel::Kernel))
11738 WrapperKind = X86ISD::WrapperRIP;
11739 else if (Subtarget->isPICStyleGOT())
11740 OpFlag = X86II::MO_GOTOFF;
11741 else if (Subtarget->isPICStyleStubPIC())
11742 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11744 auto PtrVT = getPointerTy(DAG.getDataLayout());
11745 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11747 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11749 // With PIC, the address is actually $g + Offset.
11752 DAG.getNode(ISD::ADD, DL, PtrVT,
11753 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11759 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11760 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11762 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11763 // global base reg.
11764 unsigned char OpFlag = 0;
11765 unsigned WrapperKind = X86ISD::Wrapper;
11766 CodeModel::Model M = DAG.getTarget().getCodeModel();
11768 if (Subtarget->isPICStyleRIPRel() &&
11769 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11770 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11771 OpFlag = X86II::MO_GOTPCREL;
11772 WrapperKind = X86ISD::WrapperRIP;
11773 } else if (Subtarget->isPICStyleGOT()) {
11774 OpFlag = X86II::MO_GOT;
11775 } else if (Subtarget->isPICStyleStubPIC()) {
11776 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11777 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11778 OpFlag = X86II::MO_DARWIN_NONLAZY;
11781 auto PtrVT = getPointerTy(DAG.getDataLayout());
11782 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11785 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11787 // With PIC, the address is actually $g + Offset.
11788 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11789 !Subtarget->is64Bit()) {
11791 DAG.getNode(ISD::ADD, DL, PtrVT,
11792 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11795 // For symbols that require a load from a stub to get the address, emit the
11797 if (isGlobalStubReference(OpFlag))
11798 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11799 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11800 false, false, false, 0);
11806 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11807 // Create the TargetBlockAddressAddress node.
11808 unsigned char OpFlags =
11809 Subtarget->ClassifyBlockAddressReference();
11810 CodeModel::Model M = DAG.getTarget().getCodeModel();
11811 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11812 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11814 auto PtrVT = getPointerTy(DAG.getDataLayout());
11815 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11817 if (Subtarget->isPICStyleRIPRel() &&
11818 (M == CodeModel::Small || M == CodeModel::Kernel))
11819 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11821 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11823 // With PIC, the address is actually $g + Offset.
11824 if (isGlobalRelativeToPICBase(OpFlags)) {
11825 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11826 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11833 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11834 int64_t Offset, SelectionDAG &DAG) const {
11835 // Create the TargetGlobalAddress node, folding in the constant
11836 // offset if it is legal.
11837 unsigned char OpFlags =
11838 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11839 CodeModel::Model M = DAG.getTarget().getCodeModel();
11840 auto PtrVT = getPointerTy(DAG.getDataLayout());
11842 if (OpFlags == X86II::MO_NO_FLAG &&
11843 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11844 // A direct static reference to a global.
11845 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11848 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11851 if (Subtarget->isPICStyleRIPRel() &&
11852 (M == CodeModel::Small || M == CodeModel::Kernel))
11853 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11855 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11857 // With PIC, the address is actually $g + Offset.
11858 if (isGlobalRelativeToPICBase(OpFlags)) {
11859 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11860 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11863 // For globals that require a load from a stub to get the address, emit the
11865 if (isGlobalStubReference(OpFlags))
11866 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11867 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11868 false, false, false, 0);
11870 // If there was a non-zero offset that we didn't fold, create an explicit
11871 // addition for it.
11873 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11874 DAG.getConstant(Offset, dl, PtrVT));
11880 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11881 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11882 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11883 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11887 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11888 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11889 unsigned char OperandFlags, bool LocalDynamic = false) {
11890 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11891 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11893 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11894 GA->getValueType(0),
11898 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11902 SDValue Ops[] = { Chain, TGA, *InFlag };
11903 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11905 SDValue Ops[] = { Chain, TGA };
11906 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11909 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11910 MFI->setAdjustsStack(true);
11911 MFI->setHasCalls(true);
11913 SDValue Flag = Chain.getValue(1);
11914 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11917 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11919 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11922 SDLoc dl(GA); // ? function entry point might be better
11923 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11924 DAG.getNode(X86ISD::GlobalBaseReg,
11925 SDLoc(), PtrVT), InFlag);
11926 InFlag = Chain.getValue(1);
11928 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11931 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11933 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11935 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11936 X86::RAX, X86II::MO_TLSGD);
11939 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11945 // Get the start address of the TLS block for this module.
11946 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11947 .getInfo<X86MachineFunctionInfo>();
11948 MFI->incNumLocalDynamicTLSAccesses();
11952 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11953 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11956 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11957 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11958 InFlag = Chain.getValue(1);
11959 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11960 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11963 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11967 unsigned char OperandFlags = X86II::MO_DTPOFF;
11968 unsigned WrapperKind = X86ISD::Wrapper;
11969 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11970 GA->getValueType(0),
11971 GA->getOffset(), OperandFlags);
11972 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11974 // Add x@dtpoff with the base.
11975 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11978 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11979 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11980 const EVT PtrVT, TLSModel::Model model,
11981 bool is64Bit, bool isPIC) {
11984 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11985 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11986 is64Bit ? 257 : 256));
11988 SDValue ThreadPointer =
11989 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11990 MachinePointerInfo(Ptr), false, false, false, 0);
11992 unsigned char OperandFlags = 0;
11993 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11995 unsigned WrapperKind = X86ISD::Wrapper;
11996 if (model == TLSModel::LocalExec) {
11997 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11998 } else if (model == TLSModel::InitialExec) {
12000 OperandFlags = X86II::MO_GOTTPOFF;
12001 WrapperKind = X86ISD::WrapperRIP;
12003 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12006 llvm_unreachable("Unexpected model");
12009 // emit "addl x@ntpoff,%eax" (local exec)
12010 // or "addl x@indntpoff,%eax" (initial exec)
12011 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12013 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12014 GA->getOffset(), OperandFlags);
12015 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12017 if (model == TLSModel::InitialExec) {
12018 if (isPIC && !is64Bit) {
12019 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12020 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12024 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12025 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12026 false, false, false, 0);
12029 // The address of the thread local variable is the add of the thread
12030 // pointer with the offset of the variable.
12031 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12035 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12037 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12038 const GlobalValue *GV = GA->getGlobal();
12039 auto PtrVT = getPointerTy(DAG.getDataLayout());
12041 if (Subtarget->isTargetELF()) {
12042 if (DAG.getTarget().Options.EmulatedTLS)
12043 return LowerToTLSEmulatedModel(GA, DAG);
12044 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12046 case TLSModel::GeneralDynamic:
12047 if (Subtarget->is64Bit())
12048 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12049 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12050 case TLSModel::LocalDynamic:
12051 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12052 Subtarget->is64Bit());
12053 case TLSModel::InitialExec:
12054 case TLSModel::LocalExec:
12055 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12056 DAG.getTarget().getRelocationModel() ==
12059 llvm_unreachable("Unknown TLS model.");
12062 if (Subtarget->isTargetDarwin()) {
12063 // Darwin only has one model of TLS. Lower to that.
12064 unsigned char OpFlag = 0;
12065 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12066 X86ISD::WrapperRIP : X86ISD::Wrapper;
12068 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12069 // global base reg.
12070 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12071 !Subtarget->is64Bit();
12073 OpFlag = X86II::MO_TLVP_PIC_BASE;
12075 OpFlag = X86II::MO_TLVP;
12077 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12078 GA->getValueType(0),
12079 GA->getOffset(), OpFlag);
12080 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12082 // With PIC32, the address is actually $g + Offset.
12084 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12085 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12088 // Lowering the machine isd will make sure everything is in the right
12090 SDValue Chain = DAG.getEntryNode();
12091 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12092 SDValue Args[] = { Chain, Offset };
12093 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12095 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12096 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12097 MFI->setAdjustsStack(true);
12099 // And our return value (tls address) is in the standard call return value
12101 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12102 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12105 if (Subtarget->isTargetKnownWindowsMSVC() ||
12106 Subtarget->isTargetWindowsGNU()) {
12107 // Just use the implicit TLS architecture
12108 // Need to generate someting similar to:
12109 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12111 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12112 // mov rcx, qword [rdx+rcx*8]
12113 // mov eax, .tls$:tlsvar
12114 // [rax+rcx] contains the address
12115 // Windows 64bit: gs:0x58
12116 // Windows 32bit: fs:__tls_array
12119 SDValue Chain = DAG.getEntryNode();
12121 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12122 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12123 // use its literal value of 0x2C.
12124 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12125 ? Type::getInt8PtrTy(*DAG.getContext(),
12127 : Type::getInt32PtrTy(*DAG.getContext(),
12130 SDValue TlsArray = Subtarget->is64Bit()
12131 ? DAG.getIntPtrConstant(0x58, dl)
12132 : (Subtarget->isTargetWindowsGNU()
12133 ? DAG.getIntPtrConstant(0x2C, dl)
12134 : DAG.getExternalSymbol("_tls_array", PtrVT));
12136 SDValue ThreadPointer =
12137 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12141 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12142 res = ThreadPointer;
12144 // Load the _tls_index variable
12145 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12146 if (Subtarget->is64Bit())
12147 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12148 MachinePointerInfo(), MVT::i32, false, false,
12151 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12154 auto &DL = DAG.getDataLayout();
12156 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12157 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12159 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12162 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12165 // Get the offset of start of .tls section
12166 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12167 GA->getValueType(0),
12168 GA->getOffset(), X86II::MO_SECREL);
12169 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12171 // The address of the thread local variable is the add of the thread
12172 // pointer with the offset of the variable.
12173 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12176 llvm_unreachable("TLS not implemented for this target.");
12179 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12180 /// and take a 2 x i32 value to shift plus a shift amount.
12181 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12182 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12183 MVT VT = Op.getSimpleValueType();
12184 unsigned VTBits = VT.getSizeInBits();
12186 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12187 SDValue ShOpLo = Op.getOperand(0);
12188 SDValue ShOpHi = Op.getOperand(1);
12189 SDValue ShAmt = Op.getOperand(2);
12190 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12191 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12193 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12194 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12195 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12196 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12197 : DAG.getConstant(0, dl, VT);
12199 SDValue Tmp2, Tmp3;
12200 if (Op.getOpcode() == ISD::SHL_PARTS) {
12201 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12202 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12204 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12205 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12208 // If the shift amount is larger or equal than the width of a part we can't
12209 // rely on the results of shld/shrd. Insert a test and select the appropriate
12210 // values for large shift amounts.
12211 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12212 DAG.getConstant(VTBits, dl, MVT::i8));
12213 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12214 AndNode, DAG.getConstant(0, dl, MVT::i8));
12217 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12218 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12219 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12221 if (Op.getOpcode() == ISD::SHL_PARTS) {
12222 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12223 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12225 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12226 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12229 SDValue Ops[2] = { Lo, Hi };
12230 return DAG.getMergeValues(Ops, dl);
12233 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12234 SelectionDAG &DAG) const {
12235 SDValue Src = Op.getOperand(0);
12236 MVT SrcVT = Src.getSimpleValueType();
12237 MVT VT = Op.getSimpleValueType();
12240 if (SrcVT.isVector()) {
12241 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12242 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12243 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12244 DAG.getUNDEF(SrcVT)));
12246 if (SrcVT.getVectorElementType() == MVT::i1) {
12247 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12248 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12249 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12254 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12255 "Unknown SINT_TO_FP to lower!");
12257 // These are really Legal; return the operand so the caller accepts it as
12259 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12261 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12262 Subtarget->is64Bit()) {
12266 unsigned Size = SrcVT.getSizeInBits()/8;
12267 MachineFunction &MF = DAG.getMachineFunction();
12268 auto PtrVT = getPointerTy(MF.getDataLayout());
12269 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12270 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12271 SDValue Chain = DAG.getStore(
12272 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12273 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12275 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12278 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12280 SelectionDAG &DAG) const {
12284 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12286 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12288 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12290 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12292 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12293 MachineMemOperand *MMO;
12295 int SSFI = FI->getIndex();
12296 MMO = DAG.getMachineFunction().getMachineMemOperand(
12297 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12298 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12300 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12301 StackSlot = StackSlot.getOperand(1);
12303 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12304 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12306 Tys, Ops, SrcVT, MMO);
12309 Chain = Result.getValue(1);
12310 SDValue InFlag = Result.getValue(2);
12312 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12313 // shouldn't be necessary except that RFP cannot be live across
12314 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12315 MachineFunction &MF = DAG.getMachineFunction();
12316 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12317 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12318 auto PtrVT = getPointerTy(MF.getDataLayout());
12319 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12320 Tys = DAG.getVTList(MVT::Other);
12322 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12324 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12325 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12326 MachineMemOperand::MOStore, SSFISize, SSFISize);
12328 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12329 Ops, Op.getValueType(), MMO);
12330 Result = DAG.getLoad(
12331 Op.getValueType(), DL, Chain, StackSlot,
12332 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12333 false, false, false, 0);
12339 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12340 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12341 SelectionDAG &DAG) const {
12342 // This algorithm is not obvious. Here it is what we're trying to output:
12345 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12346 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12348 haddpd %xmm0, %xmm0
12350 pshufd $0x4e, %xmm0, %xmm1
12356 LLVMContext *Context = DAG.getContext();
12358 // Build some magic constants.
12359 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12360 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12361 auto PtrVT = getPointerTy(DAG.getDataLayout());
12362 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12364 SmallVector<Constant*,2> CV1;
12366 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12367 APInt(64, 0x4330000000000000ULL))));
12369 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12370 APInt(64, 0x4530000000000000ULL))));
12371 Constant *C1 = ConstantVector::get(CV1);
12372 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12374 // Load the 64-bit value into an XMM register.
12375 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12378 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12379 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12380 false, false, false, 16);
12382 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12385 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12386 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12387 false, false, false, 16);
12388 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12389 // TODO: Are there any fast-math-flags to propagate here?
12390 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12393 if (Subtarget->hasSSE3()) {
12394 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12395 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12397 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12398 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12400 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12401 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12404 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12405 DAG.getIntPtrConstant(0, dl));
12408 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12409 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12410 SelectionDAG &DAG) const {
12412 // FP constant to bias correct the final result.
12413 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12416 // Load the 32-bit value into an XMM register.
12417 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12420 // Zero out the upper parts of the register.
12421 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12423 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12424 DAG.getBitcast(MVT::v2f64, Load),
12425 DAG.getIntPtrConstant(0, dl));
12427 // Or the load with the bias.
12428 SDValue Or = DAG.getNode(
12429 ISD::OR, dl, MVT::v2i64,
12430 DAG.getBitcast(MVT::v2i64,
12431 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12432 DAG.getBitcast(MVT::v2i64,
12433 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12435 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12436 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12438 // Subtract the bias.
12439 // TODO: Are there any fast-math-flags to propagate here?
12440 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12442 // Handle final rounding.
12443 EVT DestVT = Op.getValueType();
12445 if (DestVT.bitsLT(MVT::f64))
12446 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12447 DAG.getIntPtrConstant(0, dl));
12448 if (DestVT.bitsGT(MVT::f64))
12449 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12451 // Handle final rounding.
12455 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12456 const X86Subtarget &Subtarget) {
12457 // The algorithm is the following:
12458 // #ifdef __SSE4_1__
12459 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12460 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12461 // (uint4) 0x53000000, 0xaa);
12463 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12464 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12466 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12467 // return (float4) lo + fhi;
12470 SDValue V = Op->getOperand(0);
12471 EVT VecIntVT = V.getValueType();
12472 bool Is128 = VecIntVT == MVT::v4i32;
12473 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12474 // If we convert to something else than the supported type, e.g., to v4f64,
12476 if (VecFloatVT != Op->getValueType(0))
12479 unsigned NumElts = VecIntVT.getVectorNumElements();
12480 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12481 "Unsupported custom type");
12482 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12484 // In the #idef/#else code, we have in common:
12485 // - The vector of constants:
12491 // Create the splat vector for 0x4b000000.
12492 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12493 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12494 CstLow, CstLow, CstLow, CstLow};
12495 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12496 makeArrayRef(&CstLowArray[0], NumElts));
12497 // Create the splat vector for 0x53000000.
12498 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12499 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12500 CstHigh, CstHigh, CstHigh, CstHigh};
12501 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12502 makeArrayRef(&CstHighArray[0], NumElts));
12504 // Create the right shift.
12505 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12506 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12507 CstShift, CstShift, CstShift, CstShift};
12508 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12509 makeArrayRef(&CstShiftArray[0], NumElts));
12510 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12513 if (Subtarget.hasSSE41()) {
12514 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12515 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12516 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12517 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12518 // Low will be bitcasted right away, so do not bother bitcasting back to its
12520 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12521 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12522 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12523 // (uint4) 0x53000000, 0xaa);
12524 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12525 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12526 // High will be bitcasted right away, so do not bother bitcasting back to
12527 // its original type.
12528 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12529 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12531 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12532 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12533 CstMask, CstMask, CstMask);
12534 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12535 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12536 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12538 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12539 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12542 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12543 SDValue CstFAdd = DAG.getConstantFP(
12544 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12545 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12546 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12547 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12548 makeArrayRef(&CstFAddArray[0], NumElts));
12550 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12551 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12552 // TODO: Are there any fast-math-flags to propagate here?
12554 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12555 // return (float4) lo + fhi;
12556 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12557 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12560 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12561 SelectionDAG &DAG) const {
12562 SDValue N0 = Op.getOperand(0);
12563 MVT SVT = N0.getSimpleValueType();
12566 switch (SVT.SimpleTy) {
12568 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12573 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12574 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12575 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12579 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12582 if (Subtarget->hasAVX512())
12583 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12584 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12586 llvm_unreachable(nullptr);
12589 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12590 SelectionDAG &DAG) const {
12591 SDValue N0 = Op.getOperand(0);
12593 auto PtrVT = getPointerTy(DAG.getDataLayout());
12595 if (Op.getValueType().isVector())
12596 return lowerUINT_TO_FP_vec(Op, DAG);
12598 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12599 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12600 // the optimization here.
12601 if (DAG.SignBitIsZero(N0))
12602 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12604 MVT SrcVT = N0.getSimpleValueType();
12605 MVT DstVT = Op.getSimpleValueType();
12607 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12608 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12609 // Conversions from unsigned i32 to f32/f64 are legal,
12610 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12614 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12615 return LowerUINT_TO_FP_i64(Op, DAG);
12616 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12617 return LowerUINT_TO_FP_i32(Op, DAG);
12618 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12621 // Make a 64-bit buffer, and use it to build an FILD.
12622 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12623 if (SrcVT == MVT::i32) {
12624 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12625 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12626 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12627 StackSlot, MachinePointerInfo(),
12629 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12630 OffsetSlot, MachinePointerInfo(),
12632 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12636 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12637 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12638 StackSlot, MachinePointerInfo(),
12640 // For i64 source, we need to add the appropriate power of 2 if the input
12641 // was negative. This is the same as the optimization in
12642 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12643 // we must be careful to do the computation in x87 extended precision, not
12644 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12645 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12646 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12647 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12648 MachineMemOperand::MOLoad, 8, 8);
12650 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12651 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12652 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12655 APInt FF(32, 0x5F800000ULL);
12657 // Check whether the sign bit is set.
12658 SDValue SignSet = DAG.getSetCC(
12659 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12660 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12662 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12663 SDValue FudgePtr = DAG.getConstantPool(
12664 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12666 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12667 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12668 SDValue Four = DAG.getIntPtrConstant(4, dl);
12669 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12671 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12673 // Load the value out, extending it from f32 to f80.
12674 // FIXME: Avoid the extend by constructing the right constant pool?
12675 SDValue Fudge = DAG.getExtLoad(
12676 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12677 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12678 false, false, false, 4);
12679 // Extend everything to 80 bits to force it to be done on x87.
12680 // TODO: Are there any fast-math-flags to propagate here?
12681 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12682 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12683 DAG.getIntPtrConstant(0, dl));
12686 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12687 // is legal, or has an f16 source (which needs to be promoted to f32),
12688 // just return an <SDValue(), SDValue()> pair.
12689 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12690 // to i16, i32 or i64, and we lower it to a legal sequence.
12691 // If lowered to the final integer result we return a <result, SDValue()> pair.
12692 // Otherwise we lower it to a sequence ending with a FIST, return a
12693 // <FIST, StackSlot> pair, and the caller is responsible for loading
12694 // the final integer result from StackSlot.
12695 std::pair<SDValue,SDValue>
12696 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12697 bool IsSigned, bool IsReplace) const {
12700 EVT DstTy = Op.getValueType();
12701 EVT TheVT = Op.getOperand(0).getValueType();
12702 auto PtrVT = getPointerTy(DAG.getDataLayout());
12704 if (TheVT == MVT::f16)
12705 // We need to promote the f16 to f32 before using the lowering
12706 // in this routine.
12707 return std::make_pair(SDValue(), SDValue());
12709 assert((TheVT == MVT::f32 ||
12710 TheVT == MVT::f64 ||
12711 TheVT == MVT::f80) &&
12712 "Unexpected FP operand type in FP_TO_INTHelper");
12714 // If using FIST to compute an unsigned i64, we'll need some fixup
12715 // to handle values above the maximum signed i64. A FIST is always
12716 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12717 bool UnsignedFixup = !IsSigned &&
12718 DstTy == MVT::i64 &&
12719 (!Subtarget->is64Bit() ||
12720 !isScalarFPTypeInSSEReg(TheVT));
12722 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12723 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12724 // The low 32 bits of the fist result will have the correct uint32 result.
12725 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12729 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12730 DstTy.getSimpleVT() >= MVT::i16 &&
12731 "Unknown FP_TO_INT to lower!");
12733 // These are really Legal.
12734 if (DstTy == MVT::i32 &&
12735 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12736 return std::make_pair(SDValue(), SDValue());
12737 if (Subtarget->is64Bit() &&
12738 DstTy == MVT::i64 &&
12739 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12740 return std::make_pair(SDValue(), SDValue());
12742 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12744 MachineFunction &MF = DAG.getMachineFunction();
12745 unsigned MemSize = DstTy.getSizeInBits()/8;
12746 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12747 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12750 switch (DstTy.getSimpleVT().SimpleTy) {
12751 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12752 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12753 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12754 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12757 SDValue Chain = DAG.getEntryNode();
12758 SDValue Value = Op.getOperand(0);
12759 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12761 if (UnsignedFixup) {
12763 // Conversion to unsigned i64 is implemented with a select,
12764 // depending on whether the source value fits in the range
12765 // of a signed i64. Let Thresh be the FP equivalent of
12766 // 0x8000000000000000ULL.
12768 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12769 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12770 // Fist-to-mem64 FistSrc
12771 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12772 // to XOR'ing the high 32 bits with Adjust.
12774 // Being a power of 2, Thresh is exactly representable in all FP formats.
12775 // For X87 we'd like to use the smallest FP type for this constant, but
12776 // for DAG type consistency we have to match the FP operand type.
12778 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12779 APFloat::opStatus Status = APFloat::opOK;
12780 bool LosesInfo = false;
12781 if (TheVT == MVT::f64)
12782 // The rounding mode is irrelevant as the conversion should be exact.
12783 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12785 else if (TheVT == MVT::f80)
12786 Status = Thresh.convert(APFloat::x87DoubleExtended,
12787 APFloat::rmNearestTiesToEven, &LosesInfo);
12789 assert(Status == APFloat::opOK && !LosesInfo &&
12790 "FP conversion should have been exact");
12792 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12794 SDValue Cmp = DAG.getSetCC(DL,
12795 getSetCCResultType(DAG.getDataLayout(),
12796 *DAG.getContext(), TheVT),
12797 Value, ThreshVal, ISD::SETLT);
12798 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12799 DAG.getConstant(0, DL, MVT::i32),
12800 DAG.getConstant(0x80000000, DL, MVT::i32));
12801 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12802 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12803 *DAG.getContext(), TheVT),
12804 Value, ThreshVal, ISD::SETLT);
12805 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12808 // FIXME This causes a redundant load/store if the SSE-class value is already
12809 // in memory, such as if it is on the callstack.
12810 if (isScalarFPTypeInSSEReg(TheVT)) {
12811 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12812 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12813 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12815 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12817 Chain, StackSlot, DAG.getValueType(TheVT)
12820 MachineMemOperand *MMO =
12821 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12822 MachineMemOperand::MOLoad, MemSize, MemSize);
12823 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12824 Chain = Value.getValue(1);
12825 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12826 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12829 MachineMemOperand *MMO =
12830 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12831 MachineMemOperand::MOStore, MemSize, MemSize);
12833 if (UnsignedFixup) {
12835 // Insert the FIST, load its result as two i32's,
12836 // and XOR the high i32 with Adjust.
12838 SDValue FistOps[] = { Chain, Value, StackSlot };
12839 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12840 FistOps, DstTy, MMO);
12842 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12843 MachinePointerInfo(),
12844 false, false, false, 0);
12845 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12846 DAG.getConstant(4, DL, PtrVT));
12848 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12849 MachinePointerInfo(),
12850 false, false, false, 0);
12851 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12853 if (Subtarget->is64Bit()) {
12854 // Join High32 and Low32 into a 64-bit result.
12855 // (High32 << 32) | Low32
12856 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12857 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12858 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12859 DAG.getConstant(32, DL, MVT::i8));
12860 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12861 return std::make_pair(Result, SDValue());
12864 SDValue ResultOps[] = { Low32, High32 };
12866 SDValue pair = IsReplace
12867 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12868 : DAG.getMergeValues(ResultOps, DL);
12869 return std::make_pair(pair, SDValue());
12871 // Build the FP_TO_INT*_IN_MEM
12872 SDValue Ops[] = { Chain, Value, StackSlot };
12873 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12875 return std::make_pair(FIST, StackSlot);
12879 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12880 const X86Subtarget *Subtarget) {
12881 MVT VT = Op->getSimpleValueType(0);
12882 SDValue In = Op->getOperand(0);
12883 MVT InVT = In.getSimpleValueType();
12886 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12887 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12889 // Optimize vectors in AVX mode:
12892 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12893 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12894 // Concat upper and lower parts.
12897 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12898 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12899 // Concat upper and lower parts.
12902 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12903 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12904 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12907 if (Subtarget->hasInt256())
12908 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12910 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12911 SDValue Undef = DAG.getUNDEF(InVT);
12912 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12913 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12914 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12916 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12917 VT.getVectorNumElements()/2);
12919 OpLo = DAG.getBitcast(HVT, OpLo);
12920 OpHi = DAG.getBitcast(HVT, OpHi);
12922 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12925 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12926 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12927 MVT VT = Op->getSimpleValueType(0);
12928 SDValue In = Op->getOperand(0);
12929 MVT InVT = In.getSimpleValueType();
12931 unsigned int NumElts = VT.getVectorNumElements();
12932 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12935 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12936 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12938 assert(InVT.getVectorElementType() == MVT::i1);
12939 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12941 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12943 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12945 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12946 if (VT.is512BitVector())
12948 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12951 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12952 SelectionDAG &DAG) {
12953 if (Subtarget->hasFp256())
12954 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12960 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12961 SelectionDAG &DAG) {
12963 MVT VT = Op.getSimpleValueType();
12964 SDValue In = Op.getOperand(0);
12965 MVT SVT = In.getSimpleValueType();
12967 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12968 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12970 if (Subtarget->hasFp256())
12971 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12974 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12975 VT.getVectorNumElements() != SVT.getVectorNumElements());
12979 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12981 MVT VT = Op.getSimpleValueType();
12982 SDValue In = Op.getOperand(0);
12983 MVT InVT = In.getSimpleValueType();
12985 if (VT == MVT::i1) {
12986 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12987 "Invalid scalar TRUNCATE operation");
12988 if (InVT.getSizeInBits() >= 32)
12990 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12991 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12993 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12994 "Invalid TRUNCATE operation");
12996 // move vector to mask - truncate solution for SKX
12997 if (VT.getVectorElementType() == MVT::i1) {
12998 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12999 Subtarget->hasBWI())
13000 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13001 if ((InVT.is256BitVector() || InVT.is128BitVector())
13002 && InVT.getScalarSizeInBits() <= 16 &&
13003 Subtarget->hasBWI() && Subtarget->hasVLX())
13004 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13005 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13006 Subtarget->hasDQI())
13007 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13008 if ((InVT.is256BitVector() || InVT.is128BitVector())
13009 && InVT.getScalarSizeInBits() >= 32 &&
13010 Subtarget->hasDQI() && Subtarget->hasVLX())
13011 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13014 if (VT.getVectorElementType() == MVT::i1) {
13015 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13016 unsigned NumElts = InVT.getVectorNumElements();
13017 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13018 if (InVT.getSizeInBits() < 512) {
13019 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13020 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13025 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13026 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13027 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13030 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13031 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13032 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13033 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13035 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13036 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13037 if (Subtarget->hasInt256()) {
13038 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13039 In = DAG.getBitcast(MVT::v8i32, In);
13040 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13042 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13043 DAG.getIntPtrConstant(0, DL));
13046 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13047 DAG.getIntPtrConstant(0, DL));
13048 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13049 DAG.getIntPtrConstant(2, DL));
13050 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13051 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13052 static const int ShufMask[] = {0, 2, 4, 6};
13053 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13056 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13057 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13058 if (Subtarget->hasInt256()) {
13059 In = DAG.getBitcast(MVT::v32i8, In);
13061 SmallVector<SDValue,32> pshufbMask;
13062 for (unsigned i = 0; i < 2; ++i) {
13063 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13064 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13065 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13066 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13067 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13068 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13069 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13070 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13071 for (unsigned j = 0; j < 8; ++j)
13072 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13074 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13075 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13076 In = DAG.getBitcast(MVT::v4i64, In);
13078 static const int ShufMask[] = {0, 2, -1, -1};
13079 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13081 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13082 DAG.getIntPtrConstant(0, DL));
13083 return DAG.getBitcast(VT, In);
13086 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13087 DAG.getIntPtrConstant(0, DL));
13089 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13090 DAG.getIntPtrConstant(4, DL));
13092 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13093 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13095 // The PSHUFB mask:
13096 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13097 -1, -1, -1, -1, -1, -1, -1, -1};
13099 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13100 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13101 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13103 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13104 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13106 // The MOVLHPS Mask:
13107 static const int ShufMask2[] = {0, 1, 4, 5};
13108 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13109 return DAG.getBitcast(MVT::v8i16, res);
13112 // Handle truncation of V256 to V128 using shuffles.
13113 if (!VT.is128BitVector() || !InVT.is256BitVector())
13116 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13118 unsigned NumElems = VT.getVectorNumElements();
13119 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13121 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13122 // Prepare truncation shuffle mask
13123 for (unsigned i = 0; i != NumElems; ++i)
13124 MaskVec[i] = i * 2;
13125 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13126 DAG.getUNDEF(NVT), &MaskVec[0]);
13127 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13128 DAG.getIntPtrConstant(0, DL));
13131 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13132 SelectionDAG &DAG) const {
13133 assert(!Op.getSimpleValueType().isVector());
13135 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13136 /*IsSigned=*/ true, /*IsReplace=*/ false);
13137 SDValue FIST = Vals.first, StackSlot = Vals.second;
13138 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13139 if (!FIST.getNode())
13142 if (StackSlot.getNode())
13143 // Load the result.
13144 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13145 FIST, StackSlot, MachinePointerInfo(),
13146 false, false, false, 0);
13148 // The node is the result.
13152 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13153 SelectionDAG &DAG) const {
13154 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13155 /*IsSigned=*/ false, /*IsReplace=*/ false);
13156 SDValue FIST = Vals.first, StackSlot = Vals.second;
13157 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13158 if (!FIST.getNode())
13161 if (StackSlot.getNode())
13162 // Load the result.
13163 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13164 FIST, StackSlot, MachinePointerInfo(),
13165 false, false, false, 0);
13167 // The node is the result.
13171 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13173 MVT VT = Op.getSimpleValueType();
13174 SDValue In = Op.getOperand(0);
13175 MVT SVT = In.getSimpleValueType();
13177 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13179 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13180 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13181 In, DAG.getUNDEF(SVT)));
13184 /// The only differences between FABS and FNEG are the mask and the logic op.
13185 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13186 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13187 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13188 "Wrong opcode for lowering FABS or FNEG.");
13190 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13192 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13193 // into an FNABS. We'll lower the FABS after that if it is still in use.
13195 for (SDNode *User : Op->uses())
13196 if (User->getOpcode() == ISD::FNEG)
13200 MVT VT = Op.getSimpleValueType();
13202 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13203 // decide if we should generate a 16-byte constant mask when we only need 4 or
13204 // 8 bytes for the scalar case.
13210 if (VT.isVector()) {
13212 EltVT = VT.getVectorElementType();
13213 NumElts = VT.getVectorNumElements();
13215 // There are no scalar bitwise logical SSE/AVX instructions, so we
13216 // generate a 16-byte vector constant and logic op even for the scalar case.
13217 // Using a 16-byte mask allows folding the load of the mask with
13218 // the logic op, so it can save (~4 bytes) on code size.
13219 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13221 NumElts = (VT == MVT::f64) ? 2 : 4;
13224 unsigned EltBits = EltVT.getSizeInBits();
13225 LLVMContext *Context = DAG.getContext();
13226 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13228 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13229 Constant *C = ConstantInt::get(*Context, MaskElt);
13230 C = ConstantVector::getSplat(NumElts, C);
13231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13232 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13233 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13235 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13236 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13237 false, false, false, Alignment);
13239 SDValue Op0 = Op.getOperand(0);
13240 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13242 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13243 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13246 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13248 // For the scalar case extend to a 128-bit vector, perform the logic op,
13249 // and extract the scalar result back out.
13250 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13251 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13252 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13253 DAG.getIntPtrConstant(0, dl));
13256 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13258 LLVMContext *Context = DAG.getContext();
13259 SDValue Op0 = Op.getOperand(0);
13260 SDValue Op1 = Op.getOperand(1);
13262 MVT VT = Op.getSimpleValueType();
13263 MVT SrcVT = Op1.getSimpleValueType();
13265 // If second operand is smaller, extend it first.
13266 if (SrcVT.bitsLT(VT)) {
13267 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13270 // And if it is bigger, shrink it first.
13271 if (SrcVT.bitsGT(VT)) {
13272 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13276 // At this point the operands and the result should have the same
13277 // type, and that won't be f80 since that is not custom lowered.
13279 const fltSemantics &Sem =
13280 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13281 const unsigned SizeInBits = VT.getSizeInBits();
13283 SmallVector<Constant *, 4> CV(
13284 VT == MVT::f64 ? 2 : 4,
13285 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13287 // First, clear all bits but the sign bit from the second operand (sign).
13288 CV[0] = ConstantFP::get(*Context,
13289 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13290 Constant *C = ConstantVector::get(CV);
13291 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13292 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13294 // Perform all logic operations as 16-byte vectors because there are no
13295 // scalar FP logic instructions in SSE. This allows load folding of the
13296 // constants into the logic instructions.
13297 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13299 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13300 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13301 false, false, false, 16);
13302 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13303 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13305 // Next, clear the sign bit from the first operand (magnitude).
13306 // If it's a constant, we can clear it here.
13307 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13308 APFloat APF = Op0CN->getValueAPF();
13309 // If the magnitude is a positive zero, the sign bit alone is enough.
13310 if (APF.isPosZero())
13311 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13312 DAG.getIntPtrConstant(0, dl));
13314 CV[0] = ConstantFP::get(*Context, APF);
13316 CV[0] = ConstantFP::get(
13318 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13320 C = ConstantVector::get(CV);
13321 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13323 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13324 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13325 false, false, false, 16);
13326 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13327 if (!isa<ConstantFPSDNode>(Op0)) {
13328 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13329 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13331 // OR the magnitude value with the sign bit.
13332 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13333 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13334 DAG.getIntPtrConstant(0, dl));
13337 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13338 SDValue N0 = Op.getOperand(0);
13340 MVT VT = Op.getSimpleValueType();
13342 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13343 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13344 DAG.getConstant(1, dl, VT));
13345 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13348 // Check whether an OR'd tree is PTEST-able.
13349 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13350 SelectionDAG &DAG) {
13351 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13353 if (!Subtarget->hasSSE41())
13356 if (!Op->hasOneUse())
13359 SDNode *N = Op.getNode();
13362 SmallVector<SDValue, 8> Opnds;
13363 DenseMap<SDValue, unsigned> VecInMap;
13364 SmallVector<SDValue, 8> VecIns;
13365 EVT VT = MVT::Other;
13367 // Recognize a special case where a vector is casted into wide integer to
13369 Opnds.push_back(N->getOperand(0));
13370 Opnds.push_back(N->getOperand(1));
13372 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13373 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13374 // BFS traverse all OR'd operands.
13375 if (I->getOpcode() == ISD::OR) {
13376 Opnds.push_back(I->getOperand(0));
13377 Opnds.push_back(I->getOperand(1));
13378 // Re-evaluate the number of nodes to be traversed.
13379 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13383 // Quit if a non-EXTRACT_VECTOR_ELT
13384 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13387 // Quit if without a constant index.
13388 SDValue Idx = I->getOperand(1);
13389 if (!isa<ConstantSDNode>(Idx))
13392 SDValue ExtractedFromVec = I->getOperand(0);
13393 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13394 if (M == VecInMap.end()) {
13395 VT = ExtractedFromVec.getValueType();
13396 // Quit if not 128/256-bit vector.
13397 if (!VT.is128BitVector() && !VT.is256BitVector())
13399 // Quit if not the same type.
13400 if (VecInMap.begin() != VecInMap.end() &&
13401 VT != VecInMap.begin()->first.getValueType())
13403 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13404 VecIns.push_back(ExtractedFromVec);
13406 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13409 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13410 "Not extracted from 128-/256-bit vector.");
13412 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13414 for (DenseMap<SDValue, unsigned>::const_iterator
13415 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13416 // Quit if not all elements are used.
13417 if (I->second != FullMask)
13421 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13423 // Cast all vectors into TestVT for PTEST.
13424 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13425 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13427 // If more than one full vectors are evaluated, OR them first before PTEST.
13428 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13429 // Each iteration will OR 2 nodes and append the result until there is only
13430 // 1 node left, i.e. the final OR'd value of all vectors.
13431 SDValue LHS = VecIns[Slot];
13432 SDValue RHS = VecIns[Slot + 1];
13433 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13436 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13437 VecIns.back(), VecIns.back());
13440 /// \brief return true if \c Op has a use that doesn't just read flags.
13441 static bool hasNonFlagsUse(SDValue Op) {
13442 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13444 SDNode *User = *UI;
13445 unsigned UOpNo = UI.getOperandNo();
13446 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13447 // Look pass truncate.
13448 UOpNo = User->use_begin().getOperandNo();
13449 User = *User->use_begin();
13452 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13453 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13459 /// Emit nodes that will be selected as "test Op0,Op0", or something
13461 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13462 SelectionDAG &DAG) const {
13463 if (Op.getValueType() == MVT::i1) {
13464 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13465 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13466 DAG.getConstant(0, dl, MVT::i8));
13468 // CF and OF aren't always set the way we want. Determine which
13469 // of these we need.
13470 bool NeedCF = false;
13471 bool NeedOF = false;
13474 case X86::COND_A: case X86::COND_AE:
13475 case X86::COND_B: case X86::COND_BE:
13478 case X86::COND_G: case X86::COND_GE:
13479 case X86::COND_L: case X86::COND_LE:
13480 case X86::COND_O: case X86::COND_NO: {
13481 // Check if we really need to set the
13482 // Overflow flag. If NoSignedWrap is present
13483 // that is not actually needed.
13484 switch (Op->getOpcode()) {
13489 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13490 if (BinNode->Flags.hasNoSignedWrap())
13500 // See if we can use the EFLAGS value from the operand instead of
13501 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13502 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13503 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13504 // Emit a CMP with 0, which is the TEST pattern.
13505 //if (Op.getValueType() == MVT::i1)
13506 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13507 // DAG.getConstant(0, MVT::i1));
13508 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13509 DAG.getConstant(0, dl, Op.getValueType()));
13511 unsigned Opcode = 0;
13512 unsigned NumOperands = 0;
13514 // Truncate operations may prevent the merge of the SETCC instruction
13515 // and the arithmetic instruction before it. Attempt to truncate the operands
13516 // of the arithmetic instruction and use a reduced bit-width instruction.
13517 bool NeedTruncation = false;
13518 SDValue ArithOp = Op;
13519 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13520 SDValue Arith = Op->getOperand(0);
13521 // Both the trunc and the arithmetic op need to have one user each.
13522 if (Arith->hasOneUse())
13523 switch (Arith.getOpcode()) {
13530 NeedTruncation = true;
13536 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13537 // which may be the result of a CAST. We use the variable 'Op', which is the
13538 // non-casted variable when we check for possible users.
13539 switch (ArithOp.getOpcode()) {
13541 // Due to an isel shortcoming, be conservative if this add is likely to be
13542 // selected as part of a load-modify-store instruction. When the root node
13543 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13544 // uses of other nodes in the match, such as the ADD in this case. This
13545 // leads to the ADD being left around and reselected, with the result being
13546 // two adds in the output. Alas, even if none our users are stores, that
13547 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13548 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13549 // climbing the DAG back to the root, and it doesn't seem to be worth the
13551 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13552 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13553 if (UI->getOpcode() != ISD::CopyToReg &&
13554 UI->getOpcode() != ISD::SETCC &&
13555 UI->getOpcode() != ISD::STORE)
13558 if (ConstantSDNode *C =
13559 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13560 // An add of one will be selected as an INC.
13561 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13562 Opcode = X86ISD::INC;
13567 // An add of negative one (subtract of one) will be selected as a DEC.
13568 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13569 Opcode = X86ISD::DEC;
13575 // Otherwise use a regular EFLAGS-setting add.
13576 Opcode = X86ISD::ADD;
13581 // If we have a constant logical shift that's only used in a comparison
13582 // against zero turn it into an equivalent AND. This allows turning it into
13583 // a TEST instruction later.
13584 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13585 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13586 EVT VT = Op.getValueType();
13587 unsigned BitWidth = VT.getSizeInBits();
13588 unsigned ShAmt = Op->getConstantOperandVal(1);
13589 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13591 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13592 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13593 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13594 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13596 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13597 DAG.getConstant(Mask, dl, VT));
13598 DAG.ReplaceAllUsesWith(Op, New);
13604 // If the primary and result isn't used, don't bother using X86ISD::AND,
13605 // because a TEST instruction will be better.
13606 if (!hasNonFlagsUse(Op))
13612 // Due to the ISEL shortcoming noted above, be conservative if this op is
13613 // likely to be selected as part of a load-modify-store instruction.
13614 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13615 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13616 if (UI->getOpcode() == ISD::STORE)
13619 // Otherwise use a regular EFLAGS-setting instruction.
13620 switch (ArithOp.getOpcode()) {
13621 default: llvm_unreachable("unexpected operator!");
13622 case ISD::SUB: Opcode = X86ISD::SUB; break;
13623 case ISD::XOR: Opcode = X86ISD::XOR; break;
13624 case ISD::AND: Opcode = X86ISD::AND; break;
13626 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13627 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13628 if (EFLAGS.getNode())
13631 Opcode = X86ISD::OR;
13645 return SDValue(Op.getNode(), 1);
13651 // If we found that truncation is beneficial, perform the truncation and
13653 if (NeedTruncation) {
13654 EVT VT = Op.getValueType();
13655 SDValue WideVal = Op->getOperand(0);
13656 EVT WideVT = WideVal.getValueType();
13657 unsigned ConvertedOp = 0;
13658 // Use a target machine opcode to prevent further DAGCombine
13659 // optimizations that may separate the arithmetic operations
13660 // from the setcc node.
13661 switch (WideVal.getOpcode()) {
13663 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13664 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13665 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13666 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13667 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13671 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13672 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13673 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13674 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13675 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13681 // Emit a CMP with 0, which is the TEST pattern.
13682 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13683 DAG.getConstant(0, dl, Op.getValueType()));
13685 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13686 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13688 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13689 DAG.ReplaceAllUsesWith(Op, New);
13690 return SDValue(New.getNode(), 1);
13693 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13695 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13696 SDLoc dl, SelectionDAG &DAG) const {
13697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13698 if (C->getAPIntValue() == 0)
13699 return EmitTest(Op0, X86CC, dl, DAG);
13701 if (Op0.getValueType() == MVT::i1)
13702 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13705 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13706 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13707 // Do the comparison at i32 if it's smaller, besides the Atom case.
13708 // This avoids subregister aliasing issues. Keep the smaller reference
13709 // if we're optimizing for size, however, as that'll allow better folding
13710 // of memory operations.
13711 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13712 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13713 !Subtarget->isAtom()) {
13714 unsigned ExtendOp =
13715 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13716 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13717 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13719 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13720 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13721 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13723 return SDValue(Sub.getNode(), 1);
13725 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13728 /// Convert a comparison if required by the subtarget.
13729 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13730 SelectionDAG &DAG) const {
13731 // If the subtarget does not support the FUCOMI instruction, floating-point
13732 // comparisons have to be converted.
13733 if (Subtarget->hasCMov() ||
13734 Cmp.getOpcode() != X86ISD::CMP ||
13735 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13736 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13739 // The instruction selector will select an FUCOM instruction instead of
13740 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13741 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13742 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13744 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13745 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13746 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13747 DAG.getConstant(8, dl, MVT::i8));
13748 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13749 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13752 /// The minimum architected relative accuracy is 2^-12. We need one
13753 /// Newton-Raphson step to have a good float result (24 bits of precision).
13754 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13755 DAGCombinerInfo &DCI,
13756 unsigned &RefinementSteps,
13757 bool &UseOneConstNR) const {
13758 EVT VT = Op.getValueType();
13759 const char *RecipOp;
13761 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13762 // TODO: Add support for AVX512 (v16f32).
13763 // It is likely not profitable to do this for f64 because a double-precision
13764 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13765 // instructions: convert to single, rsqrtss, convert back to double, refine
13766 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13767 // along with FMA, this could be a throughput win.
13768 if (VT == MVT::f32 && Subtarget->hasSSE1())
13770 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13771 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13772 RecipOp = "vec-sqrtf";
13776 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13777 if (!Recips.isEnabled(RecipOp))
13780 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13781 UseOneConstNR = false;
13782 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13785 /// The minimum architected relative accuracy is 2^-12. We need one
13786 /// Newton-Raphson step to have a good float result (24 bits of precision).
13787 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13788 DAGCombinerInfo &DCI,
13789 unsigned &RefinementSteps) const {
13790 EVT VT = Op.getValueType();
13791 const char *RecipOp;
13793 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13794 // TODO: Add support for AVX512 (v16f32).
13795 // It is likely not profitable to do this for f64 because a double-precision
13796 // reciprocal estimate with refinement on x86 prior to FMA requires
13797 // 15 instructions: convert to single, rcpss, convert back to double, refine
13798 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13799 // along with FMA, this could be a throughput win.
13800 if (VT == MVT::f32 && Subtarget->hasSSE1())
13802 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13803 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13804 RecipOp = "vec-divf";
13808 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13809 if (!Recips.isEnabled(RecipOp))
13812 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13813 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13816 /// If we have at least two divisions that use the same divisor, convert to
13817 /// multplication by a reciprocal. This may need to be adjusted for a given
13818 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13819 /// This is because we still need one division to calculate the reciprocal and
13820 /// then we need two multiplies by that reciprocal as replacements for the
13821 /// original divisions.
13822 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13826 static bool isAllOnes(SDValue V) {
13827 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13828 return C && C->isAllOnesValue();
13831 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13832 /// if it's possible.
13833 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13834 SDLoc dl, SelectionDAG &DAG) const {
13835 SDValue Op0 = And.getOperand(0);
13836 SDValue Op1 = And.getOperand(1);
13837 if (Op0.getOpcode() == ISD::TRUNCATE)
13838 Op0 = Op0.getOperand(0);
13839 if (Op1.getOpcode() == ISD::TRUNCATE)
13840 Op1 = Op1.getOperand(0);
13843 if (Op1.getOpcode() == ISD::SHL)
13844 std::swap(Op0, Op1);
13845 if (Op0.getOpcode() == ISD::SHL) {
13846 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13847 if (And00C->getZExtValue() == 1) {
13848 // If we looked past a truncate, check that it's only truncating away
13850 unsigned BitWidth = Op0.getValueSizeInBits();
13851 unsigned AndBitWidth = And.getValueSizeInBits();
13852 if (BitWidth > AndBitWidth) {
13854 DAG.computeKnownBits(Op0, Zeros, Ones);
13855 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13859 RHS = Op0.getOperand(1);
13861 } else if (Op1.getOpcode() == ISD::Constant) {
13862 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13863 uint64_t AndRHSVal = AndRHS->getZExtValue();
13864 SDValue AndLHS = Op0;
13866 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13867 LHS = AndLHS.getOperand(0);
13868 RHS = AndLHS.getOperand(1);
13871 // Use BT if the immediate can't be encoded in a TEST instruction.
13872 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13874 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13878 if (LHS.getNode()) {
13879 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13880 // instruction. Since the shift amount is in-range-or-undefined, we know
13881 // that doing a bittest on the i32 value is ok. We extend to i32 because
13882 // the encoding for the i16 version is larger than the i32 version.
13883 // Also promote i16 to i32 for performance / code size reason.
13884 if (LHS.getValueType() == MVT::i8 ||
13885 LHS.getValueType() == MVT::i16)
13886 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13888 // If the operand types disagree, extend the shift amount to match. Since
13889 // BT ignores high bits (like shifts) we can use anyextend.
13890 if (LHS.getValueType() != RHS.getValueType())
13891 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13893 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13894 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13895 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13896 DAG.getConstant(Cond, dl, MVT::i8), BT);
13902 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13904 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13909 // SSE Condition code mapping:
13918 switch (SetCCOpcode) {
13919 default: llvm_unreachable("Unexpected SETCC condition");
13921 case ISD::SETEQ: SSECC = 0; break;
13923 case ISD::SETGT: Swap = true; // Fallthrough
13925 case ISD::SETOLT: SSECC = 1; break;
13927 case ISD::SETGE: Swap = true; // Fallthrough
13929 case ISD::SETOLE: SSECC = 2; break;
13930 case ISD::SETUO: SSECC = 3; break;
13932 case ISD::SETNE: SSECC = 4; break;
13933 case ISD::SETULE: Swap = true; // Fallthrough
13934 case ISD::SETUGE: SSECC = 5; break;
13935 case ISD::SETULT: Swap = true; // Fallthrough
13936 case ISD::SETUGT: SSECC = 6; break;
13937 case ISD::SETO: SSECC = 7; break;
13939 case ISD::SETONE: SSECC = 8; break;
13942 std::swap(Op0, Op1);
13947 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13948 // ones, and then concatenate the result back.
13949 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13950 MVT VT = Op.getSimpleValueType();
13952 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13953 "Unsupported value type for operation");
13955 unsigned NumElems = VT.getVectorNumElements();
13957 SDValue CC = Op.getOperand(2);
13959 // Extract the LHS vectors
13960 SDValue LHS = Op.getOperand(0);
13961 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13962 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13964 // Extract the RHS vectors
13965 SDValue RHS = Op.getOperand(1);
13966 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13967 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13969 // Issue the operation on the smaller types and concatenate the result back
13970 MVT EltVT = VT.getVectorElementType();
13971 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13972 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13973 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13974 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13977 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13978 SDValue Op0 = Op.getOperand(0);
13979 SDValue Op1 = Op.getOperand(1);
13980 SDValue CC = Op.getOperand(2);
13981 MVT VT = Op.getSimpleValueType();
13984 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13985 "Unexpected type for boolean compare operation");
13986 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13987 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13988 DAG.getConstant(-1, dl, VT));
13989 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13990 DAG.getConstant(-1, dl, VT));
13991 switch (SetCCOpcode) {
13992 default: llvm_unreachable("Unexpected SETCC condition");
13994 // (x == y) -> ~(x ^ y)
13995 return DAG.getNode(ISD::XOR, dl, VT,
13996 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13997 DAG.getConstant(-1, dl, VT));
13999 // (x != y) -> (x ^ y)
14000 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14003 // (x > y) -> (x & ~y)
14004 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14007 // (x < y) -> (~x & y)
14008 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14011 // (x <= y) -> (~x | y)
14012 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14015 // (x >=y) -> (x | ~y)
14016 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14020 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14021 const X86Subtarget *Subtarget) {
14022 SDValue Op0 = Op.getOperand(0);
14023 SDValue Op1 = Op.getOperand(1);
14024 SDValue CC = Op.getOperand(2);
14025 MVT VT = Op.getSimpleValueType();
14028 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14029 Op.getValueType().getScalarType() == MVT::i1 &&
14030 "Cannot set masked compare for this operation");
14032 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14034 bool Unsigned = false;
14037 switch (SetCCOpcode) {
14038 default: llvm_unreachable("Unexpected SETCC condition");
14039 case ISD::SETNE: SSECC = 4; break;
14040 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14041 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14042 case ISD::SETLT: Swap = true; //fall-through
14043 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14044 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14045 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14046 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14047 case ISD::SETULE: Unsigned = true; //fall-through
14048 case ISD::SETLE: SSECC = 2; break;
14052 std::swap(Op0, Op1);
14054 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14055 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14056 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14057 DAG.getConstant(SSECC, dl, MVT::i8));
14060 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14061 /// operand \p Op1. If non-trivial (for example because it's not constant)
14062 /// return an empty value.
14063 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14065 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14069 MVT VT = Op1.getSimpleValueType();
14070 MVT EVT = VT.getVectorElementType();
14071 unsigned n = VT.getVectorNumElements();
14072 SmallVector<SDValue, 8> ULTOp1;
14074 for (unsigned i = 0; i < n; ++i) {
14075 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14076 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14079 // Avoid underflow.
14080 APInt Val = Elt->getAPIntValue();
14084 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14087 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14090 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14091 SelectionDAG &DAG) {
14092 SDValue Op0 = Op.getOperand(0);
14093 SDValue Op1 = Op.getOperand(1);
14094 SDValue CC = Op.getOperand(2);
14095 MVT VT = Op.getSimpleValueType();
14096 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14097 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14102 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14103 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14106 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14107 unsigned Opc = X86ISD::CMPP;
14108 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14109 assert(VT.getVectorNumElements() <= 16);
14110 Opc = X86ISD::CMPM;
14112 // In the two special cases we can't handle, emit two comparisons.
14115 unsigned CombineOpc;
14116 if (SetCCOpcode == ISD::SETUEQ) {
14117 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14119 assert(SetCCOpcode == ISD::SETONE);
14120 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14123 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14124 DAG.getConstant(CC0, dl, MVT::i8));
14125 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14126 DAG.getConstant(CC1, dl, MVT::i8));
14127 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14129 // Handle all other FP comparisons here.
14130 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14131 DAG.getConstant(SSECC, dl, MVT::i8));
14134 // Break 256-bit integer vector compare into smaller ones.
14135 if (VT.is256BitVector() && !Subtarget->hasInt256())
14136 return Lower256IntVSETCC(Op, DAG);
14138 EVT OpVT = Op1.getValueType();
14139 if (OpVT.getVectorElementType() == MVT::i1)
14140 return LowerBoolVSETCC_AVX512(Op, DAG);
14142 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14143 if (Subtarget->hasAVX512()) {
14144 if (Op1.getValueType().is512BitVector() ||
14145 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14146 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14147 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14149 // In AVX-512 architecture setcc returns mask with i1 elements,
14150 // But there is no compare instruction for i8 and i16 elements in KNL.
14151 // We are not talking about 512-bit operands in this case, these
14152 // types are illegal.
14154 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14155 OpVT.getVectorElementType().getSizeInBits() >= 8))
14156 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14157 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14160 // We are handling one of the integer comparisons here. Since SSE only has
14161 // GT and EQ comparisons for integer, swapping operands and multiple
14162 // operations may be required for some comparisons.
14164 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14165 bool Subus = false;
14167 switch (SetCCOpcode) {
14168 default: llvm_unreachable("Unexpected SETCC condition");
14169 case ISD::SETNE: Invert = true;
14170 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14171 case ISD::SETLT: Swap = true;
14172 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14173 case ISD::SETGE: Swap = true;
14174 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14175 Invert = true; break;
14176 case ISD::SETULT: Swap = true;
14177 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14178 FlipSigns = true; break;
14179 case ISD::SETUGE: Swap = true;
14180 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14181 FlipSigns = true; Invert = true; break;
14184 // Special case: Use min/max operations for SETULE/SETUGE
14185 MVT VET = VT.getVectorElementType();
14187 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14188 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14191 switch (SetCCOpcode) {
14193 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14194 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14197 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14200 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14201 if (!MinMax && hasSubus) {
14202 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14204 // t = psubus Op0, Op1
14205 // pcmpeq t, <0..0>
14206 switch (SetCCOpcode) {
14208 case ISD::SETULT: {
14209 // If the comparison is against a constant we can turn this into a
14210 // setule. With psubus, setule does not require a swap. This is
14211 // beneficial because the constant in the register is no longer
14212 // destructed as the destination so it can be hoisted out of a loop.
14213 // Only do this pre-AVX since vpcmp* is no longer destructive.
14214 if (Subtarget->hasAVX())
14216 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14217 if (ULEOp1.getNode()) {
14219 Subus = true; Invert = false; Swap = false;
14223 // Psubus is better than flip-sign because it requires no inversion.
14224 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14225 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14229 Opc = X86ISD::SUBUS;
14235 std::swap(Op0, Op1);
14237 // Check that the operation in question is available (most are plain SSE2,
14238 // but PCMPGTQ and PCMPEQQ have different requirements).
14239 if (VT == MVT::v2i64) {
14240 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14241 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14243 // First cast everything to the right type.
14244 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14245 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14247 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14248 // bits of the inputs before performing those operations. The lower
14249 // compare is always unsigned.
14252 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14254 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14255 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14256 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14257 Sign, Zero, Sign, Zero);
14259 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14260 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14262 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14263 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14264 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14266 // Create masks for only the low parts/high parts of the 64 bit integers.
14267 static const int MaskHi[] = { 1, 1, 3, 3 };
14268 static const int MaskLo[] = { 0, 0, 2, 2 };
14269 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14270 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14271 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14273 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14274 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14277 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14279 return DAG.getBitcast(VT, Result);
14282 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14283 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14284 // pcmpeqd + pshufd + pand.
14285 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14287 // First cast everything to the right type.
14288 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14289 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14292 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14294 // Make sure the lower and upper halves are both all-ones.
14295 static const int Mask[] = { 1, 0, 3, 2 };
14296 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14297 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14300 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14302 return DAG.getBitcast(VT, Result);
14306 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14307 // bits of the inputs before performing those operations.
14309 EVT EltVT = VT.getVectorElementType();
14310 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14312 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14313 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14316 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14318 // If the logical-not of the result is required, perform that now.
14320 Result = DAG.getNOT(dl, Result, VT);
14323 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14326 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14327 getZeroVector(VT, Subtarget, DAG, dl));
14332 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14334 MVT VT = Op.getSimpleValueType();
14336 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14338 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14339 && "SetCC type must be 8-bit or 1-bit integer");
14340 SDValue Op0 = Op.getOperand(0);
14341 SDValue Op1 = Op.getOperand(1);
14343 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14345 // Optimize to BT if possible.
14346 // Lower (X & (1 << N)) == 0 to BT(X, N).
14347 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14348 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14349 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14350 Op1.getOpcode() == ISD::Constant &&
14351 cast<ConstantSDNode>(Op1)->isNullValue() &&
14352 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14353 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14354 if (NewSetCC.getNode()) {
14356 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14361 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14363 if (Op1.getOpcode() == ISD::Constant &&
14364 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14365 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14366 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14368 // If the input is a setcc, then reuse the input setcc or use a new one with
14369 // the inverted condition.
14370 if (Op0.getOpcode() == X86ISD::SETCC) {
14371 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14372 bool Invert = (CC == ISD::SETNE) ^
14373 cast<ConstantSDNode>(Op1)->isNullValue();
14377 CCode = X86::GetOppositeBranchCondition(CCode);
14378 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14379 DAG.getConstant(CCode, dl, MVT::i8),
14380 Op0.getOperand(1));
14382 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14386 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14387 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14388 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14390 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14391 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14394 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14395 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14396 if (X86CC == X86::COND_INVALID)
14399 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14400 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14401 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14402 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14404 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14408 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14409 static bool isX86LogicalCmp(SDValue Op) {
14410 unsigned Opc = Op.getNode()->getOpcode();
14411 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14412 Opc == X86ISD::SAHF)
14414 if (Op.getResNo() == 1 &&
14415 (Opc == X86ISD::ADD ||
14416 Opc == X86ISD::SUB ||
14417 Opc == X86ISD::ADC ||
14418 Opc == X86ISD::SBB ||
14419 Opc == X86ISD::SMUL ||
14420 Opc == X86ISD::UMUL ||
14421 Opc == X86ISD::INC ||
14422 Opc == X86ISD::DEC ||
14423 Opc == X86ISD::OR ||
14424 Opc == X86ISD::XOR ||
14425 Opc == X86ISD::AND))
14428 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14434 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14435 if (V.getOpcode() != ISD::TRUNCATE)
14438 SDValue VOp0 = V.getOperand(0);
14439 unsigned InBits = VOp0.getValueSizeInBits();
14440 unsigned Bits = V.getValueSizeInBits();
14441 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14444 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14445 bool addTest = true;
14446 SDValue Cond = Op.getOperand(0);
14447 SDValue Op1 = Op.getOperand(1);
14448 SDValue Op2 = Op.getOperand(2);
14450 EVT VT = Op1.getValueType();
14453 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14454 // are available or VBLENDV if AVX is available.
14455 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14456 if (Cond.getOpcode() == ISD::SETCC &&
14457 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14458 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14459 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14460 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14461 int SSECC = translateX86FSETCC(
14462 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14465 if (Subtarget->hasAVX512()) {
14466 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14467 DAG.getConstant(SSECC, DL, MVT::i8));
14468 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14471 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14472 DAG.getConstant(SSECC, DL, MVT::i8));
14474 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14475 // of 3 logic instructions for size savings and potentially speed.
14476 // Unfortunately, there is no scalar form of VBLENDV.
14478 // If either operand is a constant, don't try this. We can expect to
14479 // optimize away at least one of the logic instructions later in that
14480 // case, so that sequence would be faster than a variable blend.
14482 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14483 // uses XMM0 as the selection register. That may need just as many
14484 // instructions as the AND/ANDN/OR sequence due to register moves, so
14487 if (Subtarget->hasAVX() &&
14488 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14490 // Convert to vectors, do a VSELECT, and convert back to scalar.
14491 // All of the conversions should be optimized away.
14493 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14494 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14495 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14496 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14498 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14499 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14501 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14503 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14504 VSel, DAG.getIntPtrConstant(0, DL));
14506 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14507 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14508 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14512 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14514 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14515 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14516 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14517 Op1Scalar = Op1.getOperand(0);
14519 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14520 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14521 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14522 Op2Scalar = Op2.getOperand(0);
14523 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14524 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14525 Op1Scalar.getValueType(),
14526 Cond, Op1Scalar, Op2Scalar);
14527 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14528 return DAG.getBitcast(VT, newSelect);
14529 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14530 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14531 DAG.getIntPtrConstant(0, DL));
14535 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14536 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14537 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14538 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14539 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14540 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14541 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14543 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14546 if (Cond.getOpcode() == ISD::SETCC) {
14547 SDValue NewCond = LowerSETCC(Cond, DAG);
14548 if (NewCond.getNode())
14552 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14553 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14554 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14555 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14556 if (Cond.getOpcode() == X86ISD::SETCC &&
14557 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14558 isZero(Cond.getOperand(1).getOperand(1))) {
14559 SDValue Cmp = Cond.getOperand(1);
14561 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14563 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14564 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14565 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14567 SDValue CmpOp0 = Cmp.getOperand(0);
14568 // Apply further optimizations for special cases
14569 // (select (x != 0), -1, 0) -> neg & sbb
14570 // (select (x == 0), 0, -1) -> neg & sbb
14571 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14572 if (YC->isNullValue() &&
14573 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14574 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14575 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14576 DAG.getConstant(0, DL,
14577 CmpOp0.getValueType()),
14579 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14580 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14581 SDValue(Neg.getNode(), 1));
14585 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14586 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14587 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14589 SDValue Res = // Res = 0 or -1.
14590 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14591 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14593 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14594 Res = DAG.getNOT(DL, Res, Res.getValueType());
14596 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14597 if (!N2C || !N2C->isNullValue())
14598 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14603 // Look past (and (setcc_carry (cmp ...)), 1).
14604 if (Cond.getOpcode() == ISD::AND &&
14605 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14606 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14607 if (C && C->getAPIntValue() == 1)
14608 Cond = Cond.getOperand(0);
14611 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14612 // setting operand in place of the X86ISD::SETCC.
14613 unsigned CondOpcode = Cond.getOpcode();
14614 if (CondOpcode == X86ISD::SETCC ||
14615 CondOpcode == X86ISD::SETCC_CARRY) {
14616 CC = Cond.getOperand(0);
14618 SDValue Cmp = Cond.getOperand(1);
14619 unsigned Opc = Cmp.getOpcode();
14620 MVT VT = Op.getSimpleValueType();
14622 bool IllegalFPCMov = false;
14623 if (VT.isFloatingPoint() && !VT.isVector() &&
14624 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14625 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14627 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14628 Opc == X86ISD::BT) { // FIXME
14632 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14633 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14634 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14635 Cond.getOperand(0).getValueType() != MVT::i8)) {
14636 SDValue LHS = Cond.getOperand(0);
14637 SDValue RHS = Cond.getOperand(1);
14638 unsigned X86Opcode;
14641 switch (CondOpcode) {
14642 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14643 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14644 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14645 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14646 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14647 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14648 default: llvm_unreachable("unexpected overflowing operator");
14650 if (CondOpcode == ISD::UMULO)
14651 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14654 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14656 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14658 if (CondOpcode == ISD::UMULO)
14659 Cond = X86Op.getValue(2);
14661 Cond = X86Op.getValue(1);
14663 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14668 // Look past the truncate if the high bits are known zero.
14669 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14670 Cond = Cond.getOperand(0);
14672 // We know the result of AND is compared against zero. Try to match
14674 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14675 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14676 if (NewSetCC.getNode()) {
14677 CC = NewSetCC.getOperand(0);
14678 Cond = NewSetCC.getOperand(1);
14685 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14686 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14689 // a < b ? -1 : 0 -> RES = ~setcc_carry
14690 // a < b ? 0 : -1 -> RES = setcc_carry
14691 // a >= b ? -1 : 0 -> RES = setcc_carry
14692 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14693 if (Cond.getOpcode() == X86ISD::SUB) {
14694 Cond = ConvertCmpIfNecessary(Cond, DAG);
14695 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14697 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14698 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14699 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14700 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14702 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14703 return DAG.getNOT(DL, Res, Res.getValueType());
14708 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14709 // widen the cmov and push the truncate through. This avoids introducing a new
14710 // branch during isel and doesn't add any extensions.
14711 if (Op.getValueType() == MVT::i8 &&
14712 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14713 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14714 if (T1.getValueType() == T2.getValueType() &&
14715 // Blacklist CopyFromReg to avoid partial register stalls.
14716 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14717 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14718 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14719 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14723 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14724 // condition is true.
14725 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14726 SDValue Ops[] = { Op2, Op1, CC, Cond };
14727 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14730 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14731 const X86Subtarget *Subtarget,
14732 SelectionDAG &DAG) {
14733 MVT VT = Op->getSimpleValueType(0);
14734 SDValue In = Op->getOperand(0);
14735 MVT InVT = In.getSimpleValueType();
14736 MVT VTElt = VT.getVectorElementType();
14737 MVT InVTElt = InVT.getVectorElementType();
14741 if ((InVTElt == MVT::i1) &&
14742 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14743 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14745 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14746 VTElt.getSizeInBits() <= 16)) ||
14748 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14749 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14751 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14752 VTElt.getSizeInBits() >= 32))))
14753 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14755 unsigned int NumElts = VT.getVectorNumElements();
14757 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14760 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14761 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14762 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14763 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14766 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14767 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14769 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14772 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14774 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14775 if (VT.is512BitVector())
14777 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14780 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14781 const X86Subtarget *Subtarget,
14782 SelectionDAG &DAG) {
14783 SDValue In = Op->getOperand(0);
14784 MVT VT = Op->getSimpleValueType(0);
14785 MVT InVT = In.getSimpleValueType();
14786 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14788 MVT InSVT = InVT.getScalarType();
14789 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14791 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14793 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14798 // SSE41 targets can use the pmovsx* instructions directly.
14799 if (Subtarget->hasSSE41())
14800 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14802 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14806 // As SRAI is only available on i16/i32 types, we expand only up to i32
14807 // and handle i64 separately.
14808 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14809 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14810 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14811 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14812 Curr = DAG.getBitcast(CurrVT, Curr);
14815 SDValue SignExt = Curr;
14816 if (CurrVT != InVT) {
14817 unsigned SignExtShift =
14818 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14819 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14820 DAG.getConstant(SignExtShift, dl, MVT::i8));
14826 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14827 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14828 DAG.getConstant(31, dl, MVT::i8));
14829 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14830 return DAG.getBitcast(VT, Ext);
14836 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14837 SelectionDAG &DAG) {
14838 MVT VT = Op->getSimpleValueType(0);
14839 SDValue In = Op->getOperand(0);
14840 MVT InVT = In.getSimpleValueType();
14843 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14844 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14846 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14847 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14848 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14851 if (Subtarget->hasInt256())
14852 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14854 // Optimize vectors in AVX mode
14855 // Sign extend v8i16 to v8i32 and
14858 // Divide input vector into two parts
14859 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14860 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14861 // concat the vectors to original VT
14863 unsigned NumElems = InVT.getVectorNumElements();
14864 SDValue Undef = DAG.getUNDEF(InVT);
14866 SmallVector<int,8> ShufMask1(NumElems, -1);
14867 for (unsigned i = 0; i != NumElems/2; ++i)
14870 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14872 SmallVector<int,8> ShufMask2(NumElems, -1);
14873 for (unsigned i = 0; i != NumElems/2; ++i)
14874 ShufMask2[i] = i + NumElems/2;
14876 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14878 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14879 VT.getVectorNumElements()/2);
14881 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14882 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14884 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14887 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14888 // may emit an illegal shuffle but the expansion is still better than scalar
14889 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14890 // we'll emit a shuffle and a arithmetic shift.
14891 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14892 // TODO: It is possible to support ZExt by zeroing the undef values during
14893 // the shuffle phase or after the shuffle.
14894 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14895 SelectionDAG &DAG) {
14896 MVT RegVT = Op.getSimpleValueType();
14897 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14898 assert(RegVT.isInteger() &&
14899 "We only custom lower integer vector sext loads.");
14901 // Nothing useful we can do without SSE2 shuffles.
14902 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14904 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14906 EVT MemVT = Ld->getMemoryVT();
14907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14908 unsigned RegSz = RegVT.getSizeInBits();
14910 ISD::LoadExtType Ext = Ld->getExtensionType();
14912 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14913 && "Only anyext and sext are currently implemented.");
14914 assert(MemVT != RegVT && "Cannot extend to the same type");
14915 assert(MemVT.isVector() && "Must load a vector from memory");
14917 unsigned NumElems = RegVT.getVectorNumElements();
14918 unsigned MemSz = MemVT.getSizeInBits();
14919 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14921 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14922 // The only way in which we have a legal 256-bit vector result but not the
14923 // integer 256-bit operations needed to directly lower a sextload is if we
14924 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14925 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14926 // correctly legalized. We do this late to allow the canonical form of
14927 // sextload to persist throughout the rest of the DAG combiner -- it wants
14928 // to fold together any extensions it can, and so will fuse a sign_extend
14929 // of an sextload into a sextload targeting a wider value.
14931 if (MemSz == 128) {
14932 // Just switch this to a normal load.
14933 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14934 "it must be a legal 128-bit vector "
14936 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14937 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14938 Ld->isInvariant(), Ld->getAlignment());
14940 assert(MemSz < 128 &&
14941 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14942 // Do an sext load to a 128-bit vector type. We want to use the same
14943 // number of elements, but elements half as wide. This will end up being
14944 // recursively lowered by this routine, but will succeed as we definitely
14945 // have all the necessary features if we're using AVX1.
14947 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14948 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14950 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14951 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14952 Ld->isNonTemporal(), Ld->isInvariant(),
14953 Ld->getAlignment());
14956 // Replace chain users with the new chain.
14957 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14958 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14960 // Finally, do a normal sign-extend to the desired register.
14961 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14964 // All sizes must be a power of two.
14965 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14966 "Non-power-of-two elements are not custom lowered!");
14968 // Attempt to load the original value using scalar loads.
14969 // Find the largest scalar type that divides the total loaded size.
14970 MVT SclrLoadTy = MVT::i8;
14971 for (MVT Tp : MVT::integer_valuetypes()) {
14972 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14977 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14978 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14980 SclrLoadTy = MVT::f64;
14982 // Calculate the number of scalar loads that we need to perform
14983 // in order to load our vector from memory.
14984 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14986 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14987 "Can only lower sext loads with a single scalar load!");
14989 unsigned loadRegZize = RegSz;
14990 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14993 // Represent our vector as a sequence of elements which are the
14994 // largest scalar that we can load.
14995 EVT LoadUnitVecVT = EVT::getVectorVT(
14996 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14998 // Represent the data using the same element type that is stored in
14999 // memory. In practice, we ''widen'' MemVT.
15001 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15002 loadRegZize / MemVT.getScalarType().getSizeInBits());
15004 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15005 "Invalid vector type");
15007 // We can't shuffle using an illegal type.
15008 assert(TLI.isTypeLegal(WideVecVT) &&
15009 "We only lower types that form legal widened vector types");
15011 SmallVector<SDValue, 8> Chains;
15012 SDValue Ptr = Ld->getBasePtr();
15013 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15014 TLI.getPointerTy(DAG.getDataLayout()));
15015 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15017 for (unsigned i = 0; i < NumLoads; ++i) {
15018 // Perform a single load.
15019 SDValue ScalarLoad =
15020 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15021 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15022 Ld->getAlignment());
15023 Chains.push_back(ScalarLoad.getValue(1));
15024 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15025 // another round of DAGCombining.
15027 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15029 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15030 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15032 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15035 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15037 // Bitcast the loaded value to a vector of the original element type, in
15038 // the size of the target vector type.
15039 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15040 unsigned SizeRatio = RegSz / MemSz;
15042 if (Ext == ISD::SEXTLOAD) {
15043 // If we have SSE4.1, we can directly emit a VSEXT node.
15044 if (Subtarget->hasSSE41()) {
15045 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15046 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15050 // Otherwise we'll shuffle the small elements in the high bits of the
15051 // larger type and perform an arithmetic shift. If the shift is not legal
15052 // it's better to scalarize.
15053 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15054 "We can't implement a sext load without an arithmetic right shift!");
15056 // Redistribute the loaded elements into the different locations.
15057 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15058 for (unsigned i = 0; i != NumElems; ++i)
15059 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15061 SDValue Shuff = DAG.getVectorShuffle(
15062 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15064 Shuff = DAG.getBitcast(RegVT, Shuff);
15066 // Build the arithmetic shift.
15067 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15068 MemVT.getVectorElementType().getSizeInBits();
15070 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
15071 DAG.getConstant(Amt, dl, RegVT));
15073 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15077 // Redistribute the loaded elements into the different locations.
15078 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15079 for (unsigned i = 0; i != NumElems; ++i)
15080 ShuffleVec[i * SizeRatio] = i;
15082 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15083 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15085 // Bitcast to the requested type.
15086 Shuff = DAG.getBitcast(RegVT, Shuff);
15087 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15091 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15092 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15093 // from the AND / OR.
15094 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15095 Opc = Op.getOpcode();
15096 if (Opc != ISD::OR && Opc != ISD::AND)
15098 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15099 Op.getOperand(0).hasOneUse() &&
15100 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15101 Op.getOperand(1).hasOneUse());
15104 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15105 // 1 and that the SETCC node has a single use.
15106 static bool isXor1OfSetCC(SDValue Op) {
15107 if (Op.getOpcode() != ISD::XOR)
15109 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15110 if (N1C && N1C->getAPIntValue() == 1) {
15111 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15112 Op.getOperand(0).hasOneUse();
15117 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15118 bool addTest = true;
15119 SDValue Chain = Op.getOperand(0);
15120 SDValue Cond = Op.getOperand(1);
15121 SDValue Dest = Op.getOperand(2);
15124 bool Inverted = false;
15126 if (Cond.getOpcode() == ISD::SETCC) {
15127 // Check for setcc([su]{add,sub,mul}o == 0).
15128 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15129 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15130 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15131 Cond.getOperand(0).getResNo() == 1 &&
15132 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15133 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15134 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15135 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15136 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15137 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15139 Cond = Cond.getOperand(0);
15141 SDValue NewCond = LowerSETCC(Cond, DAG);
15142 if (NewCond.getNode())
15147 // FIXME: LowerXALUO doesn't handle these!!
15148 else if (Cond.getOpcode() == X86ISD::ADD ||
15149 Cond.getOpcode() == X86ISD::SUB ||
15150 Cond.getOpcode() == X86ISD::SMUL ||
15151 Cond.getOpcode() == X86ISD::UMUL)
15152 Cond = LowerXALUO(Cond, DAG);
15155 // Look pass (and (setcc_carry (cmp ...)), 1).
15156 if (Cond.getOpcode() == ISD::AND &&
15157 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15158 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15159 if (C && C->getAPIntValue() == 1)
15160 Cond = Cond.getOperand(0);
15163 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15164 // setting operand in place of the X86ISD::SETCC.
15165 unsigned CondOpcode = Cond.getOpcode();
15166 if (CondOpcode == X86ISD::SETCC ||
15167 CondOpcode == X86ISD::SETCC_CARRY) {
15168 CC = Cond.getOperand(0);
15170 SDValue Cmp = Cond.getOperand(1);
15171 unsigned Opc = Cmp.getOpcode();
15172 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15173 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15177 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15181 // These can only come from an arithmetic instruction with overflow,
15182 // e.g. SADDO, UADDO.
15183 Cond = Cond.getNode()->getOperand(1);
15189 CondOpcode = Cond.getOpcode();
15190 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15191 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15192 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15193 Cond.getOperand(0).getValueType() != MVT::i8)) {
15194 SDValue LHS = Cond.getOperand(0);
15195 SDValue RHS = Cond.getOperand(1);
15196 unsigned X86Opcode;
15199 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15200 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15202 switch (CondOpcode) {
15203 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15207 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15210 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15211 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15213 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15215 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15218 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15219 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15220 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15221 default: llvm_unreachable("unexpected overflowing operator");
15224 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15225 if (CondOpcode == ISD::UMULO)
15226 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15229 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15231 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15233 if (CondOpcode == ISD::UMULO)
15234 Cond = X86Op.getValue(2);
15236 Cond = X86Op.getValue(1);
15238 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15242 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15243 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15244 if (CondOpc == ISD::OR) {
15245 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15246 // two branches instead of an explicit OR instruction with a
15248 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15249 isX86LogicalCmp(Cmp)) {
15250 CC = Cond.getOperand(0).getOperand(0);
15251 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15252 Chain, Dest, CC, Cmp);
15253 CC = Cond.getOperand(1).getOperand(0);
15257 } else { // ISD::AND
15258 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15259 // two branches instead of an explicit AND instruction with a
15260 // separate test. However, we only do this if this block doesn't
15261 // have a fall-through edge, because this requires an explicit
15262 // jmp when the condition is false.
15263 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15264 isX86LogicalCmp(Cmp) &&
15265 Op.getNode()->hasOneUse()) {
15266 X86::CondCode CCode =
15267 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15268 CCode = X86::GetOppositeBranchCondition(CCode);
15269 CC = DAG.getConstant(CCode, dl, MVT::i8);
15270 SDNode *User = *Op.getNode()->use_begin();
15271 // Look for an unconditional branch following this conditional branch.
15272 // We need this because we need to reverse the successors in order
15273 // to implement FCMP_OEQ.
15274 if (User->getOpcode() == ISD::BR) {
15275 SDValue FalseBB = User->getOperand(1);
15277 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15278 assert(NewBR == User);
15282 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15283 Chain, Dest, CC, Cmp);
15284 X86::CondCode CCode =
15285 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15286 CCode = X86::GetOppositeBranchCondition(CCode);
15287 CC = DAG.getConstant(CCode, dl, MVT::i8);
15293 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15294 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15295 // It should be transformed during dag combiner except when the condition
15296 // is set by a arithmetics with overflow node.
15297 X86::CondCode CCode =
15298 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15299 CCode = X86::GetOppositeBranchCondition(CCode);
15300 CC = DAG.getConstant(CCode, dl, MVT::i8);
15301 Cond = Cond.getOperand(0).getOperand(1);
15303 } else if (Cond.getOpcode() == ISD::SETCC &&
15304 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15305 // For FCMP_OEQ, we can emit
15306 // two branches instead of an explicit AND instruction with a
15307 // separate test. However, we only do this if this block doesn't
15308 // have a fall-through edge, because this requires an explicit
15309 // jmp when the condition is false.
15310 if (Op.getNode()->hasOneUse()) {
15311 SDNode *User = *Op.getNode()->use_begin();
15312 // Look for an unconditional branch following this conditional branch.
15313 // We need this because we need to reverse the successors in order
15314 // to implement FCMP_OEQ.
15315 if (User->getOpcode() == ISD::BR) {
15316 SDValue FalseBB = User->getOperand(1);
15318 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15319 assert(NewBR == User);
15323 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15324 Cond.getOperand(0), Cond.getOperand(1));
15325 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15326 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15327 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15328 Chain, Dest, CC, Cmp);
15329 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15334 } else if (Cond.getOpcode() == ISD::SETCC &&
15335 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15336 // For FCMP_UNE, we can emit
15337 // two branches instead of an explicit AND instruction with a
15338 // separate test. However, we only do this if this block doesn't
15339 // have a fall-through edge, because this requires an explicit
15340 // jmp when the condition is false.
15341 if (Op.getNode()->hasOneUse()) {
15342 SDNode *User = *Op.getNode()->use_begin();
15343 // Look for an unconditional branch following this conditional branch.
15344 // We need this because we need to reverse the successors in order
15345 // to implement FCMP_UNE.
15346 if (User->getOpcode() == ISD::BR) {
15347 SDValue FalseBB = User->getOperand(1);
15349 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15350 assert(NewBR == User);
15353 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15354 Cond.getOperand(0), Cond.getOperand(1));
15355 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15356 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15357 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15358 Chain, Dest, CC, Cmp);
15359 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15369 // Look pass the truncate if the high bits are known zero.
15370 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15371 Cond = Cond.getOperand(0);
15373 // We know the result of AND is compared against zero. Try to match
15375 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15376 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15377 if (NewSetCC.getNode()) {
15378 CC = NewSetCC.getOperand(0);
15379 Cond = NewSetCC.getOperand(1);
15386 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15387 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15388 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15390 Cond = ConvertCmpIfNecessary(Cond, DAG);
15391 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15392 Chain, Dest, CC, Cond);
15395 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15396 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15397 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15398 // that the guard pages used by the OS virtual memory manager are allocated in
15399 // correct sequence.
15401 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15402 SelectionDAG &DAG) const {
15403 MachineFunction &MF = DAG.getMachineFunction();
15404 bool SplitStack = MF.shouldSplitStack();
15405 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15411 SDNode* Node = Op.getNode();
15413 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15414 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15415 " not tell us which reg is the stack pointer!");
15416 EVT VT = Node->getValueType(0);
15417 SDValue Tmp1 = SDValue(Node, 0);
15418 SDValue Tmp2 = SDValue(Node, 1);
15419 SDValue Tmp3 = Node->getOperand(2);
15420 SDValue Chain = Tmp1.getOperand(0);
15422 // Chain the dynamic stack allocation so that it doesn't modify the stack
15423 // pointer when other instructions are using the stack.
15424 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15427 SDValue Size = Tmp2.getOperand(1);
15428 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15429 Chain = SP.getValue(1);
15430 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15431 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15432 unsigned StackAlign = TFI.getStackAlignment();
15433 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15434 if (Align > StackAlign)
15435 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15436 DAG.getConstant(-(uint64_t)Align, dl, VT));
15437 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15439 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15440 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15443 SDValue Ops[2] = { Tmp1, Tmp2 };
15444 return DAG.getMergeValues(Ops, dl);
15448 SDValue Chain = Op.getOperand(0);
15449 SDValue Size = Op.getOperand(1);
15450 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15451 EVT VT = Op.getNode()->getValueType(0);
15453 bool Is64Bit = Subtarget->is64Bit();
15454 MVT SPTy = getPointerTy(DAG.getDataLayout());
15457 MachineRegisterInfo &MRI = MF.getRegInfo();
15460 // The 64 bit implementation of segmented stacks needs to clobber both r10
15461 // r11. This makes it impossible to use it along with nested parameters.
15462 const Function *F = MF.getFunction();
15464 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15466 if (I->hasNestAttr())
15467 report_fatal_error("Cannot use segmented stacks with functions that "
15468 "have nested arguments.");
15471 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15472 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15473 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15474 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15475 DAG.getRegister(Vreg, SPTy));
15476 SDValue Ops1[2] = { Value, Chain };
15477 return DAG.getMergeValues(Ops1, dl);
15480 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15482 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15483 Flag = Chain.getValue(1);
15484 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15486 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15488 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15489 unsigned SPReg = RegInfo->getStackRegister();
15490 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15491 Chain = SP.getValue(1);
15494 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15495 DAG.getConstant(-(uint64_t)Align, dl, VT));
15496 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15499 SDValue Ops1[2] = { SP, Chain };
15500 return DAG.getMergeValues(Ops1, dl);
15504 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15505 MachineFunction &MF = DAG.getMachineFunction();
15506 auto PtrVT = getPointerTy(MF.getDataLayout());
15507 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15509 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15512 if (!Subtarget->is64Bit() ||
15513 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15514 // vastart just stores the address of the VarArgsFrameIndex slot into the
15515 // memory location argument.
15516 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15517 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15518 MachinePointerInfo(SV), false, false, 0);
15522 // gp_offset (0 - 6 * 8)
15523 // fp_offset (48 - 48 + 8 * 16)
15524 // overflow_arg_area (point to parameters coming in memory).
15526 SmallVector<SDValue, 8> MemOps;
15527 SDValue FIN = Op.getOperand(1);
15529 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15530 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15532 FIN, MachinePointerInfo(SV), false, false, 0);
15533 MemOps.push_back(Store);
15536 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15537 Store = DAG.getStore(Op.getOperand(0), DL,
15538 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15540 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15541 MemOps.push_back(Store);
15543 // Store ptr to overflow_arg_area
15544 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15545 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15546 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15547 MachinePointerInfo(SV, 8),
15549 MemOps.push_back(Store);
15551 // Store ptr to reg_save_area.
15552 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15553 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15554 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15555 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15556 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15557 MemOps.push_back(Store);
15558 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15561 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15562 assert(Subtarget->is64Bit() &&
15563 "LowerVAARG only handles 64-bit va_arg!");
15564 assert(Op.getNode()->getNumOperands() == 4);
15566 MachineFunction &MF = DAG.getMachineFunction();
15567 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15568 // The Win64 ABI uses char* instead of a structure.
15569 return DAG.expandVAArg(Op.getNode());
15571 SDValue Chain = Op.getOperand(0);
15572 SDValue SrcPtr = Op.getOperand(1);
15573 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15574 unsigned Align = Op.getConstantOperandVal(3);
15577 EVT ArgVT = Op.getNode()->getValueType(0);
15578 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15579 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15582 // Decide which area this value should be read from.
15583 // TODO: Implement the AMD64 ABI in its entirety. This simple
15584 // selection mechanism works only for the basic types.
15585 if (ArgVT == MVT::f80) {
15586 llvm_unreachable("va_arg for f80 not yet implemented");
15587 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15588 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15589 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15590 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15592 llvm_unreachable("Unhandled argument type in LowerVAARG");
15595 if (ArgMode == 2) {
15596 // Sanity Check: Make sure using fp_offset makes sense.
15597 assert(!Subtarget->useSoftFloat() &&
15598 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15599 Subtarget->hasSSE1());
15602 // Insert VAARG_64 node into the DAG
15603 // VAARG_64 returns two values: Variable Argument Address, Chain
15604 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15605 DAG.getConstant(ArgMode, dl, MVT::i8),
15606 DAG.getConstant(Align, dl, MVT::i32)};
15607 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15608 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15609 VTs, InstOps, MVT::i64,
15610 MachinePointerInfo(SV),
15612 /*Volatile=*/false,
15614 /*WriteMem=*/true);
15615 Chain = VAARG.getValue(1);
15617 // Load the next argument and return it
15618 return DAG.getLoad(ArgVT, dl,
15621 MachinePointerInfo(),
15622 false, false, false, 0);
15625 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15626 SelectionDAG &DAG) {
15627 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15628 // where a va_list is still an i8*.
15629 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15630 if (Subtarget->isCallingConvWin64(
15631 DAG.getMachineFunction().getFunction()->getCallingConv()))
15632 // Probably a Win64 va_copy.
15633 return DAG.expandVACopy(Op.getNode());
15635 SDValue Chain = Op.getOperand(0);
15636 SDValue DstPtr = Op.getOperand(1);
15637 SDValue SrcPtr = Op.getOperand(2);
15638 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15639 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15642 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15643 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15645 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15648 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15649 // amount is a constant. Takes immediate version of shift as input.
15650 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15651 SDValue SrcOp, uint64_t ShiftAmt,
15652 SelectionDAG &DAG) {
15653 MVT ElementType = VT.getVectorElementType();
15655 // Fold this packed shift into its first operand if ShiftAmt is 0.
15659 // Check for ShiftAmt >= element width
15660 if (ShiftAmt >= ElementType.getSizeInBits()) {
15661 if (Opc == X86ISD::VSRAI)
15662 ShiftAmt = ElementType.getSizeInBits() - 1;
15664 return DAG.getConstant(0, dl, VT);
15667 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15668 && "Unknown target vector shift-by-constant node");
15670 // Fold this packed vector shift into a build vector if SrcOp is a
15671 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15672 if (VT == SrcOp.getSimpleValueType() &&
15673 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15674 SmallVector<SDValue, 8> Elts;
15675 unsigned NumElts = SrcOp->getNumOperands();
15676 ConstantSDNode *ND;
15679 default: llvm_unreachable(nullptr);
15680 case X86ISD::VSHLI:
15681 for (unsigned i=0; i!=NumElts; ++i) {
15682 SDValue CurrentOp = SrcOp->getOperand(i);
15683 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15684 Elts.push_back(CurrentOp);
15687 ND = cast<ConstantSDNode>(CurrentOp);
15688 const APInt &C = ND->getAPIntValue();
15689 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15692 case X86ISD::VSRLI:
15693 for (unsigned i=0; i!=NumElts; ++i) {
15694 SDValue CurrentOp = SrcOp->getOperand(i);
15695 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15696 Elts.push_back(CurrentOp);
15699 ND = cast<ConstantSDNode>(CurrentOp);
15700 const APInt &C = ND->getAPIntValue();
15701 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15704 case X86ISD::VSRAI:
15705 for (unsigned i=0; i!=NumElts; ++i) {
15706 SDValue CurrentOp = SrcOp->getOperand(i);
15707 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15708 Elts.push_back(CurrentOp);
15711 ND = cast<ConstantSDNode>(CurrentOp);
15712 const APInt &C = ND->getAPIntValue();
15713 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15718 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15721 return DAG.getNode(Opc, dl, VT, SrcOp,
15722 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15725 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15726 // may or may not be a constant. Takes immediate version of shift as input.
15727 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15728 SDValue SrcOp, SDValue ShAmt,
15729 SelectionDAG &DAG) {
15730 MVT SVT = ShAmt.getSimpleValueType();
15731 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15733 // Catch shift-by-constant.
15734 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15735 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15736 CShAmt->getZExtValue(), DAG);
15738 // Change opcode to non-immediate version
15740 default: llvm_unreachable("Unknown target vector shift node");
15741 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15742 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15743 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15746 const X86Subtarget &Subtarget =
15747 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15748 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15749 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15750 // Let the shuffle legalizer expand this shift amount node.
15751 SDValue Op0 = ShAmt.getOperand(0);
15752 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15753 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15755 // Need to build a vector containing shift amount.
15756 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15757 SmallVector<SDValue, 4> ShOps;
15758 ShOps.push_back(ShAmt);
15759 if (SVT == MVT::i32) {
15760 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15761 ShOps.push_back(DAG.getUNDEF(SVT));
15763 ShOps.push_back(DAG.getUNDEF(SVT));
15765 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15766 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15769 // The return type has to be a 128-bit type with the same element
15770 // type as the input type.
15771 MVT EltVT = VT.getVectorElementType();
15772 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15774 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15775 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15778 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15779 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15780 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15781 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15782 SDValue PreservedSrc,
15783 const X86Subtarget *Subtarget,
15784 SelectionDAG &DAG) {
15785 EVT VT = Op.getValueType();
15786 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15787 MVT::i1, VT.getVectorNumElements());
15788 SDValue VMask = SDValue();
15789 unsigned OpcodeSelect = ISD::VSELECT;
15792 assert(MaskVT.isSimple() && "invalid mask type");
15794 if (isAllOnes(Mask))
15797 if (MaskVT.bitsGT(Mask.getValueType())) {
15798 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15799 MaskVT.getSizeInBits());
15800 VMask = DAG.getBitcast(MaskVT,
15801 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15803 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15804 Mask.getValueType().getSizeInBits());
15805 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15806 // are extracted by EXTRACT_SUBVECTOR.
15807 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15808 DAG.getBitcast(BitcastVT, Mask),
15809 DAG.getIntPtrConstant(0, dl));
15812 switch (Op.getOpcode()) {
15814 case X86ISD::PCMPEQM:
15815 case X86ISD::PCMPGTM:
15817 case X86ISD::CMPMU:
15818 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15819 case X86ISD::VFPCLASS:
15820 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15821 case X86ISD::VTRUNC:
15822 case X86ISD::VTRUNCS:
15823 case X86ISD::VTRUNCUS:
15824 // We can't use ISD::VSELECT here because it is not always "Legal"
15825 // for the destination type. For example vpmovqb require only AVX512
15826 // and vselect that can operate on byte element type require BWI
15827 OpcodeSelect = X86ISD::SELECT;
15830 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15831 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15832 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15835 /// \brief Creates an SDNode for a predicated scalar operation.
15836 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15837 /// The mask is coming as MVT::i8 and it should be truncated
15838 /// to MVT::i1 while lowering masking intrinsics.
15839 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15840 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15841 /// for a scalar instruction.
15842 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15843 SDValue PreservedSrc,
15844 const X86Subtarget *Subtarget,
15845 SelectionDAG &DAG) {
15846 if (isAllOnes(Mask))
15849 EVT VT = Op.getValueType();
15851 // The mask should be of type MVT::i1
15852 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15854 if (Op.getOpcode() == X86ISD::FSETCC)
15855 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15857 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15858 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15859 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15862 static int getSEHRegistrationNodeSize(const Function *Fn) {
15863 if (!Fn->hasPersonalityFn())
15864 report_fatal_error(
15865 "querying registration node size for function without personality");
15866 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15867 // WinEHStatePass for the full struct definition.
15868 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15869 case EHPersonality::MSVC_X86SEH: return 24;
15870 case EHPersonality::MSVC_CXX: return 16;
15873 report_fatal_error("can only recover FP for MSVC EH personality functions");
15876 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15877 /// function or when returning to a parent frame after catching an exception, we
15878 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15879 /// Here's the math:
15880 /// RegNodeBase = EntryEBP - RegNodeSize
15881 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15882 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15883 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15884 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15885 SDValue EntryEBP) {
15886 MachineFunction &MF = DAG.getMachineFunction();
15889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15890 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15892 // It's possible that the parent function no longer has a personality function
15893 // if the exceptional code was optimized away, in which case we just return
15894 // the incoming EBP.
15895 if (!Fn->hasPersonalityFn())
15898 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15900 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15902 MCSymbol *OffsetSym =
15903 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15904 GlobalValue::getRealLinkageName(Fn->getName()));
15905 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15906 SDValue RegNodeFrameOffset =
15907 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15909 // RegNodeBase = EntryEBP - RegNodeSize
15910 // ParentFP = RegNodeBase - RegNodeFrameOffset
15911 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15912 DAG.getConstant(RegNodeSize, dl, PtrVT));
15913 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15916 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15917 SelectionDAG &DAG) {
15919 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15920 EVT VT = Op.getValueType();
15921 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15923 switch(IntrData->Type) {
15924 case INTR_TYPE_1OP:
15925 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15926 case INTR_TYPE_2OP:
15927 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15929 case INTR_TYPE_2OP_IMM8:
15930 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15931 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15932 case INTR_TYPE_3OP:
15933 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15934 Op.getOperand(2), Op.getOperand(3));
15935 case INTR_TYPE_4OP:
15936 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15937 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15938 case INTR_TYPE_1OP_MASK_RM: {
15939 SDValue Src = Op.getOperand(1);
15940 SDValue PassThru = Op.getOperand(2);
15941 SDValue Mask = Op.getOperand(3);
15942 SDValue RoundingMode;
15943 // We allways add rounding mode to the Node.
15944 // If the rounding mode is not specified, we add the
15945 // "current direction" mode.
15946 if (Op.getNumOperands() == 4)
15948 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15950 RoundingMode = Op.getOperand(4);
15951 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15952 if (IntrWithRoundingModeOpcode != 0)
15953 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15954 X86::STATIC_ROUNDING::CUR_DIRECTION)
15955 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15956 dl, Op.getValueType(), Src, RoundingMode),
15957 Mask, PassThru, Subtarget, DAG);
15958 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15960 Mask, PassThru, Subtarget, DAG);
15962 case INTR_TYPE_1OP_MASK: {
15963 SDValue Src = Op.getOperand(1);
15964 SDValue PassThru = Op.getOperand(2);
15965 SDValue Mask = Op.getOperand(3);
15966 // We add rounding mode to the Node when
15967 // - RM Opcode is specified and
15968 // - RM is not "current direction".
15969 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15970 if (IntrWithRoundingModeOpcode != 0) {
15971 SDValue Rnd = Op.getOperand(4);
15972 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15973 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15974 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15975 dl, Op.getValueType(),
15977 Mask, PassThru, Subtarget, DAG);
15980 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15981 Mask, PassThru, Subtarget, DAG);
15983 case INTR_TYPE_SCALAR_MASK: {
15984 SDValue Src1 = Op.getOperand(1);
15985 SDValue Src2 = Op.getOperand(2);
15986 SDValue passThru = Op.getOperand(3);
15987 SDValue Mask = Op.getOperand(4);
15988 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
15989 Mask, passThru, Subtarget, DAG);
15991 case INTR_TYPE_SCALAR_MASK_RM: {
15992 SDValue Src1 = Op.getOperand(1);
15993 SDValue Src2 = Op.getOperand(2);
15994 SDValue Src0 = Op.getOperand(3);
15995 SDValue Mask = Op.getOperand(4);
15996 // There are 2 kinds of intrinsics in this group:
15997 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
15998 // (2) With rounding mode and sae - 7 operands.
15999 if (Op.getNumOperands() == 6) {
16000 SDValue Sae = Op.getOperand(5);
16001 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16002 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16004 Mask, Src0, Subtarget, DAG);
16006 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16007 SDValue RoundingMode = Op.getOperand(5);
16008 SDValue Sae = Op.getOperand(6);
16009 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16010 RoundingMode, Sae),
16011 Mask, Src0, Subtarget, DAG);
16013 case INTR_TYPE_2OP_MASK: {
16014 SDValue Src1 = Op.getOperand(1);
16015 SDValue Src2 = Op.getOperand(2);
16016 SDValue PassThru = Op.getOperand(3);
16017 SDValue Mask = Op.getOperand(4);
16018 // We specify 2 possible opcodes for intrinsics with rounding modes.
16019 // First, we check if the intrinsic may have non-default rounding mode,
16020 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16021 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16022 if (IntrWithRoundingModeOpcode != 0) {
16023 SDValue Rnd = Op.getOperand(5);
16024 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16025 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16026 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16027 dl, Op.getValueType(),
16029 Mask, PassThru, Subtarget, DAG);
16032 // TODO: Intrinsics should have fast-math-flags to propagate.
16033 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16034 Mask, PassThru, Subtarget, DAG);
16036 case INTR_TYPE_2OP_MASK_RM: {
16037 SDValue Src1 = Op.getOperand(1);
16038 SDValue Src2 = Op.getOperand(2);
16039 SDValue PassThru = Op.getOperand(3);
16040 SDValue Mask = Op.getOperand(4);
16041 // We specify 2 possible modes for intrinsics, with/without rounding
16043 // First, we check if the intrinsic have rounding mode (6 operands),
16044 // if not, we set rounding mode to "current".
16046 if (Op.getNumOperands() == 6)
16047 Rnd = Op.getOperand(5);
16049 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16050 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16052 Mask, PassThru, Subtarget, DAG);
16054 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16055 SDValue Src1 = Op.getOperand(1);
16056 SDValue Src2 = Op.getOperand(2);
16057 SDValue Src3 = Op.getOperand(3);
16058 SDValue PassThru = Op.getOperand(4);
16059 SDValue Mask = Op.getOperand(5);
16060 SDValue Sae = Op.getOperand(6);
16062 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16064 Mask, PassThru, Subtarget, DAG);
16066 case INTR_TYPE_3OP_MASK_RM: {
16067 SDValue Src1 = Op.getOperand(1);
16068 SDValue Src2 = Op.getOperand(2);
16069 SDValue Imm = Op.getOperand(3);
16070 SDValue PassThru = Op.getOperand(4);
16071 SDValue Mask = Op.getOperand(5);
16072 // We specify 2 possible modes for intrinsics, with/without rounding
16074 // First, we check if the intrinsic have rounding mode (7 operands),
16075 // if not, we set rounding mode to "current".
16077 if (Op.getNumOperands() == 7)
16078 Rnd = Op.getOperand(6);
16080 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16081 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16082 Src1, Src2, Imm, Rnd),
16083 Mask, PassThru, Subtarget, DAG);
16085 case INTR_TYPE_3OP_IMM8_MASK:
16086 case INTR_TYPE_3OP_MASK:
16087 case INSERT_SUBVEC: {
16088 SDValue Src1 = Op.getOperand(1);
16089 SDValue Src2 = Op.getOperand(2);
16090 SDValue Src3 = Op.getOperand(3);
16091 SDValue PassThru = Op.getOperand(4);
16092 SDValue Mask = Op.getOperand(5);
16094 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16095 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16096 else if (IntrData->Type == INSERT_SUBVEC) {
16097 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16098 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16099 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16100 Imm *= Src2.getValueType().getVectorNumElements();
16101 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16104 // We specify 2 possible opcodes for intrinsics with rounding modes.
16105 // First, we check if the intrinsic may have non-default rounding mode,
16106 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16107 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16108 if (IntrWithRoundingModeOpcode != 0) {
16109 SDValue Rnd = Op.getOperand(6);
16110 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16111 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16112 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16113 dl, Op.getValueType(),
16114 Src1, Src2, Src3, Rnd),
16115 Mask, PassThru, Subtarget, DAG);
16118 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16120 Mask, PassThru, Subtarget, DAG);
16122 case VPERM_3OP_MASKZ:
16123 case VPERM_3OP_MASK:
16126 case FMA_OP_MASK: {
16127 SDValue Src1 = Op.getOperand(1);
16128 SDValue Src2 = Op.getOperand(2);
16129 SDValue Src3 = Op.getOperand(3);
16130 SDValue Mask = Op.getOperand(4);
16131 EVT VT = Op.getValueType();
16132 SDValue PassThru = SDValue();
16134 // set PassThru element
16135 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16136 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16137 else if (IntrData->Type == FMA_OP_MASK3)
16142 // We specify 2 possible opcodes for intrinsics with rounding modes.
16143 // First, we check if the intrinsic may have non-default rounding mode,
16144 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16145 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16146 if (IntrWithRoundingModeOpcode != 0) {
16147 SDValue Rnd = Op.getOperand(5);
16148 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16149 X86::STATIC_ROUNDING::CUR_DIRECTION)
16150 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16151 dl, Op.getValueType(),
16152 Src1, Src2, Src3, Rnd),
16153 Mask, PassThru, Subtarget, DAG);
16155 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16156 dl, Op.getValueType(),
16158 Mask, PassThru, Subtarget, DAG);
16161 // FPclass intrinsics with mask
16162 SDValue Src1 = Op.getOperand(1);
16163 EVT VT = Src1.getValueType();
16164 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16165 VT.getVectorNumElements());
16166 SDValue Imm = Op.getOperand(2);
16167 SDValue Mask = Op.getOperand(3);
16168 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16169 Mask.getValueType().getSizeInBits());
16170 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16171 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16172 DAG.getTargetConstant(0, dl, MaskVT),
16174 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16175 DAG.getUNDEF(BitcastVT), FPclassMask,
16176 DAG.getIntPtrConstant(0, dl));
16177 return DAG.getBitcast(Op.getValueType(), Res);
16180 case CMP_MASK_CC: {
16181 // Comparison intrinsics with masks.
16182 // Example of transformation:
16183 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16184 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16186 // (v8i1 (insert_subvector undef,
16187 // (v2i1 (and (PCMPEQM %a, %b),
16188 // (extract_subvector
16189 // (v8i1 (bitcast %mask)), 0))), 0))))
16190 EVT VT = Op.getOperand(1).getValueType();
16191 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16192 VT.getVectorNumElements());
16193 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16194 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16195 Mask.getValueType().getSizeInBits());
16197 if (IntrData->Type == CMP_MASK_CC) {
16198 SDValue CC = Op.getOperand(3);
16199 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16200 // We specify 2 possible opcodes for intrinsics with rounding modes.
16201 // First, we check if the intrinsic may have non-default rounding mode,
16202 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16203 if (IntrData->Opc1 != 0) {
16204 SDValue Rnd = Op.getOperand(5);
16205 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16206 X86::STATIC_ROUNDING::CUR_DIRECTION)
16207 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16208 Op.getOperand(2), CC, Rnd);
16210 //default rounding mode
16212 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16213 Op.getOperand(2), CC);
16216 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16217 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16220 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16221 DAG.getTargetConstant(0, dl,
16224 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16225 DAG.getUNDEF(BitcastVT), CmpMask,
16226 DAG.getIntPtrConstant(0, dl));
16227 return DAG.getBitcast(Op.getValueType(), Res);
16229 case CMP_MASK_SCALAR_CC: {
16230 SDValue Src1 = Op.getOperand(1);
16231 SDValue Src2 = Op.getOperand(2);
16232 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16233 SDValue Mask = Op.getOperand(4);
16236 if (IntrData->Opc1 != 0) {
16237 SDValue Rnd = Op.getOperand(5);
16238 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16239 X86::STATIC_ROUNDING::CUR_DIRECTION)
16240 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16242 //default rounding mode
16244 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16246 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16247 DAG.getTargetConstant(0, dl,
16251 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16252 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16253 DAG.getValueType(MVT::i1));
16255 case COMI: { // Comparison intrinsics
16256 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16257 SDValue LHS = Op.getOperand(1);
16258 SDValue RHS = Op.getOperand(2);
16259 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16260 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16261 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16262 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16263 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16264 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16267 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16268 Op.getOperand(1), Op.getOperand(2), DAG);
16270 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16271 Op.getSimpleValueType(),
16273 Op.getOperand(2), DAG),
16274 Op.getOperand(4), Op.getOperand(3), Subtarget,
16276 case COMPRESS_EXPAND_IN_REG: {
16277 SDValue Mask = Op.getOperand(3);
16278 SDValue DataToCompress = Op.getOperand(1);
16279 SDValue PassThru = Op.getOperand(2);
16280 if (isAllOnes(Mask)) // return data as is
16281 return Op.getOperand(1);
16283 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16285 Mask, PassThru, Subtarget, DAG);
16288 SDValue Mask = Op.getOperand(3);
16289 EVT VT = Op.getValueType();
16290 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16291 VT.getVectorNumElements());
16292 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16293 Mask.getValueType().getSizeInBits());
16295 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16296 DAG.getBitcast(BitcastVT, Mask),
16297 DAG.getIntPtrConstant(0, dl));
16298 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16307 default: return SDValue(); // Don't custom lower most intrinsics.
16309 case Intrinsic::x86_avx2_permd:
16310 case Intrinsic::x86_avx2_permps:
16311 // Operands intentionally swapped. Mask is last operand to intrinsic,
16312 // but second operand for node/instruction.
16313 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16314 Op.getOperand(2), Op.getOperand(1));
16316 // ptest and testp intrinsics. The intrinsic these come from are designed to
16317 // return an integer value, not just an instruction so lower it to the ptest
16318 // or testp pattern and a setcc for the result.
16319 case Intrinsic::x86_sse41_ptestz:
16320 case Intrinsic::x86_sse41_ptestc:
16321 case Intrinsic::x86_sse41_ptestnzc:
16322 case Intrinsic::x86_avx_ptestz_256:
16323 case Intrinsic::x86_avx_ptestc_256:
16324 case Intrinsic::x86_avx_ptestnzc_256:
16325 case Intrinsic::x86_avx_vtestz_ps:
16326 case Intrinsic::x86_avx_vtestc_ps:
16327 case Intrinsic::x86_avx_vtestnzc_ps:
16328 case Intrinsic::x86_avx_vtestz_pd:
16329 case Intrinsic::x86_avx_vtestc_pd:
16330 case Intrinsic::x86_avx_vtestnzc_pd:
16331 case Intrinsic::x86_avx_vtestz_ps_256:
16332 case Intrinsic::x86_avx_vtestc_ps_256:
16333 case Intrinsic::x86_avx_vtestnzc_ps_256:
16334 case Intrinsic::x86_avx_vtestz_pd_256:
16335 case Intrinsic::x86_avx_vtestc_pd_256:
16336 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16337 bool IsTestPacked = false;
16340 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16341 case Intrinsic::x86_avx_vtestz_ps:
16342 case Intrinsic::x86_avx_vtestz_pd:
16343 case Intrinsic::x86_avx_vtestz_ps_256:
16344 case Intrinsic::x86_avx_vtestz_pd_256:
16345 IsTestPacked = true; // Fallthrough
16346 case Intrinsic::x86_sse41_ptestz:
16347 case Intrinsic::x86_avx_ptestz_256:
16349 X86CC = X86::COND_E;
16351 case Intrinsic::x86_avx_vtestc_ps:
16352 case Intrinsic::x86_avx_vtestc_pd:
16353 case Intrinsic::x86_avx_vtestc_ps_256:
16354 case Intrinsic::x86_avx_vtestc_pd_256:
16355 IsTestPacked = true; // Fallthrough
16356 case Intrinsic::x86_sse41_ptestc:
16357 case Intrinsic::x86_avx_ptestc_256:
16359 X86CC = X86::COND_B;
16361 case Intrinsic::x86_avx_vtestnzc_ps:
16362 case Intrinsic::x86_avx_vtestnzc_pd:
16363 case Intrinsic::x86_avx_vtestnzc_ps_256:
16364 case Intrinsic::x86_avx_vtestnzc_pd_256:
16365 IsTestPacked = true; // Fallthrough
16366 case Intrinsic::x86_sse41_ptestnzc:
16367 case Intrinsic::x86_avx_ptestnzc_256:
16369 X86CC = X86::COND_A;
16373 SDValue LHS = Op.getOperand(1);
16374 SDValue RHS = Op.getOperand(2);
16375 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16376 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16377 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16378 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16379 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16381 case Intrinsic::x86_avx512_kortestz_w:
16382 case Intrinsic::x86_avx512_kortestc_w: {
16383 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16384 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16385 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16386 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16387 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16388 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16389 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16392 case Intrinsic::x86_sse42_pcmpistria128:
16393 case Intrinsic::x86_sse42_pcmpestria128:
16394 case Intrinsic::x86_sse42_pcmpistric128:
16395 case Intrinsic::x86_sse42_pcmpestric128:
16396 case Intrinsic::x86_sse42_pcmpistrio128:
16397 case Intrinsic::x86_sse42_pcmpestrio128:
16398 case Intrinsic::x86_sse42_pcmpistris128:
16399 case Intrinsic::x86_sse42_pcmpestris128:
16400 case Intrinsic::x86_sse42_pcmpistriz128:
16401 case Intrinsic::x86_sse42_pcmpestriz128: {
16405 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16406 case Intrinsic::x86_sse42_pcmpistria128:
16407 Opcode = X86ISD::PCMPISTRI;
16408 X86CC = X86::COND_A;
16410 case Intrinsic::x86_sse42_pcmpestria128:
16411 Opcode = X86ISD::PCMPESTRI;
16412 X86CC = X86::COND_A;
16414 case Intrinsic::x86_sse42_pcmpistric128:
16415 Opcode = X86ISD::PCMPISTRI;
16416 X86CC = X86::COND_B;
16418 case Intrinsic::x86_sse42_pcmpestric128:
16419 Opcode = X86ISD::PCMPESTRI;
16420 X86CC = X86::COND_B;
16422 case Intrinsic::x86_sse42_pcmpistrio128:
16423 Opcode = X86ISD::PCMPISTRI;
16424 X86CC = X86::COND_O;
16426 case Intrinsic::x86_sse42_pcmpestrio128:
16427 Opcode = X86ISD::PCMPESTRI;
16428 X86CC = X86::COND_O;
16430 case Intrinsic::x86_sse42_pcmpistris128:
16431 Opcode = X86ISD::PCMPISTRI;
16432 X86CC = X86::COND_S;
16434 case Intrinsic::x86_sse42_pcmpestris128:
16435 Opcode = X86ISD::PCMPESTRI;
16436 X86CC = X86::COND_S;
16438 case Intrinsic::x86_sse42_pcmpistriz128:
16439 Opcode = X86ISD::PCMPISTRI;
16440 X86CC = X86::COND_E;
16442 case Intrinsic::x86_sse42_pcmpestriz128:
16443 Opcode = X86ISD::PCMPESTRI;
16444 X86CC = X86::COND_E;
16447 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16448 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16449 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16450 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16451 DAG.getConstant(X86CC, dl, MVT::i8),
16452 SDValue(PCMP.getNode(), 1));
16453 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16456 case Intrinsic::x86_sse42_pcmpistri128:
16457 case Intrinsic::x86_sse42_pcmpestri128: {
16459 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16460 Opcode = X86ISD::PCMPISTRI;
16462 Opcode = X86ISD::PCMPESTRI;
16464 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16465 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16466 return DAG.getNode(Opcode, dl, VTs, NewOps);
16469 case Intrinsic::x86_seh_lsda: {
16470 // Compute the symbol for the LSDA. We know it'll get emitted later.
16471 MachineFunction &MF = DAG.getMachineFunction();
16472 SDValue Op1 = Op.getOperand(1);
16473 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16474 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16475 GlobalValue::getRealLinkageName(Fn->getName()));
16477 // Generate a simple absolute symbol reference. This intrinsic is only
16478 // supported on 32-bit Windows, which isn't PIC.
16479 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16480 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16483 case Intrinsic::x86_seh_recoverfp: {
16484 SDValue FnOp = Op.getOperand(1);
16485 SDValue IncomingFPOp = Op.getOperand(2);
16486 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16487 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16489 report_fatal_error(
16490 "llvm.x86.seh.recoverfp must take a function as the first argument");
16491 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16494 case Intrinsic::localaddress: {
16495 // Returns one of the stack, base, or frame pointer registers, depending on
16496 // which is used to reference local variables.
16497 MachineFunction &MF = DAG.getMachineFunction();
16498 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16500 if (RegInfo->hasBasePointer(MF))
16501 Reg = RegInfo->getBaseRegister();
16502 else // This function handles the SP or FP case.
16503 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16504 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16509 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16510 SDValue Src, SDValue Mask, SDValue Base,
16511 SDValue Index, SDValue ScaleOp, SDValue Chain,
16512 const X86Subtarget * Subtarget) {
16514 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16516 llvm_unreachable("Invalid scale type");
16517 unsigned ScaleVal = C->getZExtValue();
16518 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16519 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16521 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16522 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16523 Index.getSimpleValueType().getVectorNumElements());
16525 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16527 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16529 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16530 Mask.getValueType().getSizeInBits());
16532 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16533 // are extracted by EXTRACT_SUBVECTOR.
16534 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16535 DAG.getBitcast(BitcastVT, Mask),
16536 DAG.getIntPtrConstant(0, dl));
16538 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16539 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16540 SDValue Segment = DAG.getRegister(0, MVT::i32);
16541 if (Src.getOpcode() == ISD::UNDEF)
16542 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16543 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16544 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16545 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16546 return DAG.getMergeValues(RetOps, dl);
16549 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16550 SDValue Src, SDValue Mask, SDValue Base,
16551 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16553 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16555 llvm_unreachable("Invalid scale type");
16556 unsigned ScaleVal = C->getZExtValue();
16557 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16558 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16560 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16561 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16562 SDValue Segment = DAG.getRegister(0, MVT::i32);
16563 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16564 Index.getSimpleValueType().getVectorNumElements());
16566 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16568 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16570 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16571 Mask.getValueType().getSizeInBits());
16573 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16574 // are extracted by EXTRACT_SUBVECTOR.
16575 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16576 DAG.getBitcast(BitcastVT, Mask),
16577 DAG.getIntPtrConstant(0, dl));
16579 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16580 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16581 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16582 return SDValue(Res, 1);
16585 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16586 SDValue Mask, SDValue Base, SDValue Index,
16587 SDValue ScaleOp, SDValue Chain) {
16589 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16590 assert(C && "Invalid scale type");
16591 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16592 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16593 SDValue Segment = DAG.getRegister(0, MVT::i32);
16595 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16597 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16599 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16601 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16602 //SDVTList VTs = DAG.getVTList(MVT::Other);
16603 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16604 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16605 return SDValue(Res, 0);
16608 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16609 // read performance monitor counters (x86_rdpmc).
16610 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16611 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16612 SmallVectorImpl<SDValue> &Results) {
16613 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16614 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16617 // The ECX register is used to select the index of the performance counter
16619 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16621 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16623 // Reads the content of a 64-bit performance counter and returns it in the
16624 // registers EDX:EAX.
16625 if (Subtarget->is64Bit()) {
16626 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16627 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16630 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16631 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16634 Chain = HI.getValue(1);
16636 if (Subtarget->is64Bit()) {
16637 // The EAX register is loaded with the low-order 32 bits. The EDX register
16638 // is loaded with the supported high-order bits of the counter.
16639 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16640 DAG.getConstant(32, DL, MVT::i8));
16641 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16642 Results.push_back(Chain);
16646 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16647 SDValue Ops[] = { LO, HI };
16648 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16649 Results.push_back(Pair);
16650 Results.push_back(Chain);
16653 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16654 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16655 // also used to custom lower READCYCLECOUNTER nodes.
16656 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16657 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16658 SmallVectorImpl<SDValue> &Results) {
16659 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16660 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16663 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16664 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16665 // and the EAX register is loaded with the low-order 32 bits.
16666 if (Subtarget->is64Bit()) {
16667 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16668 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16671 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16672 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16675 SDValue Chain = HI.getValue(1);
16677 if (Opcode == X86ISD::RDTSCP_DAG) {
16678 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16680 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16681 // the ECX register. Add 'ecx' explicitly to the chain.
16682 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16684 // Explicitly store the content of ECX at the location passed in input
16685 // to the 'rdtscp' intrinsic.
16686 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16687 MachinePointerInfo(), false, false, 0);
16690 if (Subtarget->is64Bit()) {
16691 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16692 // the EAX register is loaded with the low-order 32 bits.
16693 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16694 DAG.getConstant(32, DL, MVT::i8));
16695 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16696 Results.push_back(Chain);
16700 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16701 SDValue Ops[] = { LO, HI };
16702 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16703 Results.push_back(Pair);
16704 Results.push_back(Chain);
16707 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16708 SelectionDAG &DAG) {
16709 SmallVector<SDValue, 2> Results;
16711 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16713 return DAG.getMergeValues(Results, DL);
16716 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16717 SelectionDAG &DAG) {
16718 MachineFunction &MF = DAG.getMachineFunction();
16719 const Function *Fn = MF.getFunction();
16721 SDValue Chain = Op.getOperand(0);
16723 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16724 "using llvm.x86.seh.restoreframe requires a frame pointer");
16726 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16727 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16729 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16730 unsigned FrameReg =
16731 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16732 unsigned SPReg = RegInfo->getStackRegister();
16733 unsigned SlotSize = RegInfo->getSlotSize();
16735 // Get incoming EBP.
16736 SDValue IncomingEBP =
16737 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16739 // SP is saved in the first field of every registration node, so load
16740 // [EBP-RegNodeSize] into SP.
16741 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16742 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16743 DAG.getConstant(-RegNodeSize, dl, VT));
16745 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16746 false, VT.getScalarSizeInBits() / 8);
16747 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16749 if (!RegInfo->needsStackRealignment(MF)) {
16750 // Adjust EBP to point back to the original frame position.
16751 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16752 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16754 assert(RegInfo->hasBasePointer(MF) &&
16755 "functions with Win32 EH must use frame or base pointer register");
16757 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16758 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16759 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16761 // Reload the spilled EBP value, now that the stack and base pointers are
16763 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16764 X86FI->setHasSEHFramePtrSave(true);
16765 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16766 X86FI->setSEHFramePtrSaveIndex(FI);
16767 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16768 MachinePointerInfo(), false, false, false,
16769 VT.getScalarSizeInBits() / 8);
16770 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16776 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16777 /// return truncate Store/MaskedStore Node
16778 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16782 SDValue Mask = Op.getOperand(4);
16783 SDValue DataToTruncate = Op.getOperand(3);
16784 SDValue Addr = Op.getOperand(2);
16785 SDValue Chain = Op.getOperand(0);
16787 EVT VT = DataToTruncate.getValueType();
16788 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16789 ElementType, VT.getVectorNumElements());
16791 if (isAllOnes(Mask)) // return just a truncate store
16792 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16793 MachinePointerInfo(), SVT, false, false,
16794 SVT.getScalarSizeInBits()/8);
16796 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16797 MVT::i1, VT.getVectorNumElements());
16798 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16799 Mask.getValueType().getSizeInBits());
16800 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16801 // are extracted by EXTRACT_SUBVECTOR.
16802 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16803 DAG.getBitcast(BitcastVT, Mask),
16804 DAG.getIntPtrConstant(0, dl));
16806 MachineMemOperand *MMO = DAG.getMachineFunction().
16807 getMachineMemOperand(MachinePointerInfo(),
16808 MachineMemOperand::MOStore, SVT.getStoreSize(),
16809 SVT.getScalarSizeInBits()/8);
16811 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16812 VMask, SVT, MMO, true);
16815 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16816 SelectionDAG &DAG) {
16817 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16819 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16821 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16822 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16827 switch(IntrData->Type) {
16829 llvm_unreachable("Unknown Intrinsic Type");
16833 // Emit the node with the right value type.
16834 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16835 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16837 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16838 // Otherwise return the value from Rand, which is always 0, casted to i32.
16839 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16840 DAG.getConstant(1, dl, Op->getValueType(1)),
16841 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16842 SDValue(Result.getNode(), 1) };
16843 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16844 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16847 // Return { result, isValid, chain }.
16848 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16849 SDValue(Result.getNode(), 2));
16852 //gather(v1, mask, index, base, scale);
16853 SDValue Chain = Op.getOperand(0);
16854 SDValue Src = Op.getOperand(2);
16855 SDValue Base = Op.getOperand(3);
16856 SDValue Index = Op.getOperand(4);
16857 SDValue Mask = Op.getOperand(5);
16858 SDValue Scale = Op.getOperand(6);
16859 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16863 //scatter(base, mask, index, v1, scale);
16864 SDValue Chain = Op.getOperand(0);
16865 SDValue Base = Op.getOperand(2);
16866 SDValue Mask = Op.getOperand(3);
16867 SDValue Index = Op.getOperand(4);
16868 SDValue Src = Op.getOperand(5);
16869 SDValue Scale = Op.getOperand(6);
16870 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16874 SDValue Hint = Op.getOperand(6);
16875 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16876 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16877 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16878 SDValue Chain = Op.getOperand(0);
16879 SDValue Mask = Op.getOperand(2);
16880 SDValue Index = Op.getOperand(3);
16881 SDValue Base = Op.getOperand(4);
16882 SDValue Scale = Op.getOperand(5);
16883 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16885 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16887 SmallVector<SDValue, 2> Results;
16888 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16890 return DAG.getMergeValues(Results, dl);
16892 // Read Performance Monitoring Counters.
16894 SmallVector<SDValue, 2> Results;
16895 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16896 return DAG.getMergeValues(Results, dl);
16898 // XTEST intrinsics.
16900 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16901 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16902 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16903 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16905 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16906 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16907 Ret, SDValue(InTrans.getNode(), 1));
16911 SmallVector<SDValue, 2> Results;
16912 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16913 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16914 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16915 DAG.getConstant(-1, dl, MVT::i8));
16916 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16917 Op.getOperand(4), GenCF.getValue(1));
16918 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16919 Op.getOperand(5), MachinePointerInfo(),
16921 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16922 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16924 Results.push_back(SetCC);
16925 Results.push_back(Store);
16926 return DAG.getMergeValues(Results, dl);
16928 case COMPRESS_TO_MEM: {
16930 SDValue Mask = Op.getOperand(4);
16931 SDValue DataToCompress = Op.getOperand(3);
16932 SDValue Addr = Op.getOperand(2);
16933 SDValue Chain = Op.getOperand(0);
16935 EVT VT = DataToCompress.getValueType();
16936 if (isAllOnes(Mask)) // return just a store
16937 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16938 MachinePointerInfo(), false, false,
16939 VT.getScalarSizeInBits()/8);
16941 SDValue Compressed =
16942 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16943 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16944 return DAG.getStore(Chain, dl, Compressed, Addr,
16945 MachinePointerInfo(), false, false,
16946 VT.getScalarSizeInBits()/8);
16948 case TRUNCATE_TO_MEM_VI8:
16949 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16950 case TRUNCATE_TO_MEM_VI16:
16951 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16952 case TRUNCATE_TO_MEM_VI32:
16953 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16954 case EXPAND_FROM_MEM: {
16956 SDValue Mask = Op.getOperand(4);
16957 SDValue PassThru = Op.getOperand(3);
16958 SDValue Addr = Op.getOperand(2);
16959 SDValue Chain = Op.getOperand(0);
16960 EVT VT = Op.getValueType();
16962 if (isAllOnes(Mask)) // return just a load
16963 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16964 false, VT.getScalarSizeInBits()/8);
16966 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16967 false, false, false,
16968 VT.getScalarSizeInBits()/8);
16970 SDValue Results[] = {
16971 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16972 Mask, PassThru, Subtarget, DAG), Chain};
16973 return DAG.getMergeValues(Results, dl);
16978 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16979 SelectionDAG &DAG) const {
16980 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16981 MFI->setReturnAddressIsTaken(true);
16983 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16986 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16988 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16991 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16992 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16993 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16994 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16995 DAG.getNode(ISD::ADD, dl, PtrVT,
16996 FrameAddr, Offset),
16997 MachinePointerInfo(), false, false, false, 0);
17000 // Just load the return address.
17001 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17002 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17003 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17006 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17007 MachineFunction &MF = DAG.getMachineFunction();
17008 MachineFrameInfo *MFI = MF.getFrameInfo();
17009 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17010 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17011 EVT VT = Op.getValueType();
17013 MFI->setFrameAddressIsTaken(true);
17015 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17016 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17017 // is not possible to crawl up the stack without looking at the unwind codes
17019 int FrameAddrIndex = FuncInfo->getFAIndex();
17020 if (!FrameAddrIndex) {
17021 // Set up a frame object for the return address.
17022 unsigned SlotSize = RegInfo->getSlotSize();
17023 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17024 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17025 FuncInfo->setFAIndex(FrameAddrIndex);
17027 return DAG.getFrameIndex(FrameAddrIndex, VT);
17030 unsigned FrameReg =
17031 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17032 SDLoc dl(Op); // FIXME probably not meaningful
17033 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17034 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17035 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17036 "Invalid Frame Register!");
17037 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17039 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17040 MachinePointerInfo(),
17041 false, false, false, 0);
17045 // FIXME? Maybe this could be a TableGen attribute on some registers and
17046 // this table could be generated automatically from RegInfo.
17047 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17048 SelectionDAG &DAG) const {
17049 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17050 const MachineFunction &MF = DAG.getMachineFunction();
17052 unsigned Reg = StringSwitch<unsigned>(RegName)
17053 .Case("esp", X86::ESP)
17054 .Case("rsp", X86::RSP)
17055 .Case("ebp", X86::EBP)
17056 .Case("rbp", X86::RBP)
17059 if (Reg == X86::EBP || Reg == X86::RBP) {
17060 if (!TFI.hasFP(MF))
17061 report_fatal_error("register " + StringRef(RegName) +
17062 " is allocatable: function has no frame pointer");
17065 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17066 unsigned FrameReg =
17067 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17068 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17069 "Invalid Frame Register!");
17077 report_fatal_error("Invalid register name global variable");
17080 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17081 SelectionDAG &DAG) const {
17082 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17083 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17086 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17087 SDValue Chain = Op.getOperand(0);
17088 SDValue Offset = Op.getOperand(1);
17089 SDValue Handler = Op.getOperand(2);
17092 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17093 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17094 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17095 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17096 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17097 "Invalid Frame Register!");
17098 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17099 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17101 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17102 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17104 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17105 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17107 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17109 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17110 DAG.getRegister(StoreAddrReg, PtrVT));
17113 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17114 SelectionDAG &DAG) const {
17116 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17117 DAG.getVTList(MVT::i32, MVT::Other),
17118 Op.getOperand(0), Op.getOperand(1));
17121 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17122 SelectionDAG &DAG) const {
17124 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17125 Op.getOperand(0), Op.getOperand(1));
17128 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17129 return Op.getOperand(0);
17132 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17133 SelectionDAG &DAG) const {
17134 SDValue Root = Op.getOperand(0);
17135 SDValue Trmp = Op.getOperand(1); // trampoline
17136 SDValue FPtr = Op.getOperand(2); // nested function
17137 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17140 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17141 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17143 if (Subtarget->is64Bit()) {
17144 SDValue OutChains[6];
17146 // Large code-model.
17147 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17148 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17150 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17151 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17153 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17155 // Load the pointer to the nested function into R11.
17156 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17157 SDValue Addr = Trmp;
17158 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17159 Addr, MachinePointerInfo(TrmpAddr),
17162 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17163 DAG.getConstant(2, dl, MVT::i64));
17164 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17165 MachinePointerInfo(TrmpAddr, 2),
17168 // Load the 'nest' parameter value into R10.
17169 // R10 is specified in X86CallingConv.td
17170 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17172 DAG.getConstant(10, dl, MVT::i64));
17173 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17174 Addr, MachinePointerInfo(TrmpAddr, 10),
17177 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17178 DAG.getConstant(12, dl, MVT::i64));
17179 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17180 MachinePointerInfo(TrmpAddr, 12),
17183 // Jump to the nested function.
17184 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17185 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17186 DAG.getConstant(20, dl, MVT::i64));
17187 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17188 Addr, MachinePointerInfo(TrmpAddr, 20),
17191 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17192 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17193 DAG.getConstant(22, dl, MVT::i64));
17194 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17195 Addr, MachinePointerInfo(TrmpAddr, 22),
17198 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17200 const Function *Func =
17201 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17202 CallingConv::ID CC = Func->getCallingConv();
17207 llvm_unreachable("Unsupported calling convention");
17208 case CallingConv::C:
17209 case CallingConv::X86_StdCall: {
17210 // Pass 'nest' parameter in ECX.
17211 // Must be kept in sync with X86CallingConv.td
17212 NestReg = X86::ECX;
17214 // Check that ECX wasn't needed by an 'inreg' parameter.
17215 FunctionType *FTy = Func->getFunctionType();
17216 const AttributeSet &Attrs = Func->getAttributes();
17218 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17219 unsigned InRegCount = 0;
17222 for (FunctionType::param_iterator I = FTy->param_begin(),
17223 E = FTy->param_end(); I != E; ++I, ++Idx)
17224 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17225 auto &DL = DAG.getDataLayout();
17226 // FIXME: should only count parameters that are lowered to integers.
17227 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17230 if (InRegCount > 2) {
17231 report_fatal_error("Nest register in use - reduce number of inreg"
17237 case CallingConv::X86_FastCall:
17238 case CallingConv::X86_ThisCall:
17239 case CallingConv::Fast:
17240 // Pass 'nest' parameter in EAX.
17241 // Must be kept in sync with X86CallingConv.td
17242 NestReg = X86::EAX;
17246 SDValue OutChains[4];
17247 SDValue Addr, Disp;
17249 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17250 DAG.getConstant(10, dl, MVT::i32));
17251 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17253 // This is storing the opcode for MOV32ri.
17254 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17255 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17256 OutChains[0] = DAG.getStore(Root, dl,
17257 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17258 Trmp, MachinePointerInfo(TrmpAddr),
17261 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17262 DAG.getConstant(1, dl, MVT::i32));
17263 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17264 MachinePointerInfo(TrmpAddr, 1),
17267 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17268 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17269 DAG.getConstant(5, dl, MVT::i32));
17270 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17271 Addr, MachinePointerInfo(TrmpAddr, 5),
17274 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17275 DAG.getConstant(6, dl, MVT::i32));
17276 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17277 MachinePointerInfo(TrmpAddr, 6),
17280 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17284 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17285 SelectionDAG &DAG) const {
17287 The rounding mode is in bits 11:10 of FPSR, and has the following
17289 00 Round to nearest
17294 FLT_ROUNDS, on the other hand, expects the following:
17301 To perform the conversion, we do:
17302 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17305 MachineFunction &MF = DAG.getMachineFunction();
17306 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17307 unsigned StackAlignment = TFI.getStackAlignment();
17308 MVT VT = Op.getSimpleValueType();
17311 // Save FP Control Word to stack slot
17312 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17313 SDValue StackSlot =
17314 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17316 MachineMemOperand *MMO =
17317 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17318 MachineMemOperand::MOStore, 2, 2);
17320 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17321 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17322 DAG.getVTList(MVT::Other),
17323 Ops, MVT::i16, MMO);
17325 // Load FP Control Word from stack slot
17326 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17327 MachinePointerInfo(), false, false, false, 0);
17329 // Transform as necessary
17331 DAG.getNode(ISD::SRL, DL, MVT::i16,
17332 DAG.getNode(ISD::AND, DL, MVT::i16,
17333 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17334 DAG.getConstant(11, DL, MVT::i8));
17336 DAG.getNode(ISD::SRL, DL, MVT::i16,
17337 DAG.getNode(ISD::AND, DL, MVT::i16,
17338 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17339 DAG.getConstant(9, DL, MVT::i8));
17342 DAG.getNode(ISD::AND, DL, MVT::i16,
17343 DAG.getNode(ISD::ADD, DL, MVT::i16,
17344 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17345 DAG.getConstant(1, DL, MVT::i16)),
17346 DAG.getConstant(3, DL, MVT::i16));
17348 return DAG.getNode((VT.getSizeInBits() < 16 ?
17349 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17352 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17353 MVT VT = Op.getSimpleValueType();
17355 unsigned NumBits = VT.getSizeInBits();
17358 Op = Op.getOperand(0);
17359 if (VT == MVT::i8) {
17360 // Zero extend to i32 since there is not an i8 bsr.
17362 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17365 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17366 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17367 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17369 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17372 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17373 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17376 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17378 // Finally xor with NumBits-1.
17379 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17380 DAG.getConstant(NumBits - 1, dl, OpVT));
17383 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17387 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17388 MVT VT = Op.getSimpleValueType();
17390 unsigned NumBits = VT.getSizeInBits();
17393 Op = Op.getOperand(0);
17394 if (VT == MVT::i8) {
17395 // Zero extend to i32 since there is not an i8 bsr.
17397 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17400 // Issue a bsr (scan bits in reverse).
17401 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17402 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17404 // And xor with NumBits-1.
17405 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17406 DAG.getConstant(NumBits - 1, dl, OpVT));
17409 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17413 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17414 MVT VT = Op.getSimpleValueType();
17415 unsigned NumBits = VT.getScalarSizeInBits();
17418 if (VT.isVector()) {
17419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17421 SDValue N0 = Op.getOperand(0);
17422 SDValue Zero = DAG.getConstant(0, dl, VT);
17424 // lsb(x) = (x & -x)
17425 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17426 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17428 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17429 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17430 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17431 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17432 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17433 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17436 // cttz(x) = ctpop(lsb - 1)
17437 SDValue One = DAG.getConstant(1, dl, VT);
17438 return DAG.getNode(ISD::CTPOP, dl, VT,
17439 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17442 assert(Op.getOpcode() == ISD::CTTZ &&
17443 "Only scalar CTTZ requires custom lowering");
17445 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17446 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17447 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17449 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17452 DAG.getConstant(NumBits, dl, VT),
17453 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17456 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17459 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17460 // ones, and then concatenate the result back.
17461 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17462 MVT VT = Op.getSimpleValueType();
17464 assert(VT.is256BitVector() && VT.isInteger() &&
17465 "Unsupported value type for operation");
17467 unsigned NumElems = VT.getVectorNumElements();
17470 // Extract the LHS vectors
17471 SDValue LHS = Op.getOperand(0);
17472 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17473 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17475 // Extract the RHS vectors
17476 SDValue RHS = Op.getOperand(1);
17477 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17478 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17480 MVT EltVT = VT.getVectorElementType();
17481 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17483 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17484 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17485 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17488 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17489 if (Op.getValueType() == MVT::i1)
17490 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17491 Op.getOperand(0), Op.getOperand(1));
17492 assert(Op.getSimpleValueType().is256BitVector() &&
17493 Op.getSimpleValueType().isInteger() &&
17494 "Only handle AVX 256-bit vector integer operation");
17495 return Lower256IntArith(Op, DAG);
17498 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17499 if (Op.getValueType() == MVT::i1)
17500 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17501 Op.getOperand(0), Op.getOperand(1));
17502 assert(Op.getSimpleValueType().is256BitVector() &&
17503 Op.getSimpleValueType().isInteger() &&
17504 "Only handle AVX 256-bit vector integer operation");
17505 return Lower256IntArith(Op, DAG);
17508 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17509 assert(Op.getSimpleValueType().is256BitVector() &&
17510 Op.getSimpleValueType().isInteger() &&
17511 "Only handle AVX 256-bit vector integer operation");
17512 return Lower256IntArith(Op, DAG);
17515 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17516 SelectionDAG &DAG) {
17518 MVT VT = Op.getSimpleValueType();
17521 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17523 // Decompose 256-bit ops into smaller 128-bit ops.
17524 if (VT.is256BitVector() && !Subtarget->hasInt256())
17525 return Lower256IntArith(Op, DAG);
17527 SDValue A = Op.getOperand(0);
17528 SDValue B = Op.getOperand(1);
17530 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17531 // pairs, multiply and truncate.
17532 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17533 if (Subtarget->hasInt256()) {
17534 if (VT == MVT::v32i8) {
17535 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17536 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17537 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17538 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17539 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17540 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17541 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17542 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17543 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17544 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17547 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17548 return DAG.getNode(
17549 ISD::TRUNCATE, dl, VT,
17550 DAG.getNode(ISD::MUL, dl, ExVT,
17551 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17552 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17555 assert(VT == MVT::v16i8 &&
17556 "Pre-AVX2 support only supports v16i8 multiplication");
17557 MVT ExVT = MVT::v8i16;
17559 // Extract the lo parts and sign extend to i16
17561 if (Subtarget->hasSSE41()) {
17562 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17563 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17565 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17566 -1, 4, -1, 5, -1, 6, -1, 7};
17567 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17568 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17569 ALo = DAG.getBitcast(ExVT, ALo);
17570 BLo = DAG.getBitcast(ExVT, BLo);
17571 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17572 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17575 // Extract the hi parts and sign extend to i16
17577 if (Subtarget->hasSSE41()) {
17578 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17579 -1, -1, -1, -1, -1, -1, -1, -1};
17580 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17581 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17582 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17583 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17585 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17586 -1, 12, -1, 13, -1, 14, -1, 15};
17587 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17588 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17589 AHi = DAG.getBitcast(ExVT, AHi);
17590 BHi = DAG.getBitcast(ExVT, BHi);
17591 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17592 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17595 // Multiply, mask the lower 8bits of the lo/hi results and pack
17596 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17597 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17598 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17599 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17600 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17603 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17604 if (VT == MVT::v4i32) {
17605 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17606 "Should not custom lower when pmuldq is available!");
17608 // Extract the odd parts.
17609 static const int UnpackMask[] = { 1, -1, 3, -1 };
17610 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17611 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17613 // Multiply the even parts.
17614 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17615 // Now multiply odd parts.
17616 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17618 Evens = DAG.getBitcast(VT, Evens);
17619 Odds = DAG.getBitcast(VT, Odds);
17621 // Merge the two vectors back together with a shuffle. This expands into 2
17623 static const int ShufMask[] = { 0, 4, 2, 6 };
17624 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17627 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17628 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17630 // Ahi = psrlqi(a, 32);
17631 // Bhi = psrlqi(b, 32);
17633 // AloBlo = pmuludq(a, b);
17634 // AloBhi = pmuludq(a, Bhi);
17635 // AhiBlo = pmuludq(Ahi, b);
17637 // AloBhi = psllqi(AloBhi, 32);
17638 // AhiBlo = psllqi(AhiBlo, 32);
17639 // return AloBlo + AloBhi + AhiBlo;
17641 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17642 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17644 SDValue AhiBlo = Ahi;
17645 SDValue AloBhi = Bhi;
17646 // Bit cast to 32-bit vectors for MULUDQ
17647 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17648 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17649 A = DAG.getBitcast(MulVT, A);
17650 B = DAG.getBitcast(MulVT, B);
17651 Ahi = DAG.getBitcast(MulVT, Ahi);
17652 Bhi = DAG.getBitcast(MulVT, Bhi);
17654 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17655 // After shifting right const values the result may be all-zero.
17656 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17657 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17658 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17660 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17661 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17662 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17665 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17666 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17669 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17670 assert(Subtarget->isTargetWin64() && "Unexpected target");
17671 EVT VT = Op.getValueType();
17672 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17673 "Unexpected return type for lowering");
17677 switch (Op->getOpcode()) {
17678 default: llvm_unreachable("Unexpected request for libcall!");
17679 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17680 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17681 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17682 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17683 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17684 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17688 SDValue InChain = DAG.getEntryNode();
17690 TargetLowering::ArgListTy Args;
17691 TargetLowering::ArgListEntry Entry;
17692 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17693 EVT ArgVT = Op->getOperand(i).getValueType();
17694 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17695 "Unexpected argument type for lowering");
17696 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17697 Entry.Node = StackPtr;
17698 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17700 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17701 Entry.Ty = PointerType::get(ArgTy,0);
17702 Entry.isSExt = false;
17703 Entry.isZExt = false;
17704 Args.push_back(Entry);
17707 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17708 getPointerTy(DAG.getDataLayout()));
17710 TargetLowering::CallLoweringInfo CLI(DAG);
17711 CLI.setDebugLoc(dl).setChain(InChain)
17712 .setCallee(getLibcallCallingConv(LC),
17713 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17714 Callee, std::move(Args), 0)
17715 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17717 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17718 return DAG.getBitcast(VT, CallInfo.first);
17721 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17722 SelectionDAG &DAG) {
17723 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17724 EVT VT = Op0.getValueType();
17727 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17728 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17730 // PMULxD operations multiply each even value (starting at 0) of LHS with
17731 // the related value of RHS and produce a widen result.
17732 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17733 // => <2 x i64> <ae|cg>
17735 // In other word, to have all the results, we need to perform two PMULxD:
17736 // 1. one with the even values.
17737 // 2. one with the odd values.
17738 // To achieve #2, with need to place the odd values at an even position.
17740 // Place the odd value at an even position (basically, shift all values 1
17741 // step to the left):
17742 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17743 // <a|b|c|d> => <b|undef|d|undef>
17744 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17745 // <e|f|g|h> => <f|undef|h|undef>
17746 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17748 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17750 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17751 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17753 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17754 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17755 // => <2 x i64> <ae|cg>
17756 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17757 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17758 // => <2 x i64> <bf|dh>
17759 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17761 // Shuffle it back into the right order.
17762 SDValue Highs, Lows;
17763 if (VT == MVT::v8i32) {
17764 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17765 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17766 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17767 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17769 const int HighMask[] = {1, 5, 3, 7};
17770 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17771 const int LowMask[] = {0, 4, 2, 6};
17772 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17775 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17776 // unsigned multiply.
17777 if (IsSigned && !Subtarget->hasSSE41()) {
17778 SDValue ShAmt = DAG.getConstant(
17780 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17781 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17782 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17783 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17784 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17786 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17787 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17790 // The first result of MUL_LOHI is actually the low value, followed by the
17792 SDValue Ops[] = {Lows, Highs};
17793 return DAG.getMergeValues(Ops, dl);
17796 // Return true if the required (according to Opcode) shift-imm form is natively
17797 // supported by the Subtarget
17798 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17800 if (VT.getScalarSizeInBits() < 16)
17803 if (VT.is512BitVector() &&
17804 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17807 bool LShift = VT.is128BitVector() ||
17808 (VT.is256BitVector() && Subtarget->hasInt256());
17810 bool AShift = LShift && (Subtarget->hasVLX() ||
17811 (VT != MVT::v2i64 && VT != MVT::v4i64));
17812 return (Opcode == ISD::SRA) ? AShift : LShift;
17815 // The shift amount is a variable, but it is the same for all vector lanes.
17816 // These instructions are defined together with shift-immediate.
17818 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17820 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17823 // Return true if the required (according to Opcode) variable-shift form is
17824 // natively supported by the Subtarget
17825 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17828 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17831 // vXi16 supported only on AVX-512, BWI
17832 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17835 if (VT.is512BitVector() || Subtarget->hasVLX())
17838 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17839 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17840 return (Opcode == ISD::SRA) ? AShift : LShift;
17843 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17844 const X86Subtarget *Subtarget) {
17845 MVT VT = Op.getSimpleValueType();
17847 SDValue R = Op.getOperand(0);
17848 SDValue Amt = Op.getOperand(1);
17850 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17851 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17853 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17854 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17855 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17856 SDValue Ex = DAG.getBitcast(ExVT, R);
17858 if (ShiftAmt >= 32) {
17859 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17861 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17862 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17863 ShiftAmt - 32, DAG);
17864 if (VT == MVT::v2i64)
17865 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17866 if (VT == MVT::v4i64)
17867 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17868 {9, 1, 11, 3, 13, 5, 15, 7});
17870 // SRA upper i32, SHL whole i64 and select lower i32.
17871 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17874 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17875 Lower = DAG.getBitcast(ExVT, Lower);
17876 if (VT == MVT::v2i64)
17877 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17878 if (VT == MVT::v4i64)
17879 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17880 {8, 1, 10, 3, 12, 5, 14, 7});
17882 return DAG.getBitcast(VT, Ex);
17885 // Optimize shl/srl/sra with constant shift amount.
17886 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17887 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17888 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17890 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17891 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17893 // i64 SRA needs to be performed as partial shifts.
17894 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17895 Op.getOpcode() == ISD::SRA)
17896 return ArithmeticShiftRight64(ShiftAmt);
17898 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17899 unsigned NumElts = VT.getVectorNumElements();
17900 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17902 if (Op.getOpcode() == ISD::SHL) {
17903 // Simple i8 add case
17905 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17907 // Make a large shift.
17908 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17910 SHL = DAG.getBitcast(VT, SHL);
17911 // Zero out the rightmost bits.
17912 SmallVector<SDValue, 32> V(
17913 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17914 return DAG.getNode(ISD::AND, dl, VT, SHL,
17915 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17917 if (Op.getOpcode() == ISD::SRL) {
17918 // Make a large shift.
17919 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17921 SRL = DAG.getBitcast(VT, SRL);
17922 // Zero out the leftmost bits.
17923 SmallVector<SDValue, 32> V(
17924 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17925 return DAG.getNode(ISD::AND, dl, VT, SRL,
17926 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17928 if (Op.getOpcode() == ISD::SRA) {
17929 if (ShiftAmt == 7) {
17930 // ashr(R, 7) === cmp_slt(R, 0)
17931 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17932 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17935 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17936 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17937 SmallVector<SDValue, 32> V(NumElts,
17938 DAG.getConstant(128 >> ShiftAmt, dl,
17940 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17941 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17942 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17945 llvm_unreachable("Unknown shift opcode.");
17950 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17951 if (!Subtarget->is64Bit() &&
17952 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17954 // Peek through any splat that was introduced for i64 shift vectorization.
17955 int SplatIndex = -1;
17956 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17957 if (SVN->isSplat()) {
17958 SplatIndex = SVN->getSplatIndex();
17959 Amt = Amt.getOperand(0);
17960 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17961 "Splat shuffle referencing second operand");
17964 if (Amt.getOpcode() != ISD::BITCAST ||
17965 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17968 Amt = Amt.getOperand(0);
17969 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17970 VT.getVectorNumElements();
17971 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17972 uint64_t ShiftAmt = 0;
17973 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17974 for (unsigned i = 0; i != Ratio; ++i) {
17975 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17979 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17982 // Check remaining shift amounts (if not a splat).
17983 if (SplatIndex < 0) {
17984 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17985 uint64_t ShAmt = 0;
17986 for (unsigned j = 0; j != Ratio; ++j) {
17987 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17991 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17993 if (ShAmt != ShiftAmt)
17998 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17999 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18001 if (Op.getOpcode() == ISD::SRA)
18002 return ArithmeticShiftRight64(ShiftAmt);
18008 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18009 const X86Subtarget* Subtarget) {
18010 MVT VT = Op.getSimpleValueType();
18012 SDValue R = Op.getOperand(0);
18013 SDValue Amt = Op.getOperand(1);
18015 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18016 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18018 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18019 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18021 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18023 EVT EltVT = VT.getVectorElementType();
18025 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18026 // Check if this build_vector node is doing a splat.
18027 // If so, then set BaseShAmt equal to the splat value.
18028 BaseShAmt = BV->getSplatValue();
18029 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18030 BaseShAmt = SDValue();
18032 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18033 Amt = Amt.getOperand(0);
18035 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18036 if (SVN && SVN->isSplat()) {
18037 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18038 SDValue InVec = Amt.getOperand(0);
18039 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18040 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18041 "Unexpected shuffle index found!");
18042 BaseShAmt = InVec.getOperand(SplatIdx);
18043 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18044 if (ConstantSDNode *C =
18045 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18046 if (C->getZExtValue() == SplatIdx)
18047 BaseShAmt = InVec.getOperand(1);
18052 // Avoid introducing an extract element from a shuffle.
18053 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18054 DAG.getIntPtrConstant(SplatIdx, dl));
18058 if (BaseShAmt.getNode()) {
18059 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18060 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18061 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18062 else if (EltVT.bitsLT(MVT::i32))
18063 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18065 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18069 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18070 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18071 Amt.getOpcode() == ISD::BITCAST &&
18072 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18073 Amt = Amt.getOperand(0);
18074 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18075 VT.getVectorNumElements();
18076 std::vector<SDValue> Vals(Ratio);
18077 for (unsigned i = 0; i != Ratio; ++i)
18078 Vals[i] = Amt.getOperand(i);
18079 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18080 for (unsigned j = 0; j != Ratio; ++j)
18081 if (Vals[j] != Amt.getOperand(i + j))
18085 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18086 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18091 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18092 SelectionDAG &DAG) {
18093 MVT VT = Op.getSimpleValueType();
18095 SDValue R = Op.getOperand(0);
18096 SDValue Amt = Op.getOperand(1);
18098 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18099 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18101 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18104 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18107 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18110 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18111 // shifts per-lane and then shuffle the partial results back together.
18112 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18113 // Splat the shift amounts so the scalar shifts above will catch it.
18114 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18115 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18116 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18117 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18118 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18121 // i64 vector arithmetic shift can be emulated with the transform:
18122 // M = lshr(SIGN_BIT, Amt)
18123 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18124 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18125 Op.getOpcode() == ISD::SRA) {
18126 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18127 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18128 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18129 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18130 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18134 // If possible, lower this packed shift into a vector multiply instead of
18135 // expanding it into a sequence of scalar shifts.
18136 // Do this only if the vector shift count is a constant build_vector.
18137 if (Op.getOpcode() == ISD::SHL &&
18138 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18139 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18140 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18141 SmallVector<SDValue, 8> Elts;
18142 EVT SVT = VT.getScalarType();
18143 unsigned SVTBits = SVT.getSizeInBits();
18144 const APInt &One = APInt(SVTBits, 1);
18145 unsigned NumElems = VT.getVectorNumElements();
18147 for (unsigned i=0; i !=NumElems; ++i) {
18148 SDValue Op = Amt->getOperand(i);
18149 if (Op->getOpcode() == ISD::UNDEF) {
18150 Elts.push_back(Op);
18154 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18155 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18156 uint64_t ShAmt = C.getZExtValue();
18157 if (ShAmt >= SVTBits) {
18158 Elts.push_back(DAG.getUNDEF(SVT));
18161 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18163 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18164 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18167 // Lower SHL with variable shift amount.
18168 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18169 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18171 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18172 DAG.getConstant(0x3f800000U, dl, VT));
18173 Op = DAG.getBitcast(MVT::v4f32, Op);
18174 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18175 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18178 // If possible, lower this shift as a sequence of two shifts by
18179 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18181 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18183 // Could be rewritten as:
18184 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18186 // The advantage is that the two shifts from the example would be
18187 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18188 // the vector shift into four scalar shifts plus four pairs of vector
18190 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18191 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18192 unsigned TargetOpcode = X86ISD::MOVSS;
18193 bool CanBeSimplified;
18194 // The splat value for the first packed shift (the 'X' from the example).
18195 SDValue Amt1 = Amt->getOperand(0);
18196 // The splat value for the second packed shift (the 'Y' from the example).
18197 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18198 Amt->getOperand(2);
18200 // See if it is possible to replace this node with a sequence of
18201 // two shifts followed by a MOVSS/MOVSD
18202 if (VT == MVT::v4i32) {
18203 // Check if it is legal to use a MOVSS.
18204 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18205 Amt2 == Amt->getOperand(3);
18206 if (!CanBeSimplified) {
18207 // Otherwise, check if we can still simplify this node using a MOVSD.
18208 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18209 Amt->getOperand(2) == Amt->getOperand(3);
18210 TargetOpcode = X86ISD::MOVSD;
18211 Amt2 = Amt->getOperand(2);
18214 // Do similar checks for the case where the machine value type
18216 CanBeSimplified = Amt1 == Amt->getOperand(1);
18217 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18218 CanBeSimplified = Amt2 == Amt->getOperand(i);
18220 if (!CanBeSimplified) {
18221 TargetOpcode = X86ISD::MOVSD;
18222 CanBeSimplified = true;
18223 Amt2 = Amt->getOperand(4);
18224 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18225 CanBeSimplified = Amt1 == Amt->getOperand(i);
18226 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18227 CanBeSimplified = Amt2 == Amt->getOperand(j);
18231 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18232 isa<ConstantSDNode>(Amt2)) {
18233 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18234 EVT CastVT = MVT::v4i32;
18236 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18237 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18239 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18240 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18241 if (TargetOpcode == X86ISD::MOVSD)
18242 CastVT = MVT::v2i64;
18243 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18244 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18245 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18247 return DAG.getBitcast(VT, Result);
18251 // v4i32 Non Uniform Shifts.
18252 // If the shift amount is constant we can shift each lane using the SSE2
18253 // immediate shifts, else we need to zero-extend each lane to the lower i64
18254 // and shift using the SSE2 variable shifts.
18255 // The separate results can then be blended together.
18256 if (VT == MVT::v4i32) {
18257 unsigned Opc = Op.getOpcode();
18258 SDValue Amt0, Amt1, Amt2, Amt3;
18259 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18260 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18261 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18262 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18263 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18265 // ISD::SHL is handled above but we include it here for completeness.
18268 llvm_unreachable("Unknown target vector shift node");
18270 Opc = X86ISD::VSHL;
18273 Opc = X86ISD::VSRL;
18276 Opc = X86ISD::VSRA;
18279 // The SSE2 shifts use the lower i64 as the same shift amount for
18280 // all lanes and the upper i64 is ignored. These shuffle masks
18281 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18282 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18283 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18284 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18285 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18286 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18289 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18290 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18291 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18292 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18293 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18294 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18295 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18298 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
18299 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18300 unsigned ShiftOpcode = Op->getOpcode();
18302 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18303 // On SSE41 targets we make use of the fact that VSELECT lowers
18304 // to PBLENDVB which selects bytes based just on the sign bit.
18305 if (Subtarget->hasSSE41()) {
18306 V0 = DAG.getBitcast(VT, V0);
18307 V1 = DAG.getBitcast(VT, V1);
18308 Sel = DAG.getBitcast(VT, Sel);
18309 return DAG.getBitcast(SelVT,
18310 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18312 // On pre-SSE41 targets we test for the sign bit by comparing to
18313 // zero - a negative value will set all bits of the lanes to true
18314 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18315 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18316 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18317 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18320 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18321 // We can safely do this using i16 shifts as we're only interested in
18322 // the 3 lower bits of each byte.
18323 Amt = DAG.getBitcast(ExtVT, Amt);
18324 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18325 Amt = DAG.getBitcast(VT, Amt);
18327 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18328 // r = VSELECT(r, shift(r, 4), a);
18330 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18331 R = SignBitSelect(VT, Amt, M, R);
18334 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18336 // r = VSELECT(r, shift(r, 2), a);
18337 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18338 R = SignBitSelect(VT, Amt, M, R);
18341 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18343 // return VSELECT(r, shift(r, 1), a);
18344 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18345 R = SignBitSelect(VT, Amt, M, R);
18349 if (Op->getOpcode() == ISD::SRA) {
18350 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18351 // so we can correctly sign extend. We don't care what happens to the
18353 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18354 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18355 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18356 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18357 ALo = DAG.getBitcast(ExtVT, ALo);
18358 AHi = DAG.getBitcast(ExtVT, AHi);
18359 RLo = DAG.getBitcast(ExtVT, RLo);
18360 RHi = DAG.getBitcast(ExtVT, RHi);
18362 // r = VSELECT(r, shift(r, 4), a);
18363 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18364 DAG.getConstant(4, dl, ExtVT));
18365 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18366 DAG.getConstant(4, dl, ExtVT));
18367 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18368 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18371 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18372 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18374 // r = VSELECT(r, shift(r, 2), a);
18375 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18376 DAG.getConstant(2, dl, ExtVT));
18377 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18378 DAG.getConstant(2, dl, ExtVT));
18379 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18380 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18383 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18384 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18386 // r = VSELECT(r, shift(r, 1), a);
18387 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18388 DAG.getConstant(1, dl, ExtVT));
18389 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18390 DAG.getConstant(1, dl, ExtVT));
18391 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18392 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18394 // Logical shift the result back to the lower byte, leaving a zero upper
18396 // meaning that we can safely pack with PACKUSWB.
18398 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18400 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18401 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18405 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18406 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18407 // solution better.
18408 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18409 MVT ExtVT = MVT::v8i32;
18411 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18412 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18413 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18414 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18415 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18418 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
18419 MVT ExtVT = MVT::v8i32;
18420 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18421 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18422 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18423 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18424 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18425 ALo = DAG.getBitcast(ExtVT, ALo);
18426 AHi = DAG.getBitcast(ExtVT, AHi);
18427 RLo = DAG.getBitcast(ExtVT, RLo);
18428 RHi = DAG.getBitcast(ExtVT, RHi);
18429 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18430 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18431 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18432 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18433 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18436 if (VT == MVT::v8i16) {
18437 unsigned ShiftOpcode = Op->getOpcode();
18439 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18440 // On SSE41 targets we make use of the fact that VSELECT lowers
18441 // to PBLENDVB which selects bytes based just on the sign bit.
18442 if (Subtarget->hasSSE41()) {
18443 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18444 V0 = DAG.getBitcast(ExtVT, V0);
18445 V1 = DAG.getBitcast(ExtVT, V1);
18446 Sel = DAG.getBitcast(ExtVT, Sel);
18447 return DAG.getBitcast(
18448 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18450 // On pre-SSE41 targets we splat the sign bit - a negative value will
18451 // set all bits of the lanes to true and VSELECT uses that in
18452 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18454 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18455 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18458 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18459 if (Subtarget->hasSSE41()) {
18460 // On SSE41 targets we need to replicate the shift mask in both
18461 // bytes for PBLENDVB.
18464 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18465 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18467 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18470 // r = VSELECT(r, shift(r, 8), a);
18471 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18472 R = SignBitSelect(Amt, M, R);
18475 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18477 // r = VSELECT(r, shift(r, 4), a);
18478 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18479 R = SignBitSelect(Amt, M, R);
18482 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18484 // r = VSELECT(r, shift(r, 2), a);
18485 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18486 R = SignBitSelect(Amt, M, R);
18489 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18491 // return VSELECT(r, shift(r, 1), a);
18492 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18493 R = SignBitSelect(Amt, M, R);
18497 // Decompose 256-bit shifts into smaller 128-bit shifts.
18498 if (VT.is256BitVector()) {
18499 unsigned NumElems = VT.getVectorNumElements();
18500 MVT EltVT = VT.getVectorElementType();
18501 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18503 // Extract the two vectors
18504 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18505 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18507 // Recreate the shift amount vectors
18508 SDValue Amt1, Amt2;
18509 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18510 // Constant shift amount
18511 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18512 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18513 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18515 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18516 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18518 // Variable shift amount
18519 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18520 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18523 // Issue new vector shifts for the smaller types
18524 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18525 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18527 // Concatenate the result back
18528 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18534 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18535 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18536 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18537 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18538 // has only one use.
18539 SDNode *N = Op.getNode();
18540 SDValue LHS = N->getOperand(0);
18541 SDValue RHS = N->getOperand(1);
18542 unsigned BaseOp = 0;
18545 switch (Op.getOpcode()) {
18546 default: llvm_unreachable("Unknown ovf instruction!");
18548 // A subtract of one will be selected as a INC. Note that INC doesn't
18549 // set CF, so we can't do this for UADDO.
18550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18552 BaseOp = X86ISD::INC;
18553 Cond = X86::COND_O;
18556 BaseOp = X86ISD::ADD;
18557 Cond = X86::COND_O;
18560 BaseOp = X86ISD::ADD;
18561 Cond = X86::COND_B;
18564 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18565 // set CF, so we can't do this for USUBO.
18566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18568 BaseOp = X86ISD::DEC;
18569 Cond = X86::COND_O;
18572 BaseOp = X86ISD::SUB;
18573 Cond = X86::COND_O;
18576 BaseOp = X86ISD::SUB;
18577 Cond = X86::COND_B;
18580 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18581 Cond = X86::COND_O;
18583 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18584 if (N->getValueType(0) == MVT::i8) {
18585 BaseOp = X86ISD::UMUL8;
18586 Cond = X86::COND_O;
18589 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18591 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18594 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18595 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18596 SDValue(Sum.getNode(), 2));
18598 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18602 // Also sets EFLAGS.
18603 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18604 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18607 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18608 DAG.getConstant(Cond, DL, MVT::i32),
18609 SDValue(Sum.getNode(), 1));
18611 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18614 /// Returns true if the operand type is exactly twice the native width, and
18615 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18616 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18617 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18618 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18619 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18622 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18623 else if (OpWidth == 128)
18624 return Subtarget->hasCmpxchg16b();
18629 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18630 return needsCmpXchgNb(SI->getValueOperand()->getType());
18633 // Note: this turns large loads into lock cmpxchg8b/16b.
18634 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18635 TargetLowering::AtomicExpansionKind
18636 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18637 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18638 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18639 : AtomicExpansionKind::None;
18642 TargetLowering::AtomicExpansionKind
18643 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18644 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18645 Type *MemType = AI->getType();
18647 // If the operand is too big, we must see if cmpxchg8/16b is available
18648 // and default to library calls otherwise.
18649 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18650 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18651 : AtomicExpansionKind::None;
18654 AtomicRMWInst::BinOp Op = AI->getOperation();
18657 llvm_unreachable("Unknown atomic operation");
18658 case AtomicRMWInst::Xchg:
18659 case AtomicRMWInst::Add:
18660 case AtomicRMWInst::Sub:
18661 // It's better to use xadd, xsub or xchg for these in all cases.
18662 return AtomicExpansionKind::None;
18663 case AtomicRMWInst::Or:
18664 case AtomicRMWInst::And:
18665 case AtomicRMWInst::Xor:
18666 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18667 // prefix to a normal instruction for these operations.
18668 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18669 : AtomicExpansionKind::None;
18670 case AtomicRMWInst::Nand:
18671 case AtomicRMWInst::Max:
18672 case AtomicRMWInst::Min:
18673 case AtomicRMWInst::UMax:
18674 case AtomicRMWInst::UMin:
18675 // These always require a non-trivial set of data operations on x86. We must
18676 // use a cmpxchg loop.
18677 return AtomicExpansionKind::CmpXChg;
18681 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18682 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18683 // no-sse2). There isn't any reason to disable it if the target processor
18685 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18689 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18690 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18691 Type *MemType = AI->getType();
18692 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18693 // there is no benefit in turning such RMWs into loads, and it is actually
18694 // harmful as it introduces a mfence.
18695 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18698 auto Builder = IRBuilder<>(AI);
18699 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18700 auto SynchScope = AI->getSynchScope();
18701 // We must restrict the ordering to avoid generating loads with Release or
18702 // ReleaseAcquire orderings.
18703 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18704 auto Ptr = AI->getPointerOperand();
18706 // Before the load we need a fence. Here is an example lifted from
18707 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18710 // x.store(1, relaxed);
18711 // r1 = y.fetch_add(0, release);
18713 // y.fetch_add(42, acquire);
18714 // r2 = x.load(relaxed);
18715 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18716 // lowered to just a load without a fence. A mfence flushes the store buffer,
18717 // making the optimization clearly correct.
18718 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18719 // otherwise, we might be able to be more aggressive on relaxed idempotent
18720 // rmw. In practice, they do not look useful, so we don't try to be
18721 // especially clever.
18722 if (SynchScope == SingleThread)
18723 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18724 // the IR level, so we must wrap it in an intrinsic.
18727 if (!hasMFENCE(*Subtarget))
18728 // FIXME: it might make sense to use a locked operation here but on a
18729 // different cache-line to prevent cache-line bouncing. In practice it
18730 // is probably a small win, and x86 processors without mfence are rare
18731 // enough that we do not bother.
18735 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18736 Builder.CreateCall(MFence, {});
18738 // Finally we can emit the atomic load.
18739 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18740 AI->getType()->getPrimitiveSizeInBits());
18741 Loaded->setAtomic(Order, SynchScope);
18742 AI->replaceAllUsesWith(Loaded);
18743 AI->eraseFromParent();
18747 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18748 SelectionDAG &DAG) {
18750 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18751 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18752 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18753 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18755 // The only fence that needs an instruction is a sequentially-consistent
18756 // cross-thread fence.
18757 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18758 if (hasMFENCE(*Subtarget))
18759 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18761 SDValue Chain = Op.getOperand(0);
18762 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18764 DAG.getRegister(X86::ESP, MVT::i32), // Base
18765 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18766 DAG.getRegister(0, MVT::i32), // Index
18767 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18768 DAG.getRegister(0, MVT::i32), // Segment.
18772 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18773 return SDValue(Res, 0);
18776 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18777 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18780 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18781 SelectionDAG &DAG) {
18782 MVT T = Op.getSimpleValueType();
18786 switch(T.SimpleTy) {
18787 default: llvm_unreachable("Invalid value type!");
18788 case MVT::i8: Reg = X86::AL; size = 1; break;
18789 case MVT::i16: Reg = X86::AX; size = 2; break;
18790 case MVT::i32: Reg = X86::EAX; size = 4; break;
18792 assert(Subtarget->is64Bit() && "Node not type legal!");
18793 Reg = X86::RAX; size = 8;
18796 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18797 Op.getOperand(2), SDValue());
18798 SDValue Ops[] = { cpIn.getValue(0),
18801 DAG.getTargetConstant(size, DL, MVT::i8),
18802 cpIn.getValue(1) };
18803 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18804 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18805 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18809 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18810 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18811 MVT::i32, cpOut.getValue(2));
18812 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18813 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18816 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18817 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18818 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18822 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18823 SelectionDAG &DAG) {
18824 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18825 MVT DstVT = Op.getSimpleValueType();
18827 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18828 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18829 if (DstVT != MVT::f64)
18830 // This conversion needs to be expanded.
18833 SDValue InVec = Op->getOperand(0);
18835 unsigned NumElts = SrcVT.getVectorNumElements();
18836 EVT SVT = SrcVT.getVectorElementType();
18838 // Widen the vector in input in the case of MVT::v2i32.
18839 // Example: from MVT::v2i32 to MVT::v4i32.
18840 SmallVector<SDValue, 16> Elts;
18841 for (unsigned i = 0, e = NumElts; i != e; ++i)
18842 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18843 DAG.getIntPtrConstant(i, dl)));
18845 // Explicitly mark the extra elements as Undef.
18846 Elts.append(NumElts, DAG.getUNDEF(SVT));
18848 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18849 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18850 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18851 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18852 DAG.getIntPtrConstant(0, dl));
18855 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18856 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18857 assert((DstVT == MVT::i64 ||
18858 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18859 "Unexpected custom BITCAST");
18860 // i64 <=> MMX conversions are Legal.
18861 if (SrcVT==MVT::i64 && DstVT.isVector())
18863 if (DstVT==MVT::i64 && SrcVT.isVector())
18865 // MMX <=> MMX conversions are Legal.
18866 if (SrcVT.isVector() && DstVT.isVector())
18868 // All other conversions need to be expanded.
18872 /// Compute the horizontal sum of bytes in V for the elements of VT.
18874 /// Requires V to be a byte vector and VT to be an integer vector type with
18875 /// wider elements than V's type. The width of the elements of VT determines
18876 /// how many bytes of V are summed horizontally to produce each element of the
18878 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18879 const X86Subtarget *Subtarget,
18880 SelectionDAG &DAG) {
18882 MVT ByteVecVT = V.getSimpleValueType();
18883 MVT EltVT = VT.getVectorElementType();
18884 int NumElts = VT.getVectorNumElements();
18885 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18886 "Expected value to have byte element type.");
18887 assert(EltVT != MVT::i8 &&
18888 "Horizontal byte sum only makes sense for wider elements!");
18889 unsigned VecSize = VT.getSizeInBits();
18890 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18892 // PSADBW instruction horizontally add all bytes and leave the result in i64
18893 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18894 if (EltVT == MVT::i64) {
18895 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18896 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18897 return DAG.getBitcast(VT, V);
18900 if (EltVT == MVT::i32) {
18901 // We unpack the low half and high half into i32s interleaved with zeros so
18902 // that we can use PSADBW to horizontally sum them. The most useful part of
18903 // this is that it lines up the results of two PSADBW instructions to be
18904 // two v2i64 vectors which concatenated are the 4 population counts. We can
18905 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18906 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18907 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18908 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18910 // Do the horizontal sums into two v2i64s.
18911 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18912 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18913 DAG.getBitcast(ByteVecVT, Low), Zeros);
18914 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18915 DAG.getBitcast(ByteVecVT, High), Zeros);
18917 // Merge them together.
18918 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18919 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18920 DAG.getBitcast(ShortVecVT, Low),
18921 DAG.getBitcast(ShortVecVT, High));
18923 return DAG.getBitcast(VT, V);
18926 // The only element type left is i16.
18927 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18929 // To obtain pop count for each i16 element starting from the pop count for
18930 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18931 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18932 // directly supported.
18933 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18934 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18935 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18936 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18937 DAG.getBitcast(ByteVecVT, V));
18938 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18941 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18942 const X86Subtarget *Subtarget,
18943 SelectionDAG &DAG) {
18944 MVT VT = Op.getSimpleValueType();
18945 MVT EltVT = VT.getVectorElementType();
18946 unsigned VecSize = VT.getSizeInBits();
18948 // Implement a lookup table in register by using an algorithm based on:
18949 // http://wm.ite.pl/articles/sse-popcount.html
18951 // The general idea is that every lower byte nibble in the input vector is an
18952 // index into a in-register pre-computed pop count table. We then split up the
18953 // input vector in two new ones: (1) a vector with only the shifted-right
18954 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18955 // masked out higher ones) for each byte. PSHUB is used separately with both
18956 // to index the in-register table. Next, both are added and the result is a
18957 // i8 vector where each element contains the pop count for input byte.
18959 // To obtain the pop count for elements != i8, we follow up with the same
18960 // approach and use additional tricks as described below.
18962 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18963 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18964 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18965 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18967 int NumByteElts = VecSize / 8;
18968 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18969 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18970 SmallVector<SDValue, 16> LUTVec;
18971 for (int i = 0; i < NumByteElts; ++i)
18972 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18973 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18974 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18975 DAG.getConstant(0x0F, DL, MVT::i8));
18976 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18979 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18980 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18981 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18984 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18986 // The input vector is used as the shuffle mask that index elements into the
18987 // LUT. After counting low and high nibbles, add the vector to obtain the
18988 // final pop count per i8 element.
18989 SDValue HighPopCnt =
18990 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18991 SDValue LowPopCnt =
18992 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18993 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18995 if (EltVT == MVT::i8)
18998 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19001 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19002 const X86Subtarget *Subtarget,
19003 SelectionDAG &DAG) {
19004 MVT VT = Op.getSimpleValueType();
19005 assert(VT.is128BitVector() &&
19006 "Only 128-bit vector bitmath lowering supported.");
19008 int VecSize = VT.getSizeInBits();
19009 MVT EltVT = VT.getVectorElementType();
19010 int Len = EltVT.getSizeInBits();
19012 // This is the vectorized version of the "best" algorithm from
19013 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19014 // with a minor tweak to use a series of adds + shifts instead of vector
19015 // multiplications. Implemented for all integer vector types. We only use
19016 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19017 // much faster, even faster than using native popcnt instructions.
19019 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19020 MVT VT = V.getSimpleValueType();
19021 SmallVector<SDValue, 32> Shifters(
19022 VT.getVectorNumElements(),
19023 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19024 return DAG.getNode(OpCode, DL, VT, V,
19025 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19027 auto GetMask = [&](SDValue V, APInt Mask) {
19028 MVT VT = V.getSimpleValueType();
19029 SmallVector<SDValue, 32> Masks(
19030 VT.getVectorNumElements(),
19031 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19032 return DAG.getNode(ISD::AND, DL, VT, V,
19033 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19036 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19037 // x86, so set the SRL type to have elements at least i16 wide. This is
19038 // correct because all of our SRLs are followed immediately by a mask anyways
19039 // that handles any bits that sneak into the high bits of the byte elements.
19040 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19044 // v = v - ((v >> 1) & 0x55555555...)
19046 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19047 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19048 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19050 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19051 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19052 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19053 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19054 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19056 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19057 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19058 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19059 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19061 // At this point, V contains the byte-wise population count, and we are
19062 // merely doing a horizontal sum if necessary to get the wider element
19064 if (EltVT == MVT::i8)
19067 return LowerHorizontalByteSum(
19068 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19072 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19073 SelectionDAG &DAG) {
19074 MVT VT = Op.getSimpleValueType();
19075 // FIXME: Need to add AVX-512 support here!
19076 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19077 "Unknown CTPOP type to handle");
19078 SDLoc DL(Op.getNode());
19079 SDValue Op0 = Op.getOperand(0);
19081 if (!Subtarget->hasSSSE3()) {
19082 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19083 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19084 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19087 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19088 unsigned NumElems = VT.getVectorNumElements();
19090 // Extract each 128-bit vector, compute pop count and concat the result.
19091 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19092 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19094 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19095 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19096 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19099 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19102 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19103 SelectionDAG &DAG) {
19104 assert(Op.getValueType().isVector() &&
19105 "We only do custom lowering for vector population count.");
19106 return LowerVectorCTPOP(Op, Subtarget, DAG);
19109 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19110 SDNode *Node = Op.getNode();
19112 EVT T = Node->getValueType(0);
19113 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19114 DAG.getConstant(0, dl, T), Node->getOperand(2));
19115 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19116 cast<AtomicSDNode>(Node)->getMemoryVT(),
19117 Node->getOperand(0),
19118 Node->getOperand(1), negOp,
19119 cast<AtomicSDNode>(Node)->getMemOperand(),
19120 cast<AtomicSDNode>(Node)->getOrdering(),
19121 cast<AtomicSDNode>(Node)->getSynchScope());
19124 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19125 SDNode *Node = Op.getNode();
19127 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19129 // Convert seq_cst store -> xchg
19130 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19131 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19132 // (The only way to get a 16-byte store is cmpxchg16b)
19133 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19134 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19135 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19136 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19137 cast<AtomicSDNode>(Node)->getMemoryVT(),
19138 Node->getOperand(0),
19139 Node->getOperand(1), Node->getOperand(2),
19140 cast<AtomicSDNode>(Node)->getMemOperand(),
19141 cast<AtomicSDNode>(Node)->getOrdering(),
19142 cast<AtomicSDNode>(Node)->getSynchScope());
19143 return Swap.getValue(1);
19145 // Other atomic stores have a simple pattern.
19149 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19150 EVT VT = Op.getNode()->getSimpleValueType(0);
19152 // Let legalize expand this if it isn't a legal type yet.
19153 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19156 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19159 bool ExtraOp = false;
19160 switch (Op.getOpcode()) {
19161 default: llvm_unreachable("Invalid code");
19162 case ISD::ADDC: Opc = X86ISD::ADD; break;
19163 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19164 case ISD::SUBC: Opc = X86ISD::SUB; break;
19165 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19169 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19171 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19172 Op.getOperand(1), Op.getOperand(2));
19175 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19176 SelectionDAG &DAG) {
19177 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19179 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19180 // which returns the values as { float, float } (in XMM0) or
19181 // { double, double } (which is returned in XMM0, XMM1).
19183 SDValue Arg = Op.getOperand(0);
19184 EVT ArgVT = Arg.getValueType();
19185 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19187 TargetLowering::ArgListTy Args;
19188 TargetLowering::ArgListEntry Entry;
19192 Entry.isSExt = false;
19193 Entry.isZExt = false;
19194 Args.push_back(Entry);
19196 bool isF64 = ArgVT == MVT::f64;
19197 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19198 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19199 // the results are returned via SRet in memory.
19200 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19203 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19205 Type *RetTy = isF64
19206 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19207 : (Type*)VectorType::get(ArgTy, 4);
19209 TargetLowering::CallLoweringInfo CLI(DAG);
19210 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19211 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19213 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19216 // Returned in xmm0 and xmm1.
19217 return CallResult.first;
19219 // Returned in bits 0:31 and 32:64 xmm0.
19220 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19221 CallResult.first, DAG.getIntPtrConstant(0, dl));
19222 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19223 CallResult.first, DAG.getIntPtrConstant(1, dl));
19224 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19225 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19228 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19229 SelectionDAG &DAG) {
19230 assert(Subtarget->hasAVX512() &&
19231 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19233 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19234 EVT VT = N->getValue().getValueType();
19235 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19238 // X86 scatter kills mask register, so its type should be added to
19239 // the list of return values
19240 if (N->getNumValues() == 1) {
19241 SDValue Index = N->getIndex();
19242 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19243 !Index.getValueType().is512BitVector())
19244 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19246 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19247 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19248 N->getOperand(3), Index };
19250 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19251 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19252 return SDValue(NewScatter.getNode(), 0);
19257 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19258 SelectionDAG &DAG) {
19259 assert(Subtarget->hasAVX512() &&
19260 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19262 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19263 EVT VT = Op.getValueType();
19264 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19267 SDValue Index = N->getIndex();
19268 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19269 !Index.getValueType().is512BitVector()) {
19270 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19271 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19272 N->getOperand(3), Index };
19273 DAG.UpdateNodeOperands(N, Ops);
19278 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19279 SelectionDAG &DAG) const {
19280 // TODO: Eventually, the lowering of these nodes should be informed by or
19281 // deferred to the GC strategy for the function in which they appear. For
19282 // now, however, they must be lowered to something. Since they are logically
19283 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19284 // require special handling for these nodes), lower them as literal NOOPs for
19286 SmallVector<SDValue, 2> Ops;
19288 Ops.push_back(Op.getOperand(0));
19289 if (Op->getGluedNode())
19290 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19293 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19294 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19299 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19300 SelectionDAG &DAG) const {
19301 // TODO: Eventually, the lowering of these nodes should be informed by or
19302 // deferred to the GC strategy for the function in which they appear. For
19303 // now, however, they must be lowered to something. Since they are logically
19304 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19305 // require special handling for these nodes), lower them as literal NOOPs for
19307 SmallVector<SDValue, 2> Ops;
19309 Ops.push_back(Op.getOperand(0));
19310 if (Op->getGluedNode())
19311 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19314 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19315 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19320 /// LowerOperation - Provide custom lowering hooks for some operations.
19322 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19323 switch (Op.getOpcode()) {
19324 default: llvm_unreachable("Should not custom lower this!");
19325 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19326 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19327 return LowerCMP_SWAP(Op, Subtarget, DAG);
19328 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19329 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19330 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19331 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19332 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19333 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19334 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19335 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19336 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19337 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19338 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19339 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19340 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19341 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19342 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19343 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19344 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19345 case ISD::SHL_PARTS:
19346 case ISD::SRA_PARTS:
19347 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19348 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19349 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19350 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19351 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19352 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19353 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19354 case ISD::SIGN_EXTEND_VECTOR_INREG:
19355 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19356 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19357 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19358 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19359 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19361 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19362 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19363 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19364 case ISD::SETCC: return LowerSETCC(Op, DAG);
19365 case ISD::SELECT: return LowerSELECT(Op, DAG);
19366 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19367 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19368 case ISD::VASTART: return LowerVASTART(Op, DAG);
19369 case ISD::VAARG: return LowerVAARG(Op, DAG);
19370 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19371 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19372 case ISD::INTRINSIC_VOID:
19373 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19374 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19375 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19376 case ISD::FRAME_TO_ARGS_OFFSET:
19377 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19378 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19379 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19380 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19381 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19382 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19383 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19384 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19385 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19386 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19388 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19389 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19390 case ISD::UMUL_LOHI:
19391 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19394 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19400 case ISD::UMULO: return LowerXALUO(Op, DAG);
19401 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19402 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19406 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19407 case ISD::ADD: return LowerADD(Op, DAG);
19408 case ISD::SUB: return LowerSUB(Op, DAG);
19412 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19413 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19414 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19415 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19416 case ISD::GC_TRANSITION_START:
19417 return LowerGC_TRANSITION_START(Op, DAG);
19418 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19422 /// ReplaceNodeResults - Replace a node with an illegal result type
19423 /// with a new node built out of custom code.
19424 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19425 SmallVectorImpl<SDValue>&Results,
19426 SelectionDAG &DAG) const {
19428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19429 switch (N->getOpcode()) {
19431 llvm_unreachable("Do not know how to custom type legalize this operation!");
19432 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19433 case X86ISD::FMINC:
19435 case X86ISD::FMAXC:
19436 case X86ISD::FMAX: {
19437 EVT VT = N->getValueType(0);
19438 if (VT != MVT::v2f32)
19439 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19440 SDValue UNDEF = DAG.getUNDEF(VT);
19441 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19442 N->getOperand(0), UNDEF);
19443 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19444 N->getOperand(1), UNDEF);
19445 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19448 case ISD::SIGN_EXTEND_INREG:
19453 // We don't want to expand or promote these.
19460 case ISD::UDIVREM: {
19461 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19462 Results.push_back(V);
19465 case ISD::FP_TO_SINT:
19466 case ISD::FP_TO_UINT: {
19467 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19469 std::pair<SDValue,SDValue> Vals =
19470 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19471 SDValue FIST = Vals.first, StackSlot = Vals.second;
19472 if (FIST.getNode()) {
19473 EVT VT = N->getValueType(0);
19474 // Return a load from the stack slot.
19475 if (StackSlot.getNode())
19476 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19477 MachinePointerInfo(),
19478 false, false, false, 0));
19480 Results.push_back(FIST);
19484 case ISD::UINT_TO_FP: {
19485 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19486 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19487 N->getValueType(0) != MVT::v2f32)
19489 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19491 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19493 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19494 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19495 DAG.getBitcast(MVT::v2i64, VBias));
19496 Or = DAG.getBitcast(MVT::v2f64, Or);
19497 // TODO: Are there any fast-math-flags to propagate here?
19498 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19499 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19502 case ISD::FP_ROUND: {
19503 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19505 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19506 Results.push_back(V);
19509 case ISD::FP_EXTEND: {
19510 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19511 // No other ValueType for FP_EXTEND should reach this point.
19512 assert(N->getValueType(0) == MVT::v2f32 &&
19513 "Do not know how to legalize this Node");
19516 case ISD::INTRINSIC_W_CHAIN: {
19517 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19519 default : llvm_unreachable("Do not know how to custom type "
19520 "legalize this intrinsic operation!");
19521 case Intrinsic::x86_rdtsc:
19522 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19524 case Intrinsic::x86_rdtscp:
19525 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19527 case Intrinsic::x86_rdpmc:
19528 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19531 case ISD::READCYCLECOUNTER: {
19532 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19535 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19536 EVT T = N->getValueType(0);
19537 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19538 bool Regs64bit = T == MVT::i128;
19539 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19540 SDValue cpInL, cpInH;
19541 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19542 DAG.getConstant(0, dl, HalfT));
19543 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19544 DAG.getConstant(1, dl, HalfT));
19545 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19546 Regs64bit ? X86::RAX : X86::EAX,
19548 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19549 Regs64bit ? X86::RDX : X86::EDX,
19550 cpInH, cpInL.getValue(1));
19551 SDValue swapInL, swapInH;
19552 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19553 DAG.getConstant(0, dl, HalfT));
19554 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19555 DAG.getConstant(1, dl, HalfT));
19556 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19557 Regs64bit ? X86::RBX : X86::EBX,
19558 swapInL, cpInH.getValue(1));
19559 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19560 Regs64bit ? X86::RCX : X86::ECX,
19561 swapInH, swapInL.getValue(1));
19562 SDValue Ops[] = { swapInH.getValue(0),
19564 swapInH.getValue(1) };
19565 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19566 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19567 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19568 X86ISD::LCMPXCHG8_DAG;
19569 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19570 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19571 Regs64bit ? X86::RAX : X86::EAX,
19572 HalfT, Result.getValue(1));
19573 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19574 Regs64bit ? X86::RDX : X86::EDX,
19575 HalfT, cpOutL.getValue(2));
19576 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19578 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19579 MVT::i32, cpOutH.getValue(2));
19581 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19582 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19583 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19585 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19586 Results.push_back(Success);
19587 Results.push_back(EFLAGS.getValue(1));
19590 case ISD::ATOMIC_SWAP:
19591 case ISD::ATOMIC_LOAD_ADD:
19592 case ISD::ATOMIC_LOAD_SUB:
19593 case ISD::ATOMIC_LOAD_AND:
19594 case ISD::ATOMIC_LOAD_OR:
19595 case ISD::ATOMIC_LOAD_XOR:
19596 case ISD::ATOMIC_LOAD_NAND:
19597 case ISD::ATOMIC_LOAD_MIN:
19598 case ISD::ATOMIC_LOAD_MAX:
19599 case ISD::ATOMIC_LOAD_UMIN:
19600 case ISD::ATOMIC_LOAD_UMAX:
19601 case ISD::ATOMIC_LOAD: {
19602 // Delegate to generic TypeLegalization. Situations we can really handle
19603 // should have already been dealt with by AtomicExpandPass.cpp.
19606 case ISD::BITCAST: {
19607 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19608 EVT DstVT = N->getValueType(0);
19609 EVT SrcVT = N->getOperand(0)->getValueType(0);
19611 if (SrcVT != MVT::f64 ||
19612 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19615 unsigned NumElts = DstVT.getVectorNumElements();
19616 EVT SVT = DstVT.getVectorElementType();
19617 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19618 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19619 MVT::v2f64, N->getOperand(0));
19620 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19622 if (ExperimentalVectorWideningLegalization) {
19623 // If we are legalizing vectors by widening, we already have the desired
19624 // legal vector type, just return it.
19625 Results.push_back(ToVecInt);
19629 SmallVector<SDValue, 8> Elts;
19630 for (unsigned i = 0, e = NumElts; i != e; ++i)
19631 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19632 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19634 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19639 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19640 switch ((X86ISD::NodeType)Opcode) {
19641 case X86ISD::FIRST_NUMBER: break;
19642 case X86ISD::BSF: return "X86ISD::BSF";
19643 case X86ISD::BSR: return "X86ISD::BSR";
19644 case X86ISD::SHLD: return "X86ISD::SHLD";
19645 case X86ISD::SHRD: return "X86ISD::SHRD";
19646 case X86ISD::FAND: return "X86ISD::FAND";
19647 case X86ISD::FANDN: return "X86ISD::FANDN";
19648 case X86ISD::FOR: return "X86ISD::FOR";
19649 case X86ISD::FXOR: return "X86ISD::FXOR";
19650 case X86ISD::FILD: return "X86ISD::FILD";
19651 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19652 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19653 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19654 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19655 case X86ISD::FLD: return "X86ISD::FLD";
19656 case X86ISD::FST: return "X86ISD::FST";
19657 case X86ISD::CALL: return "X86ISD::CALL";
19658 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19659 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19660 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19661 case X86ISD::BT: return "X86ISD::BT";
19662 case X86ISD::CMP: return "X86ISD::CMP";
19663 case X86ISD::COMI: return "X86ISD::COMI";
19664 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19665 case X86ISD::CMPM: return "X86ISD::CMPM";
19666 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19667 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19668 case X86ISD::SETCC: return "X86ISD::SETCC";
19669 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19670 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19671 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19672 case X86ISD::CMOV: return "X86ISD::CMOV";
19673 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19674 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19675 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19676 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19677 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19678 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19679 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19680 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19681 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19682 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19683 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19684 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19685 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19686 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19687 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19688 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19689 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19690 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19691 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19692 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19693 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19694 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19695 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19696 case X86ISD::HADD: return "X86ISD::HADD";
19697 case X86ISD::HSUB: return "X86ISD::HSUB";
19698 case X86ISD::FHADD: return "X86ISD::FHADD";
19699 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19700 case X86ISD::ABS: return "X86ISD::ABS";
19701 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19702 case X86ISD::FMAX: return "X86ISD::FMAX";
19703 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19704 case X86ISD::FMIN: return "X86ISD::FMIN";
19705 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19706 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19707 case X86ISD::FMINC: return "X86ISD::FMINC";
19708 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19709 case X86ISD::FRCP: return "X86ISD::FRCP";
19710 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19711 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19712 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19713 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19714 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19715 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19716 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19717 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19718 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19719 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19720 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19721 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19722 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19723 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19724 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19725 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19726 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19727 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19728 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19729 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19730 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19731 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19732 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19733 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19734 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19735 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19736 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19737 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19738 case X86ISD::VSHL: return "X86ISD::VSHL";
19739 case X86ISD::VSRL: return "X86ISD::VSRL";
19740 case X86ISD::VSRA: return "X86ISD::VSRA";
19741 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19742 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19743 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19744 case X86ISD::CMPP: return "X86ISD::CMPP";
19745 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19746 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19747 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19748 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19749 case X86ISD::ADD: return "X86ISD::ADD";
19750 case X86ISD::SUB: return "X86ISD::SUB";
19751 case X86ISD::ADC: return "X86ISD::ADC";
19752 case X86ISD::SBB: return "X86ISD::SBB";
19753 case X86ISD::SMUL: return "X86ISD::SMUL";
19754 case X86ISD::UMUL: return "X86ISD::UMUL";
19755 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19756 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19757 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19758 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19759 case X86ISD::INC: return "X86ISD::INC";
19760 case X86ISD::DEC: return "X86ISD::DEC";
19761 case X86ISD::OR: return "X86ISD::OR";
19762 case X86ISD::XOR: return "X86ISD::XOR";
19763 case X86ISD::AND: return "X86ISD::AND";
19764 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19765 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19766 case X86ISD::PTEST: return "X86ISD::PTEST";
19767 case X86ISD::TESTP: return "X86ISD::TESTP";
19768 case X86ISD::TESTM: return "X86ISD::TESTM";
19769 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19770 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19771 case X86ISD::KTEST: return "X86ISD::KTEST";
19772 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19773 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19774 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19775 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19776 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19777 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19778 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19779 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19780 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19781 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19782 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19783 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19784 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19785 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19786 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19787 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19788 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19789 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19790 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19791 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19792 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19793 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19794 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19795 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19796 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19797 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19798 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19799 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19800 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19801 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19802 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19803 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19804 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19805 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19806 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19807 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19808 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19809 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19810 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19811 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19812 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19813 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19814 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19815 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19816 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19817 case X86ISD::SAHF: return "X86ISD::SAHF";
19818 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19819 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19820 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19821 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19822 case X86ISD::FMADD: return "X86ISD::FMADD";
19823 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19824 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19825 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19826 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19827 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19828 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19829 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19830 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19831 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19832 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19833 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19834 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19835 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19836 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19837 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19838 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19839 case X86ISD::XTEST: return "X86ISD::XTEST";
19840 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19841 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19842 case X86ISD::SELECT: return "X86ISD::SELECT";
19843 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19844 case X86ISD::RCP28: return "X86ISD::RCP28";
19845 case X86ISD::EXP2: return "X86ISD::EXP2";
19846 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19847 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19848 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19849 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19850 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19851 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19852 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19853 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19854 case X86ISD::ADDS: return "X86ISD::ADDS";
19855 case X86ISD::SUBS: return "X86ISD::SUBS";
19856 case X86ISD::AVG: return "X86ISD::AVG";
19857 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19858 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19859 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19860 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19861 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19862 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
19867 // isLegalAddressingMode - Return true if the addressing mode represented
19868 // by AM is legal for this target, for a load/store of the specified type.
19869 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19870 const AddrMode &AM, Type *Ty,
19871 unsigned AS) const {
19872 // X86 supports extremely general addressing modes.
19873 CodeModel::Model M = getTargetMachine().getCodeModel();
19874 Reloc::Model R = getTargetMachine().getRelocationModel();
19876 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19877 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19882 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19884 // If a reference to this global requires an extra load, we can't fold it.
19885 if (isGlobalStubReference(GVFlags))
19888 // If BaseGV requires a register for the PIC base, we cannot also have a
19889 // BaseReg specified.
19890 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19893 // If lower 4G is not available, then we must use rip-relative addressing.
19894 if ((M != CodeModel::Small || R != Reloc::Static) &&
19895 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19899 switch (AM.Scale) {
19905 // These scales always work.
19910 // These scales are formed with basereg+scalereg. Only accept if there is
19915 default: // Other stuff never works.
19922 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19923 unsigned Bits = Ty->getScalarSizeInBits();
19925 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19926 // particularly cheaper than those without.
19930 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19931 // variable shifts just as cheap as scalar ones.
19932 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19935 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19936 // fully general vector.
19940 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19941 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19943 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19944 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19945 return NumBits1 > NumBits2;
19948 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19949 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19952 if (!isTypeLegal(EVT::getEVT(Ty1)))
19955 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19957 // Assuming the caller doesn't have a zeroext or signext return parameter,
19958 // truncation all the way down to i1 is valid.
19962 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19963 return isInt<32>(Imm);
19966 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19967 // Can also use sub to handle negated immediates.
19968 return isInt<32>(Imm);
19971 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19972 if (!VT1.isInteger() || !VT2.isInteger())
19974 unsigned NumBits1 = VT1.getSizeInBits();
19975 unsigned NumBits2 = VT2.getSizeInBits();
19976 return NumBits1 > NumBits2;
19979 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19980 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19981 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19984 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19985 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19986 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19989 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19990 EVT VT1 = Val.getValueType();
19991 if (isZExtFree(VT1, VT2))
19994 if (Val.getOpcode() != ISD::LOAD)
19997 if (!VT1.isSimple() || !VT1.isInteger() ||
19998 !VT2.isSimple() || !VT2.isInteger())
20001 switch (VT1.getSimpleVT().SimpleTy) {
20006 // X86 has 8, 16, and 32-bit zero-extending loads.
20013 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20016 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20017 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20020 VT = VT.getScalarType();
20022 if (!VT.isSimple())
20025 switch (VT.getSimpleVT().SimpleTy) {
20036 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20037 // i16 instructions are longer (0x66 prefix) and potentially slower.
20038 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20041 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20042 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20043 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20044 /// are assumed to be legal.
20046 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20048 if (!VT.isSimple())
20051 // Not for i1 vectors
20052 if (VT.getScalarType() == MVT::i1)
20055 // Very little shuffling can be done for 64-bit vectors right now.
20056 if (VT.getSizeInBits() == 64)
20059 // We only care that the types being shuffled are legal. The lowering can
20060 // handle any possible shuffle mask that results.
20061 return isTypeLegal(VT.getSimpleVT());
20065 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20067 // Just delegate to the generic legality, clear masks aren't special.
20068 return isShuffleMaskLegal(Mask, VT);
20071 //===----------------------------------------------------------------------===//
20072 // X86 Scheduler Hooks
20073 //===----------------------------------------------------------------------===//
20075 /// Utility function to emit xbegin specifying the start of an RTM region.
20076 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20077 const TargetInstrInfo *TII) {
20078 DebugLoc DL = MI->getDebugLoc();
20080 const BasicBlock *BB = MBB->getBasicBlock();
20081 MachineFunction::iterator I = MBB;
20084 // For the v = xbegin(), we generate
20095 MachineBasicBlock *thisMBB = MBB;
20096 MachineFunction *MF = MBB->getParent();
20097 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20098 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20099 MF->insert(I, mainMBB);
20100 MF->insert(I, sinkMBB);
20102 // Transfer the remainder of BB and its successor edges to sinkMBB.
20103 sinkMBB->splice(sinkMBB->begin(), MBB,
20104 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20105 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20109 // # fallthrough to mainMBB
20110 // # abortion to sinkMBB
20111 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20112 thisMBB->addSuccessor(mainMBB);
20113 thisMBB->addSuccessor(sinkMBB);
20117 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20118 mainMBB->addSuccessor(sinkMBB);
20121 // EAX is live into the sinkMBB
20122 sinkMBB->addLiveIn(X86::EAX);
20123 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20124 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20127 MI->eraseFromParent();
20131 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20132 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20133 // in the .td file.
20134 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20135 const TargetInstrInfo *TII) {
20137 switch (MI->getOpcode()) {
20138 default: llvm_unreachable("illegal opcode!");
20139 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20140 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20141 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20142 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20143 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20144 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20145 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20146 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20149 DebugLoc dl = MI->getDebugLoc();
20150 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20152 unsigned NumArgs = MI->getNumOperands();
20153 for (unsigned i = 1; i < NumArgs; ++i) {
20154 MachineOperand &Op = MI->getOperand(i);
20155 if (!(Op.isReg() && Op.isImplicit()))
20156 MIB.addOperand(Op);
20158 if (MI->hasOneMemOperand())
20159 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20161 BuildMI(*BB, MI, dl,
20162 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20163 .addReg(X86::XMM0);
20165 MI->eraseFromParent();
20169 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20170 // defs in an instruction pattern
20171 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20172 const TargetInstrInfo *TII) {
20174 switch (MI->getOpcode()) {
20175 default: llvm_unreachable("illegal opcode!");
20176 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20177 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20178 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20179 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20180 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20181 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20182 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20183 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20186 DebugLoc dl = MI->getDebugLoc();
20187 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20189 unsigned NumArgs = MI->getNumOperands(); // remove the results
20190 for (unsigned i = 1; i < NumArgs; ++i) {
20191 MachineOperand &Op = MI->getOperand(i);
20192 if (!(Op.isReg() && Op.isImplicit()))
20193 MIB.addOperand(Op);
20195 if (MI->hasOneMemOperand())
20196 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20198 BuildMI(*BB, MI, dl,
20199 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20202 MI->eraseFromParent();
20206 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20207 const X86Subtarget *Subtarget) {
20208 DebugLoc dl = MI->getDebugLoc();
20209 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20210 // Address into RAX/EAX, other two args into ECX, EDX.
20211 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20212 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20213 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20214 for (int i = 0; i < X86::AddrNumOperands; ++i)
20215 MIB.addOperand(MI->getOperand(i));
20217 unsigned ValOps = X86::AddrNumOperands;
20218 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20219 .addReg(MI->getOperand(ValOps).getReg());
20220 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20221 .addReg(MI->getOperand(ValOps+1).getReg());
20223 // The instruction doesn't actually take any operands though.
20224 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20226 MI->eraseFromParent(); // The pseudo is gone now.
20230 MachineBasicBlock *
20231 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20232 MachineBasicBlock *MBB) const {
20233 // Emit va_arg instruction on X86-64.
20235 // Operands to this pseudo-instruction:
20236 // 0 ) Output : destination address (reg)
20237 // 1-5) Input : va_list address (addr, i64mem)
20238 // 6 ) ArgSize : Size (in bytes) of vararg type
20239 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20240 // 8 ) Align : Alignment of type
20241 // 9 ) EFLAGS (implicit-def)
20243 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20244 static_assert(X86::AddrNumOperands == 5,
20245 "VAARG_64 assumes 5 address operands");
20247 unsigned DestReg = MI->getOperand(0).getReg();
20248 MachineOperand &Base = MI->getOperand(1);
20249 MachineOperand &Scale = MI->getOperand(2);
20250 MachineOperand &Index = MI->getOperand(3);
20251 MachineOperand &Disp = MI->getOperand(4);
20252 MachineOperand &Segment = MI->getOperand(5);
20253 unsigned ArgSize = MI->getOperand(6).getImm();
20254 unsigned ArgMode = MI->getOperand(7).getImm();
20255 unsigned Align = MI->getOperand(8).getImm();
20257 // Memory Reference
20258 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20259 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20260 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20262 // Machine Information
20263 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20264 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20265 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20266 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20267 DebugLoc DL = MI->getDebugLoc();
20269 // struct va_list {
20272 // i64 overflow_area (address)
20273 // i64 reg_save_area (address)
20275 // sizeof(va_list) = 24
20276 // alignment(va_list) = 8
20278 unsigned TotalNumIntRegs = 6;
20279 unsigned TotalNumXMMRegs = 8;
20280 bool UseGPOffset = (ArgMode == 1);
20281 bool UseFPOffset = (ArgMode == 2);
20282 unsigned MaxOffset = TotalNumIntRegs * 8 +
20283 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20285 /* Align ArgSize to a multiple of 8 */
20286 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20287 bool NeedsAlign = (Align > 8);
20289 MachineBasicBlock *thisMBB = MBB;
20290 MachineBasicBlock *overflowMBB;
20291 MachineBasicBlock *offsetMBB;
20292 MachineBasicBlock *endMBB;
20294 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20295 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20296 unsigned OffsetReg = 0;
20298 if (!UseGPOffset && !UseFPOffset) {
20299 // If we only pull from the overflow region, we don't create a branch.
20300 // We don't need to alter control flow.
20301 OffsetDestReg = 0; // unused
20302 OverflowDestReg = DestReg;
20304 offsetMBB = nullptr;
20305 overflowMBB = thisMBB;
20308 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20309 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20310 // If not, pull from overflow_area. (branch to overflowMBB)
20315 // offsetMBB overflowMBB
20320 // Registers for the PHI in endMBB
20321 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20322 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20324 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20325 MachineFunction *MF = MBB->getParent();
20326 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20327 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20328 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20330 MachineFunction::iterator MBBIter = MBB;
20333 // Insert the new basic blocks
20334 MF->insert(MBBIter, offsetMBB);
20335 MF->insert(MBBIter, overflowMBB);
20336 MF->insert(MBBIter, endMBB);
20338 // Transfer the remainder of MBB and its successor edges to endMBB.
20339 endMBB->splice(endMBB->begin(), thisMBB,
20340 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20341 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20343 // Make offsetMBB and overflowMBB successors of thisMBB
20344 thisMBB->addSuccessor(offsetMBB);
20345 thisMBB->addSuccessor(overflowMBB);
20347 // endMBB is a successor of both offsetMBB and overflowMBB
20348 offsetMBB->addSuccessor(endMBB);
20349 overflowMBB->addSuccessor(endMBB);
20351 // Load the offset value into a register
20352 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20353 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20357 .addDisp(Disp, UseFPOffset ? 4 : 0)
20358 .addOperand(Segment)
20359 .setMemRefs(MMOBegin, MMOEnd);
20361 // Check if there is enough room left to pull this argument.
20362 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20364 .addImm(MaxOffset + 8 - ArgSizeA8);
20366 // Branch to "overflowMBB" if offset >= max
20367 // Fall through to "offsetMBB" otherwise
20368 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20369 .addMBB(overflowMBB);
20372 // In offsetMBB, emit code to use the reg_save_area.
20374 assert(OffsetReg != 0);
20376 // Read the reg_save_area address.
20377 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20378 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20383 .addOperand(Segment)
20384 .setMemRefs(MMOBegin, MMOEnd);
20386 // Zero-extend the offset
20387 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20388 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20391 .addImm(X86::sub_32bit);
20393 // Add the offset to the reg_save_area to get the final address.
20394 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20395 .addReg(OffsetReg64)
20396 .addReg(RegSaveReg);
20398 // Compute the offset for the next argument
20399 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20400 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20402 .addImm(UseFPOffset ? 16 : 8);
20404 // Store it back into the va_list.
20405 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20409 .addDisp(Disp, UseFPOffset ? 4 : 0)
20410 .addOperand(Segment)
20411 .addReg(NextOffsetReg)
20412 .setMemRefs(MMOBegin, MMOEnd);
20415 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20420 // Emit code to use overflow area
20423 // Load the overflow_area address into a register.
20424 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20425 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20430 .addOperand(Segment)
20431 .setMemRefs(MMOBegin, MMOEnd);
20433 // If we need to align it, do so. Otherwise, just copy the address
20434 // to OverflowDestReg.
20436 // Align the overflow address
20437 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20438 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20440 // aligned_addr = (addr + (align-1)) & ~(align-1)
20441 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20442 .addReg(OverflowAddrReg)
20445 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20447 .addImm(~(uint64_t)(Align-1));
20449 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20450 .addReg(OverflowAddrReg);
20453 // Compute the next overflow address after this argument.
20454 // (the overflow address should be kept 8-byte aligned)
20455 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20456 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20457 .addReg(OverflowDestReg)
20458 .addImm(ArgSizeA8);
20460 // Store the new overflow address.
20461 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20466 .addOperand(Segment)
20467 .addReg(NextAddrReg)
20468 .setMemRefs(MMOBegin, MMOEnd);
20470 // If we branched, emit the PHI to the front of endMBB.
20472 BuildMI(*endMBB, endMBB->begin(), DL,
20473 TII->get(X86::PHI), DestReg)
20474 .addReg(OffsetDestReg).addMBB(offsetMBB)
20475 .addReg(OverflowDestReg).addMBB(overflowMBB);
20478 // Erase the pseudo instruction
20479 MI->eraseFromParent();
20484 MachineBasicBlock *
20485 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20487 MachineBasicBlock *MBB) const {
20488 // Emit code to save XMM registers to the stack. The ABI says that the
20489 // number of registers to save is given in %al, so it's theoretically
20490 // possible to do an indirect jump trick to avoid saving all of them,
20491 // however this code takes a simpler approach and just executes all
20492 // of the stores if %al is non-zero. It's less code, and it's probably
20493 // easier on the hardware branch predictor, and stores aren't all that
20494 // expensive anyway.
20496 // Create the new basic blocks. One block contains all the XMM stores,
20497 // and one block is the final destination regardless of whether any
20498 // stores were performed.
20499 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20500 MachineFunction *F = MBB->getParent();
20501 MachineFunction::iterator MBBIter = MBB;
20503 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20504 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20505 F->insert(MBBIter, XMMSaveMBB);
20506 F->insert(MBBIter, EndMBB);
20508 // Transfer the remainder of MBB and its successor edges to EndMBB.
20509 EndMBB->splice(EndMBB->begin(), MBB,
20510 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20511 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20513 // The original block will now fall through to the XMM save block.
20514 MBB->addSuccessor(XMMSaveMBB);
20515 // The XMMSaveMBB will fall through to the end block.
20516 XMMSaveMBB->addSuccessor(EndMBB);
20518 // Now add the instructions.
20519 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20520 DebugLoc DL = MI->getDebugLoc();
20522 unsigned CountReg = MI->getOperand(0).getReg();
20523 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20524 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20526 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20527 // If %al is 0, branch around the XMM save block.
20528 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20529 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20530 MBB->addSuccessor(EndMBB);
20533 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20534 // that was just emitted, but clearly shouldn't be "saved".
20535 assert((MI->getNumOperands() <= 3 ||
20536 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20537 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20538 && "Expected last argument to be EFLAGS");
20539 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20540 // In the XMM save block, save all the XMM argument registers.
20541 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20542 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20543 MachineMemOperand *MMO = F->getMachineMemOperand(
20544 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20545 MachineMemOperand::MOStore,
20546 /*Size=*/16, /*Align=*/16);
20547 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20548 .addFrameIndex(RegSaveFrameIndex)
20549 .addImm(/*Scale=*/1)
20550 .addReg(/*IndexReg=*/0)
20551 .addImm(/*Disp=*/Offset)
20552 .addReg(/*Segment=*/0)
20553 .addReg(MI->getOperand(i).getReg())
20554 .addMemOperand(MMO);
20557 MI->eraseFromParent(); // The pseudo instruction is gone now.
20562 // The EFLAGS operand of SelectItr might be missing a kill marker
20563 // because there were multiple uses of EFLAGS, and ISel didn't know
20564 // which to mark. Figure out whether SelectItr should have had a
20565 // kill marker, and set it if it should. Returns the correct kill
20567 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20568 MachineBasicBlock* BB,
20569 const TargetRegisterInfo* TRI) {
20570 // Scan forward through BB for a use/def of EFLAGS.
20571 MachineBasicBlock::iterator miI(std::next(SelectItr));
20572 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20573 const MachineInstr& mi = *miI;
20574 if (mi.readsRegister(X86::EFLAGS))
20576 if (mi.definesRegister(X86::EFLAGS))
20577 break; // Should have kill-flag - update below.
20580 // If we hit the end of the block, check whether EFLAGS is live into a
20582 if (miI == BB->end()) {
20583 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20584 sEnd = BB->succ_end();
20585 sItr != sEnd; ++sItr) {
20586 MachineBasicBlock* succ = *sItr;
20587 if (succ->isLiveIn(X86::EFLAGS))
20592 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20593 // out. SelectMI should have a kill flag on EFLAGS.
20594 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20598 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20599 // together with other CMOV pseudo-opcodes into a single basic-block with
20600 // conditional jump around it.
20601 static bool isCMOVPseudo(MachineInstr *MI) {
20602 switch (MI->getOpcode()) {
20603 case X86::CMOV_FR32:
20604 case X86::CMOV_FR64:
20605 case X86::CMOV_GR8:
20606 case X86::CMOV_GR16:
20607 case X86::CMOV_GR32:
20608 case X86::CMOV_RFP32:
20609 case X86::CMOV_RFP64:
20610 case X86::CMOV_RFP80:
20611 case X86::CMOV_V2F64:
20612 case X86::CMOV_V2I64:
20613 case X86::CMOV_V4F32:
20614 case X86::CMOV_V4F64:
20615 case X86::CMOV_V4I64:
20616 case X86::CMOV_V16F32:
20617 case X86::CMOV_V8F32:
20618 case X86::CMOV_V8F64:
20619 case X86::CMOV_V8I64:
20620 case X86::CMOV_V8I1:
20621 case X86::CMOV_V16I1:
20622 case X86::CMOV_V32I1:
20623 case X86::CMOV_V64I1:
20631 MachineBasicBlock *
20632 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20633 MachineBasicBlock *BB) const {
20634 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20635 DebugLoc DL = MI->getDebugLoc();
20637 // To "insert" a SELECT_CC instruction, we actually have to insert the
20638 // diamond control-flow pattern. The incoming instruction knows the
20639 // destination vreg to set, the condition code register to branch on, the
20640 // true/false values to select between, and a branch opcode to use.
20641 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20642 MachineFunction::iterator It = BB;
20648 // cmpTY ccX, r1, r2
20650 // fallthrough --> copy0MBB
20651 MachineBasicBlock *thisMBB = BB;
20652 MachineFunction *F = BB->getParent();
20654 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20655 // as described above, by inserting a BB, and then making a PHI at the join
20656 // point to select the true and false operands of the CMOV in the PHI.
20658 // The code also handles two different cases of multiple CMOV opcodes
20662 // In this case, there are multiple CMOVs in a row, all which are based on
20663 // the same condition setting (or the exact opposite condition setting).
20664 // In this case we can lower all the CMOVs using a single inserted BB, and
20665 // then make a number of PHIs at the join point to model the CMOVs. The only
20666 // trickiness here, is that in a case like:
20668 // t2 = CMOV cond1 t1, f1
20669 // t3 = CMOV cond1 t2, f2
20671 // when rewriting this into PHIs, we have to perform some renaming on the
20672 // temps since you cannot have a PHI operand refer to a PHI result earlier
20673 // in the same block. The "simple" but wrong lowering would be:
20675 // t2 = PHI t1(BB1), f1(BB2)
20676 // t3 = PHI t2(BB1), f2(BB2)
20678 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20679 // renaming is to note that on the path through BB1, t2 is really just a
20680 // copy of t1, and do that renaming, properly generating:
20682 // t2 = PHI t1(BB1), f1(BB2)
20683 // t3 = PHI t1(BB1), f2(BB2)
20685 // Case 2, we lower cascaded CMOVs such as
20687 // (CMOV (CMOV F, T, cc1), T, cc2)
20689 // to two successives branches. For that, we look for another CMOV as the
20690 // following instruction.
20692 // Without this, we would add a PHI between the two jumps, which ends up
20693 // creating a few copies all around. For instance, for
20695 // (sitofp (zext (fcmp une)))
20697 // we would generate:
20699 // ucomiss %xmm1, %xmm0
20700 // movss <1.0f>, %xmm0
20701 // movaps %xmm0, %xmm1
20703 // xorps %xmm1, %xmm1
20706 // movaps %xmm1, %xmm0
20710 // because this custom-inserter would have generated:
20722 // A: X = ...; Y = ...
20724 // C: Z = PHI [X, A], [Y, B]
20726 // E: PHI [X, C], [Z, D]
20728 // If we lower both CMOVs in a single step, we can instead generate:
20740 // A: X = ...; Y = ...
20742 // E: PHI [X, A], [X, C], [Y, D]
20744 // Which, in our sitofp/fcmp example, gives us something like:
20746 // ucomiss %xmm1, %xmm0
20747 // movss <1.0f>, %xmm0
20750 // xorps %xmm0, %xmm0
20754 MachineInstr *CascadedCMOV = nullptr;
20755 MachineInstr *LastCMOV = MI;
20756 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20757 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20758 MachineBasicBlock::iterator NextMIIt =
20759 std::next(MachineBasicBlock::iterator(MI));
20761 // Check for case 1, where there are multiple CMOVs with the same condition
20762 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20763 // number of jumps the most.
20765 if (isCMOVPseudo(MI)) {
20766 // See if we have a string of CMOVS with the same condition.
20767 while (NextMIIt != BB->end() &&
20768 isCMOVPseudo(NextMIIt) &&
20769 (NextMIIt->getOperand(3).getImm() == CC ||
20770 NextMIIt->getOperand(3).getImm() == OppCC)) {
20771 LastCMOV = &*NextMIIt;
20776 // This checks for case 2, but only do this if we didn't already find
20777 // case 1, as indicated by LastCMOV == MI.
20778 if (LastCMOV == MI &&
20779 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20780 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20781 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20782 CascadedCMOV = &*NextMIIt;
20785 MachineBasicBlock *jcc1MBB = nullptr;
20787 // If we have a cascaded CMOV, we lower it to two successive branches to
20788 // the same block. EFLAGS is used by both, so mark it as live in the second.
20789 if (CascadedCMOV) {
20790 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20791 F->insert(It, jcc1MBB);
20792 jcc1MBB->addLiveIn(X86::EFLAGS);
20795 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20796 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20797 F->insert(It, copy0MBB);
20798 F->insert(It, sinkMBB);
20800 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20801 // live into the sink and copy blocks.
20802 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20804 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20805 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20806 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20807 copy0MBB->addLiveIn(X86::EFLAGS);
20808 sinkMBB->addLiveIn(X86::EFLAGS);
20811 // Transfer the remainder of BB and its successor edges to sinkMBB.
20812 sinkMBB->splice(sinkMBB->begin(), BB,
20813 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20814 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20816 // Add the true and fallthrough blocks as its successors.
20817 if (CascadedCMOV) {
20818 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20819 BB->addSuccessor(jcc1MBB);
20821 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20822 // jump to the sinkMBB.
20823 jcc1MBB->addSuccessor(copy0MBB);
20824 jcc1MBB->addSuccessor(sinkMBB);
20826 BB->addSuccessor(copy0MBB);
20829 // The true block target of the first (or only) branch is always sinkMBB.
20830 BB->addSuccessor(sinkMBB);
20832 // Create the conditional branch instruction.
20833 unsigned Opc = X86::GetCondBranchFromCond(CC);
20834 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20836 if (CascadedCMOV) {
20837 unsigned Opc2 = X86::GetCondBranchFromCond(
20838 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20839 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20843 // %FalseValue = ...
20844 // # fallthrough to sinkMBB
20845 copy0MBB->addSuccessor(sinkMBB);
20848 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20850 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20851 MachineBasicBlock::iterator MIItEnd =
20852 std::next(MachineBasicBlock::iterator(LastCMOV));
20853 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20854 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20855 MachineInstrBuilder MIB;
20857 // As we are creating the PHIs, we have to be careful if there is more than
20858 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20859 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20860 // That also means that PHI construction must work forward from earlier to
20861 // later, and that the code must maintain a mapping from earlier PHI's
20862 // destination registers, and the registers that went into the PHI.
20864 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20865 unsigned DestReg = MIIt->getOperand(0).getReg();
20866 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20867 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20869 // If this CMOV we are generating is the opposite condition from
20870 // the jump we generated, then we have to swap the operands for the
20871 // PHI that is going to be generated.
20872 if (MIIt->getOperand(3).getImm() == OppCC)
20873 std::swap(Op1Reg, Op2Reg);
20875 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20876 Op1Reg = RegRewriteTable[Op1Reg].first;
20878 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20879 Op2Reg = RegRewriteTable[Op2Reg].second;
20881 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20882 TII->get(X86::PHI), DestReg)
20883 .addReg(Op1Reg).addMBB(copy0MBB)
20884 .addReg(Op2Reg).addMBB(thisMBB);
20886 // Add this PHI to the rewrite table.
20887 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20890 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20891 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20892 if (CascadedCMOV) {
20893 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20894 // Copy the PHI result to the register defined by the second CMOV.
20895 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20896 DL, TII->get(TargetOpcode::COPY),
20897 CascadedCMOV->getOperand(0).getReg())
20898 .addReg(MI->getOperand(0).getReg());
20899 CascadedCMOV->eraseFromParent();
20902 // Now remove the CMOV(s).
20903 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20904 (MIIt++)->eraseFromParent();
20909 MachineBasicBlock *
20910 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20911 MachineBasicBlock *BB) const {
20912 // Combine the following atomic floating-point modification pattern:
20913 // a.store(reg OP a.load(acquire), release)
20914 // Transform them into:
20915 // OPss (%gpr), %xmm
20916 // movss %xmm, (%gpr)
20917 // Or sd equivalent for 64-bit operations.
20919 switch (MI->getOpcode()) {
20920 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20921 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20922 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20924 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20925 DebugLoc DL = MI->getDebugLoc();
20926 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20927 unsigned MSrc = MI->getOperand(0).getReg();
20928 unsigned VSrc = MI->getOperand(5).getReg();
20929 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20930 .addReg(/*Base=*/MSrc)
20931 .addImm(/*Scale=*/1)
20932 .addReg(/*Index=*/0)
20935 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20936 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20938 .addReg(/*Base=*/MSrc)
20939 .addImm(/*Scale=*/1)
20940 .addReg(/*Index=*/0)
20941 .addImm(/*Disp=*/0)
20942 .addReg(/*Segment=*/0);
20943 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20944 MI->eraseFromParent(); // The pseudo instruction is gone now.
20948 MachineBasicBlock *
20949 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20950 MachineBasicBlock *BB) const {
20951 MachineFunction *MF = BB->getParent();
20952 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20953 DebugLoc DL = MI->getDebugLoc();
20954 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20956 assert(MF->shouldSplitStack());
20958 const bool Is64Bit = Subtarget->is64Bit();
20959 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20961 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20962 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20965 // ... [Till the alloca]
20966 // If stacklet is not large enough, jump to mallocMBB
20969 // Allocate by subtracting from RSP
20970 // Jump to continueMBB
20973 // Allocate by call to runtime
20977 // [rest of original BB]
20980 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20981 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20982 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20984 MachineRegisterInfo &MRI = MF->getRegInfo();
20985 const TargetRegisterClass *AddrRegClass =
20986 getRegClassFor(getPointerTy(MF->getDataLayout()));
20988 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20989 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20990 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20991 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20992 sizeVReg = MI->getOperand(1).getReg(),
20993 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20995 MachineFunction::iterator MBBIter = BB;
20998 MF->insert(MBBIter, bumpMBB);
20999 MF->insert(MBBIter, mallocMBB);
21000 MF->insert(MBBIter, continueMBB);
21002 continueMBB->splice(continueMBB->begin(), BB,
21003 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21004 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21006 // Add code to the main basic block to check if the stack limit has been hit,
21007 // and if so, jump to mallocMBB otherwise to bumpMBB.
21008 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21009 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21010 .addReg(tmpSPVReg).addReg(sizeVReg);
21011 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21012 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21013 .addReg(SPLimitVReg);
21014 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21016 // bumpMBB simply decreases the stack pointer, since we know the current
21017 // stacklet has enough space.
21018 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21019 .addReg(SPLimitVReg);
21020 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21021 .addReg(SPLimitVReg);
21022 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21024 // Calls into a routine in libgcc to allocate more space from the heap.
21025 const uint32_t *RegMask =
21026 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21028 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21030 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21031 .addExternalSymbol("__morestack_allocate_stack_space")
21032 .addRegMask(RegMask)
21033 .addReg(X86::RDI, RegState::Implicit)
21034 .addReg(X86::RAX, RegState::ImplicitDefine);
21035 } else if (Is64Bit) {
21036 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21038 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21039 .addExternalSymbol("__morestack_allocate_stack_space")
21040 .addRegMask(RegMask)
21041 .addReg(X86::EDI, RegState::Implicit)
21042 .addReg(X86::EAX, RegState::ImplicitDefine);
21044 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21046 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21047 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21048 .addExternalSymbol("__morestack_allocate_stack_space")
21049 .addRegMask(RegMask)
21050 .addReg(X86::EAX, RegState::ImplicitDefine);
21054 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21057 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21058 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21059 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21061 // Set up the CFG correctly.
21062 BB->addSuccessor(bumpMBB);
21063 BB->addSuccessor(mallocMBB);
21064 mallocMBB->addSuccessor(continueMBB);
21065 bumpMBB->addSuccessor(continueMBB);
21067 // Take care of the PHI nodes.
21068 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21069 MI->getOperand(0).getReg())
21070 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21071 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21073 // Delete the original pseudo instruction.
21074 MI->eraseFromParent();
21077 return continueMBB;
21080 MachineBasicBlock *
21081 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21082 MachineBasicBlock *BB) const {
21083 DebugLoc DL = MI->getDebugLoc();
21085 assert(!Subtarget->isTargetMachO());
21087 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21090 MI->eraseFromParent(); // The pseudo instruction is gone now.
21094 MachineBasicBlock *
21095 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21096 MachineBasicBlock *BB) const {
21097 // This is pretty easy. We're taking the value that we received from
21098 // our load from the relocation, sticking it in either RDI (x86-64)
21099 // or EAX and doing an indirect call. The return value will then
21100 // be in the normal return register.
21101 MachineFunction *F = BB->getParent();
21102 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21103 DebugLoc DL = MI->getDebugLoc();
21105 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21106 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21108 // Get a register mask for the lowered call.
21109 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21110 // proper register mask.
21111 const uint32_t *RegMask =
21112 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21113 if (Subtarget->is64Bit()) {
21114 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21115 TII->get(X86::MOV64rm), X86::RDI)
21117 .addImm(0).addReg(0)
21118 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21119 MI->getOperand(3).getTargetFlags())
21121 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21122 addDirectMem(MIB, X86::RDI);
21123 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21124 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21125 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21126 TII->get(X86::MOV32rm), X86::EAX)
21128 .addImm(0).addReg(0)
21129 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21130 MI->getOperand(3).getTargetFlags())
21132 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21133 addDirectMem(MIB, X86::EAX);
21134 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21136 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21137 TII->get(X86::MOV32rm), X86::EAX)
21138 .addReg(TII->getGlobalBaseReg(F))
21139 .addImm(0).addReg(0)
21140 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21141 MI->getOperand(3).getTargetFlags())
21143 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21144 addDirectMem(MIB, X86::EAX);
21145 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21148 MI->eraseFromParent(); // The pseudo instruction is gone now.
21152 MachineBasicBlock *
21153 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21154 MachineBasicBlock *MBB) const {
21155 DebugLoc DL = MI->getDebugLoc();
21156 MachineFunction *MF = MBB->getParent();
21157 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21158 MachineRegisterInfo &MRI = MF->getRegInfo();
21160 const BasicBlock *BB = MBB->getBasicBlock();
21161 MachineFunction::iterator I = MBB;
21164 // Memory Reference
21165 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21166 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21169 unsigned MemOpndSlot = 0;
21171 unsigned CurOp = 0;
21173 DstReg = MI->getOperand(CurOp++).getReg();
21174 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21175 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21176 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21177 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21179 MemOpndSlot = CurOp;
21181 MVT PVT = getPointerTy(MF->getDataLayout());
21182 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21183 "Invalid Pointer Size!");
21185 // For v = setjmp(buf), we generate
21188 // buf[LabelOffset] = restoreMBB
21189 // SjLjSetup restoreMBB
21195 // v = phi(main, restore)
21198 // if base pointer being used, load it from frame
21201 MachineBasicBlock *thisMBB = MBB;
21202 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21203 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21204 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21205 MF->insert(I, mainMBB);
21206 MF->insert(I, sinkMBB);
21207 MF->push_back(restoreMBB);
21209 MachineInstrBuilder MIB;
21211 // Transfer the remainder of BB and its successor edges to sinkMBB.
21212 sinkMBB->splice(sinkMBB->begin(), MBB,
21213 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21214 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21217 unsigned PtrStoreOpc = 0;
21218 unsigned LabelReg = 0;
21219 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21220 Reloc::Model RM = MF->getTarget().getRelocationModel();
21221 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21222 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21224 // Prepare IP either in reg or imm.
21225 if (!UseImmLabel) {
21226 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21227 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21228 LabelReg = MRI.createVirtualRegister(PtrRC);
21229 if (Subtarget->is64Bit()) {
21230 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21234 .addMBB(restoreMBB)
21237 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21238 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21239 .addReg(XII->getGlobalBaseReg(MF))
21242 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21246 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21248 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21249 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21250 if (i == X86::AddrDisp)
21251 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21253 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21256 MIB.addReg(LabelReg);
21258 MIB.addMBB(restoreMBB);
21259 MIB.setMemRefs(MMOBegin, MMOEnd);
21261 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21262 .addMBB(restoreMBB);
21264 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21265 MIB.addRegMask(RegInfo->getNoPreservedMask());
21266 thisMBB->addSuccessor(mainMBB);
21267 thisMBB->addSuccessor(restoreMBB);
21271 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21272 mainMBB->addSuccessor(sinkMBB);
21275 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21276 TII->get(X86::PHI), DstReg)
21277 .addReg(mainDstReg).addMBB(mainMBB)
21278 .addReg(restoreDstReg).addMBB(restoreMBB);
21281 if (RegInfo->hasBasePointer(*MF)) {
21282 const bool Uses64BitFramePtr =
21283 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21284 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21285 X86FI->setRestoreBasePointer(MF);
21286 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21287 unsigned BasePtr = RegInfo->getBaseRegister();
21288 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21289 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21290 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21291 .setMIFlag(MachineInstr::FrameSetup);
21293 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21294 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21295 restoreMBB->addSuccessor(sinkMBB);
21297 MI->eraseFromParent();
21301 MachineBasicBlock *
21302 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21303 MachineBasicBlock *MBB) const {
21304 DebugLoc DL = MI->getDebugLoc();
21305 MachineFunction *MF = MBB->getParent();
21306 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21307 MachineRegisterInfo &MRI = MF->getRegInfo();
21309 // Memory Reference
21310 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21311 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21313 MVT PVT = getPointerTy(MF->getDataLayout());
21314 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21315 "Invalid Pointer Size!");
21317 const TargetRegisterClass *RC =
21318 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21319 unsigned Tmp = MRI.createVirtualRegister(RC);
21320 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21321 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21322 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21323 unsigned SP = RegInfo->getStackRegister();
21325 MachineInstrBuilder MIB;
21327 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21328 const int64_t SPOffset = 2 * PVT.getStoreSize();
21330 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21331 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21334 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21335 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21336 MIB.addOperand(MI->getOperand(i));
21337 MIB.setMemRefs(MMOBegin, MMOEnd);
21339 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21340 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21341 if (i == X86::AddrDisp)
21342 MIB.addDisp(MI->getOperand(i), LabelOffset);
21344 MIB.addOperand(MI->getOperand(i));
21346 MIB.setMemRefs(MMOBegin, MMOEnd);
21348 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21349 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21350 if (i == X86::AddrDisp)
21351 MIB.addDisp(MI->getOperand(i), SPOffset);
21353 MIB.addOperand(MI->getOperand(i));
21355 MIB.setMemRefs(MMOBegin, MMOEnd);
21357 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21359 MI->eraseFromParent();
21363 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21364 // accumulator loops. Writing back to the accumulator allows the coalescer
21365 // to remove extra copies in the loop.
21366 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21367 MachineBasicBlock *
21368 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21369 MachineBasicBlock *MBB) const {
21370 MachineOperand &AddendOp = MI->getOperand(3);
21372 // Bail out early if the addend isn't a register - we can't switch these.
21373 if (!AddendOp.isReg())
21376 MachineFunction &MF = *MBB->getParent();
21377 MachineRegisterInfo &MRI = MF.getRegInfo();
21379 // Check whether the addend is defined by a PHI:
21380 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21381 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21382 if (!AddendDef.isPHI())
21385 // Look for the following pattern:
21387 // %addend = phi [%entry, 0], [%loop, %result]
21389 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21393 // %addend = phi [%entry, 0], [%loop, %result]
21395 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21397 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21398 assert(AddendDef.getOperand(i).isReg());
21399 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21400 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21401 if (&PHISrcInst == MI) {
21402 // Found a matching instruction.
21403 unsigned NewFMAOpc = 0;
21404 switch (MI->getOpcode()) {
21405 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21406 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21407 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21408 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21409 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21410 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21411 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21412 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21413 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21414 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21415 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21416 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21417 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21418 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21419 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21420 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21421 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21422 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21423 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21424 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21426 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21427 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21428 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21429 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21430 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21431 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21432 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21433 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21434 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21435 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21436 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21437 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21438 default: llvm_unreachable("Unrecognized FMA variant.");
21441 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21442 MachineInstrBuilder MIB =
21443 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21444 .addOperand(MI->getOperand(0))
21445 .addOperand(MI->getOperand(3))
21446 .addOperand(MI->getOperand(2))
21447 .addOperand(MI->getOperand(1));
21448 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21449 MI->eraseFromParent();
21456 MachineBasicBlock *
21457 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21458 MachineBasicBlock *BB) const {
21459 switch (MI->getOpcode()) {
21460 default: llvm_unreachable("Unexpected instr type to insert");
21461 case X86::TAILJMPd64:
21462 case X86::TAILJMPr64:
21463 case X86::TAILJMPm64:
21464 case X86::TAILJMPd64_REX:
21465 case X86::TAILJMPr64_REX:
21466 case X86::TAILJMPm64_REX:
21467 llvm_unreachable("TAILJMP64 would not be touched here.");
21468 case X86::TCRETURNdi64:
21469 case X86::TCRETURNri64:
21470 case X86::TCRETURNmi64:
21472 case X86::WIN_ALLOCA:
21473 return EmitLoweredWinAlloca(MI, BB);
21474 case X86::SEG_ALLOCA_32:
21475 case X86::SEG_ALLOCA_64:
21476 return EmitLoweredSegAlloca(MI, BB);
21477 case X86::TLSCall_32:
21478 case X86::TLSCall_64:
21479 return EmitLoweredTLSCall(MI, BB);
21480 case X86::CMOV_FR32:
21481 case X86::CMOV_FR64:
21482 case X86::CMOV_GR8:
21483 case X86::CMOV_GR16:
21484 case X86::CMOV_GR32:
21485 case X86::CMOV_RFP32:
21486 case X86::CMOV_RFP64:
21487 case X86::CMOV_RFP80:
21488 case X86::CMOV_V2F64:
21489 case X86::CMOV_V2I64:
21490 case X86::CMOV_V4F32:
21491 case X86::CMOV_V4F64:
21492 case X86::CMOV_V4I64:
21493 case X86::CMOV_V16F32:
21494 case X86::CMOV_V8F32:
21495 case X86::CMOV_V8F64:
21496 case X86::CMOV_V8I64:
21497 case X86::CMOV_V8I1:
21498 case X86::CMOV_V16I1:
21499 case X86::CMOV_V32I1:
21500 case X86::CMOV_V64I1:
21501 return EmitLoweredSelect(MI, BB);
21503 case X86::RELEASE_FADD32mr:
21504 case X86::RELEASE_FADD64mr:
21505 return EmitLoweredAtomicFP(MI, BB);
21507 case X86::FP32_TO_INT16_IN_MEM:
21508 case X86::FP32_TO_INT32_IN_MEM:
21509 case X86::FP32_TO_INT64_IN_MEM:
21510 case X86::FP64_TO_INT16_IN_MEM:
21511 case X86::FP64_TO_INT32_IN_MEM:
21512 case X86::FP64_TO_INT64_IN_MEM:
21513 case X86::FP80_TO_INT16_IN_MEM:
21514 case X86::FP80_TO_INT32_IN_MEM:
21515 case X86::FP80_TO_INT64_IN_MEM: {
21516 MachineFunction *F = BB->getParent();
21517 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21518 DebugLoc DL = MI->getDebugLoc();
21520 // Change the floating point control register to use "round towards zero"
21521 // mode when truncating to an integer value.
21522 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21523 addFrameReference(BuildMI(*BB, MI, DL,
21524 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21526 // Load the old value of the high byte of the control word...
21528 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21529 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21532 // Set the high part to be round to zero...
21533 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21536 // Reload the modified control word now...
21537 addFrameReference(BuildMI(*BB, MI, DL,
21538 TII->get(X86::FLDCW16m)), CWFrameIdx);
21540 // Restore the memory image of control word to original value
21541 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21544 // Get the X86 opcode to use.
21546 switch (MI->getOpcode()) {
21547 default: llvm_unreachable("illegal opcode!");
21548 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21549 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21550 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21551 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21552 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21553 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21554 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21555 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21556 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21560 MachineOperand &Op = MI->getOperand(0);
21562 AM.BaseType = X86AddressMode::RegBase;
21563 AM.Base.Reg = Op.getReg();
21565 AM.BaseType = X86AddressMode::FrameIndexBase;
21566 AM.Base.FrameIndex = Op.getIndex();
21568 Op = MI->getOperand(1);
21570 AM.Scale = Op.getImm();
21571 Op = MI->getOperand(2);
21573 AM.IndexReg = Op.getImm();
21574 Op = MI->getOperand(3);
21575 if (Op.isGlobal()) {
21576 AM.GV = Op.getGlobal();
21578 AM.Disp = Op.getImm();
21580 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21581 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21583 // Reload the original control word now.
21584 addFrameReference(BuildMI(*BB, MI, DL,
21585 TII->get(X86::FLDCW16m)), CWFrameIdx);
21587 MI->eraseFromParent(); // The pseudo instruction is gone now.
21590 // String/text processing lowering.
21591 case X86::PCMPISTRM128REG:
21592 case X86::VPCMPISTRM128REG:
21593 case X86::PCMPISTRM128MEM:
21594 case X86::VPCMPISTRM128MEM:
21595 case X86::PCMPESTRM128REG:
21596 case X86::VPCMPESTRM128REG:
21597 case X86::PCMPESTRM128MEM:
21598 case X86::VPCMPESTRM128MEM:
21599 assert(Subtarget->hasSSE42() &&
21600 "Target must have SSE4.2 or AVX features enabled");
21601 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21603 // String/text processing lowering.
21604 case X86::PCMPISTRIREG:
21605 case X86::VPCMPISTRIREG:
21606 case X86::PCMPISTRIMEM:
21607 case X86::VPCMPISTRIMEM:
21608 case X86::PCMPESTRIREG:
21609 case X86::VPCMPESTRIREG:
21610 case X86::PCMPESTRIMEM:
21611 case X86::VPCMPESTRIMEM:
21612 assert(Subtarget->hasSSE42() &&
21613 "Target must have SSE4.2 or AVX features enabled");
21614 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21616 // Thread synchronization.
21618 return EmitMonitor(MI, BB, Subtarget);
21622 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21624 case X86::VASTART_SAVE_XMM_REGS:
21625 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21627 case X86::VAARG_64:
21628 return EmitVAARG64WithCustomInserter(MI, BB);
21630 case X86::EH_SjLj_SetJmp32:
21631 case X86::EH_SjLj_SetJmp64:
21632 return emitEHSjLjSetJmp(MI, BB);
21634 case X86::EH_SjLj_LongJmp32:
21635 case X86::EH_SjLj_LongJmp64:
21636 return emitEHSjLjLongJmp(MI, BB);
21638 case TargetOpcode::STATEPOINT:
21639 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21640 // this point in the process. We diverge later.
21641 return emitPatchPoint(MI, BB);
21643 case TargetOpcode::STACKMAP:
21644 case TargetOpcode::PATCHPOINT:
21645 return emitPatchPoint(MI, BB);
21647 case X86::VFMADDPDr213r:
21648 case X86::VFMADDPSr213r:
21649 case X86::VFMADDSDr213r:
21650 case X86::VFMADDSSr213r:
21651 case X86::VFMSUBPDr213r:
21652 case X86::VFMSUBPSr213r:
21653 case X86::VFMSUBSDr213r:
21654 case X86::VFMSUBSSr213r:
21655 case X86::VFNMADDPDr213r:
21656 case X86::VFNMADDPSr213r:
21657 case X86::VFNMADDSDr213r:
21658 case X86::VFNMADDSSr213r:
21659 case X86::VFNMSUBPDr213r:
21660 case X86::VFNMSUBPSr213r:
21661 case X86::VFNMSUBSDr213r:
21662 case X86::VFNMSUBSSr213r:
21663 case X86::VFMADDSUBPDr213r:
21664 case X86::VFMADDSUBPSr213r:
21665 case X86::VFMSUBADDPDr213r:
21666 case X86::VFMSUBADDPSr213r:
21667 case X86::VFMADDPDr213rY:
21668 case X86::VFMADDPSr213rY:
21669 case X86::VFMSUBPDr213rY:
21670 case X86::VFMSUBPSr213rY:
21671 case X86::VFNMADDPDr213rY:
21672 case X86::VFNMADDPSr213rY:
21673 case X86::VFNMSUBPDr213rY:
21674 case X86::VFNMSUBPSr213rY:
21675 case X86::VFMADDSUBPDr213rY:
21676 case X86::VFMADDSUBPSr213rY:
21677 case X86::VFMSUBADDPDr213rY:
21678 case X86::VFMSUBADDPSr213rY:
21679 return emitFMA3Instr(MI, BB);
21683 //===----------------------------------------------------------------------===//
21684 // X86 Optimization Hooks
21685 //===----------------------------------------------------------------------===//
21687 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21690 const SelectionDAG &DAG,
21691 unsigned Depth) const {
21692 unsigned BitWidth = KnownZero.getBitWidth();
21693 unsigned Opc = Op.getOpcode();
21694 assert((Opc >= ISD::BUILTIN_OP_END ||
21695 Opc == ISD::INTRINSIC_WO_CHAIN ||
21696 Opc == ISD::INTRINSIC_W_CHAIN ||
21697 Opc == ISD::INTRINSIC_VOID) &&
21698 "Should use MaskedValueIsZero if you don't know whether Op"
21699 " is a target node!");
21701 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21715 // These nodes' second result is a boolean.
21716 if (Op.getResNo() == 0)
21719 case X86ISD::SETCC:
21720 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21722 case ISD::INTRINSIC_WO_CHAIN: {
21723 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21724 unsigned NumLoBits = 0;
21727 case Intrinsic::x86_sse_movmsk_ps:
21728 case Intrinsic::x86_avx_movmsk_ps_256:
21729 case Intrinsic::x86_sse2_movmsk_pd:
21730 case Intrinsic::x86_avx_movmsk_pd_256:
21731 case Intrinsic::x86_mmx_pmovmskb:
21732 case Intrinsic::x86_sse2_pmovmskb_128:
21733 case Intrinsic::x86_avx2_pmovmskb: {
21734 // High bits of movmskp{s|d}, pmovmskb are known zero.
21736 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21737 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21738 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21739 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21740 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21741 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21742 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21743 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21745 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21754 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21756 const SelectionDAG &,
21757 unsigned Depth) const {
21758 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21759 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21760 return Op.getValueType().getScalarType().getSizeInBits();
21766 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21767 /// node is a GlobalAddress + offset.
21768 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21769 const GlobalValue* &GA,
21770 int64_t &Offset) const {
21771 if (N->getOpcode() == X86ISD::Wrapper) {
21772 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21773 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21774 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21778 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21781 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21782 /// same as extracting the high 128-bit part of 256-bit vector and then
21783 /// inserting the result into the low part of a new 256-bit vector
21784 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21785 EVT VT = SVOp->getValueType(0);
21786 unsigned NumElems = VT.getVectorNumElements();
21788 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21789 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21790 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21791 SVOp->getMaskElt(j) >= 0)
21797 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21798 /// same as extracting the low 128-bit part of 256-bit vector and then
21799 /// inserting the result into the high part of a new 256-bit vector
21800 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21801 EVT VT = SVOp->getValueType(0);
21802 unsigned NumElems = VT.getVectorNumElements();
21804 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21805 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21806 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21807 SVOp->getMaskElt(j) >= 0)
21813 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21814 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21815 TargetLowering::DAGCombinerInfo &DCI,
21816 const X86Subtarget* Subtarget) {
21818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21819 SDValue V1 = SVOp->getOperand(0);
21820 SDValue V2 = SVOp->getOperand(1);
21821 EVT VT = SVOp->getValueType(0);
21822 unsigned NumElems = VT.getVectorNumElements();
21824 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21825 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21829 // V UNDEF BUILD_VECTOR UNDEF
21831 // CONCAT_VECTOR CONCAT_VECTOR
21834 // RESULT: V + zero extended
21836 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21837 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21838 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21841 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21844 // To match the shuffle mask, the first half of the mask should
21845 // be exactly the first vector, and all the rest a splat with the
21846 // first element of the second one.
21847 for (unsigned i = 0; i != NumElems/2; ++i)
21848 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21849 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21852 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21853 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21854 if (Ld->hasNUsesOfValue(1, 0)) {
21855 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21856 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21858 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21860 Ld->getPointerInfo(),
21861 Ld->getAlignment(),
21862 false/*isVolatile*/, true/*ReadMem*/,
21863 false/*WriteMem*/);
21865 // Make sure the newly-created LOAD is in the same position as Ld in
21866 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21867 // and update uses of Ld's output chain to use the TokenFactor.
21868 if (Ld->hasAnyUseOfValue(1)) {
21869 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21870 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21871 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21872 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21873 SDValue(ResNode.getNode(), 1));
21876 return DAG.getBitcast(VT, ResNode);
21880 // Emit a zeroed vector and insert the desired subvector on its
21882 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21883 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21884 return DCI.CombineTo(N, InsV);
21887 //===--------------------------------------------------------------------===//
21888 // Combine some shuffles into subvector extracts and inserts:
21891 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21892 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21893 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21894 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21895 return DCI.CombineTo(N, InsV);
21898 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21899 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21900 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21901 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21902 return DCI.CombineTo(N, InsV);
21908 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21911 /// This is the leaf of the recursive combinine below. When we have found some
21912 /// chain of single-use x86 shuffle instructions and accumulated the combined
21913 /// shuffle mask represented by them, this will try to pattern match that mask
21914 /// into either a single instruction if there is a special purpose instruction
21915 /// for this operation, or into a PSHUFB instruction which is a fully general
21916 /// instruction but should only be used to replace chains over a certain depth.
21917 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21918 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21919 TargetLowering::DAGCombinerInfo &DCI,
21920 const X86Subtarget *Subtarget) {
21921 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21923 // Find the operand that enters the chain. Note that multiple uses are OK
21924 // here, we're not going to remove the operand we find.
21925 SDValue Input = Op.getOperand(0);
21926 while (Input.getOpcode() == ISD::BITCAST)
21927 Input = Input.getOperand(0);
21929 MVT VT = Input.getSimpleValueType();
21930 MVT RootVT = Root.getSimpleValueType();
21933 // Just remove no-op shuffle masks.
21934 if (Mask.size() == 1) {
21935 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21940 // Use the float domain if the operand type is a floating point type.
21941 bool FloatDomain = VT.isFloatingPoint();
21943 // For floating point shuffles, we don't have free copies in the shuffle
21944 // instructions or the ability to load as part of the instruction, so
21945 // canonicalize their shuffles to UNPCK or MOV variants.
21947 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21948 // vectors because it can have a load folded into it that UNPCK cannot. This
21949 // doesn't preclude something switching to the shorter encoding post-RA.
21951 // FIXME: Should teach these routines about AVX vector widths.
21952 if (FloatDomain && VT.getSizeInBits() == 128) {
21953 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21954 bool Lo = Mask.equals({0, 0});
21957 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21958 // is no slower than UNPCKLPD but has the option to fold the input operand
21959 // into even an unaligned memory load.
21960 if (Lo && Subtarget->hasSSE3()) {
21961 Shuffle = X86ISD::MOVDDUP;
21962 ShuffleVT = MVT::v2f64;
21964 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21965 // than the UNPCK variants.
21966 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21967 ShuffleVT = MVT::v4f32;
21969 if (Depth == 1 && Root->getOpcode() == Shuffle)
21970 return false; // Nothing to do!
21971 Op = DAG.getBitcast(ShuffleVT, Input);
21972 DCI.AddToWorklist(Op.getNode());
21973 if (Shuffle == X86ISD::MOVDDUP)
21974 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21976 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21977 DCI.AddToWorklist(Op.getNode());
21978 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21982 if (Subtarget->hasSSE3() &&
21983 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21984 bool Lo = Mask.equals({0, 0, 2, 2});
21985 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21986 MVT ShuffleVT = MVT::v4f32;
21987 if (Depth == 1 && Root->getOpcode() == Shuffle)
21988 return false; // Nothing to do!
21989 Op = DAG.getBitcast(ShuffleVT, Input);
21990 DCI.AddToWorklist(Op.getNode());
21991 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21992 DCI.AddToWorklist(Op.getNode());
21993 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21997 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
21998 bool Lo = Mask.equals({0, 0, 1, 1});
21999 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22000 MVT ShuffleVT = MVT::v4f32;
22001 if (Depth == 1 && Root->getOpcode() == Shuffle)
22002 return false; // Nothing to do!
22003 Op = DAG.getBitcast(ShuffleVT, Input);
22004 DCI.AddToWorklist(Op.getNode());
22005 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22006 DCI.AddToWorklist(Op.getNode());
22007 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22013 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22014 // variants as none of these have single-instruction variants that are
22015 // superior to the UNPCK formulation.
22016 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22017 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22018 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22019 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22021 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22022 bool Lo = Mask[0] == 0;
22023 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22024 if (Depth == 1 && Root->getOpcode() == Shuffle)
22025 return false; // Nothing to do!
22027 switch (Mask.size()) {
22029 ShuffleVT = MVT::v8i16;
22032 ShuffleVT = MVT::v16i8;
22035 llvm_unreachable("Impossible mask size!");
22037 Op = DAG.getBitcast(ShuffleVT, Input);
22038 DCI.AddToWorklist(Op.getNode());
22039 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22040 DCI.AddToWorklist(Op.getNode());
22041 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22046 // Don't try to re-form single instruction chains under any circumstances now
22047 // that we've done encoding canonicalization for them.
22051 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22052 // can replace them with a single PSHUFB instruction profitably. Intel's
22053 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22054 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22055 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22056 SmallVector<SDValue, 16> PSHUFBMask;
22057 int NumBytes = VT.getSizeInBits() / 8;
22058 int Ratio = NumBytes / Mask.size();
22059 for (int i = 0; i < NumBytes; ++i) {
22060 if (Mask[i / Ratio] == SM_SentinelUndef) {
22061 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22064 int M = Mask[i / Ratio] != SM_SentinelZero
22065 ? Ratio * Mask[i / Ratio] + i % Ratio
22067 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22069 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22070 Op = DAG.getBitcast(ByteVT, Input);
22071 DCI.AddToWorklist(Op.getNode());
22072 SDValue PSHUFBMaskOp =
22073 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22074 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22075 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22076 DCI.AddToWorklist(Op.getNode());
22077 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22082 // Failed to find any combines.
22086 /// \brief Fully generic combining of x86 shuffle instructions.
22088 /// This should be the last combine run over the x86 shuffle instructions. Once
22089 /// they have been fully optimized, this will recursively consider all chains
22090 /// of single-use shuffle instructions, build a generic model of the cumulative
22091 /// shuffle operation, and check for simpler instructions which implement this
22092 /// operation. We use this primarily for two purposes:
22094 /// 1) Collapse generic shuffles to specialized single instructions when
22095 /// equivalent. In most cases, this is just an encoding size win, but
22096 /// sometimes we will collapse multiple generic shuffles into a single
22097 /// special-purpose shuffle.
22098 /// 2) Look for sequences of shuffle instructions with 3 or more total
22099 /// instructions, and replace them with the slightly more expensive SSSE3
22100 /// PSHUFB instruction if available. We do this as the last combining step
22101 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22102 /// a suitable short sequence of other instructions. The PHUFB will either
22103 /// use a register or have to read from memory and so is slightly (but only
22104 /// slightly) more expensive than the other shuffle instructions.
22106 /// Because this is inherently a quadratic operation (for each shuffle in
22107 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22108 /// This should never be an issue in practice as the shuffle lowering doesn't
22109 /// produce sequences of more than 8 instructions.
22111 /// FIXME: We will currently miss some cases where the redundant shuffling
22112 /// would simplify under the threshold for PSHUFB formation because of
22113 /// combine-ordering. To fix this, we should do the redundant instruction
22114 /// combining in this recursive walk.
22115 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22116 ArrayRef<int> RootMask,
22117 int Depth, bool HasPSHUFB,
22119 TargetLowering::DAGCombinerInfo &DCI,
22120 const X86Subtarget *Subtarget) {
22121 // Bound the depth of our recursive combine because this is ultimately
22122 // quadratic in nature.
22126 // Directly rip through bitcasts to find the underlying operand.
22127 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22128 Op = Op.getOperand(0);
22130 MVT VT = Op.getSimpleValueType();
22131 if (!VT.isVector())
22132 return false; // Bail if we hit a non-vector.
22134 assert(Root.getSimpleValueType().isVector() &&
22135 "Shuffles operate on vector types!");
22136 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22137 "Can only combine shuffles of the same vector register size.");
22139 if (!isTargetShuffle(Op.getOpcode()))
22141 SmallVector<int, 16> OpMask;
22143 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22144 // We only can combine unary shuffles which we can decode the mask for.
22145 if (!HaveMask || !IsUnary)
22148 assert(VT.getVectorNumElements() == OpMask.size() &&
22149 "Different mask size from vector size!");
22150 assert(((RootMask.size() > OpMask.size() &&
22151 RootMask.size() % OpMask.size() == 0) ||
22152 (OpMask.size() > RootMask.size() &&
22153 OpMask.size() % RootMask.size() == 0) ||
22154 OpMask.size() == RootMask.size()) &&
22155 "The smaller number of elements must divide the larger.");
22156 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22157 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22158 assert(((RootRatio == 1 && OpRatio == 1) ||
22159 (RootRatio == 1) != (OpRatio == 1)) &&
22160 "Must not have a ratio for both incoming and op masks!");
22162 SmallVector<int, 16> Mask;
22163 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22165 // Merge this shuffle operation's mask into our accumulated mask. Note that
22166 // this shuffle's mask will be the first applied to the input, followed by the
22167 // root mask to get us all the way to the root value arrangement. The reason
22168 // for this order is that we are recursing up the operation chain.
22169 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22170 int RootIdx = i / RootRatio;
22171 if (RootMask[RootIdx] < 0) {
22172 // This is a zero or undef lane, we're done.
22173 Mask.push_back(RootMask[RootIdx]);
22177 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22178 int OpIdx = RootMaskedIdx / OpRatio;
22179 if (OpMask[OpIdx] < 0) {
22180 // The incoming lanes are zero or undef, it doesn't matter which ones we
22182 Mask.push_back(OpMask[OpIdx]);
22186 // Ok, we have non-zero lanes, map them through.
22187 Mask.push_back(OpMask[OpIdx] * OpRatio +
22188 RootMaskedIdx % OpRatio);
22191 // See if we can recurse into the operand to combine more things.
22192 switch (Op.getOpcode()) {
22193 case X86ISD::PSHUFB:
22195 case X86ISD::PSHUFD:
22196 case X86ISD::PSHUFHW:
22197 case X86ISD::PSHUFLW:
22198 if (Op.getOperand(0).hasOneUse() &&
22199 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22200 HasPSHUFB, DAG, DCI, Subtarget))
22204 case X86ISD::UNPCKL:
22205 case X86ISD::UNPCKH:
22206 assert(Op.getOperand(0) == Op.getOperand(1) &&
22207 "We only combine unary shuffles!");
22208 // We can't check for single use, we have to check that this shuffle is the
22210 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22211 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22212 HasPSHUFB, DAG, DCI, Subtarget))
22217 // Minor canonicalization of the accumulated shuffle mask to make it easier
22218 // to match below. All this does is detect masks with squential pairs of
22219 // elements, and shrink them to the half-width mask. It does this in a loop
22220 // so it will reduce the size of the mask to the minimal width mask which
22221 // performs an equivalent shuffle.
22222 SmallVector<int, 16> WidenedMask;
22223 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22224 Mask = std::move(WidenedMask);
22225 WidenedMask.clear();
22228 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22232 /// \brief Get the PSHUF-style mask from PSHUF node.
22234 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22235 /// PSHUF-style masks that can be reused with such instructions.
22236 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22237 MVT VT = N.getSimpleValueType();
22238 SmallVector<int, 4> Mask;
22240 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22244 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22245 // matter. Check that the upper masks are repeats and remove them.
22246 if (VT.getSizeInBits() > 128) {
22247 int LaneElts = 128 / VT.getScalarSizeInBits();
22249 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22250 for (int j = 0; j < LaneElts; ++j)
22251 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22252 "Mask doesn't repeat in high 128-bit lanes!");
22254 Mask.resize(LaneElts);
22257 switch (N.getOpcode()) {
22258 case X86ISD::PSHUFD:
22260 case X86ISD::PSHUFLW:
22263 case X86ISD::PSHUFHW:
22264 Mask.erase(Mask.begin(), Mask.begin() + 4);
22265 for (int &M : Mask)
22269 llvm_unreachable("No valid shuffle instruction found!");
22273 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22275 /// We walk up the chain and look for a combinable shuffle, skipping over
22276 /// shuffles that we could hoist this shuffle's transformation past without
22277 /// altering anything.
22279 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22281 TargetLowering::DAGCombinerInfo &DCI) {
22282 assert(N.getOpcode() == X86ISD::PSHUFD &&
22283 "Called with something other than an x86 128-bit half shuffle!");
22286 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22287 // of the shuffles in the chain so that we can form a fresh chain to replace
22289 SmallVector<SDValue, 8> Chain;
22290 SDValue V = N.getOperand(0);
22291 for (; V.hasOneUse(); V = V.getOperand(0)) {
22292 switch (V.getOpcode()) {
22294 return SDValue(); // Nothing combined!
22297 // Skip bitcasts as we always know the type for the target specific
22301 case X86ISD::PSHUFD:
22302 // Found another dword shuffle.
22305 case X86ISD::PSHUFLW:
22306 // Check that the low words (being shuffled) are the identity in the
22307 // dword shuffle, and the high words are self-contained.
22308 if (Mask[0] != 0 || Mask[1] != 1 ||
22309 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22312 Chain.push_back(V);
22315 case X86ISD::PSHUFHW:
22316 // Check that the high words (being shuffled) are the identity in the
22317 // dword shuffle, and the low words are self-contained.
22318 if (Mask[2] != 2 || Mask[3] != 3 ||
22319 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22322 Chain.push_back(V);
22325 case X86ISD::UNPCKL:
22326 case X86ISD::UNPCKH:
22327 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22328 // shuffle into a preceding word shuffle.
22329 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22330 V.getSimpleValueType().getScalarType() != MVT::i16)
22333 // Search for a half-shuffle which we can combine with.
22334 unsigned CombineOp =
22335 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22336 if (V.getOperand(0) != V.getOperand(1) ||
22337 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22339 Chain.push_back(V);
22340 V = V.getOperand(0);
22342 switch (V.getOpcode()) {
22344 return SDValue(); // Nothing to combine.
22346 case X86ISD::PSHUFLW:
22347 case X86ISD::PSHUFHW:
22348 if (V.getOpcode() == CombineOp)
22351 Chain.push_back(V);
22355 V = V.getOperand(0);
22359 } while (V.hasOneUse());
22362 // Break out of the loop if we break out of the switch.
22366 if (!V.hasOneUse())
22367 // We fell out of the loop without finding a viable combining instruction.
22370 // Merge this node's mask and our incoming mask.
22371 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22372 for (int &M : Mask)
22374 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22375 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22377 // Rebuild the chain around this new shuffle.
22378 while (!Chain.empty()) {
22379 SDValue W = Chain.pop_back_val();
22381 if (V.getValueType() != W.getOperand(0).getValueType())
22382 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22384 switch (W.getOpcode()) {
22386 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22388 case X86ISD::UNPCKL:
22389 case X86ISD::UNPCKH:
22390 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22393 case X86ISD::PSHUFD:
22394 case X86ISD::PSHUFLW:
22395 case X86ISD::PSHUFHW:
22396 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22400 if (V.getValueType() != N.getValueType())
22401 V = DAG.getBitcast(N.getValueType(), V);
22403 // Return the new chain to replace N.
22407 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22410 /// We walk up the chain, skipping shuffles of the other half and looking
22411 /// through shuffles which switch halves trying to find a shuffle of the same
22412 /// pair of dwords.
22413 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22415 TargetLowering::DAGCombinerInfo &DCI) {
22417 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22418 "Called with something other than an x86 128-bit half shuffle!");
22420 unsigned CombineOpcode = N.getOpcode();
22422 // Walk up a single-use chain looking for a combinable shuffle.
22423 SDValue V = N.getOperand(0);
22424 for (; V.hasOneUse(); V = V.getOperand(0)) {
22425 switch (V.getOpcode()) {
22427 return false; // Nothing combined!
22430 // Skip bitcasts as we always know the type for the target specific
22434 case X86ISD::PSHUFLW:
22435 case X86ISD::PSHUFHW:
22436 if (V.getOpcode() == CombineOpcode)
22439 // Other-half shuffles are no-ops.
22442 // Break out of the loop if we break out of the switch.
22446 if (!V.hasOneUse())
22447 // We fell out of the loop without finding a viable combining instruction.
22450 // Combine away the bottom node as its shuffle will be accumulated into
22451 // a preceding shuffle.
22452 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22454 // Record the old value.
22457 // Merge this node's mask and our incoming mask (adjusted to account for all
22458 // the pshufd instructions encountered).
22459 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22460 for (int &M : Mask)
22462 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22463 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22465 // Check that the shuffles didn't cancel each other out. If not, we need to
22466 // combine to the new one.
22468 // Replace the combinable shuffle with the combined one, updating all users
22469 // so that we re-evaluate the chain here.
22470 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22475 /// \brief Try to combine x86 target specific shuffles.
22476 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22477 TargetLowering::DAGCombinerInfo &DCI,
22478 const X86Subtarget *Subtarget) {
22480 MVT VT = N.getSimpleValueType();
22481 SmallVector<int, 4> Mask;
22483 switch (N.getOpcode()) {
22484 case X86ISD::PSHUFD:
22485 case X86ISD::PSHUFLW:
22486 case X86ISD::PSHUFHW:
22487 Mask = getPSHUFShuffleMask(N);
22488 assert(Mask.size() == 4);
22494 // Nuke no-op shuffles that show up after combining.
22495 if (isNoopShuffleMask(Mask))
22496 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22498 // Look for simplifications involving one or two shuffle instructions.
22499 SDValue V = N.getOperand(0);
22500 switch (N.getOpcode()) {
22503 case X86ISD::PSHUFLW:
22504 case X86ISD::PSHUFHW:
22505 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22507 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22508 return SDValue(); // We combined away this shuffle, so we're done.
22510 // See if this reduces to a PSHUFD which is no more expensive and can
22511 // combine with more operations. Note that it has to at least flip the
22512 // dwords as otherwise it would have been removed as a no-op.
22513 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22514 int DMask[] = {0, 1, 2, 3};
22515 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22516 DMask[DOffset + 0] = DOffset + 1;
22517 DMask[DOffset + 1] = DOffset + 0;
22518 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22519 V = DAG.getBitcast(DVT, V);
22520 DCI.AddToWorklist(V.getNode());
22521 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22522 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22523 DCI.AddToWorklist(V.getNode());
22524 return DAG.getBitcast(VT, V);
22527 // Look for shuffle patterns which can be implemented as a single unpack.
22528 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22529 // only works when we have a PSHUFD followed by two half-shuffles.
22530 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22531 (V.getOpcode() == X86ISD::PSHUFLW ||
22532 V.getOpcode() == X86ISD::PSHUFHW) &&
22533 V.getOpcode() != N.getOpcode() &&
22535 SDValue D = V.getOperand(0);
22536 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22537 D = D.getOperand(0);
22538 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22539 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22540 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22541 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22542 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22544 for (int i = 0; i < 4; ++i) {
22545 WordMask[i + NOffset] = Mask[i] + NOffset;
22546 WordMask[i + VOffset] = VMask[i] + VOffset;
22548 // Map the word mask through the DWord mask.
22550 for (int i = 0; i < 8; ++i)
22551 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22552 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22553 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22554 // We can replace all three shuffles with an unpack.
22555 V = DAG.getBitcast(VT, D.getOperand(0));
22556 DCI.AddToWorklist(V.getNode());
22557 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22566 case X86ISD::PSHUFD:
22567 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22576 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22578 /// We combine this directly on the abstract vector shuffle nodes so it is
22579 /// easier to generically match. We also insert dummy vector shuffle nodes for
22580 /// the operands which explicitly discard the lanes which are unused by this
22581 /// operation to try to flow through the rest of the combiner the fact that
22582 /// they're unused.
22583 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22585 EVT VT = N->getValueType(0);
22587 // We only handle target-independent shuffles.
22588 // FIXME: It would be easy and harmless to use the target shuffle mask
22589 // extraction tool to support more.
22590 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22593 auto *SVN = cast<ShuffleVectorSDNode>(N);
22594 ArrayRef<int> Mask = SVN->getMask();
22595 SDValue V1 = N->getOperand(0);
22596 SDValue V2 = N->getOperand(1);
22598 // We require the first shuffle operand to be the SUB node, and the second to
22599 // be the ADD node.
22600 // FIXME: We should support the commuted patterns.
22601 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22604 // If there are other uses of these operations we can't fold them.
22605 if (!V1->hasOneUse() || !V2->hasOneUse())
22608 // Ensure that both operations have the same operands. Note that we can
22609 // commute the FADD operands.
22610 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22611 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22612 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22615 // We're looking for blends between FADD and FSUB nodes. We insist on these
22616 // nodes being lined up in a specific expected pattern.
22617 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22618 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22619 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22622 // Only specific types are legal at this point, assert so we notice if and
22623 // when these change.
22624 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22625 VT == MVT::v4f64) &&
22626 "Unknown vector type encountered!");
22628 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22631 /// PerformShuffleCombine - Performs several different shuffle combines.
22632 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22633 TargetLowering::DAGCombinerInfo &DCI,
22634 const X86Subtarget *Subtarget) {
22636 SDValue N0 = N->getOperand(0);
22637 SDValue N1 = N->getOperand(1);
22638 EVT VT = N->getValueType(0);
22640 // Don't create instructions with illegal types after legalize types has run.
22641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22642 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22645 // If we have legalized the vector types, look for blends of FADD and FSUB
22646 // nodes that we can fuse into an ADDSUB node.
22647 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22648 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22651 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22652 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22653 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22654 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22656 // During Type Legalization, when promoting illegal vector types,
22657 // the backend might introduce new shuffle dag nodes and bitcasts.
22659 // This code performs the following transformation:
22660 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22661 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22663 // We do this only if both the bitcast and the BINOP dag nodes have
22664 // one use. Also, perform this transformation only if the new binary
22665 // operation is legal. This is to avoid introducing dag nodes that
22666 // potentially need to be further expanded (or custom lowered) into a
22667 // less optimal sequence of dag nodes.
22668 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22669 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22670 N0.getOpcode() == ISD::BITCAST) {
22671 SDValue BC0 = N0.getOperand(0);
22672 EVT SVT = BC0.getValueType();
22673 unsigned Opcode = BC0.getOpcode();
22674 unsigned NumElts = VT.getVectorNumElements();
22676 if (BC0.hasOneUse() && SVT.isVector() &&
22677 SVT.getVectorNumElements() * 2 == NumElts &&
22678 TLI.isOperationLegal(Opcode, VT)) {
22679 bool CanFold = false;
22691 unsigned SVTNumElts = SVT.getVectorNumElements();
22692 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22693 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22694 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22695 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22696 CanFold = SVOp->getMaskElt(i) < 0;
22699 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22700 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22701 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22702 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22707 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22708 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22709 // consecutive, non-overlapping, and in the right order.
22710 SmallVector<SDValue, 16> Elts;
22711 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22712 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22714 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22717 if (isTargetShuffle(N->getOpcode())) {
22719 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22720 if (Shuffle.getNode())
22723 // Try recursively combining arbitrary sequences of x86 shuffle
22724 // instructions into higher-order shuffles. We do this after combining
22725 // specific PSHUF instruction sequences into their minimal form so that we
22726 // can evaluate how many specialized shuffle instructions are involved in
22727 // a particular chain.
22728 SmallVector<int, 1> NonceMask; // Just a placeholder.
22729 NonceMask.push_back(0);
22730 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22731 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22733 return SDValue(); // This routine will use CombineTo to replace N.
22739 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22740 /// specific shuffle of a load can be folded into a single element load.
22741 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22742 /// shuffles have been custom lowered so we need to handle those here.
22743 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22744 TargetLowering::DAGCombinerInfo &DCI) {
22745 if (DCI.isBeforeLegalizeOps())
22748 SDValue InVec = N->getOperand(0);
22749 SDValue EltNo = N->getOperand(1);
22751 if (!isa<ConstantSDNode>(EltNo))
22754 EVT OriginalVT = InVec.getValueType();
22756 if (InVec.getOpcode() == ISD::BITCAST) {
22757 // Don't duplicate a load with other uses.
22758 if (!InVec.hasOneUse())
22760 EVT BCVT = InVec.getOperand(0).getValueType();
22761 if (!BCVT.isVector() ||
22762 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22764 InVec = InVec.getOperand(0);
22767 EVT CurrentVT = InVec.getValueType();
22769 if (!isTargetShuffle(InVec.getOpcode()))
22772 // Don't duplicate a load with other uses.
22773 if (!InVec.hasOneUse())
22776 SmallVector<int, 16> ShuffleMask;
22778 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22779 ShuffleMask, UnaryShuffle))
22782 // Select the input vector, guarding against out of range extract vector.
22783 unsigned NumElems = CurrentVT.getVectorNumElements();
22784 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22785 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22786 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22787 : InVec.getOperand(1);
22789 // If inputs to shuffle are the same for both ops, then allow 2 uses
22790 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22791 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22793 if (LdNode.getOpcode() == ISD::BITCAST) {
22794 // Don't duplicate a load with other uses.
22795 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22798 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22799 LdNode = LdNode.getOperand(0);
22802 if (!ISD::isNormalLoad(LdNode.getNode()))
22805 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22807 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22810 EVT EltVT = N->getValueType(0);
22811 // If there's a bitcast before the shuffle, check if the load type and
22812 // alignment is valid.
22813 unsigned Align = LN0->getAlignment();
22814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22815 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22816 EltVT.getTypeForEVT(*DAG.getContext()));
22818 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22821 // All checks match so transform back to vector_shuffle so that DAG combiner
22822 // can finish the job
22825 // Create shuffle node taking into account the case that its a unary shuffle
22826 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22827 : InVec.getOperand(1);
22828 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22829 InVec.getOperand(0), Shuffle,
22831 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22832 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22836 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22837 /// special and don't usually play with other vector types, it's better to
22838 /// handle them early to be sure we emit efficient code by avoiding
22839 /// store-load conversions.
22840 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22841 if (N->getValueType(0) != MVT::x86mmx ||
22842 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22843 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22846 SDValue V = N->getOperand(0);
22847 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22848 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22849 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22850 N->getValueType(0), V.getOperand(0));
22855 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22856 /// generation and convert it from being a bunch of shuffles and extracts
22857 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22858 /// storing the value and loading scalars back, while for x64 we should
22859 /// use 64-bit extracts and shifts.
22860 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22861 TargetLowering::DAGCombinerInfo &DCI) {
22862 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22865 SDValue InputVector = N->getOperand(0);
22866 SDLoc dl(InputVector);
22867 // Detect mmx to i32 conversion through a v2i32 elt extract.
22868 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22869 N->getValueType(0) == MVT::i32 &&
22870 InputVector.getValueType() == MVT::v2i32) {
22872 // The bitcast source is a direct mmx result.
22873 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22874 if (MMXSrc.getValueType() == MVT::x86mmx)
22875 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22876 N->getValueType(0),
22877 InputVector.getNode()->getOperand(0));
22879 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22880 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22881 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22882 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22883 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22884 MMXSrcOp.getValueType() == MVT::v1i64 &&
22885 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22886 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22887 N->getValueType(0),
22888 MMXSrcOp.getOperand(0));
22891 EVT VT = N->getValueType(0);
22893 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22894 InputVector.getOpcode() == ISD::BITCAST &&
22895 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22896 uint64_t ExtractedElt =
22897 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22898 uint64_t InputValue =
22899 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22900 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22901 return DAG.getConstant(Res, dl, MVT::i1);
22903 // Only operate on vectors of 4 elements, where the alternative shuffling
22904 // gets to be more expensive.
22905 if (InputVector.getValueType() != MVT::v4i32)
22908 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22909 // single use which is a sign-extend or zero-extend, and all elements are
22911 SmallVector<SDNode *, 4> Uses;
22912 unsigned ExtractedElements = 0;
22913 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22914 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22915 if (UI.getUse().getResNo() != InputVector.getResNo())
22918 SDNode *Extract = *UI;
22919 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22922 if (Extract->getValueType(0) != MVT::i32)
22924 if (!Extract->hasOneUse())
22926 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22927 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22929 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22932 // Record which element was extracted.
22933 ExtractedElements |=
22934 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22936 Uses.push_back(Extract);
22939 // If not all the elements were used, this may not be worthwhile.
22940 if (ExtractedElements != 15)
22943 // Ok, we've now decided to do the transformation.
22944 // If 64-bit shifts are legal, use the extract-shift sequence,
22945 // otherwise bounce the vector off the cache.
22946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22949 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22950 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22951 auto &DL = DAG.getDataLayout();
22952 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22953 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22954 DAG.getConstant(0, dl, VecIdxTy));
22955 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22956 DAG.getConstant(1, dl, VecIdxTy));
22958 SDValue ShAmt = DAG.getConstant(
22959 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22960 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22961 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22962 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22963 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22964 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22965 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22967 // Store the value to a temporary stack slot.
22968 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22969 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22970 MachinePointerInfo(), false, false, 0);
22972 EVT ElementType = InputVector.getValueType().getVectorElementType();
22973 unsigned EltSize = ElementType.getSizeInBits() / 8;
22975 // Replace each use (extract) with a load of the appropriate element.
22976 for (unsigned i = 0; i < 4; ++i) {
22977 uint64_t Offset = EltSize * i;
22978 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22979 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22981 SDValue ScalarAddr =
22982 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22984 // Load the scalar.
22985 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22986 ScalarAddr, MachinePointerInfo(),
22987 false, false, false, 0);
22992 // Replace the extracts
22993 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22994 UE = Uses.end(); UI != UE; ++UI) {
22995 SDNode *Extract = *UI;
22997 SDValue Idx = Extract->getOperand(1);
22998 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22999 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23002 // The replacement was made in place; don't return anything.
23007 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23008 const X86Subtarget *Subtarget) {
23010 SDValue Cond = N->getOperand(0);
23011 SDValue LHS = N->getOperand(1);
23012 SDValue RHS = N->getOperand(2);
23014 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23015 SDValue CondSrc = Cond->getOperand(0);
23016 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23017 Cond = CondSrc->getOperand(0);
23020 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23023 // A vselect where all conditions and data are constants can be optimized into
23024 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23025 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23026 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23029 unsigned MaskValue = 0;
23030 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23033 MVT VT = N->getSimpleValueType(0);
23034 unsigned NumElems = VT.getVectorNumElements();
23035 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23036 for (unsigned i = 0; i < NumElems; ++i) {
23037 // Be sure we emit undef where we can.
23038 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23039 ShuffleMask[i] = -1;
23041 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23045 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23047 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23050 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23052 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23053 TargetLowering::DAGCombinerInfo &DCI,
23054 const X86Subtarget *Subtarget) {
23056 SDValue Cond = N->getOperand(0);
23057 // Get the LHS/RHS of the select.
23058 SDValue LHS = N->getOperand(1);
23059 SDValue RHS = N->getOperand(2);
23060 EVT VT = LHS.getValueType();
23061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23063 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23064 // instructions match the semantics of the common C idiom x<y?x:y but not
23065 // x<=y?x:y, because of how they handle negative zero (which can be
23066 // ignored in unsafe-math mode).
23067 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23068 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23069 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23070 (Subtarget->hasSSE2() ||
23071 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23072 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23074 unsigned Opcode = 0;
23075 // Check for x CC y ? x : y.
23076 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23077 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23081 // Converting this to a min would handle NaNs incorrectly, and swapping
23082 // the operands would cause it to handle comparisons between positive
23083 // and negative zero incorrectly.
23084 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23085 if (!DAG.getTarget().Options.UnsafeFPMath &&
23086 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23088 std::swap(LHS, RHS);
23090 Opcode = X86ISD::FMIN;
23093 // Converting this to a min would handle comparisons between positive
23094 // and negative zero incorrectly.
23095 if (!DAG.getTarget().Options.UnsafeFPMath &&
23096 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23098 Opcode = X86ISD::FMIN;
23101 // Converting this to a min would handle both negative zeros and NaNs
23102 // incorrectly, but we can swap the operands to fix both.
23103 std::swap(LHS, RHS);
23107 Opcode = X86ISD::FMIN;
23111 // Converting this to a max would handle comparisons between positive
23112 // and negative zero incorrectly.
23113 if (!DAG.getTarget().Options.UnsafeFPMath &&
23114 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23116 Opcode = X86ISD::FMAX;
23119 // Converting this to a max would handle NaNs incorrectly, and swapping
23120 // the operands would cause it to handle comparisons between positive
23121 // and negative zero incorrectly.
23122 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23123 if (!DAG.getTarget().Options.UnsafeFPMath &&
23124 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23126 std::swap(LHS, RHS);
23128 Opcode = X86ISD::FMAX;
23131 // Converting this to a max would handle both negative zeros and NaNs
23132 // incorrectly, but we can swap the operands to fix both.
23133 std::swap(LHS, RHS);
23137 Opcode = X86ISD::FMAX;
23140 // Check for x CC y ? y : x -- a min/max with reversed arms.
23141 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23142 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23146 // Converting this to a min would handle comparisons between positive
23147 // and negative zero incorrectly, and swapping the operands would
23148 // cause it to handle NaNs incorrectly.
23149 if (!DAG.getTarget().Options.UnsafeFPMath &&
23150 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23151 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23153 std::swap(LHS, RHS);
23155 Opcode = X86ISD::FMIN;
23158 // Converting this to a min would handle NaNs incorrectly.
23159 if (!DAG.getTarget().Options.UnsafeFPMath &&
23160 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23162 Opcode = X86ISD::FMIN;
23165 // Converting this to a min would handle both negative zeros and NaNs
23166 // incorrectly, but we can swap the operands to fix both.
23167 std::swap(LHS, RHS);
23171 Opcode = X86ISD::FMIN;
23175 // Converting this to a max would handle NaNs incorrectly.
23176 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23178 Opcode = X86ISD::FMAX;
23181 // Converting this to a max would handle comparisons between positive
23182 // and negative zero incorrectly, and swapping the operands would
23183 // cause it to handle NaNs incorrectly.
23184 if (!DAG.getTarget().Options.UnsafeFPMath &&
23185 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23186 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23188 std::swap(LHS, RHS);
23190 Opcode = X86ISD::FMAX;
23193 // Converting this to a max would handle both negative zeros and NaNs
23194 // incorrectly, but we can swap the operands to fix both.
23195 std::swap(LHS, RHS);
23199 Opcode = X86ISD::FMAX;
23205 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23208 EVT CondVT = Cond.getValueType();
23209 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23210 CondVT.getVectorElementType() == MVT::i1) {
23211 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23212 // lowering on KNL. In this case we convert it to
23213 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23214 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23215 // Since SKX these selects have a proper lowering.
23216 EVT OpVT = LHS.getValueType();
23217 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23218 (OpVT.getVectorElementType() == MVT::i8 ||
23219 OpVT.getVectorElementType() == MVT::i16) &&
23220 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23221 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23222 DCI.AddToWorklist(Cond.getNode());
23223 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23226 // If this is a select between two integer constants, try to do some
23228 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23229 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23230 // Don't do this for crazy integer types.
23231 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23232 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23233 // so that TrueC (the true value) is larger than FalseC.
23234 bool NeedsCondInvert = false;
23236 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23237 // Efficiently invertible.
23238 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23239 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23240 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23241 NeedsCondInvert = true;
23242 std::swap(TrueC, FalseC);
23245 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23246 if (FalseC->getAPIntValue() == 0 &&
23247 TrueC->getAPIntValue().isPowerOf2()) {
23248 if (NeedsCondInvert) // Invert the condition if needed.
23249 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23250 DAG.getConstant(1, DL, Cond.getValueType()));
23252 // Zero extend the condition if needed.
23253 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23255 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23256 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23257 DAG.getConstant(ShAmt, DL, MVT::i8));
23260 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23261 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23262 if (NeedsCondInvert) // Invert the condition if needed.
23263 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23264 DAG.getConstant(1, DL, Cond.getValueType()));
23266 // Zero extend the condition if needed.
23267 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23268 FalseC->getValueType(0), Cond);
23269 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23270 SDValue(FalseC, 0));
23273 // Optimize cases that will turn into an LEA instruction. This requires
23274 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23275 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23276 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23277 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23279 bool isFastMultiplier = false;
23281 switch ((unsigned char)Diff) {
23283 case 1: // result = add base, cond
23284 case 2: // result = lea base( , cond*2)
23285 case 3: // result = lea base(cond, cond*2)
23286 case 4: // result = lea base( , cond*4)
23287 case 5: // result = lea base(cond, cond*4)
23288 case 8: // result = lea base( , cond*8)
23289 case 9: // result = lea base(cond, cond*8)
23290 isFastMultiplier = true;
23295 if (isFastMultiplier) {
23296 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23297 if (NeedsCondInvert) // Invert the condition if needed.
23298 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23299 DAG.getConstant(1, DL, Cond.getValueType()));
23301 // Zero extend the condition if needed.
23302 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23304 // Scale the condition by the difference.
23306 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23307 DAG.getConstant(Diff, DL,
23308 Cond.getValueType()));
23310 // Add the base if non-zero.
23311 if (FalseC->getAPIntValue() != 0)
23312 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23313 SDValue(FalseC, 0));
23320 // Canonicalize max and min:
23321 // (x > y) ? x : y -> (x >= y) ? x : y
23322 // (x < y) ? x : y -> (x <= y) ? x : y
23323 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23324 // the need for an extra compare
23325 // against zero. e.g.
23326 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23328 // testl %edi, %edi
23330 // cmovgl %edi, %eax
23334 // cmovsl %eax, %edi
23335 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23336 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23337 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23338 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23343 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23344 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23345 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23346 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23351 // Early exit check
23352 if (!TLI.isTypeLegal(VT))
23355 // Match VSELECTs into subs with unsigned saturation.
23356 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23357 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23358 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23359 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23360 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23362 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23363 // left side invert the predicate to simplify logic below.
23365 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23367 CC = ISD::getSetCCInverse(CC, true);
23368 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23372 if (Other.getNode() && Other->getNumOperands() == 2 &&
23373 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23374 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23375 SDValue CondRHS = Cond->getOperand(1);
23377 // Look for a general sub with unsigned saturation first.
23378 // x >= y ? x-y : 0 --> subus x, y
23379 // x > y ? x-y : 0 --> subus x, y
23380 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23381 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23382 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23384 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23385 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23386 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23387 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23388 // If the RHS is a constant we have to reverse the const
23389 // canonicalization.
23390 // x > C-1 ? x+-C : 0 --> subus x, C
23391 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23392 CondRHSConst->getAPIntValue() ==
23393 (-OpRHSConst->getAPIntValue() - 1))
23394 return DAG.getNode(
23395 X86ISD::SUBUS, DL, VT, OpLHS,
23396 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23398 // Another special case: If C was a sign bit, the sub has been
23399 // canonicalized into a xor.
23400 // FIXME: Would it be better to use computeKnownBits to determine
23401 // whether it's safe to decanonicalize the xor?
23402 // x s< 0 ? x^C : 0 --> subus x, C
23403 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23404 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23405 OpRHSConst->getAPIntValue().isSignBit())
23406 // Note that we have to rebuild the RHS constant here to ensure we
23407 // don't rely on particular values of undef lanes.
23408 return DAG.getNode(
23409 X86ISD::SUBUS, DL, VT, OpLHS,
23410 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23415 // Simplify vector selection if condition value type matches vselect
23417 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23418 assert(Cond.getValueType().isVector() &&
23419 "vector select expects a vector selector!");
23421 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23422 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23424 // Try invert the condition if true value is not all 1s and false value
23426 if (!TValIsAllOnes && !FValIsAllZeros &&
23427 // Check if the selector will be produced by CMPP*/PCMP*
23428 Cond.getOpcode() == ISD::SETCC &&
23429 // Check if SETCC has already been promoted
23430 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23432 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23433 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23435 if (TValIsAllZeros || FValIsAllOnes) {
23436 SDValue CC = Cond.getOperand(2);
23437 ISD::CondCode NewCC =
23438 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23439 Cond.getOperand(0).getValueType().isInteger());
23440 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23441 std::swap(LHS, RHS);
23442 TValIsAllOnes = FValIsAllOnes;
23443 FValIsAllZeros = TValIsAllZeros;
23447 if (TValIsAllOnes || FValIsAllZeros) {
23450 if (TValIsAllOnes && FValIsAllZeros)
23452 else if (TValIsAllOnes)
23454 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23455 else if (FValIsAllZeros)
23456 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23457 DAG.getBitcast(CondVT, LHS));
23459 return DAG.getBitcast(VT, Ret);
23463 // We should generate an X86ISD::BLENDI from a vselect if its argument
23464 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23465 // constants. This specific pattern gets generated when we split a
23466 // selector for a 512 bit vector in a machine without AVX512 (but with
23467 // 256-bit vectors), during legalization:
23469 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23471 // Iff we find this pattern and the build_vectors are built from
23472 // constants, we translate the vselect into a shuffle_vector that we
23473 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23474 if ((N->getOpcode() == ISD::VSELECT ||
23475 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23476 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23477 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23478 if (Shuffle.getNode())
23482 // If this is a *dynamic* select (non-constant condition) and we can match
23483 // this node with one of the variable blend instructions, restructure the
23484 // condition so that the blends can use the high bit of each element and use
23485 // SimplifyDemandedBits to simplify the condition operand.
23486 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23487 !DCI.isBeforeLegalize() &&
23488 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23489 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23491 // Don't optimize vector selects that map to mask-registers.
23495 // We can only handle the cases where VSELECT is directly legal on the
23496 // subtarget. We custom lower VSELECT nodes with constant conditions and
23497 // this makes it hard to see whether a dynamic VSELECT will correctly
23498 // lower, so we both check the operation's status and explicitly handle the
23499 // cases where a *dynamic* blend will fail even though a constant-condition
23500 // blend could be custom lowered.
23501 // FIXME: We should find a better way to handle this class of problems.
23502 // Potentially, we should combine constant-condition vselect nodes
23503 // pre-legalization into shuffles and not mark as many types as custom
23505 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23507 // FIXME: We don't support i16-element blends currently. We could and
23508 // should support them by making *all* the bits in the condition be set
23509 // rather than just the high bit and using an i8-element blend.
23510 if (VT.getScalarType() == MVT::i16)
23512 // Dynamic blending was only available from SSE4.1 onward.
23513 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23515 // Byte blends are only available in AVX2
23516 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23517 !Subtarget->hasAVX2())
23520 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23521 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23523 APInt KnownZero, KnownOne;
23524 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23525 DCI.isBeforeLegalizeOps());
23526 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23527 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23529 // If we changed the computation somewhere in the DAG, this change
23530 // will affect all users of Cond.
23531 // Make sure it is fine and update all the nodes so that we do not
23532 // use the generic VSELECT anymore. Otherwise, we may perform
23533 // wrong optimizations as we messed up with the actual expectation
23534 // for the vector boolean values.
23535 if (Cond != TLO.Old) {
23536 // Check all uses of that condition operand to check whether it will be
23537 // consumed by non-BLEND instructions, which may depend on all bits are
23539 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23541 if (I->getOpcode() != ISD::VSELECT)
23542 // TODO: Add other opcodes eventually lowered into BLEND.
23545 // Update all the users of the condition, before committing the change,
23546 // so that the VSELECT optimizations that expect the correct vector
23547 // boolean value will not be triggered.
23548 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23550 DAG.ReplaceAllUsesOfValueWith(
23552 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23553 Cond, I->getOperand(1), I->getOperand(2)));
23554 DCI.CommitTargetLoweringOpt(TLO);
23557 // At this point, only Cond is changed. Change the condition
23558 // just for N to keep the opportunity to optimize all other
23559 // users their own way.
23560 DAG.ReplaceAllUsesOfValueWith(
23562 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23563 TLO.New, N->getOperand(1), N->getOperand(2)));
23571 // Check whether a boolean test is testing a boolean value generated by
23572 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23575 // Simplify the following patterns:
23576 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23577 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23578 // to (Op EFLAGS Cond)
23580 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23581 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23582 // to (Op EFLAGS !Cond)
23584 // where Op could be BRCOND or CMOV.
23586 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23587 // Quit if not CMP and SUB with its value result used.
23588 if (Cmp.getOpcode() != X86ISD::CMP &&
23589 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23592 // Quit if not used as a boolean value.
23593 if (CC != X86::COND_E && CC != X86::COND_NE)
23596 // Check CMP operands. One of them should be 0 or 1 and the other should be
23597 // an SetCC or extended from it.
23598 SDValue Op1 = Cmp.getOperand(0);
23599 SDValue Op2 = Cmp.getOperand(1);
23602 const ConstantSDNode* C = nullptr;
23603 bool needOppositeCond = (CC == X86::COND_E);
23604 bool checkAgainstTrue = false; // Is it a comparison against 1?
23606 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23608 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23610 else // Quit if all operands are not constants.
23613 if (C->getZExtValue() == 1) {
23614 needOppositeCond = !needOppositeCond;
23615 checkAgainstTrue = true;
23616 } else if (C->getZExtValue() != 0)
23617 // Quit if the constant is neither 0 or 1.
23620 bool truncatedToBoolWithAnd = false;
23621 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23622 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23623 SetCC.getOpcode() == ISD::TRUNCATE ||
23624 SetCC.getOpcode() == ISD::AND) {
23625 if (SetCC.getOpcode() == ISD::AND) {
23627 ConstantSDNode *CS;
23628 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23629 CS->getZExtValue() == 1)
23631 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23632 CS->getZExtValue() == 1)
23636 SetCC = SetCC.getOperand(OpIdx);
23637 truncatedToBoolWithAnd = true;
23639 SetCC = SetCC.getOperand(0);
23642 switch (SetCC.getOpcode()) {
23643 case X86ISD::SETCC_CARRY:
23644 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23645 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23646 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23647 // truncated to i1 using 'and'.
23648 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23650 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23651 "Invalid use of SETCC_CARRY!");
23653 case X86ISD::SETCC:
23654 // Set the condition code or opposite one if necessary.
23655 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23656 if (needOppositeCond)
23657 CC = X86::GetOppositeBranchCondition(CC);
23658 return SetCC.getOperand(1);
23659 case X86ISD::CMOV: {
23660 // Check whether false/true value has canonical one, i.e. 0 or 1.
23661 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23662 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23663 // Quit if true value is not a constant.
23666 // Quit if false value is not a constant.
23668 SDValue Op = SetCC.getOperand(0);
23669 // Skip 'zext' or 'trunc' node.
23670 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23671 Op.getOpcode() == ISD::TRUNCATE)
23672 Op = Op.getOperand(0);
23673 // A special case for rdrand/rdseed, where 0 is set if false cond is
23675 if ((Op.getOpcode() != X86ISD::RDRAND &&
23676 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23679 // Quit if false value is not the constant 0 or 1.
23680 bool FValIsFalse = true;
23681 if (FVal && FVal->getZExtValue() != 0) {
23682 if (FVal->getZExtValue() != 1)
23684 // If FVal is 1, opposite cond is needed.
23685 needOppositeCond = !needOppositeCond;
23686 FValIsFalse = false;
23688 // Quit if TVal is not the constant opposite of FVal.
23689 if (FValIsFalse && TVal->getZExtValue() != 1)
23691 if (!FValIsFalse && TVal->getZExtValue() != 0)
23693 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23694 if (needOppositeCond)
23695 CC = X86::GetOppositeBranchCondition(CC);
23696 return SetCC.getOperand(3);
23703 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23705 /// (X86or (X86setcc) (X86setcc))
23706 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23707 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23708 X86::CondCode &CC1, SDValue &Flags,
23710 if (Cond->getOpcode() == X86ISD::CMP) {
23711 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23712 if (!CondOp1C || !CondOp1C->isNullValue())
23715 Cond = Cond->getOperand(0);
23720 SDValue SetCC0, SetCC1;
23721 switch (Cond->getOpcode()) {
23722 default: return false;
23729 SetCC0 = Cond->getOperand(0);
23730 SetCC1 = Cond->getOperand(1);
23734 // Make sure we have SETCC nodes, using the same flags value.
23735 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23736 SetCC1.getOpcode() != X86ISD::SETCC ||
23737 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23740 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23741 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23742 Flags = SetCC0->getOperand(1);
23746 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23747 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23748 TargetLowering::DAGCombinerInfo &DCI,
23749 const X86Subtarget *Subtarget) {
23752 // If the flag operand isn't dead, don't touch this CMOV.
23753 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23756 SDValue FalseOp = N->getOperand(0);
23757 SDValue TrueOp = N->getOperand(1);
23758 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23759 SDValue Cond = N->getOperand(3);
23761 if (CC == X86::COND_E || CC == X86::COND_NE) {
23762 switch (Cond.getOpcode()) {
23766 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23767 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23768 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23774 Flags = checkBoolTestSetCCCombine(Cond, CC);
23775 if (Flags.getNode() &&
23776 // Extra check as FCMOV only supports a subset of X86 cond.
23777 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23778 SDValue Ops[] = { FalseOp, TrueOp,
23779 DAG.getConstant(CC, DL, MVT::i8), Flags };
23780 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23783 // If this is a select between two integer constants, try to do some
23784 // optimizations. Note that the operands are ordered the opposite of SELECT
23786 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23787 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23788 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23789 // larger than FalseC (the false value).
23790 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23791 CC = X86::GetOppositeBranchCondition(CC);
23792 std::swap(TrueC, FalseC);
23793 std::swap(TrueOp, FalseOp);
23796 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23797 // This is efficient for any integer data type (including i8/i16) and
23799 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23800 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23801 DAG.getConstant(CC, DL, MVT::i8), Cond);
23803 // Zero extend the condition if needed.
23804 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23806 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23807 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23808 DAG.getConstant(ShAmt, DL, MVT::i8));
23809 if (N->getNumValues() == 2) // Dead flag value?
23810 return DCI.CombineTo(N, Cond, SDValue());
23814 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23815 // for any integer data type, including i8/i16.
23816 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23817 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23818 DAG.getConstant(CC, DL, MVT::i8), Cond);
23820 // Zero extend the condition if needed.
23821 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23822 FalseC->getValueType(0), Cond);
23823 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23824 SDValue(FalseC, 0));
23826 if (N->getNumValues() == 2) // Dead flag value?
23827 return DCI.CombineTo(N, Cond, SDValue());
23831 // Optimize cases that will turn into an LEA instruction. This requires
23832 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23833 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23834 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23835 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23837 bool isFastMultiplier = false;
23839 switch ((unsigned char)Diff) {
23841 case 1: // result = add base, cond
23842 case 2: // result = lea base( , cond*2)
23843 case 3: // result = lea base(cond, cond*2)
23844 case 4: // result = lea base( , cond*4)
23845 case 5: // result = lea base(cond, cond*4)
23846 case 8: // result = lea base( , cond*8)
23847 case 9: // result = lea base(cond, cond*8)
23848 isFastMultiplier = true;
23853 if (isFastMultiplier) {
23854 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23855 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23856 DAG.getConstant(CC, DL, MVT::i8), Cond);
23857 // Zero extend the condition if needed.
23858 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23860 // Scale the condition by the difference.
23862 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23863 DAG.getConstant(Diff, DL, Cond.getValueType()));
23865 // Add the base if non-zero.
23866 if (FalseC->getAPIntValue() != 0)
23867 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23868 SDValue(FalseC, 0));
23869 if (N->getNumValues() == 2) // Dead flag value?
23870 return DCI.CombineTo(N, Cond, SDValue());
23877 // Handle these cases:
23878 // (select (x != c), e, c) -> select (x != c), e, x),
23879 // (select (x == c), c, e) -> select (x == c), x, e)
23880 // where the c is an integer constant, and the "select" is the combination
23881 // of CMOV and CMP.
23883 // The rationale for this change is that the conditional-move from a constant
23884 // needs two instructions, however, conditional-move from a register needs
23885 // only one instruction.
23887 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23888 // some instruction-combining opportunities. This opt needs to be
23889 // postponed as late as possible.
23891 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23892 // the DCI.xxxx conditions are provided to postpone the optimization as
23893 // late as possible.
23895 ConstantSDNode *CmpAgainst = nullptr;
23896 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23897 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23898 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23900 if (CC == X86::COND_NE &&
23901 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23902 CC = X86::GetOppositeBranchCondition(CC);
23903 std::swap(TrueOp, FalseOp);
23906 if (CC == X86::COND_E &&
23907 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23908 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23909 DAG.getConstant(CC, DL, MVT::i8), Cond };
23910 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23915 // Fold and/or of setcc's to double CMOV:
23916 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23917 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23919 // This combine lets us generate:
23920 // cmovcc1 (jcc1 if we don't have CMOV)
23926 // cmovne (jne if we don't have CMOV)
23927 // When we can't use the CMOV instruction, it might increase branch
23929 // When we can use CMOV, or when there is no mispredict, this improves
23930 // throughput and reduces register pressure.
23932 if (CC == X86::COND_NE) {
23934 X86::CondCode CC0, CC1;
23936 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23938 std::swap(FalseOp, TrueOp);
23939 CC0 = X86::GetOppositeBranchCondition(CC0);
23940 CC1 = X86::GetOppositeBranchCondition(CC1);
23943 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23945 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23946 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23947 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23948 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23956 /// PerformMulCombine - Optimize a single multiply with constant into two
23957 /// in order to implement it with two cheaper instructions, e.g.
23958 /// LEA + SHL, LEA + LEA.
23959 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23960 TargetLowering::DAGCombinerInfo &DCI) {
23961 // An imul is usually smaller than the alternative sequence.
23962 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23965 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23968 EVT VT = N->getValueType(0);
23969 if (VT != MVT::i64 && VT != MVT::i32)
23972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23975 uint64_t MulAmt = C->getZExtValue();
23976 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23979 uint64_t MulAmt1 = 0;
23980 uint64_t MulAmt2 = 0;
23981 if ((MulAmt % 9) == 0) {
23983 MulAmt2 = MulAmt / 9;
23984 } else if ((MulAmt % 5) == 0) {
23986 MulAmt2 = MulAmt / 5;
23987 } else if ((MulAmt % 3) == 0) {
23989 MulAmt2 = MulAmt / 3;
23992 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23995 if (isPowerOf2_64(MulAmt2) &&
23996 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23997 // If second multiplifer is pow2, issue it first. We want the multiply by
23998 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24000 std::swap(MulAmt1, MulAmt2);
24003 if (isPowerOf2_64(MulAmt1))
24004 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24005 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24007 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24008 DAG.getConstant(MulAmt1, DL, VT));
24010 if (isPowerOf2_64(MulAmt2))
24011 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24012 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24014 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24015 DAG.getConstant(MulAmt2, DL, VT));
24017 // Do not add new nodes to DAG combiner worklist.
24018 DCI.CombineTo(N, NewMul, false);
24023 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24024 SDValue N0 = N->getOperand(0);
24025 SDValue N1 = N->getOperand(1);
24026 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24027 EVT VT = N0.getValueType();
24029 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24030 // since the result of setcc_c is all zero's or all ones.
24031 if (VT.isInteger() && !VT.isVector() &&
24032 N1C && N0.getOpcode() == ISD::AND &&
24033 N0.getOperand(1).getOpcode() == ISD::Constant) {
24034 SDValue N00 = N0.getOperand(0);
24035 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24036 APInt ShAmt = N1C->getAPIntValue();
24037 Mask = Mask.shl(ShAmt);
24038 bool MaskOK = false;
24039 // We can handle cases concerning bit-widening nodes containing setcc_c if
24040 // we carefully interrogate the mask to make sure we are semantics
24042 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24043 // of the underlying setcc_c operation if the setcc_c was zero extended.
24044 // Consider the following example:
24045 // zext(setcc_c) -> i32 0x0000FFFF
24046 // c1 -> i32 0x0000FFFF
24047 // c2 -> i32 0x00000001
24048 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24049 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24050 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24052 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24053 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24055 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24056 N00.getOpcode() == ISD::ANY_EXTEND) &&
24057 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24058 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24060 if (MaskOK && Mask != 0) {
24062 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24066 // Hardware support for vector shifts is sparse which makes us scalarize the
24067 // vector operations in many cases. Also, on sandybridge ADD is faster than
24069 // (shl V, 1) -> add V,V
24070 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24071 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24072 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24073 // We shift all of the values by one. In many cases we do not have
24074 // hardware support for this operation. This is better expressed as an ADD
24076 if (N1SplatC->getAPIntValue() == 1)
24077 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24083 /// \brief Returns a vector of 0s if the node in input is a vector logical
24084 /// shift by a constant amount which is known to be bigger than or equal
24085 /// to the vector element size in bits.
24086 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24087 const X86Subtarget *Subtarget) {
24088 EVT VT = N->getValueType(0);
24090 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24091 (!Subtarget->hasInt256() ||
24092 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24095 SDValue Amt = N->getOperand(1);
24097 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24098 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24099 APInt ShiftAmt = AmtSplat->getAPIntValue();
24100 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24102 // SSE2/AVX2 logical shifts always return a vector of 0s
24103 // if the shift amount is bigger than or equal to
24104 // the element size. The constant shift amount will be
24105 // encoded as a 8-bit immediate.
24106 if (ShiftAmt.trunc(8).uge(MaxAmount))
24107 return getZeroVector(VT, Subtarget, DAG, DL);
24113 /// PerformShiftCombine - Combine shifts.
24114 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24115 TargetLowering::DAGCombinerInfo &DCI,
24116 const X86Subtarget *Subtarget) {
24117 if (N->getOpcode() == ISD::SHL)
24118 if (SDValue V = PerformSHLCombine(N, DAG))
24121 // Try to fold this logical shift into a zero vector.
24122 if (N->getOpcode() != ISD::SRA)
24123 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24129 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24130 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24131 // and friends. Likewise for OR -> CMPNEQSS.
24132 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24133 TargetLowering::DAGCombinerInfo &DCI,
24134 const X86Subtarget *Subtarget) {
24137 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24138 // we're requiring SSE2 for both.
24139 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24140 SDValue N0 = N->getOperand(0);
24141 SDValue N1 = N->getOperand(1);
24142 SDValue CMP0 = N0->getOperand(1);
24143 SDValue CMP1 = N1->getOperand(1);
24146 // The SETCCs should both refer to the same CMP.
24147 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24150 SDValue CMP00 = CMP0->getOperand(0);
24151 SDValue CMP01 = CMP0->getOperand(1);
24152 EVT VT = CMP00.getValueType();
24154 if (VT == MVT::f32 || VT == MVT::f64) {
24155 bool ExpectingFlags = false;
24156 // Check for any users that want flags:
24157 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24158 !ExpectingFlags && UI != UE; ++UI)
24159 switch (UI->getOpcode()) {
24164 ExpectingFlags = true;
24166 case ISD::CopyToReg:
24167 case ISD::SIGN_EXTEND:
24168 case ISD::ZERO_EXTEND:
24169 case ISD::ANY_EXTEND:
24173 if (!ExpectingFlags) {
24174 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24175 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24177 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24178 X86::CondCode tmp = cc0;
24183 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24184 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24185 // FIXME: need symbolic constants for these magic numbers.
24186 // See X86ATTInstPrinter.cpp:printSSECC().
24187 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24188 if (Subtarget->hasAVX512()) {
24189 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24191 DAG.getConstant(x86cc, DL, MVT::i8));
24192 if (N->getValueType(0) != MVT::i1)
24193 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24197 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24198 CMP00.getValueType(), CMP00, CMP01,
24199 DAG.getConstant(x86cc, DL,
24202 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24203 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24205 if (is64BitFP && !Subtarget->is64Bit()) {
24206 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24207 // 64-bit integer, since that's not a legal type. Since
24208 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24209 // bits, but can do this little dance to extract the lowest 32 bits
24210 // and work with those going forward.
24211 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24213 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24214 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24215 Vector32, DAG.getIntPtrConstant(0, DL));
24219 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24220 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24221 DAG.getConstant(1, DL, IntVT));
24222 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24224 return OneBitOfTruth;
24232 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24233 /// so it can be folded inside ANDNP.
24234 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24235 EVT VT = N->getValueType(0);
24237 // Match direct AllOnes for 128 and 256-bit vectors
24238 if (ISD::isBuildVectorAllOnes(N))
24241 // Look through a bit convert.
24242 if (N->getOpcode() == ISD::BITCAST)
24243 N = N->getOperand(0).getNode();
24245 // Sometimes the operand may come from a insert_subvector building a 256-bit
24247 if (VT.is256BitVector() &&
24248 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24249 SDValue V1 = N->getOperand(0);
24250 SDValue V2 = N->getOperand(1);
24252 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24253 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24254 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24255 ISD::isBuildVectorAllOnes(V2.getNode()))
24262 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24263 // register. In most cases we actually compare or select YMM-sized registers
24264 // and mixing the two types creates horrible code. This method optimizes
24265 // some of the transition sequences.
24266 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24267 TargetLowering::DAGCombinerInfo &DCI,
24268 const X86Subtarget *Subtarget) {
24269 EVT VT = N->getValueType(0);
24270 if (!VT.is256BitVector())
24273 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24274 N->getOpcode() == ISD::ZERO_EXTEND ||
24275 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24277 SDValue Narrow = N->getOperand(0);
24278 EVT NarrowVT = Narrow->getValueType(0);
24279 if (!NarrowVT.is128BitVector())
24282 if (Narrow->getOpcode() != ISD::XOR &&
24283 Narrow->getOpcode() != ISD::AND &&
24284 Narrow->getOpcode() != ISD::OR)
24287 SDValue N0 = Narrow->getOperand(0);
24288 SDValue N1 = Narrow->getOperand(1);
24291 // The Left side has to be a trunc.
24292 if (N0.getOpcode() != ISD::TRUNCATE)
24295 // The type of the truncated inputs.
24296 EVT WideVT = N0->getOperand(0)->getValueType(0);
24300 // The right side has to be a 'trunc' or a constant vector.
24301 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24302 ConstantSDNode *RHSConstSplat = nullptr;
24303 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24304 RHSConstSplat = RHSBV->getConstantSplatNode();
24305 if (!RHSTrunc && !RHSConstSplat)
24308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24310 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24313 // Set N0 and N1 to hold the inputs to the new wide operation.
24314 N0 = N0->getOperand(0);
24315 if (RHSConstSplat) {
24316 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24317 SDValue(RHSConstSplat, 0));
24318 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24319 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24320 } else if (RHSTrunc) {
24321 N1 = N1->getOperand(0);
24324 // Generate the wide operation.
24325 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24326 unsigned Opcode = N->getOpcode();
24328 case ISD::ANY_EXTEND:
24330 case ISD::ZERO_EXTEND: {
24331 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24332 APInt Mask = APInt::getAllOnesValue(InBits);
24333 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24334 return DAG.getNode(ISD::AND, DL, VT,
24335 Op, DAG.getConstant(Mask, DL, VT));
24337 case ISD::SIGN_EXTEND:
24338 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24339 Op, DAG.getValueType(NarrowVT));
24341 llvm_unreachable("Unexpected opcode");
24345 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24346 TargetLowering::DAGCombinerInfo &DCI,
24347 const X86Subtarget *Subtarget) {
24348 SDValue N0 = N->getOperand(0);
24349 SDValue N1 = N->getOperand(1);
24352 // A vector zext_in_reg may be represented as a shuffle,
24353 // feeding into a bitcast (this represents anyext) feeding into
24354 // an and with a mask.
24355 // We'd like to try to combine that into a shuffle with zero
24356 // plus a bitcast, removing the and.
24357 if (N0.getOpcode() != ISD::BITCAST ||
24358 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24361 // The other side of the AND should be a splat of 2^C, where C
24362 // is the number of bits in the source type.
24363 if (N1.getOpcode() == ISD::BITCAST)
24364 N1 = N1.getOperand(0);
24365 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24367 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24369 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24370 EVT SrcType = Shuffle->getValueType(0);
24372 // We expect a single-source shuffle
24373 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24376 unsigned SrcSize = SrcType.getScalarSizeInBits();
24378 APInt SplatValue, SplatUndef;
24379 unsigned SplatBitSize;
24381 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24382 SplatBitSize, HasAnyUndefs))
24385 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24386 // Make sure the splat matches the mask we expect
24387 if (SplatBitSize > ResSize ||
24388 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24391 // Make sure the input and output size make sense
24392 if (SrcSize >= ResSize || ResSize % SrcSize)
24395 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24396 // The number of u's between each two values depends on the ratio between
24397 // the source and dest type.
24398 unsigned ZextRatio = ResSize / SrcSize;
24399 bool IsZext = true;
24400 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24401 if (i % ZextRatio) {
24402 if (Shuffle->getMaskElt(i) > 0) {
24408 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24409 // Expected element number
24419 // Ok, perform the transformation - replace the shuffle with
24420 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24421 // (instead of undef) where the k elements come from the zero vector.
24422 SmallVector<int, 8> Mask;
24423 unsigned NumElems = SrcType.getVectorNumElements();
24424 for (unsigned i = 0; i < NumElems; ++i)
24426 Mask.push_back(NumElems);
24428 Mask.push_back(i / ZextRatio);
24430 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24431 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24432 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24435 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24436 TargetLowering::DAGCombinerInfo &DCI,
24437 const X86Subtarget *Subtarget) {
24438 if (DCI.isBeforeLegalizeOps())
24441 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24444 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24447 EVT VT = N->getValueType(0);
24448 SDValue N0 = N->getOperand(0);
24449 SDValue N1 = N->getOperand(1);
24452 // Create BEXTR instructions
24453 // BEXTR is ((X >> imm) & (2**size-1))
24454 if (VT == MVT::i32 || VT == MVT::i64) {
24455 // Check for BEXTR.
24456 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24457 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24458 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24459 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24460 if (MaskNode && ShiftNode) {
24461 uint64_t Mask = MaskNode->getZExtValue();
24462 uint64_t Shift = ShiftNode->getZExtValue();
24463 if (isMask_64(Mask)) {
24464 uint64_t MaskSize = countPopulation(Mask);
24465 if (Shift + MaskSize <= VT.getSizeInBits())
24466 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24467 DAG.getConstant(Shift | (MaskSize << 8), DL,
24476 // Want to form ANDNP nodes:
24477 // 1) In the hopes of then easily combining them with OR and AND nodes
24478 // to form PBLEND/PSIGN.
24479 // 2) To match ANDN packed intrinsics
24480 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24483 // Check LHS for vnot
24484 if (N0.getOpcode() == ISD::XOR &&
24485 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24486 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24487 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24489 // Check RHS for vnot
24490 if (N1.getOpcode() == ISD::XOR &&
24491 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24492 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24493 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24498 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24499 TargetLowering::DAGCombinerInfo &DCI,
24500 const X86Subtarget *Subtarget) {
24501 if (DCI.isBeforeLegalizeOps())
24504 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24507 SDValue N0 = N->getOperand(0);
24508 SDValue N1 = N->getOperand(1);
24509 EVT VT = N->getValueType(0);
24511 // look for psign/blend
24512 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24513 if (!Subtarget->hasSSSE3() ||
24514 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24517 // Canonicalize pandn to RHS
24518 if (N0.getOpcode() == X86ISD::ANDNP)
24520 // or (and (m, y), (pandn m, x))
24521 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24522 SDValue Mask = N1.getOperand(0);
24523 SDValue X = N1.getOperand(1);
24525 if (N0.getOperand(0) == Mask)
24526 Y = N0.getOperand(1);
24527 if (N0.getOperand(1) == Mask)
24528 Y = N0.getOperand(0);
24530 // Check to see if the mask appeared in both the AND and ANDNP and
24534 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24535 // Look through mask bitcast.
24536 if (Mask.getOpcode() == ISD::BITCAST)
24537 Mask = Mask.getOperand(0);
24538 if (X.getOpcode() == ISD::BITCAST)
24539 X = X.getOperand(0);
24540 if (Y.getOpcode() == ISD::BITCAST)
24541 Y = Y.getOperand(0);
24543 EVT MaskVT = Mask.getValueType();
24545 // Validate that the Mask operand is a vector sra node.
24546 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24547 // there is no psrai.b
24548 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24549 unsigned SraAmt = ~0;
24550 if (Mask.getOpcode() == ISD::SRA) {
24551 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24552 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24553 SraAmt = AmtConst->getZExtValue();
24554 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24555 SDValue SraC = Mask.getOperand(1);
24556 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24558 if ((SraAmt + 1) != EltBits)
24563 // Now we know we at least have a plendvb with the mask val. See if
24564 // we can form a psignb/w/d.
24565 // psign = x.type == y.type == mask.type && y = sub(0, x);
24566 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24567 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24568 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24569 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24570 "Unsupported VT for PSIGN");
24571 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24572 return DAG.getBitcast(VT, Mask);
24574 // PBLENDVB only available on SSE 4.1
24575 if (!Subtarget->hasSSE41())
24578 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24580 X = DAG.getBitcast(BlendVT, X);
24581 Y = DAG.getBitcast(BlendVT, Y);
24582 Mask = DAG.getBitcast(BlendVT, Mask);
24583 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24584 return DAG.getBitcast(VT, Mask);
24588 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24591 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24592 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24594 // SHLD/SHRD instructions have lower register pressure, but on some
24595 // platforms they have higher latency than the equivalent
24596 // series of shifts/or that would otherwise be generated.
24597 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24598 // have higher latencies and we are not optimizing for size.
24599 if (!OptForSize && Subtarget->isSHLDSlow())
24602 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24604 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24606 if (!N0.hasOneUse() || !N1.hasOneUse())
24609 SDValue ShAmt0 = N0.getOperand(1);
24610 if (ShAmt0.getValueType() != MVT::i8)
24612 SDValue ShAmt1 = N1.getOperand(1);
24613 if (ShAmt1.getValueType() != MVT::i8)
24615 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24616 ShAmt0 = ShAmt0.getOperand(0);
24617 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24618 ShAmt1 = ShAmt1.getOperand(0);
24621 unsigned Opc = X86ISD::SHLD;
24622 SDValue Op0 = N0.getOperand(0);
24623 SDValue Op1 = N1.getOperand(0);
24624 if (ShAmt0.getOpcode() == ISD::SUB) {
24625 Opc = X86ISD::SHRD;
24626 std::swap(Op0, Op1);
24627 std::swap(ShAmt0, ShAmt1);
24630 unsigned Bits = VT.getSizeInBits();
24631 if (ShAmt1.getOpcode() == ISD::SUB) {
24632 SDValue Sum = ShAmt1.getOperand(0);
24633 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24634 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24635 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24636 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24637 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24638 return DAG.getNode(Opc, DL, VT,
24640 DAG.getNode(ISD::TRUNCATE, DL,
24643 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24644 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24646 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24647 return DAG.getNode(Opc, DL, VT,
24648 N0.getOperand(0), N1.getOperand(0),
24649 DAG.getNode(ISD::TRUNCATE, DL,
24656 // Generate NEG and CMOV for integer abs.
24657 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24658 EVT VT = N->getValueType(0);
24660 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24661 // 8-bit integer abs to NEG and CMOV.
24662 if (VT.isInteger() && VT.getSizeInBits() == 8)
24665 SDValue N0 = N->getOperand(0);
24666 SDValue N1 = N->getOperand(1);
24669 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24670 // and change it to SUB and CMOV.
24671 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24672 N0.getOpcode() == ISD::ADD &&
24673 N0.getOperand(1) == N1 &&
24674 N1.getOpcode() == ISD::SRA &&
24675 N1.getOperand(0) == N0.getOperand(0))
24676 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24677 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24678 // Generate SUB & CMOV.
24679 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24680 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24682 SDValue Ops[] = { N0.getOperand(0), Neg,
24683 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24684 SDValue(Neg.getNode(), 1) };
24685 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24690 // Try to turn tests against the signbit in the form of:
24691 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24694 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24695 // This is only worth doing if the output type is i8.
24696 if (N->getValueType(0) != MVT::i8)
24699 SDValue N0 = N->getOperand(0);
24700 SDValue N1 = N->getOperand(1);
24702 // We should be performing an xor against a truncated shift.
24703 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24706 // Make sure we are performing an xor against one.
24707 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24710 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24711 SDValue Shift = N0.getOperand(0);
24712 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24715 // Make sure we are truncating from one of i16, i32 or i64.
24716 EVT ShiftTy = Shift.getValueType();
24717 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24720 // Make sure the shift amount extracts the sign bit.
24721 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24722 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24725 // Create a greater-than comparison against -1.
24726 // N.B. Using SETGE against 0 works but we want a canonical looking
24727 // comparison, using SETGT matches up with what TranslateX86CC.
24729 SDValue ShiftOp = Shift.getOperand(0);
24730 EVT ShiftOpTy = ShiftOp.getValueType();
24731 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24732 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24736 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24737 TargetLowering::DAGCombinerInfo &DCI,
24738 const X86Subtarget *Subtarget) {
24739 if (DCI.isBeforeLegalizeOps())
24742 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24745 if (Subtarget->hasCMov())
24746 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24752 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24753 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24754 TargetLowering::DAGCombinerInfo &DCI,
24755 const X86Subtarget *Subtarget) {
24756 LoadSDNode *Ld = cast<LoadSDNode>(N);
24757 EVT RegVT = Ld->getValueType(0);
24758 EVT MemVT = Ld->getMemoryVT();
24760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24762 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24763 // into two 16-byte operations.
24764 ISD::LoadExtType Ext = Ld->getExtensionType();
24766 unsigned AddressSpace = Ld->getAddressSpace();
24767 unsigned Alignment = Ld->getAlignment();
24768 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24769 Ext == ISD::NON_EXTLOAD &&
24770 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24771 AddressSpace, Alignment, &Fast) && !Fast) {
24772 unsigned NumElems = RegVT.getVectorNumElements();
24776 SDValue Ptr = Ld->getBasePtr();
24777 SDValue Increment =
24778 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24780 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24782 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24783 Ld->getPointerInfo(), Ld->isVolatile(),
24784 Ld->isNonTemporal(), Ld->isInvariant(),
24786 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24787 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24788 Ld->getPointerInfo(), Ld->isVolatile(),
24789 Ld->isNonTemporal(), Ld->isInvariant(),
24790 std::min(16U, Alignment));
24791 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24793 Load2.getValue(1));
24795 SDValue NewVec = DAG.getUNDEF(RegVT);
24796 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24797 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24798 return DCI.CombineTo(N, NewVec, TF, true);
24804 /// PerformMLOADCombine - Resolve extending loads
24805 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24806 TargetLowering::DAGCombinerInfo &DCI,
24807 const X86Subtarget *Subtarget) {
24808 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24809 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24812 EVT VT = Mld->getValueType(0);
24813 unsigned NumElems = VT.getVectorNumElements();
24814 EVT LdVT = Mld->getMemoryVT();
24817 assert(LdVT != VT && "Cannot extend to the same type");
24818 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24819 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24820 // From, To sizes and ElemCount must be pow of two
24821 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24822 "Unexpected size for extending masked load");
24824 unsigned SizeRatio = ToSz / FromSz;
24825 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24827 // Create a type on which we perform the shuffle
24828 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24829 LdVT.getScalarType(), NumElems*SizeRatio);
24830 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24832 // Convert Src0 value
24833 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24834 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24835 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24836 for (unsigned i = 0; i != NumElems; ++i)
24837 ShuffleVec[i] = i * SizeRatio;
24839 // Can't shuffle using an illegal type.
24840 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24841 "WideVecVT should be legal");
24842 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24843 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24845 // Prepare the new mask
24847 SDValue Mask = Mld->getMask();
24848 if (Mask.getValueType() == VT) {
24849 // Mask and original value have the same type
24850 NewMask = DAG.getBitcast(WideVecVT, Mask);
24851 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24852 for (unsigned i = 0; i != NumElems; ++i)
24853 ShuffleVec[i] = i * SizeRatio;
24854 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24855 ShuffleVec[i] = NumElems*SizeRatio;
24856 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24857 DAG.getConstant(0, dl, WideVecVT),
24861 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24862 unsigned WidenNumElts = NumElems*SizeRatio;
24863 unsigned MaskNumElts = VT.getVectorNumElements();
24864 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24867 unsigned NumConcat = WidenNumElts / MaskNumElts;
24868 SmallVector<SDValue, 16> Ops(NumConcat);
24869 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24871 for (unsigned i = 1; i != NumConcat; ++i)
24874 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24877 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24878 Mld->getBasePtr(), NewMask, WideSrc0,
24879 Mld->getMemoryVT(), Mld->getMemOperand(),
24881 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24882 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24884 /// PerformMSTORECombine - Resolve truncating stores
24885 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24886 const X86Subtarget *Subtarget) {
24887 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24888 if (!Mst->isTruncatingStore())
24891 EVT VT = Mst->getValue().getValueType();
24892 unsigned NumElems = VT.getVectorNumElements();
24893 EVT StVT = Mst->getMemoryVT();
24896 assert(StVT != VT && "Cannot truncate to the same type");
24897 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24898 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24902 // The truncating store is legal in some cases. For example
24903 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24904 // are designated for truncate store.
24905 // In this case we don't need any further transformations.
24906 if (TLI.isTruncStoreLegal(VT, StVT))
24909 // From, To sizes and ElemCount must be pow of two
24910 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24911 "Unexpected size for truncating masked store");
24912 // We are going to use the original vector elt for storing.
24913 // Accumulated smaller vector elements must be a multiple of the store size.
24914 assert (((NumElems * FromSz) % ToSz) == 0 &&
24915 "Unexpected ratio for truncating masked store");
24917 unsigned SizeRatio = FromSz / ToSz;
24918 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24920 // Create a type on which we perform the shuffle
24921 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24922 StVT.getScalarType(), NumElems*SizeRatio);
24924 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24926 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24927 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24928 for (unsigned i = 0; i != NumElems; ++i)
24929 ShuffleVec[i] = i * SizeRatio;
24931 // Can't shuffle using an illegal type.
24932 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24933 "WideVecVT should be legal");
24935 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24936 DAG.getUNDEF(WideVecVT),
24940 SDValue Mask = Mst->getMask();
24941 if (Mask.getValueType() == VT) {
24942 // Mask and original value have the same type
24943 NewMask = DAG.getBitcast(WideVecVT, Mask);
24944 for (unsigned i = 0; i != NumElems; ++i)
24945 ShuffleVec[i] = i * SizeRatio;
24946 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24947 ShuffleVec[i] = NumElems*SizeRatio;
24948 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24949 DAG.getConstant(0, dl, WideVecVT),
24953 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24954 unsigned WidenNumElts = NumElems*SizeRatio;
24955 unsigned MaskNumElts = VT.getVectorNumElements();
24956 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24959 unsigned NumConcat = WidenNumElts / MaskNumElts;
24960 SmallVector<SDValue, 16> Ops(NumConcat);
24961 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24963 for (unsigned i = 1; i != NumConcat; ++i)
24966 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24969 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24970 NewMask, StVT, Mst->getMemOperand(), false);
24972 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24973 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24974 const X86Subtarget *Subtarget) {
24975 StoreSDNode *St = cast<StoreSDNode>(N);
24976 EVT VT = St->getValue().getValueType();
24977 EVT StVT = St->getMemoryVT();
24979 SDValue StoredVal = St->getOperand(1);
24980 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24982 // If we are saving a concatenation of two XMM registers and 32-byte stores
24983 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24985 unsigned AddressSpace = St->getAddressSpace();
24986 unsigned Alignment = St->getAlignment();
24987 if (VT.is256BitVector() && StVT == VT &&
24988 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
24989 AddressSpace, Alignment, &Fast) && !Fast) {
24990 unsigned NumElems = VT.getVectorNumElements();
24994 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24995 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24998 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24999 SDValue Ptr0 = St->getBasePtr();
25000 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25002 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25003 St->getPointerInfo(), St->isVolatile(),
25004 St->isNonTemporal(), Alignment);
25005 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25006 St->getPointerInfo(), St->isVolatile(),
25007 St->isNonTemporal(),
25008 std::min(16U, Alignment));
25009 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25012 // Optimize trunc store (of multiple scalars) to shuffle and store.
25013 // First, pack all of the elements in one place. Next, store to memory
25014 // in fewer chunks.
25015 if (St->isTruncatingStore() && VT.isVector()) {
25016 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25017 unsigned NumElems = VT.getVectorNumElements();
25018 assert(StVT != VT && "Cannot truncate to the same type");
25019 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25020 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25022 // The truncating store is legal in some cases. For example
25023 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25024 // are designated for truncate store.
25025 // In this case we don't need any further transformations.
25026 if (TLI.isTruncStoreLegal(VT, StVT))
25029 // From, To sizes and ElemCount must be pow of two
25030 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25031 // We are going to use the original vector elt for storing.
25032 // Accumulated smaller vector elements must be a multiple of the store size.
25033 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25035 unsigned SizeRatio = FromSz / ToSz;
25037 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25039 // Create a type on which we perform the shuffle
25040 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25041 StVT.getScalarType(), NumElems*SizeRatio);
25043 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25045 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25046 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25047 for (unsigned i = 0; i != NumElems; ++i)
25048 ShuffleVec[i] = i * SizeRatio;
25050 // Can't shuffle using an illegal type.
25051 if (!TLI.isTypeLegal(WideVecVT))
25054 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25055 DAG.getUNDEF(WideVecVT),
25057 // At this point all of the data is stored at the bottom of the
25058 // register. We now need to save it to mem.
25060 // Find the largest store unit
25061 MVT StoreType = MVT::i8;
25062 for (MVT Tp : MVT::integer_valuetypes()) {
25063 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25067 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25068 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25069 (64 <= NumElems * ToSz))
25070 StoreType = MVT::f64;
25072 // Bitcast the original vector into a vector of store-size units
25073 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25074 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25075 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25076 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25077 SmallVector<SDValue, 8> Chains;
25078 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25079 TLI.getPointerTy(DAG.getDataLayout()));
25080 SDValue Ptr = St->getBasePtr();
25082 // Perform one or more big stores into memory.
25083 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25084 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25085 StoreType, ShuffWide,
25086 DAG.getIntPtrConstant(i, dl));
25087 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25088 St->getPointerInfo(), St->isVolatile(),
25089 St->isNonTemporal(), St->getAlignment());
25090 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25091 Chains.push_back(Ch);
25094 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25097 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25098 // the FP state in cases where an emms may be missing.
25099 // A preferable solution to the general problem is to figure out the right
25100 // places to insert EMMS. This qualifies as a quick hack.
25102 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25103 if (VT.getSizeInBits() != 64)
25106 const Function *F = DAG.getMachineFunction().getFunction();
25107 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25109 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25110 if ((VT.isVector() ||
25111 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25112 isa<LoadSDNode>(St->getValue()) &&
25113 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25114 St->getChain().hasOneUse() && !St->isVolatile()) {
25115 SDNode* LdVal = St->getValue().getNode();
25116 LoadSDNode *Ld = nullptr;
25117 int TokenFactorIndex = -1;
25118 SmallVector<SDValue, 8> Ops;
25119 SDNode* ChainVal = St->getChain().getNode();
25120 // Must be a store of a load. We currently handle two cases: the load
25121 // is a direct child, and it's under an intervening TokenFactor. It is
25122 // possible to dig deeper under nested TokenFactors.
25123 if (ChainVal == LdVal)
25124 Ld = cast<LoadSDNode>(St->getChain());
25125 else if (St->getValue().hasOneUse() &&
25126 ChainVal->getOpcode() == ISD::TokenFactor) {
25127 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25128 if (ChainVal->getOperand(i).getNode() == LdVal) {
25129 TokenFactorIndex = i;
25130 Ld = cast<LoadSDNode>(St->getValue());
25132 Ops.push_back(ChainVal->getOperand(i));
25136 if (!Ld || !ISD::isNormalLoad(Ld))
25139 // If this is not the MMX case, i.e. we are just turning i64 load/store
25140 // into f64 load/store, avoid the transformation if there are multiple
25141 // uses of the loaded value.
25142 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25147 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25148 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25150 if (Subtarget->is64Bit() || F64IsLegal) {
25151 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25152 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25153 Ld->getPointerInfo(), Ld->isVolatile(),
25154 Ld->isNonTemporal(), Ld->isInvariant(),
25155 Ld->getAlignment());
25156 SDValue NewChain = NewLd.getValue(1);
25157 if (TokenFactorIndex != -1) {
25158 Ops.push_back(NewChain);
25159 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25161 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25162 St->getPointerInfo(),
25163 St->isVolatile(), St->isNonTemporal(),
25164 St->getAlignment());
25167 // Otherwise, lower to two pairs of 32-bit loads / stores.
25168 SDValue LoAddr = Ld->getBasePtr();
25169 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25170 DAG.getConstant(4, LdDL, MVT::i32));
25172 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25173 Ld->getPointerInfo(),
25174 Ld->isVolatile(), Ld->isNonTemporal(),
25175 Ld->isInvariant(), Ld->getAlignment());
25176 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25177 Ld->getPointerInfo().getWithOffset(4),
25178 Ld->isVolatile(), Ld->isNonTemporal(),
25180 MinAlign(Ld->getAlignment(), 4));
25182 SDValue NewChain = LoLd.getValue(1);
25183 if (TokenFactorIndex != -1) {
25184 Ops.push_back(LoLd);
25185 Ops.push_back(HiLd);
25186 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25189 LoAddr = St->getBasePtr();
25190 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25191 DAG.getConstant(4, StDL, MVT::i32));
25193 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25194 St->getPointerInfo(),
25195 St->isVolatile(), St->isNonTemporal(),
25196 St->getAlignment());
25197 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25198 St->getPointerInfo().getWithOffset(4),
25200 St->isNonTemporal(),
25201 MinAlign(St->getAlignment(), 4));
25202 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25205 // This is similar to the above case, but here we handle a scalar 64-bit
25206 // integer store that is extracted from a vector on a 32-bit target.
25207 // If we have SSE2, then we can treat it like a floating-point double
25208 // to get past legalization. The execution dependencies fixup pass will
25209 // choose the optimal machine instruction for the store if this really is
25210 // an integer or v2f32 rather than an f64.
25211 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25212 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25213 SDValue OldExtract = St->getOperand(1);
25214 SDValue ExtOp0 = OldExtract.getOperand(0);
25215 unsigned VecSize = ExtOp0.getValueSizeInBits();
25216 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25217 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25218 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25219 BitCast, OldExtract.getOperand(1));
25220 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25221 St->getPointerInfo(), St->isVolatile(),
25222 St->isNonTemporal(), St->getAlignment());
25228 /// Return 'true' if this vector operation is "horizontal"
25229 /// and return the operands for the horizontal operation in LHS and RHS. A
25230 /// horizontal operation performs the binary operation on successive elements
25231 /// of its first operand, then on successive elements of its second operand,
25232 /// returning the resulting values in a vector. For example, if
25233 /// A = < float a0, float a1, float a2, float a3 >
25235 /// B = < float b0, float b1, float b2, float b3 >
25236 /// then the result of doing a horizontal operation on A and B is
25237 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25238 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25239 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25240 /// set to A, RHS to B, and the routine returns 'true'.
25241 /// Note that the binary operation should have the property that if one of the
25242 /// operands is UNDEF then the result is UNDEF.
25243 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25244 // Look for the following pattern: if
25245 // A = < float a0, float a1, float a2, float a3 >
25246 // B = < float b0, float b1, float b2, float b3 >
25248 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25249 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25250 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25251 // which is A horizontal-op B.
25253 // At least one of the operands should be a vector shuffle.
25254 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25255 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25258 MVT VT = LHS.getSimpleValueType();
25260 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25261 "Unsupported vector type for horizontal add/sub");
25263 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25264 // operate independently on 128-bit lanes.
25265 unsigned NumElts = VT.getVectorNumElements();
25266 unsigned NumLanes = VT.getSizeInBits()/128;
25267 unsigned NumLaneElts = NumElts / NumLanes;
25268 assert((NumLaneElts % 2 == 0) &&
25269 "Vector type should have an even number of elements in each lane");
25270 unsigned HalfLaneElts = NumLaneElts/2;
25272 // View LHS in the form
25273 // LHS = VECTOR_SHUFFLE A, B, LMask
25274 // If LHS is not a shuffle then pretend it is the shuffle
25275 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25276 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25279 SmallVector<int, 16> LMask(NumElts);
25280 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25281 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25282 A = LHS.getOperand(0);
25283 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25284 B = LHS.getOperand(1);
25285 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25286 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25288 if (LHS.getOpcode() != ISD::UNDEF)
25290 for (unsigned i = 0; i != NumElts; ++i)
25294 // Likewise, view RHS in the form
25295 // RHS = VECTOR_SHUFFLE C, D, RMask
25297 SmallVector<int, 16> RMask(NumElts);
25298 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25299 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25300 C = RHS.getOperand(0);
25301 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25302 D = RHS.getOperand(1);
25303 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25304 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25306 if (RHS.getOpcode() != ISD::UNDEF)
25308 for (unsigned i = 0; i != NumElts; ++i)
25312 // Check that the shuffles are both shuffling the same vectors.
25313 if (!(A == C && B == D) && !(A == D && B == C))
25316 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25317 if (!A.getNode() && !B.getNode())
25320 // If A and B occur in reverse order in RHS, then "swap" them (which means
25321 // rewriting the mask).
25323 ShuffleVectorSDNode::commuteMask(RMask);
25325 // At this point LHS and RHS are equivalent to
25326 // LHS = VECTOR_SHUFFLE A, B, LMask
25327 // RHS = VECTOR_SHUFFLE A, B, RMask
25328 // Check that the masks correspond to performing a horizontal operation.
25329 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25330 for (unsigned i = 0; i != NumLaneElts; ++i) {
25331 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25333 // Ignore any UNDEF components.
25334 if (LIdx < 0 || RIdx < 0 ||
25335 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25336 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25339 // Check that successive elements are being operated on. If not, this is
25340 // not a horizontal operation.
25341 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25342 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25343 if (!(LIdx == Index && RIdx == Index + 1) &&
25344 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25349 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25350 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25354 /// Do target-specific dag combines on floating point adds.
25355 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25356 const X86Subtarget *Subtarget) {
25357 EVT VT = N->getValueType(0);
25358 SDValue LHS = N->getOperand(0);
25359 SDValue RHS = N->getOperand(1);
25361 // Try to synthesize horizontal adds from adds of shuffles.
25362 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25363 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25364 isHorizontalBinOp(LHS, RHS, true))
25365 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25369 /// Do target-specific dag combines on floating point subs.
25370 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25371 const X86Subtarget *Subtarget) {
25372 EVT VT = N->getValueType(0);
25373 SDValue LHS = N->getOperand(0);
25374 SDValue RHS = N->getOperand(1);
25376 // Try to synthesize horizontal subs from subs of shuffles.
25377 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25378 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25379 isHorizontalBinOp(LHS, RHS, false))
25380 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25384 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25385 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25386 const X86Subtarget *Subtarget) {
25387 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25389 // F[X]OR(0.0, x) -> x
25390 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25391 if (C->getValueAPF().isPosZero())
25392 return N->getOperand(1);
25394 // F[X]OR(x, 0.0) -> x
25395 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25396 if (C->getValueAPF().isPosZero())
25397 return N->getOperand(0);
25399 EVT VT = N->getValueType(0);
25400 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25402 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25403 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25405 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25406 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25407 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25408 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25409 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25414 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25415 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25416 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25418 // Only perform optimizations if UnsafeMath is used.
25419 if (!DAG.getTarget().Options.UnsafeFPMath)
25422 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25423 // into FMINC and FMAXC, which are Commutative operations.
25424 unsigned NewOp = 0;
25425 switch (N->getOpcode()) {
25426 default: llvm_unreachable("unknown opcode");
25427 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25428 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25431 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25432 N->getOperand(0), N->getOperand(1));
25435 /// Do target-specific dag combines on X86ISD::FAND nodes.
25436 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25437 // FAND(0.0, x) -> 0.0
25438 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25439 if (C->getValueAPF().isPosZero())
25440 return N->getOperand(0);
25442 // FAND(x, 0.0) -> 0.0
25443 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25444 if (C->getValueAPF().isPosZero())
25445 return N->getOperand(1);
25450 /// Do target-specific dag combines on X86ISD::FANDN nodes
25451 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25452 // FANDN(0.0, x) -> x
25453 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25454 if (C->getValueAPF().isPosZero())
25455 return N->getOperand(1);
25457 // FANDN(x, 0.0) -> 0.0
25458 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25459 if (C->getValueAPF().isPosZero())
25460 return N->getOperand(1);
25465 static SDValue PerformBTCombine(SDNode *N,
25467 TargetLowering::DAGCombinerInfo &DCI) {
25468 // BT ignores high bits in the bit index operand.
25469 SDValue Op1 = N->getOperand(1);
25470 if (Op1.hasOneUse()) {
25471 unsigned BitWidth = Op1.getValueSizeInBits();
25472 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25473 APInt KnownZero, KnownOne;
25474 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25475 !DCI.isBeforeLegalizeOps());
25476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25477 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25478 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25479 DCI.CommitTargetLoweringOpt(TLO);
25484 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25485 SDValue Op = N->getOperand(0);
25486 if (Op.getOpcode() == ISD::BITCAST)
25487 Op = Op.getOperand(0);
25488 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25489 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25490 VT.getVectorElementType().getSizeInBits() ==
25491 OpVT.getVectorElementType().getSizeInBits()) {
25492 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25497 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25498 const X86Subtarget *Subtarget) {
25499 EVT VT = N->getValueType(0);
25500 if (!VT.isVector())
25503 SDValue N0 = N->getOperand(0);
25504 SDValue N1 = N->getOperand(1);
25505 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25508 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25509 // both SSE and AVX2 since there is no sign-extended shift right
25510 // operation on a vector with 64-bit elements.
25511 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25512 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25513 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25514 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25515 SDValue N00 = N0.getOperand(0);
25517 // EXTLOAD has a better solution on AVX2,
25518 // it may be replaced with X86ISD::VSEXT node.
25519 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25520 if (!ISD::isNormalLoad(N00.getNode()))
25523 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25524 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25526 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25532 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25533 TargetLowering::DAGCombinerInfo &DCI,
25534 const X86Subtarget *Subtarget) {
25535 SDValue N0 = N->getOperand(0);
25536 EVT VT = N->getValueType(0);
25537 EVT SVT = VT.getScalarType();
25538 EVT InVT = N0.getValueType();
25539 EVT InSVT = InVT.getScalarType();
25542 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25543 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25544 // This exposes the sext to the sdivrem lowering, so that it directly extends
25545 // from AH (which we otherwise need to do contortions to access).
25546 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25547 InVT == MVT::i8 && VT == MVT::i32) {
25548 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25549 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25550 N0.getOperand(0), N0.getOperand(1));
25551 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25552 return R.getValue(1);
25555 if (!DCI.isBeforeLegalizeOps()) {
25556 if (InVT == MVT::i1) {
25557 SDValue Zero = DAG.getConstant(0, DL, VT);
25559 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25560 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25565 if (VT.isVector() && Subtarget->hasSSE2()) {
25566 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25567 EVT InVT = N.getValueType();
25568 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25569 Size / InVT.getScalarSizeInBits());
25570 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25571 DAG.getUNDEF(InVT));
25573 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25576 // If target-size is less than 128-bits, extend to a type that would extend
25577 // to 128 bits, extend that and extract the original target vector.
25578 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25579 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25580 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25581 unsigned Scale = 128 / VT.getSizeInBits();
25583 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25584 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25585 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25586 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25587 DAG.getIntPtrConstant(0, DL));
25590 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25591 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25592 if (VT.getSizeInBits() == 128 &&
25593 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25594 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25595 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25596 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25599 // On pre-AVX2 targets, split into 128-bit nodes of
25600 // ISD::SIGN_EXTEND_VECTOR_INREG.
25601 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25602 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25603 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25604 unsigned NumVecs = VT.getSizeInBits() / 128;
25605 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25606 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25607 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25609 SmallVector<SDValue, 8> Opnds;
25610 for (unsigned i = 0, Offset = 0; i != NumVecs;
25611 ++i, Offset += NumSubElts) {
25612 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25613 DAG.getIntPtrConstant(Offset, DL));
25614 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25615 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25616 Opnds.push_back(SrcVec);
25618 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25622 if (!Subtarget->hasFp256())
25625 if (VT.isVector() && VT.getSizeInBits() == 256)
25626 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25632 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25633 const X86Subtarget* Subtarget) {
25635 EVT VT = N->getValueType(0);
25637 // Let legalize expand this if it isn't a legal type yet.
25638 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25641 EVT ScalarVT = VT.getScalarType();
25642 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25643 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25644 !Subtarget->hasAVX512()))
25647 SDValue A = N->getOperand(0);
25648 SDValue B = N->getOperand(1);
25649 SDValue C = N->getOperand(2);
25651 bool NegA = (A.getOpcode() == ISD::FNEG);
25652 bool NegB = (B.getOpcode() == ISD::FNEG);
25653 bool NegC = (C.getOpcode() == ISD::FNEG);
25655 // Negative multiplication when NegA xor NegB
25656 bool NegMul = (NegA != NegB);
25658 A = A.getOperand(0);
25660 B = B.getOperand(0);
25662 C = C.getOperand(0);
25666 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25668 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25670 return DAG.getNode(Opcode, dl, VT, A, B, C);
25673 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25674 TargetLowering::DAGCombinerInfo &DCI,
25675 const X86Subtarget *Subtarget) {
25676 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25677 // (and (i32 x86isd::setcc_carry), 1)
25678 // This eliminates the zext. This transformation is necessary because
25679 // ISD::SETCC is always legalized to i8.
25681 SDValue N0 = N->getOperand(0);
25682 EVT VT = N->getValueType(0);
25684 if (N0.getOpcode() == ISD::AND &&
25686 N0.getOperand(0).hasOneUse()) {
25687 SDValue N00 = N0.getOperand(0);
25688 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25689 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25690 if (!C || C->getZExtValue() != 1)
25692 return DAG.getNode(ISD::AND, dl, VT,
25693 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25694 N00.getOperand(0), N00.getOperand(1)),
25695 DAG.getConstant(1, dl, VT));
25699 if (N0.getOpcode() == ISD::TRUNCATE &&
25701 N0.getOperand(0).hasOneUse()) {
25702 SDValue N00 = N0.getOperand(0);
25703 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25704 return DAG.getNode(ISD::AND, dl, VT,
25705 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25706 N00.getOperand(0), N00.getOperand(1)),
25707 DAG.getConstant(1, dl, VT));
25711 if (VT.is256BitVector())
25712 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25715 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25716 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25717 // This exposes the zext to the udivrem lowering, so that it directly extends
25718 // from AH (which we otherwise need to do contortions to access).
25719 if (N0.getOpcode() == ISD::UDIVREM &&
25720 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25721 (VT == MVT::i32 || VT == MVT::i64)) {
25722 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25723 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25724 N0.getOperand(0), N0.getOperand(1));
25725 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25726 return R.getValue(1);
25732 // Optimize x == -y --> x+y == 0
25733 // x != -y --> x+y != 0
25734 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25735 const X86Subtarget* Subtarget) {
25736 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25737 SDValue LHS = N->getOperand(0);
25738 SDValue RHS = N->getOperand(1);
25739 EVT VT = N->getValueType(0);
25742 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25743 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25744 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25745 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25746 LHS.getOperand(1));
25747 return DAG.getSetCC(DL, N->getValueType(0), addV,
25748 DAG.getConstant(0, DL, addV.getValueType()), CC);
25750 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25751 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25752 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25753 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25754 RHS.getOperand(1));
25755 return DAG.getSetCC(DL, N->getValueType(0), addV,
25756 DAG.getConstant(0, DL, addV.getValueType()), CC);
25759 if (VT.getScalarType() == MVT::i1 &&
25760 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25762 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25763 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25764 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25766 if (!IsSEXT0 || !IsVZero1) {
25767 // Swap the operands and update the condition code.
25768 std::swap(LHS, RHS);
25769 CC = ISD::getSetCCSwappedOperands(CC);
25771 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25772 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25773 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25776 if (IsSEXT0 && IsVZero1) {
25777 assert(VT == LHS.getOperand(0).getValueType() &&
25778 "Uexpected operand type");
25779 if (CC == ISD::SETGT)
25780 return DAG.getConstant(0, DL, VT);
25781 if (CC == ISD::SETLE)
25782 return DAG.getConstant(1, DL, VT);
25783 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25784 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25786 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25787 "Unexpected condition code!");
25788 return LHS.getOperand(0);
25795 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25796 SelectionDAG &DAG) {
25798 MVT VT = Load->getSimpleValueType(0);
25799 MVT EVT = VT.getVectorElementType();
25800 SDValue Addr = Load->getOperand(1);
25801 SDValue NewAddr = DAG.getNode(
25802 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25803 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25804 Addr.getSimpleValueType()));
25807 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25808 DAG.getMachineFunction().getMachineMemOperand(
25809 Load->getMemOperand(), 0, EVT.getStoreSize()));
25813 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25814 const X86Subtarget *Subtarget) {
25816 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25817 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25818 "X86insertps is only defined for v4x32");
25820 SDValue Ld = N->getOperand(1);
25821 if (MayFoldLoad(Ld)) {
25822 // Extract the countS bits from the immediate so we can get the proper
25823 // address when narrowing the vector load to a specific element.
25824 // When the second source op is a memory address, insertps doesn't use
25825 // countS and just gets an f32 from that address.
25826 unsigned DestIndex =
25827 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25829 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25831 // Create this as a scalar to vector to match the instruction pattern.
25832 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25833 // countS bits are ignored when loading from memory on insertps, which
25834 // means we don't need to explicitly set them to 0.
25835 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25836 LoadScalarToVector, N->getOperand(2));
25841 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25842 SDValue V0 = N->getOperand(0);
25843 SDValue V1 = N->getOperand(1);
25845 EVT VT = N->getValueType(0);
25847 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25848 // operands and changing the mask to 1. This saves us a bunch of
25849 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25850 // x86InstrInfo knows how to commute this back after instruction selection
25851 // if it would help register allocation.
25853 // TODO: If optimizing for size or a processor that doesn't suffer from
25854 // partial register update stalls, this should be transformed into a MOVSD
25855 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25857 if (VT == MVT::v2f64)
25858 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25859 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25860 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25861 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25867 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25868 // as "sbb reg,reg", since it can be extended without zext and produces
25869 // an all-ones bit which is more useful than 0/1 in some cases.
25870 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25873 return DAG.getNode(ISD::AND, DL, VT,
25874 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25875 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25877 DAG.getConstant(1, DL, VT));
25878 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25879 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25880 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25881 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25885 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25886 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25887 TargetLowering::DAGCombinerInfo &DCI,
25888 const X86Subtarget *Subtarget) {
25890 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25891 SDValue EFLAGS = N->getOperand(1);
25893 if (CC == X86::COND_A) {
25894 // Try to convert COND_A into COND_B in an attempt to facilitate
25895 // materializing "setb reg".
25897 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25898 // cannot take an immediate as its first operand.
25900 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25901 EFLAGS.getValueType().isInteger() &&
25902 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25903 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25904 EFLAGS.getNode()->getVTList(),
25905 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25906 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25907 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25911 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25912 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25914 if (CC == X86::COND_B)
25915 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25917 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25918 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25919 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25925 // Optimize branch condition evaluation.
25927 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25928 TargetLowering::DAGCombinerInfo &DCI,
25929 const X86Subtarget *Subtarget) {
25931 SDValue Chain = N->getOperand(0);
25932 SDValue Dest = N->getOperand(1);
25933 SDValue EFLAGS = N->getOperand(3);
25934 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25936 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25937 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25938 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25945 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25946 SelectionDAG &DAG) {
25947 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25948 // optimize away operation when it's from a constant.
25950 // The general transformation is:
25951 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25952 // AND(VECTOR_CMP(x,y), constant2)
25953 // constant2 = UNARYOP(constant)
25955 // Early exit if this isn't a vector operation, the operand of the
25956 // unary operation isn't a bitwise AND, or if the sizes of the operations
25957 // aren't the same.
25958 EVT VT = N->getValueType(0);
25959 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25960 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25961 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25964 // Now check that the other operand of the AND is a constant. We could
25965 // make the transformation for non-constant splats as well, but it's unclear
25966 // that would be a benefit as it would not eliminate any operations, just
25967 // perform one more step in scalar code before moving to the vector unit.
25968 if (BuildVectorSDNode *BV =
25969 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25970 // Bail out if the vector isn't a constant.
25971 if (!BV->isConstant())
25974 // Everything checks out. Build up the new and improved node.
25976 EVT IntVT = BV->getValueType(0);
25977 // Create a new constant of the appropriate type for the transformed
25979 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25980 // The AND node needs bitcasts to/from an integer vector type around it.
25981 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
25982 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25983 N->getOperand(0)->getOperand(0), MaskConst);
25984 SDValue Res = DAG.getBitcast(VT, NewAnd);
25991 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25992 const X86Subtarget *Subtarget) {
25993 SDValue Op0 = N->getOperand(0);
25994 EVT VT = N->getValueType(0);
25995 EVT InVT = Op0.getValueType();
25996 EVT InSVT = InVT.getScalarType();
25997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25999 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26000 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26001 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26003 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26004 InVT.getVectorNumElements());
26005 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26007 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26008 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26010 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26016 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26017 const X86Subtarget *Subtarget) {
26018 // First try to optimize away the conversion entirely when it's
26019 // conditionally from a constant. Vectors only.
26020 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26023 // Now move on to more general possibilities.
26024 SDValue Op0 = N->getOperand(0);
26025 EVT VT = N->getValueType(0);
26026 EVT InVT = Op0.getValueType();
26027 EVT InSVT = InVT.getScalarType();
26029 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26030 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26031 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26033 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26034 InVT.getVectorNumElements());
26035 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26036 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26039 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26040 // a 32-bit target where SSE doesn't support i64->FP operations.
26041 if (Op0.getOpcode() == ISD::LOAD) {
26042 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26043 EVT LdVT = Ld->getValueType(0);
26045 // This transformation is not supported if the result type is f16
26046 if (VT == MVT::f16)
26049 if (!Ld->isVolatile() && !VT.isVector() &&
26050 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26051 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26052 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26053 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26054 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26061 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26062 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26063 X86TargetLowering::DAGCombinerInfo &DCI) {
26064 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26065 // the result is either zero or one (depending on the input carry bit).
26066 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26067 if (X86::isZeroNode(N->getOperand(0)) &&
26068 X86::isZeroNode(N->getOperand(1)) &&
26069 // We don't have a good way to replace an EFLAGS use, so only do this when
26071 SDValue(N, 1).use_empty()) {
26073 EVT VT = N->getValueType(0);
26074 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26075 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26076 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26077 DAG.getConstant(X86::COND_B, DL,
26080 DAG.getConstant(1, DL, VT));
26081 return DCI.CombineTo(N, Res1, CarryOut);
26087 // fold (add Y, (sete X, 0)) -> adc 0, Y
26088 // (add Y, (setne X, 0)) -> sbb -1, Y
26089 // (sub (sete X, 0), Y) -> sbb 0, Y
26090 // (sub (setne X, 0), Y) -> adc -1, Y
26091 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26094 // Look through ZExts.
26095 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26096 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26099 SDValue SetCC = Ext.getOperand(0);
26100 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26103 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26104 if (CC != X86::COND_E && CC != X86::COND_NE)
26107 SDValue Cmp = SetCC.getOperand(1);
26108 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26109 !X86::isZeroNode(Cmp.getOperand(1)) ||
26110 !Cmp.getOperand(0).getValueType().isInteger())
26113 SDValue CmpOp0 = Cmp.getOperand(0);
26114 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26115 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26117 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26118 if (CC == X86::COND_NE)
26119 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26120 DL, OtherVal.getValueType(), OtherVal,
26121 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26123 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26124 DL, OtherVal.getValueType(), OtherVal,
26125 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26128 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26129 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26130 const X86Subtarget *Subtarget) {
26131 EVT VT = N->getValueType(0);
26132 SDValue Op0 = N->getOperand(0);
26133 SDValue Op1 = N->getOperand(1);
26135 // Try to synthesize horizontal adds from adds of shuffles.
26136 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26137 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26138 isHorizontalBinOp(Op0, Op1, true))
26139 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26141 return OptimizeConditionalInDecrement(N, DAG);
26144 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26145 const X86Subtarget *Subtarget) {
26146 SDValue Op0 = N->getOperand(0);
26147 SDValue Op1 = N->getOperand(1);
26149 // X86 can't encode an immediate LHS of a sub. See if we can push the
26150 // negation into a preceding instruction.
26151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26152 // If the RHS of the sub is a XOR with one use and a constant, invert the
26153 // immediate. Then add one to the LHS of the sub so we can turn
26154 // X-Y -> X+~Y+1, saving one register.
26155 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26156 isa<ConstantSDNode>(Op1.getOperand(1))) {
26157 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26158 EVT VT = Op0.getValueType();
26159 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26161 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26162 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26163 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26167 // Try to synthesize horizontal adds from adds of shuffles.
26168 EVT VT = N->getValueType(0);
26169 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26170 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26171 isHorizontalBinOp(Op0, Op1, true))
26172 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26174 return OptimizeConditionalInDecrement(N, DAG);
26177 /// performVZEXTCombine - Performs build vector combines
26178 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26179 TargetLowering::DAGCombinerInfo &DCI,
26180 const X86Subtarget *Subtarget) {
26182 MVT VT = N->getSimpleValueType(0);
26183 SDValue Op = N->getOperand(0);
26184 MVT OpVT = Op.getSimpleValueType();
26185 MVT OpEltVT = OpVT.getVectorElementType();
26186 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26188 // (vzext (bitcast (vzext (x)) -> (vzext x)
26190 while (V.getOpcode() == ISD::BITCAST)
26191 V = V.getOperand(0);
26193 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26194 MVT InnerVT = V.getSimpleValueType();
26195 MVT InnerEltVT = InnerVT.getVectorElementType();
26197 // If the element sizes match exactly, we can just do one larger vzext. This
26198 // is always an exact type match as vzext operates on integer types.
26199 if (OpEltVT == InnerEltVT) {
26200 assert(OpVT == InnerVT && "Types must match for vzext!");
26201 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26204 // The only other way we can combine them is if only a single element of the
26205 // inner vzext is used in the input to the outer vzext.
26206 if (InnerEltVT.getSizeInBits() < InputBits)
26209 // In this case, the inner vzext is completely dead because we're going to
26210 // only look at bits inside of the low element. Just do the outer vzext on
26211 // a bitcast of the input to the inner.
26212 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26215 // Check if we can bypass extracting and re-inserting an element of an input
26216 // vector. Essentially:
26217 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26218 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26219 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26220 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26221 SDValue ExtractedV = V.getOperand(0);
26222 SDValue OrigV = ExtractedV.getOperand(0);
26223 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26224 if (ExtractIdx->getZExtValue() == 0) {
26225 MVT OrigVT = OrigV.getSimpleValueType();
26226 // Extract a subvector if necessary...
26227 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26228 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26229 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26230 OrigVT.getVectorNumElements() / Ratio);
26231 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26232 DAG.getIntPtrConstant(0, DL));
26234 Op = DAG.getBitcast(OpVT, OrigV);
26235 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26242 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26243 DAGCombinerInfo &DCI) const {
26244 SelectionDAG &DAG = DCI.DAG;
26245 switch (N->getOpcode()) {
26247 case ISD::EXTRACT_VECTOR_ELT:
26248 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26251 case X86ISD::SHRUNKBLEND:
26252 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26253 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26254 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26255 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26256 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26257 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26258 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26261 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26262 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26263 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26264 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26265 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26266 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26267 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26268 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26269 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26270 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26271 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26272 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26274 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26276 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26277 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26278 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26279 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26280 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26281 case ISD::ANY_EXTEND:
26282 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26283 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26284 case ISD::SIGN_EXTEND_INREG:
26285 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26286 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26287 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26288 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26289 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26290 case X86ISD::SHUFP: // Handle all target specific shuffles
26291 case X86ISD::PALIGNR:
26292 case X86ISD::UNPCKH:
26293 case X86ISD::UNPCKL:
26294 case X86ISD::MOVHLPS:
26295 case X86ISD::MOVLHPS:
26296 case X86ISD::PSHUFB:
26297 case X86ISD::PSHUFD:
26298 case X86ISD::PSHUFHW:
26299 case X86ISD::PSHUFLW:
26300 case X86ISD::MOVSS:
26301 case X86ISD::MOVSD:
26302 case X86ISD::VPERMILPI:
26303 case X86ISD::VPERM2X128:
26304 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26305 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26306 case X86ISD::INSERTPS: {
26307 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26308 return PerformINSERTPSCombine(N, DAG, Subtarget);
26311 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26317 /// isTypeDesirableForOp - Return true if the target has native support for
26318 /// the specified value type and it is 'desirable' to use the type for the
26319 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26320 /// instruction encodings are longer and some i16 instructions are slow.
26321 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26322 if (!isTypeLegal(VT))
26324 if (VT != MVT::i16)
26331 case ISD::SIGN_EXTEND:
26332 case ISD::ZERO_EXTEND:
26333 case ISD::ANY_EXTEND:
26346 /// IsDesirableToPromoteOp - This method query the target whether it is
26347 /// beneficial for dag combiner to promote the specified node. If true, it
26348 /// should return the desired promotion type by reference.
26349 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26350 EVT VT = Op.getValueType();
26351 if (VT != MVT::i16)
26354 bool Promote = false;
26355 bool Commute = false;
26356 switch (Op.getOpcode()) {
26359 LoadSDNode *LD = cast<LoadSDNode>(Op);
26360 // If the non-extending load has a single use and it's not live out, then it
26361 // might be folded.
26362 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26363 Op.hasOneUse()*/) {
26364 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26365 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26366 // The only case where we'd want to promote LOAD (rather then it being
26367 // promoted as an operand is when it's only use is liveout.
26368 if (UI->getOpcode() != ISD::CopyToReg)
26375 case ISD::SIGN_EXTEND:
26376 case ISD::ZERO_EXTEND:
26377 case ISD::ANY_EXTEND:
26382 SDValue N0 = Op.getOperand(0);
26383 // Look out for (store (shl (load), x)).
26384 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26397 SDValue N0 = Op.getOperand(0);
26398 SDValue N1 = Op.getOperand(1);
26399 if (!Commute && MayFoldLoad(N1))
26401 // Avoid disabling potential load folding opportunities.
26402 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26404 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26414 //===----------------------------------------------------------------------===//
26415 // X86 Inline Assembly Support
26416 //===----------------------------------------------------------------------===//
26418 // Helper to match a string separated by whitespace.
26419 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26420 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26422 for (StringRef Piece : Pieces) {
26423 if (!S.startswith(Piece)) // Check if the piece matches.
26426 S = S.substr(Piece.size());
26427 StringRef::size_type Pos = S.find_first_not_of(" \t");
26428 if (Pos == 0) // We matched a prefix.
26437 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26439 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26440 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26441 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26442 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26444 if (AsmPieces.size() == 3)
26446 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26453 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26454 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26456 std::string AsmStr = IA->getAsmString();
26458 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26459 if (!Ty || Ty->getBitWidth() % 16 != 0)
26462 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26463 SmallVector<StringRef, 4> AsmPieces;
26464 SplitString(AsmStr, AsmPieces, ";\n");
26466 switch (AsmPieces.size()) {
26467 default: return false;
26469 // FIXME: this should verify that we are targeting a 486 or better. If not,
26470 // we will turn this bswap into something that will be lowered to logical
26471 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26472 // lower so don't worry about this.
26474 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26475 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26476 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26477 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26478 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26479 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26480 // No need to check constraints, nothing other than the equivalent of
26481 // "=r,0" would be valid here.
26482 return IntrinsicLowering::LowerToByteSwap(CI);
26485 // rorw $$8, ${0:w} --> llvm.bswap.i16
26486 if (CI->getType()->isIntegerTy(16) &&
26487 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26488 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26489 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26491 StringRef ConstraintsStr = IA->getConstraintString();
26492 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26493 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26494 if (clobbersFlagRegisters(AsmPieces))
26495 return IntrinsicLowering::LowerToByteSwap(CI);
26499 if (CI->getType()->isIntegerTy(32) &&
26500 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26501 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26502 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26503 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26505 StringRef ConstraintsStr = IA->getConstraintString();
26506 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26507 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26508 if (clobbersFlagRegisters(AsmPieces))
26509 return IntrinsicLowering::LowerToByteSwap(CI);
26512 if (CI->getType()->isIntegerTy(64)) {
26513 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26514 if (Constraints.size() >= 2 &&
26515 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26516 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26517 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26518 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26519 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26520 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26521 return IntrinsicLowering::LowerToByteSwap(CI);
26529 /// getConstraintType - Given a constraint letter, return the type of
26530 /// constraint it is for this target.
26531 X86TargetLowering::ConstraintType
26532 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26533 if (Constraint.size() == 1) {
26534 switch (Constraint[0]) {
26545 return C_RegisterClass;
26569 return TargetLowering::getConstraintType(Constraint);
26572 /// Examine constraint type and operand type and determine a weight value.
26573 /// This object must already have been set up with the operand type
26574 /// and the current alternative constraint selected.
26575 TargetLowering::ConstraintWeight
26576 X86TargetLowering::getSingleConstraintMatchWeight(
26577 AsmOperandInfo &info, const char *constraint) const {
26578 ConstraintWeight weight = CW_Invalid;
26579 Value *CallOperandVal = info.CallOperandVal;
26580 // If we don't have a value, we can't do a match,
26581 // but allow it at the lowest weight.
26582 if (!CallOperandVal)
26584 Type *type = CallOperandVal->getType();
26585 // Look at the constraint type.
26586 switch (*constraint) {
26588 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26599 if (CallOperandVal->getType()->isIntegerTy())
26600 weight = CW_SpecificReg;
26605 if (type->isFloatingPointTy())
26606 weight = CW_SpecificReg;
26609 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26610 weight = CW_SpecificReg;
26614 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26615 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26616 weight = CW_Register;
26619 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26620 if (C->getZExtValue() <= 31)
26621 weight = CW_Constant;
26625 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26626 if (C->getZExtValue() <= 63)
26627 weight = CW_Constant;
26631 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26632 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26633 weight = CW_Constant;
26637 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26638 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26639 weight = CW_Constant;
26643 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26644 if (C->getZExtValue() <= 3)
26645 weight = CW_Constant;
26649 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26650 if (C->getZExtValue() <= 0xff)
26651 weight = CW_Constant;
26656 if (isa<ConstantFP>(CallOperandVal)) {
26657 weight = CW_Constant;
26661 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26662 if ((C->getSExtValue() >= -0x80000000LL) &&
26663 (C->getSExtValue() <= 0x7fffffffLL))
26664 weight = CW_Constant;
26668 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26669 if (C->getZExtValue() <= 0xffffffff)
26670 weight = CW_Constant;
26677 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26678 /// with another that has more specific requirements based on the type of the
26679 /// corresponding operand.
26680 const char *X86TargetLowering::
26681 LowerXConstraint(EVT ConstraintVT) const {
26682 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26683 // 'f' like normal targets.
26684 if (ConstraintVT.isFloatingPoint()) {
26685 if (Subtarget->hasSSE2())
26687 if (Subtarget->hasSSE1())
26691 return TargetLowering::LowerXConstraint(ConstraintVT);
26694 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26695 /// vector. If it is invalid, don't add anything to Ops.
26696 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26697 std::string &Constraint,
26698 std::vector<SDValue>&Ops,
26699 SelectionDAG &DAG) const {
26702 // Only support length 1 constraints for now.
26703 if (Constraint.length() > 1) return;
26705 char ConstraintLetter = Constraint[0];
26706 switch (ConstraintLetter) {
26709 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26710 if (C->getZExtValue() <= 31) {
26711 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26712 Op.getValueType());
26718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26719 if (C->getZExtValue() <= 63) {
26720 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26721 Op.getValueType());
26727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26728 if (isInt<8>(C->getSExtValue())) {
26729 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26730 Op.getValueType());
26736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26737 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26738 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26739 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26740 Op.getValueType());
26746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26747 if (C->getZExtValue() <= 3) {
26748 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26749 Op.getValueType());
26755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26756 if (C->getZExtValue() <= 255) {
26757 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26758 Op.getValueType());
26764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26765 if (C->getZExtValue() <= 127) {
26766 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26767 Op.getValueType());
26773 // 32-bit signed value
26774 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26775 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26776 C->getSExtValue())) {
26777 // Widen to 64 bits here to get it sign extended.
26778 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26781 // FIXME gcc accepts some relocatable values here too, but only in certain
26782 // memory models; it's complicated.
26787 // 32-bit unsigned value
26788 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26789 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26790 C->getZExtValue())) {
26791 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26792 Op.getValueType());
26796 // FIXME gcc accepts some relocatable values here too, but only in certain
26797 // memory models; it's complicated.
26801 // Literal immediates are always ok.
26802 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26803 // Widen to 64 bits here to get it sign extended.
26804 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26808 // In any sort of PIC mode addresses need to be computed at runtime by
26809 // adding in a register or some sort of table lookup. These can't
26810 // be used as immediates.
26811 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26814 // If we are in non-pic codegen mode, we allow the address of a global (with
26815 // an optional displacement) to be used with 'i'.
26816 GlobalAddressSDNode *GA = nullptr;
26817 int64_t Offset = 0;
26819 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26821 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26822 Offset += GA->getOffset();
26824 } else if (Op.getOpcode() == ISD::ADD) {
26825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26826 Offset += C->getZExtValue();
26827 Op = Op.getOperand(0);
26830 } else if (Op.getOpcode() == ISD::SUB) {
26831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26832 Offset += -C->getZExtValue();
26833 Op = Op.getOperand(0);
26838 // Otherwise, this isn't something we can handle, reject it.
26842 const GlobalValue *GV = GA->getGlobal();
26843 // If we require an extra load to get this address, as in PIC mode, we
26844 // can't accept it.
26845 if (isGlobalStubReference(
26846 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26849 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26850 GA->getValueType(0), Offset);
26855 if (Result.getNode()) {
26856 Ops.push_back(Result);
26859 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26862 std::pair<unsigned, const TargetRegisterClass *>
26863 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26864 StringRef Constraint,
26866 // First, see if this is a constraint that directly corresponds to an LLVM
26868 if (Constraint.size() == 1) {
26869 // GCC Constraint Letters
26870 switch (Constraint[0]) {
26872 // TODO: Slight differences here in allocation order and leaving
26873 // RIP in the class. Do they matter any more here than they do
26874 // in the normal allocation?
26875 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26876 if (Subtarget->is64Bit()) {
26877 if (VT == MVT::i32 || VT == MVT::f32)
26878 return std::make_pair(0U, &X86::GR32RegClass);
26879 if (VT == MVT::i16)
26880 return std::make_pair(0U, &X86::GR16RegClass);
26881 if (VT == MVT::i8 || VT == MVT::i1)
26882 return std::make_pair(0U, &X86::GR8RegClass);
26883 if (VT == MVT::i64 || VT == MVT::f64)
26884 return std::make_pair(0U, &X86::GR64RegClass);
26887 // 32-bit fallthrough
26888 case 'Q': // Q_REGS
26889 if (VT == MVT::i32 || VT == MVT::f32)
26890 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26891 if (VT == MVT::i16)
26892 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26893 if (VT == MVT::i8 || VT == MVT::i1)
26894 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26895 if (VT == MVT::i64)
26896 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26898 case 'r': // GENERAL_REGS
26899 case 'l': // INDEX_REGS
26900 if (VT == MVT::i8 || VT == MVT::i1)
26901 return std::make_pair(0U, &X86::GR8RegClass);
26902 if (VT == MVT::i16)
26903 return std::make_pair(0U, &X86::GR16RegClass);
26904 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26905 return std::make_pair(0U, &X86::GR32RegClass);
26906 return std::make_pair(0U, &X86::GR64RegClass);
26907 case 'R': // LEGACY_REGS
26908 if (VT == MVT::i8 || VT == MVT::i1)
26909 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26910 if (VT == MVT::i16)
26911 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26912 if (VT == MVT::i32 || !Subtarget->is64Bit())
26913 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26914 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26915 case 'f': // FP Stack registers.
26916 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26917 // value to the correct fpstack register class.
26918 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26919 return std::make_pair(0U, &X86::RFP32RegClass);
26920 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26921 return std::make_pair(0U, &X86::RFP64RegClass);
26922 return std::make_pair(0U, &X86::RFP80RegClass);
26923 case 'y': // MMX_REGS if MMX allowed.
26924 if (!Subtarget->hasMMX()) break;
26925 return std::make_pair(0U, &X86::VR64RegClass);
26926 case 'Y': // SSE_REGS if SSE2 allowed
26927 if (!Subtarget->hasSSE2()) break;
26929 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26930 if (!Subtarget->hasSSE1()) break;
26932 switch (VT.SimpleTy) {
26934 // Scalar SSE types.
26937 return std::make_pair(0U, &X86::FR32RegClass);
26940 return std::make_pair(0U, &X86::FR64RegClass);
26948 return std::make_pair(0U, &X86::VR128RegClass);
26956 return std::make_pair(0U, &X86::VR256RegClass);
26961 return std::make_pair(0U, &X86::VR512RegClass);
26967 // Use the default implementation in TargetLowering to convert the register
26968 // constraint into a member of a register class.
26969 std::pair<unsigned, const TargetRegisterClass*> Res;
26970 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
26972 // Not found as a standard register?
26974 // Map st(0) -> st(7) -> ST0
26975 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26976 tolower(Constraint[1]) == 's' &&
26977 tolower(Constraint[2]) == 't' &&
26978 Constraint[3] == '(' &&
26979 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26980 Constraint[5] == ')' &&
26981 Constraint[6] == '}') {
26983 Res.first = X86::FP0+Constraint[4]-'0';
26984 Res.second = &X86::RFP80RegClass;
26988 // GCC allows "st(0)" to be called just plain "st".
26989 if (StringRef("{st}").equals_lower(Constraint)) {
26990 Res.first = X86::FP0;
26991 Res.second = &X86::RFP80RegClass;
26996 if (StringRef("{flags}").equals_lower(Constraint)) {
26997 Res.first = X86::EFLAGS;
26998 Res.second = &X86::CCRRegClass;
27002 // 'A' means EAX + EDX.
27003 if (Constraint == "A") {
27004 Res.first = X86::EAX;
27005 Res.second = &X86::GR32_ADRegClass;
27011 // Otherwise, check to see if this is a register class of the wrong value
27012 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27013 // turn into {ax},{dx}.
27014 // MVT::Other is used to specify clobber names.
27015 if (Res.second->hasType(VT) || VT == MVT::Other)
27016 return Res; // Correct type already, nothing to do.
27018 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27019 // return "eax". This should even work for things like getting 64bit integer
27020 // registers when given an f64 type.
27021 const TargetRegisterClass *Class = Res.second;
27022 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27023 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27024 unsigned Size = VT.getSizeInBits();
27025 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27026 : Size == 16 ? MVT::i16
27027 : Size == 32 ? MVT::i32
27028 : Size == 64 ? MVT::i64
27030 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27032 Res.first = DestReg;
27033 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27034 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27035 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27036 : &X86::GR64RegClass;
27037 assert(Res.second->contains(Res.first) && "Register in register class");
27039 // No register found/type mismatch.
27041 Res.second = nullptr;
27043 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27044 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27045 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27046 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27047 Class == &X86::VR512RegClass) {
27048 // Handle references to XMM physical registers that got mapped into the
27049 // wrong class. This can happen with constraints like {xmm0} where the
27050 // target independent register mapper will just pick the first match it can
27051 // find, ignoring the required type.
27053 if (VT == MVT::f32 || VT == MVT::i32)
27054 Res.second = &X86::FR32RegClass;
27055 else if (VT == MVT::f64 || VT == MVT::i64)
27056 Res.second = &X86::FR64RegClass;
27057 else if (X86::VR128RegClass.hasType(VT))
27058 Res.second = &X86::VR128RegClass;
27059 else if (X86::VR256RegClass.hasType(VT))
27060 Res.second = &X86::VR256RegClass;
27061 else if (X86::VR512RegClass.hasType(VT))
27062 Res.second = &X86::VR512RegClass;
27064 // Type mismatch and not a clobber: Return an error;
27066 Res.second = nullptr;
27073 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27074 const AddrMode &AM, Type *Ty,
27075 unsigned AS) const {
27076 // Scaling factors are not free at all.
27077 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27078 // will take 2 allocations in the out of order engine instead of 1
27079 // for plain addressing mode, i.e. inst (reg1).
27081 // vaddps (%rsi,%drx), %ymm0, %ymm1
27082 // Requires two allocations (one for the load, one for the computation)
27084 // vaddps (%rsi), %ymm0, %ymm1
27085 // Requires just 1 allocation, i.e., freeing allocations for other operations
27086 // and having less micro operations to execute.
27088 // For some X86 architectures, this is even worse because for instance for
27089 // stores, the complex addressing mode forces the instruction to use the
27090 // "load" ports instead of the dedicated "store" port.
27091 // E.g., on Haswell:
27092 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27093 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27094 if (isLegalAddressingMode(DL, AM, Ty, AS))
27095 // Scale represents reg2 * scale, thus account for 1
27096 // as soon as we use a second register.
27097 return AM.Scale != 0;
27101 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27102 // Integer division on x86 is expensive. However, when aggressively optimizing
27103 // for code size, we prefer to use a div instruction, as it is usually smaller
27104 // than the alternative sequence.
27105 // The exception to this is vector division. Since x86 doesn't have vector
27106 // integer division, leaving the division as-is is a loss even in terms of
27107 // size, because it will have to be scalarized, while the alternative code
27108 // sequence can be performed in vector form.
27109 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27110 Attribute::MinSize);
27111 return OptSize && !VT.isVector();