1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILP:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILP:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILP:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5353 APInt MaskElement = CN->getAPIntValue();
5355 // We now have to decode the element which could be any integer size and
5356 // extract each byte of it.
5357 for (int j = 0; j < NumBytesPerElement; ++j) {
5358 // Note that this is x86 and so always little endian: the low byte is
5359 // the first byte of the mask.
5360 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5361 MaskElement = MaskElement.lshr(8);
5364 DecodePSHUFBMask(RawMask, Mask);
5368 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5372 SDValue Ptr = MaskLoad->getBasePtr();
5373 if (Ptr->getOpcode() == X86ISD::Wrapper)
5374 Ptr = Ptr->getOperand(0);
5376 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5377 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5380 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5381 // FIXME: Support AVX-512 here.
5382 if (!C->getType()->isVectorTy() ||
5383 (C->getNumElements() != 16 && C->getNumElements() != 32))
5386 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5387 DecodePSHUFBMask(C, Mask);
5393 case X86ISD::VPERMI:
5394 ImmN = N->getOperand(N->getNumOperands()-1);
5395 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5399 case X86ISD::MOVSD: {
5400 // The index 0 always comes from the first element of the second source,
5401 // this is why MOVSS and MOVSD are used in the first place. The other
5402 // elements come from the other positions of the first source vector
5403 Mask.push_back(NumElems);
5404 for (unsigned i = 1; i != NumElems; ++i) {
5409 case X86ISD::VPERM2X128:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 if (Mask.empty()) return false;
5414 case X86ISD::MOVSLDUP:
5415 DecodeMOVSLDUPMask(VT, Mask);
5417 case X86ISD::MOVSHDUP:
5418 DecodeMOVSHDUPMask(VT, Mask);
5420 case X86ISD::MOVDDUP:
5421 case X86ISD::MOVLHPD:
5422 case X86ISD::MOVLPD:
5423 case X86ISD::MOVLPS:
5424 // Not yet implemented
5426 default: llvm_unreachable("unknown target shuffle node");
5429 // If we have a fake unary shuffle, the shuffle mask is spread across two
5430 // inputs that are actually the same node. Re-map the mask to always point
5431 // into the first input.
5434 if (M >= (int)Mask.size())
5440 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5441 /// element of the result of the vector shuffle.
5442 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5445 return SDValue(); // Limit search depth.
5447 SDValue V = SDValue(N, 0);
5448 EVT VT = V.getValueType();
5449 unsigned Opcode = V.getOpcode();
5451 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5452 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5453 int Elt = SV->getMaskElt(Index);
5456 return DAG.getUNDEF(VT.getVectorElementType());
5458 unsigned NumElems = VT.getVectorNumElements();
5459 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5460 : SV->getOperand(1);
5461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5464 // Recurse into target specific vector shuffles to find scalars.
5465 if (isTargetShuffle(Opcode)) {
5466 MVT ShufVT = V.getSimpleValueType();
5467 unsigned NumElems = ShufVT.getVectorNumElements();
5468 SmallVector<int, 16> ShuffleMask;
5471 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5474 int Elt = ShuffleMask[Index];
5476 return DAG.getUNDEF(ShufVT.getVectorElementType());
5478 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5480 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5484 // Actual nodes that may contain scalar elements
5485 if (Opcode == ISD::BITCAST) {
5486 V = V.getOperand(0);
5487 EVT SrcVT = V.getValueType();
5488 unsigned NumElems = VT.getVectorNumElements();
5490 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5494 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5495 return (Index == 0) ? V.getOperand(0)
5496 : DAG.getUNDEF(VT.getVectorElementType());
5498 if (V.getOpcode() == ISD::BUILD_VECTOR)
5499 return V.getOperand(Index);
5504 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5505 /// shuffle operation which come from a consecutively from a zero. The
5506 /// search can start in two different directions, from left or right.
5507 /// We count undefs as zeros until PreferredNum is reached.
5508 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5509 unsigned NumElems, bool ZerosFromLeft,
5511 unsigned PreferredNum = -1U) {
5512 unsigned NumZeros = 0;
5513 for (unsigned i = 0; i != NumElems; ++i) {
5514 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5515 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5519 if (X86::isZeroNode(Elt))
5521 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5522 NumZeros = std::min(NumZeros + 1, PreferredNum);
5530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5531 /// correspond consecutively to elements from one of the vector operands,
5532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5536 unsigned NumElems, unsigned &OpNum) {
5537 bool SeenV1 = false;
5538 bool SeenV2 = false;
5540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5541 int Idx = SVOp->getMaskElt(i);
5542 // Ignore undef indicies
5546 if (Idx < (int)NumElems)
5551 // Only accept consecutive elements from the same vector
5552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5556 OpNum = SeenV1 ? 0 : 1;
5560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5561 /// logical left shift of a vector.
5562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5565 SVOp->getSimpleValueType(0).getVectorNumElements();
5566 unsigned NumZeros = getNumOfConsecutiveZeros(
5567 SVOp, NumElems, false /* check zeros from right */, DAG,
5568 SVOp->getMaskElt(0));
5574 // Considering the elements in the mask that are not consecutive zeros,
5575 // check if they consecutively come from only one of the source vectors.
5577 // V1 = {X, A, B, C} 0
5579 // vector_shuffle V1, V2 <1, 2, 3, X>
5581 if (!isShuffleMaskConsecutive(SVOp,
5582 0, // Mask Start Index
5583 NumElems-NumZeros, // Mask End Index(exclusive)
5584 NumZeros, // Where to start looking in the src vector
5585 NumElems, // Number of elements in vector
5586 OpSrc)) // Which source operand ?
5591 ShVal = SVOp->getOperand(OpSrc);
5595 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5596 /// logical left shift of a vector.
5597 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5598 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5600 SVOp->getSimpleValueType(0).getVectorNumElements();
5601 unsigned NumZeros = getNumOfConsecutiveZeros(
5602 SVOp, NumElems, true /* check zeros from left */, DAG,
5603 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5609 // Considering the elements in the mask that are not consecutive zeros,
5610 // check if they consecutively come from only one of the source vectors.
5612 // 0 { A, B, X, X } = V2
5614 // vector_shuffle V1, V2 <X, X, 4, 5>
5616 if (!isShuffleMaskConsecutive(SVOp,
5617 NumZeros, // Mask Start Index
5618 NumElems, // Mask End Index(exclusive)
5619 0, // Where to start looking in the src vector
5620 NumElems, // Number of elements in vector
5621 OpSrc)) // Which source operand ?
5626 ShVal = SVOp->getOperand(OpSrc);
5630 /// isVectorShift - Returns true if the shuffle can be implemented as a
5631 /// logical left or right shift of a vector.
5632 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5634 // Although the logic below support any bitwidth size, there are no
5635 // shift instructions which handle more than 128-bit vectors.
5636 if (!SVOp->getSimpleValueType(0).is128BitVector())
5639 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5640 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5646 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5648 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5649 unsigned NumNonZero, unsigned NumZero,
5651 const X86Subtarget* Subtarget,
5652 const TargetLowering &TLI) {
5659 for (unsigned i = 0; i < 16; ++i) {
5660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5661 if (ThisIsNonZero && First) {
5663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5665 V = DAG.getUNDEF(MVT::v8i16);
5670 SDValue ThisElt, LastElt;
5671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5672 if (LastIsNonZero) {
5673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5674 MVT::i16, Op.getOperand(i-1));
5676 if (ThisIsNonZero) {
5677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5679 ThisElt, DAG.getConstant(8, MVT::i8));
5681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5685 if (ThisElt.getNode())
5686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5687 DAG.getIntPtrConstant(i/2));
5691 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5697 unsigned NumNonZero, unsigned NumZero,
5699 const X86Subtarget* Subtarget,
5700 const TargetLowering &TLI) {
5707 for (unsigned i = 0; i < 8; ++i) {
5708 bool isNonZero = (NonZeros & (1 << i)) != 0;
5712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5714 V = DAG.getUNDEF(MVT::v8i16);
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5718 MVT::v8i16, V, Op.getOperand(i),
5719 DAG.getIntPtrConstant(i));
5726 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5727 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5728 unsigned NonZeros, unsigned NumNonZero,
5729 unsigned NumZero, SelectionDAG &DAG,
5730 const X86Subtarget *Subtarget,
5731 const TargetLowering &TLI) {
5732 // We know there's at least one non-zero element
5733 unsigned FirstNonZeroIdx = 0;
5734 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5735 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5736 X86::isZeroNode(FirstNonZero)) {
5738 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5741 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5742 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5745 SDValue V = FirstNonZero.getOperand(0);
5746 MVT VVT = V.getSimpleValueType();
5747 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5750 unsigned FirstNonZeroDst =
5751 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5752 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5753 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5754 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5756 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5757 SDValue Elem = Op.getOperand(Idx);
5758 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5761 // TODO: What else can be here? Deal with it.
5762 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5765 // TODO: Some optimizations are still possible here
5766 // ex: Getting one element from a vector, and the rest from another.
5767 if (Elem.getOperand(0) != V)
5770 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5773 else if (IncorrectIdx == -1U) {
5777 // There was already one element with an incorrect index.
5778 // We can't optimize this case to an insertps.
5782 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5784 EVT VT = Op.getSimpleValueType();
5785 unsigned ElementMoveMask = 0;
5786 if (IncorrectIdx == -1U)
5787 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5789 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5791 SDValue InsertpsMask =
5792 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5799 /// getVShift - Return a vector logical shift node.
5801 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5802 unsigned NumBits, SelectionDAG &DAG,
5803 const TargetLowering &TLI, SDLoc dl) {
5804 assert(VT.is128BitVector() && "Unknown type for VShift");
5805 EVT ShVT = MVT::v2i64;
5806 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5807 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5808 return DAG.getNode(ISD::BITCAST, dl, VT,
5809 DAG.getNode(Opc, dl, ShVT, SrcOp,
5810 DAG.getConstant(NumBits,
5811 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5815 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5817 // Check if the scalar load can be widened into a vector load. And if
5818 // the address is "base + cst" see if the cst can be "absorbed" into
5819 // the shuffle mask.
5820 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5821 SDValue Ptr = LD->getBasePtr();
5822 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5824 EVT PVT = LD->getValueType(0);
5825 if (PVT != MVT::i32 && PVT != MVT::f32)
5830 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5831 FI = FINode->getIndex();
5833 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5834 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5835 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5836 Offset = Ptr.getConstantOperandVal(1);
5837 Ptr = Ptr.getOperand(0);
5842 // FIXME: 256-bit vector instructions don't require a strict alignment,
5843 // improve this code to support it better.
5844 unsigned RequiredAlign = VT.getSizeInBits()/8;
5845 SDValue Chain = LD->getChain();
5846 // Make sure the stack object alignment is at least 16 or 32.
5847 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5848 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5849 if (MFI->isFixedObjectIndex(FI)) {
5850 // Can't change the alignment. FIXME: It's possible to compute
5851 // the exact stack offset and reference FI + adjust offset instead.
5852 // If someone *really* cares about this. That's the way to implement it.
5855 MFI->setObjectAlignment(FI, RequiredAlign);
5859 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5860 // Ptr + (Offset & ~15).
5863 if ((Offset % RequiredAlign) & 3)
5865 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5867 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5868 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5870 int EltNo = (Offset - StartOffset) >> 2;
5871 unsigned NumElems = VT.getVectorNumElements();
5873 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5874 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5875 LD->getPointerInfo().getWithOffset(StartOffset),
5876 false, false, false, 0);
5878 SmallVector<int, 8> Mask;
5879 for (unsigned i = 0; i != NumElems; ++i)
5880 Mask.push_back(EltNo);
5882 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5888 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5889 /// vector of type 'VT', see if the elements can be replaced by a single large
5890 /// load which has the same value as a build_vector whose operands are 'elts'.
5892 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5894 /// FIXME: we'd also like to handle the case where the last elements are zero
5895 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5896 /// There's even a handy isZeroNode for that purpose.
5897 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5898 SDLoc &DL, SelectionDAG &DAG,
5899 bool isAfterLegalize) {
5900 EVT EltVT = VT.getVectorElementType();
5901 unsigned NumElems = Elts.size();
5903 LoadSDNode *LDBase = nullptr;
5904 unsigned LastLoadedElt = -1U;
5906 // For each element in the initializer, see if we've found a load or an undef.
5907 // If we don't find an initial load element, or later load elements are
5908 // non-consecutive, bail out.
5909 for (unsigned i = 0; i < NumElems; ++i) {
5910 SDValue Elt = Elts[i];
5912 if (!Elt.getNode() ||
5913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5916 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5918 LDBase = cast<LoadSDNode>(Elt.getNode());
5922 if (Elt.getOpcode() == ISD::UNDEF)
5925 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5931 // If we have found an entire vector of loads and undefs, then return a large
5932 // load of the entire vector width starting at the base pointer. If we found
5933 // consecutive loads for the low half, generate a vzext_load node.
5934 if (LastLoadedElt == NumElems - 1) {
5936 if (isAfterLegalize &&
5937 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5940 SDValue NewLd = SDValue();
5942 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5943 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5944 LDBase->getPointerInfo(),
5945 LDBase->isVolatile(), LDBase->isNonTemporal(),
5946 LDBase->isInvariant(), 0);
5947 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5948 LDBase->getPointerInfo(),
5949 LDBase->isVolatile(), LDBase->isNonTemporal(),
5950 LDBase->isInvariant(), LDBase->getAlignment());
5952 if (LDBase->hasAnyUseOfValue(1)) {
5953 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5955 SDValue(NewLd.getNode(), 1));
5956 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5957 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5958 SDValue(NewLd.getNode(), 1));
5963 if (NumElems == 4 && LastLoadedElt == 1 &&
5964 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5965 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5966 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5968 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5969 LDBase->getPointerInfo(),
5970 LDBase->getAlignment(),
5971 false/*isVolatile*/, true/*ReadMem*/,
5974 // Make sure the newly-created LOAD is in the same position as LDBase in
5975 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5976 // update uses of LDBase's output chain to use the TokenFactor.
5977 if (LDBase->hasAnyUseOfValue(1)) {
5978 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5979 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5980 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5981 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5982 SDValue(ResNode.getNode(), 1));
5985 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5990 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5991 /// to generate a splat value for the following cases:
5992 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5993 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5994 /// a scalar load, or a constant.
5995 /// The VBROADCAST node is returned when a pattern is found,
5996 /// or SDValue() otherwise.
5997 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5998 SelectionDAG &DAG) {
5999 // VBROADCAST requires AVX.
6000 // TODO: Splats could be generated for non-AVX CPUs using SSE
6001 // instructions, but there's less potential gain for only 128-bit vectors.
6002 if (!Subtarget->hasAVX())
6005 MVT VT = Op.getSimpleValueType();
6008 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6009 "Unsupported vector type for broadcast.");
6014 switch (Op.getOpcode()) {
6016 // Unknown pattern found.
6019 case ISD::BUILD_VECTOR: {
6020 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6021 BitVector UndefElements;
6022 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6024 // We need a splat of a single value to use broadcast, and it doesn't
6025 // make any sense if the value is only in one element of the vector.
6026 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6030 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6031 Ld.getOpcode() == ISD::ConstantFP);
6033 // Make sure that all of the users of a non-constant load are from the
6034 // BUILD_VECTOR node.
6035 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6040 case ISD::VECTOR_SHUFFLE: {
6041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6043 // Shuffles must have a splat mask where the first element is
6045 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6048 SDValue Sc = Op.getOperand(0);
6049 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6050 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6052 if (!Subtarget->hasInt256())
6055 // Use the register form of the broadcast instruction available on AVX2.
6056 if (VT.getSizeInBits() >= 256)
6057 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6058 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6061 Ld = Sc.getOperand(0);
6062 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6063 Ld.getOpcode() == ISD::ConstantFP);
6065 // The scalar_to_vector node and the suspected
6066 // load node must have exactly one user.
6067 // Constants may have multiple users.
6069 // AVX-512 has register version of the broadcast
6070 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6071 Ld.getValueType().getSizeInBits() >= 32;
6072 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6079 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6080 bool IsGE256 = (VT.getSizeInBits() >= 256);
6082 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6083 // instruction to save 8 or more bytes of constant pool data.
6084 // TODO: If multiple splats are generated to load the same constant,
6085 // it may be detrimental to overall size. There needs to be a way to detect
6086 // that condition to know if this is truly a size win.
6087 const Function *F = DAG.getMachineFunction().getFunction();
6088 bool OptForSize = F->getAttributes().
6089 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6091 // Handle broadcasting a single constant scalar from the constant pool
6093 // On Sandybridge (no AVX2), it is still better to load a constant vector
6094 // from the constant pool and not to broadcast it from a scalar.
6095 // But override that restriction when optimizing for size.
6096 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6097 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6098 EVT CVT = Ld.getValueType();
6099 assert(!CVT.isVector() && "Must not broadcast a vector type");
6101 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6102 // For size optimization, also splat v2f64 and v2i64, and for size opt
6103 // with AVX2, also splat i8 and i16.
6104 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6105 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6106 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6107 const Constant *C = nullptr;
6108 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6109 C = CI->getConstantIntValue();
6110 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6111 C = CF->getConstantFPValue();
6113 assert(C && "Invalid constant type");
6115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6116 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6117 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6118 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6119 MachinePointerInfo::getConstantPool(),
6120 false, false, false, Alignment);
6122 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6126 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6128 // Handle AVX2 in-register broadcasts.
6129 if (!IsLoad && Subtarget->hasInt256() &&
6130 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6131 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6133 // The scalar source must be a normal load.
6137 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6138 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6140 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6141 // double since there is no vbroadcastsd xmm
6142 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6143 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6144 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6147 // Unsupported broadcast.
6151 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6152 /// underlying vector and index.
6154 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6156 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6158 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6159 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6162 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6164 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6166 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6167 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6170 // In this case the vector is the extract_subvector expression and the index
6171 // is 2, as specified by the shuffle.
6172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6173 SDValue ShuffleVec = SVOp->getOperand(0);
6174 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6175 assert(ShuffleVecVT.getVectorElementType() ==
6176 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6178 int ShuffleIdx = SVOp->getMaskElt(Idx);
6179 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6180 ExtractedFromVec = ShuffleVec;
6186 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6187 MVT VT = Op.getSimpleValueType();
6189 // Skip if insert_vec_elt is not supported.
6190 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6191 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6195 unsigned NumElems = Op.getNumOperands();
6199 SmallVector<unsigned, 4> InsertIndices;
6200 SmallVector<int, 8> Mask(NumElems, -1);
6202 for (unsigned i = 0; i != NumElems; ++i) {
6203 unsigned Opc = Op.getOperand(i).getOpcode();
6205 if (Opc == ISD::UNDEF)
6208 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6209 // Quit if more than 1 elements need inserting.
6210 if (InsertIndices.size() > 1)
6213 InsertIndices.push_back(i);
6217 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6218 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6219 // Quit if non-constant index.
6220 if (!isa<ConstantSDNode>(ExtIdx))
6222 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6224 // Quit if extracted from vector of different type.
6225 if (ExtractedFromVec.getValueType() != VT)
6228 if (!VecIn1.getNode())
6229 VecIn1 = ExtractedFromVec;
6230 else if (VecIn1 != ExtractedFromVec) {
6231 if (!VecIn2.getNode())
6232 VecIn2 = ExtractedFromVec;
6233 else if (VecIn2 != ExtractedFromVec)
6234 // Quit if more than 2 vectors to shuffle
6238 if (ExtractedFromVec == VecIn1)
6240 else if (ExtractedFromVec == VecIn2)
6241 Mask[i] = Idx + NumElems;
6244 if (!VecIn1.getNode())
6247 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6248 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6249 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6250 unsigned Idx = InsertIndices[i];
6251 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6252 DAG.getIntPtrConstant(Idx));
6258 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6260 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6262 MVT VT = Op.getSimpleValueType();
6263 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6264 "Unexpected type in LowerBUILD_VECTORvXi1!");
6267 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6268 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6269 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6270 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6273 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6274 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6275 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6276 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6279 bool AllContants = true;
6280 uint64_t Immediate = 0;
6281 int NonConstIdx = -1;
6282 bool IsSplat = true;
6283 unsigned NumNonConsts = 0;
6284 unsigned NumConsts = 0;
6285 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6286 SDValue In = Op.getOperand(idx);
6287 if (In.getOpcode() == ISD::UNDEF)
6289 if (!isa<ConstantSDNode>(In)) {
6290 AllContants = false;
6296 if (cast<ConstantSDNode>(In)->getZExtValue())
6297 Immediate |= (1ULL << idx);
6299 if (In != Op.getOperand(0))
6304 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6305 DAG.getConstant(Immediate, MVT::i16));
6306 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6307 DAG.getIntPtrConstant(0));
6310 if (NumNonConsts == 1 && NonConstIdx != 0) {
6313 SDValue VecAsImm = DAG.getConstant(Immediate,
6314 MVT::getIntegerVT(VT.getSizeInBits()));
6315 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6318 DstVec = DAG.getUNDEF(VT);
6319 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6320 Op.getOperand(NonConstIdx),
6321 DAG.getIntPtrConstant(NonConstIdx));
6323 if (!IsSplat && (NonConstIdx != 0))
6324 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6325 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6328 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6329 DAG.getConstant(-1, SelectVT),
6330 DAG.getConstant(0, SelectVT));
6332 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6333 DAG.getConstant((Immediate | 1), SelectVT),
6334 DAG.getConstant(Immediate, SelectVT));
6335 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6338 /// \brief Return true if \p N implements a horizontal binop and return the
6339 /// operands for the horizontal binop into V0 and V1.
6341 /// This is a helper function of PerformBUILD_VECTORCombine.
6342 /// This function checks that the build_vector \p N in input implements a
6343 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6344 /// operation to match.
6345 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6346 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6347 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6350 /// This function only analyzes elements of \p N whose indices are
6351 /// in range [BaseIdx, LastIdx).
6352 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6354 unsigned BaseIdx, unsigned LastIdx,
6355 SDValue &V0, SDValue &V1) {
6356 EVT VT = N->getValueType(0);
6358 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6359 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6360 "Invalid Vector in input!");
6362 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6363 bool CanFold = true;
6364 unsigned ExpectedVExtractIdx = BaseIdx;
6365 unsigned NumElts = LastIdx - BaseIdx;
6366 V0 = DAG.getUNDEF(VT);
6367 V1 = DAG.getUNDEF(VT);
6369 // Check if N implements a horizontal binop.
6370 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6371 SDValue Op = N->getOperand(i + BaseIdx);
6374 if (Op->getOpcode() == ISD::UNDEF) {
6375 // Update the expected vector extract index.
6376 if (i * 2 == NumElts)
6377 ExpectedVExtractIdx = BaseIdx;
6378 ExpectedVExtractIdx += 2;
6382 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6387 SDValue Op0 = Op.getOperand(0);
6388 SDValue Op1 = Op.getOperand(1);
6390 // Try to match the following pattern:
6391 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6392 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6393 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6394 Op0.getOperand(0) == Op1.getOperand(0) &&
6395 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6396 isa<ConstantSDNode>(Op1.getOperand(1)));
6400 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6401 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6403 if (i * 2 < NumElts) {
6404 if (V0.getOpcode() == ISD::UNDEF)
6405 V0 = Op0.getOperand(0);
6407 if (V1.getOpcode() == ISD::UNDEF)
6408 V1 = Op0.getOperand(0);
6409 if (i * 2 == NumElts)
6410 ExpectedVExtractIdx = BaseIdx;
6413 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6414 if (I0 == ExpectedVExtractIdx)
6415 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6416 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6417 // Try to match the following dag sequence:
6418 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6419 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6423 ExpectedVExtractIdx += 2;
6429 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6430 /// a concat_vector.
6432 /// This is a helper function of PerformBUILD_VECTORCombine.
6433 /// This function expects two 256-bit vectors called V0 and V1.
6434 /// At first, each vector is split into two separate 128-bit vectors.
6435 /// Then, the resulting 128-bit vectors are used to implement two
6436 /// horizontal binary operations.
6438 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6440 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6441 /// the two new horizontal binop.
6442 /// When Mode is set, the first horizontal binop dag node would take as input
6443 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6444 /// horizontal binop dag node would take as input the lower 128-bit of V1
6445 /// and the upper 128-bit of V1.
6447 /// HADD V0_LO, V0_HI
6448 /// HADD V1_LO, V1_HI
6450 /// Otherwise, the first horizontal binop dag node takes as input the lower
6451 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6452 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6454 /// HADD V0_LO, V1_LO
6455 /// HADD V0_HI, V1_HI
6457 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6458 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6459 /// the upper 128-bits of the result.
6460 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6461 SDLoc DL, SelectionDAG &DAG,
6462 unsigned X86Opcode, bool Mode,
6463 bool isUndefLO, bool isUndefHI) {
6464 EVT VT = V0.getValueType();
6465 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6466 "Invalid nodes in input!");
6468 unsigned NumElts = VT.getVectorNumElements();
6469 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6470 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6471 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6472 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6473 EVT NewVT = V0_LO.getValueType();
6475 SDValue LO = DAG.getUNDEF(NewVT);
6476 SDValue HI = DAG.getUNDEF(NewVT);
6479 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6480 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6481 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6482 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6483 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6485 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6486 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6487 V1_LO->getOpcode() != ISD::UNDEF))
6488 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6490 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6491 V1_HI->getOpcode() != ISD::UNDEF))
6492 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6495 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6498 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6499 /// sequence of 'vadd + vsub + blendi'.
6500 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6501 const X86Subtarget *Subtarget) {
6503 EVT VT = BV->getValueType(0);
6504 unsigned NumElts = VT.getVectorNumElements();
6505 SDValue InVec0 = DAG.getUNDEF(VT);
6506 SDValue InVec1 = DAG.getUNDEF(VT);
6508 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6509 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6511 // Odd-numbered elements in the input build vector are obtained from
6512 // adding two integer/float elements.
6513 // Even-numbered elements in the input build vector are obtained from
6514 // subtracting two integer/float elements.
6515 unsigned ExpectedOpcode = ISD::FSUB;
6516 unsigned NextExpectedOpcode = ISD::FADD;
6517 bool AddFound = false;
6518 bool SubFound = false;
6520 for (unsigned i = 0, e = NumElts; i != e; i++) {
6521 SDValue Op = BV->getOperand(i);
6523 // Skip 'undef' values.
6524 unsigned Opcode = Op.getOpcode();
6525 if (Opcode == ISD::UNDEF) {
6526 std::swap(ExpectedOpcode, NextExpectedOpcode);
6530 // Early exit if we found an unexpected opcode.
6531 if (Opcode != ExpectedOpcode)
6534 SDValue Op0 = Op.getOperand(0);
6535 SDValue Op1 = Op.getOperand(1);
6537 // Try to match the following pattern:
6538 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6539 // Early exit if we cannot match that sequence.
6540 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6541 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6542 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6543 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6544 Op0.getOperand(1) != Op1.getOperand(1))
6547 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6551 // We found a valid add/sub node. Update the information accordingly.
6557 // Update InVec0 and InVec1.
6558 if (InVec0.getOpcode() == ISD::UNDEF)
6559 InVec0 = Op0.getOperand(0);
6560 if (InVec1.getOpcode() == ISD::UNDEF)
6561 InVec1 = Op1.getOperand(0);
6563 // Make sure that operands in input to each add/sub node always
6564 // come from a same pair of vectors.
6565 if (InVec0 != Op0.getOperand(0)) {
6566 if (ExpectedOpcode == ISD::FSUB)
6569 // FADD is commutable. Try to commute the operands
6570 // and then test again.
6571 std::swap(Op0, Op1);
6572 if (InVec0 != Op0.getOperand(0))
6576 if (InVec1 != Op1.getOperand(0))
6579 // Update the pair of expected opcodes.
6580 std::swap(ExpectedOpcode, NextExpectedOpcode);
6583 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6584 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6585 InVec1.getOpcode() != ISD::UNDEF)
6586 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6591 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6592 const X86Subtarget *Subtarget) {
6594 EVT VT = N->getValueType(0);
6595 unsigned NumElts = VT.getVectorNumElements();
6596 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6597 SDValue InVec0, InVec1;
6599 // Try to match an ADDSUB.
6600 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6601 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6602 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6603 if (Value.getNode())
6607 // Try to match horizontal ADD/SUB.
6608 unsigned NumUndefsLO = 0;
6609 unsigned NumUndefsHI = 0;
6610 unsigned Half = NumElts/2;
6612 // Count the number of UNDEF operands in the build_vector in input.
6613 for (unsigned i = 0, e = Half; i != e; ++i)
6614 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6617 for (unsigned i = Half, e = NumElts; i != e; ++i)
6618 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6621 // Early exit if this is either a build_vector of all UNDEFs or all the
6622 // operands but one are UNDEF.
6623 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6626 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6627 // Try to match an SSE3 float HADD/HSUB.
6628 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6629 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6631 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6632 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6633 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6634 // Try to match an SSSE3 integer HADD/HSUB.
6635 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6636 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6638 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6642 if (!Subtarget->hasAVX())
6645 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6646 // Try to match an AVX horizontal add/sub of packed single/double
6647 // precision floating point values from 256-bit vectors.
6648 SDValue InVec2, InVec3;
6649 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6650 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6651 ((InVec0.getOpcode() == ISD::UNDEF ||
6652 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6653 ((InVec1.getOpcode() == ISD::UNDEF ||
6654 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6655 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6657 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6658 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6659 ((InVec0.getOpcode() == ISD::UNDEF ||
6660 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6661 ((InVec1.getOpcode() == ISD::UNDEF ||
6662 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6663 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6664 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6665 // Try to match an AVX2 horizontal add/sub of signed integers.
6666 SDValue InVec2, InVec3;
6668 bool CanFold = true;
6670 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6671 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6672 ((InVec0.getOpcode() == ISD::UNDEF ||
6673 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6674 ((InVec1.getOpcode() == ISD::UNDEF ||
6675 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6676 X86Opcode = X86ISD::HADD;
6677 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6678 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6679 ((InVec0.getOpcode() == ISD::UNDEF ||
6680 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6681 ((InVec1.getOpcode() == ISD::UNDEF ||
6682 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6683 X86Opcode = X86ISD::HSUB;
6688 // Fold this build_vector into a single horizontal add/sub.
6689 // Do this only if the target has AVX2.
6690 if (Subtarget->hasAVX2())
6691 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6693 // Do not try to expand this build_vector into a pair of horizontal
6694 // add/sub if we can emit a pair of scalar add/sub.
6695 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6698 // Convert this build_vector into a pair of horizontal binop followed by
6700 bool isUndefLO = NumUndefsLO == Half;
6701 bool isUndefHI = NumUndefsHI == Half;
6702 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6703 isUndefLO, isUndefHI);
6707 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6708 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6710 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6711 X86Opcode = X86ISD::HADD;
6712 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6713 X86Opcode = X86ISD::HSUB;
6714 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6715 X86Opcode = X86ISD::FHADD;
6716 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6717 X86Opcode = X86ISD::FHSUB;
6721 // Don't try to expand this build_vector into a pair of horizontal add/sub
6722 // if we can simply emit a pair of scalar add/sub.
6723 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6726 // Convert this build_vector into two horizontal add/sub followed by
6728 bool isUndefLO = NumUndefsLO == Half;
6729 bool isUndefHI = NumUndefsHI == Half;
6730 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6731 isUndefLO, isUndefHI);
6738 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6741 MVT VT = Op.getSimpleValueType();
6742 MVT ExtVT = VT.getVectorElementType();
6743 unsigned NumElems = Op.getNumOperands();
6745 // Generate vectors for predicate vectors.
6746 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6747 return LowerBUILD_VECTORvXi1(Op, DAG);
6749 // Vectors containing all zeros can be matched by pxor and xorps later
6750 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6751 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6752 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6753 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6756 return getZeroVector(VT, Subtarget, DAG, dl);
6759 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6760 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6761 // vpcmpeqd on 256-bit vectors.
6762 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6763 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6766 if (!VT.is512BitVector())
6767 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6770 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6771 if (Broadcast.getNode())
6774 unsigned EVTBits = ExtVT.getSizeInBits();
6776 unsigned NumZero = 0;
6777 unsigned NumNonZero = 0;
6778 unsigned NonZeros = 0;
6779 bool IsAllConstants = true;
6780 SmallSet<SDValue, 8> Values;
6781 for (unsigned i = 0; i < NumElems; ++i) {
6782 SDValue Elt = Op.getOperand(i);
6783 if (Elt.getOpcode() == ISD::UNDEF)
6786 if (Elt.getOpcode() != ISD::Constant &&
6787 Elt.getOpcode() != ISD::ConstantFP)
6788 IsAllConstants = false;
6789 if (X86::isZeroNode(Elt))
6792 NonZeros |= (1 << i);
6797 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6798 if (NumNonZero == 0)
6799 return DAG.getUNDEF(VT);
6801 // Special case for single non-zero, non-undef, element.
6802 if (NumNonZero == 1) {
6803 unsigned Idx = countTrailingZeros(NonZeros);
6804 SDValue Item = Op.getOperand(Idx);
6806 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6807 // the value are obviously zero, truncate the value to i32 and do the
6808 // insertion that way. Only do this if the value is non-constant or if the
6809 // value is a constant being inserted into element 0. It is cheaper to do
6810 // a constant pool load than it is to do a movd + shuffle.
6811 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6812 (!IsAllConstants || Idx == 0)) {
6813 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6815 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6816 EVT VecVT = MVT::v4i32;
6817 unsigned VecElts = 4;
6819 // Truncate the value (which may itself be a constant) to i32, and
6820 // convert it to a vector with movd (S2V+shuffle to zero extend).
6821 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6822 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6824 // If using the new shuffle lowering, just directly insert this.
6825 if (ExperimentalVectorShuffleLowering)
6827 ISD::BITCAST, dl, VT,
6828 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6830 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6832 // Now we have our 32-bit value zero extended in the low element of
6833 // a vector. If Idx != 0, swizzle it into place.
6835 SmallVector<int, 4> Mask;
6836 Mask.push_back(Idx);
6837 for (unsigned i = 1; i != VecElts; ++i)
6839 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6842 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6846 // If we have a constant or non-constant insertion into the low element of
6847 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6848 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6849 // depending on what the source datatype is.
6852 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6854 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6855 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6856 if (VT.is256BitVector() || VT.is512BitVector()) {
6857 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6858 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6859 Item, DAG.getIntPtrConstant(0));
6861 assert(VT.is128BitVector() && "Expected an SSE value type!");
6862 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6863 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6864 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6867 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6868 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6869 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6870 if (VT.is256BitVector()) {
6871 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6872 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6874 assert(VT.is128BitVector() && "Expected an SSE value type!");
6875 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6881 // Is it a vector logical left shift?
6882 if (NumElems == 2 && Idx == 1 &&
6883 X86::isZeroNode(Op.getOperand(0)) &&
6884 !X86::isZeroNode(Op.getOperand(1))) {
6885 unsigned NumBits = VT.getSizeInBits();
6886 return getVShift(true, VT,
6887 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6888 VT, Op.getOperand(1)),
6889 NumBits/2, DAG, *this, dl);
6892 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6895 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6896 // is a non-constant being inserted into an element other than the low one,
6897 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6898 // movd/movss) to move this into the low element, then shuffle it into
6900 if (EVTBits == 32) {
6901 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6903 // If using the new shuffle lowering, just directly insert this.
6904 if (ExperimentalVectorShuffleLowering)
6905 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6907 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6908 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6909 SmallVector<int, 8> MaskVec;
6910 for (unsigned i = 0; i != NumElems; ++i)
6911 MaskVec.push_back(i == Idx ? 0 : 1);
6912 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6916 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6917 if (Values.size() == 1) {
6918 if (EVTBits == 32) {
6919 // Instead of a shuffle like this:
6920 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6921 // Check if it's possible to issue this instead.
6922 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6923 unsigned Idx = countTrailingZeros(NonZeros);
6924 SDValue Item = Op.getOperand(Idx);
6925 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6926 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6931 // A vector full of immediates; various special cases are already
6932 // handled, so this is best done with a single constant-pool load.
6936 // For AVX-length vectors, build the individual 128-bit pieces and use
6937 // shuffles to put them in place.
6938 if (VT.is256BitVector() || VT.is512BitVector()) {
6939 SmallVector<SDValue, 64> V;
6940 for (unsigned i = 0; i != NumElems; ++i)
6941 V.push_back(Op.getOperand(i));
6943 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6945 // Build both the lower and upper subvector.
6946 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6947 makeArrayRef(&V[0], NumElems/2));
6948 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6949 makeArrayRef(&V[NumElems / 2], NumElems/2));
6951 // Recreate the wider vector with the lower and upper part.
6952 if (VT.is256BitVector())
6953 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6954 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6957 // Let legalizer expand 2-wide build_vectors.
6958 if (EVTBits == 64) {
6959 if (NumNonZero == 1) {
6960 // One half is zero or undef.
6961 unsigned Idx = countTrailingZeros(NonZeros);
6962 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6963 Op.getOperand(Idx));
6964 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6969 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6970 if (EVTBits == 8 && NumElems == 16) {
6971 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6973 if (V.getNode()) return V;
6976 if (EVTBits == 16 && NumElems == 8) {
6977 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6979 if (V.getNode()) return V;
6982 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6983 if (EVTBits == 32 && NumElems == 4) {
6984 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6985 NumZero, DAG, Subtarget, *this);
6990 // If element VT is == 32 bits, turn it into a number of shuffles.
6991 SmallVector<SDValue, 8> V(NumElems);
6992 if (NumElems == 4 && NumZero > 0) {
6993 for (unsigned i = 0; i < 4; ++i) {
6994 bool isZero = !(NonZeros & (1 << i));
6996 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6998 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7001 for (unsigned i = 0; i < 2; ++i) {
7002 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7005 V[i] = V[i*2]; // Must be a zero vector.
7008 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7011 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7014 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7019 bool Reverse1 = (NonZeros & 0x3) == 2;
7020 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7024 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7025 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7027 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7030 if (Values.size() > 1 && VT.is128BitVector()) {
7031 // Check for a build vector of consecutive loads.
7032 for (unsigned i = 0; i < NumElems; ++i)
7033 V[i] = Op.getOperand(i);
7035 // Check for elements which are consecutive loads.
7036 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7040 // Check for a build vector from mostly shuffle plus few inserting.
7041 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7045 // For SSE 4.1, use insertps to put the high elements into the low element.
7046 if (getSubtarget()->hasSSE41()) {
7048 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7049 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7051 Result = DAG.getUNDEF(VT);
7053 for (unsigned i = 1; i < NumElems; ++i) {
7054 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7055 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7056 Op.getOperand(i), DAG.getIntPtrConstant(i));
7061 // Otherwise, expand into a number of unpckl*, start by extending each of
7062 // our (non-undef) elements to the full vector width with the element in the
7063 // bottom slot of the vector (which generates no code for SSE).
7064 for (unsigned i = 0; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7066 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7068 V[i] = DAG.getUNDEF(VT);
7071 // Next, we iteratively mix elements, e.g. for v4f32:
7072 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7073 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7074 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7075 unsigned EltStride = NumElems >> 1;
7076 while (EltStride != 0) {
7077 for (unsigned i = 0; i < EltStride; ++i) {
7078 // If V[i+EltStride] is undef and this is the first round of mixing,
7079 // then it is safe to just drop this shuffle: V[i] is already in the
7080 // right place, the one element (since it's the first round) being
7081 // inserted as undef can be dropped. This isn't safe for successive
7082 // rounds because they will permute elements within both vectors.
7083 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7084 EltStride == NumElems/2)
7087 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7096 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7097 // to create 256-bit vectors from two other 128-bit ones.
7098 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7100 MVT ResVT = Op.getSimpleValueType();
7102 assert((ResVT.is256BitVector() ||
7103 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7105 SDValue V1 = Op.getOperand(0);
7106 SDValue V2 = Op.getOperand(1);
7107 unsigned NumElems = ResVT.getVectorNumElements();
7108 if(ResVT.is256BitVector())
7109 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7111 if (Op.getNumOperands() == 4) {
7112 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7113 ResVT.getVectorNumElements()/2);
7114 SDValue V3 = Op.getOperand(2);
7115 SDValue V4 = Op.getOperand(3);
7116 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7117 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7119 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7123 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7124 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7125 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7126 Op.getNumOperands() == 4)));
7128 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7129 // from two other 128-bit ones.
7131 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7132 return LowerAVXCONCAT_VECTORS(Op, DAG);
7136 //===----------------------------------------------------------------------===//
7137 // Vector shuffle lowering
7139 // This is an experimental code path for lowering vector shuffles on x86. It is
7140 // designed to handle arbitrary vector shuffles and blends, gracefully
7141 // degrading performance as necessary. It works hard to recognize idiomatic
7142 // shuffles and lower them to optimal instruction patterns without leaving
7143 // a framework that allows reasonably efficient handling of all vector shuffle
7145 //===----------------------------------------------------------------------===//
7147 /// \brief Tiny helper function to identify a no-op mask.
7149 /// This is a somewhat boring predicate function. It checks whether the mask
7150 /// array input, which is assumed to be a single-input shuffle mask of the kind
7151 /// used by the X86 shuffle instructions (not a fully general
7152 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7153 /// in-place shuffle are 'no-op's.
7154 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7155 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7156 if (Mask[i] != -1 && Mask[i] != i)
7161 /// \brief Helper function to classify a mask as a single-input mask.
7163 /// This isn't a generic single-input test because in the vector shuffle
7164 /// lowering we canonicalize single inputs to be the first input operand. This
7165 /// means we can more quickly test for a single input by only checking whether
7166 /// an input from the second operand exists. We also assume that the size of
7167 /// mask corresponds to the size of the input vectors which isn't true in the
7168 /// fully general case.
7169 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7171 if (M >= (int)Mask.size())
7176 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7177 // 2013 will allow us to use it as a non-type template parameter.
7180 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7182 /// See its documentation for details.
7183 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7184 if (Mask.size() != Args.size())
7186 for (int i = 0, e = Mask.size(); i < e; ++i) {
7187 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7188 if (Mask[i] != -1 && Mask[i] != *Args[i])
7196 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7199 /// This is a fast way to test a shuffle mask against a fixed pattern:
7201 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7203 /// It returns true if the mask is exactly as wide as the argument list, and
7204 /// each element of the mask is either -1 (signifying undef) or the value given
7205 /// in the argument.
7206 static const VariadicFunction1<
7207 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7209 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7211 /// This helper function produces an 8-bit shuffle immediate corresponding to
7212 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7213 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7216 /// NB: We rely heavily on "undef" masks preserving the input lane.
7217 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7218 SelectionDAG &DAG) {
7219 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7220 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7221 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7222 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7223 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7226 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7227 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7228 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7229 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7230 return DAG.getConstant(Imm, MVT::i8);
7233 /// \brief Try to emit a blend instruction for a shuffle.
7235 /// This doesn't do any checks for the availability of instructions for blending
7236 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7237 /// be matched in the backend with the type given. What it does check for is
7238 /// that the shuffle mask is in fact a blend.
7239 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7240 SDValue V2, ArrayRef<int> Mask,
7241 SelectionDAG &DAG) {
7243 unsigned BlendMask = 0;
7244 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7245 if (Mask[i] >= Size) {
7246 if (Mask[i] != i + Size)
7247 return SDValue(); // Shuffled V2 input!
7248 BlendMask |= 1u << i;
7251 if (Mask[i] >= 0 && Mask[i] != i)
7252 return SDValue(); // Shuffled V1 input!
7254 switch (VT.SimpleTy) {
7259 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7260 DAG.getConstant(BlendMask, MVT::i8));
7265 // For integer shuffles we need to expand the mask and cast the inputs to
7266 // v8i16s prior to blending.
7267 int Scale = 8 / VT.getVectorNumElements();
7269 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7270 if (Mask[i] >= Size)
7271 for (int j = 0; j < Scale; ++j)
7272 BlendMask |= 1u << (i * Scale + j);
7274 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7275 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7276 return DAG.getNode(ISD::BITCAST, DL, VT,
7277 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7278 DAG.getConstant(BlendMask, MVT::i8)));
7282 llvm_unreachable("Not a supported integer vector type!");
7286 /// \brief Try to lower a vector shuffle as a byte rotation.
7288 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7289 /// byte-rotation of a the concatentation of two vectors. This routine will
7290 /// try to generically lower a vector shuffle through such an instruction. It
7291 /// does not check for the availability of PALIGNR-based lowerings, only the
7292 /// applicability of this strategy to the given mask. This matches shuffle
7293 /// vectors that look like:
7295 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7297 /// Essentially it concatenates V1 and V2, shifts right by some number of
7298 /// elements, and takes the low elements as the result. Note that while this is
7299 /// specified as a *right shift* because x86 is little-endian, it is a *left
7300 /// rotate* of the vector lanes.
7302 /// Note that this only handles 128-bit vector widths currently.
7303 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7306 SelectionDAG &DAG) {
7307 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7309 // We need to detect various ways of spelling a rotation:
7310 // [11, 12, 13, 14, 15, 0, 1, 2]
7311 // [-1, 12, 13, 14, -1, -1, 1, -1]
7312 // [-1, -1, -1, -1, -1, -1, 1, 2]
7313 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7314 // [-1, 4, 5, 6, -1, -1, 9, -1]
7315 // [-1, 4, 5, 6, -1, -1, -1, -1]
7318 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7321 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7323 // Based on the mod-Size value of this mask element determine where
7324 // a rotated vector would have started.
7325 int StartIdx = i - (Mask[i] % Size);
7327 // The identity rotation isn't interesting, stop.
7330 // If we found the tail of a vector the rotation must be the missing
7331 // front. If we found the head of a vector, it must be how much of the head.
7332 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7335 Rotation = CandidateRotation;
7336 else if (Rotation != CandidateRotation)
7337 // The rotations don't match, so we can't match this mask.
7340 // Compute which value this mask is pointing at.
7341 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7343 // Compute which of the two target values this index should be assigned to.
7344 // This reflects whether the high elements are remaining or the low elements
7346 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7348 // Either set up this value if we've not encountered it before, or check
7349 // that it remains consistent.
7352 else if (TargetV != MaskV)
7353 // This may be a rotation, but it pulls from the inputs in some
7354 // unsupported interleaving.
7358 // Check that we successfully analyzed the mask, and normalize the results.
7359 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7360 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7366 // Cast the inputs to v16i8 to match PALIGNR.
7367 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7368 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7370 assert(VT.getSizeInBits() == 128 &&
7371 "Rotate-based lowering only supports 128-bit lowering!");
7372 assert(Mask.size() <= 16 &&
7373 "Can shuffle at most 16 bytes in a 128-bit vector!");
7374 // The actual rotate instruction rotates bytes, so we need to scale the
7375 // rotation based on how many bytes are in the vector.
7376 int Scale = 16 / Mask.size();
7378 return DAG.getNode(ISD::BITCAST, DL, VT,
7379 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7380 DAG.getConstant(Rotation * Scale, MVT::i8)));
7383 /// \brief Compute whether each element of a shuffle is zeroable.
7385 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7386 /// Either it is an undef element in the shuffle mask, the element of the input
7387 /// referenced is undef, or the element of the input referenced is known to be
7388 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7389 /// as many lanes with this technique as possible to simplify the remaining
7391 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7392 SDValue V1, SDValue V2) {
7393 SmallBitVector Zeroable(Mask.size(), false);
7395 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7396 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7398 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7400 // Handle the easy cases.
7401 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7406 // If this is an index into a build_vector node, dig out the input value and
7408 SDValue V = M < Size ? V1 : V2;
7409 if (V.getOpcode() != ISD::BUILD_VECTOR)
7412 SDValue Input = V.getOperand(M % Size);
7413 // The UNDEF opcode check really should be dead code here, but not quite
7414 // worth asserting on (it isn't invalid, just unexpected).
7415 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7422 /// \brief Lower a vector shuffle as a zero or any extension.
7424 /// Given a specific number of elements, element bit width, and extension
7425 /// stride, produce either a zero or any extension based on the available
7426 /// features of the subtarget.
7427 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7428 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7429 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7430 assert(Scale > 1 && "Need a scale to extend.");
7431 int EltBits = VT.getSizeInBits() / NumElements;
7432 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7433 "Only 8, 16, and 32 bit elements can be extended.");
7434 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7436 // Found a valid zext mask! Try various lowering strategies based on the
7437 // input type and available ISA extensions.
7438 if (Subtarget->hasSSE41()) {
7439 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7440 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7441 NumElements / Scale);
7442 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7443 return DAG.getNode(ISD::BITCAST, DL, VT,
7444 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7447 // For any extends we can cheat for larger element sizes and use shuffle
7448 // instructions that can fold with a load and/or copy.
7449 if (AnyExt && EltBits == 32) {
7450 int PSHUFDMask[4] = {0, -1, 1, -1};
7452 ISD::BITCAST, DL, VT,
7453 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7454 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7455 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7457 if (AnyExt && EltBits == 16 && Scale > 2) {
7458 int PSHUFDMask[4] = {0, -1, 0, -1};
7459 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7460 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7461 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7462 int PSHUFHWMask[4] = {1, -1, -1, -1};
7464 ISD::BITCAST, DL, VT,
7465 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7466 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7467 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7470 // If this would require more than 2 unpack instructions to expand, use
7471 // pshufb when available. We can only use more than 2 unpack instructions
7472 // when zero extending i8 elements which also makes it easier to use pshufb.
7473 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7474 assert(NumElements == 16 && "Unexpected byte vector width!");
7475 SDValue PSHUFBMask[16];
7476 for (int i = 0; i < 16; ++i)
7478 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7479 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7480 return DAG.getNode(ISD::BITCAST, DL, VT,
7481 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7482 DAG.getNode(ISD::BUILD_VECTOR, DL,
7483 MVT::v16i8, PSHUFBMask)));
7486 // Otherwise emit a sequence of unpacks.
7488 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7489 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7490 : getZeroVector(InputVT, Subtarget, DAG, DL);
7491 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7492 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7496 } while (Scale > 1);
7497 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7500 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7502 /// This routine will try to do everything in its power to cleverly lower
7503 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7504 /// check for the profitability of this lowering, it tries to aggressively
7505 /// match this pattern. It will use all of the micro-architectural details it
7506 /// can to emit an efficient lowering. It handles both blends with all-zero
7507 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7508 /// masking out later).
7510 /// The reason we have dedicated lowering for zext-style shuffles is that they
7511 /// are both incredibly common and often quite performance sensitive.
7512 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7513 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7514 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7515 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7517 int Bits = VT.getSizeInBits();
7518 int NumElements = Mask.size();
7520 // Define a helper function to check a particular ext-scale and lower to it if
7522 auto Lower = [&](int Scale) -> SDValue {
7525 for (int i = 0; i < NumElements; ++i) {
7527 continue; // Valid anywhere but doesn't tell us anything.
7528 if (i % Scale != 0) {
7529 // Each of the extend elements needs to be zeroable.
7533 // We no lorger are in the anyext case.
7538 // Each of the base elements needs to be consecutive indices into the
7539 // same input vector.
7540 SDValue V = Mask[i] < NumElements ? V1 : V2;
7543 else if (InputV != V)
7544 return SDValue(); // Flip-flopping inputs.
7546 if (Mask[i] % NumElements != i / Scale)
7547 return SDValue(); // Non-consecutive strided elemenst.
7550 // If we fail to find an input, we have a zero-shuffle which should always
7551 // have already been handled.
7552 // FIXME: Maybe handle this here in case during blending we end up with one?
7556 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7557 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7560 // The widest scale possible for extending is to a 64-bit integer.
7561 assert(Bits % 64 == 0 &&
7562 "The number of bits in a vector must be divisible by 64 on x86!");
7563 int NumExtElements = Bits / 64;
7565 // Each iteration, try extending the elements half as much, but into twice as
7567 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7568 assert(NumElements % NumExtElements == 0 &&
7569 "The input vector size must be divisble by the extended size.");
7570 if (SDValue V = Lower(NumElements / NumExtElements))
7574 // No viable ext lowering found.
7578 /// \brief Try to lower insertion of a single element into a zero vector.
7580 /// This is a common pattern that we have especially efficient patterns to lower
7581 /// across all subtarget feature sets.
7582 static SDValue lowerVectorShuffleAsElementInsertion(
7583 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7584 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7585 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7587 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7588 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7590 if (Mask.size() == 2) {
7591 if (!Zeroable[V2Index ^ 1]) {
7592 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7593 // with 2 to flip from {2,3} to {0,1} and vice versa.
7594 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7595 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7596 if (Zeroable[V2Index])
7597 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7603 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7604 if (i != V2Index && !Zeroable[i])
7605 return SDValue(); // Not inserting into a zero vector.
7608 // Step over any bitcasts on either input so we can scan the actual
7609 // BUILD_VECTOR nodes.
7610 while (V1.getOpcode() == ISD::BITCAST)
7611 V1 = V1.getOperand(0);
7612 while (V2.getOpcode() == ISD::BITCAST)
7613 V2 = V2.getOperand(0);
7615 // Check for a single input from a SCALAR_TO_VECTOR node.
7616 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7617 // all the smarts here sunk into that routine. However, the current
7618 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7619 // vector shuffle lowering is dead.
7620 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7621 Mask[V2Index] == (int)Mask.size()) ||
7622 V2.getOpcode() == ISD::BUILD_VECTOR))
7625 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7627 // First, we need to zext the scalar if it is smaller than an i32.
7629 MVT EltVT = VT.getVectorElementType();
7630 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7631 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7632 // Zero-extend directly to i32.
7634 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7637 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7638 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7640 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7643 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7644 // the desired position. Otherwise it is more efficient to do a vector
7645 // shift left. We know that we can do a vector shift left because all
7646 // the inputs are zero.
7647 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7648 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7649 V2Shuffle[V2Index] = 0;
7650 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7652 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7654 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7656 V2Index * EltVT.getSizeInBits(),
7657 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7658 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7664 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7666 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7667 /// support for floating point shuffles but not integer shuffles. These
7668 /// instructions will incur a domain crossing penalty on some chips though so
7669 /// it is better to avoid lowering through this for integer vectors where
7671 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7672 const X86Subtarget *Subtarget,
7673 SelectionDAG &DAG) {
7675 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7676 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7677 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7679 ArrayRef<int> Mask = SVOp->getMask();
7680 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7682 if (isSingleInputShuffleMask(Mask)) {
7683 // Straight shuffle of a single input vector. Simulate this by using the
7684 // single input as both of the "inputs" to this instruction..
7685 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7687 if (Subtarget->hasAVX()) {
7688 // If we have AVX, we can use VPERMILPS which will allow folding a load
7689 // into the shuffle.
7690 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v2f64, V1,
7691 DAG.getConstant(SHUFPDMask, MVT::i8));
7694 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7695 DAG.getConstant(SHUFPDMask, MVT::i8));
7697 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7698 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7700 // Use dedicated unpack instructions for masks that match their pattern.
7701 if (isShuffleEquivalent(Mask, 0, 2))
7702 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7703 if (isShuffleEquivalent(Mask, 1, 3))
7704 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7706 // If we have a single input, insert that into V1 if we can do so cheaply.
7707 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7708 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7709 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7712 if (Subtarget->hasSSE41())
7714 lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask, DAG))
7717 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7718 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7719 DAG.getConstant(SHUFPDMask, MVT::i8));
7722 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7724 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7725 /// the integer unit to minimize domain crossing penalties. However, for blends
7726 /// it falls back to the floating point shuffle operation with appropriate bit
7728 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7729 const X86Subtarget *Subtarget,
7730 SelectionDAG &DAG) {
7732 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7733 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7734 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7736 ArrayRef<int> Mask = SVOp->getMask();
7737 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7739 if (isSingleInputShuffleMask(Mask)) {
7740 // Straight shuffle of a single input vector. For everything from SSE2
7741 // onward this has a single fast instruction with no scary immediates.
7742 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7743 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7744 int WidenedMask[4] = {
7745 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7746 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7748 ISD::BITCAST, DL, MVT::v2i64,
7749 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7750 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7753 // Use dedicated unpack instructions for masks that match their pattern.
7754 if (isShuffleEquivalent(Mask, 0, 2))
7755 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7756 if (isShuffleEquivalent(Mask, 1, 3))
7757 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7759 // If we have a single input from V2 insert that into V1 if we can do so
7761 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7762 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7763 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7766 if (Subtarget->hasSSE41())
7768 lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask, DAG))
7771 // Try to use rotation instructions if available.
7772 if (Subtarget->hasSSSE3())
7773 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7774 DL, MVT::v2i64, V1, V2, Mask, DAG))
7777 // We implement this with SHUFPD which is pretty lame because it will likely
7778 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7779 // However, all the alternatives are still more cycles and newer chips don't
7780 // have this problem. It would be really nice if x86 had better shuffles here.
7781 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7782 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7783 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7784 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7787 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7789 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7790 /// It makes no assumptions about whether this is the *best* lowering, it simply
7792 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7793 ArrayRef<int> Mask, SDValue V1,
7794 SDValue V2, SelectionDAG &DAG) {
7795 SDValue LowV = V1, HighV = V2;
7796 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7799 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7801 if (NumV2Elements == 1) {
7803 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7806 // Compute the index adjacent to V2Index and in the same half by toggling
7808 int V2AdjIndex = V2Index ^ 1;
7810 if (Mask[V2AdjIndex] == -1) {
7811 // Handles all the cases where we have a single V2 element and an undef.
7812 // This will only ever happen in the high lanes because we commute the
7813 // vector otherwise.
7815 std::swap(LowV, HighV);
7816 NewMask[V2Index] -= 4;
7818 // Handle the case where the V2 element ends up adjacent to a V1 element.
7819 // To make this work, blend them together as the first step.
7820 int V1Index = V2AdjIndex;
7821 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7822 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7823 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7825 // Now proceed to reconstruct the final blend as we have the necessary
7826 // high or low half formed.
7833 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7834 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7836 } else if (NumV2Elements == 2) {
7837 if (Mask[0] < 4 && Mask[1] < 4) {
7838 // Handle the easy case where we have V1 in the low lanes and V2 in the
7839 // high lanes. We never see this reversed because we sort the shuffle.
7843 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7844 // trying to place elements directly, just blend them and set up the final
7845 // shuffle to place them.
7847 // The first two blend mask elements are for V1, the second two are for
7849 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7850 Mask[2] < 4 ? Mask[2] : Mask[3],
7851 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7852 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7853 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7854 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7856 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7859 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7860 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7861 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7862 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7865 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7866 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7869 /// \brief Lower 4-lane 32-bit floating point shuffles.
7871 /// Uses instructions exclusively from the floating point unit to minimize
7872 /// domain crossing penalties, as these are sufficient to implement all v4f32
7874 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7875 const X86Subtarget *Subtarget,
7876 SelectionDAG &DAG) {
7878 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7879 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7880 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7881 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7882 ArrayRef<int> Mask = SVOp->getMask();
7883 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7886 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7888 if (NumV2Elements == 0) {
7889 if (Subtarget->hasAVX()) {
7890 // If we have AVX, we can use VPERMILPS which will allow folding a load
7891 // into the shuffle.
7892 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f32, V1,
7893 getV4X86ShuffleImm8ForMask(Mask, DAG));
7896 // Otherwise, use a straight shuffle of a single input vector. We pass the
7897 // input vector to both operands to simulate this with a SHUFPS.
7898 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7899 getV4X86ShuffleImm8ForMask(Mask, DAG));
7902 // Use dedicated unpack instructions for masks that match their pattern.
7903 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7904 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7905 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7906 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7908 // There are special ways we can lower some single-element blends. However, we
7909 // have custom ways we can lower more complex single-element blends below that
7910 // we defer to if both this and BLENDPS fail to match, so restrict this to
7911 // when the V2 input is targeting element 0 of the mask -- that is the fast
7913 if (NumV2Elements == 1 && Mask[0] >= 4)
7914 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7915 Mask, Subtarget, DAG))
7918 if (Subtarget->hasSSE41())
7920 lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask, DAG))
7923 // Check for whether we can use INSERTPS to perform the blend. We only use
7924 // INSERTPS when the V1 elements are already in the correct locations
7925 // because otherwise we can just always use two SHUFPS instructions which
7926 // are much smaller to encode than a SHUFPS and an INSERTPS.
7927 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
7929 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7932 // When using INSERTPS we can zero any lane of the destination. Collect
7933 // the zero inputs into a mask and drop them from the lanes of V1 which
7934 // actually need to be present as inputs to the INSERTPS.
7935 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7937 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7938 bool InsertNeedsShuffle = false;
7940 for (int i = 0; i < 4; ++i)
7944 } else if (Mask[i] != i) {
7945 InsertNeedsShuffle = true;
7950 // We don't want to use INSERTPS or other insertion techniques if it will
7951 // require shuffling anyways.
7952 if (!InsertNeedsShuffle) {
7953 // If all of V1 is zeroable, replace it with undef.
7954 if ((ZMask | 1 << V2Index) == 0xF)
7955 V1 = DAG.getUNDEF(MVT::v4f32);
7957 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7958 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7960 // Insert the V2 element into the desired position.
7961 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7962 DAG.getConstant(InsertPSMask, MVT::i8));
7966 // Otherwise fall back to a SHUFPS lowering strategy.
7967 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7970 /// \brief Lower 4-lane i32 vector shuffles.
7972 /// We try to handle these with integer-domain shuffles where we can, but for
7973 /// blends we use the floating point domain blend instructions.
7974 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7975 const X86Subtarget *Subtarget,
7976 SelectionDAG &DAG) {
7978 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7979 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7980 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7982 ArrayRef<int> Mask = SVOp->getMask();
7983 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7986 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7988 if (NumV2Elements == 0) {
7989 // Straight shuffle of a single input vector. For everything from SSE2
7990 // onward this has a single fast instruction with no scary immediates.
7991 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7992 // but we aren't actually going to use the UNPCK instruction because doing
7993 // so prevents folding a load into this instruction or making a copy.
7994 const int UnpackLoMask[] = {0, 0, 1, 1};
7995 const int UnpackHiMask[] = {2, 2, 3, 3};
7996 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
7997 Mask = UnpackLoMask;
7998 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
7999 Mask = UnpackHiMask;
8001 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8002 getV4X86ShuffleImm8ForMask(Mask, DAG));
8005 // Whenever we can lower this as a zext, that instruction is strictly faster
8006 // than any alternative.
8007 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8008 Mask, Subtarget, DAG))
8011 // Use dedicated unpack instructions for masks that match their pattern.
8012 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8013 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8014 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8015 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8017 // There are special ways we can lower some single-element blends.
8018 if (NumV2Elements == 1)
8019 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8020 Mask, Subtarget, DAG))
8023 if (Subtarget->hasSSE41())
8025 lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask, DAG))
8028 // Try to use rotation instructions if available.
8029 if (Subtarget->hasSSSE3())
8030 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8031 DL, MVT::v4i32, V1, V2, Mask, DAG))
8034 // We implement this with SHUFPS because it can blend from two vectors.
8035 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8036 // up the inputs, bypassing domain shift penalties that we would encur if we
8037 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8039 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8040 DAG.getVectorShuffle(
8042 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8043 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8046 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8047 /// shuffle lowering, and the most complex part.
8049 /// The lowering strategy is to try to form pairs of input lanes which are
8050 /// targeted at the same half of the final vector, and then use a dword shuffle
8051 /// to place them onto the right half, and finally unpack the paired lanes into
8052 /// their final position.
8054 /// The exact breakdown of how to form these dword pairs and align them on the
8055 /// correct sides is really tricky. See the comments within the function for
8056 /// more of the details.
8057 static SDValue lowerV8I16SingleInputVectorShuffle(
8058 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8059 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8060 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8061 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8062 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8064 SmallVector<int, 4> LoInputs;
8065 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8066 [](int M) { return M >= 0; });
8067 std::sort(LoInputs.begin(), LoInputs.end());
8068 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8069 SmallVector<int, 4> HiInputs;
8070 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8071 [](int M) { return M >= 0; });
8072 std::sort(HiInputs.begin(), HiInputs.end());
8073 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8075 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8076 int NumHToL = LoInputs.size() - NumLToL;
8078 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8079 int NumHToH = HiInputs.size() - NumLToH;
8080 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8081 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8082 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8083 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8085 // Use dedicated unpack instructions for masks that match their pattern.
8086 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8087 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8088 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8089 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8091 // Try to use rotation instructions if available.
8092 if (Subtarget->hasSSSE3())
8093 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8094 DL, MVT::v8i16, V, V, Mask, DAG))
8097 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8098 // such inputs we can swap two of the dwords across the half mark and end up
8099 // with <=2 inputs to each half in each half. Once there, we can fall through
8100 // to the generic code below. For example:
8102 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8103 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8105 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8106 // and an existing 2-into-2 on the other half. In this case we may have to
8107 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8108 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8109 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8110 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8111 // half than the one we target for fixing) will be fixed when we re-enter this
8112 // path. We will also combine away any sequence of PSHUFD instructions that
8113 // result into a single instruction. Here is an example of the tricky case:
8115 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8116 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8118 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8120 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8121 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8123 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8124 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8126 // The result is fine to be handled by the generic logic.
8127 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8128 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8129 int AOffset, int BOffset) {
8130 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8131 "Must call this with A having 3 or 1 inputs from the A half.");
8132 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8133 "Must call this with B having 1 or 3 inputs from the B half.");
8134 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8135 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8137 // Compute the index of dword with only one word among the three inputs in
8138 // a half by taking the sum of the half with three inputs and subtracting
8139 // the sum of the actual three inputs. The difference is the remaining
8142 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8143 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8144 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8145 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8146 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8147 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8148 int TripleNonInputIdx =
8149 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8150 TripleDWord = TripleNonInputIdx / 2;
8152 // We use xor with one to compute the adjacent DWord to whichever one the
8154 OneInputDWord = (OneInput / 2) ^ 1;
8156 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8157 // and BToA inputs. If there is also such a problem with the BToB and AToB
8158 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8159 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8160 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8161 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8162 // Compute how many inputs will be flipped by swapping these DWords. We
8164 // to balance this to ensure we don't form a 3-1 shuffle in the other
8166 int NumFlippedAToBInputs =
8167 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8168 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8169 int NumFlippedBToBInputs =
8170 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8171 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8172 if ((NumFlippedAToBInputs == 1 &&
8173 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8174 (NumFlippedBToBInputs == 1 &&
8175 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8176 // We choose whether to fix the A half or B half based on whether that
8177 // half has zero flipped inputs. At zero, we may not be able to fix it
8178 // with that half. We also bias towards fixing the B half because that
8179 // will more commonly be the high half, and we have to bias one way.
8180 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8181 ArrayRef<int> Inputs) {
8182 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8183 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8184 PinnedIdx ^ 1) != Inputs.end();
8185 // Determine whether the free index is in the flipped dword or the
8186 // unflipped dword based on where the pinned index is. We use this bit
8187 // in an xor to conditionally select the adjacent dword.
8188 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8189 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8190 FixFreeIdx) != Inputs.end();
8191 if (IsFixIdxInput == IsFixFreeIdxInput)
8193 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8194 FixFreeIdx) != Inputs.end();
8195 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8196 "We need to be changing the number of flipped inputs!");
8197 int PSHUFHalfMask[] = {0, 1, 2, 3};
8198 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8199 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8201 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8204 if (M != -1 && M == FixIdx)
8206 else if (M != -1 && M == FixFreeIdx)
8209 if (NumFlippedBToBInputs != 0) {
8211 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8212 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8214 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8216 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8217 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8222 int PSHUFDMask[] = {0, 1, 2, 3};
8223 PSHUFDMask[ADWord] = BDWord;
8224 PSHUFDMask[BDWord] = ADWord;
8225 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8226 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8227 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8228 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8230 // Adjust the mask to match the new locations of A and B.
8232 if (M != -1 && M/2 == ADWord)
8233 M = 2 * BDWord + M % 2;
8234 else if (M != -1 && M/2 == BDWord)
8235 M = 2 * ADWord + M % 2;
8237 // Recurse back into this routine to re-compute state now that this isn't
8238 // a 3 and 1 problem.
8239 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8242 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8243 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8244 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8245 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8247 // At this point there are at most two inputs to the low and high halves from
8248 // each half. That means the inputs can always be grouped into dwords and
8249 // those dwords can then be moved to the correct half with a dword shuffle.
8250 // We use at most one low and one high word shuffle to collect these paired
8251 // inputs into dwords, and finally a dword shuffle to place them.
8252 int PSHUFLMask[4] = {-1, -1, -1, -1};
8253 int PSHUFHMask[4] = {-1, -1, -1, -1};
8254 int PSHUFDMask[4] = {-1, -1, -1, -1};
8256 // First fix the masks for all the inputs that are staying in their
8257 // original halves. This will then dictate the targets of the cross-half
8259 auto fixInPlaceInputs =
8260 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8261 MutableArrayRef<int> SourceHalfMask,
8262 MutableArrayRef<int> HalfMask, int HalfOffset) {
8263 if (InPlaceInputs.empty())
8265 if (InPlaceInputs.size() == 1) {
8266 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8267 InPlaceInputs[0] - HalfOffset;
8268 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8271 if (IncomingInputs.empty()) {
8272 // Just fix all of the in place inputs.
8273 for (int Input : InPlaceInputs) {
8274 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8275 PSHUFDMask[Input / 2] = Input / 2;
8280 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8281 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8282 InPlaceInputs[0] - HalfOffset;
8283 // Put the second input next to the first so that they are packed into
8284 // a dword. We find the adjacent index by toggling the low bit.
8285 int AdjIndex = InPlaceInputs[0] ^ 1;
8286 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8287 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8288 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8290 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8291 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8293 // Now gather the cross-half inputs and place them into a free dword of
8294 // their target half.
8295 // FIXME: This operation could almost certainly be simplified dramatically to
8296 // look more like the 3-1 fixing operation.
8297 auto moveInputsToRightHalf = [&PSHUFDMask](
8298 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8299 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8300 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8302 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8303 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8305 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8307 int LowWord = Word & ~1;
8308 int HighWord = Word | 1;
8309 return isWordClobbered(SourceHalfMask, LowWord) ||
8310 isWordClobbered(SourceHalfMask, HighWord);
8313 if (IncomingInputs.empty())
8316 if (ExistingInputs.empty()) {
8317 // Map any dwords with inputs from them into the right half.
8318 for (int Input : IncomingInputs) {
8319 // If the source half mask maps over the inputs, turn those into
8320 // swaps and use the swapped lane.
8321 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8322 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8323 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8324 Input - SourceOffset;
8325 // We have to swap the uses in our half mask in one sweep.
8326 for (int &M : HalfMask)
8327 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8329 else if (M == Input)
8330 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8332 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8333 Input - SourceOffset &&
8334 "Previous placement doesn't match!");
8336 // Note that this correctly re-maps both when we do a swap and when
8337 // we observe the other side of the swap above. We rely on that to
8338 // avoid swapping the members of the input list directly.
8339 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8342 // Map the input's dword into the correct half.
8343 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8344 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8346 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8348 "Previous placement doesn't match!");
8351 // And just directly shift any other-half mask elements to be same-half
8352 // as we will have mirrored the dword containing the element into the
8353 // same position within that half.
8354 for (int &M : HalfMask)
8355 if (M >= SourceOffset && M < SourceOffset + 4) {
8356 M = M - SourceOffset + DestOffset;
8357 assert(M >= 0 && "This should never wrap below zero!");
8362 // Ensure we have the input in a viable dword of its current half. This
8363 // is particularly tricky because the original position may be clobbered
8364 // by inputs being moved and *staying* in that half.
8365 if (IncomingInputs.size() == 1) {
8366 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8367 int InputFixed = std::find(std::begin(SourceHalfMask),
8368 std::end(SourceHalfMask), -1) -
8369 std::begin(SourceHalfMask) + SourceOffset;
8370 SourceHalfMask[InputFixed - SourceOffset] =
8371 IncomingInputs[0] - SourceOffset;
8372 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8374 IncomingInputs[0] = InputFixed;
8376 } else if (IncomingInputs.size() == 2) {
8377 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8378 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8379 // We have two non-adjacent or clobbered inputs we need to extract from
8380 // the source half. To do this, we need to map them into some adjacent
8381 // dword slot in the source mask.
8382 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8383 IncomingInputs[1] - SourceOffset};
8385 // If there is a free slot in the source half mask adjacent to one of
8386 // the inputs, place the other input in it. We use (Index XOR 1) to
8387 // compute an adjacent index.
8388 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8389 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8390 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8391 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8392 InputsFixed[1] = InputsFixed[0] ^ 1;
8393 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8394 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8395 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8396 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8397 InputsFixed[0] = InputsFixed[1] ^ 1;
8398 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8399 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8400 // The two inputs are in the same DWord but it is clobbered and the
8401 // adjacent DWord isn't used at all. Move both inputs to the free
8403 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8404 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8405 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8406 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8408 // The only way we hit this point is if there is no clobbering
8409 // (because there are no off-half inputs to this half) and there is no
8410 // free slot adjacent to one of the inputs. In this case, we have to
8411 // swap an input with a non-input.
8412 for (int i = 0; i < 4; ++i)
8413 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8414 "We can't handle any clobbers here!");
8415 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8416 "Cannot have adjacent inputs here!");
8418 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8419 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8421 // We also have to update the final source mask in this case because
8422 // it may need to undo the above swap.
8423 for (int &M : FinalSourceHalfMask)
8424 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8425 M = InputsFixed[1] + SourceOffset;
8426 else if (M == InputsFixed[1] + SourceOffset)
8427 M = (InputsFixed[0] ^ 1) + SourceOffset;
8429 InputsFixed[1] = InputsFixed[0] ^ 1;
8432 // Point everything at the fixed inputs.
8433 for (int &M : HalfMask)
8434 if (M == IncomingInputs[0])
8435 M = InputsFixed[0] + SourceOffset;
8436 else if (M == IncomingInputs[1])
8437 M = InputsFixed[1] + SourceOffset;
8439 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8440 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8443 llvm_unreachable("Unhandled input size!");
8446 // Now hoist the DWord down to the right half.
8447 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8448 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8449 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8450 for (int &M : HalfMask)
8451 for (int Input : IncomingInputs)
8453 M = FreeDWord * 2 + Input % 2;
8455 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8456 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8457 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8458 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8460 // Now enact all the shuffles we've computed to move the inputs into their
8462 if (!isNoopShuffleMask(PSHUFLMask))
8463 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8464 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8465 if (!isNoopShuffleMask(PSHUFHMask))
8466 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8467 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8468 if (!isNoopShuffleMask(PSHUFDMask))
8469 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8470 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8471 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8472 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8474 // At this point, each half should contain all its inputs, and we can then
8475 // just shuffle them into their final position.
8476 assert(std::count_if(LoMask.begin(), LoMask.end(),
8477 [](int M) { return M >= 4; }) == 0 &&
8478 "Failed to lift all the high half inputs to the low mask!");
8479 assert(std::count_if(HiMask.begin(), HiMask.end(),
8480 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8481 "Failed to lift all the low half inputs to the high mask!");
8483 // Do a half shuffle for the low mask.
8484 if (!isNoopShuffleMask(LoMask))
8485 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8486 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8488 // Do a half shuffle with the high mask after shifting its values down.
8489 for (int &M : HiMask)
8492 if (!isNoopShuffleMask(HiMask))
8493 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8494 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8499 /// \brief Detect whether the mask pattern should be lowered through
8502 /// This essentially tests whether viewing the mask as an interleaving of two
8503 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8504 /// lowering it through interleaving is a significantly better strategy.
8505 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8506 int NumEvenInputs[2] = {0, 0};
8507 int NumOddInputs[2] = {0, 0};
8508 int NumLoInputs[2] = {0, 0};
8509 int NumHiInputs[2] = {0, 0};
8510 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8514 int InputIdx = Mask[i] >= Size;
8517 ++NumLoInputs[InputIdx];
8519 ++NumHiInputs[InputIdx];
8522 ++NumEvenInputs[InputIdx];
8524 ++NumOddInputs[InputIdx];
8527 // The minimum number of cross-input results for both the interleaved and
8528 // split cases. If interleaving results in fewer cross-input results, return
8530 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8531 NumEvenInputs[0] + NumOddInputs[1]);
8532 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8533 NumLoInputs[0] + NumHiInputs[1]);
8534 return InterleavedCrosses < SplitCrosses;
8537 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8539 /// This strategy only works when the inputs from each vector fit into a single
8540 /// half of that vector, and generally there are not so many inputs as to leave
8541 /// the in-place shuffles required highly constrained (and thus expensive). It
8542 /// shifts all the inputs into a single side of both input vectors and then
8543 /// uses an unpack to interleave these inputs in a single vector. At that
8544 /// point, we will fall back on the generic single input shuffle lowering.
8545 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8547 MutableArrayRef<int> Mask,
8548 const X86Subtarget *Subtarget,
8549 SelectionDAG &DAG) {
8550 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8551 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8552 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8553 for (int i = 0; i < 8; ++i)
8554 if (Mask[i] >= 0 && Mask[i] < 4)
8555 LoV1Inputs.push_back(i);
8556 else if (Mask[i] >= 4 && Mask[i] < 8)
8557 HiV1Inputs.push_back(i);
8558 else if (Mask[i] >= 8 && Mask[i] < 12)
8559 LoV2Inputs.push_back(i);
8560 else if (Mask[i] >= 12)
8561 HiV2Inputs.push_back(i);
8563 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8564 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8567 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8568 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8569 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8571 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8572 HiV1Inputs.size() + HiV2Inputs.size();
8574 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8575 ArrayRef<int> HiInputs, bool MoveToLo,
8577 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8578 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8579 if (BadInputs.empty())
8582 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8583 int MoveOffset = MoveToLo ? 0 : 4;
8585 if (GoodInputs.empty()) {
8586 for (int BadInput : BadInputs) {
8587 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8588 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8591 if (GoodInputs.size() == 2) {
8592 // If the low inputs are spread across two dwords, pack them into
8594 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8595 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8596 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8597 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8599 // Otherwise pin the good inputs.
8600 for (int GoodInput : GoodInputs)
8601 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8604 if (BadInputs.size() == 2) {
8605 // If we have two bad inputs then there may be either one or two good
8606 // inputs fixed in place. Find a fixed input, and then find the *other*
8607 // two adjacent indices by using modular arithmetic.
8609 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8610 [](int M) { return M >= 0; }) -
8611 std::begin(MoveMask);
8613 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8614 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8615 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8616 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8617 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8618 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8619 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8621 assert(BadInputs.size() == 1 && "All sizes handled");
8622 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8623 std::end(MoveMask), -1) -
8624 std::begin(MoveMask);
8625 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8626 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8630 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8633 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8635 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8638 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8639 // cross-half traffic in the final shuffle.
8641 // Munge the mask to be a single-input mask after the unpack merges the
8645 M = 2 * (M % 4) + (M / 8);
8647 return DAG.getVectorShuffle(
8648 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8649 DL, MVT::v8i16, V1, V2),
8650 DAG.getUNDEF(MVT::v8i16), Mask);
8653 /// \brief Generic lowering of 8-lane i16 shuffles.
8655 /// This handles both single-input shuffles and combined shuffle/blends with
8656 /// two inputs. The single input shuffles are immediately delegated to
8657 /// a dedicated lowering routine.
8659 /// The blends are lowered in one of three fundamental ways. If there are few
8660 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8661 /// of the input is significantly cheaper when lowered as an interleaving of
8662 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8663 /// halves of the inputs separately (making them have relatively few inputs)
8664 /// and then concatenate them.
8665 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8666 const X86Subtarget *Subtarget,
8667 SelectionDAG &DAG) {
8669 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8670 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8671 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8672 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8673 ArrayRef<int> OrigMask = SVOp->getMask();
8674 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8675 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8676 MutableArrayRef<int> Mask(MaskStorage);
8678 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8680 // Whenever we can lower this as a zext, that instruction is strictly faster
8681 // than any alternative.
8682 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8683 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8686 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8687 auto isV2 = [](int M) { return M >= 8; };
8689 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8690 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8692 if (NumV2Inputs == 0)
8693 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8695 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8696 "to be V1-input shuffles.");
8698 // There are special ways we can lower some single-element blends.
8699 if (NumV2Inputs == 1)
8700 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8701 Mask, Subtarget, DAG))
8704 if (Subtarget->hasSSE41())
8706 lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8709 // Try to use rotation instructions if available.
8710 if (Subtarget->hasSSSE3())
8711 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8714 if (NumV1Inputs + NumV2Inputs <= 4)
8715 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8717 // Check whether an interleaving lowering is likely to be more efficient.
8718 // This isn't perfect but it is a strong heuristic that tends to work well on
8719 // the kinds of shuffles that show up in practice.
8721 // FIXME: Handle 1x, 2x, and 4x interleaving.
8722 if (shouldLowerAsInterleaving(Mask)) {
8723 // FIXME: Figure out whether we should pack these into the low or high
8726 int EMask[8], OMask[8];
8727 for (int i = 0; i < 4; ++i) {
8728 EMask[i] = Mask[2*i];
8729 OMask[i] = Mask[2*i + 1];
8734 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8735 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8737 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8740 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8741 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8743 for (int i = 0; i < 4; ++i) {
8744 LoBlendMask[i] = Mask[i];
8745 HiBlendMask[i] = Mask[i + 4];
8748 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8749 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8750 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8751 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8753 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8754 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8757 /// \brief Check whether a compaction lowering can be done by dropping even
8758 /// elements and compute how many times even elements must be dropped.
8760 /// This handles shuffles which take every Nth element where N is a power of
8761 /// two. Example shuffle masks:
8763 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8764 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8765 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8766 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8767 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8768 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8770 /// Any of these lanes can of course be undef.
8772 /// This routine only supports N <= 3.
8773 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8776 /// \returns N above, or the number of times even elements must be dropped if
8777 /// there is such a number. Otherwise returns zero.
8778 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8779 // Figure out whether we're looping over two inputs or just one.
8780 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8782 // The modulus for the shuffle vector entries is based on whether this is
8783 // a single input or not.
8784 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8785 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8786 "We should only be called with masks with a power-of-2 size!");
8788 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8790 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8791 // and 2^3 simultaneously. This is because we may have ambiguity with
8792 // partially undef inputs.
8793 bool ViableForN[3] = {true, true, true};
8795 for (int i = 0, e = Mask.size(); i < e; ++i) {
8796 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8801 bool IsAnyViable = false;
8802 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8803 if (ViableForN[j]) {
8806 // The shuffle mask must be equal to (i * 2^N) % M.
8807 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8810 ViableForN[j] = false;
8812 // Early exit if we exhaust the possible powers of two.
8817 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8821 // Return 0 as there is no viable power of two.
8825 /// \brief Generic lowering of v16i8 shuffles.
8827 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8828 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8829 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8830 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8832 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8833 const X86Subtarget *Subtarget,
8834 SelectionDAG &DAG) {
8836 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8837 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8838 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8840 ArrayRef<int> OrigMask = SVOp->getMask();
8841 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8843 // Try to use rotation instructions if available.
8844 if (Subtarget->hasSSSE3())
8845 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8849 // Try to use a zext lowering.
8850 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8851 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8854 int MaskStorage[16] = {
8855 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8856 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8857 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8858 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8859 MutableArrayRef<int> Mask(MaskStorage);
8860 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8861 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8864 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8866 // For single-input shuffles, there are some nicer lowering tricks we can use.
8867 if (NumV2Elements == 0) {
8868 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8869 // Notably, this handles splat and partial-splat shuffles more efficiently.
8870 // However, it only makes sense if the pre-duplication shuffle simplifies
8871 // things significantly. Currently, this means we need to be able to
8872 // express the pre-duplication shuffle as an i16 shuffle.
8874 // FIXME: We should check for other patterns which can be widened into an
8875 // i16 shuffle as well.
8876 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8877 for (int i = 0; i < 16; i += 2)
8878 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8883 auto tryToWidenViaDuplication = [&]() -> SDValue {
8884 if (!canWidenViaDuplication(Mask))
8886 SmallVector<int, 4> LoInputs;
8887 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8888 [](int M) { return M >= 0 && M < 8; });
8889 std::sort(LoInputs.begin(), LoInputs.end());
8890 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8892 SmallVector<int, 4> HiInputs;
8893 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8894 [](int M) { return M >= 8; });
8895 std::sort(HiInputs.begin(), HiInputs.end());
8896 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8899 bool TargetLo = LoInputs.size() >= HiInputs.size();
8900 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8901 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8903 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8904 SmallDenseMap<int, int, 8> LaneMap;
8905 for (int I : InPlaceInputs) {
8906 PreDupI16Shuffle[I/2] = I/2;
8909 int j = TargetLo ? 0 : 4, je = j + 4;
8910 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8911 // Check if j is already a shuffle of this input. This happens when
8912 // there are two adjacent bytes after we move the low one.
8913 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8914 // If we haven't yet mapped the input, search for a slot into which
8916 while (j < je && PreDupI16Shuffle[j] != -1)
8920 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8923 // Map this input with the i16 shuffle.
8924 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8927 // Update the lane map based on the mapping we ended up with.
8928 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8931 ISD::BITCAST, DL, MVT::v16i8,
8932 DAG.getVectorShuffle(MVT::v8i16, DL,
8933 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8934 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8936 // Unpack the bytes to form the i16s that will be shuffled into place.
8937 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8938 MVT::v16i8, V1, V1);
8940 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8941 for (int i = 0; i < 16; i += 2) {
8943 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8944 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8947 ISD::BITCAST, DL, MVT::v16i8,
8948 DAG.getVectorShuffle(MVT::v8i16, DL,
8949 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8950 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8952 if (SDValue V = tryToWidenViaDuplication())
8956 // Check whether an interleaving lowering is likely to be more efficient.
8957 // This isn't perfect but it is a strong heuristic that tends to work well on
8958 // the kinds of shuffles that show up in practice.
8960 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8961 if (shouldLowerAsInterleaving(Mask)) {
8962 // FIXME: Figure out whether we should pack these into the low or high
8965 int EMask[16], OMask[16];
8966 for (int i = 0; i < 8; ++i) {
8967 EMask[i] = Mask[2*i];
8968 OMask[i] = Mask[2*i + 1];
8973 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8974 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8976 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8979 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8980 // with PSHUFB. It is important to do this before we attempt to generate any
8981 // blends but after all of the single-input lowerings. If the single input
8982 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8983 // want to preserve that and we can DAG combine any longer sequences into
8984 // a PSHUFB in the end. But once we start blending from multiple inputs,
8985 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8986 // and there are *very* few patterns that would actually be faster than the
8987 // PSHUFB approach because of its ability to zero lanes.
8989 // FIXME: The only exceptions to the above are blends which are exact
8990 // interleavings with direct instructions supporting them. We currently don't
8991 // handle those well here.
8992 if (Subtarget->hasSSSE3()) {
8995 for (int i = 0; i < 16; ++i)
8996 if (Mask[i] == -1) {
8997 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8999 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9001 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9003 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9004 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9005 if (isSingleInputShuffleMask(Mask))
9006 return V1; // Single inputs are easy.
9008 // Otherwise, blend the two.
9009 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9010 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9011 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9014 // There are special ways we can lower some single-element blends.
9015 if (NumV2Elements == 1)
9016 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9017 Mask, Subtarget, DAG))
9020 // Check whether a compaction lowering can be done. This handles shuffles
9021 // which take every Nth element for some even N. See the helper function for
9024 // We special case these as they can be particularly efficiently handled with
9025 // the PACKUSB instruction on x86 and they show up in common patterns of
9026 // rearranging bytes to truncate wide elements.
9027 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9028 // NumEvenDrops is the power of two stride of the elements. Another way of
9029 // thinking about it is that we need to drop the even elements this many
9030 // times to get the original input.
9031 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9033 // First we need to zero all the dropped bytes.
9034 assert(NumEvenDrops <= 3 &&
9035 "No support for dropping even elements more than 3 times.");
9036 // We use the mask type to pick which bytes are preserved based on how many
9037 // elements are dropped.
9038 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9039 SDValue ByteClearMask =
9040 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9041 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9042 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9044 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9046 // Now pack things back together.
9047 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9048 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9049 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9050 for (int i = 1; i < NumEvenDrops; ++i) {
9051 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9052 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9058 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9059 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9060 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9061 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9063 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9064 MutableArrayRef<int> V1HalfBlendMask,
9065 MutableArrayRef<int> V2HalfBlendMask) {
9066 for (int i = 0; i < 8; ++i)
9067 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9068 V1HalfBlendMask[i] = HalfMask[i];
9070 } else if (HalfMask[i] >= 16) {
9071 V2HalfBlendMask[i] = HalfMask[i] - 16;
9072 HalfMask[i] = i + 8;
9075 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9076 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9078 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9080 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9081 MutableArrayRef<int> HiBlendMask) {
9083 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9084 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9086 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9087 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9088 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9089 [](int M) { return M >= 0 && M % 2 == 1; })) {
9090 // Use a mask to drop the high bytes.
9091 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9092 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9093 DAG.getConstant(0x00FF, MVT::v8i16));
9095 // This will be a single vector shuffle instead of a blend so nuke V2.
9096 V2 = DAG.getUNDEF(MVT::v8i16);
9098 // Squash the masks to point directly into V1.
9099 for (int &M : LoBlendMask)
9102 for (int &M : HiBlendMask)
9106 // Otherwise just unpack the low half of V into V1 and the high half into
9107 // V2 so that we can blend them as i16s.
9108 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9109 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9110 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9111 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9114 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9115 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9116 return std::make_pair(BlendedLo, BlendedHi);
9118 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9119 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9120 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9122 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9123 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9125 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9128 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9130 /// This routine breaks down the specific type of 128-bit shuffle and
9131 /// dispatches to the lowering routines accordingly.
9132 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9133 MVT VT, const X86Subtarget *Subtarget,
9134 SelectionDAG &DAG) {
9135 switch (VT.SimpleTy) {
9137 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9139 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9141 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9143 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9145 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9147 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9150 llvm_unreachable("Unimplemented!");
9154 /// \brief Test whether there are elements crossing 128-bit lanes in this
9157 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9158 /// and we routinely test for these.
9159 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9160 int LaneSize = 128 / VT.getScalarSizeInBits();
9161 int Size = Mask.size();
9162 for (int i = 0; i < Size; ++i)
9163 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9168 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
9170 /// This checks a shuffle mask to see if it is performing the same
9171 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
9172 /// that it is also not lane-crossing.
9173 static bool is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask) {
9174 int LaneSize = 128 / VT.getScalarSizeInBits();
9175 int Size = Mask.size();
9176 for (int i = LaneSize; i < Size; ++i)
9177 if (Mask[i] >= 0 && Mask[i] != (Mask[i % LaneSize] + (i / LaneSize) * LaneSize))
9182 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9185 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9186 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9187 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9188 /// we encode the logic here for specific shuffle lowering routines to bail to
9189 /// when they exhaust the features avaible to more directly handle the shuffle.
9190 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9192 const X86Subtarget *Subtarget,
9193 SelectionDAG &DAG) {
9195 MVT VT = Op.getSimpleValueType();
9196 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9197 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9198 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9200 ArrayRef<int> Mask = SVOp->getMask();
9202 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9203 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9205 int NumElements = VT.getVectorNumElements();
9206 int SplitNumElements = NumElements / 2;
9207 MVT ScalarVT = VT.getScalarType();
9208 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9210 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9211 DAG.getIntPtrConstant(0));
9212 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9213 DAG.getIntPtrConstant(SplitNumElements));
9214 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9215 DAG.getIntPtrConstant(0));
9216 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9217 DAG.getIntPtrConstant(SplitNumElements));
9219 // Now create two 4-way blends of these half-width vectors.
9220 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9221 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9222 for (int i = 0; i < SplitNumElements; ++i) {
9223 int M = HalfMask[i];
9224 if (M >= NumElements) {
9225 V2BlendMask.push_back(M - NumElements);
9226 V1BlendMask.push_back(-1);
9227 BlendMask.push_back(SplitNumElements + i);
9228 } else if (M >= 0) {
9229 V2BlendMask.push_back(-1);
9230 V1BlendMask.push_back(M);
9231 BlendMask.push_back(i);
9233 V2BlendMask.push_back(-1);
9234 V1BlendMask.push_back(-1);
9235 BlendMask.push_back(-1);
9238 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9239 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9240 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9242 SDValue Lo = HalfBlend(LoMask);
9243 SDValue Hi = HalfBlend(HiMask);
9244 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9247 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9249 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9250 /// isn't available.
9251 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9252 const X86Subtarget *Subtarget,
9253 SelectionDAG &DAG) {
9255 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9256 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9257 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9258 ArrayRef<int> Mask = SVOp->getMask();
9259 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9261 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9262 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9264 if (isSingleInputShuffleMask(Mask)) {
9265 // Non-half-crossing single input shuffles can be lowerid with an
9266 // interleaved permutation.
9267 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9268 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9269 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
9270 DAG.getConstant(VPERMILPMask, MVT::i8));
9273 // X86 has dedicated unpack instructions that can handle specific blend
9274 // operations: UNPCKH and UNPCKL.
9275 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9276 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9277 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9278 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9280 // If we have a single input to the zero element, insert that into V1 if we
9281 // can do so cheaply.
9283 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9284 if (NumV2Elements == 1 && Mask[0] >= 4)
9285 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9286 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9290 lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask, DAG))
9293 // Check if the blend happens to exactly fit that of SHUFPD.
9294 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9295 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9296 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9297 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9298 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9299 DAG.getConstant(SHUFPDMask, MVT::i8));
9301 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9302 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9303 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9304 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9305 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9306 DAG.getConstant(SHUFPDMask, MVT::i8));
9309 // Shuffle the input elements into the desired positions in V1 and V2 and
9310 // blend them together.
9311 int V1Mask[] = {-1, -1, -1, -1};
9312 int V2Mask[] = {-1, -1, -1, -1};
9313 for (int i = 0; i < 4; ++i)
9314 if (Mask[i] >= 0 && Mask[i] < 4)
9315 V1Mask[i] = Mask[i];
9316 else if (Mask[i] >= 4)
9317 V2Mask[i] = Mask[i] - 4;
9319 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9320 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9322 unsigned BlendMask = 0;
9323 for (int i = 0; i < 4; ++i)
9325 BlendMask |= 1 << i;
9327 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9328 DAG.getConstant(BlendMask, MVT::i8));
9331 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9333 /// This routine is only called when we have AVX2 and thus a reasonable
9334 /// instruction set for v4i64 shuffling..
9335 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9336 const X86Subtarget *Subtarget,
9337 SelectionDAG &DAG) {
9339 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9340 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9341 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9342 ArrayRef<int> Mask = SVOp->getMask();
9343 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9344 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9346 // FIXME: Actually implement this using AVX2!!!
9347 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9348 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9349 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9350 DAG.getVectorShuffle(MVT::v4f64, DL, V1, V2, Mask));
9353 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9355 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9356 /// isn't available.
9357 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9358 const X86Subtarget *Subtarget,
9359 SelectionDAG &DAG) {
9361 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9362 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9363 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9364 ArrayRef<int> Mask = SVOp->getMask();
9365 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9367 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9368 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9371 lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask, DAG))
9374 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9375 // options to efficiently lower the shuffle.
9376 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask)) {
9377 ArrayRef<int> LoMask = Mask.slice(0, 4);
9378 if (isSingleInputShuffleMask(Mask))
9379 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v8f32, V1,
9380 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9382 // Use dedicated unpack instructions for masks that match their pattern.
9383 if (isShuffleEquivalent(LoMask, 0, 8, 1, 9))
9384 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9385 if (isShuffleEquivalent(LoMask, 2, 10, 3, 11))
9386 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9388 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9389 // have already handled any direct blends.
9390 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9391 for (int &M : SHUFPSMask)
9394 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9397 // If we have a single input shuffle with different shuffle patterns in the
9398 // two 128-bit lanes, just do two shuffles and blend them together. This will
9399 // be faster than extracting the high 128-bit lane, shuffling it, and
9400 // re-inserting it. Especially on newer processors where blending is *the*
9401 // fastest operation.
9402 if (isSingleInputShuffleMask(Mask)) {
9403 int LoMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9404 int HiMask[4] = {Mask[4], Mask[5], Mask[6], Mask[7]};
9405 for (int &M : HiMask)
9408 SDValue Lo = V1, Hi = V1;
9409 if (!isNoopShuffleMask(LoMask))
9410 Lo = DAG.getNode(X86ISD::VPERMILP, DL, MVT::v8f32, Lo,
9411 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9412 if (!isNoopShuffleMask(HiMask))
9413 Hi = DAG.getNode(X86ISD::VPERMILP, DL, MVT::v8f32, Hi,
9414 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9415 unsigned BlendMask = 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7;
9416 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, Lo, Hi,
9417 DAG.getConstant(BlendMask, MVT::i8));
9420 // Shuffle the input elements into the desired positions in V1 and V2 and
9421 // blend them together.
9422 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9423 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9424 unsigned BlendMask = 0;
9425 for (int i = 0; i < 8; ++i)
9426 if (Mask[i] >= 0 && Mask[i] < 8) {
9427 V1Mask[i] = Mask[i];
9428 } else if (Mask[i] >= 8) {
9429 V2Mask[i] = Mask[i] - 8;
9430 BlendMask |= 1 << i;
9433 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9434 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9436 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9437 DAG.getConstant(BlendMask, MVT::i8));
9440 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9442 /// This routine is only called when we have AVX2 and thus a reasonable
9443 /// instruction set for v8i32 shuffling..
9444 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9445 const X86Subtarget *Subtarget,
9446 SelectionDAG &DAG) {
9448 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9449 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9450 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9451 ArrayRef<int> Mask = SVOp->getMask();
9452 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9453 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9455 // FIXME: Actually implement this using AVX2!!!
9456 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V1);
9457 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V2);
9458 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i32,
9459 DAG.getVectorShuffle(MVT::v8f32, DL, V1, V2, Mask));
9462 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9464 /// This routine is only called when we have AVX2 and thus a reasonable
9465 /// instruction set for v16i16 shuffling..
9466 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9467 const X86Subtarget *Subtarget,
9468 SelectionDAG &DAG) {
9470 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9471 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9472 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9473 ArrayRef<int> Mask = SVOp->getMask();
9474 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9475 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9477 // FIXME: Actually implement this using AVX2!!!
9479 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9482 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9484 /// This routine is only called when we have AVX2 and thus a reasonable
9485 /// instruction set for v32i8 shuffling..
9486 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9487 const X86Subtarget *Subtarget,
9488 SelectionDAG &DAG) {
9490 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9491 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9493 ArrayRef<int> Mask = SVOp->getMask();
9494 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9495 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9497 // FIXME: Actually implement this using AVX2!!!
9499 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9502 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9504 /// This routine either breaks down the specific type of a 256-bit x86 vector
9505 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9506 /// together based on the available instructions.
9507 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9508 MVT VT, const X86Subtarget *Subtarget,
9509 SelectionDAG &DAG) {
9511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9512 ArrayRef<int> Mask = SVOp->getMask();
9514 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9515 // check for those subtargets here and avoid much of the subtarget querying in
9516 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9517 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9518 // floating point types there eventually, just immediately cast everything to
9519 // a float and operate entirely in that domain.
9520 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9521 int ElementBits = VT.getScalarSizeInBits();
9522 if (ElementBits < 32)
9523 // No floating point type available, decompose into 128-bit vectors.
9524 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9526 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9527 VT.getVectorNumElements());
9528 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9529 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9530 return DAG.getNode(ISD::BITCAST, DL, VT,
9531 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9534 switch (VT.SimpleTy) {
9536 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9538 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9540 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9542 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9544 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9546 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9549 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9553 /// \brief Tiny helper function to test whether a shuffle mask could be
9554 /// simplified by widening the elements being shuffled.
9555 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9556 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9557 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9558 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9559 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9565 /// \brief Top-level lowering for x86 vector shuffles.
9567 /// This handles decomposition, canonicalization, and lowering of all x86
9568 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9569 /// above in helper routines. The canonicalization attempts to widen shuffles
9570 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9571 /// s.t. only one of the two inputs needs to be tested, etc.
9572 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9573 SelectionDAG &DAG) {
9574 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9575 ArrayRef<int> Mask = SVOp->getMask();
9576 SDValue V1 = Op.getOperand(0);
9577 SDValue V2 = Op.getOperand(1);
9578 MVT VT = Op.getSimpleValueType();
9579 int NumElements = VT.getVectorNumElements();
9582 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9584 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9585 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9586 if (V1IsUndef && V2IsUndef)
9587 return DAG.getUNDEF(VT);
9589 // When we create a shuffle node we put the UNDEF node to second operand,
9590 // but in some cases the first operand may be transformed to UNDEF.
9591 // In this case we should just commute the node.
9593 return DAG.getCommutedVectorShuffle(*SVOp);
9595 // Check for non-undef masks pointing at an undef vector and make the masks
9596 // undef as well. This makes it easier to match the shuffle based solely on
9600 if (M >= NumElements) {
9601 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9602 for (int &M : NewMask)
9603 if (M >= NumElements)
9605 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9608 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9609 // lanes but wider integers. We cap this to not form integers larger than i64
9610 // but it might be interesting to form i128 integers to handle flipping the
9611 // low and high halves of AVX 256-bit vectors.
9612 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9613 canWidenShuffleElements(Mask)) {
9614 SmallVector<int, 8> NewMask;
9615 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9616 NewMask.push_back(Mask[i] != -1
9618 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9620 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9621 VT.getVectorNumElements() / 2);
9622 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9623 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9624 return DAG.getNode(ISD::BITCAST, dl, VT,
9625 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9628 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9629 for (int M : SVOp->getMask())
9632 else if (M < NumElements)
9637 // Commute the shuffle as needed such that more elements come from V1 than
9638 // V2. This allows us to match the shuffle pattern strictly on how many
9639 // elements come from V1 without handling the symmetric cases.
9640 if (NumV2Elements > NumV1Elements)
9641 return DAG.getCommutedVectorShuffle(*SVOp);
9643 // When the number of V1 and V2 elements are the same, try to minimize the
9644 // number of uses of V2 in the low half of the vector. When that is tied,
9645 // ensure that the sum of indices for V1 is equal to or lower than the sum
9647 if (NumV1Elements == NumV2Elements) {
9648 int LowV1Elements = 0, LowV2Elements = 0;
9649 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9650 if (M >= NumElements)
9654 if (LowV2Elements > LowV1Elements)
9655 return DAG.getCommutedVectorShuffle(*SVOp);
9657 int SumV1Indices = 0, SumV2Indices = 0;
9658 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9659 if (SVOp->getMask()[i] >= NumElements)
9661 else if (SVOp->getMask()[i] >= 0)
9663 if (SumV2Indices < SumV1Indices)
9664 return DAG.getCommutedVectorShuffle(*SVOp);
9667 // For each vector width, delegate to a specialized lowering routine.
9668 if (VT.getSizeInBits() == 128)
9669 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9671 if (VT.getSizeInBits() == 256)
9672 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9674 llvm_unreachable("Unimplemented!");
9678 //===----------------------------------------------------------------------===//
9679 // Legacy vector shuffle lowering
9681 // This code is the legacy code handling vector shuffles until the above
9682 // replaces its functionality and performance.
9683 //===----------------------------------------------------------------------===//
9685 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9686 bool hasInt256, unsigned *MaskOut = nullptr) {
9687 MVT EltVT = VT.getVectorElementType();
9689 // There is no blend with immediate in AVX-512.
9690 if (VT.is512BitVector())
9693 if (!hasSSE41 || EltVT == MVT::i8)
9695 if (!hasInt256 && VT == MVT::v16i16)
9698 unsigned MaskValue = 0;
9699 unsigned NumElems = VT.getVectorNumElements();
9700 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9701 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9702 unsigned NumElemsInLane = NumElems / NumLanes;
9704 // Blend for v16i16 should be symetric for the both lanes.
9705 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9707 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9708 int EltIdx = MaskVals[i];
9710 if ((EltIdx < 0 || EltIdx == (int)i) &&
9711 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9714 if (((unsigned)EltIdx == (i + NumElems)) &&
9715 (SndLaneEltIdx < 0 ||
9716 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9717 MaskValue |= (1 << i);
9723 *MaskOut = MaskValue;
9727 // Try to lower a shuffle node into a simple blend instruction.
9728 // This function assumes isBlendMask returns true for this
9729 // SuffleVectorSDNode
9730 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9732 const X86Subtarget *Subtarget,
9733 SelectionDAG &DAG) {
9734 MVT VT = SVOp->getSimpleValueType(0);
9735 MVT EltVT = VT.getVectorElementType();
9736 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9737 Subtarget->hasInt256() && "Trying to lower a "
9738 "VECTOR_SHUFFLE to a Blend but "
9739 "with the wrong mask"));
9740 SDValue V1 = SVOp->getOperand(0);
9741 SDValue V2 = SVOp->getOperand(1);
9743 unsigned NumElems = VT.getVectorNumElements();
9745 // Convert i32 vectors to floating point if it is not AVX2.
9746 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9748 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9749 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9751 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9752 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9755 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9756 DAG.getConstant(MaskValue, MVT::i32));
9757 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9760 /// In vector type \p VT, return true if the element at index \p InputIdx
9761 /// falls on a different 128-bit lane than \p OutputIdx.
9762 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9763 unsigned OutputIdx) {
9764 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9765 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9768 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9769 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9770 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9771 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9773 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9774 SelectionDAG &DAG) {
9775 MVT VT = V1.getSimpleValueType();
9776 assert(VT.is128BitVector() || VT.is256BitVector());
9778 MVT EltVT = VT.getVectorElementType();
9779 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9780 unsigned NumElts = VT.getVectorNumElements();
9782 SmallVector<SDValue, 32> PshufbMask;
9783 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9784 int InputIdx = MaskVals[OutputIdx];
9785 unsigned InputByteIdx;
9787 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9788 InputByteIdx = 0x80;
9790 // Cross lane is not allowed.
9791 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9793 InputByteIdx = InputIdx * EltSizeInBytes;
9794 // Index is an byte offset within the 128-bit lane.
9795 InputByteIdx &= 0xf;
9798 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9799 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9800 if (InputByteIdx != 0x80)
9805 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9807 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9808 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9809 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9812 // v8i16 shuffles - Prefer shuffles in the following order:
9813 // 1. [all] pshuflw, pshufhw, optional move
9814 // 2. [ssse3] 1 x pshufb
9815 // 3. [ssse3] 2 x pshufb + 1 x por
9816 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9818 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9819 SelectionDAG &DAG) {
9820 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9821 SDValue V1 = SVOp->getOperand(0);
9822 SDValue V2 = SVOp->getOperand(1);
9824 SmallVector<int, 8> MaskVals;
9826 // Determine if more than 1 of the words in each of the low and high quadwords
9827 // of the result come from the same quadword of one of the two inputs. Undef
9828 // mask values count as coming from any quadword, for better codegen.
9830 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9831 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9832 unsigned LoQuad[] = { 0, 0, 0, 0 };
9833 unsigned HiQuad[] = { 0, 0, 0, 0 };
9834 // Indices of quads used.
9835 std::bitset<4> InputQuads;
9836 for (unsigned i = 0; i < 8; ++i) {
9837 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9838 int EltIdx = SVOp->getMaskElt(i);
9839 MaskVals.push_back(EltIdx);
9848 InputQuads.set(EltIdx / 4);
9851 int BestLoQuad = -1;
9852 unsigned MaxQuad = 1;
9853 for (unsigned i = 0; i < 4; ++i) {
9854 if (LoQuad[i] > MaxQuad) {
9856 MaxQuad = LoQuad[i];
9860 int BestHiQuad = -1;
9862 for (unsigned i = 0; i < 4; ++i) {
9863 if (HiQuad[i] > MaxQuad) {
9865 MaxQuad = HiQuad[i];
9869 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9870 // of the two input vectors, shuffle them into one input vector so only a
9871 // single pshufb instruction is necessary. If there are more than 2 input
9872 // quads, disable the next transformation since it does not help SSSE3.
9873 bool V1Used = InputQuads[0] || InputQuads[1];
9874 bool V2Used = InputQuads[2] || InputQuads[3];
9875 if (Subtarget->hasSSSE3()) {
9876 if (InputQuads.count() == 2 && V1Used && V2Used) {
9877 BestLoQuad = InputQuads[0] ? 0 : 1;
9878 BestHiQuad = InputQuads[2] ? 2 : 3;
9880 if (InputQuads.count() > 2) {
9886 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9887 // the shuffle mask. If a quad is scored as -1, that means that it contains
9888 // words from all 4 input quadwords.
9890 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9892 BestLoQuad < 0 ? 0 : BestLoQuad,
9893 BestHiQuad < 0 ? 1 : BestHiQuad
9895 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9896 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9897 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9898 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9900 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9901 // source words for the shuffle, to aid later transformations.
9902 bool AllWordsInNewV = true;
9903 bool InOrder[2] = { true, true };
9904 for (unsigned i = 0; i != 8; ++i) {
9905 int idx = MaskVals[i];
9907 InOrder[i/4] = false;
9908 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9910 AllWordsInNewV = false;
9914 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9915 if (AllWordsInNewV) {
9916 for (int i = 0; i != 8; ++i) {
9917 int idx = MaskVals[i];
9920 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9921 if ((idx != i) && idx < 4)
9923 if ((idx != i) && idx > 3)
9932 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9933 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9934 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9935 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9936 unsigned TargetMask = 0;
9937 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9938 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9939 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9940 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9941 getShufflePSHUFLWImmediate(SVOp);
9942 V1 = NewV.getOperand(0);
9943 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9947 // Promote splats to a larger type which usually leads to more efficient code.
9948 // FIXME: Is this true if pshufb is available?
9949 if (SVOp->isSplat())
9950 return PromoteSplat(SVOp, DAG);
9952 // If we have SSSE3, and all words of the result are from 1 input vector,
9953 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9954 // is present, fall back to case 4.
9955 if (Subtarget->hasSSSE3()) {
9956 SmallVector<SDValue,16> pshufbMask;
9958 // If we have elements from both input vectors, set the high bit of the
9959 // shuffle mask element to zero out elements that come from V2 in the V1
9960 // mask, and elements that come from V1 in the V2 mask, so that the two
9961 // results can be OR'd together.
9962 bool TwoInputs = V1Used && V2Used;
9963 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9965 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9967 // Calculate the shuffle mask for the second input, shuffle it, and
9968 // OR it with the first shuffled input.
9969 CommuteVectorShuffleMask(MaskVals, 8);
9970 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9971 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9972 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9975 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9976 // and update MaskVals with new element order.
9977 std::bitset<8> InOrder;
9978 if (BestLoQuad >= 0) {
9979 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9980 for (int i = 0; i != 4; ++i) {
9981 int idx = MaskVals[i];
9984 } else if ((idx / 4) == BestLoQuad) {
9989 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9992 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9993 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9994 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9996 getShufflePSHUFLWImmediate(SVOp), DAG);
10000 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10001 // and update MaskVals with the new element order.
10002 if (BestHiQuad >= 0) {
10003 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10004 for (unsigned i = 4; i != 8; ++i) {
10005 int idx = MaskVals[i];
10008 } else if ((idx / 4) == BestHiQuad) {
10009 MaskV[i] = (idx & 3) + 4;
10013 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10016 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10018 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10019 NewV.getOperand(0),
10020 getShufflePSHUFHWImmediate(SVOp), DAG);
10024 // In case BestHi & BestLo were both -1, which means each quadword has a word
10025 // from each of the four input quadwords, calculate the InOrder bitvector now
10026 // before falling through to the insert/extract cleanup.
10027 if (BestLoQuad == -1 && BestHiQuad == -1) {
10029 for (int i = 0; i != 8; ++i)
10030 if (MaskVals[i] < 0 || MaskVals[i] == i)
10034 // The other elements are put in the right place using pextrw and pinsrw.
10035 for (unsigned i = 0; i != 8; ++i) {
10038 int EltIdx = MaskVals[i];
10041 SDValue ExtOp = (EltIdx < 8) ?
10042 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10043 DAG.getIntPtrConstant(EltIdx)) :
10044 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10045 DAG.getIntPtrConstant(EltIdx - 8));
10046 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10047 DAG.getIntPtrConstant(i));
10052 /// \brief v16i16 shuffles
10054 /// FIXME: We only support generation of a single pshufb currently. We can
10055 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10056 /// well (e.g 2 x pshufb + 1 x por).
10058 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10059 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10060 SDValue V1 = SVOp->getOperand(0);
10061 SDValue V2 = SVOp->getOperand(1);
10064 if (V2.getOpcode() != ISD::UNDEF)
10067 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10068 return getPSHUFB(MaskVals, V1, dl, DAG);
10071 // v16i8 shuffles - Prefer shuffles in the following order:
10072 // 1. [ssse3] 1 x pshufb
10073 // 2. [ssse3] 2 x pshufb + 1 x por
10074 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10075 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10076 const X86Subtarget* Subtarget,
10077 SelectionDAG &DAG) {
10078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10079 SDValue V1 = SVOp->getOperand(0);
10080 SDValue V2 = SVOp->getOperand(1);
10082 ArrayRef<int> MaskVals = SVOp->getMask();
10084 // Promote splats to a larger type which usually leads to more efficient code.
10085 // FIXME: Is this true if pshufb is available?
10086 if (SVOp->isSplat())
10087 return PromoteSplat(SVOp, DAG);
10089 // If we have SSSE3, case 1 is generated when all result bytes come from
10090 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10091 // present, fall back to case 3.
10093 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10094 if (Subtarget->hasSSSE3()) {
10095 SmallVector<SDValue,16> pshufbMask;
10097 // If all result elements are from one input vector, then only translate
10098 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10100 // Otherwise, we have elements from both input vectors, and must zero out
10101 // elements that come from V2 in the first mask, and V1 in the second mask
10102 // so that we can OR them together.
10103 for (unsigned i = 0; i != 16; ++i) {
10104 int EltIdx = MaskVals[i];
10105 if (EltIdx < 0 || EltIdx >= 16)
10107 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10109 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10110 DAG.getNode(ISD::BUILD_VECTOR, dl,
10111 MVT::v16i8, pshufbMask));
10113 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10114 // the 2nd operand if it's undefined or zero.
10115 if (V2.getOpcode() == ISD::UNDEF ||
10116 ISD::isBuildVectorAllZeros(V2.getNode()))
10119 // Calculate the shuffle mask for the second input, shuffle it, and
10120 // OR it with the first shuffled input.
10121 pshufbMask.clear();
10122 for (unsigned i = 0; i != 16; ++i) {
10123 int EltIdx = MaskVals[i];
10124 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10125 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10127 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10128 DAG.getNode(ISD::BUILD_VECTOR, dl,
10129 MVT::v16i8, pshufbMask));
10130 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10133 // No SSSE3 - Calculate in place words and then fix all out of place words
10134 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10135 // the 16 different words that comprise the two doublequadword input vectors.
10136 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10137 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10139 for (int i = 0; i != 8; ++i) {
10140 int Elt0 = MaskVals[i*2];
10141 int Elt1 = MaskVals[i*2+1];
10143 // This word of the result is all undef, skip it.
10144 if (Elt0 < 0 && Elt1 < 0)
10147 // This word of the result is already in the correct place, skip it.
10148 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10151 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10152 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10155 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10156 // using a single extract together, load it and store it.
10157 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10158 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10159 DAG.getIntPtrConstant(Elt1 / 2));
10160 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10161 DAG.getIntPtrConstant(i));
10165 // If Elt1 is defined, extract it from the appropriate source. If the
10166 // source byte is not also odd, shift the extracted word left 8 bits
10167 // otherwise clear the bottom 8 bits if we need to do an or.
10169 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10170 DAG.getIntPtrConstant(Elt1 / 2));
10171 if ((Elt1 & 1) == 0)
10172 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10174 TLI.getShiftAmountTy(InsElt.getValueType())));
10175 else if (Elt0 >= 0)
10176 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10177 DAG.getConstant(0xFF00, MVT::i16));
10179 // If Elt0 is defined, extract it from the appropriate source. If the
10180 // source byte is not also even, shift the extracted word right 8 bits. If
10181 // Elt1 was also defined, OR the extracted values together before
10182 // inserting them in the result.
10184 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10185 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10186 if ((Elt0 & 1) != 0)
10187 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10189 TLI.getShiftAmountTy(InsElt0.getValueType())));
10190 else if (Elt1 >= 0)
10191 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10192 DAG.getConstant(0x00FF, MVT::i16));
10193 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10196 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10197 DAG.getIntPtrConstant(i));
10199 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10202 // v32i8 shuffles - Translate to VPSHUFB if possible.
10204 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10205 const X86Subtarget *Subtarget,
10206 SelectionDAG &DAG) {
10207 MVT VT = SVOp->getSimpleValueType(0);
10208 SDValue V1 = SVOp->getOperand(0);
10209 SDValue V2 = SVOp->getOperand(1);
10211 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10213 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10214 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10215 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10217 // VPSHUFB may be generated if
10218 // (1) one of input vector is undefined or zeroinitializer.
10219 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10220 // And (2) the mask indexes don't cross the 128-bit lane.
10221 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10222 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10225 if (V1IsAllZero && !V2IsAllZero) {
10226 CommuteVectorShuffleMask(MaskVals, 32);
10229 return getPSHUFB(MaskVals, V1, dl, DAG);
10232 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10233 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10234 /// done when every pair / quad of shuffle mask elements point to elements in
10235 /// the right sequence. e.g.
10236 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10238 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10239 SelectionDAG &DAG) {
10240 MVT VT = SVOp->getSimpleValueType(0);
10242 unsigned NumElems = VT.getVectorNumElements();
10245 switch (VT.SimpleTy) {
10246 default: llvm_unreachable("Unexpected!");
10249 return SDValue(SVOp, 0);
10250 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10251 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10252 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10253 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10254 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10255 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10258 SmallVector<int, 8> MaskVec;
10259 for (unsigned i = 0; i != NumElems; i += Scale) {
10261 for (unsigned j = 0; j != Scale; ++j) {
10262 int EltIdx = SVOp->getMaskElt(i+j);
10266 StartIdx = (EltIdx / Scale);
10267 if (EltIdx != (int)(StartIdx*Scale + j))
10270 MaskVec.push_back(StartIdx);
10273 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10274 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10275 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10278 /// getVZextMovL - Return a zero-extending vector move low node.
10280 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10281 SDValue SrcOp, SelectionDAG &DAG,
10282 const X86Subtarget *Subtarget, SDLoc dl) {
10283 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10284 LoadSDNode *LD = nullptr;
10285 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10286 LD = dyn_cast<LoadSDNode>(SrcOp);
10288 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10290 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10291 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10292 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10293 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10294 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10296 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10297 return DAG.getNode(ISD::BITCAST, dl, VT,
10298 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10299 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10301 SrcOp.getOperand(0)
10307 return DAG.getNode(ISD::BITCAST, dl, VT,
10308 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10309 DAG.getNode(ISD::BITCAST, dl,
10313 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10314 /// which could not be matched by any known target speficic shuffle
10316 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10318 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10319 if (NewOp.getNode())
10322 MVT VT = SVOp->getSimpleValueType(0);
10324 unsigned NumElems = VT.getVectorNumElements();
10325 unsigned NumLaneElems = NumElems / 2;
10328 MVT EltVT = VT.getVectorElementType();
10329 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10332 SmallVector<int, 16> Mask;
10333 for (unsigned l = 0; l < 2; ++l) {
10334 // Build a shuffle mask for the output, discovering on the fly which
10335 // input vectors to use as shuffle operands (recorded in InputUsed).
10336 // If building a suitable shuffle vector proves too hard, then bail
10337 // out with UseBuildVector set.
10338 bool UseBuildVector = false;
10339 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10340 unsigned LaneStart = l * NumLaneElems;
10341 for (unsigned i = 0; i != NumLaneElems; ++i) {
10342 // The mask element. This indexes into the input.
10343 int Idx = SVOp->getMaskElt(i+LaneStart);
10345 // the mask element does not index into any input vector.
10346 Mask.push_back(-1);
10350 // The input vector this mask element indexes into.
10351 int Input = Idx / NumLaneElems;
10353 // Turn the index into an offset from the start of the input vector.
10354 Idx -= Input * NumLaneElems;
10356 // Find or create a shuffle vector operand to hold this input.
10358 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10359 if (InputUsed[OpNo] == Input)
10360 // This input vector is already an operand.
10362 if (InputUsed[OpNo] < 0) {
10363 // Create a new operand for this input vector.
10364 InputUsed[OpNo] = Input;
10369 if (OpNo >= array_lengthof(InputUsed)) {
10370 // More than two input vectors used! Give up on trying to create a
10371 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10372 UseBuildVector = true;
10376 // Add the mask index for the new shuffle vector.
10377 Mask.push_back(Idx + OpNo * NumLaneElems);
10380 if (UseBuildVector) {
10381 SmallVector<SDValue, 16> SVOps;
10382 for (unsigned i = 0; i != NumLaneElems; ++i) {
10383 // The mask element. This indexes into the input.
10384 int Idx = SVOp->getMaskElt(i+LaneStart);
10386 SVOps.push_back(DAG.getUNDEF(EltVT));
10390 // The input vector this mask element indexes into.
10391 int Input = Idx / NumElems;
10393 // Turn the index into an offset from the start of the input vector.
10394 Idx -= Input * NumElems;
10396 // Extract the vector element by hand.
10397 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10398 SVOp->getOperand(Input),
10399 DAG.getIntPtrConstant(Idx)));
10402 // Construct the output using a BUILD_VECTOR.
10403 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10404 } else if (InputUsed[0] < 0) {
10405 // No input vectors were used! The result is undefined.
10406 Output[l] = DAG.getUNDEF(NVT);
10408 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10409 (InputUsed[0] % 2) * NumLaneElems,
10411 // If only one input was used, use an undefined vector for the other.
10412 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10413 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10414 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10415 // At least one input vector was used. Create a new shuffle vector.
10416 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10422 // Concatenate the result back
10423 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10426 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10427 /// 4 elements, and match them with several different shuffle types.
10429 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10430 SDValue V1 = SVOp->getOperand(0);
10431 SDValue V2 = SVOp->getOperand(1);
10433 MVT VT = SVOp->getSimpleValueType(0);
10435 assert(VT.is128BitVector() && "Unsupported vector size");
10437 std::pair<int, int> Locs[4];
10438 int Mask1[] = { -1, -1, -1, -1 };
10439 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10441 unsigned NumHi = 0;
10442 unsigned NumLo = 0;
10443 for (unsigned i = 0; i != 4; ++i) {
10444 int Idx = PermMask[i];
10446 Locs[i] = std::make_pair(-1, -1);
10448 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10450 Locs[i] = std::make_pair(0, NumLo);
10451 Mask1[NumLo] = Idx;
10454 Locs[i] = std::make_pair(1, NumHi);
10456 Mask1[2+NumHi] = Idx;
10462 if (NumLo <= 2 && NumHi <= 2) {
10463 // If no more than two elements come from either vector. This can be
10464 // implemented with two shuffles. First shuffle gather the elements.
10465 // The second shuffle, which takes the first shuffle as both of its
10466 // vector operands, put the elements into the right order.
10467 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10469 int Mask2[] = { -1, -1, -1, -1 };
10471 for (unsigned i = 0; i != 4; ++i)
10472 if (Locs[i].first != -1) {
10473 unsigned Idx = (i < 2) ? 0 : 4;
10474 Idx += Locs[i].first * 2 + Locs[i].second;
10478 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10481 if (NumLo == 3 || NumHi == 3) {
10482 // Otherwise, we must have three elements from one vector, call it X, and
10483 // one element from the other, call it Y. First, use a shufps to build an
10484 // intermediate vector with the one element from Y and the element from X
10485 // that will be in the same half in the final destination (the indexes don't
10486 // matter). Then, use a shufps to build the final vector, taking the half
10487 // containing the element from Y from the intermediate, and the other half
10490 // Normalize it so the 3 elements come from V1.
10491 CommuteVectorShuffleMask(PermMask, 4);
10495 // Find the element from V2.
10497 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10498 int Val = PermMask[HiIndex];
10505 Mask1[0] = PermMask[HiIndex];
10507 Mask1[2] = PermMask[HiIndex^1];
10509 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10511 if (HiIndex >= 2) {
10512 Mask1[0] = PermMask[0];
10513 Mask1[1] = PermMask[1];
10514 Mask1[2] = HiIndex & 1 ? 6 : 4;
10515 Mask1[3] = HiIndex & 1 ? 4 : 6;
10516 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10519 Mask1[0] = HiIndex & 1 ? 2 : 0;
10520 Mask1[1] = HiIndex & 1 ? 0 : 2;
10521 Mask1[2] = PermMask[2];
10522 Mask1[3] = PermMask[3];
10527 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10530 // Break it into (shuffle shuffle_hi, shuffle_lo).
10531 int LoMask[] = { -1, -1, -1, -1 };
10532 int HiMask[] = { -1, -1, -1, -1 };
10534 int *MaskPtr = LoMask;
10535 unsigned MaskIdx = 0;
10536 unsigned LoIdx = 0;
10537 unsigned HiIdx = 2;
10538 for (unsigned i = 0; i != 4; ++i) {
10545 int Idx = PermMask[i];
10547 Locs[i] = std::make_pair(-1, -1);
10548 } else if (Idx < 4) {
10549 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10550 MaskPtr[LoIdx] = Idx;
10553 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10554 MaskPtr[HiIdx] = Idx;
10559 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10560 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10561 int MaskOps[] = { -1, -1, -1, -1 };
10562 for (unsigned i = 0; i != 4; ++i)
10563 if (Locs[i].first != -1)
10564 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10565 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10568 static bool MayFoldVectorLoad(SDValue V) {
10569 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10570 V = V.getOperand(0);
10572 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10573 V = V.getOperand(0);
10574 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10575 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10576 // BUILD_VECTOR (load), undef
10577 V = V.getOperand(0);
10579 return MayFoldLoad(V);
10583 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10584 MVT VT = Op.getSimpleValueType();
10586 // Canonizalize to v2f64.
10587 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10588 return DAG.getNode(ISD::BITCAST, dl, VT,
10589 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10594 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10596 SDValue V1 = Op.getOperand(0);
10597 SDValue V2 = Op.getOperand(1);
10598 MVT VT = Op.getSimpleValueType();
10600 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10602 if (HasSSE2 && VT == MVT::v2f64)
10603 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10605 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10606 return DAG.getNode(ISD::BITCAST, dl, VT,
10607 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10608 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10609 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10613 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10614 SDValue V1 = Op.getOperand(0);
10615 SDValue V2 = Op.getOperand(1);
10616 MVT VT = Op.getSimpleValueType();
10618 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10619 "unsupported shuffle type");
10621 if (V2.getOpcode() == ISD::UNDEF)
10625 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10629 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10630 SDValue V1 = Op.getOperand(0);
10631 SDValue V2 = Op.getOperand(1);
10632 MVT VT = Op.getSimpleValueType();
10633 unsigned NumElems = VT.getVectorNumElements();
10635 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10636 // operand of these instructions is only memory, so check if there's a
10637 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10639 bool CanFoldLoad = false;
10641 // Trivial case, when V2 comes from a load.
10642 if (MayFoldVectorLoad(V2))
10643 CanFoldLoad = true;
10645 // When V1 is a load, it can be folded later into a store in isel, example:
10646 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10648 // (MOVLPSmr addr:$src1, VR128:$src2)
10649 // So, recognize this potential and also use MOVLPS or MOVLPD
10650 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10651 CanFoldLoad = true;
10653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10655 if (HasSSE2 && NumElems == 2)
10656 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10659 // If we don't care about the second element, proceed to use movss.
10660 if (SVOp->getMaskElt(1) != -1)
10661 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10664 // movl and movlp will both match v2i64, but v2i64 is never matched by
10665 // movl earlier because we make it strict to avoid messing with the movlp load
10666 // folding logic (see the code above getMOVLP call). Match it here then,
10667 // this is horrible, but will stay like this until we move all shuffle
10668 // matching to x86 specific nodes. Note that for the 1st condition all
10669 // types are matched with movsd.
10671 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10672 // as to remove this logic from here, as much as possible
10673 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10674 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10675 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10678 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10680 // Invert the operand order and use SHUFPS to match it.
10681 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10682 getShuffleSHUFImmediate(SVOp), DAG);
10685 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10686 SelectionDAG &DAG) {
10688 MVT VT = Load->getSimpleValueType(0);
10689 MVT EVT = VT.getVectorElementType();
10690 SDValue Addr = Load->getOperand(1);
10691 SDValue NewAddr = DAG.getNode(
10692 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10693 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10696 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10697 DAG.getMachineFunction().getMachineMemOperand(
10698 Load->getMemOperand(), 0, EVT.getStoreSize()));
10702 // It is only safe to call this function if isINSERTPSMask is true for
10703 // this shufflevector mask.
10704 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10705 SelectionDAG &DAG) {
10706 // Generate an insertps instruction when inserting an f32 from memory onto a
10707 // v4f32 or when copying a member from one v4f32 to another.
10708 // We also use it for transferring i32 from one register to another,
10709 // since it simply copies the same bits.
10710 // If we're transferring an i32 from memory to a specific element in a
10711 // register, we output a generic DAG that will match the PINSRD
10713 MVT VT = SVOp->getSimpleValueType(0);
10714 MVT EVT = VT.getVectorElementType();
10715 SDValue V1 = SVOp->getOperand(0);
10716 SDValue V2 = SVOp->getOperand(1);
10717 auto Mask = SVOp->getMask();
10718 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10719 "unsupported vector type for insertps/pinsrd");
10721 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10722 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10723 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10727 unsigned DestIndex;
10731 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10734 // If we have 1 element from each vector, we have to check if we're
10735 // changing V1's element's place. If so, we're done. Otherwise, we
10736 // should assume we're changing V2's element's place and behave
10738 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10739 assert(DestIndex <= INT32_MAX && "truncated destination index");
10740 if (FromV1 == FromV2 &&
10741 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10745 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10748 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10749 "More than one element from V1 and from V2, or no elements from one "
10750 "of the vectors. This case should not have returned true from "
10755 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10758 // Get an index into the source vector in the range [0,4) (the mask is
10759 // in the range [0,8) because it can address V1 and V2)
10760 unsigned SrcIndex = Mask[DestIndex] % 4;
10761 if (MayFoldLoad(From)) {
10762 // Trivial case, when From comes from a load and is only used by the
10763 // shuffle. Make it use insertps from the vector that we need from that
10766 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10767 if (!NewLoad.getNode())
10770 if (EVT == MVT::f32) {
10771 // Create this as a scalar to vector to match the instruction pattern.
10772 SDValue LoadScalarToVector =
10773 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10774 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10775 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10777 } else { // EVT == MVT::i32
10778 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10779 // instruction, to match the PINSRD instruction, which loads an i32 to a
10780 // certain vector element.
10781 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10782 DAG.getConstant(DestIndex, MVT::i32));
10786 // Vector-element-to-vector
10787 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10788 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10791 // Reduce a vector shuffle to zext.
10792 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10793 SelectionDAG &DAG) {
10794 // PMOVZX is only available from SSE41.
10795 if (!Subtarget->hasSSE41())
10798 MVT VT = Op.getSimpleValueType();
10800 // Only AVX2 support 256-bit vector integer extending.
10801 if (!Subtarget->hasInt256() && VT.is256BitVector())
10804 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10806 SDValue V1 = Op.getOperand(0);
10807 SDValue V2 = Op.getOperand(1);
10808 unsigned NumElems = VT.getVectorNumElements();
10810 // Extending is an unary operation and the element type of the source vector
10811 // won't be equal to or larger than i64.
10812 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10813 VT.getVectorElementType() == MVT::i64)
10816 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10817 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10818 while ((1U << Shift) < NumElems) {
10819 if (SVOp->getMaskElt(1U << Shift) == 1)
10822 // The maximal ratio is 8, i.e. from i8 to i64.
10827 // Check the shuffle mask.
10828 unsigned Mask = (1U << Shift) - 1;
10829 for (unsigned i = 0; i != NumElems; ++i) {
10830 int EltIdx = SVOp->getMaskElt(i);
10831 if ((i & Mask) != 0 && EltIdx != -1)
10833 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10837 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10838 MVT NeVT = MVT::getIntegerVT(NBits);
10839 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10841 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10844 // Simplify the operand as it's prepared to be fed into shuffle.
10845 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10846 if (V1.getOpcode() == ISD::BITCAST &&
10847 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10848 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10849 V1.getOperand(0).getOperand(0)
10850 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10851 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10852 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10853 ConstantSDNode *CIdx =
10854 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10855 // If it's foldable, i.e. normal load with single use, we will let code
10856 // selection to fold it. Otherwise, we will short the conversion sequence.
10857 if (CIdx && CIdx->getZExtValue() == 0 &&
10858 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10859 MVT FullVT = V.getSimpleValueType();
10860 MVT V1VT = V1.getSimpleValueType();
10861 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10862 // The "ext_vec_elt" node is wider than the result node.
10863 // In this case we should extract subvector from V.
10864 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10865 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10866 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10867 FullVT.getVectorNumElements()/Ratio);
10868 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10869 DAG.getIntPtrConstant(0));
10871 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10875 return DAG.getNode(ISD::BITCAST, DL, VT,
10876 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10879 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10880 SelectionDAG &DAG) {
10881 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10882 MVT VT = Op.getSimpleValueType();
10884 SDValue V1 = Op.getOperand(0);
10885 SDValue V2 = Op.getOperand(1);
10887 if (isZeroShuffle(SVOp))
10888 return getZeroVector(VT, Subtarget, DAG, dl);
10890 // Handle splat operations
10891 if (SVOp->isSplat()) {
10892 // Use vbroadcast whenever the splat comes from a foldable load
10893 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10894 if (Broadcast.getNode())
10898 // Check integer expanding shuffles.
10899 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10900 if (NewOp.getNode())
10903 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10905 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10906 VT == MVT::v32i8) {
10907 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10908 if (NewOp.getNode())
10909 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10910 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10911 // FIXME: Figure out a cleaner way to do this.
10912 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10913 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10914 if (NewOp.getNode()) {
10915 MVT NewVT = NewOp.getSimpleValueType();
10916 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10917 NewVT, true, false))
10918 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10921 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10922 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10923 if (NewOp.getNode()) {
10924 MVT NewVT = NewOp.getSimpleValueType();
10925 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10926 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10935 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10936 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10937 SDValue V1 = Op.getOperand(0);
10938 SDValue V2 = Op.getOperand(1);
10939 MVT VT = Op.getSimpleValueType();
10941 unsigned NumElems = VT.getVectorNumElements();
10942 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10943 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10944 bool V1IsSplat = false;
10945 bool V2IsSplat = false;
10946 bool HasSSE2 = Subtarget->hasSSE2();
10947 bool HasFp256 = Subtarget->hasFp256();
10948 bool HasInt256 = Subtarget->hasInt256();
10949 MachineFunction &MF = DAG.getMachineFunction();
10950 bool OptForSize = MF.getFunction()->getAttributes().
10951 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10953 // Check if we should use the experimental vector shuffle lowering. If so,
10954 // delegate completely to that code path.
10955 if (ExperimentalVectorShuffleLowering)
10956 return lowerVectorShuffle(Op, Subtarget, DAG);
10958 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10960 if (V1IsUndef && V2IsUndef)
10961 return DAG.getUNDEF(VT);
10963 // When we create a shuffle node we put the UNDEF node to second operand,
10964 // but in some cases the first operand may be transformed to UNDEF.
10965 // In this case we should just commute the node.
10967 return DAG.getCommutedVectorShuffle(*SVOp);
10969 // Vector shuffle lowering takes 3 steps:
10971 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10972 // narrowing and commutation of operands should be handled.
10973 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10975 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10976 // so the shuffle can be broken into other shuffles and the legalizer can
10977 // try the lowering again.
10979 // The general idea is that no vector_shuffle operation should be left to
10980 // be matched during isel, all of them must be converted to a target specific
10983 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10984 // narrowing and commutation of operands should be handled. The actual code
10985 // doesn't include all of those, work in progress...
10986 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10987 if (NewOp.getNode())
10990 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10992 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10993 // unpckh_undef). Only use pshufd if speed is more important than size.
10994 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10995 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10996 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10997 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10999 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11000 V2IsUndef && MayFoldVectorLoad(V1))
11001 return getMOVDDup(Op, dl, V1, DAG);
11003 if (isMOVHLPS_v_undef_Mask(M, VT))
11004 return getMOVHighToLow(Op, dl, DAG);
11006 // Use to match splats
11007 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11008 (VT == MVT::v2f64 || VT == MVT::v2i64))
11009 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11011 if (isPSHUFDMask(M, VT)) {
11012 // The actual implementation will match the mask in the if above and then
11013 // during isel it can match several different instructions, not only pshufd
11014 // as its name says, sad but true, emulate the behavior for now...
11015 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11016 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11018 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11020 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11021 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11023 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11024 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
11027 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11031 if (isPALIGNRMask(M, VT, Subtarget))
11032 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11033 getShufflePALIGNRImmediate(SVOp),
11036 if (isVALIGNMask(M, VT, Subtarget))
11037 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11038 getShuffleVALIGNImmediate(SVOp),
11041 // Check if this can be converted into a logical shift.
11042 bool isLeft = false;
11043 unsigned ShAmt = 0;
11045 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11046 if (isShift && ShVal.hasOneUse()) {
11047 // If the shifted value has multiple uses, it may be cheaper to use
11048 // v_set0 + movlhps or movhlps, etc.
11049 MVT EltVT = VT.getVectorElementType();
11050 ShAmt *= EltVT.getSizeInBits();
11051 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11054 if (isMOVLMask(M, VT)) {
11055 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11056 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11057 if (!isMOVLPMask(M, VT)) {
11058 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11059 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11061 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11062 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11066 // FIXME: fold these into legal mask.
11067 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11068 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11070 if (isMOVHLPSMask(M, VT))
11071 return getMOVHighToLow(Op, dl, DAG);
11073 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11074 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11076 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11077 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11079 if (isMOVLPMask(M, VT))
11080 return getMOVLP(Op, dl, DAG, HasSSE2);
11082 if (ShouldXformToMOVHLPS(M, VT) ||
11083 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11084 return DAG.getCommutedVectorShuffle(*SVOp);
11087 // No better options. Use a vshldq / vsrldq.
11088 MVT EltVT = VT.getVectorElementType();
11089 ShAmt *= EltVT.getSizeInBits();
11090 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11093 bool Commuted = false;
11094 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11095 // 1,1,1,1 -> v8i16 though.
11096 BitVector UndefElements;
11097 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11098 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11100 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11101 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11104 // Canonicalize the splat or undef, if present, to be on the RHS.
11105 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11106 CommuteVectorShuffleMask(M, NumElems);
11108 std::swap(V1IsSplat, V2IsSplat);
11112 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11113 // Shuffling low element of v1 into undef, just return v1.
11116 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11117 // the instruction selector will not match, so get a canonical MOVL with
11118 // swapped operands to undo the commute.
11119 return getMOVL(DAG, dl, VT, V2, V1);
11122 if (isUNPCKLMask(M, VT, HasInt256))
11123 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11125 if (isUNPCKHMask(M, VT, HasInt256))
11126 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11129 // Normalize mask so all entries that point to V2 points to its first
11130 // element then try to match unpck{h|l} again. If match, return a
11131 // new vector_shuffle with the corrected mask.p
11132 SmallVector<int, 8> NewMask(M.begin(), M.end());
11133 NormalizeMask(NewMask, NumElems);
11134 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11135 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11136 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11137 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11141 // Commute is back and try unpck* again.
11142 // FIXME: this seems wrong.
11143 CommuteVectorShuffleMask(M, NumElems);
11145 std::swap(V1IsSplat, V2IsSplat);
11147 if (isUNPCKLMask(M, VT, HasInt256))
11148 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11150 if (isUNPCKHMask(M, VT, HasInt256))
11151 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11154 // Normalize the node to match x86 shuffle ops if needed
11155 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11156 return DAG.getCommutedVectorShuffle(*SVOp);
11158 // The checks below are all present in isShuffleMaskLegal, but they are
11159 // inlined here right now to enable us to directly emit target specific
11160 // nodes, and remove one by one until they don't return Op anymore.
11162 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11163 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11164 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11165 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11168 if (isPSHUFHWMask(M, VT, HasInt256))
11169 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11170 getShufflePSHUFHWImmediate(SVOp),
11173 if (isPSHUFLWMask(M, VT, HasInt256))
11174 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11175 getShufflePSHUFLWImmediate(SVOp),
11178 unsigned MaskValue;
11179 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11181 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11183 if (isSHUFPMask(M, VT))
11184 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11185 getShuffleSHUFImmediate(SVOp), DAG);
11187 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11188 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11189 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11190 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11192 //===--------------------------------------------------------------------===//
11193 // Generate target specific nodes for 128 or 256-bit shuffles only
11194 // supported in the AVX instruction set.
11197 // Handle VMOVDDUPY permutations
11198 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11199 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11201 // Handle VPERMILPS/D* permutations
11202 if (isVPERMILPMask(M, VT)) {
11203 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11204 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11205 getShuffleSHUFImmediate(SVOp), DAG);
11206 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
11207 getShuffleSHUFImmediate(SVOp), DAG);
11211 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11212 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11213 Idx*(NumElems/2), DAG, dl);
11215 // Handle VPERM2F128/VPERM2I128 permutations
11216 if (isVPERM2X128Mask(M, VT, HasFp256))
11217 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11218 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11220 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11221 return getINSERTPS(SVOp, dl, DAG);
11224 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11225 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11227 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11228 VT.is512BitVector()) {
11229 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11230 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11231 SmallVector<SDValue, 16> permclMask;
11232 for (unsigned i = 0; i != NumElems; ++i) {
11233 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11236 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11238 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11239 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11240 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11241 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11242 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11245 //===--------------------------------------------------------------------===//
11246 // Since no target specific shuffle was selected for this generic one,
11247 // lower it into other known shuffles. FIXME: this isn't true yet, but
11248 // this is the plan.
11251 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11252 if (VT == MVT::v8i16) {
11253 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11254 if (NewOp.getNode())
11258 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11259 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11260 if (NewOp.getNode())
11264 if (VT == MVT::v16i8) {
11265 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11266 if (NewOp.getNode())
11270 if (VT == MVT::v32i8) {
11271 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11272 if (NewOp.getNode())
11276 // Handle all 128-bit wide vectors with 4 elements, and match them with
11277 // several different shuffle types.
11278 if (NumElems == 4 && VT.is128BitVector())
11279 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11281 // Handle general 256-bit shuffles
11282 if (VT.is256BitVector())
11283 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11288 // This function assumes its argument is a BUILD_VECTOR of constants or
11289 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11291 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11292 unsigned &MaskValue) {
11294 unsigned NumElems = BuildVector->getNumOperands();
11295 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11296 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11297 unsigned NumElemsInLane = NumElems / NumLanes;
11299 // Blend for v16i16 should be symetric for the both lanes.
11300 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11301 SDValue EltCond = BuildVector->getOperand(i);
11302 SDValue SndLaneEltCond =
11303 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11305 int Lane1Cond = -1, Lane2Cond = -1;
11306 if (isa<ConstantSDNode>(EltCond))
11307 Lane1Cond = !isZero(EltCond);
11308 if (isa<ConstantSDNode>(SndLaneEltCond))
11309 Lane2Cond = !isZero(SndLaneEltCond);
11311 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11312 // Lane1Cond != 0, means we want the first argument.
11313 // Lane1Cond == 0, means we want the second argument.
11314 // The encoding of this argument is 0 for the first argument, 1
11315 // for the second. Therefore, invert the condition.
11316 MaskValue |= !Lane1Cond << i;
11317 else if (Lane1Cond < 0)
11318 MaskValue |= !Lane2Cond << i;
11325 // Try to lower a vselect node into a simple blend instruction.
11326 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11327 SelectionDAG &DAG) {
11328 SDValue Cond = Op.getOperand(0);
11329 SDValue LHS = Op.getOperand(1);
11330 SDValue RHS = Op.getOperand(2);
11332 MVT VT = Op.getSimpleValueType();
11333 MVT EltVT = VT.getVectorElementType();
11334 unsigned NumElems = VT.getVectorNumElements();
11336 // There is no blend with immediate in AVX-512.
11337 if (VT.is512BitVector())
11340 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11342 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11345 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11348 // Check the mask for BLEND and build the value.
11349 unsigned MaskValue = 0;
11350 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11353 // Convert i32 vectors to floating point if it is not AVX2.
11354 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11356 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11357 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11359 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11360 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11363 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11364 DAG.getConstant(MaskValue, MVT::i32));
11365 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11368 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11369 // A vselect where all conditions and data are constants can be optimized into
11370 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11371 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11372 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11373 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11376 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11377 if (BlendOp.getNode())
11380 // Some types for vselect were previously set to Expand, not Legal or
11381 // Custom. Return an empty SDValue so we fall-through to Expand, after
11382 // the Custom lowering phase.
11383 MVT VT = Op.getSimpleValueType();
11384 switch (VT.SimpleTy) {
11389 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11394 // We couldn't create a "Blend with immediate" node.
11395 // This node should still be legal, but we'll have to emit a blendv*
11400 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11401 MVT VT = Op.getSimpleValueType();
11404 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11407 if (VT.getSizeInBits() == 8) {
11408 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11409 Op.getOperand(0), Op.getOperand(1));
11410 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11411 DAG.getValueType(VT));
11412 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11415 if (VT.getSizeInBits() == 16) {
11416 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11417 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11419 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11420 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11421 DAG.getNode(ISD::BITCAST, dl,
11424 Op.getOperand(1)));
11425 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11426 Op.getOperand(0), Op.getOperand(1));
11427 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11428 DAG.getValueType(VT));
11429 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11432 if (VT == MVT::f32) {
11433 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11434 // the result back to FR32 register. It's only worth matching if the
11435 // result has a single use which is a store or a bitcast to i32. And in
11436 // the case of a store, it's not worth it if the index is a constant 0,
11437 // because a MOVSSmr can be used instead, which is smaller and faster.
11438 if (!Op.hasOneUse())
11440 SDNode *User = *Op.getNode()->use_begin();
11441 if ((User->getOpcode() != ISD::STORE ||
11442 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11443 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11444 (User->getOpcode() != ISD::BITCAST ||
11445 User->getValueType(0) != MVT::i32))
11447 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11448 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11451 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11454 if (VT == MVT::i32 || VT == MVT::i64) {
11455 // ExtractPS/pextrq works with constant index.
11456 if (isa<ConstantSDNode>(Op.getOperand(1)))
11462 /// Extract one bit from mask vector, like v16i1 or v8i1.
11463 /// AVX-512 feature.
11465 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11466 SDValue Vec = Op.getOperand(0);
11468 MVT VecVT = Vec.getSimpleValueType();
11469 SDValue Idx = Op.getOperand(1);
11470 MVT EltVT = Op.getSimpleValueType();
11472 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11474 // variable index can't be handled in mask registers,
11475 // extend vector to VR512
11476 if (!isa<ConstantSDNode>(Idx)) {
11477 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11478 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11479 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11480 ExtVT.getVectorElementType(), Ext, Idx);
11481 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11484 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11485 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11486 unsigned MaxSift = rc->getSize()*8 - 1;
11487 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11488 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11489 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11490 DAG.getConstant(MaxSift, MVT::i8));
11491 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11492 DAG.getIntPtrConstant(0));
11496 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11497 SelectionDAG &DAG) const {
11499 SDValue Vec = Op.getOperand(0);
11500 MVT VecVT = Vec.getSimpleValueType();
11501 SDValue Idx = Op.getOperand(1);
11503 if (Op.getSimpleValueType() == MVT::i1)
11504 return ExtractBitFromMaskVector(Op, DAG);
11506 if (!isa<ConstantSDNode>(Idx)) {
11507 if (VecVT.is512BitVector() ||
11508 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11509 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11512 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11513 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11514 MaskEltVT.getSizeInBits());
11516 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11517 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11518 getZeroVector(MaskVT, Subtarget, DAG, dl),
11519 Idx, DAG.getConstant(0, getPointerTy()));
11520 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11521 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11522 Perm, DAG.getConstant(0, getPointerTy()));
11527 // If this is a 256-bit vector result, first extract the 128-bit vector and
11528 // then extract the element from the 128-bit vector.
11529 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11531 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11532 // Get the 128-bit vector.
11533 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11534 MVT EltVT = VecVT.getVectorElementType();
11536 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11538 //if (IdxVal >= NumElems/2)
11539 // IdxVal -= NumElems/2;
11540 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11541 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11542 DAG.getConstant(IdxVal, MVT::i32));
11545 assert(VecVT.is128BitVector() && "Unexpected vector length");
11547 if (Subtarget->hasSSE41()) {
11548 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11553 MVT VT = Op.getSimpleValueType();
11554 // TODO: handle v16i8.
11555 if (VT.getSizeInBits() == 16) {
11556 SDValue Vec = Op.getOperand(0);
11557 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11559 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11560 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11561 DAG.getNode(ISD::BITCAST, dl,
11563 Op.getOperand(1)));
11564 // Transform it so it match pextrw which produces a 32-bit result.
11565 MVT EltVT = MVT::i32;
11566 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11567 Op.getOperand(0), Op.getOperand(1));
11568 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11569 DAG.getValueType(VT));
11570 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11573 if (VT.getSizeInBits() == 32) {
11574 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11578 // SHUFPS the element to the lowest double word, then movss.
11579 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11580 MVT VVT = Op.getOperand(0).getSimpleValueType();
11581 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11582 DAG.getUNDEF(VVT), Mask);
11583 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11584 DAG.getIntPtrConstant(0));
11587 if (VT.getSizeInBits() == 64) {
11588 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11589 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11590 // to match extract_elt for f64.
11591 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11595 // UNPCKHPD the element to the lowest double word, then movsd.
11596 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11597 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11598 int Mask[2] = { 1, -1 };
11599 MVT VVT = Op.getOperand(0).getSimpleValueType();
11600 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11601 DAG.getUNDEF(VVT), Mask);
11602 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11603 DAG.getIntPtrConstant(0));
11609 /// Insert one bit to mask vector, like v16i1 or v8i1.
11610 /// AVX-512 feature.
11612 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11614 SDValue Vec = Op.getOperand(0);
11615 SDValue Elt = Op.getOperand(1);
11616 SDValue Idx = Op.getOperand(2);
11617 MVT VecVT = Vec.getSimpleValueType();
11619 if (!isa<ConstantSDNode>(Idx)) {
11620 // Non constant index. Extend source and destination,
11621 // insert element and then truncate the result.
11622 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11623 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11624 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11625 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11626 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11627 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11630 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11631 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11632 if (Vec.getOpcode() == ISD::UNDEF)
11633 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11634 DAG.getConstant(IdxVal, MVT::i8));
11635 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11636 unsigned MaxSift = rc->getSize()*8 - 1;
11637 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11638 DAG.getConstant(MaxSift, MVT::i8));
11639 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11640 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11641 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11644 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11645 SelectionDAG &DAG) const {
11646 MVT VT = Op.getSimpleValueType();
11647 MVT EltVT = VT.getVectorElementType();
11649 if (EltVT == MVT::i1)
11650 return InsertBitToMaskVector(Op, DAG);
11653 SDValue N0 = Op.getOperand(0);
11654 SDValue N1 = Op.getOperand(1);
11655 SDValue N2 = Op.getOperand(2);
11656 if (!isa<ConstantSDNode>(N2))
11658 auto *N2C = cast<ConstantSDNode>(N2);
11659 unsigned IdxVal = N2C->getZExtValue();
11661 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11662 // into that, and then insert the subvector back into the result.
11663 if (VT.is256BitVector() || VT.is512BitVector()) {
11664 // Get the desired 128-bit vector half.
11665 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11667 // Insert the element into the desired half.
11668 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11669 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11671 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11672 DAG.getConstant(IdxIn128, MVT::i32));
11674 // Insert the changed part back to the 256-bit vector
11675 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11677 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11679 if (Subtarget->hasSSE41()) {
11680 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11682 if (VT == MVT::v8i16) {
11683 Opc = X86ISD::PINSRW;
11685 assert(VT == MVT::v16i8);
11686 Opc = X86ISD::PINSRB;
11689 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11691 if (N1.getValueType() != MVT::i32)
11692 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11693 if (N2.getValueType() != MVT::i32)
11694 N2 = DAG.getIntPtrConstant(IdxVal);
11695 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11698 if (EltVT == MVT::f32) {
11699 // Bits [7:6] of the constant are the source select. This will always be
11700 // zero here. The DAG Combiner may combine an extract_elt index into
11702 // bits. For example (insert (extract, 3), 2) could be matched by
11704 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11705 // Bits [5:4] of the constant are the destination select. This is the
11706 // value of the incoming immediate.
11707 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11708 // combine either bitwise AND or insert of float 0.0 to set these bits.
11709 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11710 // Create this as a scalar to vector..
11711 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11712 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11715 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11716 // PINSR* works with constant index.
11721 if (EltVT == MVT::i8)
11724 if (EltVT.getSizeInBits() == 16) {
11725 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11726 // as its second argument.
11727 if (N1.getValueType() != MVT::i32)
11728 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11729 if (N2.getValueType() != MVT::i32)
11730 N2 = DAG.getIntPtrConstant(IdxVal);
11731 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11736 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11738 MVT OpVT = Op.getSimpleValueType();
11740 // If this is a 256-bit vector result, first insert into a 128-bit
11741 // vector and then insert into the 256-bit vector.
11742 if (!OpVT.is128BitVector()) {
11743 // Insert into a 128-bit vector.
11744 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11745 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11746 OpVT.getVectorNumElements() / SizeFactor);
11748 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11750 // Insert the 128-bit vector.
11751 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11754 if (OpVT == MVT::v1i64 &&
11755 Op.getOperand(0).getValueType() == MVT::i64)
11756 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11758 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11759 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11760 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11761 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11764 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11765 // a simple subregister reference or explicit instructions to grab
11766 // upper bits of a vector.
11767 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11768 SelectionDAG &DAG) {
11770 SDValue In = Op.getOperand(0);
11771 SDValue Idx = Op.getOperand(1);
11772 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11773 MVT ResVT = Op.getSimpleValueType();
11774 MVT InVT = In.getSimpleValueType();
11776 if (Subtarget->hasFp256()) {
11777 if (ResVT.is128BitVector() &&
11778 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11779 isa<ConstantSDNode>(Idx)) {
11780 return Extract128BitVector(In, IdxVal, DAG, dl);
11782 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11783 isa<ConstantSDNode>(Idx)) {
11784 return Extract256BitVector(In, IdxVal, DAG, dl);
11790 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11791 // simple superregister reference or explicit instructions to insert
11792 // the upper bits of a vector.
11793 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11794 SelectionDAG &DAG) {
11795 if (Subtarget->hasFp256()) {
11796 SDLoc dl(Op.getNode());
11797 SDValue Vec = Op.getNode()->getOperand(0);
11798 SDValue SubVec = Op.getNode()->getOperand(1);
11799 SDValue Idx = Op.getNode()->getOperand(2);
11801 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11802 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11803 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11804 isa<ConstantSDNode>(Idx)) {
11805 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11806 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11809 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11810 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11811 isa<ConstantSDNode>(Idx)) {
11812 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11813 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11819 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11820 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11821 // one of the above mentioned nodes. It has to be wrapped because otherwise
11822 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11823 // be used to form addressing mode. These wrapped nodes will be selected
11826 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11827 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11829 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11830 // global base reg.
11831 unsigned char OpFlag = 0;
11832 unsigned WrapperKind = X86ISD::Wrapper;
11833 CodeModel::Model M = DAG.getTarget().getCodeModel();
11835 if (Subtarget->isPICStyleRIPRel() &&
11836 (M == CodeModel::Small || M == CodeModel::Kernel))
11837 WrapperKind = X86ISD::WrapperRIP;
11838 else if (Subtarget->isPICStyleGOT())
11839 OpFlag = X86II::MO_GOTOFF;
11840 else if (Subtarget->isPICStyleStubPIC())
11841 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11843 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11844 CP->getAlignment(),
11845 CP->getOffset(), OpFlag);
11847 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11848 // With PIC, the address is actually $g + Offset.
11850 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11851 DAG.getNode(X86ISD::GlobalBaseReg,
11852 SDLoc(), getPointerTy()),
11859 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11860 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11862 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11863 // global base reg.
11864 unsigned char OpFlag = 0;
11865 unsigned WrapperKind = X86ISD::Wrapper;
11866 CodeModel::Model M = DAG.getTarget().getCodeModel();
11868 if (Subtarget->isPICStyleRIPRel() &&
11869 (M == CodeModel::Small || M == CodeModel::Kernel))
11870 WrapperKind = X86ISD::WrapperRIP;
11871 else if (Subtarget->isPICStyleGOT())
11872 OpFlag = X86II::MO_GOTOFF;
11873 else if (Subtarget->isPICStyleStubPIC())
11874 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11876 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11879 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11881 // With PIC, the address is actually $g + Offset.
11883 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11884 DAG.getNode(X86ISD::GlobalBaseReg,
11885 SDLoc(), getPointerTy()),
11892 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11893 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11895 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11896 // global base reg.
11897 unsigned char OpFlag = 0;
11898 unsigned WrapperKind = X86ISD::Wrapper;
11899 CodeModel::Model M = DAG.getTarget().getCodeModel();
11901 if (Subtarget->isPICStyleRIPRel() &&
11902 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11903 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11904 OpFlag = X86II::MO_GOTPCREL;
11905 WrapperKind = X86ISD::WrapperRIP;
11906 } else if (Subtarget->isPICStyleGOT()) {
11907 OpFlag = X86II::MO_GOT;
11908 } else if (Subtarget->isPICStyleStubPIC()) {
11909 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11910 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11911 OpFlag = X86II::MO_DARWIN_NONLAZY;
11914 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11917 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11919 // With PIC, the address is actually $g + Offset.
11920 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11921 !Subtarget->is64Bit()) {
11922 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11923 DAG.getNode(X86ISD::GlobalBaseReg,
11924 SDLoc(), getPointerTy()),
11928 // For symbols that require a load from a stub to get the address, emit the
11930 if (isGlobalStubReference(OpFlag))
11931 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11932 MachinePointerInfo::getGOT(), false, false, false, 0);
11938 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11939 // Create the TargetBlockAddressAddress node.
11940 unsigned char OpFlags =
11941 Subtarget->ClassifyBlockAddressReference();
11942 CodeModel::Model M = DAG.getTarget().getCodeModel();
11943 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11944 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11946 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11949 if (Subtarget->isPICStyleRIPRel() &&
11950 (M == CodeModel::Small || M == CodeModel::Kernel))
11951 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11953 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11955 // With PIC, the address is actually $g + Offset.
11956 if (isGlobalRelativeToPICBase(OpFlags)) {
11957 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11958 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11966 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11967 int64_t Offset, SelectionDAG &DAG) const {
11968 // Create the TargetGlobalAddress node, folding in the constant
11969 // offset if it is legal.
11970 unsigned char OpFlags =
11971 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11972 CodeModel::Model M = DAG.getTarget().getCodeModel();
11974 if (OpFlags == X86II::MO_NO_FLAG &&
11975 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11976 // A direct static reference to a global.
11977 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11980 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11983 if (Subtarget->isPICStyleRIPRel() &&
11984 (M == CodeModel::Small || M == CodeModel::Kernel))
11985 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11987 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11989 // With PIC, the address is actually $g + Offset.
11990 if (isGlobalRelativeToPICBase(OpFlags)) {
11991 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11992 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11996 // For globals that require a load from a stub to get the address, emit the
11998 if (isGlobalStubReference(OpFlags))
11999 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12000 MachinePointerInfo::getGOT(), false, false, false, 0);
12002 // If there was a non-zero offset that we didn't fold, create an explicit
12003 // addition for it.
12005 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12006 DAG.getConstant(Offset, getPointerTy()));
12012 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12013 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12014 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12015 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12019 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12020 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12021 unsigned char OperandFlags, bool LocalDynamic = false) {
12022 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12023 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12025 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12026 GA->getValueType(0),
12030 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12034 SDValue Ops[] = { Chain, TGA, *InFlag };
12035 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12037 SDValue Ops[] = { Chain, TGA };
12038 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12041 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12042 MFI->setAdjustsStack(true);
12044 SDValue Flag = Chain.getValue(1);
12045 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12048 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12050 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12053 SDLoc dl(GA); // ? function entry point might be better
12054 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12055 DAG.getNode(X86ISD::GlobalBaseReg,
12056 SDLoc(), PtrVT), InFlag);
12057 InFlag = Chain.getValue(1);
12059 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12062 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12064 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12066 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12067 X86::RAX, X86II::MO_TLSGD);
12070 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12076 // Get the start address of the TLS block for this module.
12077 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12078 .getInfo<X86MachineFunctionInfo>();
12079 MFI->incNumLocalDynamicTLSAccesses();
12083 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12084 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12087 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12088 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12089 InFlag = Chain.getValue(1);
12090 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12091 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12094 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12098 unsigned char OperandFlags = X86II::MO_DTPOFF;
12099 unsigned WrapperKind = X86ISD::Wrapper;
12100 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12101 GA->getValueType(0),
12102 GA->getOffset(), OperandFlags);
12103 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12105 // Add x@dtpoff with the base.
12106 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12109 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12110 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12111 const EVT PtrVT, TLSModel::Model model,
12112 bool is64Bit, bool isPIC) {
12115 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12116 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12117 is64Bit ? 257 : 256));
12119 SDValue ThreadPointer =
12120 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12121 MachinePointerInfo(Ptr), false, false, false, 0);
12123 unsigned char OperandFlags = 0;
12124 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12126 unsigned WrapperKind = X86ISD::Wrapper;
12127 if (model == TLSModel::LocalExec) {
12128 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12129 } else if (model == TLSModel::InitialExec) {
12131 OperandFlags = X86II::MO_GOTTPOFF;
12132 WrapperKind = X86ISD::WrapperRIP;
12134 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12137 llvm_unreachable("Unexpected model");
12140 // emit "addl x@ntpoff,%eax" (local exec)
12141 // or "addl x@indntpoff,%eax" (initial exec)
12142 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12144 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12145 GA->getOffset(), OperandFlags);
12146 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12148 if (model == TLSModel::InitialExec) {
12149 if (isPIC && !is64Bit) {
12150 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12151 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12155 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12156 MachinePointerInfo::getGOT(), false, false, false, 0);
12159 // The address of the thread local variable is the add of the thread
12160 // pointer with the offset of the variable.
12161 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12165 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12167 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12168 const GlobalValue *GV = GA->getGlobal();
12170 if (Subtarget->isTargetELF()) {
12171 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12174 case TLSModel::GeneralDynamic:
12175 if (Subtarget->is64Bit())
12176 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12177 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12178 case TLSModel::LocalDynamic:
12179 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12180 Subtarget->is64Bit());
12181 case TLSModel::InitialExec:
12182 case TLSModel::LocalExec:
12183 return LowerToTLSExecModel(
12184 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12185 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12187 llvm_unreachable("Unknown TLS model.");
12190 if (Subtarget->isTargetDarwin()) {
12191 // Darwin only has one model of TLS. Lower to that.
12192 unsigned char OpFlag = 0;
12193 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12194 X86ISD::WrapperRIP : X86ISD::Wrapper;
12196 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12197 // global base reg.
12198 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12199 !Subtarget->is64Bit();
12201 OpFlag = X86II::MO_TLVP_PIC_BASE;
12203 OpFlag = X86II::MO_TLVP;
12205 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12206 GA->getValueType(0),
12207 GA->getOffset(), OpFlag);
12208 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12210 // With PIC32, the address is actually $g + Offset.
12212 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12213 DAG.getNode(X86ISD::GlobalBaseReg,
12214 SDLoc(), getPointerTy()),
12217 // Lowering the machine isd will make sure everything is in the right
12219 SDValue Chain = DAG.getEntryNode();
12220 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12221 SDValue Args[] = { Chain, Offset };
12222 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12224 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12225 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12226 MFI->setAdjustsStack(true);
12228 // And our return value (tls address) is in the standard call return value
12230 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12231 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12232 Chain.getValue(1));
12235 if (Subtarget->isTargetKnownWindowsMSVC() ||
12236 Subtarget->isTargetWindowsGNU()) {
12237 // Just use the implicit TLS architecture
12238 // Need to generate someting similar to:
12239 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12241 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12242 // mov rcx, qword [rdx+rcx*8]
12243 // mov eax, .tls$:tlsvar
12244 // [rax+rcx] contains the address
12245 // Windows 64bit: gs:0x58
12246 // Windows 32bit: fs:__tls_array
12249 SDValue Chain = DAG.getEntryNode();
12251 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12252 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12253 // use its literal value of 0x2C.
12254 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12255 ? Type::getInt8PtrTy(*DAG.getContext(),
12257 : Type::getInt32PtrTy(*DAG.getContext(),
12261 Subtarget->is64Bit()
12262 ? DAG.getIntPtrConstant(0x58)
12263 : (Subtarget->isTargetWindowsGNU()
12264 ? DAG.getIntPtrConstant(0x2C)
12265 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12267 SDValue ThreadPointer =
12268 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12269 MachinePointerInfo(Ptr), false, false, false, 0);
12271 // Load the _tls_index variable
12272 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12273 if (Subtarget->is64Bit())
12274 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12275 IDX, MachinePointerInfo(), MVT::i32,
12276 false, false, false, 0);
12278 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12279 false, false, false, 0);
12281 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12283 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12285 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12286 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12287 false, false, false, 0);
12289 // Get the offset of start of .tls section
12290 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12291 GA->getValueType(0),
12292 GA->getOffset(), X86II::MO_SECREL);
12293 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12295 // The address of the thread local variable is the add of the thread
12296 // pointer with the offset of the variable.
12297 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12300 llvm_unreachable("TLS not implemented for this target.");
12303 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12304 /// and take a 2 x i32 value to shift plus a shift amount.
12305 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12306 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12307 MVT VT = Op.getSimpleValueType();
12308 unsigned VTBits = VT.getSizeInBits();
12310 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12311 SDValue ShOpLo = Op.getOperand(0);
12312 SDValue ShOpHi = Op.getOperand(1);
12313 SDValue ShAmt = Op.getOperand(2);
12314 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12315 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12317 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12318 DAG.getConstant(VTBits - 1, MVT::i8));
12319 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12320 DAG.getConstant(VTBits - 1, MVT::i8))
12321 : DAG.getConstant(0, VT);
12323 SDValue Tmp2, Tmp3;
12324 if (Op.getOpcode() == ISD::SHL_PARTS) {
12325 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12326 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12328 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12329 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12332 // If the shift amount is larger or equal than the width of a part we can't
12333 // rely on the results of shld/shrd. Insert a test and select the appropriate
12334 // values for large shift amounts.
12335 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12336 DAG.getConstant(VTBits, MVT::i8));
12337 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12338 AndNode, DAG.getConstant(0, MVT::i8));
12341 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12342 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12343 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12345 if (Op.getOpcode() == ISD::SHL_PARTS) {
12346 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12347 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12349 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12350 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12353 SDValue Ops[2] = { Lo, Hi };
12354 return DAG.getMergeValues(Ops, dl);
12357 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12358 SelectionDAG &DAG) const {
12359 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12361 if (SrcVT.isVector())
12364 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12365 "Unknown SINT_TO_FP to lower!");
12367 // These are really Legal; return the operand so the caller accepts it as
12369 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12371 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12372 Subtarget->is64Bit()) {
12377 unsigned Size = SrcVT.getSizeInBits()/8;
12378 MachineFunction &MF = DAG.getMachineFunction();
12379 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12380 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12381 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12383 MachinePointerInfo::getFixedStack(SSFI),
12385 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12388 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12390 SelectionDAG &DAG) const {
12394 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12396 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12398 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12400 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12402 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12403 MachineMemOperand *MMO;
12405 int SSFI = FI->getIndex();
12407 DAG.getMachineFunction()
12408 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12409 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12411 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12412 StackSlot = StackSlot.getOperand(1);
12414 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12415 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12417 Tys, Ops, SrcVT, MMO);
12420 Chain = Result.getValue(1);
12421 SDValue InFlag = Result.getValue(2);
12423 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12424 // shouldn't be necessary except that RFP cannot be live across
12425 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12426 MachineFunction &MF = DAG.getMachineFunction();
12427 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12428 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12429 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12430 Tys = DAG.getVTList(MVT::Other);
12432 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12434 MachineMemOperand *MMO =
12435 DAG.getMachineFunction()
12436 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12437 MachineMemOperand::MOStore, SSFISize, SSFISize);
12439 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12440 Ops, Op.getValueType(), MMO);
12441 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12442 MachinePointerInfo::getFixedStack(SSFI),
12443 false, false, false, 0);
12449 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12450 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12451 SelectionDAG &DAG) const {
12452 // This algorithm is not obvious. Here it is what we're trying to output:
12455 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12456 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12458 haddpd %xmm0, %xmm0
12460 pshufd $0x4e, %xmm0, %xmm1
12466 LLVMContext *Context = DAG.getContext();
12468 // Build some magic constants.
12469 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12470 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12471 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12473 SmallVector<Constant*,2> CV1;
12475 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12476 APInt(64, 0x4330000000000000ULL))));
12478 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12479 APInt(64, 0x4530000000000000ULL))));
12480 Constant *C1 = ConstantVector::get(CV1);
12481 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12483 // Load the 64-bit value into an XMM register.
12484 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12486 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12487 MachinePointerInfo::getConstantPool(),
12488 false, false, false, 16);
12489 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12490 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12493 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12494 MachinePointerInfo::getConstantPool(),
12495 false, false, false, 16);
12496 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12497 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12500 if (Subtarget->hasSSE3()) {
12501 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12502 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12504 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12505 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12507 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12508 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12512 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12513 DAG.getIntPtrConstant(0));
12516 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12517 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12518 SelectionDAG &DAG) const {
12520 // FP constant to bias correct the final result.
12521 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12524 // Load the 32-bit value into an XMM register.
12525 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12528 // Zero out the upper parts of the register.
12529 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12531 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12532 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12533 DAG.getIntPtrConstant(0));
12535 // Or the load with the bias.
12536 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12537 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12538 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12539 MVT::v2f64, Load)),
12540 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12541 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12542 MVT::v2f64, Bias)));
12543 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12544 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12545 DAG.getIntPtrConstant(0));
12547 // Subtract the bias.
12548 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12550 // Handle final rounding.
12551 EVT DestVT = Op.getValueType();
12553 if (DestVT.bitsLT(MVT::f64))
12554 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12555 DAG.getIntPtrConstant(0));
12556 if (DestVT.bitsGT(MVT::f64))
12557 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12559 // Handle final rounding.
12563 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12564 SelectionDAG &DAG) const {
12565 SDValue N0 = Op.getOperand(0);
12566 MVT SVT = N0.getSimpleValueType();
12569 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12570 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12571 "Custom UINT_TO_FP is not supported!");
12573 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12574 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12575 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12578 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12579 SelectionDAG &DAG) const {
12580 SDValue N0 = Op.getOperand(0);
12583 if (Op.getValueType().isVector())
12584 return lowerUINT_TO_FP_vec(Op, DAG);
12586 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12587 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12588 // the optimization here.
12589 if (DAG.SignBitIsZero(N0))
12590 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12592 MVT SrcVT = N0.getSimpleValueType();
12593 MVT DstVT = Op.getSimpleValueType();
12594 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12595 return LowerUINT_TO_FP_i64(Op, DAG);
12596 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12597 return LowerUINT_TO_FP_i32(Op, DAG);
12598 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12601 // Make a 64-bit buffer, and use it to build an FILD.
12602 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12603 if (SrcVT == MVT::i32) {
12604 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12605 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12606 getPointerTy(), StackSlot, WordOff);
12607 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12608 StackSlot, MachinePointerInfo(),
12610 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12611 OffsetSlot, MachinePointerInfo(),
12613 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12617 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12618 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12619 StackSlot, MachinePointerInfo(),
12621 // For i64 source, we need to add the appropriate power of 2 if the input
12622 // was negative. This is the same as the optimization in
12623 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12624 // we must be careful to do the computation in x87 extended precision, not
12625 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12626 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12627 MachineMemOperand *MMO =
12628 DAG.getMachineFunction()
12629 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12630 MachineMemOperand::MOLoad, 8, 8);
12632 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12633 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12634 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12637 APInt FF(32, 0x5F800000ULL);
12639 // Check whether the sign bit is set.
12640 SDValue SignSet = DAG.getSetCC(dl,
12641 getSetCCResultType(*DAG.getContext(), MVT::i64),
12642 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12645 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12646 SDValue FudgePtr = DAG.getConstantPool(
12647 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12650 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12651 SDValue Zero = DAG.getIntPtrConstant(0);
12652 SDValue Four = DAG.getIntPtrConstant(4);
12653 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12655 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12657 // Load the value out, extending it from f32 to f80.
12658 // FIXME: Avoid the extend by constructing the right constant pool?
12659 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12660 FudgePtr, MachinePointerInfo::getConstantPool(),
12661 MVT::f32, false, false, false, 4);
12662 // Extend everything to 80 bits to force it to be done on x87.
12663 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12664 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12667 std::pair<SDValue,SDValue>
12668 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12669 bool IsSigned, bool IsReplace) const {
12672 EVT DstTy = Op.getValueType();
12674 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12675 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12679 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12680 DstTy.getSimpleVT() >= MVT::i16 &&
12681 "Unknown FP_TO_INT to lower!");
12683 // These are really Legal.
12684 if (DstTy == MVT::i32 &&
12685 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12686 return std::make_pair(SDValue(), SDValue());
12687 if (Subtarget->is64Bit() &&
12688 DstTy == MVT::i64 &&
12689 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12690 return std::make_pair(SDValue(), SDValue());
12692 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12693 // stack slot, or into the FTOL runtime function.
12694 MachineFunction &MF = DAG.getMachineFunction();
12695 unsigned MemSize = DstTy.getSizeInBits()/8;
12696 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12697 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12700 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12701 Opc = X86ISD::WIN_FTOL;
12703 switch (DstTy.getSimpleVT().SimpleTy) {
12704 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12705 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12706 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12707 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12710 SDValue Chain = DAG.getEntryNode();
12711 SDValue Value = Op.getOperand(0);
12712 EVT TheVT = Op.getOperand(0).getValueType();
12713 // FIXME This causes a redundant load/store if the SSE-class value is already
12714 // in memory, such as if it is on the callstack.
12715 if (isScalarFPTypeInSSEReg(TheVT)) {
12716 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12717 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12718 MachinePointerInfo::getFixedStack(SSFI),
12720 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12722 Chain, StackSlot, DAG.getValueType(TheVT)
12725 MachineMemOperand *MMO =
12726 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12727 MachineMemOperand::MOLoad, MemSize, MemSize);
12728 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12729 Chain = Value.getValue(1);
12730 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12731 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12734 MachineMemOperand *MMO =
12735 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12736 MachineMemOperand::MOStore, MemSize, MemSize);
12738 if (Opc != X86ISD::WIN_FTOL) {
12739 // Build the FP_TO_INT*_IN_MEM
12740 SDValue Ops[] = { Chain, Value, StackSlot };
12741 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12743 return std::make_pair(FIST, StackSlot);
12745 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12746 DAG.getVTList(MVT::Other, MVT::Glue),
12748 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12749 MVT::i32, ftol.getValue(1));
12750 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12751 MVT::i32, eax.getValue(2));
12752 SDValue Ops[] = { eax, edx };
12753 SDValue pair = IsReplace
12754 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12755 : DAG.getMergeValues(Ops, DL);
12756 return std::make_pair(pair, SDValue());
12760 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12761 const X86Subtarget *Subtarget) {
12762 MVT VT = Op->getSimpleValueType(0);
12763 SDValue In = Op->getOperand(0);
12764 MVT InVT = In.getSimpleValueType();
12767 // Optimize vectors in AVX mode:
12770 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12771 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12772 // Concat upper and lower parts.
12775 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12776 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12777 // Concat upper and lower parts.
12780 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12781 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12782 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12785 if (Subtarget->hasInt256())
12786 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12788 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12789 SDValue Undef = DAG.getUNDEF(InVT);
12790 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12791 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12792 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12794 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12795 VT.getVectorNumElements()/2);
12797 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12798 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12800 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12803 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12804 SelectionDAG &DAG) {
12805 MVT VT = Op->getSimpleValueType(0);
12806 SDValue In = Op->getOperand(0);
12807 MVT InVT = In.getSimpleValueType();
12809 unsigned int NumElts = VT.getVectorNumElements();
12810 if (NumElts != 8 && NumElts != 16)
12813 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12814 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12816 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12818 // Now we have only mask extension
12819 assert(InVT.getVectorElementType() == MVT::i1);
12820 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12821 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12822 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12823 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12824 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12825 MachinePointerInfo::getConstantPool(),
12826 false, false, false, Alignment);
12828 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12829 if (VT.is512BitVector())
12831 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12834 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12835 SelectionDAG &DAG) {
12836 if (Subtarget->hasFp256()) {
12837 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12845 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12846 SelectionDAG &DAG) {
12848 MVT VT = Op.getSimpleValueType();
12849 SDValue In = Op.getOperand(0);
12850 MVT SVT = In.getSimpleValueType();
12852 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12853 return LowerZERO_EXTEND_AVX512(Op, DAG);
12855 if (Subtarget->hasFp256()) {
12856 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12861 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12862 VT.getVectorNumElements() != SVT.getVectorNumElements());
12866 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12868 MVT VT = Op.getSimpleValueType();
12869 SDValue In = Op.getOperand(0);
12870 MVT InVT = In.getSimpleValueType();
12872 if (VT == MVT::i1) {
12873 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12874 "Invalid scalar TRUNCATE operation");
12875 if (InVT.getSizeInBits() >= 32)
12877 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12878 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12880 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12881 "Invalid TRUNCATE operation");
12883 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12884 if (VT.getVectorElementType().getSizeInBits() >=8)
12885 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12887 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12888 unsigned NumElts = InVT.getVectorNumElements();
12889 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12890 if (InVT.getSizeInBits() < 512) {
12891 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12892 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12896 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12897 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12898 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12899 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12900 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12901 MachinePointerInfo::getConstantPool(),
12902 false, false, false, Alignment);
12903 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12904 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12905 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12908 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12909 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12910 if (Subtarget->hasInt256()) {
12911 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12912 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12913 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12915 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12916 DAG.getIntPtrConstant(0));
12919 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12920 DAG.getIntPtrConstant(0));
12921 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12922 DAG.getIntPtrConstant(2));
12923 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12924 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12925 static const int ShufMask[] = {0, 2, 4, 6};
12926 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12929 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12930 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12931 if (Subtarget->hasInt256()) {
12932 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12934 SmallVector<SDValue,32> pshufbMask;
12935 for (unsigned i = 0; i < 2; ++i) {
12936 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12937 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12938 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12939 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12940 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12941 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12942 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12943 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12944 for (unsigned j = 0; j < 8; ++j)
12945 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12947 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12948 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12949 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12951 static const int ShufMask[] = {0, 2, -1, -1};
12952 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12954 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12955 DAG.getIntPtrConstant(0));
12956 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12959 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12960 DAG.getIntPtrConstant(0));
12962 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12963 DAG.getIntPtrConstant(4));
12965 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12966 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12968 // The PSHUFB mask:
12969 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12970 -1, -1, -1, -1, -1, -1, -1, -1};
12972 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12973 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12974 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12976 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12977 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12979 // The MOVLHPS Mask:
12980 static const int ShufMask2[] = {0, 1, 4, 5};
12981 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12982 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12985 // Handle truncation of V256 to V128 using shuffles.
12986 if (!VT.is128BitVector() || !InVT.is256BitVector())
12989 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12991 unsigned NumElems = VT.getVectorNumElements();
12992 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12994 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12995 // Prepare truncation shuffle mask
12996 for (unsigned i = 0; i != NumElems; ++i)
12997 MaskVec[i] = i * 2;
12998 SDValue V = DAG.getVectorShuffle(NVT, DL,
12999 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13000 DAG.getUNDEF(NVT), &MaskVec[0]);
13001 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13002 DAG.getIntPtrConstant(0));
13005 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13006 SelectionDAG &DAG) const {
13007 assert(!Op.getSimpleValueType().isVector());
13009 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13010 /*IsSigned=*/ true, /*IsReplace=*/ false);
13011 SDValue FIST = Vals.first, StackSlot = Vals.second;
13012 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13013 if (!FIST.getNode()) return Op;
13015 if (StackSlot.getNode())
13016 // Load the result.
13017 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13018 FIST, StackSlot, MachinePointerInfo(),
13019 false, false, false, 0);
13021 // The node is the result.
13025 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13026 SelectionDAG &DAG) const {
13027 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13028 /*IsSigned=*/ false, /*IsReplace=*/ false);
13029 SDValue FIST = Vals.first, StackSlot = Vals.second;
13030 assert(FIST.getNode() && "Unexpected failure");
13032 if (StackSlot.getNode())
13033 // Load the result.
13034 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13035 FIST, StackSlot, MachinePointerInfo(),
13036 false, false, false, 0);
13038 // The node is the result.
13042 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13044 MVT VT = Op.getSimpleValueType();
13045 SDValue In = Op.getOperand(0);
13046 MVT SVT = In.getSimpleValueType();
13048 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13050 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13051 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13052 In, DAG.getUNDEF(SVT)));
13055 // The only differences between FABS and FNEG are the mask and the logic op.
13056 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13057 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13058 "Wrong opcode for lowering FABS or FNEG.");
13060 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13062 MVT VT = Op.getSimpleValueType();
13063 // Assume scalar op for initialization; update for vector if needed.
13064 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13065 // generate a 16-byte vector constant and logic op even for the scalar case.
13066 // Using a 16-byte mask allows folding the load of the mask with
13067 // the logic op, so it can save (~4 bytes) on code size.
13069 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13070 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13071 // decide if we should generate a 16-byte constant mask when we only need 4 or
13072 // 8 bytes for the scalar case.
13073 if (VT.isVector()) {
13074 EltVT = VT.getVectorElementType();
13075 NumElts = VT.getVectorNumElements();
13078 unsigned EltBits = EltVT.getSizeInBits();
13079 LLVMContext *Context = DAG.getContext();
13080 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13082 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13083 Constant *C = ConstantInt::get(*Context, MaskElt);
13084 C = ConstantVector::getSplat(NumElts, C);
13085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13086 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13087 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13088 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13089 MachinePointerInfo::getConstantPool(),
13090 false, false, false, Alignment);
13092 if (VT.isVector()) {
13093 // For a vector, cast operands to a vector type, perform the logic op,
13094 // and cast the result back to the original value type.
13095 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13096 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13097 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13098 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13099 return DAG.getNode(ISD::BITCAST, dl, VT,
13100 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13102 // If not vector, then scalar.
13103 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13104 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13107 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13109 LLVMContext *Context = DAG.getContext();
13110 SDValue Op0 = Op.getOperand(0);
13111 SDValue Op1 = Op.getOperand(1);
13113 MVT VT = Op.getSimpleValueType();
13114 MVT SrcVT = Op1.getSimpleValueType();
13116 // If second operand is smaller, extend it first.
13117 if (SrcVT.bitsLT(VT)) {
13118 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13121 // And if it is bigger, shrink it first.
13122 if (SrcVT.bitsGT(VT)) {
13123 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13127 // At this point the operands and the result should have the same
13128 // type, and that won't be f80 since that is not custom lowered.
13130 // First get the sign bit of second operand.
13131 SmallVector<Constant*,4> CV;
13132 if (SrcVT == MVT::f64) {
13133 const fltSemantics &Sem = APFloat::IEEEdouble;
13134 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13135 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13137 const fltSemantics &Sem = APFloat::IEEEsingle;
13138 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13139 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13140 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13141 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13143 Constant *C = ConstantVector::get(CV);
13144 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13145 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13146 MachinePointerInfo::getConstantPool(),
13147 false, false, false, 16);
13148 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13150 // Shift sign bit right or left if the two operands have different types.
13151 if (SrcVT.bitsGT(VT)) {
13152 // Op0 is MVT::f32, Op1 is MVT::f64.
13153 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13154 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13155 DAG.getConstant(32, MVT::i32));
13156 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13157 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13158 DAG.getIntPtrConstant(0));
13161 // Clear first operand sign bit.
13163 if (VT == MVT::f64) {
13164 const fltSemantics &Sem = APFloat::IEEEdouble;
13165 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13166 APInt(64, ~(1ULL << 63)))));
13167 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13169 const fltSemantics &Sem = APFloat::IEEEsingle;
13170 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13171 APInt(32, ~(1U << 31)))));
13172 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13173 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13174 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13176 C = ConstantVector::get(CV);
13177 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13178 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13179 MachinePointerInfo::getConstantPool(),
13180 false, false, false, 16);
13181 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13183 // Or the value with the sign bit.
13184 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13187 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13188 SDValue N0 = Op.getOperand(0);
13190 MVT VT = Op.getSimpleValueType();
13192 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13193 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13194 DAG.getConstant(1, VT));
13195 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13198 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13200 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13201 SelectionDAG &DAG) {
13202 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13204 if (!Subtarget->hasSSE41())
13207 if (!Op->hasOneUse())
13210 SDNode *N = Op.getNode();
13213 SmallVector<SDValue, 8> Opnds;
13214 DenseMap<SDValue, unsigned> VecInMap;
13215 SmallVector<SDValue, 8> VecIns;
13216 EVT VT = MVT::Other;
13218 // Recognize a special case where a vector is casted into wide integer to
13220 Opnds.push_back(N->getOperand(0));
13221 Opnds.push_back(N->getOperand(1));
13223 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13224 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13225 // BFS traverse all OR'd operands.
13226 if (I->getOpcode() == ISD::OR) {
13227 Opnds.push_back(I->getOperand(0));
13228 Opnds.push_back(I->getOperand(1));
13229 // Re-evaluate the number of nodes to be traversed.
13230 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13234 // Quit if a non-EXTRACT_VECTOR_ELT
13235 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13238 // Quit if without a constant index.
13239 SDValue Idx = I->getOperand(1);
13240 if (!isa<ConstantSDNode>(Idx))
13243 SDValue ExtractedFromVec = I->getOperand(0);
13244 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13245 if (M == VecInMap.end()) {
13246 VT = ExtractedFromVec.getValueType();
13247 // Quit if not 128/256-bit vector.
13248 if (!VT.is128BitVector() && !VT.is256BitVector())
13250 // Quit if not the same type.
13251 if (VecInMap.begin() != VecInMap.end() &&
13252 VT != VecInMap.begin()->first.getValueType())
13254 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13255 VecIns.push_back(ExtractedFromVec);
13257 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13260 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13261 "Not extracted from 128-/256-bit vector.");
13263 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13265 for (DenseMap<SDValue, unsigned>::const_iterator
13266 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13267 // Quit if not all elements are used.
13268 if (I->second != FullMask)
13272 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13274 // Cast all vectors into TestVT for PTEST.
13275 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13276 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13278 // If more than one full vectors are evaluated, OR them first before PTEST.
13279 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13280 // Each iteration will OR 2 nodes and append the result until there is only
13281 // 1 node left, i.e. the final OR'd value of all vectors.
13282 SDValue LHS = VecIns[Slot];
13283 SDValue RHS = VecIns[Slot + 1];
13284 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13287 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13288 VecIns.back(), VecIns.back());
13291 /// \brief return true if \c Op has a use that doesn't just read flags.
13292 static bool hasNonFlagsUse(SDValue Op) {
13293 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13295 SDNode *User = *UI;
13296 unsigned UOpNo = UI.getOperandNo();
13297 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13298 // Look pass truncate.
13299 UOpNo = User->use_begin().getOperandNo();
13300 User = *User->use_begin();
13303 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13304 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13310 /// Emit nodes that will be selected as "test Op0,Op0", or something
13312 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13313 SelectionDAG &DAG) const {
13314 if (Op.getValueType() == MVT::i1)
13315 // KORTEST instruction should be selected
13316 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13317 DAG.getConstant(0, Op.getValueType()));
13319 // CF and OF aren't always set the way we want. Determine which
13320 // of these we need.
13321 bool NeedCF = false;
13322 bool NeedOF = false;
13325 case X86::COND_A: case X86::COND_AE:
13326 case X86::COND_B: case X86::COND_BE:
13329 case X86::COND_G: case X86::COND_GE:
13330 case X86::COND_L: case X86::COND_LE:
13331 case X86::COND_O: case X86::COND_NO: {
13332 // Check if we really need to set the
13333 // Overflow flag. If NoSignedWrap is present
13334 // that is not actually needed.
13335 switch (Op->getOpcode()) {
13340 const BinaryWithFlagsSDNode *BinNode =
13341 cast<BinaryWithFlagsSDNode>(Op.getNode());
13342 if (BinNode->hasNoSignedWrap())
13352 // See if we can use the EFLAGS value from the operand instead of
13353 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13354 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13355 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13356 // Emit a CMP with 0, which is the TEST pattern.
13357 //if (Op.getValueType() == MVT::i1)
13358 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13359 // DAG.getConstant(0, MVT::i1));
13360 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13361 DAG.getConstant(0, Op.getValueType()));
13363 unsigned Opcode = 0;
13364 unsigned NumOperands = 0;
13366 // Truncate operations may prevent the merge of the SETCC instruction
13367 // and the arithmetic instruction before it. Attempt to truncate the operands
13368 // of the arithmetic instruction and use a reduced bit-width instruction.
13369 bool NeedTruncation = false;
13370 SDValue ArithOp = Op;
13371 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13372 SDValue Arith = Op->getOperand(0);
13373 // Both the trunc and the arithmetic op need to have one user each.
13374 if (Arith->hasOneUse())
13375 switch (Arith.getOpcode()) {
13382 NeedTruncation = true;
13388 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13389 // which may be the result of a CAST. We use the variable 'Op', which is the
13390 // non-casted variable when we check for possible users.
13391 switch (ArithOp.getOpcode()) {
13393 // Due to an isel shortcoming, be conservative if this add is likely to be
13394 // selected as part of a load-modify-store instruction. When the root node
13395 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13396 // uses of other nodes in the match, such as the ADD in this case. This
13397 // leads to the ADD being left around and reselected, with the result being
13398 // two adds in the output. Alas, even if none our users are stores, that
13399 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13400 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13401 // climbing the DAG back to the root, and it doesn't seem to be worth the
13403 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13404 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13405 if (UI->getOpcode() != ISD::CopyToReg &&
13406 UI->getOpcode() != ISD::SETCC &&
13407 UI->getOpcode() != ISD::STORE)
13410 if (ConstantSDNode *C =
13411 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13412 // An add of one will be selected as an INC.
13413 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13414 Opcode = X86ISD::INC;
13419 // An add of negative one (subtract of one) will be selected as a DEC.
13420 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13421 Opcode = X86ISD::DEC;
13427 // Otherwise use a regular EFLAGS-setting add.
13428 Opcode = X86ISD::ADD;
13433 // If we have a constant logical shift that's only used in a comparison
13434 // against zero turn it into an equivalent AND. This allows turning it into
13435 // a TEST instruction later.
13436 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13437 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13438 EVT VT = Op.getValueType();
13439 unsigned BitWidth = VT.getSizeInBits();
13440 unsigned ShAmt = Op->getConstantOperandVal(1);
13441 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13443 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13444 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13445 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13446 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13448 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13449 DAG.getConstant(Mask, VT));
13450 DAG.ReplaceAllUsesWith(Op, New);
13456 // If the primary and result isn't used, don't bother using X86ISD::AND,
13457 // because a TEST instruction will be better.
13458 if (!hasNonFlagsUse(Op))
13464 // Due to the ISEL shortcoming noted above, be conservative if this op is
13465 // likely to be selected as part of a load-modify-store instruction.
13466 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13467 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13468 if (UI->getOpcode() == ISD::STORE)
13471 // Otherwise use a regular EFLAGS-setting instruction.
13472 switch (ArithOp.getOpcode()) {
13473 default: llvm_unreachable("unexpected operator!");
13474 case ISD::SUB: Opcode = X86ISD::SUB; break;
13475 case ISD::XOR: Opcode = X86ISD::XOR; break;
13476 case ISD::AND: Opcode = X86ISD::AND; break;
13478 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13479 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13480 if (EFLAGS.getNode())
13483 Opcode = X86ISD::OR;
13497 return SDValue(Op.getNode(), 1);
13503 // If we found that truncation is beneficial, perform the truncation and
13505 if (NeedTruncation) {
13506 EVT VT = Op.getValueType();
13507 SDValue WideVal = Op->getOperand(0);
13508 EVT WideVT = WideVal.getValueType();
13509 unsigned ConvertedOp = 0;
13510 // Use a target machine opcode to prevent further DAGCombine
13511 // optimizations that may separate the arithmetic operations
13512 // from the setcc node.
13513 switch (WideVal.getOpcode()) {
13515 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13516 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13517 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13518 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13519 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13524 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13525 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13526 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13527 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13533 // Emit a CMP with 0, which is the TEST pattern.
13534 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13535 DAG.getConstant(0, Op.getValueType()));
13537 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13538 SmallVector<SDValue, 4> Ops;
13539 for (unsigned i = 0; i != NumOperands; ++i)
13540 Ops.push_back(Op.getOperand(i));
13542 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13543 DAG.ReplaceAllUsesWith(Op, New);
13544 return SDValue(New.getNode(), 1);
13547 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13549 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13550 SDLoc dl, SelectionDAG &DAG) const {
13551 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13552 if (C->getAPIntValue() == 0)
13553 return EmitTest(Op0, X86CC, dl, DAG);
13555 if (Op0.getValueType() == MVT::i1)
13556 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13559 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13560 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13561 // Do the comparison at i32 if it's smaller, besides the Atom case.
13562 // This avoids subregister aliasing issues. Keep the smaller reference
13563 // if we're optimizing for size, however, as that'll allow better folding
13564 // of memory operations.
13565 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13566 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13567 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13568 !Subtarget->isAtom()) {
13569 unsigned ExtendOp =
13570 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13571 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13572 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13574 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13575 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13576 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13578 return SDValue(Sub.getNode(), 1);
13580 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13583 /// Convert a comparison if required by the subtarget.
13584 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13585 SelectionDAG &DAG) const {
13586 // If the subtarget does not support the FUCOMI instruction, floating-point
13587 // comparisons have to be converted.
13588 if (Subtarget->hasCMov() ||
13589 Cmp.getOpcode() != X86ISD::CMP ||
13590 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13591 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13594 // The instruction selector will select an FUCOM instruction instead of
13595 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13596 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13597 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13599 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13600 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13601 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13602 DAG.getConstant(8, MVT::i8));
13603 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13604 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13607 static bool isAllOnes(SDValue V) {
13608 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13609 return C && C->isAllOnesValue();
13612 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13613 /// if it's possible.
13614 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13615 SDLoc dl, SelectionDAG &DAG) const {
13616 SDValue Op0 = And.getOperand(0);
13617 SDValue Op1 = And.getOperand(1);
13618 if (Op0.getOpcode() == ISD::TRUNCATE)
13619 Op0 = Op0.getOperand(0);
13620 if (Op1.getOpcode() == ISD::TRUNCATE)
13621 Op1 = Op1.getOperand(0);
13624 if (Op1.getOpcode() == ISD::SHL)
13625 std::swap(Op0, Op1);
13626 if (Op0.getOpcode() == ISD::SHL) {
13627 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13628 if (And00C->getZExtValue() == 1) {
13629 // If we looked past a truncate, check that it's only truncating away
13631 unsigned BitWidth = Op0.getValueSizeInBits();
13632 unsigned AndBitWidth = And.getValueSizeInBits();
13633 if (BitWidth > AndBitWidth) {
13635 DAG.computeKnownBits(Op0, Zeros, Ones);
13636 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13640 RHS = Op0.getOperand(1);
13642 } else if (Op1.getOpcode() == ISD::Constant) {
13643 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13644 uint64_t AndRHSVal = AndRHS->getZExtValue();
13645 SDValue AndLHS = Op0;
13647 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13648 LHS = AndLHS.getOperand(0);
13649 RHS = AndLHS.getOperand(1);
13652 // Use BT if the immediate can't be encoded in a TEST instruction.
13653 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13655 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13659 if (LHS.getNode()) {
13660 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13661 // instruction. Since the shift amount is in-range-or-undefined, we know
13662 // that doing a bittest on the i32 value is ok. We extend to i32 because
13663 // the encoding for the i16 version is larger than the i32 version.
13664 // Also promote i16 to i32 for performance / code size reason.
13665 if (LHS.getValueType() == MVT::i8 ||
13666 LHS.getValueType() == MVT::i16)
13667 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13669 // If the operand types disagree, extend the shift amount to match. Since
13670 // BT ignores high bits (like shifts) we can use anyextend.
13671 if (LHS.getValueType() != RHS.getValueType())
13672 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13674 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13675 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13676 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13677 DAG.getConstant(Cond, MVT::i8), BT);
13683 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13685 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13690 // SSE Condition code mapping:
13699 switch (SetCCOpcode) {
13700 default: llvm_unreachable("Unexpected SETCC condition");
13702 case ISD::SETEQ: SSECC = 0; break;
13704 case ISD::SETGT: Swap = true; // Fallthrough
13706 case ISD::SETOLT: SSECC = 1; break;
13708 case ISD::SETGE: Swap = true; // Fallthrough
13710 case ISD::SETOLE: SSECC = 2; break;
13711 case ISD::SETUO: SSECC = 3; break;
13713 case ISD::SETNE: SSECC = 4; break;
13714 case ISD::SETULE: Swap = true; // Fallthrough
13715 case ISD::SETUGE: SSECC = 5; break;
13716 case ISD::SETULT: Swap = true; // Fallthrough
13717 case ISD::SETUGT: SSECC = 6; break;
13718 case ISD::SETO: SSECC = 7; break;
13720 case ISD::SETONE: SSECC = 8; break;
13723 std::swap(Op0, Op1);
13728 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13729 // ones, and then concatenate the result back.
13730 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13731 MVT VT = Op.getSimpleValueType();
13733 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13734 "Unsupported value type for operation");
13736 unsigned NumElems = VT.getVectorNumElements();
13738 SDValue CC = Op.getOperand(2);
13740 // Extract the LHS vectors
13741 SDValue LHS = Op.getOperand(0);
13742 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13743 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13745 // Extract the RHS vectors
13746 SDValue RHS = Op.getOperand(1);
13747 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13748 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13750 // Issue the operation on the smaller types and concatenate the result back
13751 MVT EltVT = VT.getVectorElementType();
13752 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13753 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13754 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13755 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13758 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13759 const X86Subtarget *Subtarget) {
13760 SDValue Op0 = Op.getOperand(0);
13761 SDValue Op1 = Op.getOperand(1);
13762 SDValue CC = Op.getOperand(2);
13763 MVT VT = Op.getSimpleValueType();
13766 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13767 Op.getValueType().getScalarType() == MVT::i1 &&
13768 "Cannot set masked compare for this operation");
13770 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13772 bool Unsigned = false;
13775 switch (SetCCOpcode) {
13776 default: llvm_unreachable("Unexpected SETCC condition");
13777 case ISD::SETNE: SSECC = 4; break;
13778 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13779 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13780 case ISD::SETLT: Swap = true; //fall-through
13781 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13782 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13783 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13784 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13785 case ISD::SETULE: Unsigned = true; //fall-through
13786 case ISD::SETLE: SSECC = 2; break;
13790 std::swap(Op0, Op1);
13792 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13793 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13794 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13795 DAG.getConstant(SSECC, MVT::i8));
13798 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13799 /// operand \p Op1. If non-trivial (for example because it's not constant)
13800 /// return an empty value.
13801 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13803 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13807 MVT VT = Op1.getSimpleValueType();
13808 MVT EVT = VT.getVectorElementType();
13809 unsigned n = VT.getVectorNumElements();
13810 SmallVector<SDValue, 8> ULTOp1;
13812 for (unsigned i = 0; i < n; ++i) {
13813 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13814 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13817 // Avoid underflow.
13818 APInt Val = Elt->getAPIntValue();
13822 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13825 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13828 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13829 SelectionDAG &DAG) {
13830 SDValue Op0 = Op.getOperand(0);
13831 SDValue Op1 = Op.getOperand(1);
13832 SDValue CC = Op.getOperand(2);
13833 MVT VT = Op.getSimpleValueType();
13834 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13835 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13840 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13841 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13844 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13845 unsigned Opc = X86ISD::CMPP;
13846 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13847 assert(VT.getVectorNumElements() <= 16);
13848 Opc = X86ISD::CMPM;
13850 // In the two special cases we can't handle, emit two comparisons.
13853 unsigned CombineOpc;
13854 if (SetCCOpcode == ISD::SETUEQ) {
13855 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13857 assert(SetCCOpcode == ISD::SETONE);
13858 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13861 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13862 DAG.getConstant(CC0, MVT::i8));
13863 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13864 DAG.getConstant(CC1, MVT::i8));
13865 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13867 // Handle all other FP comparisons here.
13868 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13869 DAG.getConstant(SSECC, MVT::i8));
13872 // Break 256-bit integer vector compare into smaller ones.
13873 if (VT.is256BitVector() && !Subtarget->hasInt256())
13874 return Lower256IntVSETCC(Op, DAG);
13876 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13877 EVT OpVT = Op1.getValueType();
13878 if (Subtarget->hasAVX512()) {
13879 if (Op1.getValueType().is512BitVector() ||
13880 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13881 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13882 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13884 // In AVX-512 architecture setcc returns mask with i1 elements,
13885 // But there is no compare instruction for i8 and i16 elements in KNL.
13886 // We are not talking about 512-bit operands in this case, these
13887 // types are illegal.
13889 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13890 OpVT.getVectorElementType().getSizeInBits() >= 8))
13891 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13892 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13895 // We are handling one of the integer comparisons here. Since SSE only has
13896 // GT and EQ comparisons for integer, swapping operands and multiple
13897 // operations may be required for some comparisons.
13899 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13900 bool Subus = false;
13902 switch (SetCCOpcode) {
13903 default: llvm_unreachable("Unexpected SETCC condition");
13904 case ISD::SETNE: Invert = true;
13905 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13906 case ISD::SETLT: Swap = true;
13907 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13908 case ISD::SETGE: Swap = true;
13909 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13910 Invert = true; break;
13911 case ISD::SETULT: Swap = true;
13912 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13913 FlipSigns = true; break;
13914 case ISD::SETUGE: Swap = true;
13915 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13916 FlipSigns = true; Invert = true; break;
13919 // Special case: Use min/max operations for SETULE/SETUGE
13920 MVT VET = VT.getVectorElementType();
13922 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13923 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13926 switch (SetCCOpcode) {
13928 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13929 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13932 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13935 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13936 if (!MinMax && hasSubus) {
13937 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13939 // t = psubus Op0, Op1
13940 // pcmpeq t, <0..0>
13941 switch (SetCCOpcode) {
13943 case ISD::SETULT: {
13944 // If the comparison is against a constant we can turn this into a
13945 // setule. With psubus, setule does not require a swap. This is
13946 // beneficial because the constant in the register is no longer
13947 // destructed as the destination so it can be hoisted out of a loop.
13948 // Only do this pre-AVX since vpcmp* is no longer destructive.
13949 if (Subtarget->hasAVX())
13951 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13952 if (ULEOp1.getNode()) {
13954 Subus = true; Invert = false; Swap = false;
13958 // Psubus is better than flip-sign because it requires no inversion.
13959 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13960 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13964 Opc = X86ISD::SUBUS;
13970 std::swap(Op0, Op1);
13972 // Check that the operation in question is available (most are plain SSE2,
13973 // but PCMPGTQ and PCMPEQQ have different requirements).
13974 if (VT == MVT::v2i64) {
13975 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13976 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13978 // First cast everything to the right type.
13979 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13980 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13982 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13983 // bits of the inputs before performing those operations. The lower
13984 // compare is always unsigned.
13987 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13989 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13990 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13991 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13992 Sign, Zero, Sign, Zero);
13994 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13995 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13997 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13998 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13999 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14001 // Create masks for only the low parts/high parts of the 64 bit integers.
14002 static const int MaskHi[] = { 1, 1, 3, 3 };
14003 static const int MaskLo[] = { 0, 0, 2, 2 };
14004 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14005 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14006 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14008 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14009 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14012 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14014 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14017 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14018 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14019 // pcmpeqd + pshufd + pand.
14020 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14022 // First cast everything to the right type.
14023 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14024 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14027 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14029 // Make sure the lower and upper halves are both all-ones.
14030 static const int Mask[] = { 1, 0, 3, 2 };
14031 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14032 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14035 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14037 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14041 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14042 // bits of the inputs before performing those operations.
14044 EVT EltVT = VT.getVectorElementType();
14045 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14046 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14047 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14050 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14052 // If the logical-not of the result is required, perform that now.
14054 Result = DAG.getNOT(dl, Result, VT);
14057 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14060 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14061 getZeroVector(VT, Subtarget, DAG, dl));
14066 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14068 MVT VT = Op.getSimpleValueType();
14070 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14072 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14073 && "SetCC type must be 8-bit or 1-bit integer");
14074 SDValue Op0 = Op.getOperand(0);
14075 SDValue Op1 = Op.getOperand(1);
14077 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14079 // Optimize to BT if possible.
14080 // Lower (X & (1 << N)) == 0 to BT(X, N).
14081 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14082 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14083 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14084 Op1.getOpcode() == ISD::Constant &&
14085 cast<ConstantSDNode>(Op1)->isNullValue() &&
14086 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14087 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14088 if (NewSetCC.getNode())
14092 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14094 if (Op1.getOpcode() == ISD::Constant &&
14095 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14096 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14097 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14099 // If the input is a setcc, then reuse the input setcc or use a new one with
14100 // the inverted condition.
14101 if (Op0.getOpcode() == X86ISD::SETCC) {
14102 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14103 bool Invert = (CC == ISD::SETNE) ^
14104 cast<ConstantSDNode>(Op1)->isNullValue();
14108 CCode = X86::GetOppositeBranchCondition(CCode);
14109 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14110 DAG.getConstant(CCode, MVT::i8),
14111 Op0.getOperand(1));
14113 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14117 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14118 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14119 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14121 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14122 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14125 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14126 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14127 if (X86CC == X86::COND_INVALID)
14130 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14131 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14132 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14133 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14135 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14139 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14140 static bool isX86LogicalCmp(SDValue Op) {
14141 unsigned Opc = Op.getNode()->getOpcode();
14142 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14143 Opc == X86ISD::SAHF)
14145 if (Op.getResNo() == 1 &&
14146 (Opc == X86ISD::ADD ||
14147 Opc == X86ISD::SUB ||
14148 Opc == X86ISD::ADC ||
14149 Opc == X86ISD::SBB ||
14150 Opc == X86ISD::SMUL ||
14151 Opc == X86ISD::UMUL ||
14152 Opc == X86ISD::INC ||
14153 Opc == X86ISD::DEC ||
14154 Opc == X86ISD::OR ||
14155 Opc == X86ISD::XOR ||
14156 Opc == X86ISD::AND))
14159 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14165 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14166 if (V.getOpcode() != ISD::TRUNCATE)
14169 SDValue VOp0 = V.getOperand(0);
14170 unsigned InBits = VOp0.getValueSizeInBits();
14171 unsigned Bits = V.getValueSizeInBits();
14172 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14175 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14176 bool addTest = true;
14177 SDValue Cond = Op.getOperand(0);
14178 SDValue Op1 = Op.getOperand(1);
14179 SDValue Op2 = Op.getOperand(2);
14181 EVT VT = Op1.getValueType();
14184 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14185 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14186 // sequence later on.
14187 if (Cond.getOpcode() == ISD::SETCC &&
14188 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14189 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14190 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14191 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14192 int SSECC = translateX86FSETCC(
14193 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14196 if (Subtarget->hasAVX512()) {
14197 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14198 DAG.getConstant(SSECC, MVT::i8));
14199 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14201 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14202 DAG.getConstant(SSECC, MVT::i8));
14203 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14204 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14205 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14209 if (Cond.getOpcode() == ISD::SETCC) {
14210 SDValue NewCond = LowerSETCC(Cond, DAG);
14211 if (NewCond.getNode())
14215 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14216 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14217 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14218 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14219 if (Cond.getOpcode() == X86ISD::SETCC &&
14220 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14221 isZero(Cond.getOperand(1).getOperand(1))) {
14222 SDValue Cmp = Cond.getOperand(1);
14224 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14226 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14227 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14228 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14230 SDValue CmpOp0 = Cmp.getOperand(0);
14231 // Apply further optimizations for special cases
14232 // (select (x != 0), -1, 0) -> neg & sbb
14233 // (select (x == 0), 0, -1) -> neg & sbb
14234 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14235 if (YC->isNullValue() &&
14236 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14237 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14238 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14239 DAG.getConstant(0, CmpOp0.getValueType()),
14241 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14242 DAG.getConstant(X86::COND_B, MVT::i8),
14243 SDValue(Neg.getNode(), 1));
14247 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14248 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14249 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14251 SDValue Res = // Res = 0 or -1.
14252 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14253 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14255 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14256 Res = DAG.getNOT(DL, Res, Res.getValueType());
14258 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14259 if (!N2C || !N2C->isNullValue())
14260 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14265 // Look past (and (setcc_carry (cmp ...)), 1).
14266 if (Cond.getOpcode() == ISD::AND &&
14267 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14268 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14269 if (C && C->getAPIntValue() == 1)
14270 Cond = Cond.getOperand(0);
14273 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14274 // setting operand in place of the X86ISD::SETCC.
14275 unsigned CondOpcode = Cond.getOpcode();
14276 if (CondOpcode == X86ISD::SETCC ||
14277 CondOpcode == X86ISD::SETCC_CARRY) {
14278 CC = Cond.getOperand(0);
14280 SDValue Cmp = Cond.getOperand(1);
14281 unsigned Opc = Cmp.getOpcode();
14282 MVT VT = Op.getSimpleValueType();
14284 bool IllegalFPCMov = false;
14285 if (VT.isFloatingPoint() && !VT.isVector() &&
14286 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14287 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14289 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14290 Opc == X86ISD::BT) { // FIXME
14294 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14295 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14296 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14297 Cond.getOperand(0).getValueType() != MVT::i8)) {
14298 SDValue LHS = Cond.getOperand(0);
14299 SDValue RHS = Cond.getOperand(1);
14300 unsigned X86Opcode;
14303 switch (CondOpcode) {
14304 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14305 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14306 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14307 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14308 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14309 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14310 default: llvm_unreachable("unexpected overflowing operator");
14312 if (CondOpcode == ISD::UMULO)
14313 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14316 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14318 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14320 if (CondOpcode == ISD::UMULO)
14321 Cond = X86Op.getValue(2);
14323 Cond = X86Op.getValue(1);
14325 CC = DAG.getConstant(X86Cond, MVT::i8);
14330 // Look pass the truncate if the high bits are known zero.
14331 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14332 Cond = Cond.getOperand(0);
14334 // We know the result of AND is compared against zero. Try to match
14336 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14337 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14338 if (NewSetCC.getNode()) {
14339 CC = NewSetCC.getOperand(0);
14340 Cond = NewSetCC.getOperand(1);
14347 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14348 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14351 // a < b ? -1 : 0 -> RES = ~setcc_carry
14352 // a < b ? 0 : -1 -> RES = setcc_carry
14353 // a >= b ? -1 : 0 -> RES = setcc_carry
14354 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14355 if (Cond.getOpcode() == X86ISD::SUB) {
14356 Cond = ConvertCmpIfNecessary(Cond, DAG);
14357 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14359 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14360 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14361 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14362 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14363 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14364 return DAG.getNOT(DL, Res, Res.getValueType());
14369 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14370 // widen the cmov and push the truncate through. This avoids introducing a new
14371 // branch during isel and doesn't add any extensions.
14372 if (Op.getValueType() == MVT::i8 &&
14373 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14374 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14375 if (T1.getValueType() == T2.getValueType() &&
14376 // Blacklist CopyFromReg to avoid partial register stalls.
14377 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14378 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14379 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14380 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14384 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14385 // condition is true.
14386 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14387 SDValue Ops[] = { Op2, Op1, CC, Cond };
14388 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14391 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14392 MVT VT = Op->getSimpleValueType(0);
14393 SDValue In = Op->getOperand(0);
14394 MVT InVT = In.getSimpleValueType();
14397 unsigned int NumElts = VT.getVectorNumElements();
14398 if (NumElts != 8 && NumElts != 16)
14401 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14402 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14405 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14407 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14408 Constant *C = ConstantInt::get(*DAG.getContext(),
14409 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14411 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14412 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14413 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14414 MachinePointerInfo::getConstantPool(),
14415 false, false, false, Alignment);
14416 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14417 if (VT.is512BitVector())
14419 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14422 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14423 SelectionDAG &DAG) {
14424 MVT VT = Op->getSimpleValueType(0);
14425 SDValue In = Op->getOperand(0);
14426 MVT InVT = In.getSimpleValueType();
14429 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14430 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14432 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14433 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14434 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14437 if (Subtarget->hasInt256())
14438 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14440 // Optimize vectors in AVX mode
14441 // Sign extend v8i16 to v8i32 and
14444 // Divide input vector into two parts
14445 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14446 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14447 // concat the vectors to original VT
14449 unsigned NumElems = InVT.getVectorNumElements();
14450 SDValue Undef = DAG.getUNDEF(InVT);
14452 SmallVector<int,8> ShufMask1(NumElems, -1);
14453 for (unsigned i = 0; i != NumElems/2; ++i)
14456 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14458 SmallVector<int,8> ShufMask2(NumElems, -1);
14459 for (unsigned i = 0; i != NumElems/2; ++i)
14460 ShufMask2[i] = i + NumElems/2;
14462 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14464 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14465 VT.getVectorNumElements()/2);
14467 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14468 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14470 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14473 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14474 // may emit an illegal shuffle but the expansion is still better than scalar
14475 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14476 // we'll emit a shuffle and a arithmetic shift.
14477 // TODO: It is possible to support ZExt by zeroing the undef values during
14478 // the shuffle phase or after the shuffle.
14479 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14480 SelectionDAG &DAG) {
14481 MVT RegVT = Op.getSimpleValueType();
14482 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14483 assert(RegVT.isInteger() &&
14484 "We only custom lower integer vector sext loads.");
14486 // Nothing useful we can do without SSE2 shuffles.
14487 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14489 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14491 EVT MemVT = Ld->getMemoryVT();
14492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14493 unsigned RegSz = RegVT.getSizeInBits();
14495 ISD::LoadExtType Ext = Ld->getExtensionType();
14497 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14498 && "Only anyext and sext are currently implemented.");
14499 assert(MemVT != RegVT && "Cannot extend to the same type");
14500 assert(MemVT.isVector() && "Must load a vector from memory");
14502 unsigned NumElems = RegVT.getVectorNumElements();
14503 unsigned MemSz = MemVT.getSizeInBits();
14504 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14506 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14507 // The only way in which we have a legal 256-bit vector result but not the
14508 // integer 256-bit operations needed to directly lower a sextload is if we
14509 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14510 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14511 // correctly legalized. We do this late to allow the canonical form of
14512 // sextload to persist throughout the rest of the DAG combiner -- it wants
14513 // to fold together any extensions it can, and so will fuse a sign_extend
14514 // of an sextload into a sextload targeting a wider value.
14516 if (MemSz == 128) {
14517 // Just switch this to a normal load.
14518 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14519 "it must be a legal 128-bit vector "
14521 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14522 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14523 Ld->isInvariant(), Ld->getAlignment());
14525 assert(MemSz < 128 &&
14526 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14527 // Do an sext load to a 128-bit vector type. We want to use the same
14528 // number of elements, but elements half as wide. This will end up being
14529 // recursively lowered by this routine, but will succeed as we definitely
14530 // have all the necessary features if we're using AVX1.
14532 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14533 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14535 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14536 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14537 Ld->isNonTemporal(), Ld->isInvariant(),
14538 Ld->getAlignment());
14541 // Replace chain users with the new chain.
14542 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14543 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14545 // Finally, do a normal sign-extend to the desired register.
14546 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14549 // All sizes must be a power of two.
14550 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14551 "Non-power-of-two elements are not custom lowered!");
14553 // Attempt to load the original value using scalar loads.
14554 // Find the largest scalar type that divides the total loaded size.
14555 MVT SclrLoadTy = MVT::i8;
14556 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14557 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14558 MVT Tp = (MVT::SimpleValueType)tp;
14559 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14564 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14565 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14567 SclrLoadTy = MVT::f64;
14569 // Calculate the number of scalar loads that we need to perform
14570 // in order to load our vector from memory.
14571 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14573 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14574 "Can only lower sext loads with a single scalar load!");
14576 unsigned loadRegZize = RegSz;
14577 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14580 // Represent our vector as a sequence of elements which are the
14581 // largest scalar that we can load.
14582 EVT LoadUnitVecVT = EVT::getVectorVT(
14583 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14585 // Represent the data using the same element type that is stored in
14586 // memory. In practice, we ''widen'' MemVT.
14588 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14589 loadRegZize / MemVT.getScalarType().getSizeInBits());
14591 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14592 "Invalid vector type");
14594 // We can't shuffle using an illegal type.
14595 assert(TLI.isTypeLegal(WideVecVT) &&
14596 "We only lower types that form legal widened vector types");
14598 SmallVector<SDValue, 8> Chains;
14599 SDValue Ptr = Ld->getBasePtr();
14600 SDValue Increment =
14601 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14602 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14604 for (unsigned i = 0; i < NumLoads; ++i) {
14605 // Perform a single load.
14606 SDValue ScalarLoad =
14607 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14608 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14609 Ld->getAlignment());
14610 Chains.push_back(ScalarLoad.getValue(1));
14611 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14612 // another round of DAGCombining.
14614 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14616 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14617 ScalarLoad, DAG.getIntPtrConstant(i));
14619 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14622 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14624 // Bitcast the loaded value to a vector of the original element type, in
14625 // the size of the target vector type.
14626 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14627 unsigned SizeRatio = RegSz / MemSz;
14629 if (Ext == ISD::SEXTLOAD) {
14630 // If we have SSE4.1, we can directly emit a VSEXT node.
14631 if (Subtarget->hasSSE41()) {
14632 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14633 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14637 // Otherwise we'll shuffle the small elements in the high bits of the
14638 // larger type and perform an arithmetic shift. If the shift is not legal
14639 // it's better to scalarize.
14640 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14641 "We can't implement a sext load without an arithmetic right shift!");
14643 // Redistribute the loaded elements into the different locations.
14644 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14645 for (unsigned i = 0; i != NumElems; ++i)
14646 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14648 SDValue Shuff = DAG.getVectorShuffle(
14649 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14651 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14653 // Build the arithmetic shift.
14654 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14655 MemVT.getVectorElementType().getSizeInBits();
14657 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14659 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14663 // Redistribute the loaded elements into the different locations.
14664 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14665 for (unsigned i = 0; i != NumElems; ++i)
14666 ShuffleVec[i * SizeRatio] = i;
14668 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14669 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14671 // Bitcast to the requested type.
14672 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14673 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14677 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14678 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14679 // from the AND / OR.
14680 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14681 Opc = Op.getOpcode();
14682 if (Opc != ISD::OR && Opc != ISD::AND)
14684 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14685 Op.getOperand(0).hasOneUse() &&
14686 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14687 Op.getOperand(1).hasOneUse());
14690 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14691 // 1 and that the SETCC node has a single use.
14692 static bool isXor1OfSetCC(SDValue Op) {
14693 if (Op.getOpcode() != ISD::XOR)
14695 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14696 if (N1C && N1C->getAPIntValue() == 1) {
14697 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14698 Op.getOperand(0).hasOneUse();
14703 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14704 bool addTest = true;
14705 SDValue Chain = Op.getOperand(0);
14706 SDValue Cond = Op.getOperand(1);
14707 SDValue Dest = Op.getOperand(2);
14710 bool Inverted = false;
14712 if (Cond.getOpcode() == ISD::SETCC) {
14713 // Check for setcc([su]{add,sub,mul}o == 0).
14714 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14715 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14716 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14717 Cond.getOperand(0).getResNo() == 1 &&
14718 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14719 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14720 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14721 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14722 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14723 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14725 Cond = Cond.getOperand(0);
14727 SDValue NewCond = LowerSETCC(Cond, DAG);
14728 if (NewCond.getNode())
14733 // FIXME: LowerXALUO doesn't handle these!!
14734 else if (Cond.getOpcode() == X86ISD::ADD ||
14735 Cond.getOpcode() == X86ISD::SUB ||
14736 Cond.getOpcode() == X86ISD::SMUL ||
14737 Cond.getOpcode() == X86ISD::UMUL)
14738 Cond = LowerXALUO(Cond, DAG);
14741 // Look pass (and (setcc_carry (cmp ...)), 1).
14742 if (Cond.getOpcode() == ISD::AND &&
14743 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14744 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14745 if (C && C->getAPIntValue() == 1)
14746 Cond = Cond.getOperand(0);
14749 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14750 // setting operand in place of the X86ISD::SETCC.
14751 unsigned CondOpcode = Cond.getOpcode();
14752 if (CondOpcode == X86ISD::SETCC ||
14753 CondOpcode == X86ISD::SETCC_CARRY) {
14754 CC = Cond.getOperand(0);
14756 SDValue Cmp = Cond.getOperand(1);
14757 unsigned Opc = Cmp.getOpcode();
14758 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14759 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14763 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14767 // These can only come from an arithmetic instruction with overflow,
14768 // e.g. SADDO, UADDO.
14769 Cond = Cond.getNode()->getOperand(1);
14775 CondOpcode = Cond.getOpcode();
14776 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14777 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14778 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14779 Cond.getOperand(0).getValueType() != MVT::i8)) {
14780 SDValue LHS = Cond.getOperand(0);
14781 SDValue RHS = Cond.getOperand(1);
14782 unsigned X86Opcode;
14785 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14786 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14788 switch (CondOpcode) {
14789 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14791 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14793 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14796 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14797 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14799 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14801 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14804 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14805 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14806 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14807 default: llvm_unreachable("unexpected overflowing operator");
14810 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14811 if (CondOpcode == ISD::UMULO)
14812 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14815 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14817 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14819 if (CondOpcode == ISD::UMULO)
14820 Cond = X86Op.getValue(2);
14822 Cond = X86Op.getValue(1);
14824 CC = DAG.getConstant(X86Cond, MVT::i8);
14828 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14829 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14830 if (CondOpc == ISD::OR) {
14831 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14832 // two branches instead of an explicit OR instruction with a
14834 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14835 isX86LogicalCmp(Cmp)) {
14836 CC = Cond.getOperand(0).getOperand(0);
14837 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14838 Chain, Dest, CC, Cmp);
14839 CC = Cond.getOperand(1).getOperand(0);
14843 } else { // ISD::AND
14844 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14845 // two branches instead of an explicit AND instruction with a
14846 // separate test. However, we only do this if this block doesn't
14847 // have a fall-through edge, because this requires an explicit
14848 // jmp when the condition is false.
14849 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14850 isX86LogicalCmp(Cmp) &&
14851 Op.getNode()->hasOneUse()) {
14852 X86::CondCode CCode =
14853 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14854 CCode = X86::GetOppositeBranchCondition(CCode);
14855 CC = DAG.getConstant(CCode, MVT::i8);
14856 SDNode *User = *Op.getNode()->use_begin();
14857 // Look for an unconditional branch following this conditional branch.
14858 // We need this because we need to reverse the successors in order
14859 // to implement FCMP_OEQ.
14860 if (User->getOpcode() == ISD::BR) {
14861 SDValue FalseBB = User->getOperand(1);
14863 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14864 assert(NewBR == User);
14868 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14869 Chain, Dest, CC, Cmp);
14870 X86::CondCode CCode =
14871 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14872 CCode = X86::GetOppositeBranchCondition(CCode);
14873 CC = DAG.getConstant(CCode, MVT::i8);
14879 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14880 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14881 // It should be transformed during dag combiner except when the condition
14882 // is set by a arithmetics with overflow node.
14883 X86::CondCode CCode =
14884 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14885 CCode = X86::GetOppositeBranchCondition(CCode);
14886 CC = DAG.getConstant(CCode, MVT::i8);
14887 Cond = Cond.getOperand(0).getOperand(1);
14889 } else if (Cond.getOpcode() == ISD::SETCC &&
14890 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14891 // For FCMP_OEQ, we can emit
14892 // two branches instead of an explicit AND instruction with a
14893 // separate test. However, we only do this if this block doesn't
14894 // have a fall-through edge, because this requires an explicit
14895 // jmp when the condition is false.
14896 if (Op.getNode()->hasOneUse()) {
14897 SDNode *User = *Op.getNode()->use_begin();
14898 // Look for an unconditional branch following this conditional branch.
14899 // We need this because we need to reverse the successors in order
14900 // to implement FCMP_OEQ.
14901 if (User->getOpcode() == ISD::BR) {
14902 SDValue FalseBB = User->getOperand(1);
14904 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14905 assert(NewBR == User);
14909 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14910 Cond.getOperand(0), Cond.getOperand(1));
14911 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14912 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14913 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14914 Chain, Dest, CC, Cmp);
14915 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14920 } else if (Cond.getOpcode() == ISD::SETCC &&
14921 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14922 // For FCMP_UNE, we can emit
14923 // two branches instead of an explicit AND instruction with a
14924 // separate test. However, we only do this if this block doesn't
14925 // have a fall-through edge, because this requires an explicit
14926 // jmp when the condition is false.
14927 if (Op.getNode()->hasOneUse()) {
14928 SDNode *User = *Op.getNode()->use_begin();
14929 // Look for an unconditional branch following this conditional branch.
14930 // We need this because we need to reverse the successors in order
14931 // to implement FCMP_UNE.
14932 if (User->getOpcode() == ISD::BR) {
14933 SDValue FalseBB = User->getOperand(1);
14935 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14936 assert(NewBR == User);
14939 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14940 Cond.getOperand(0), Cond.getOperand(1));
14941 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14942 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14943 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14944 Chain, Dest, CC, Cmp);
14945 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14955 // Look pass the truncate if the high bits are known zero.
14956 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14957 Cond = Cond.getOperand(0);
14959 // We know the result of AND is compared against zero. Try to match
14961 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14962 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14963 if (NewSetCC.getNode()) {
14964 CC = NewSetCC.getOperand(0);
14965 Cond = NewSetCC.getOperand(1);
14972 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14973 CC = DAG.getConstant(X86Cond, MVT::i8);
14974 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14976 Cond = ConvertCmpIfNecessary(Cond, DAG);
14977 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14978 Chain, Dest, CC, Cond);
14981 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14982 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14983 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14984 // that the guard pages used by the OS virtual memory manager are allocated in
14985 // correct sequence.
14987 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14988 SelectionDAG &DAG) const {
14989 MachineFunction &MF = DAG.getMachineFunction();
14990 bool SplitStack = MF.shouldSplitStack();
14991 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14997 SDNode* Node = Op.getNode();
14999 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15000 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15001 " not tell us which reg is the stack pointer!");
15002 EVT VT = Node->getValueType(0);
15003 SDValue Tmp1 = SDValue(Node, 0);
15004 SDValue Tmp2 = SDValue(Node, 1);
15005 SDValue Tmp3 = Node->getOperand(2);
15006 SDValue Chain = Tmp1.getOperand(0);
15008 // Chain the dynamic stack allocation so that it doesn't modify the stack
15009 // pointer when other instructions are using the stack.
15010 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15013 SDValue Size = Tmp2.getOperand(1);
15014 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15015 Chain = SP.getValue(1);
15016 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15017 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15018 unsigned StackAlign = TFI.getStackAlignment();
15019 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15020 if (Align > StackAlign)
15021 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15022 DAG.getConstant(-(uint64_t)Align, VT));
15023 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15025 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15026 DAG.getIntPtrConstant(0, true), SDValue(),
15029 SDValue Ops[2] = { Tmp1, Tmp2 };
15030 return DAG.getMergeValues(Ops, dl);
15034 SDValue Chain = Op.getOperand(0);
15035 SDValue Size = Op.getOperand(1);
15036 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15037 EVT VT = Op.getNode()->getValueType(0);
15039 bool Is64Bit = Subtarget->is64Bit();
15040 EVT SPTy = getPointerTy();
15043 MachineRegisterInfo &MRI = MF.getRegInfo();
15046 // The 64 bit implementation of segmented stacks needs to clobber both r10
15047 // r11. This makes it impossible to use it along with nested parameters.
15048 const Function *F = MF.getFunction();
15050 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15052 if (I->hasNestAttr())
15053 report_fatal_error("Cannot use segmented stacks with functions that "
15054 "have nested arguments.");
15057 const TargetRegisterClass *AddrRegClass =
15058 getRegClassFor(getPointerTy());
15059 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15060 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15061 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15062 DAG.getRegister(Vreg, SPTy));
15063 SDValue Ops1[2] = { Value, Chain };
15064 return DAG.getMergeValues(Ops1, dl);
15067 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15069 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15070 Flag = Chain.getValue(1);
15071 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15073 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15075 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15076 DAG.getSubtarget().getRegisterInfo());
15077 unsigned SPReg = RegInfo->getStackRegister();
15078 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15079 Chain = SP.getValue(1);
15082 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15083 DAG.getConstant(-(uint64_t)Align, VT));
15084 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15087 SDValue Ops1[2] = { SP, Chain };
15088 return DAG.getMergeValues(Ops1, dl);
15092 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15093 MachineFunction &MF = DAG.getMachineFunction();
15094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15096 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15099 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15100 // vastart just stores the address of the VarArgsFrameIndex slot into the
15101 // memory location argument.
15102 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15104 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15105 MachinePointerInfo(SV), false, false, 0);
15109 // gp_offset (0 - 6 * 8)
15110 // fp_offset (48 - 48 + 8 * 16)
15111 // overflow_arg_area (point to parameters coming in memory).
15113 SmallVector<SDValue, 8> MemOps;
15114 SDValue FIN = Op.getOperand(1);
15116 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15117 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15119 FIN, MachinePointerInfo(SV), false, false, 0);
15120 MemOps.push_back(Store);
15123 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15124 FIN, DAG.getIntPtrConstant(4));
15125 Store = DAG.getStore(Op.getOperand(0), DL,
15126 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15128 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15129 MemOps.push_back(Store);
15131 // Store ptr to overflow_arg_area
15132 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15133 FIN, DAG.getIntPtrConstant(4));
15134 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15136 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15137 MachinePointerInfo(SV, 8),
15139 MemOps.push_back(Store);
15141 // Store ptr to reg_save_area.
15142 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15143 FIN, DAG.getIntPtrConstant(8));
15144 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15146 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15147 MachinePointerInfo(SV, 16), false, false, 0);
15148 MemOps.push_back(Store);
15149 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15152 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15153 assert(Subtarget->is64Bit() &&
15154 "LowerVAARG only handles 64-bit va_arg!");
15155 assert((Subtarget->isTargetLinux() ||
15156 Subtarget->isTargetDarwin()) &&
15157 "Unhandled target in LowerVAARG");
15158 assert(Op.getNode()->getNumOperands() == 4);
15159 SDValue Chain = Op.getOperand(0);
15160 SDValue SrcPtr = Op.getOperand(1);
15161 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15162 unsigned Align = Op.getConstantOperandVal(3);
15165 EVT ArgVT = Op.getNode()->getValueType(0);
15166 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15167 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15170 // Decide which area this value should be read from.
15171 // TODO: Implement the AMD64 ABI in its entirety. This simple
15172 // selection mechanism works only for the basic types.
15173 if (ArgVT == MVT::f80) {
15174 llvm_unreachable("va_arg for f80 not yet implemented");
15175 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15176 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15177 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15178 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15180 llvm_unreachable("Unhandled argument type in LowerVAARG");
15183 if (ArgMode == 2) {
15184 // Sanity Check: Make sure using fp_offset makes sense.
15185 assert(!DAG.getTarget().Options.UseSoftFloat &&
15186 !(DAG.getMachineFunction()
15187 .getFunction()->getAttributes()
15188 .hasAttribute(AttributeSet::FunctionIndex,
15189 Attribute::NoImplicitFloat)) &&
15190 Subtarget->hasSSE1());
15193 // Insert VAARG_64 node into the DAG
15194 // VAARG_64 returns two values: Variable Argument Address, Chain
15195 SmallVector<SDValue, 11> InstOps;
15196 InstOps.push_back(Chain);
15197 InstOps.push_back(SrcPtr);
15198 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15199 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15200 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15201 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15202 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15203 VTs, InstOps, MVT::i64,
15204 MachinePointerInfo(SV),
15206 /*Volatile=*/false,
15208 /*WriteMem=*/true);
15209 Chain = VAARG.getValue(1);
15211 // Load the next argument and return it
15212 return DAG.getLoad(ArgVT, dl,
15215 MachinePointerInfo(),
15216 false, false, false, 0);
15219 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15220 SelectionDAG &DAG) {
15221 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15222 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15223 SDValue Chain = Op.getOperand(0);
15224 SDValue DstPtr = Op.getOperand(1);
15225 SDValue SrcPtr = Op.getOperand(2);
15226 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15227 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15230 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15231 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15233 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15236 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15237 // amount is a constant. Takes immediate version of shift as input.
15238 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15239 SDValue SrcOp, uint64_t ShiftAmt,
15240 SelectionDAG &DAG) {
15241 MVT ElementType = VT.getVectorElementType();
15243 // Fold this packed shift into its first operand if ShiftAmt is 0.
15247 // Check for ShiftAmt >= element width
15248 if (ShiftAmt >= ElementType.getSizeInBits()) {
15249 if (Opc == X86ISD::VSRAI)
15250 ShiftAmt = ElementType.getSizeInBits() - 1;
15252 return DAG.getConstant(0, VT);
15255 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15256 && "Unknown target vector shift-by-constant node");
15258 // Fold this packed vector shift into a build vector if SrcOp is a
15259 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15260 if (VT == SrcOp.getSimpleValueType() &&
15261 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15262 SmallVector<SDValue, 8> Elts;
15263 unsigned NumElts = SrcOp->getNumOperands();
15264 ConstantSDNode *ND;
15267 default: llvm_unreachable(nullptr);
15268 case X86ISD::VSHLI:
15269 for (unsigned i=0; i!=NumElts; ++i) {
15270 SDValue CurrentOp = SrcOp->getOperand(i);
15271 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15272 Elts.push_back(CurrentOp);
15275 ND = cast<ConstantSDNode>(CurrentOp);
15276 const APInt &C = ND->getAPIntValue();
15277 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15280 case X86ISD::VSRLI:
15281 for (unsigned i=0; i!=NumElts; ++i) {
15282 SDValue CurrentOp = SrcOp->getOperand(i);
15283 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15284 Elts.push_back(CurrentOp);
15287 ND = cast<ConstantSDNode>(CurrentOp);
15288 const APInt &C = ND->getAPIntValue();
15289 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15292 case X86ISD::VSRAI:
15293 for (unsigned i=0; i!=NumElts; ++i) {
15294 SDValue CurrentOp = SrcOp->getOperand(i);
15295 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15296 Elts.push_back(CurrentOp);
15299 ND = cast<ConstantSDNode>(CurrentOp);
15300 const APInt &C = ND->getAPIntValue();
15301 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15306 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15309 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15312 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15313 // may or may not be a constant. Takes immediate version of shift as input.
15314 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15315 SDValue SrcOp, SDValue ShAmt,
15316 SelectionDAG &DAG) {
15317 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15319 // Catch shift-by-constant.
15320 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15321 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15322 CShAmt->getZExtValue(), DAG);
15324 // Change opcode to non-immediate version
15326 default: llvm_unreachable("Unknown target vector shift node");
15327 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15328 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15329 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15332 // Need to build a vector containing shift amount
15333 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15336 ShOps[1] = DAG.getConstant(0, MVT::i32);
15337 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15338 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15340 // The return type has to be a 128-bit type with the same element
15341 // type as the input type.
15342 MVT EltVT = VT.getVectorElementType();
15343 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15345 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15346 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15349 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15350 /// necessary casting for \p Mask when lowering masking intrinsics.
15351 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15352 SDValue PreservedSrc, SelectionDAG &DAG) {
15353 EVT VT = Op.getValueType();
15354 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15355 MVT::i1, VT.getVectorNumElements());
15358 assert(MaskVT.isSimple() && "invalid mask type");
15359 return DAG.getNode(ISD::VSELECT, dl, VT,
15360 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15364 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15366 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15367 case Intrinsic::x86_fma_vfmadd_ps:
15368 case Intrinsic::x86_fma_vfmadd_pd:
15369 case Intrinsic::x86_fma_vfmadd_ps_256:
15370 case Intrinsic::x86_fma_vfmadd_pd_256:
15371 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15372 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15373 return X86ISD::FMADD;
15374 case Intrinsic::x86_fma_vfmsub_ps:
15375 case Intrinsic::x86_fma_vfmsub_pd:
15376 case Intrinsic::x86_fma_vfmsub_ps_256:
15377 case Intrinsic::x86_fma_vfmsub_pd_256:
15378 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15379 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15380 return X86ISD::FMSUB;
15381 case Intrinsic::x86_fma_vfnmadd_ps:
15382 case Intrinsic::x86_fma_vfnmadd_pd:
15383 case Intrinsic::x86_fma_vfnmadd_ps_256:
15384 case Intrinsic::x86_fma_vfnmadd_pd_256:
15385 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15386 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15387 return X86ISD::FNMADD;
15388 case Intrinsic::x86_fma_vfnmsub_ps:
15389 case Intrinsic::x86_fma_vfnmsub_pd:
15390 case Intrinsic::x86_fma_vfnmsub_ps_256:
15391 case Intrinsic::x86_fma_vfnmsub_pd_256:
15392 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15393 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15394 return X86ISD::FNMSUB;
15395 case Intrinsic::x86_fma_vfmaddsub_ps:
15396 case Intrinsic::x86_fma_vfmaddsub_pd:
15397 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15398 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15399 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15400 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15401 return X86ISD::FMADDSUB;
15402 case Intrinsic::x86_fma_vfmsubadd_ps:
15403 case Intrinsic::x86_fma_vfmsubadd_pd:
15404 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15405 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15406 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15407 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15408 return X86ISD::FMSUBADD;
15412 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15414 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15416 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15418 switch(IntrData->Type) {
15419 case INTR_TYPE_1OP:
15420 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15421 case INTR_TYPE_2OP:
15422 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15424 case INTR_TYPE_3OP:
15425 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15426 Op.getOperand(2), Op.getOperand(3));
15427 case COMI: { // Comparison intrinsics
15428 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15429 SDValue LHS = Op.getOperand(1);
15430 SDValue RHS = Op.getOperand(2);
15431 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15432 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15433 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15434 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15435 DAG.getConstant(X86CC, MVT::i8), Cond);
15436 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15439 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15440 Op.getOperand(1), Op.getOperand(2), DAG);
15447 default: return SDValue(); // Don't custom lower most intrinsics.
15449 // Arithmetic intrinsics.
15450 case Intrinsic::x86_sse2_pmulu_dq:
15451 case Intrinsic::x86_avx2_pmulu_dq:
15452 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15453 Op.getOperand(1), Op.getOperand(2));
15455 case Intrinsic::x86_sse41_pmuldq:
15456 case Intrinsic::x86_avx2_pmul_dq:
15457 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15458 Op.getOperand(1), Op.getOperand(2));
15460 case Intrinsic::x86_sse2_pmulhu_w:
15461 case Intrinsic::x86_avx2_pmulhu_w:
15462 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15463 Op.getOperand(1), Op.getOperand(2));
15465 case Intrinsic::x86_sse2_pmulh_w:
15466 case Intrinsic::x86_avx2_pmulh_w:
15467 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15468 Op.getOperand(1), Op.getOperand(2));
15470 // SSE/SSE2/AVX floating point max/min intrinsics.
15471 case Intrinsic::x86_sse_max_ps:
15472 case Intrinsic::x86_sse2_max_pd:
15473 case Intrinsic::x86_avx_max_ps_256:
15474 case Intrinsic::x86_avx_max_pd_256:
15475 case Intrinsic::x86_sse_min_ps:
15476 case Intrinsic::x86_sse2_min_pd:
15477 case Intrinsic::x86_avx_min_ps_256:
15478 case Intrinsic::x86_avx_min_pd_256: {
15481 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15482 case Intrinsic::x86_sse_max_ps:
15483 case Intrinsic::x86_sse2_max_pd:
15484 case Intrinsic::x86_avx_max_ps_256:
15485 case Intrinsic::x86_avx_max_pd_256:
15486 Opcode = X86ISD::FMAX;
15488 case Intrinsic::x86_sse_min_ps:
15489 case Intrinsic::x86_sse2_min_pd:
15490 case Intrinsic::x86_avx_min_ps_256:
15491 case Intrinsic::x86_avx_min_pd_256:
15492 Opcode = X86ISD::FMIN;
15495 return DAG.getNode(Opcode, dl, Op.getValueType(),
15496 Op.getOperand(1), Op.getOperand(2));
15499 // AVX2 variable shift intrinsics
15500 case Intrinsic::x86_avx2_psllv_d:
15501 case Intrinsic::x86_avx2_psllv_q:
15502 case Intrinsic::x86_avx2_psllv_d_256:
15503 case Intrinsic::x86_avx2_psllv_q_256:
15504 case Intrinsic::x86_avx2_psrlv_d:
15505 case Intrinsic::x86_avx2_psrlv_q:
15506 case Intrinsic::x86_avx2_psrlv_d_256:
15507 case Intrinsic::x86_avx2_psrlv_q_256:
15508 case Intrinsic::x86_avx2_psrav_d:
15509 case Intrinsic::x86_avx2_psrav_d_256: {
15512 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15513 case Intrinsic::x86_avx2_psllv_d:
15514 case Intrinsic::x86_avx2_psllv_q:
15515 case Intrinsic::x86_avx2_psllv_d_256:
15516 case Intrinsic::x86_avx2_psllv_q_256:
15519 case Intrinsic::x86_avx2_psrlv_d:
15520 case Intrinsic::x86_avx2_psrlv_q:
15521 case Intrinsic::x86_avx2_psrlv_d_256:
15522 case Intrinsic::x86_avx2_psrlv_q_256:
15525 case Intrinsic::x86_avx2_psrav_d:
15526 case Intrinsic::x86_avx2_psrav_d_256:
15530 return DAG.getNode(Opcode, dl, Op.getValueType(),
15531 Op.getOperand(1), Op.getOperand(2));
15534 case Intrinsic::x86_sse2_packssdw_128:
15535 case Intrinsic::x86_sse2_packsswb_128:
15536 case Intrinsic::x86_avx2_packssdw:
15537 case Intrinsic::x86_avx2_packsswb:
15538 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15539 Op.getOperand(1), Op.getOperand(2));
15541 case Intrinsic::x86_sse2_packuswb_128:
15542 case Intrinsic::x86_sse41_packusdw:
15543 case Intrinsic::x86_avx2_packuswb:
15544 case Intrinsic::x86_avx2_packusdw:
15545 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15546 Op.getOperand(1), Op.getOperand(2));
15548 case Intrinsic::x86_ssse3_pshuf_b_128:
15549 case Intrinsic::x86_avx2_pshuf_b:
15550 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15551 Op.getOperand(1), Op.getOperand(2));
15553 case Intrinsic::x86_sse2_pshuf_d:
15554 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15555 Op.getOperand(1), Op.getOperand(2));
15557 case Intrinsic::x86_sse2_pshufl_w:
15558 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15559 Op.getOperand(1), Op.getOperand(2));
15561 case Intrinsic::x86_sse2_pshufh_w:
15562 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15563 Op.getOperand(1), Op.getOperand(2));
15565 case Intrinsic::x86_ssse3_psign_b_128:
15566 case Intrinsic::x86_ssse3_psign_w_128:
15567 case Intrinsic::x86_ssse3_psign_d_128:
15568 case Intrinsic::x86_avx2_psign_b:
15569 case Intrinsic::x86_avx2_psign_w:
15570 case Intrinsic::x86_avx2_psign_d:
15571 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15572 Op.getOperand(1), Op.getOperand(2));
15574 case Intrinsic::x86_avx2_permd:
15575 case Intrinsic::x86_avx2_permps:
15576 // Operands intentionally swapped. Mask is last operand to intrinsic,
15577 // but second operand for node/instruction.
15578 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15579 Op.getOperand(2), Op.getOperand(1));
15581 case Intrinsic::x86_avx512_mask_valign_q_512:
15582 case Intrinsic::x86_avx512_mask_valign_d_512:
15583 // Vector source operands are swapped.
15584 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15585 Op.getValueType(), Op.getOperand(2),
15588 Op.getOperand(5), Op.getOperand(4), DAG);
15590 // ptest and testp intrinsics. The intrinsic these come from are designed to
15591 // return an integer value, not just an instruction so lower it to the ptest
15592 // or testp pattern and a setcc for the result.
15593 case Intrinsic::x86_sse41_ptestz:
15594 case Intrinsic::x86_sse41_ptestc:
15595 case Intrinsic::x86_sse41_ptestnzc:
15596 case Intrinsic::x86_avx_ptestz_256:
15597 case Intrinsic::x86_avx_ptestc_256:
15598 case Intrinsic::x86_avx_ptestnzc_256:
15599 case Intrinsic::x86_avx_vtestz_ps:
15600 case Intrinsic::x86_avx_vtestc_ps:
15601 case Intrinsic::x86_avx_vtestnzc_ps:
15602 case Intrinsic::x86_avx_vtestz_pd:
15603 case Intrinsic::x86_avx_vtestc_pd:
15604 case Intrinsic::x86_avx_vtestnzc_pd:
15605 case Intrinsic::x86_avx_vtestz_ps_256:
15606 case Intrinsic::x86_avx_vtestc_ps_256:
15607 case Intrinsic::x86_avx_vtestnzc_ps_256:
15608 case Intrinsic::x86_avx_vtestz_pd_256:
15609 case Intrinsic::x86_avx_vtestc_pd_256:
15610 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15611 bool IsTestPacked = false;
15614 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15615 case Intrinsic::x86_avx_vtestz_ps:
15616 case Intrinsic::x86_avx_vtestz_pd:
15617 case Intrinsic::x86_avx_vtestz_ps_256:
15618 case Intrinsic::x86_avx_vtestz_pd_256:
15619 IsTestPacked = true; // Fallthrough
15620 case Intrinsic::x86_sse41_ptestz:
15621 case Intrinsic::x86_avx_ptestz_256:
15623 X86CC = X86::COND_E;
15625 case Intrinsic::x86_avx_vtestc_ps:
15626 case Intrinsic::x86_avx_vtestc_pd:
15627 case Intrinsic::x86_avx_vtestc_ps_256:
15628 case Intrinsic::x86_avx_vtestc_pd_256:
15629 IsTestPacked = true; // Fallthrough
15630 case Intrinsic::x86_sse41_ptestc:
15631 case Intrinsic::x86_avx_ptestc_256:
15633 X86CC = X86::COND_B;
15635 case Intrinsic::x86_avx_vtestnzc_ps:
15636 case Intrinsic::x86_avx_vtestnzc_pd:
15637 case Intrinsic::x86_avx_vtestnzc_ps_256:
15638 case Intrinsic::x86_avx_vtestnzc_pd_256:
15639 IsTestPacked = true; // Fallthrough
15640 case Intrinsic::x86_sse41_ptestnzc:
15641 case Intrinsic::x86_avx_ptestnzc_256:
15643 X86CC = X86::COND_A;
15647 SDValue LHS = Op.getOperand(1);
15648 SDValue RHS = Op.getOperand(2);
15649 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15650 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15651 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15652 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15653 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15655 case Intrinsic::x86_avx512_kortestz_w:
15656 case Intrinsic::x86_avx512_kortestc_w: {
15657 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15658 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15659 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15660 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15661 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15662 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15663 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15666 case Intrinsic::x86_sse42_pcmpistria128:
15667 case Intrinsic::x86_sse42_pcmpestria128:
15668 case Intrinsic::x86_sse42_pcmpistric128:
15669 case Intrinsic::x86_sse42_pcmpestric128:
15670 case Intrinsic::x86_sse42_pcmpistrio128:
15671 case Intrinsic::x86_sse42_pcmpestrio128:
15672 case Intrinsic::x86_sse42_pcmpistris128:
15673 case Intrinsic::x86_sse42_pcmpestris128:
15674 case Intrinsic::x86_sse42_pcmpistriz128:
15675 case Intrinsic::x86_sse42_pcmpestriz128: {
15679 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15680 case Intrinsic::x86_sse42_pcmpistria128:
15681 Opcode = X86ISD::PCMPISTRI;
15682 X86CC = X86::COND_A;
15684 case Intrinsic::x86_sse42_pcmpestria128:
15685 Opcode = X86ISD::PCMPESTRI;
15686 X86CC = X86::COND_A;
15688 case Intrinsic::x86_sse42_pcmpistric128:
15689 Opcode = X86ISD::PCMPISTRI;
15690 X86CC = X86::COND_B;
15692 case Intrinsic::x86_sse42_pcmpestric128:
15693 Opcode = X86ISD::PCMPESTRI;
15694 X86CC = X86::COND_B;
15696 case Intrinsic::x86_sse42_pcmpistrio128:
15697 Opcode = X86ISD::PCMPISTRI;
15698 X86CC = X86::COND_O;
15700 case Intrinsic::x86_sse42_pcmpestrio128:
15701 Opcode = X86ISD::PCMPESTRI;
15702 X86CC = X86::COND_O;
15704 case Intrinsic::x86_sse42_pcmpistris128:
15705 Opcode = X86ISD::PCMPISTRI;
15706 X86CC = X86::COND_S;
15708 case Intrinsic::x86_sse42_pcmpestris128:
15709 Opcode = X86ISD::PCMPESTRI;
15710 X86CC = X86::COND_S;
15712 case Intrinsic::x86_sse42_pcmpistriz128:
15713 Opcode = X86ISD::PCMPISTRI;
15714 X86CC = X86::COND_E;
15716 case Intrinsic::x86_sse42_pcmpestriz128:
15717 Opcode = X86ISD::PCMPESTRI;
15718 X86CC = X86::COND_E;
15721 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15722 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15723 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15724 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15725 DAG.getConstant(X86CC, MVT::i8),
15726 SDValue(PCMP.getNode(), 1));
15727 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15730 case Intrinsic::x86_sse42_pcmpistri128:
15731 case Intrinsic::x86_sse42_pcmpestri128: {
15733 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15734 Opcode = X86ISD::PCMPISTRI;
15736 Opcode = X86ISD::PCMPESTRI;
15738 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15739 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15740 return DAG.getNode(Opcode, dl, VTs, NewOps);
15743 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15744 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15745 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15746 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15747 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15748 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15749 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15750 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15751 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15752 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15753 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15754 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15755 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15756 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15757 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15758 dl, Op.getValueType(),
15762 Op.getOperand(4), Op.getOperand(1), DAG);
15767 case Intrinsic::x86_fma_vfmadd_ps:
15768 case Intrinsic::x86_fma_vfmadd_pd:
15769 case Intrinsic::x86_fma_vfmsub_ps:
15770 case Intrinsic::x86_fma_vfmsub_pd:
15771 case Intrinsic::x86_fma_vfnmadd_ps:
15772 case Intrinsic::x86_fma_vfnmadd_pd:
15773 case Intrinsic::x86_fma_vfnmsub_ps:
15774 case Intrinsic::x86_fma_vfnmsub_pd:
15775 case Intrinsic::x86_fma_vfmaddsub_ps:
15776 case Intrinsic::x86_fma_vfmaddsub_pd:
15777 case Intrinsic::x86_fma_vfmsubadd_ps:
15778 case Intrinsic::x86_fma_vfmsubadd_pd:
15779 case Intrinsic::x86_fma_vfmadd_ps_256:
15780 case Intrinsic::x86_fma_vfmadd_pd_256:
15781 case Intrinsic::x86_fma_vfmsub_ps_256:
15782 case Intrinsic::x86_fma_vfmsub_pd_256:
15783 case Intrinsic::x86_fma_vfnmadd_ps_256:
15784 case Intrinsic::x86_fma_vfnmadd_pd_256:
15785 case Intrinsic::x86_fma_vfnmsub_ps_256:
15786 case Intrinsic::x86_fma_vfnmsub_pd_256:
15787 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15788 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15789 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15790 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15791 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15792 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15796 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15797 SDValue Src, SDValue Mask, SDValue Base,
15798 SDValue Index, SDValue ScaleOp, SDValue Chain,
15799 const X86Subtarget * Subtarget) {
15801 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15802 assert(C && "Invalid scale type");
15803 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15804 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15805 Index.getSimpleValueType().getVectorNumElements());
15807 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15809 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15811 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15812 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15813 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15814 SDValue Segment = DAG.getRegister(0, MVT::i32);
15815 if (Src.getOpcode() == ISD::UNDEF)
15816 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15817 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15818 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15819 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15820 return DAG.getMergeValues(RetOps, dl);
15823 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15824 SDValue Src, SDValue Mask, SDValue Base,
15825 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15827 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15828 assert(C && "Invalid scale type");
15829 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15830 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15831 SDValue Segment = DAG.getRegister(0, MVT::i32);
15832 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15833 Index.getSimpleValueType().getVectorNumElements());
15835 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15837 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15839 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15840 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15841 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15842 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15843 return SDValue(Res, 1);
15846 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15847 SDValue Mask, SDValue Base, SDValue Index,
15848 SDValue ScaleOp, SDValue Chain) {
15850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15851 assert(C && "Invalid scale type");
15852 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15853 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15854 SDValue Segment = DAG.getRegister(0, MVT::i32);
15856 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15858 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15860 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15862 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15863 //SDVTList VTs = DAG.getVTList(MVT::Other);
15864 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15865 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15866 return SDValue(Res, 0);
15869 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15870 // read performance monitor counters (x86_rdpmc).
15871 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15872 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15873 SmallVectorImpl<SDValue> &Results) {
15874 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15875 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15878 // The ECX register is used to select the index of the performance counter
15880 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15882 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15884 // Reads the content of a 64-bit performance counter and returns it in the
15885 // registers EDX:EAX.
15886 if (Subtarget->is64Bit()) {
15887 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15888 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15891 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15892 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15895 Chain = HI.getValue(1);
15897 if (Subtarget->is64Bit()) {
15898 // The EAX register is loaded with the low-order 32 bits. The EDX register
15899 // is loaded with the supported high-order bits of the counter.
15900 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15901 DAG.getConstant(32, MVT::i8));
15902 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15903 Results.push_back(Chain);
15907 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15908 SDValue Ops[] = { LO, HI };
15909 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15910 Results.push_back(Pair);
15911 Results.push_back(Chain);
15914 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15915 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15916 // also used to custom lower READCYCLECOUNTER nodes.
15917 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15918 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15919 SmallVectorImpl<SDValue> &Results) {
15920 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15921 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15924 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15925 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15926 // and the EAX register is loaded with the low-order 32 bits.
15927 if (Subtarget->is64Bit()) {
15928 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15929 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15932 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15933 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15936 SDValue Chain = HI.getValue(1);
15938 if (Opcode == X86ISD::RDTSCP_DAG) {
15939 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15941 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15942 // the ECX register. Add 'ecx' explicitly to the chain.
15943 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15945 // Explicitly store the content of ECX at the location passed in input
15946 // to the 'rdtscp' intrinsic.
15947 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15948 MachinePointerInfo(), false, false, 0);
15951 if (Subtarget->is64Bit()) {
15952 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15953 // the EAX register is loaded with the low-order 32 bits.
15954 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15955 DAG.getConstant(32, MVT::i8));
15956 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15957 Results.push_back(Chain);
15961 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15962 SDValue Ops[] = { LO, HI };
15963 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15964 Results.push_back(Pair);
15965 Results.push_back(Chain);
15968 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15969 SelectionDAG &DAG) {
15970 SmallVector<SDValue, 2> Results;
15972 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15974 return DAG.getMergeValues(Results, DL);
15978 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15979 SelectionDAG &DAG) {
15980 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15982 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15987 switch(IntrData->Type) {
15989 llvm_unreachable("Unknown Intrinsic Type");
15993 // Emit the node with the right value type.
15994 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15995 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15997 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15998 // Otherwise return the value from Rand, which is always 0, casted to i32.
15999 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16000 DAG.getConstant(1, Op->getValueType(1)),
16001 DAG.getConstant(X86::COND_B, MVT::i32),
16002 SDValue(Result.getNode(), 1) };
16003 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16004 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16007 // Return { result, isValid, chain }.
16008 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16009 SDValue(Result.getNode(), 2));
16012 //gather(v1, mask, index, base, scale);
16013 SDValue Chain = Op.getOperand(0);
16014 SDValue Src = Op.getOperand(2);
16015 SDValue Base = Op.getOperand(3);
16016 SDValue Index = Op.getOperand(4);
16017 SDValue Mask = Op.getOperand(5);
16018 SDValue Scale = Op.getOperand(6);
16019 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16023 //scatter(base, mask, index, v1, scale);
16024 SDValue Chain = Op.getOperand(0);
16025 SDValue Base = Op.getOperand(2);
16026 SDValue Mask = Op.getOperand(3);
16027 SDValue Index = Op.getOperand(4);
16028 SDValue Src = Op.getOperand(5);
16029 SDValue Scale = Op.getOperand(6);
16030 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16033 SDValue Hint = Op.getOperand(6);
16035 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16036 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16037 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16038 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16039 SDValue Chain = Op.getOperand(0);
16040 SDValue Mask = Op.getOperand(2);
16041 SDValue Index = Op.getOperand(3);
16042 SDValue Base = Op.getOperand(4);
16043 SDValue Scale = Op.getOperand(5);
16044 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16046 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16048 SmallVector<SDValue, 2> Results;
16049 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16050 return DAG.getMergeValues(Results, dl);
16052 // Read Performance Monitoring Counters.
16054 SmallVector<SDValue, 2> Results;
16055 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16056 return DAG.getMergeValues(Results, dl);
16058 // XTEST intrinsics.
16060 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16061 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16062 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16063 DAG.getConstant(X86::COND_NE, MVT::i8),
16065 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16066 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16067 Ret, SDValue(InTrans.getNode(), 1));
16071 SmallVector<SDValue, 2> Results;
16072 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16073 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16074 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16075 DAG.getConstant(-1, MVT::i8));
16076 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16077 Op.getOperand(4), GenCF.getValue(1));
16078 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16079 Op.getOperand(5), MachinePointerInfo(),
16081 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16082 DAG.getConstant(X86::COND_B, MVT::i8),
16084 Results.push_back(SetCC);
16085 Results.push_back(Store);
16086 return DAG.getMergeValues(Results, dl);
16091 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16092 SelectionDAG &DAG) const {
16093 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16094 MFI->setReturnAddressIsTaken(true);
16096 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16099 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16101 EVT PtrVT = getPointerTy();
16104 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16105 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16106 DAG.getSubtarget().getRegisterInfo());
16107 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16108 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16109 DAG.getNode(ISD::ADD, dl, PtrVT,
16110 FrameAddr, Offset),
16111 MachinePointerInfo(), false, false, false, 0);
16114 // Just load the return address.
16115 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16116 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16117 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16120 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16121 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16122 MFI->setFrameAddressIsTaken(true);
16124 EVT VT = Op.getValueType();
16125 SDLoc dl(Op); // FIXME probably not meaningful
16126 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16127 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16128 DAG.getSubtarget().getRegisterInfo());
16129 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16130 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16131 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16132 "Invalid Frame Register!");
16133 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16135 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16136 MachinePointerInfo(),
16137 false, false, false, 0);
16141 // FIXME? Maybe this could be a TableGen attribute on some registers and
16142 // this table could be generated automatically from RegInfo.
16143 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16145 unsigned Reg = StringSwitch<unsigned>(RegName)
16146 .Case("esp", X86::ESP)
16147 .Case("rsp", X86::RSP)
16151 report_fatal_error("Invalid register name global variable");
16154 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16155 SelectionDAG &DAG) const {
16156 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16157 DAG.getSubtarget().getRegisterInfo());
16158 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16161 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16162 SDValue Chain = Op.getOperand(0);
16163 SDValue Offset = Op.getOperand(1);
16164 SDValue Handler = Op.getOperand(2);
16167 EVT PtrVT = getPointerTy();
16168 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16169 DAG.getSubtarget().getRegisterInfo());
16170 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16171 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16172 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16173 "Invalid Frame Register!");
16174 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16175 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16177 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16178 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16179 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16180 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16182 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16184 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16185 DAG.getRegister(StoreAddrReg, PtrVT));
16188 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16189 SelectionDAG &DAG) const {
16191 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16192 DAG.getVTList(MVT::i32, MVT::Other),
16193 Op.getOperand(0), Op.getOperand(1));
16196 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16197 SelectionDAG &DAG) const {
16199 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16200 Op.getOperand(0), Op.getOperand(1));
16203 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16204 return Op.getOperand(0);
16207 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16208 SelectionDAG &DAG) const {
16209 SDValue Root = Op.getOperand(0);
16210 SDValue Trmp = Op.getOperand(1); // trampoline
16211 SDValue FPtr = Op.getOperand(2); // nested function
16212 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16215 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16216 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16218 if (Subtarget->is64Bit()) {
16219 SDValue OutChains[6];
16221 // Large code-model.
16222 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16223 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16225 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16226 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16228 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16230 // Load the pointer to the nested function into R11.
16231 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16232 SDValue Addr = Trmp;
16233 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16234 Addr, MachinePointerInfo(TrmpAddr),
16237 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16238 DAG.getConstant(2, MVT::i64));
16239 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16240 MachinePointerInfo(TrmpAddr, 2),
16243 // Load the 'nest' parameter value into R10.
16244 // R10 is specified in X86CallingConv.td
16245 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16246 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16247 DAG.getConstant(10, MVT::i64));
16248 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16249 Addr, MachinePointerInfo(TrmpAddr, 10),
16252 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16253 DAG.getConstant(12, MVT::i64));
16254 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16255 MachinePointerInfo(TrmpAddr, 12),
16258 // Jump to the nested function.
16259 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16260 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16261 DAG.getConstant(20, MVT::i64));
16262 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16263 Addr, MachinePointerInfo(TrmpAddr, 20),
16266 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16267 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16268 DAG.getConstant(22, MVT::i64));
16269 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16270 MachinePointerInfo(TrmpAddr, 22),
16273 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16275 const Function *Func =
16276 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16277 CallingConv::ID CC = Func->getCallingConv();
16282 llvm_unreachable("Unsupported calling convention");
16283 case CallingConv::C:
16284 case CallingConv::X86_StdCall: {
16285 // Pass 'nest' parameter in ECX.
16286 // Must be kept in sync with X86CallingConv.td
16287 NestReg = X86::ECX;
16289 // Check that ECX wasn't needed by an 'inreg' parameter.
16290 FunctionType *FTy = Func->getFunctionType();
16291 const AttributeSet &Attrs = Func->getAttributes();
16293 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16294 unsigned InRegCount = 0;
16297 for (FunctionType::param_iterator I = FTy->param_begin(),
16298 E = FTy->param_end(); I != E; ++I, ++Idx)
16299 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16300 // FIXME: should only count parameters that are lowered to integers.
16301 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16303 if (InRegCount > 2) {
16304 report_fatal_error("Nest register in use - reduce number of inreg"
16310 case CallingConv::X86_FastCall:
16311 case CallingConv::X86_ThisCall:
16312 case CallingConv::Fast:
16313 // Pass 'nest' parameter in EAX.
16314 // Must be kept in sync with X86CallingConv.td
16315 NestReg = X86::EAX;
16319 SDValue OutChains[4];
16320 SDValue Addr, Disp;
16322 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16323 DAG.getConstant(10, MVT::i32));
16324 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16326 // This is storing the opcode for MOV32ri.
16327 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16328 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16329 OutChains[0] = DAG.getStore(Root, dl,
16330 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16331 Trmp, MachinePointerInfo(TrmpAddr),
16334 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16335 DAG.getConstant(1, MVT::i32));
16336 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16337 MachinePointerInfo(TrmpAddr, 1),
16340 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16341 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16342 DAG.getConstant(5, MVT::i32));
16343 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16344 MachinePointerInfo(TrmpAddr, 5),
16347 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16348 DAG.getConstant(6, MVT::i32));
16349 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16350 MachinePointerInfo(TrmpAddr, 6),
16353 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16357 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16358 SelectionDAG &DAG) const {
16360 The rounding mode is in bits 11:10 of FPSR, and has the following
16362 00 Round to nearest
16367 FLT_ROUNDS, on the other hand, expects the following:
16374 To perform the conversion, we do:
16375 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16378 MachineFunction &MF = DAG.getMachineFunction();
16379 const TargetMachine &TM = MF.getTarget();
16380 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16381 unsigned StackAlignment = TFI.getStackAlignment();
16382 MVT VT = Op.getSimpleValueType();
16385 // Save FP Control Word to stack slot
16386 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16387 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16389 MachineMemOperand *MMO =
16390 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16391 MachineMemOperand::MOStore, 2, 2);
16393 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16394 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16395 DAG.getVTList(MVT::Other),
16396 Ops, MVT::i16, MMO);
16398 // Load FP Control Word from stack slot
16399 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16400 MachinePointerInfo(), false, false, false, 0);
16402 // Transform as necessary
16404 DAG.getNode(ISD::SRL, DL, MVT::i16,
16405 DAG.getNode(ISD::AND, DL, MVT::i16,
16406 CWD, DAG.getConstant(0x800, MVT::i16)),
16407 DAG.getConstant(11, MVT::i8));
16409 DAG.getNode(ISD::SRL, DL, MVT::i16,
16410 DAG.getNode(ISD::AND, DL, MVT::i16,
16411 CWD, DAG.getConstant(0x400, MVT::i16)),
16412 DAG.getConstant(9, MVT::i8));
16415 DAG.getNode(ISD::AND, DL, MVT::i16,
16416 DAG.getNode(ISD::ADD, DL, MVT::i16,
16417 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16418 DAG.getConstant(1, MVT::i16)),
16419 DAG.getConstant(3, MVT::i16));
16421 return DAG.getNode((VT.getSizeInBits() < 16 ?
16422 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16425 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16426 MVT VT = Op.getSimpleValueType();
16428 unsigned NumBits = VT.getSizeInBits();
16431 Op = Op.getOperand(0);
16432 if (VT == MVT::i8) {
16433 // Zero extend to i32 since there is not an i8 bsr.
16435 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16438 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16439 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16440 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16442 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16445 DAG.getConstant(NumBits+NumBits-1, OpVT),
16446 DAG.getConstant(X86::COND_E, MVT::i8),
16449 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16451 // Finally xor with NumBits-1.
16452 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16455 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16459 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16460 MVT VT = Op.getSimpleValueType();
16462 unsigned NumBits = VT.getSizeInBits();
16465 Op = Op.getOperand(0);
16466 if (VT == MVT::i8) {
16467 // Zero extend to i32 since there is not an i8 bsr.
16469 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16472 // Issue a bsr (scan bits in reverse).
16473 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16474 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16476 // And xor with NumBits-1.
16477 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16480 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16484 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16485 MVT VT = Op.getSimpleValueType();
16486 unsigned NumBits = VT.getSizeInBits();
16488 Op = Op.getOperand(0);
16490 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16491 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16492 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16494 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16497 DAG.getConstant(NumBits, VT),
16498 DAG.getConstant(X86::COND_E, MVT::i8),
16501 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16504 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16505 // ones, and then concatenate the result back.
16506 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16507 MVT VT = Op.getSimpleValueType();
16509 assert(VT.is256BitVector() && VT.isInteger() &&
16510 "Unsupported value type for operation");
16512 unsigned NumElems = VT.getVectorNumElements();
16515 // Extract the LHS vectors
16516 SDValue LHS = Op.getOperand(0);
16517 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16518 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16520 // Extract the RHS vectors
16521 SDValue RHS = Op.getOperand(1);
16522 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16523 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16525 MVT EltVT = VT.getVectorElementType();
16526 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16528 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16529 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16530 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16533 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16534 assert(Op.getSimpleValueType().is256BitVector() &&
16535 Op.getSimpleValueType().isInteger() &&
16536 "Only handle AVX 256-bit vector integer operation");
16537 return Lower256IntArith(Op, DAG);
16540 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16541 assert(Op.getSimpleValueType().is256BitVector() &&
16542 Op.getSimpleValueType().isInteger() &&
16543 "Only handle AVX 256-bit vector integer operation");
16544 return Lower256IntArith(Op, DAG);
16547 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16548 SelectionDAG &DAG) {
16550 MVT VT = Op.getSimpleValueType();
16552 // Decompose 256-bit ops into smaller 128-bit ops.
16553 if (VT.is256BitVector() && !Subtarget->hasInt256())
16554 return Lower256IntArith(Op, DAG);
16556 SDValue A = Op.getOperand(0);
16557 SDValue B = Op.getOperand(1);
16559 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16560 if (VT == MVT::v4i32) {
16561 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16562 "Should not custom lower when pmuldq is available!");
16564 // Extract the odd parts.
16565 static const int UnpackMask[] = { 1, -1, 3, -1 };
16566 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16567 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16569 // Multiply the even parts.
16570 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16571 // Now multiply odd parts.
16572 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16574 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16575 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16577 // Merge the two vectors back together with a shuffle. This expands into 2
16579 static const int ShufMask[] = { 0, 4, 2, 6 };
16580 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16583 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16584 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16586 // Ahi = psrlqi(a, 32);
16587 // Bhi = psrlqi(b, 32);
16589 // AloBlo = pmuludq(a, b);
16590 // AloBhi = pmuludq(a, Bhi);
16591 // AhiBlo = pmuludq(Ahi, b);
16593 // AloBhi = psllqi(AloBhi, 32);
16594 // AhiBlo = psllqi(AhiBlo, 32);
16595 // return AloBlo + AloBhi + AhiBlo;
16597 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16598 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16600 // Bit cast to 32-bit vectors for MULUDQ
16601 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16602 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16603 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16604 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16605 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16606 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16608 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16609 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16610 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16612 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16613 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16615 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16616 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16619 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16620 assert(Subtarget->isTargetWin64() && "Unexpected target");
16621 EVT VT = Op.getValueType();
16622 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16623 "Unexpected return type for lowering");
16627 switch (Op->getOpcode()) {
16628 default: llvm_unreachable("Unexpected request for libcall!");
16629 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16630 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16631 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16632 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16633 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16634 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16638 SDValue InChain = DAG.getEntryNode();
16640 TargetLowering::ArgListTy Args;
16641 TargetLowering::ArgListEntry Entry;
16642 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16643 EVT ArgVT = Op->getOperand(i).getValueType();
16644 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16645 "Unexpected argument type for lowering");
16646 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16647 Entry.Node = StackPtr;
16648 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16650 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16651 Entry.Ty = PointerType::get(ArgTy,0);
16652 Entry.isSExt = false;
16653 Entry.isZExt = false;
16654 Args.push_back(Entry);
16657 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16660 TargetLowering::CallLoweringInfo CLI(DAG);
16661 CLI.setDebugLoc(dl).setChain(InChain)
16662 .setCallee(getLibcallCallingConv(LC),
16663 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16664 Callee, std::move(Args), 0)
16665 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16667 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16668 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16671 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16672 SelectionDAG &DAG) {
16673 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16674 EVT VT = Op0.getValueType();
16677 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16678 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16680 // PMULxD operations multiply each even value (starting at 0) of LHS with
16681 // the related value of RHS and produce a widen result.
16682 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16683 // => <2 x i64> <ae|cg>
16685 // In other word, to have all the results, we need to perform two PMULxD:
16686 // 1. one with the even values.
16687 // 2. one with the odd values.
16688 // To achieve #2, with need to place the odd values at an even position.
16690 // Place the odd value at an even position (basically, shift all values 1
16691 // step to the left):
16692 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16693 // <a|b|c|d> => <b|undef|d|undef>
16694 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16695 // <e|f|g|h> => <f|undef|h|undef>
16696 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16698 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16700 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16701 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16703 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16704 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16705 // => <2 x i64> <ae|cg>
16706 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16707 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16708 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16709 // => <2 x i64> <bf|dh>
16710 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16711 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16713 // Shuffle it back into the right order.
16714 SDValue Highs, Lows;
16715 if (VT == MVT::v8i32) {
16716 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16717 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16718 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16719 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16721 const int HighMask[] = {1, 5, 3, 7};
16722 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16723 const int LowMask[] = {0, 4, 2, 6};
16724 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16727 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16728 // unsigned multiply.
16729 if (IsSigned && !Subtarget->hasSSE41()) {
16731 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16732 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16733 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16734 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16735 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16737 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16738 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16741 // The first result of MUL_LOHI is actually the low value, followed by the
16743 SDValue Ops[] = {Lows, Highs};
16744 return DAG.getMergeValues(Ops, dl);
16747 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16748 const X86Subtarget *Subtarget) {
16749 MVT VT = Op.getSimpleValueType();
16751 SDValue R = Op.getOperand(0);
16752 SDValue Amt = Op.getOperand(1);
16754 // Optimize shl/srl/sra with constant shift amount.
16755 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16756 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16757 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16759 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16760 (Subtarget->hasInt256() &&
16761 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16762 (Subtarget->hasAVX512() &&
16763 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16764 if (Op.getOpcode() == ISD::SHL)
16765 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16767 if (Op.getOpcode() == ISD::SRL)
16768 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16770 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16771 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16775 if (VT == MVT::v16i8) {
16776 if (Op.getOpcode() == ISD::SHL) {
16777 // Make a large shift.
16778 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16779 MVT::v8i16, R, ShiftAmt,
16781 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16782 // Zero out the rightmost bits.
16783 SmallVector<SDValue, 16> V(16,
16784 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16786 return DAG.getNode(ISD::AND, dl, VT, SHL,
16787 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16789 if (Op.getOpcode() == ISD::SRL) {
16790 // Make a large shift.
16791 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16792 MVT::v8i16, R, ShiftAmt,
16794 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16795 // Zero out the leftmost bits.
16796 SmallVector<SDValue, 16> V(16,
16797 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16799 return DAG.getNode(ISD::AND, dl, VT, SRL,
16800 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16802 if (Op.getOpcode() == ISD::SRA) {
16803 if (ShiftAmt == 7) {
16804 // R s>> 7 === R s< 0
16805 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16806 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16809 // R s>> a === ((R u>> a) ^ m) - m
16810 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16811 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16813 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16814 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16815 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16818 llvm_unreachable("Unknown shift opcode.");
16821 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16822 if (Op.getOpcode() == ISD::SHL) {
16823 // Make a large shift.
16824 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16825 MVT::v16i16, R, ShiftAmt,
16827 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16828 // Zero out the rightmost bits.
16829 SmallVector<SDValue, 32> V(32,
16830 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16832 return DAG.getNode(ISD::AND, dl, VT, SHL,
16833 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16835 if (Op.getOpcode() == ISD::SRL) {
16836 // Make a large shift.
16837 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16838 MVT::v16i16, R, ShiftAmt,
16840 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16841 // Zero out the leftmost bits.
16842 SmallVector<SDValue, 32> V(32,
16843 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16845 return DAG.getNode(ISD::AND, dl, VT, SRL,
16846 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16848 if (Op.getOpcode() == ISD::SRA) {
16849 if (ShiftAmt == 7) {
16850 // R s>> 7 === R s< 0
16851 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16852 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16855 // R s>> a === ((R u>> a) ^ m) - m
16856 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16857 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16859 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16860 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16861 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16864 llvm_unreachable("Unknown shift opcode.");
16869 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16870 if (!Subtarget->is64Bit() &&
16871 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16872 Amt.getOpcode() == ISD::BITCAST &&
16873 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16874 Amt = Amt.getOperand(0);
16875 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16876 VT.getVectorNumElements();
16877 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16878 uint64_t ShiftAmt = 0;
16879 for (unsigned i = 0; i != Ratio; ++i) {
16880 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16884 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16886 // Check remaining shift amounts.
16887 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16888 uint64_t ShAmt = 0;
16889 for (unsigned j = 0; j != Ratio; ++j) {
16890 ConstantSDNode *C =
16891 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16895 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16897 if (ShAmt != ShiftAmt)
16900 switch (Op.getOpcode()) {
16902 llvm_unreachable("Unknown shift opcode!");
16904 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16907 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16910 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16918 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16919 const X86Subtarget* Subtarget) {
16920 MVT VT = Op.getSimpleValueType();
16922 SDValue R = Op.getOperand(0);
16923 SDValue Amt = Op.getOperand(1);
16925 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16926 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16927 (Subtarget->hasInt256() &&
16928 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16929 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16930 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16932 EVT EltVT = VT.getVectorElementType();
16934 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16935 unsigned NumElts = VT.getVectorNumElements();
16937 for (i = 0; i != NumElts; ++i) {
16938 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16942 for (j = i; j != NumElts; ++j) {
16943 SDValue Arg = Amt.getOperand(j);
16944 if (Arg.getOpcode() == ISD::UNDEF) continue;
16945 if (Arg != Amt.getOperand(i))
16948 if (i != NumElts && j == NumElts)
16949 BaseShAmt = Amt.getOperand(i);
16951 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16952 Amt = Amt.getOperand(0);
16953 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16954 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16955 SDValue InVec = Amt.getOperand(0);
16956 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16957 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16959 for (; i != NumElts; ++i) {
16960 SDValue Arg = InVec.getOperand(i);
16961 if (Arg.getOpcode() == ISD::UNDEF) continue;
16965 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16966 if (ConstantSDNode *C =
16967 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16968 unsigned SplatIdx =
16969 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16970 if (C->getZExtValue() == SplatIdx)
16971 BaseShAmt = InVec.getOperand(1);
16974 if (!BaseShAmt.getNode())
16975 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16976 DAG.getIntPtrConstant(0));
16980 if (BaseShAmt.getNode()) {
16981 if (EltVT.bitsGT(MVT::i32))
16982 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16983 else if (EltVT.bitsLT(MVT::i32))
16984 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16986 switch (Op.getOpcode()) {
16988 llvm_unreachable("Unknown shift opcode!");
16990 switch (VT.SimpleTy) {
16991 default: return SDValue();
17000 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17003 switch (VT.SimpleTy) {
17004 default: return SDValue();
17011 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17014 switch (VT.SimpleTy) {
17015 default: return SDValue();
17024 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17030 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17031 if (!Subtarget->is64Bit() &&
17032 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17033 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17034 Amt.getOpcode() == ISD::BITCAST &&
17035 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17036 Amt = Amt.getOperand(0);
17037 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17038 VT.getVectorNumElements();
17039 std::vector<SDValue> Vals(Ratio);
17040 for (unsigned i = 0; i != Ratio; ++i)
17041 Vals[i] = Amt.getOperand(i);
17042 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17043 for (unsigned j = 0; j != Ratio; ++j)
17044 if (Vals[j] != Amt.getOperand(i + j))
17047 switch (Op.getOpcode()) {
17049 llvm_unreachable("Unknown shift opcode!");
17051 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17053 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17055 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17062 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17063 SelectionDAG &DAG) {
17064 MVT VT = Op.getSimpleValueType();
17066 SDValue R = Op.getOperand(0);
17067 SDValue Amt = Op.getOperand(1);
17070 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17071 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17073 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17077 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17081 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17083 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17084 if (Subtarget->hasInt256()) {
17085 if (Op.getOpcode() == ISD::SRL &&
17086 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17087 VT == MVT::v4i64 || VT == MVT::v8i32))
17089 if (Op.getOpcode() == ISD::SHL &&
17090 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17091 VT == MVT::v4i64 || VT == MVT::v8i32))
17093 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17097 // If possible, lower this packed shift into a vector multiply instead of
17098 // expanding it into a sequence of scalar shifts.
17099 // Do this only if the vector shift count is a constant build_vector.
17100 if (Op.getOpcode() == ISD::SHL &&
17101 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17102 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17103 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17104 SmallVector<SDValue, 8> Elts;
17105 EVT SVT = VT.getScalarType();
17106 unsigned SVTBits = SVT.getSizeInBits();
17107 const APInt &One = APInt(SVTBits, 1);
17108 unsigned NumElems = VT.getVectorNumElements();
17110 for (unsigned i=0; i !=NumElems; ++i) {
17111 SDValue Op = Amt->getOperand(i);
17112 if (Op->getOpcode() == ISD::UNDEF) {
17113 Elts.push_back(Op);
17117 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17118 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17119 uint64_t ShAmt = C.getZExtValue();
17120 if (ShAmt >= SVTBits) {
17121 Elts.push_back(DAG.getUNDEF(SVT));
17124 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17126 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17127 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17130 // Lower SHL with variable shift amount.
17131 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17132 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17134 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17135 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17136 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17137 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17140 // If possible, lower this shift as a sequence of two shifts by
17141 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17143 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17145 // Could be rewritten as:
17146 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17148 // The advantage is that the two shifts from the example would be
17149 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17150 // the vector shift into four scalar shifts plus four pairs of vector
17152 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17153 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17154 unsigned TargetOpcode = X86ISD::MOVSS;
17155 bool CanBeSimplified;
17156 // The splat value for the first packed shift (the 'X' from the example).
17157 SDValue Amt1 = Amt->getOperand(0);
17158 // The splat value for the second packed shift (the 'Y' from the example).
17159 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17160 Amt->getOperand(2);
17162 // See if it is possible to replace this node with a sequence of
17163 // two shifts followed by a MOVSS/MOVSD
17164 if (VT == MVT::v4i32) {
17165 // Check if it is legal to use a MOVSS.
17166 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17167 Amt2 == Amt->getOperand(3);
17168 if (!CanBeSimplified) {
17169 // Otherwise, check if we can still simplify this node using a MOVSD.
17170 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17171 Amt->getOperand(2) == Amt->getOperand(3);
17172 TargetOpcode = X86ISD::MOVSD;
17173 Amt2 = Amt->getOperand(2);
17176 // Do similar checks for the case where the machine value type
17178 CanBeSimplified = Amt1 == Amt->getOperand(1);
17179 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17180 CanBeSimplified = Amt2 == Amt->getOperand(i);
17182 if (!CanBeSimplified) {
17183 TargetOpcode = X86ISD::MOVSD;
17184 CanBeSimplified = true;
17185 Amt2 = Amt->getOperand(4);
17186 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17187 CanBeSimplified = Amt1 == Amt->getOperand(i);
17188 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17189 CanBeSimplified = Amt2 == Amt->getOperand(j);
17193 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17194 isa<ConstantSDNode>(Amt2)) {
17195 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17196 EVT CastVT = MVT::v4i32;
17198 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17199 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17201 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17202 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17203 if (TargetOpcode == X86ISD::MOVSD)
17204 CastVT = MVT::v2i64;
17205 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17206 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17207 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17209 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17213 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17214 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17217 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17218 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17220 // Turn 'a' into a mask suitable for VSELECT
17221 SDValue VSelM = DAG.getConstant(0x80, VT);
17222 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17223 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17225 SDValue CM1 = DAG.getConstant(0x0f, VT);
17226 SDValue CM2 = DAG.getConstant(0x3f, VT);
17228 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17229 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17230 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17231 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17232 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17235 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17236 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17237 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17239 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17240 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17241 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17242 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17243 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17246 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17247 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17248 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17250 // return VSELECT(r, r+r, a);
17251 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17252 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17256 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17257 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17258 // solution better.
17259 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17260 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17262 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17263 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17264 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17265 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17266 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17269 // Decompose 256-bit shifts into smaller 128-bit shifts.
17270 if (VT.is256BitVector()) {
17271 unsigned NumElems = VT.getVectorNumElements();
17272 MVT EltVT = VT.getVectorElementType();
17273 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17275 // Extract the two vectors
17276 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17277 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17279 // Recreate the shift amount vectors
17280 SDValue Amt1, Amt2;
17281 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17282 // Constant shift amount
17283 SmallVector<SDValue, 4> Amt1Csts;
17284 SmallVector<SDValue, 4> Amt2Csts;
17285 for (unsigned i = 0; i != NumElems/2; ++i)
17286 Amt1Csts.push_back(Amt->getOperand(i));
17287 for (unsigned i = NumElems/2; i != NumElems; ++i)
17288 Amt2Csts.push_back(Amt->getOperand(i));
17290 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17291 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17293 // Variable shift amount
17294 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17295 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17298 // Issue new vector shifts for the smaller types
17299 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17300 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17302 // Concatenate the result back
17303 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17309 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17310 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17311 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17312 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17313 // has only one use.
17314 SDNode *N = Op.getNode();
17315 SDValue LHS = N->getOperand(0);
17316 SDValue RHS = N->getOperand(1);
17317 unsigned BaseOp = 0;
17320 switch (Op.getOpcode()) {
17321 default: llvm_unreachable("Unknown ovf instruction!");
17323 // A subtract of one will be selected as a INC. Note that INC doesn't
17324 // set CF, so we can't do this for UADDO.
17325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17327 BaseOp = X86ISD::INC;
17328 Cond = X86::COND_O;
17331 BaseOp = X86ISD::ADD;
17332 Cond = X86::COND_O;
17335 BaseOp = X86ISD::ADD;
17336 Cond = X86::COND_B;
17339 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17340 // set CF, so we can't do this for USUBO.
17341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17343 BaseOp = X86ISD::DEC;
17344 Cond = X86::COND_O;
17347 BaseOp = X86ISD::SUB;
17348 Cond = X86::COND_O;
17351 BaseOp = X86ISD::SUB;
17352 Cond = X86::COND_B;
17355 BaseOp = X86ISD::SMUL;
17356 Cond = X86::COND_O;
17358 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17359 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17361 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17364 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17365 DAG.getConstant(X86::COND_O, MVT::i32),
17366 SDValue(Sum.getNode(), 2));
17368 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17372 // Also sets EFLAGS.
17373 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17374 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17377 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17378 DAG.getConstant(Cond, MVT::i32),
17379 SDValue(Sum.getNode(), 1));
17381 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17384 // Sign extension of the low part of vector elements. This may be used either
17385 // when sign extend instructions are not available or if the vector element
17386 // sizes already match the sign-extended size. If the vector elements are in
17387 // their pre-extended size and sign extend instructions are available, that will
17388 // be handled by LowerSIGN_EXTEND.
17389 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17390 SelectionDAG &DAG) const {
17392 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17393 MVT VT = Op.getSimpleValueType();
17395 if (!Subtarget->hasSSE2() || !VT.isVector())
17398 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17399 ExtraVT.getScalarType().getSizeInBits();
17401 switch (VT.SimpleTy) {
17402 default: return SDValue();
17405 if (!Subtarget->hasFp256())
17407 if (!Subtarget->hasInt256()) {
17408 // needs to be split
17409 unsigned NumElems = VT.getVectorNumElements();
17411 // Extract the LHS vectors
17412 SDValue LHS = Op.getOperand(0);
17413 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17414 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17416 MVT EltVT = VT.getVectorElementType();
17417 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17419 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17420 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17421 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17423 SDValue Extra = DAG.getValueType(ExtraVT);
17425 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17426 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17428 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17433 SDValue Op0 = Op.getOperand(0);
17435 // This is a sign extension of some low part of vector elements without
17436 // changing the size of the vector elements themselves:
17437 // Shift-Left + Shift-Right-Algebraic.
17438 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17440 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17446 /// Returns true if the operand type is exactly twice the native width, and
17447 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17448 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17449 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17450 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17451 const X86Subtarget &Subtarget =
17452 getTargetMachine().getSubtarget<X86Subtarget>();
17453 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17456 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17457 else if (OpWidth == 128)
17458 return Subtarget.hasCmpxchg16b();
17463 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17464 return needsCmpXchgNb(SI->getValueOperand()->getType());
17467 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *SI) const {
17468 return false; // FIXME, currently these are expanded separately in this file.
17471 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17472 const X86Subtarget &Subtarget =
17473 getTargetMachine().getSubtarget<X86Subtarget>();
17474 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17475 const Type *MemType = AI->getType();
17477 // If the operand is too big, we must see if cmpxchg8/16b is available
17478 // and default to library calls otherwise.
17479 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17480 return needsCmpXchgNb(MemType);
17482 AtomicRMWInst::BinOp Op = AI->getOperation();
17485 llvm_unreachable("Unknown atomic operation");
17486 case AtomicRMWInst::Xchg:
17487 case AtomicRMWInst::Add:
17488 case AtomicRMWInst::Sub:
17489 // It's better to use xadd, xsub or xchg for these in all cases.
17491 case AtomicRMWInst::Or:
17492 case AtomicRMWInst::And:
17493 case AtomicRMWInst::Xor:
17494 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17495 // prefix to a normal instruction for these operations.
17496 return !AI->use_empty();
17497 case AtomicRMWInst::Nand:
17498 case AtomicRMWInst::Max:
17499 case AtomicRMWInst::Min:
17500 case AtomicRMWInst::UMax:
17501 case AtomicRMWInst::UMin:
17502 // These always require a non-trivial set of data operations on x86. We must
17503 // use a cmpxchg loop.
17508 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17509 SelectionDAG &DAG) {
17511 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17512 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17513 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17514 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17516 // The only fence that needs an instruction is a sequentially-consistent
17517 // cross-thread fence.
17518 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17519 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17520 // no-sse2). There isn't any reason to disable it if the target processor
17522 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17523 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17525 SDValue Chain = Op.getOperand(0);
17526 SDValue Zero = DAG.getConstant(0, MVT::i32);
17528 DAG.getRegister(X86::ESP, MVT::i32), // Base
17529 DAG.getTargetConstant(1, MVT::i8), // Scale
17530 DAG.getRegister(0, MVT::i32), // Index
17531 DAG.getTargetConstant(0, MVT::i32), // Disp
17532 DAG.getRegister(0, MVT::i32), // Segment.
17536 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17537 return SDValue(Res, 0);
17540 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17541 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17544 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17545 SelectionDAG &DAG) {
17546 MVT T = Op.getSimpleValueType();
17550 switch(T.SimpleTy) {
17551 default: llvm_unreachable("Invalid value type!");
17552 case MVT::i8: Reg = X86::AL; size = 1; break;
17553 case MVT::i16: Reg = X86::AX; size = 2; break;
17554 case MVT::i32: Reg = X86::EAX; size = 4; break;
17556 assert(Subtarget->is64Bit() && "Node not type legal!");
17557 Reg = X86::RAX; size = 8;
17560 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17561 Op.getOperand(2), SDValue());
17562 SDValue Ops[] = { cpIn.getValue(0),
17565 DAG.getTargetConstant(size, MVT::i8),
17566 cpIn.getValue(1) };
17567 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17568 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17569 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17573 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17574 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17575 MVT::i32, cpOut.getValue(2));
17576 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17577 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17579 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17580 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17581 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17585 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17586 SelectionDAG &DAG) {
17587 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17588 MVT DstVT = Op.getSimpleValueType();
17590 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17591 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17592 if (DstVT != MVT::f64)
17593 // This conversion needs to be expanded.
17596 SDValue InVec = Op->getOperand(0);
17598 unsigned NumElts = SrcVT.getVectorNumElements();
17599 EVT SVT = SrcVT.getVectorElementType();
17601 // Widen the vector in input in the case of MVT::v2i32.
17602 // Example: from MVT::v2i32 to MVT::v4i32.
17603 SmallVector<SDValue, 16> Elts;
17604 for (unsigned i = 0, e = NumElts; i != e; ++i)
17605 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17606 DAG.getIntPtrConstant(i)));
17608 // Explicitly mark the extra elements as Undef.
17609 SDValue Undef = DAG.getUNDEF(SVT);
17610 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17611 Elts.push_back(Undef);
17613 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17614 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17615 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17616 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17617 DAG.getIntPtrConstant(0));
17620 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17621 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17622 assert((DstVT == MVT::i64 ||
17623 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17624 "Unexpected custom BITCAST");
17625 // i64 <=> MMX conversions are Legal.
17626 if (SrcVT==MVT::i64 && DstVT.isVector())
17628 if (DstVT==MVT::i64 && SrcVT.isVector())
17630 // MMX <=> MMX conversions are Legal.
17631 if (SrcVT.isVector() && DstVT.isVector())
17633 // All other conversions need to be expanded.
17637 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17638 SDNode *Node = Op.getNode();
17640 EVT T = Node->getValueType(0);
17641 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17642 DAG.getConstant(0, T), Node->getOperand(2));
17643 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17644 cast<AtomicSDNode>(Node)->getMemoryVT(),
17645 Node->getOperand(0),
17646 Node->getOperand(1), negOp,
17647 cast<AtomicSDNode>(Node)->getMemOperand(),
17648 cast<AtomicSDNode>(Node)->getOrdering(),
17649 cast<AtomicSDNode>(Node)->getSynchScope());
17652 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17653 SDNode *Node = Op.getNode();
17655 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17657 // Convert seq_cst store -> xchg
17658 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17659 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17660 // (The only way to get a 16-byte store is cmpxchg16b)
17661 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17662 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17663 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17664 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17665 cast<AtomicSDNode>(Node)->getMemoryVT(),
17666 Node->getOperand(0),
17667 Node->getOperand(1), Node->getOperand(2),
17668 cast<AtomicSDNode>(Node)->getMemOperand(),
17669 cast<AtomicSDNode>(Node)->getOrdering(),
17670 cast<AtomicSDNode>(Node)->getSynchScope());
17671 return Swap.getValue(1);
17673 // Other atomic stores have a simple pattern.
17677 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17678 EVT VT = Op.getNode()->getSimpleValueType(0);
17680 // Let legalize expand this if it isn't a legal type yet.
17681 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17684 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17687 bool ExtraOp = false;
17688 switch (Op.getOpcode()) {
17689 default: llvm_unreachable("Invalid code");
17690 case ISD::ADDC: Opc = X86ISD::ADD; break;
17691 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17692 case ISD::SUBC: Opc = X86ISD::SUB; break;
17693 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17697 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17699 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17700 Op.getOperand(1), Op.getOperand(2));
17703 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17704 SelectionDAG &DAG) {
17705 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17707 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17708 // which returns the values as { float, float } (in XMM0) or
17709 // { double, double } (which is returned in XMM0, XMM1).
17711 SDValue Arg = Op.getOperand(0);
17712 EVT ArgVT = Arg.getValueType();
17713 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17715 TargetLowering::ArgListTy Args;
17716 TargetLowering::ArgListEntry Entry;
17720 Entry.isSExt = false;
17721 Entry.isZExt = false;
17722 Args.push_back(Entry);
17724 bool isF64 = ArgVT == MVT::f64;
17725 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17726 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17727 // the results are returned via SRet in memory.
17728 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17729 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17730 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17732 Type *RetTy = isF64
17733 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17734 : (Type*)VectorType::get(ArgTy, 4);
17736 TargetLowering::CallLoweringInfo CLI(DAG);
17737 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17738 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17740 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17743 // Returned in xmm0 and xmm1.
17744 return CallResult.first;
17746 // Returned in bits 0:31 and 32:64 xmm0.
17747 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17748 CallResult.first, DAG.getIntPtrConstant(0));
17749 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17750 CallResult.first, DAG.getIntPtrConstant(1));
17751 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17752 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17755 /// LowerOperation - Provide custom lowering hooks for some operations.
17757 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17758 switch (Op.getOpcode()) {
17759 default: llvm_unreachable("Should not custom lower this!");
17760 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17761 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17762 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17763 return LowerCMP_SWAP(Op, Subtarget, DAG);
17764 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17765 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17766 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17767 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17768 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17769 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17770 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17771 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17772 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17773 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17774 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17775 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17776 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17777 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17778 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17779 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17780 case ISD::SHL_PARTS:
17781 case ISD::SRA_PARTS:
17782 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17783 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17784 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17785 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17786 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17787 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17788 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17789 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17790 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17791 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17792 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17794 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17795 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17796 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17797 case ISD::SETCC: return LowerSETCC(Op, DAG);
17798 case ISD::SELECT: return LowerSELECT(Op, DAG);
17799 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17800 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17801 case ISD::VASTART: return LowerVASTART(Op, DAG);
17802 case ISD::VAARG: return LowerVAARG(Op, DAG);
17803 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17804 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17805 case ISD::INTRINSIC_VOID:
17806 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17807 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17808 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17809 case ISD::FRAME_TO_ARGS_OFFSET:
17810 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17811 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17812 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17813 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17814 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17815 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17816 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17817 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17818 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17819 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17820 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17821 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17822 case ISD::UMUL_LOHI:
17823 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17826 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17832 case ISD::UMULO: return LowerXALUO(Op, DAG);
17833 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17834 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17838 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17839 case ISD::ADD: return LowerADD(Op, DAG);
17840 case ISD::SUB: return LowerSUB(Op, DAG);
17841 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17845 static void ReplaceATOMIC_LOAD(SDNode *Node,
17846 SmallVectorImpl<SDValue> &Results,
17847 SelectionDAG &DAG) {
17849 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17851 // Convert wide load -> cmpxchg8b/cmpxchg16b
17852 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17853 // (The only way to get a 16-byte load is cmpxchg16b)
17854 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17855 SDValue Zero = DAG.getConstant(0, VT);
17856 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17858 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17859 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17860 cast<AtomicSDNode>(Node)->getMemOperand(),
17861 cast<AtomicSDNode>(Node)->getOrdering(),
17862 cast<AtomicSDNode>(Node)->getOrdering(),
17863 cast<AtomicSDNode>(Node)->getSynchScope());
17864 Results.push_back(Swap.getValue(0));
17865 Results.push_back(Swap.getValue(2));
17868 /// ReplaceNodeResults - Replace a node with an illegal result type
17869 /// with a new node built out of custom code.
17870 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17871 SmallVectorImpl<SDValue>&Results,
17872 SelectionDAG &DAG) const {
17874 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17875 switch (N->getOpcode()) {
17877 llvm_unreachable("Do not know how to custom type legalize this operation!");
17878 case ISD::SIGN_EXTEND_INREG:
17883 // We don't want to expand or promote these.
17890 case ISD::UDIVREM: {
17891 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17892 Results.push_back(V);
17895 case ISD::FP_TO_SINT:
17896 case ISD::FP_TO_UINT: {
17897 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17899 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17902 std::pair<SDValue,SDValue> Vals =
17903 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17904 SDValue FIST = Vals.first, StackSlot = Vals.second;
17905 if (FIST.getNode()) {
17906 EVT VT = N->getValueType(0);
17907 // Return a load from the stack slot.
17908 if (StackSlot.getNode())
17909 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17910 MachinePointerInfo(),
17911 false, false, false, 0));
17913 Results.push_back(FIST);
17917 case ISD::UINT_TO_FP: {
17918 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17919 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17920 N->getValueType(0) != MVT::v2f32)
17922 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17924 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17926 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17927 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17928 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17929 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17930 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17931 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17934 case ISD::FP_ROUND: {
17935 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17937 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17938 Results.push_back(V);
17941 case ISD::INTRINSIC_W_CHAIN: {
17942 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17944 default : llvm_unreachable("Do not know how to custom type "
17945 "legalize this intrinsic operation!");
17946 case Intrinsic::x86_rdtsc:
17947 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17949 case Intrinsic::x86_rdtscp:
17950 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17952 case Intrinsic::x86_rdpmc:
17953 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17956 case ISD::READCYCLECOUNTER: {
17957 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17960 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17961 EVT T = N->getValueType(0);
17962 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17963 bool Regs64bit = T == MVT::i128;
17964 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17965 SDValue cpInL, cpInH;
17966 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17967 DAG.getConstant(0, HalfT));
17968 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17969 DAG.getConstant(1, HalfT));
17970 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17971 Regs64bit ? X86::RAX : X86::EAX,
17973 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17974 Regs64bit ? X86::RDX : X86::EDX,
17975 cpInH, cpInL.getValue(1));
17976 SDValue swapInL, swapInH;
17977 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17978 DAG.getConstant(0, HalfT));
17979 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17980 DAG.getConstant(1, HalfT));
17981 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17982 Regs64bit ? X86::RBX : X86::EBX,
17983 swapInL, cpInH.getValue(1));
17984 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17985 Regs64bit ? X86::RCX : X86::ECX,
17986 swapInH, swapInL.getValue(1));
17987 SDValue Ops[] = { swapInH.getValue(0),
17989 swapInH.getValue(1) };
17990 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17991 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17992 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17993 X86ISD::LCMPXCHG8_DAG;
17994 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17995 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17996 Regs64bit ? X86::RAX : X86::EAX,
17997 HalfT, Result.getValue(1));
17998 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17999 Regs64bit ? X86::RDX : X86::EDX,
18000 HalfT, cpOutL.getValue(2));
18001 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18003 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18004 MVT::i32, cpOutH.getValue(2));
18006 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18007 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18008 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18010 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18011 Results.push_back(Success);
18012 Results.push_back(EFLAGS.getValue(1));
18015 case ISD::ATOMIC_SWAP:
18016 case ISD::ATOMIC_LOAD_ADD:
18017 case ISD::ATOMIC_LOAD_SUB:
18018 case ISD::ATOMIC_LOAD_AND:
18019 case ISD::ATOMIC_LOAD_OR:
18020 case ISD::ATOMIC_LOAD_XOR:
18021 case ISD::ATOMIC_LOAD_NAND:
18022 case ISD::ATOMIC_LOAD_MIN:
18023 case ISD::ATOMIC_LOAD_MAX:
18024 case ISD::ATOMIC_LOAD_UMIN:
18025 case ISD::ATOMIC_LOAD_UMAX:
18026 // Delegate to generic TypeLegalization. Situations we can really handle
18027 // should have already been dealt with by AtomicExpandPass.cpp.
18029 case ISD::ATOMIC_LOAD: {
18030 ReplaceATOMIC_LOAD(N, Results, DAG);
18033 case ISD::BITCAST: {
18034 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18035 EVT DstVT = N->getValueType(0);
18036 EVT SrcVT = N->getOperand(0)->getValueType(0);
18038 if (SrcVT != MVT::f64 ||
18039 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18042 unsigned NumElts = DstVT.getVectorNumElements();
18043 EVT SVT = DstVT.getVectorElementType();
18044 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18045 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18046 MVT::v2f64, N->getOperand(0));
18047 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18049 if (ExperimentalVectorWideningLegalization) {
18050 // If we are legalizing vectors by widening, we already have the desired
18051 // legal vector type, just return it.
18052 Results.push_back(ToVecInt);
18056 SmallVector<SDValue, 8> Elts;
18057 for (unsigned i = 0, e = NumElts; i != e; ++i)
18058 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18059 ToVecInt, DAG.getIntPtrConstant(i)));
18061 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18066 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18068 default: return nullptr;
18069 case X86ISD::BSF: return "X86ISD::BSF";
18070 case X86ISD::BSR: return "X86ISD::BSR";
18071 case X86ISD::SHLD: return "X86ISD::SHLD";
18072 case X86ISD::SHRD: return "X86ISD::SHRD";
18073 case X86ISD::FAND: return "X86ISD::FAND";
18074 case X86ISD::FANDN: return "X86ISD::FANDN";
18075 case X86ISD::FOR: return "X86ISD::FOR";
18076 case X86ISD::FXOR: return "X86ISD::FXOR";
18077 case X86ISD::FSRL: return "X86ISD::FSRL";
18078 case X86ISD::FILD: return "X86ISD::FILD";
18079 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18080 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18081 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18082 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18083 case X86ISD::FLD: return "X86ISD::FLD";
18084 case X86ISD::FST: return "X86ISD::FST";
18085 case X86ISD::CALL: return "X86ISD::CALL";
18086 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18087 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18088 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18089 case X86ISD::BT: return "X86ISD::BT";
18090 case X86ISD::CMP: return "X86ISD::CMP";
18091 case X86ISD::COMI: return "X86ISD::COMI";
18092 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18093 case X86ISD::CMPM: return "X86ISD::CMPM";
18094 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18095 case X86ISD::SETCC: return "X86ISD::SETCC";
18096 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18097 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18098 case X86ISD::CMOV: return "X86ISD::CMOV";
18099 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18100 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18101 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18102 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18103 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18104 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18105 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18106 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18107 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18108 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18109 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18110 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18111 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18112 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18113 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18114 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18115 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18116 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18117 case X86ISD::HADD: return "X86ISD::HADD";
18118 case X86ISD::HSUB: return "X86ISD::HSUB";
18119 case X86ISD::FHADD: return "X86ISD::FHADD";
18120 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18121 case X86ISD::UMAX: return "X86ISD::UMAX";
18122 case X86ISD::UMIN: return "X86ISD::UMIN";
18123 case X86ISD::SMAX: return "X86ISD::SMAX";
18124 case X86ISD::SMIN: return "X86ISD::SMIN";
18125 case X86ISD::FMAX: return "X86ISD::FMAX";
18126 case X86ISD::FMIN: return "X86ISD::FMIN";
18127 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18128 case X86ISD::FMINC: return "X86ISD::FMINC";
18129 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18130 case X86ISD::FRCP: return "X86ISD::FRCP";
18131 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18132 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18133 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18134 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18135 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18136 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18137 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18138 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18139 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18140 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18141 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18142 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18143 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18144 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18145 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18146 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18147 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18148 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18149 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18150 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18151 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18152 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18153 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18154 case X86ISD::VSHL: return "X86ISD::VSHL";
18155 case X86ISD::VSRL: return "X86ISD::VSRL";
18156 case X86ISD::VSRA: return "X86ISD::VSRA";
18157 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18158 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18159 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18160 case X86ISD::CMPP: return "X86ISD::CMPP";
18161 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18162 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18163 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18164 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18165 case X86ISD::ADD: return "X86ISD::ADD";
18166 case X86ISD::SUB: return "X86ISD::SUB";
18167 case X86ISD::ADC: return "X86ISD::ADC";
18168 case X86ISD::SBB: return "X86ISD::SBB";
18169 case X86ISD::SMUL: return "X86ISD::SMUL";
18170 case X86ISD::UMUL: return "X86ISD::UMUL";
18171 case X86ISD::INC: return "X86ISD::INC";
18172 case X86ISD::DEC: return "X86ISD::DEC";
18173 case X86ISD::OR: return "X86ISD::OR";
18174 case X86ISD::XOR: return "X86ISD::XOR";
18175 case X86ISD::AND: return "X86ISD::AND";
18176 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18177 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18178 case X86ISD::PTEST: return "X86ISD::PTEST";
18179 case X86ISD::TESTP: return "X86ISD::TESTP";
18180 case X86ISD::TESTM: return "X86ISD::TESTM";
18181 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18182 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18183 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18184 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18185 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18186 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18187 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18188 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18189 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18190 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18191 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18192 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18193 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18194 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18195 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18196 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18197 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18198 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18199 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18200 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18201 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18202 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18203 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18204 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18205 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18206 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
18207 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18208 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18209 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18210 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18211 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18212 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18213 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18214 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18215 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18216 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18217 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18218 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18219 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18220 case X86ISD::SAHF: return "X86ISD::SAHF";
18221 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18222 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18223 case X86ISD::FMADD: return "X86ISD::FMADD";
18224 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18225 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18226 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18227 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18228 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18229 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18230 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18231 case X86ISD::XTEST: return "X86ISD::XTEST";
18235 // isLegalAddressingMode - Return true if the addressing mode represented
18236 // by AM is legal for this target, for a load/store of the specified type.
18237 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18239 // X86 supports extremely general addressing modes.
18240 CodeModel::Model M = getTargetMachine().getCodeModel();
18241 Reloc::Model R = getTargetMachine().getRelocationModel();
18243 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18244 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18249 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18251 // If a reference to this global requires an extra load, we can't fold it.
18252 if (isGlobalStubReference(GVFlags))
18255 // If BaseGV requires a register for the PIC base, we cannot also have a
18256 // BaseReg specified.
18257 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18260 // If lower 4G is not available, then we must use rip-relative addressing.
18261 if ((M != CodeModel::Small || R != Reloc::Static) &&
18262 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18266 switch (AM.Scale) {
18272 // These scales always work.
18277 // These scales are formed with basereg+scalereg. Only accept if there is
18282 default: // Other stuff never works.
18289 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18290 unsigned Bits = Ty->getScalarSizeInBits();
18292 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18293 // particularly cheaper than those without.
18297 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18298 // variable shifts just as cheap as scalar ones.
18299 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18302 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18303 // fully general vector.
18307 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18308 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18310 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18311 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18312 return NumBits1 > NumBits2;
18315 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18316 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18319 if (!isTypeLegal(EVT::getEVT(Ty1)))
18322 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18324 // Assuming the caller doesn't have a zeroext or signext return parameter,
18325 // truncation all the way down to i1 is valid.
18329 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18330 return isInt<32>(Imm);
18333 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18334 // Can also use sub to handle negated immediates.
18335 return isInt<32>(Imm);
18338 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18339 if (!VT1.isInteger() || !VT2.isInteger())
18341 unsigned NumBits1 = VT1.getSizeInBits();
18342 unsigned NumBits2 = VT2.getSizeInBits();
18343 return NumBits1 > NumBits2;
18346 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18347 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18348 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18351 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18352 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18353 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18356 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18357 EVT VT1 = Val.getValueType();
18358 if (isZExtFree(VT1, VT2))
18361 if (Val.getOpcode() != ISD::LOAD)
18364 if (!VT1.isSimple() || !VT1.isInteger() ||
18365 !VT2.isSimple() || !VT2.isInteger())
18368 switch (VT1.getSimpleVT().SimpleTy) {
18373 // X86 has 8, 16, and 32-bit zero-extending loads.
18381 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18382 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18385 VT = VT.getScalarType();
18387 if (!VT.isSimple())
18390 switch (VT.getSimpleVT().SimpleTy) {
18401 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18402 // i16 instructions are longer (0x66 prefix) and potentially slower.
18403 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18406 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18407 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18408 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18409 /// are assumed to be legal.
18411 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18413 if (!VT.isSimple())
18416 MVT SVT = VT.getSimpleVT();
18418 // Very little shuffling can be done for 64-bit vectors right now.
18419 if (VT.getSizeInBits() == 64)
18422 // If this is a single-input shuffle with no 128 bit lane crossings we can
18423 // lower it into pshufb.
18424 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18425 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18426 bool isLegal = true;
18427 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18428 if (M[I] >= (int)SVT.getVectorNumElements() ||
18429 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18438 // FIXME: blends, shifts.
18439 return (SVT.getVectorNumElements() == 2 ||
18440 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18441 isMOVLMask(M, SVT) ||
18442 isMOVHLPSMask(M, SVT) ||
18443 isSHUFPMask(M, SVT) ||
18444 isPSHUFDMask(M, SVT) ||
18445 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18446 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18447 isPALIGNRMask(M, SVT, Subtarget) ||
18448 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18449 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18450 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18451 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18452 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18456 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18458 if (!VT.isSimple())
18461 MVT SVT = VT.getSimpleVT();
18462 unsigned NumElts = SVT.getVectorNumElements();
18463 // FIXME: This collection of masks seems suspect.
18466 if (NumElts == 4 && SVT.is128BitVector()) {
18467 return (isMOVLMask(Mask, SVT) ||
18468 isCommutedMOVLMask(Mask, SVT, true) ||
18469 isSHUFPMask(Mask, SVT) ||
18470 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18475 //===----------------------------------------------------------------------===//
18476 // X86 Scheduler Hooks
18477 //===----------------------------------------------------------------------===//
18479 /// Utility function to emit xbegin specifying the start of an RTM region.
18480 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18481 const TargetInstrInfo *TII) {
18482 DebugLoc DL = MI->getDebugLoc();
18484 const BasicBlock *BB = MBB->getBasicBlock();
18485 MachineFunction::iterator I = MBB;
18488 // For the v = xbegin(), we generate
18499 MachineBasicBlock *thisMBB = MBB;
18500 MachineFunction *MF = MBB->getParent();
18501 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18502 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18503 MF->insert(I, mainMBB);
18504 MF->insert(I, sinkMBB);
18506 // Transfer the remainder of BB and its successor edges to sinkMBB.
18507 sinkMBB->splice(sinkMBB->begin(), MBB,
18508 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18509 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18513 // # fallthrough to mainMBB
18514 // # abortion to sinkMBB
18515 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18516 thisMBB->addSuccessor(mainMBB);
18517 thisMBB->addSuccessor(sinkMBB);
18521 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18522 mainMBB->addSuccessor(sinkMBB);
18525 // EAX is live into the sinkMBB
18526 sinkMBB->addLiveIn(X86::EAX);
18527 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18528 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18531 MI->eraseFromParent();
18535 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18536 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18537 // in the .td file.
18538 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18539 const TargetInstrInfo *TII) {
18541 switch (MI->getOpcode()) {
18542 default: llvm_unreachable("illegal opcode!");
18543 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18544 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18545 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18546 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18547 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18548 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18549 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18550 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18553 DebugLoc dl = MI->getDebugLoc();
18554 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18556 unsigned NumArgs = MI->getNumOperands();
18557 for (unsigned i = 1; i < NumArgs; ++i) {
18558 MachineOperand &Op = MI->getOperand(i);
18559 if (!(Op.isReg() && Op.isImplicit()))
18560 MIB.addOperand(Op);
18562 if (MI->hasOneMemOperand())
18563 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18565 BuildMI(*BB, MI, dl,
18566 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18567 .addReg(X86::XMM0);
18569 MI->eraseFromParent();
18573 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18574 // defs in an instruction pattern
18575 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18576 const TargetInstrInfo *TII) {
18578 switch (MI->getOpcode()) {
18579 default: llvm_unreachable("illegal opcode!");
18580 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18581 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18582 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18583 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18584 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18585 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18586 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18587 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18590 DebugLoc dl = MI->getDebugLoc();
18591 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18593 unsigned NumArgs = MI->getNumOperands(); // remove the results
18594 for (unsigned i = 1; i < NumArgs; ++i) {
18595 MachineOperand &Op = MI->getOperand(i);
18596 if (!(Op.isReg() && Op.isImplicit()))
18597 MIB.addOperand(Op);
18599 if (MI->hasOneMemOperand())
18600 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18602 BuildMI(*BB, MI, dl,
18603 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18606 MI->eraseFromParent();
18610 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18611 const TargetInstrInfo *TII,
18612 const X86Subtarget* Subtarget) {
18613 DebugLoc dl = MI->getDebugLoc();
18615 // Address into RAX/EAX, other two args into ECX, EDX.
18616 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18617 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18618 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18619 for (int i = 0; i < X86::AddrNumOperands; ++i)
18620 MIB.addOperand(MI->getOperand(i));
18622 unsigned ValOps = X86::AddrNumOperands;
18623 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18624 .addReg(MI->getOperand(ValOps).getReg());
18625 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18626 .addReg(MI->getOperand(ValOps+1).getReg());
18628 // The instruction doesn't actually take any operands though.
18629 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18631 MI->eraseFromParent(); // The pseudo is gone now.
18635 MachineBasicBlock *
18636 X86TargetLowering::EmitVAARG64WithCustomInserter(
18638 MachineBasicBlock *MBB) const {
18639 // Emit va_arg instruction on X86-64.
18641 // Operands to this pseudo-instruction:
18642 // 0 ) Output : destination address (reg)
18643 // 1-5) Input : va_list address (addr, i64mem)
18644 // 6 ) ArgSize : Size (in bytes) of vararg type
18645 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18646 // 8 ) Align : Alignment of type
18647 // 9 ) EFLAGS (implicit-def)
18649 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18650 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18652 unsigned DestReg = MI->getOperand(0).getReg();
18653 MachineOperand &Base = MI->getOperand(1);
18654 MachineOperand &Scale = MI->getOperand(2);
18655 MachineOperand &Index = MI->getOperand(3);
18656 MachineOperand &Disp = MI->getOperand(4);
18657 MachineOperand &Segment = MI->getOperand(5);
18658 unsigned ArgSize = MI->getOperand(6).getImm();
18659 unsigned ArgMode = MI->getOperand(7).getImm();
18660 unsigned Align = MI->getOperand(8).getImm();
18662 // Memory Reference
18663 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18664 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18665 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18667 // Machine Information
18668 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18669 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18670 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18671 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18672 DebugLoc DL = MI->getDebugLoc();
18674 // struct va_list {
18677 // i64 overflow_area (address)
18678 // i64 reg_save_area (address)
18680 // sizeof(va_list) = 24
18681 // alignment(va_list) = 8
18683 unsigned TotalNumIntRegs = 6;
18684 unsigned TotalNumXMMRegs = 8;
18685 bool UseGPOffset = (ArgMode == 1);
18686 bool UseFPOffset = (ArgMode == 2);
18687 unsigned MaxOffset = TotalNumIntRegs * 8 +
18688 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18690 /* Align ArgSize to a multiple of 8 */
18691 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18692 bool NeedsAlign = (Align > 8);
18694 MachineBasicBlock *thisMBB = MBB;
18695 MachineBasicBlock *overflowMBB;
18696 MachineBasicBlock *offsetMBB;
18697 MachineBasicBlock *endMBB;
18699 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18700 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18701 unsigned OffsetReg = 0;
18703 if (!UseGPOffset && !UseFPOffset) {
18704 // If we only pull from the overflow region, we don't create a branch.
18705 // We don't need to alter control flow.
18706 OffsetDestReg = 0; // unused
18707 OverflowDestReg = DestReg;
18709 offsetMBB = nullptr;
18710 overflowMBB = thisMBB;
18713 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18714 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18715 // If not, pull from overflow_area. (branch to overflowMBB)
18720 // offsetMBB overflowMBB
18725 // Registers for the PHI in endMBB
18726 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18727 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18729 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18730 MachineFunction *MF = MBB->getParent();
18731 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18732 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18733 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18735 MachineFunction::iterator MBBIter = MBB;
18738 // Insert the new basic blocks
18739 MF->insert(MBBIter, offsetMBB);
18740 MF->insert(MBBIter, overflowMBB);
18741 MF->insert(MBBIter, endMBB);
18743 // Transfer the remainder of MBB and its successor edges to endMBB.
18744 endMBB->splice(endMBB->begin(), thisMBB,
18745 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18746 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18748 // Make offsetMBB and overflowMBB successors of thisMBB
18749 thisMBB->addSuccessor(offsetMBB);
18750 thisMBB->addSuccessor(overflowMBB);
18752 // endMBB is a successor of both offsetMBB and overflowMBB
18753 offsetMBB->addSuccessor(endMBB);
18754 overflowMBB->addSuccessor(endMBB);
18756 // Load the offset value into a register
18757 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18758 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18762 .addDisp(Disp, UseFPOffset ? 4 : 0)
18763 .addOperand(Segment)
18764 .setMemRefs(MMOBegin, MMOEnd);
18766 // Check if there is enough room left to pull this argument.
18767 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18769 .addImm(MaxOffset + 8 - ArgSizeA8);
18771 // Branch to "overflowMBB" if offset >= max
18772 // Fall through to "offsetMBB" otherwise
18773 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18774 .addMBB(overflowMBB);
18777 // In offsetMBB, emit code to use the reg_save_area.
18779 assert(OffsetReg != 0);
18781 // Read the reg_save_area address.
18782 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18783 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18788 .addOperand(Segment)
18789 .setMemRefs(MMOBegin, MMOEnd);
18791 // Zero-extend the offset
18792 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18793 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18796 .addImm(X86::sub_32bit);
18798 // Add the offset to the reg_save_area to get the final address.
18799 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18800 .addReg(OffsetReg64)
18801 .addReg(RegSaveReg);
18803 // Compute the offset for the next argument
18804 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18805 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18807 .addImm(UseFPOffset ? 16 : 8);
18809 // Store it back into the va_list.
18810 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18814 .addDisp(Disp, UseFPOffset ? 4 : 0)
18815 .addOperand(Segment)
18816 .addReg(NextOffsetReg)
18817 .setMemRefs(MMOBegin, MMOEnd);
18820 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18825 // Emit code to use overflow area
18828 // Load the overflow_area address into a register.
18829 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18830 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18835 .addOperand(Segment)
18836 .setMemRefs(MMOBegin, MMOEnd);
18838 // If we need to align it, do so. Otherwise, just copy the address
18839 // to OverflowDestReg.
18841 // Align the overflow address
18842 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18843 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18845 // aligned_addr = (addr + (align-1)) & ~(align-1)
18846 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18847 .addReg(OverflowAddrReg)
18850 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18852 .addImm(~(uint64_t)(Align-1));
18854 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18855 .addReg(OverflowAddrReg);
18858 // Compute the next overflow address after this argument.
18859 // (the overflow address should be kept 8-byte aligned)
18860 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18861 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18862 .addReg(OverflowDestReg)
18863 .addImm(ArgSizeA8);
18865 // Store the new overflow address.
18866 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18871 .addOperand(Segment)
18872 .addReg(NextAddrReg)
18873 .setMemRefs(MMOBegin, MMOEnd);
18875 // If we branched, emit the PHI to the front of endMBB.
18877 BuildMI(*endMBB, endMBB->begin(), DL,
18878 TII->get(X86::PHI), DestReg)
18879 .addReg(OffsetDestReg).addMBB(offsetMBB)
18880 .addReg(OverflowDestReg).addMBB(overflowMBB);
18883 // Erase the pseudo instruction
18884 MI->eraseFromParent();
18889 MachineBasicBlock *
18890 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18892 MachineBasicBlock *MBB) const {
18893 // Emit code to save XMM registers to the stack. The ABI says that the
18894 // number of registers to save is given in %al, so it's theoretically
18895 // possible to do an indirect jump trick to avoid saving all of them,
18896 // however this code takes a simpler approach and just executes all
18897 // of the stores if %al is non-zero. It's less code, and it's probably
18898 // easier on the hardware branch predictor, and stores aren't all that
18899 // expensive anyway.
18901 // Create the new basic blocks. One block contains all the XMM stores,
18902 // and one block is the final destination regardless of whether any
18903 // stores were performed.
18904 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18905 MachineFunction *F = MBB->getParent();
18906 MachineFunction::iterator MBBIter = MBB;
18908 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18909 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18910 F->insert(MBBIter, XMMSaveMBB);
18911 F->insert(MBBIter, EndMBB);
18913 // Transfer the remainder of MBB and its successor edges to EndMBB.
18914 EndMBB->splice(EndMBB->begin(), MBB,
18915 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18916 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18918 // The original block will now fall through to the XMM save block.
18919 MBB->addSuccessor(XMMSaveMBB);
18920 // The XMMSaveMBB will fall through to the end block.
18921 XMMSaveMBB->addSuccessor(EndMBB);
18923 // Now add the instructions.
18924 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18925 DebugLoc DL = MI->getDebugLoc();
18927 unsigned CountReg = MI->getOperand(0).getReg();
18928 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18929 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18931 if (!Subtarget->isTargetWin64()) {
18932 // If %al is 0, branch around the XMM save block.
18933 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18934 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18935 MBB->addSuccessor(EndMBB);
18938 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18939 // that was just emitted, but clearly shouldn't be "saved".
18940 assert((MI->getNumOperands() <= 3 ||
18941 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18942 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18943 && "Expected last argument to be EFLAGS");
18944 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18945 // In the XMM save block, save all the XMM argument registers.
18946 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18947 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18948 MachineMemOperand *MMO =
18949 F->getMachineMemOperand(
18950 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18951 MachineMemOperand::MOStore,
18952 /*Size=*/16, /*Align=*/16);
18953 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18954 .addFrameIndex(RegSaveFrameIndex)
18955 .addImm(/*Scale=*/1)
18956 .addReg(/*IndexReg=*/0)
18957 .addImm(/*Disp=*/Offset)
18958 .addReg(/*Segment=*/0)
18959 .addReg(MI->getOperand(i).getReg())
18960 .addMemOperand(MMO);
18963 MI->eraseFromParent(); // The pseudo instruction is gone now.
18968 // The EFLAGS operand of SelectItr might be missing a kill marker
18969 // because there were multiple uses of EFLAGS, and ISel didn't know
18970 // which to mark. Figure out whether SelectItr should have had a
18971 // kill marker, and set it if it should. Returns the correct kill
18973 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18974 MachineBasicBlock* BB,
18975 const TargetRegisterInfo* TRI) {
18976 // Scan forward through BB for a use/def of EFLAGS.
18977 MachineBasicBlock::iterator miI(std::next(SelectItr));
18978 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18979 const MachineInstr& mi = *miI;
18980 if (mi.readsRegister(X86::EFLAGS))
18982 if (mi.definesRegister(X86::EFLAGS))
18983 break; // Should have kill-flag - update below.
18986 // If we hit the end of the block, check whether EFLAGS is live into a
18988 if (miI == BB->end()) {
18989 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18990 sEnd = BB->succ_end();
18991 sItr != sEnd; ++sItr) {
18992 MachineBasicBlock* succ = *sItr;
18993 if (succ->isLiveIn(X86::EFLAGS))
18998 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18999 // out. SelectMI should have a kill flag on EFLAGS.
19000 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19004 MachineBasicBlock *
19005 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19006 MachineBasicBlock *BB) const {
19007 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19008 DebugLoc DL = MI->getDebugLoc();
19010 // To "insert" a SELECT_CC instruction, we actually have to insert the
19011 // diamond control-flow pattern. The incoming instruction knows the
19012 // destination vreg to set, the condition code register to branch on, the
19013 // true/false values to select between, and a branch opcode to use.
19014 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19015 MachineFunction::iterator It = BB;
19021 // cmpTY ccX, r1, r2
19023 // fallthrough --> copy0MBB
19024 MachineBasicBlock *thisMBB = BB;
19025 MachineFunction *F = BB->getParent();
19026 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19027 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19028 F->insert(It, copy0MBB);
19029 F->insert(It, sinkMBB);
19031 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19032 // live into the sink and copy blocks.
19033 const TargetRegisterInfo *TRI =
19034 BB->getParent()->getSubtarget().getRegisterInfo();
19035 if (!MI->killsRegister(X86::EFLAGS) &&
19036 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19037 copy0MBB->addLiveIn(X86::EFLAGS);
19038 sinkMBB->addLiveIn(X86::EFLAGS);
19041 // Transfer the remainder of BB and its successor edges to sinkMBB.
19042 sinkMBB->splice(sinkMBB->begin(), BB,
19043 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19044 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19046 // Add the true and fallthrough blocks as its successors.
19047 BB->addSuccessor(copy0MBB);
19048 BB->addSuccessor(sinkMBB);
19050 // Create the conditional branch instruction.
19052 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19053 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19056 // %FalseValue = ...
19057 // # fallthrough to sinkMBB
19058 copy0MBB->addSuccessor(sinkMBB);
19061 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19063 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19064 TII->get(X86::PHI), MI->getOperand(0).getReg())
19065 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19066 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19068 MI->eraseFromParent(); // The pseudo instruction is gone now.
19072 MachineBasicBlock *
19073 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19074 MachineBasicBlock *BB) const {
19075 MachineFunction *MF = BB->getParent();
19076 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19077 DebugLoc DL = MI->getDebugLoc();
19078 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19080 assert(MF->shouldSplitStack());
19082 const bool Is64Bit = Subtarget->is64Bit();
19083 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19085 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19086 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19089 // ... [Till the alloca]
19090 // If stacklet is not large enough, jump to mallocMBB
19093 // Allocate by subtracting from RSP
19094 // Jump to continueMBB
19097 // Allocate by call to runtime
19101 // [rest of original BB]
19104 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19105 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19106 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19108 MachineRegisterInfo &MRI = MF->getRegInfo();
19109 const TargetRegisterClass *AddrRegClass =
19110 getRegClassFor(getPointerTy());
19112 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19113 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19114 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19115 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19116 sizeVReg = MI->getOperand(1).getReg(),
19117 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19119 MachineFunction::iterator MBBIter = BB;
19122 MF->insert(MBBIter, bumpMBB);
19123 MF->insert(MBBIter, mallocMBB);
19124 MF->insert(MBBIter, continueMBB);
19126 continueMBB->splice(continueMBB->begin(), BB,
19127 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19128 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19130 // Add code to the main basic block to check if the stack limit has been hit,
19131 // and if so, jump to mallocMBB otherwise to bumpMBB.
19132 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19133 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19134 .addReg(tmpSPVReg).addReg(sizeVReg);
19135 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19136 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19137 .addReg(SPLimitVReg);
19138 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19140 // bumpMBB simply decreases the stack pointer, since we know the current
19141 // stacklet has enough space.
19142 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19143 .addReg(SPLimitVReg);
19144 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19145 .addReg(SPLimitVReg);
19146 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19148 // Calls into a routine in libgcc to allocate more space from the heap.
19149 const uint32_t *RegMask = MF->getTarget()
19150 .getSubtargetImpl()
19151 ->getRegisterInfo()
19152 ->getCallPreservedMask(CallingConv::C);
19154 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19156 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19157 .addExternalSymbol("__morestack_allocate_stack_space")
19158 .addRegMask(RegMask)
19159 .addReg(X86::RDI, RegState::Implicit)
19160 .addReg(X86::RAX, RegState::ImplicitDefine);
19161 } else if (Is64Bit) {
19162 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19164 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19165 .addExternalSymbol("__morestack_allocate_stack_space")
19166 .addRegMask(RegMask)
19167 .addReg(X86::EDI, RegState::Implicit)
19168 .addReg(X86::EAX, RegState::ImplicitDefine);
19170 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19172 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19173 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19174 .addExternalSymbol("__morestack_allocate_stack_space")
19175 .addRegMask(RegMask)
19176 .addReg(X86::EAX, RegState::ImplicitDefine);
19180 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19183 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19184 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19185 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19187 // Set up the CFG correctly.
19188 BB->addSuccessor(bumpMBB);
19189 BB->addSuccessor(mallocMBB);
19190 mallocMBB->addSuccessor(continueMBB);
19191 bumpMBB->addSuccessor(continueMBB);
19193 // Take care of the PHI nodes.
19194 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19195 MI->getOperand(0).getReg())
19196 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19197 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19199 // Delete the original pseudo instruction.
19200 MI->eraseFromParent();
19203 return continueMBB;
19206 MachineBasicBlock *
19207 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19208 MachineBasicBlock *BB) const {
19209 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19210 DebugLoc DL = MI->getDebugLoc();
19212 assert(!Subtarget->isTargetMacho());
19214 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19215 // non-trivial part is impdef of ESP.
19217 if (Subtarget->isTargetWin64()) {
19218 if (Subtarget->isTargetCygMing()) {
19219 // ___chkstk(Mingw64):
19220 // Clobbers R10, R11, RAX and EFLAGS.
19222 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19223 .addExternalSymbol("___chkstk")
19224 .addReg(X86::RAX, RegState::Implicit)
19225 .addReg(X86::RSP, RegState::Implicit)
19226 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19227 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19228 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19230 // __chkstk(MSVCRT): does not update stack pointer.
19231 // Clobbers R10, R11 and EFLAGS.
19232 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19233 .addExternalSymbol("__chkstk")
19234 .addReg(X86::RAX, RegState::Implicit)
19235 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19236 // RAX has the offset to be subtracted from RSP.
19237 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19242 const char *StackProbeSymbol =
19243 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19245 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19246 .addExternalSymbol(StackProbeSymbol)
19247 .addReg(X86::EAX, RegState::Implicit)
19248 .addReg(X86::ESP, RegState::Implicit)
19249 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19250 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19251 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19254 MI->eraseFromParent(); // The pseudo instruction is gone now.
19258 MachineBasicBlock *
19259 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19260 MachineBasicBlock *BB) const {
19261 // This is pretty easy. We're taking the value that we received from
19262 // our load from the relocation, sticking it in either RDI (x86-64)
19263 // or EAX and doing an indirect call. The return value will then
19264 // be in the normal return register.
19265 MachineFunction *F = BB->getParent();
19266 const X86InstrInfo *TII =
19267 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19268 DebugLoc DL = MI->getDebugLoc();
19270 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19271 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19273 // Get a register mask for the lowered call.
19274 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19275 // proper register mask.
19276 const uint32_t *RegMask = F->getTarget()
19277 .getSubtargetImpl()
19278 ->getRegisterInfo()
19279 ->getCallPreservedMask(CallingConv::C);
19280 if (Subtarget->is64Bit()) {
19281 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19282 TII->get(X86::MOV64rm), X86::RDI)
19284 .addImm(0).addReg(0)
19285 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19286 MI->getOperand(3).getTargetFlags())
19288 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19289 addDirectMem(MIB, X86::RDI);
19290 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19291 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19292 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19293 TII->get(X86::MOV32rm), X86::EAX)
19295 .addImm(0).addReg(0)
19296 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19297 MI->getOperand(3).getTargetFlags())
19299 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19300 addDirectMem(MIB, X86::EAX);
19301 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19303 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19304 TII->get(X86::MOV32rm), X86::EAX)
19305 .addReg(TII->getGlobalBaseReg(F))
19306 .addImm(0).addReg(0)
19307 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19308 MI->getOperand(3).getTargetFlags())
19310 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19311 addDirectMem(MIB, X86::EAX);
19312 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19315 MI->eraseFromParent(); // The pseudo instruction is gone now.
19319 MachineBasicBlock *
19320 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19321 MachineBasicBlock *MBB) const {
19322 DebugLoc DL = MI->getDebugLoc();
19323 MachineFunction *MF = MBB->getParent();
19324 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19325 MachineRegisterInfo &MRI = MF->getRegInfo();
19327 const BasicBlock *BB = MBB->getBasicBlock();
19328 MachineFunction::iterator I = MBB;
19331 // Memory Reference
19332 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19333 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19336 unsigned MemOpndSlot = 0;
19338 unsigned CurOp = 0;
19340 DstReg = MI->getOperand(CurOp++).getReg();
19341 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19342 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19343 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19344 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19346 MemOpndSlot = CurOp;
19348 MVT PVT = getPointerTy();
19349 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19350 "Invalid Pointer Size!");
19352 // For v = setjmp(buf), we generate
19355 // buf[LabelOffset] = restoreMBB
19356 // SjLjSetup restoreMBB
19362 // v = phi(main, restore)
19367 MachineBasicBlock *thisMBB = MBB;
19368 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19369 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19370 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19371 MF->insert(I, mainMBB);
19372 MF->insert(I, sinkMBB);
19373 MF->push_back(restoreMBB);
19375 MachineInstrBuilder MIB;
19377 // Transfer the remainder of BB and its successor edges to sinkMBB.
19378 sinkMBB->splice(sinkMBB->begin(), MBB,
19379 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19380 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19383 unsigned PtrStoreOpc = 0;
19384 unsigned LabelReg = 0;
19385 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19386 Reloc::Model RM = MF->getTarget().getRelocationModel();
19387 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19388 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19390 // Prepare IP either in reg or imm.
19391 if (!UseImmLabel) {
19392 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19393 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19394 LabelReg = MRI.createVirtualRegister(PtrRC);
19395 if (Subtarget->is64Bit()) {
19396 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19400 .addMBB(restoreMBB)
19403 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19404 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19405 .addReg(XII->getGlobalBaseReg(MF))
19408 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19412 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19414 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19415 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19416 if (i == X86::AddrDisp)
19417 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19419 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19422 MIB.addReg(LabelReg);
19424 MIB.addMBB(restoreMBB);
19425 MIB.setMemRefs(MMOBegin, MMOEnd);
19427 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19428 .addMBB(restoreMBB);
19430 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19431 MF->getSubtarget().getRegisterInfo());
19432 MIB.addRegMask(RegInfo->getNoPreservedMask());
19433 thisMBB->addSuccessor(mainMBB);
19434 thisMBB->addSuccessor(restoreMBB);
19438 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19439 mainMBB->addSuccessor(sinkMBB);
19442 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19443 TII->get(X86::PHI), DstReg)
19444 .addReg(mainDstReg).addMBB(mainMBB)
19445 .addReg(restoreDstReg).addMBB(restoreMBB);
19448 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19449 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19450 restoreMBB->addSuccessor(sinkMBB);
19452 MI->eraseFromParent();
19456 MachineBasicBlock *
19457 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19458 MachineBasicBlock *MBB) const {
19459 DebugLoc DL = MI->getDebugLoc();
19460 MachineFunction *MF = MBB->getParent();
19461 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19462 MachineRegisterInfo &MRI = MF->getRegInfo();
19464 // Memory Reference
19465 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19466 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19468 MVT PVT = getPointerTy();
19469 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19470 "Invalid Pointer Size!");
19472 const TargetRegisterClass *RC =
19473 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19474 unsigned Tmp = MRI.createVirtualRegister(RC);
19475 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19476 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19477 MF->getSubtarget().getRegisterInfo());
19478 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19479 unsigned SP = RegInfo->getStackRegister();
19481 MachineInstrBuilder MIB;
19483 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19484 const int64_t SPOffset = 2 * PVT.getStoreSize();
19486 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19487 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19490 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19491 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19492 MIB.addOperand(MI->getOperand(i));
19493 MIB.setMemRefs(MMOBegin, MMOEnd);
19495 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19496 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19497 if (i == X86::AddrDisp)
19498 MIB.addDisp(MI->getOperand(i), LabelOffset);
19500 MIB.addOperand(MI->getOperand(i));
19502 MIB.setMemRefs(MMOBegin, MMOEnd);
19504 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19505 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19506 if (i == X86::AddrDisp)
19507 MIB.addDisp(MI->getOperand(i), SPOffset);
19509 MIB.addOperand(MI->getOperand(i));
19511 MIB.setMemRefs(MMOBegin, MMOEnd);
19513 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19515 MI->eraseFromParent();
19519 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19520 // accumulator loops. Writing back to the accumulator allows the coalescer
19521 // to remove extra copies in the loop.
19522 MachineBasicBlock *
19523 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19524 MachineBasicBlock *MBB) const {
19525 MachineOperand &AddendOp = MI->getOperand(3);
19527 // Bail out early if the addend isn't a register - we can't switch these.
19528 if (!AddendOp.isReg())
19531 MachineFunction &MF = *MBB->getParent();
19532 MachineRegisterInfo &MRI = MF.getRegInfo();
19534 // Check whether the addend is defined by a PHI:
19535 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19536 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19537 if (!AddendDef.isPHI())
19540 // Look for the following pattern:
19542 // %addend = phi [%entry, 0], [%loop, %result]
19544 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19548 // %addend = phi [%entry, 0], [%loop, %result]
19550 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19552 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19553 assert(AddendDef.getOperand(i).isReg());
19554 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19555 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19556 if (&PHISrcInst == MI) {
19557 // Found a matching instruction.
19558 unsigned NewFMAOpc = 0;
19559 switch (MI->getOpcode()) {
19560 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19561 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19562 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19563 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19564 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19565 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19566 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19567 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19568 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19569 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19570 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19571 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19572 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19573 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19574 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19575 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19576 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19577 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19578 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19579 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19580 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19581 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19582 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19583 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19584 default: llvm_unreachable("Unrecognized FMA variant.");
19587 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19588 MachineInstrBuilder MIB =
19589 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19590 .addOperand(MI->getOperand(0))
19591 .addOperand(MI->getOperand(3))
19592 .addOperand(MI->getOperand(2))
19593 .addOperand(MI->getOperand(1));
19594 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19595 MI->eraseFromParent();
19602 MachineBasicBlock *
19603 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19604 MachineBasicBlock *BB) const {
19605 switch (MI->getOpcode()) {
19606 default: llvm_unreachable("Unexpected instr type to insert");
19607 case X86::TAILJMPd64:
19608 case X86::TAILJMPr64:
19609 case X86::TAILJMPm64:
19610 llvm_unreachable("TAILJMP64 would not be touched here.");
19611 case X86::TCRETURNdi64:
19612 case X86::TCRETURNri64:
19613 case X86::TCRETURNmi64:
19615 case X86::WIN_ALLOCA:
19616 return EmitLoweredWinAlloca(MI, BB);
19617 case X86::SEG_ALLOCA_32:
19618 case X86::SEG_ALLOCA_64:
19619 return EmitLoweredSegAlloca(MI, BB);
19620 case X86::TLSCall_32:
19621 case X86::TLSCall_64:
19622 return EmitLoweredTLSCall(MI, BB);
19623 case X86::CMOV_GR8:
19624 case X86::CMOV_FR32:
19625 case X86::CMOV_FR64:
19626 case X86::CMOV_V4F32:
19627 case X86::CMOV_V2F64:
19628 case X86::CMOV_V2I64:
19629 case X86::CMOV_V8F32:
19630 case X86::CMOV_V4F64:
19631 case X86::CMOV_V4I64:
19632 case X86::CMOV_V16F32:
19633 case X86::CMOV_V8F64:
19634 case X86::CMOV_V8I64:
19635 case X86::CMOV_GR16:
19636 case X86::CMOV_GR32:
19637 case X86::CMOV_RFP32:
19638 case X86::CMOV_RFP64:
19639 case X86::CMOV_RFP80:
19640 return EmitLoweredSelect(MI, BB);
19642 case X86::FP32_TO_INT16_IN_MEM:
19643 case X86::FP32_TO_INT32_IN_MEM:
19644 case X86::FP32_TO_INT64_IN_MEM:
19645 case X86::FP64_TO_INT16_IN_MEM:
19646 case X86::FP64_TO_INT32_IN_MEM:
19647 case X86::FP64_TO_INT64_IN_MEM:
19648 case X86::FP80_TO_INT16_IN_MEM:
19649 case X86::FP80_TO_INT32_IN_MEM:
19650 case X86::FP80_TO_INT64_IN_MEM: {
19651 MachineFunction *F = BB->getParent();
19652 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19653 DebugLoc DL = MI->getDebugLoc();
19655 // Change the floating point control register to use "round towards zero"
19656 // mode when truncating to an integer value.
19657 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19658 addFrameReference(BuildMI(*BB, MI, DL,
19659 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19661 // Load the old value of the high byte of the control word...
19663 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19664 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19667 // Set the high part to be round to zero...
19668 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19671 // Reload the modified control word now...
19672 addFrameReference(BuildMI(*BB, MI, DL,
19673 TII->get(X86::FLDCW16m)), CWFrameIdx);
19675 // Restore the memory image of control word to original value
19676 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19679 // Get the X86 opcode to use.
19681 switch (MI->getOpcode()) {
19682 default: llvm_unreachable("illegal opcode!");
19683 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19684 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19685 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19686 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19687 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19688 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19689 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19690 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19691 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19695 MachineOperand &Op = MI->getOperand(0);
19697 AM.BaseType = X86AddressMode::RegBase;
19698 AM.Base.Reg = Op.getReg();
19700 AM.BaseType = X86AddressMode::FrameIndexBase;
19701 AM.Base.FrameIndex = Op.getIndex();
19703 Op = MI->getOperand(1);
19705 AM.Scale = Op.getImm();
19706 Op = MI->getOperand(2);
19708 AM.IndexReg = Op.getImm();
19709 Op = MI->getOperand(3);
19710 if (Op.isGlobal()) {
19711 AM.GV = Op.getGlobal();
19713 AM.Disp = Op.getImm();
19715 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19716 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19718 // Reload the original control word now.
19719 addFrameReference(BuildMI(*BB, MI, DL,
19720 TII->get(X86::FLDCW16m)), CWFrameIdx);
19722 MI->eraseFromParent(); // The pseudo instruction is gone now.
19725 // String/text processing lowering.
19726 case X86::PCMPISTRM128REG:
19727 case X86::VPCMPISTRM128REG:
19728 case X86::PCMPISTRM128MEM:
19729 case X86::VPCMPISTRM128MEM:
19730 case X86::PCMPESTRM128REG:
19731 case X86::VPCMPESTRM128REG:
19732 case X86::PCMPESTRM128MEM:
19733 case X86::VPCMPESTRM128MEM:
19734 assert(Subtarget->hasSSE42() &&
19735 "Target must have SSE4.2 or AVX features enabled");
19736 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19738 // String/text processing lowering.
19739 case X86::PCMPISTRIREG:
19740 case X86::VPCMPISTRIREG:
19741 case X86::PCMPISTRIMEM:
19742 case X86::VPCMPISTRIMEM:
19743 case X86::PCMPESTRIREG:
19744 case X86::VPCMPESTRIREG:
19745 case X86::PCMPESTRIMEM:
19746 case X86::VPCMPESTRIMEM:
19747 assert(Subtarget->hasSSE42() &&
19748 "Target must have SSE4.2 or AVX features enabled");
19749 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19751 // Thread synchronization.
19753 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19758 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19760 case X86::VASTART_SAVE_XMM_REGS:
19761 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19763 case X86::VAARG_64:
19764 return EmitVAARG64WithCustomInserter(MI, BB);
19766 case X86::EH_SjLj_SetJmp32:
19767 case X86::EH_SjLj_SetJmp64:
19768 return emitEHSjLjSetJmp(MI, BB);
19770 case X86::EH_SjLj_LongJmp32:
19771 case X86::EH_SjLj_LongJmp64:
19772 return emitEHSjLjLongJmp(MI, BB);
19774 case TargetOpcode::STACKMAP:
19775 case TargetOpcode::PATCHPOINT:
19776 return emitPatchPoint(MI, BB);
19778 case X86::VFMADDPDr213r:
19779 case X86::VFMADDPSr213r:
19780 case X86::VFMADDSDr213r:
19781 case X86::VFMADDSSr213r:
19782 case X86::VFMSUBPDr213r:
19783 case X86::VFMSUBPSr213r:
19784 case X86::VFMSUBSDr213r:
19785 case X86::VFMSUBSSr213r:
19786 case X86::VFNMADDPDr213r:
19787 case X86::VFNMADDPSr213r:
19788 case X86::VFNMADDSDr213r:
19789 case X86::VFNMADDSSr213r:
19790 case X86::VFNMSUBPDr213r:
19791 case X86::VFNMSUBPSr213r:
19792 case X86::VFNMSUBSDr213r:
19793 case X86::VFNMSUBSSr213r:
19794 case X86::VFMADDPDr213rY:
19795 case X86::VFMADDPSr213rY:
19796 case X86::VFMSUBPDr213rY:
19797 case X86::VFMSUBPSr213rY:
19798 case X86::VFNMADDPDr213rY:
19799 case X86::VFNMADDPSr213rY:
19800 case X86::VFNMSUBPDr213rY:
19801 case X86::VFNMSUBPSr213rY:
19802 return emitFMA3Instr(MI, BB);
19806 //===----------------------------------------------------------------------===//
19807 // X86 Optimization Hooks
19808 //===----------------------------------------------------------------------===//
19810 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19813 const SelectionDAG &DAG,
19814 unsigned Depth) const {
19815 unsigned BitWidth = KnownZero.getBitWidth();
19816 unsigned Opc = Op.getOpcode();
19817 assert((Opc >= ISD::BUILTIN_OP_END ||
19818 Opc == ISD::INTRINSIC_WO_CHAIN ||
19819 Opc == ISD::INTRINSIC_W_CHAIN ||
19820 Opc == ISD::INTRINSIC_VOID) &&
19821 "Should use MaskedValueIsZero if you don't know whether Op"
19822 " is a target node!");
19824 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19838 // These nodes' second result is a boolean.
19839 if (Op.getResNo() == 0)
19842 case X86ISD::SETCC:
19843 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19845 case ISD::INTRINSIC_WO_CHAIN: {
19846 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19847 unsigned NumLoBits = 0;
19850 case Intrinsic::x86_sse_movmsk_ps:
19851 case Intrinsic::x86_avx_movmsk_ps_256:
19852 case Intrinsic::x86_sse2_movmsk_pd:
19853 case Intrinsic::x86_avx_movmsk_pd_256:
19854 case Intrinsic::x86_mmx_pmovmskb:
19855 case Intrinsic::x86_sse2_pmovmskb_128:
19856 case Intrinsic::x86_avx2_pmovmskb: {
19857 // High bits of movmskp{s|d}, pmovmskb are known zero.
19859 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19860 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19861 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19862 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19863 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19864 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19865 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19866 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19868 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19877 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19879 const SelectionDAG &,
19880 unsigned Depth) const {
19881 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19882 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19883 return Op.getValueType().getScalarType().getSizeInBits();
19889 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19890 /// node is a GlobalAddress + offset.
19891 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19892 const GlobalValue* &GA,
19893 int64_t &Offset) const {
19894 if (N->getOpcode() == X86ISD::Wrapper) {
19895 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19896 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19897 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19901 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19904 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19905 /// same as extracting the high 128-bit part of 256-bit vector and then
19906 /// inserting the result into the low part of a new 256-bit vector
19907 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19908 EVT VT = SVOp->getValueType(0);
19909 unsigned NumElems = VT.getVectorNumElements();
19911 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19912 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19913 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19914 SVOp->getMaskElt(j) >= 0)
19920 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19921 /// same as extracting the low 128-bit part of 256-bit vector and then
19922 /// inserting the result into the high part of a new 256-bit vector
19923 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19924 EVT VT = SVOp->getValueType(0);
19925 unsigned NumElems = VT.getVectorNumElements();
19927 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19928 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19929 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19930 SVOp->getMaskElt(j) >= 0)
19936 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19937 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19938 TargetLowering::DAGCombinerInfo &DCI,
19939 const X86Subtarget* Subtarget) {
19941 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19942 SDValue V1 = SVOp->getOperand(0);
19943 SDValue V2 = SVOp->getOperand(1);
19944 EVT VT = SVOp->getValueType(0);
19945 unsigned NumElems = VT.getVectorNumElements();
19947 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19948 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19952 // V UNDEF BUILD_VECTOR UNDEF
19954 // CONCAT_VECTOR CONCAT_VECTOR
19957 // RESULT: V + zero extended
19959 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19960 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19961 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19964 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19967 // To match the shuffle mask, the first half of the mask should
19968 // be exactly the first vector, and all the rest a splat with the
19969 // first element of the second one.
19970 for (unsigned i = 0; i != NumElems/2; ++i)
19971 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19972 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19975 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19976 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19977 if (Ld->hasNUsesOfValue(1, 0)) {
19978 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19979 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19981 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19983 Ld->getPointerInfo(),
19984 Ld->getAlignment(),
19985 false/*isVolatile*/, true/*ReadMem*/,
19986 false/*WriteMem*/);
19988 // Make sure the newly-created LOAD is in the same position as Ld in
19989 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19990 // and update uses of Ld's output chain to use the TokenFactor.
19991 if (Ld->hasAnyUseOfValue(1)) {
19992 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19993 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19994 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19995 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19996 SDValue(ResNode.getNode(), 1));
19999 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20003 // Emit a zeroed vector and insert the desired subvector on its
20005 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20006 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20007 return DCI.CombineTo(N, InsV);
20010 //===--------------------------------------------------------------------===//
20011 // Combine some shuffles into subvector extracts and inserts:
20014 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20015 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20016 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20017 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20018 return DCI.CombineTo(N, InsV);
20021 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20022 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20023 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20024 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20025 return DCI.CombineTo(N, InsV);
20031 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20034 /// This is the leaf of the recursive combinine below. When we have found some
20035 /// chain of single-use x86 shuffle instructions and accumulated the combined
20036 /// shuffle mask represented by them, this will try to pattern match that mask
20037 /// into either a single instruction if there is a special purpose instruction
20038 /// for this operation, or into a PSHUFB instruction which is a fully general
20039 /// instruction but should only be used to replace chains over a certain depth.
20040 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20041 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20042 TargetLowering::DAGCombinerInfo &DCI,
20043 const X86Subtarget *Subtarget) {
20044 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20046 // Find the operand that enters the chain. Note that multiple uses are OK
20047 // here, we're not going to remove the operand we find.
20048 SDValue Input = Op.getOperand(0);
20049 while (Input.getOpcode() == ISD::BITCAST)
20050 Input = Input.getOperand(0);
20052 MVT VT = Input.getSimpleValueType();
20053 MVT RootVT = Root.getSimpleValueType();
20056 // Just remove no-op shuffle masks.
20057 if (Mask.size() == 1) {
20058 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20063 // Use the float domain if the operand type is a floating point type.
20064 bool FloatDomain = VT.isFloatingPoint();
20066 // For floating point shuffles, we don't have free copies in the shuffle
20067 // instructions or the ability to load as part of the instruction, so
20068 // canonicalize their shuffles to UNPCK or MOV variants.
20070 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20071 // vectors because it can have a load folded into it that UNPCK cannot. This
20072 // doesn't preclude something switching to the shorter encoding post-RA.
20074 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20075 bool Lo = Mask.equals(0, 0);
20078 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20079 // is no slower than UNPCKLPD but has the option to fold the input operand
20080 // into even an unaligned memory load.
20081 if (Lo && Subtarget->hasSSE3()) {
20082 Shuffle = X86ISD::MOVDDUP;
20083 ShuffleVT = MVT::v2f64;
20085 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20086 // than the UNPCK variants.
20087 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20088 ShuffleVT = MVT::v4f32;
20090 if (Depth == 1 && Root->getOpcode() == Shuffle)
20091 return false; // Nothing to do!
20092 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20093 DCI.AddToWorklist(Op.getNode());
20094 if (Shuffle == X86ISD::MOVDDUP)
20095 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20097 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20098 DCI.AddToWorklist(Op.getNode());
20099 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20103 if (Subtarget->hasSSE3() &&
20104 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20105 bool Lo = Mask.equals(0, 0, 2, 2);
20106 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20107 MVT ShuffleVT = MVT::v4f32;
20108 if (Depth == 1 && Root->getOpcode() == Shuffle)
20109 return false; // Nothing to do!
20110 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20111 DCI.AddToWorklist(Op.getNode());
20112 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20113 DCI.AddToWorklist(Op.getNode());
20114 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20118 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20119 bool Lo = Mask.equals(0, 0, 1, 1);
20120 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20121 MVT ShuffleVT = MVT::v4f32;
20122 if (Depth == 1 && Root->getOpcode() == Shuffle)
20123 return false; // Nothing to do!
20124 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20125 DCI.AddToWorklist(Op.getNode());
20126 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20127 DCI.AddToWorklist(Op.getNode());
20128 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20134 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20135 // variants as none of these have single-instruction variants that are
20136 // superior to the UNPCK formulation.
20137 if (!FloatDomain &&
20138 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20139 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20140 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20141 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20143 bool Lo = Mask[0] == 0;
20144 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20145 if (Depth == 1 && Root->getOpcode() == Shuffle)
20146 return false; // Nothing to do!
20148 switch (Mask.size()) {
20150 ShuffleVT = MVT::v8i16;
20153 ShuffleVT = MVT::v16i8;
20156 llvm_unreachable("Impossible mask size!");
20158 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20159 DCI.AddToWorklist(Op.getNode());
20160 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20161 DCI.AddToWorklist(Op.getNode());
20162 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20167 // Don't try to re-form single instruction chains under any circumstances now
20168 // that we've done encoding canonicalization for them.
20172 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20173 // can replace them with a single PSHUFB instruction profitably. Intel's
20174 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20175 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20176 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20177 SmallVector<SDValue, 16> PSHUFBMask;
20178 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20179 int Ratio = 16 / Mask.size();
20180 for (unsigned i = 0; i < 16; ++i) {
20181 int M = Mask[i / Ratio] != SM_SentinelZero
20182 ? Ratio * Mask[i / Ratio] + i % Ratio
20184 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20186 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20187 DCI.AddToWorklist(Op.getNode());
20188 SDValue PSHUFBMaskOp =
20189 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20190 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20191 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20192 DCI.AddToWorklist(Op.getNode());
20193 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20198 // Failed to find any combines.
20202 /// \brief Fully generic combining of x86 shuffle instructions.
20204 /// This should be the last combine run over the x86 shuffle instructions. Once
20205 /// they have been fully optimized, this will recursively consider all chains
20206 /// of single-use shuffle instructions, build a generic model of the cumulative
20207 /// shuffle operation, and check for simpler instructions which implement this
20208 /// operation. We use this primarily for two purposes:
20210 /// 1) Collapse generic shuffles to specialized single instructions when
20211 /// equivalent. In most cases, this is just an encoding size win, but
20212 /// sometimes we will collapse multiple generic shuffles into a single
20213 /// special-purpose shuffle.
20214 /// 2) Look for sequences of shuffle instructions with 3 or more total
20215 /// instructions, and replace them with the slightly more expensive SSSE3
20216 /// PSHUFB instruction if available. We do this as the last combining step
20217 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20218 /// a suitable short sequence of other instructions. The PHUFB will either
20219 /// use a register or have to read from memory and so is slightly (but only
20220 /// slightly) more expensive than the other shuffle instructions.
20222 /// Because this is inherently a quadratic operation (for each shuffle in
20223 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20224 /// This should never be an issue in practice as the shuffle lowering doesn't
20225 /// produce sequences of more than 8 instructions.
20227 /// FIXME: We will currently miss some cases where the redundant shuffling
20228 /// would simplify under the threshold for PSHUFB formation because of
20229 /// combine-ordering. To fix this, we should do the redundant instruction
20230 /// combining in this recursive walk.
20231 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20232 ArrayRef<int> RootMask,
20233 int Depth, bool HasPSHUFB,
20235 TargetLowering::DAGCombinerInfo &DCI,
20236 const X86Subtarget *Subtarget) {
20237 // Bound the depth of our recursive combine because this is ultimately
20238 // quadratic in nature.
20242 // Directly rip through bitcasts to find the underlying operand.
20243 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20244 Op = Op.getOperand(0);
20246 MVT VT = Op.getSimpleValueType();
20247 if (!VT.isVector())
20248 return false; // Bail if we hit a non-vector.
20249 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20250 // version should be added.
20251 if (VT.getSizeInBits() != 128)
20254 assert(Root.getSimpleValueType().isVector() &&
20255 "Shuffles operate on vector types!");
20256 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20257 "Can only combine shuffles of the same vector register size.");
20259 if (!isTargetShuffle(Op.getOpcode()))
20261 SmallVector<int, 16> OpMask;
20263 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20264 // We only can combine unary shuffles which we can decode the mask for.
20265 if (!HaveMask || !IsUnary)
20268 assert(VT.getVectorNumElements() == OpMask.size() &&
20269 "Different mask size from vector size!");
20270 assert(((RootMask.size() > OpMask.size() &&
20271 RootMask.size() % OpMask.size() == 0) ||
20272 (OpMask.size() > RootMask.size() &&
20273 OpMask.size() % RootMask.size() == 0) ||
20274 OpMask.size() == RootMask.size()) &&
20275 "The smaller number of elements must divide the larger.");
20276 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20277 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20278 assert(((RootRatio == 1 && OpRatio == 1) ||
20279 (RootRatio == 1) != (OpRatio == 1)) &&
20280 "Must not have a ratio for both incoming and op masks!");
20282 SmallVector<int, 16> Mask;
20283 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20285 // Merge this shuffle operation's mask into our accumulated mask. Note that
20286 // this shuffle's mask will be the first applied to the input, followed by the
20287 // root mask to get us all the way to the root value arrangement. The reason
20288 // for this order is that we are recursing up the operation chain.
20289 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20290 int RootIdx = i / RootRatio;
20291 if (RootMask[RootIdx] == SM_SentinelZero) {
20292 // This is a zero-ed lane, we're done.
20293 Mask.push_back(SM_SentinelZero);
20297 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20298 int OpIdx = RootMaskedIdx / OpRatio;
20299 if (OpMask[OpIdx] == SM_SentinelZero) {
20300 // The incoming lanes are zero, it doesn't matter which ones we are using.
20301 Mask.push_back(SM_SentinelZero);
20305 // Ok, we have non-zero lanes, map them through.
20306 Mask.push_back(OpMask[OpIdx] * OpRatio +
20307 RootMaskedIdx % OpRatio);
20310 // See if we can recurse into the operand to combine more things.
20311 switch (Op.getOpcode()) {
20312 case X86ISD::PSHUFB:
20314 case X86ISD::PSHUFD:
20315 case X86ISD::PSHUFHW:
20316 case X86ISD::PSHUFLW:
20317 if (Op.getOperand(0).hasOneUse() &&
20318 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20319 HasPSHUFB, DAG, DCI, Subtarget))
20323 case X86ISD::UNPCKL:
20324 case X86ISD::UNPCKH:
20325 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20326 // We can't check for single use, we have to check that this shuffle is the only user.
20327 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20328 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20329 HasPSHUFB, DAG, DCI, Subtarget))
20334 // Minor canonicalization of the accumulated shuffle mask to make it easier
20335 // to match below. All this does is detect masks with squential pairs of
20336 // elements, and shrink them to the half-width mask. It does this in a loop
20337 // so it will reduce the size of the mask to the minimal width mask which
20338 // performs an equivalent shuffle.
20339 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20340 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20341 Mask[i] = Mask[2 * i] / 2;
20342 Mask.resize(Mask.size() / 2);
20345 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20349 /// \brief Get the PSHUF-style mask from PSHUF node.
20351 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20352 /// PSHUF-style masks that can be reused with such instructions.
20353 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20354 SmallVector<int, 4> Mask;
20356 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20360 switch (N.getOpcode()) {
20361 case X86ISD::PSHUFD:
20363 case X86ISD::PSHUFLW:
20366 case X86ISD::PSHUFHW:
20367 Mask.erase(Mask.begin(), Mask.begin() + 4);
20368 for (int &M : Mask)
20372 llvm_unreachable("No valid shuffle instruction found!");
20376 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20378 /// We walk up the chain and look for a combinable shuffle, skipping over
20379 /// shuffles that we could hoist this shuffle's transformation past without
20380 /// altering anything.
20382 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20384 TargetLowering::DAGCombinerInfo &DCI) {
20385 assert(N.getOpcode() == X86ISD::PSHUFD &&
20386 "Called with something other than an x86 128-bit half shuffle!");
20389 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20390 // of the shuffles in the chain so that we can form a fresh chain to replace
20392 SmallVector<SDValue, 8> Chain;
20393 SDValue V = N.getOperand(0);
20394 for (; V.hasOneUse(); V = V.getOperand(0)) {
20395 switch (V.getOpcode()) {
20397 return SDValue(); // Nothing combined!
20400 // Skip bitcasts as we always know the type for the target specific
20404 case X86ISD::PSHUFD:
20405 // Found another dword shuffle.
20408 case X86ISD::PSHUFLW:
20409 // Check that the low words (being shuffled) are the identity in the
20410 // dword shuffle, and the high words are self-contained.
20411 if (Mask[0] != 0 || Mask[1] != 1 ||
20412 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20415 Chain.push_back(V);
20418 case X86ISD::PSHUFHW:
20419 // Check that the high words (being shuffled) are the identity in the
20420 // dword shuffle, and the low words are self-contained.
20421 if (Mask[2] != 2 || Mask[3] != 3 ||
20422 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20425 Chain.push_back(V);
20428 case X86ISD::UNPCKL:
20429 case X86ISD::UNPCKH:
20430 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20431 // shuffle into a preceding word shuffle.
20432 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20435 // Search for a half-shuffle which we can combine with.
20436 unsigned CombineOp =
20437 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20438 if (V.getOperand(0) != V.getOperand(1) ||
20439 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20441 Chain.push_back(V);
20442 V = V.getOperand(0);
20444 switch (V.getOpcode()) {
20446 return SDValue(); // Nothing to combine.
20448 case X86ISD::PSHUFLW:
20449 case X86ISD::PSHUFHW:
20450 if (V.getOpcode() == CombineOp)
20453 Chain.push_back(V);
20457 V = V.getOperand(0);
20461 } while (V.hasOneUse());
20464 // Break out of the loop if we break out of the switch.
20468 if (!V.hasOneUse())
20469 // We fell out of the loop without finding a viable combining instruction.
20472 // Merge this node's mask and our incoming mask.
20473 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20474 for (int &M : Mask)
20476 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20477 getV4X86ShuffleImm8ForMask(Mask, DAG));
20479 // Rebuild the chain around this new shuffle.
20480 while (!Chain.empty()) {
20481 SDValue W = Chain.pop_back_val();
20483 if (V.getValueType() != W.getOperand(0).getValueType())
20484 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20486 switch (W.getOpcode()) {
20488 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20490 case X86ISD::UNPCKL:
20491 case X86ISD::UNPCKH:
20492 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20495 case X86ISD::PSHUFD:
20496 case X86ISD::PSHUFLW:
20497 case X86ISD::PSHUFHW:
20498 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20502 if (V.getValueType() != N.getValueType())
20503 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20505 // Return the new chain to replace N.
20509 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20511 /// We walk up the chain, skipping shuffles of the other half and looking
20512 /// through shuffles which switch halves trying to find a shuffle of the same
20513 /// pair of dwords.
20514 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20516 TargetLowering::DAGCombinerInfo &DCI) {
20518 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20519 "Called with something other than an x86 128-bit half shuffle!");
20521 unsigned CombineOpcode = N.getOpcode();
20523 // Walk up a single-use chain looking for a combinable shuffle.
20524 SDValue V = N.getOperand(0);
20525 for (; V.hasOneUse(); V = V.getOperand(0)) {
20526 switch (V.getOpcode()) {
20528 return false; // Nothing combined!
20531 // Skip bitcasts as we always know the type for the target specific
20535 case X86ISD::PSHUFLW:
20536 case X86ISD::PSHUFHW:
20537 if (V.getOpcode() == CombineOpcode)
20540 // Other-half shuffles are no-ops.
20543 // Break out of the loop if we break out of the switch.
20547 if (!V.hasOneUse())
20548 // We fell out of the loop without finding a viable combining instruction.
20551 // Combine away the bottom node as its shuffle will be accumulated into
20552 // a preceding shuffle.
20553 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20555 // Record the old value.
20558 // Merge this node's mask and our incoming mask (adjusted to account for all
20559 // the pshufd instructions encountered).
20560 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20561 for (int &M : Mask)
20563 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20564 getV4X86ShuffleImm8ForMask(Mask, DAG));
20566 // Check that the shuffles didn't cancel each other out. If not, we need to
20567 // combine to the new one.
20569 // Replace the combinable shuffle with the combined one, updating all users
20570 // so that we re-evaluate the chain here.
20571 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20576 /// \brief Try to combine x86 target specific shuffles.
20577 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20578 TargetLowering::DAGCombinerInfo &DCI,
20579 const X86Subtarget *Subtarget) {
20581 MVT VT = N.getSimpleValueType();
20582 SmallVector<int, 4> Mask;
20584 switch (N.getOpcode()) {
20585 case X86ISD::PSHUFD:
20586 case X86ISD::PSHUFLW:
20587 case X86ISD::PSHUFHW:
20588 Mask = getPSHUFShuffleMask(N);
20589 assert(Mask.size() == 4);
20595 // Nuke no-op shuffles that show up after combining.
20596 if (isNoopShuffleMask(Mask))
20597 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20599 // Look for simplifications involving one or two shuffle instructions.
20600 SDValue V = N.getOperand(0);
20601 switch (N.getOpcode()) {
20604 case X86ISD::PSHUFLW:
20605 case X86ISD::PSHUFHW:
20606 assert(VT == MVT::v8i16);
20609 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20610 return SDValue(); // We combined away this shuffle, so we're done.
20612 // See if this reduces to a PSHUFD which is no more expensive and can
20613 // combine with more operations.
20614 if (canWidenShuffleElements(Mask)) {
20615 int DMask[] = {-1, -1, -1, -1};
20616 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20617 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20618 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20619 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20620 DCI.AddToWorklist(V.getNode());
20621 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20622 getV4X86ShuffleImm8ForMask(DMask, DAG));
20623 DCI.AddToWorklist(V.getNode());
20624 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20627 // Look for shuffle patterns which can be implemented as a single unpack.
20628 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20629 // only works when we have a PSHUFD followed by two half-shuffles.
20630 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20631 (V.getOpcode() == X86ISD::PSHUFLW ||
20632 V.getOpcode() == X86ISD::PSHUFHW) &&
20633 V.getOpcode() != N.getOpcode() &&
20635 SDValue D = V.getOperand(0);
20636 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20637 D = D.getOperand(0);
20638 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20639 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20640 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20641 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20642 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20644 for (int i = 0; i < 4; ++i) {
20645 WordMask[i + NOffset] = Mask[i] + NOffset;
20646 WordMask[i + VOffset] = VMask[i] + VOffset;
20648 // Map the word mask through the DWord mask.
20650 for (int i = 0; i < 8; ++i)
20651 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20652 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20653 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20654 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20655 std::begin(UnpackLoMask)) ||
20656 std::equal(std::begin(MappedMask), std::end(MappedMask),
20657 std::begin(UnpackHiMask))) {
20658 // We can replace all three shuffles with an unpack.
20659 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20660 DCI.AddToWorklist(V.getNode());
20661 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20663 DL, MVT::v8i16, V, V);
20670 case X86ISD::PSHUFD:
20671 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20680 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20682 /// We combine this directly on the abstract vector shuffle nodes so it is
20683 /// easier to generically match. We also insert dummy vector shuffle nodes for
20684 /// the operands which explicitly discard the lanes which are unused by this
20685 /// operation to try to flow through the rest of the combiner the fact that
20686 /// they're unused.
20687 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20689 EVT VT = N->getValueType(0);
20691 // We only handle target-independent shuffles.
20692 // FIXME: It would be easy and harmless to use the target shuffle mask
20693 // extraction tool to support more.
20694 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20697 auto *SVN = cast<ShuffleVectorSDNode>(N);
20698 ArrayRef<int> Mask = SVN->getMask();
20699 SDValue V1 = N->getOperand(0);
20700 SDValue V2 = N->getOperand(1);
20702 // We require the first shuffle operand to be the SUB node, and the second to
20703 // be the ADD node.
20704 // FIXME: We should support the commuted patterns.
20705 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20708 // If there are other uses of these operations we can't fold them.
20709 if (!V1->hasOneUse() || !V2->hasOneUse())
20712 // Ensure that both operations have the same operands. Note that we can
20713 // commute the FADD operands.
20714 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20715 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20716 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20719 // We're looking for blends between FADD and FSUB nodes. We insist on these
20720 // nodes being lined up in a specific expected pattern.
20721 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20722 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20723 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20726 // Only specific types are legal at this point, assert so we notice if and
20727 // when these change.
20728 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20729 VT == MVT::v4f64) &&
20730 "Unknown vector type encountered!");
20732 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20735 /// PerformShuffleCombine - Performs several different shuffle combines.
20736 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20737 TargetLowering::DAGCombinerInfo &DCI,
20738 const X86Subtarget *Subtarget) {
20740 SDValue N0 = N->getOperand(0);
20741 SDValue N1 = N->getOperand(1);
20742 EVT VT = N->getValueType(0);
20744 // Don't create instructions with illegal types after legalize types has run.
20745 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20746 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20749 // If we have legalized the vector types, look for blends of FADD and FSUB
20750 // nodes that we can fuse into an ADDSUB node.
20751 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20752 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20755 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20756 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20757 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20758 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20760 // During Type Legalization, when promoting illegal vector types,
20761 // the backend might introduce new shuffle dag nodes and bitcasts.
20763 // This code performs the following transformation:
20764 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20765 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20767 // We do this only if both the bitcast and the BINOP dag nodes have
20768 // one use. Also, perform this transformation only if the new binary
20769 // operation is legal. This is to avoid introducing dag nodes that
20770 // potentially need to be further expanded (or custom lowered) into a
20771 // less optimal sequence of dag nodes.
20772 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20773 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20774 N0.getOpcode() == ISD::BITCAST) {
20775 SDValue BC0 = N0.getOperand(0);
20776 EVT SVT = BC0.getValueType();
20777 unsigned Opcode = BC0.getOpcode();
20778 unsigned NumElts = VT.getVectorNumElements();
20780 if (BC0.hasOneUse() && SVT.isVector() &&
20781 SVT.getVectorNumElements() * 2 == NumElts &&
20782 TLI.isOperationLegal(Opcode, VT)) {
20783 bool CanFold = false;
20795 unsigned SVTNumElts = SVT.getVectorNumElements();
20796 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20797 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20798 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20799 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20800 CanFold = SVOp->getMaskElt(i) < 0;
20803 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20804 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20805 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20806 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20811 // Only handle 128 wide vector from here on.
20812 if (!VT.is128BitVector())
20815 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20816 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20817 // consecutive, non-overlapping, and in the right order.
20818 SmallVector<SDValue, 16> Elts;
20819 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20820 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20822 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20826 if (isTargetShuffle(N->getOpcode())) {
20828 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20829 if (Shuffle.getNode())
20832 // Try recursively combining arbitrary sequences of x86 shuffle
20833 // instructions into higher-order shuffles. We do this after combining
20834 // specific PSHUF instruction sequences into their minimal form so that we
20835 // can evaluate how many specialized shuffle instructions are involved in
20836 // a particular chain.
20837 SmallVector<int, 1> NonceMask; // Just a placeholder.
20838 NonceMask.push_back(0);
20839 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20840 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20842 return SDValue(); // This routine will use CombineTo to replace N.
20848 /// PerformTruncateCombine - Converts truncate operation to
20849 /// a sequence of vector shuffle operations.
20850 /// It is possible when we truncate 256-bit vector to 128-bit vector
20851 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20852 TargetLowering::DAGCombinerInfo &DCI,
20853 const X86Subtarget *Subtarget) {
20857 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20858 /// specific shuffle of a load can be folded into a single element load.
20859 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20860 /// shuffles have been customed lowered so we need to handle those here.
20861 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20862 TargetLowering::DAGCombinerInfo &DCI) {
20863 if (DCI.isBeforeLegalizeOps())
20866 SDValue InVec = N->getOperand(0);
20867 SDValue EltNo = N->getOperand(1);
20869 if (!isa<ConstantSDNode>(EltNo))
20872 EVT VT = InVec.getValueType();
20874 if (InVec.getOpcode() == ISD::BITCAST) {
20875 // Don't duplicate a load with other uses.
20876 if (!InVec.hasOneUse())
20878 EVT BCVT = InVec.getOperand(0).getValueType();
20879 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20881 InVec = InVec.getOperand(0);
20884 if (!isTargetShuffle(InVec.getOpcode()))
20887 // Don't duplicate a load with other uses.
20888 if (!InVec.hasOneUse())
20891 SmallVector<int, 16> ShuffleMask;
20893 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20897 // Select the input vector, guarding against out of range extract vector.
20898 unsigned NumElems = VT.getVectorNumElements();
20899 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20900 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20901 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20902 : InVec.getOperand(1);
20904 // If inputs to shuffle are the same for both ops, then allow 2 uses
20905 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20907 if (LdNode.getOpcode() == ISD::BITCAST) {
20908 // Don't duplicate a load with other uses.
20909 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20912 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20913 LdNode = LdNode.getOperand(0);
20916 if (!ISD::isNormalLoad(LdNode.getNode()))
20919 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20921 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20924 EVT EltVT = N->getValueType(0);
20925 // If there's a bitcast before the shuffle, check if the load type and
20926 // alignment is valid.
20927 unsigned Align = LN0->getAlignment();
20928 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20929 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20930 EltVT.getTypeForEVT(*DAG.getContext()));
20932 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20935 // All checks match so transform back to vector_shuffle so that DAG combiner
20936 // can finish the job
20939 // Create shuffle node taking into account the case that its a unary shuffle
20940 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20941 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20942 InVec.getOperand(0), Shuffle,
20944 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20945 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20949 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20950 /// generation and convert it from being a bunch of shuffles and extracts
20951 /// to a simple store and scalar loads to extract the elements.
20952 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20953 TargetLowering::DAGCombinerInfo &DCI) {
20954 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20955 if (NewOp.getNode())
20958 SDValue InputVector = N->getOperand(0);
20960 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20961 // from mmx to v2i32 has a single usage.
20962 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20963 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20964 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20965 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20966 N->getValueType(0),
20967 InputVector.getNode()->getOperand(0));
20969 // Only operate on vectors of 4 elements, where the alternative shuffling
20970 // gets to be more expensive.
20971 if (InputVector.getValueType() != MVT::v4i32)
20974 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20975 // single use which is a sign-extend or zero-extend, and all elements are
20977 SmallVector<SDNode *, 4> Uses;
20978 unsigned ExtractedElements = 0;
20979 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20980 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20981 if (UI.getUse().getResNo() != InputVector.getResNo())
20984 SDNode *Extract = *UI;
20985 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20988 if (Extract->getValueType(0) != MVT::i32)
20990 if (!Extract->hasOneUse())
20992 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20993 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20995 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20998 // Record which element was extracted.
20999 ExtractedElements |=
21000 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21002 Uses.push_back(Extract);
21005 // If not all the elements were used, this may not be worthwhile.
21006 if (ExtractedElements != 15)
21009 // Ok, we've now decided to do the transformation.
21010 SDLoc dl(InputVector);
21012 // Store the value to a temporary stack slot.
21013 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21014 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21015 MachinePointerInfo(), false, false, 0);
21017 // Replace each use (extract) with a load of the appropriate element.
21018 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21019 UE = Uses.end(); UI != UE; ++UI) {
21020 SDNode *Extract = *UI;
21022 // cOMpute the element's address.
21023 SDValue Idx = Extract->getOperand(1);
21025 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21026 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21027 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21028 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21030 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21031 StackPtr, OffsetVal);
21033 // Load the scalar.
21034 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21035 ScalarAddr, MachinePointerInfo(),
21036 false, false, false, 0);
21038 // Replace the exact with the load.
21039 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21042 // The replacement was made in place; don't return anything.
21046 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21047 static std::pair<unsigned, bool>
21048 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21049 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21050 if (!VT.isVector())
21051 return std::make_pair(0, false);
21053 bool NeedSplit = false;
21054 switch (VT.getSimpleVT().SimpleTy) {
21055 default: return std::make_pair(0, false);
21059 if (!Subtarget->hasAVX2())
21061 if (!Subtarget->hasAVX())
21062 return std::make_pair(0, false);
21067 if (!Subtarget->hasSSE2())
21068 return std::make_pair(0, false);
21071 // SSE2 has only a small subset of the operations.
21072 bool hasUnsigned = Subtarget->hasSSE41() ||
21073 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21074 bool hasSigned = Subtarget->hasSSE41() ||
21075 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21077 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21080 // Check for x CC y ? x : y.
21081 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21082 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21087 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21090 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21093 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21096 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21098 // Check for x CC y ? y : x -- a min/max with reversed arms.
21099 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21100 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21105 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21108 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21111 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21114 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21118 return std::make_pair(Opc, NeedSplit);
21122 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21123 const X86Subtarget *Subtarget) {
21125 SDValue Cond = N->getOperand(0);
21126 SDValue LHS = N->getOperand(1);
21127 SDValue RHS = N->getOperand(2);
21129 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21130 SDValue CondSrc = Cond->getOperand(0);
21131 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21132 Cond = CondSrc->getOperand(0);
21135 MVT VT = N->getSimpleValueType(0);
21136 MVT EltVT = VT.getVectorElementType();
21137 unsigned NumElems = VT.getVectorNumElements();
21138 // There is no blend with immediate in AVX-512.
21139 if (VT.is512BitVector())
21142 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21144 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21147 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21150 // A vselect where all conditions and data are constants can be optimized into
21151 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21152 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21153 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21156 unsigned MaskValue = 0;
21157 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21160 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21161 for (unsigned i = 0; i < NumElems; ++i) {
21162 // Be sure we emit undef where we can.
21163 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21164 ShuffleMask[i] = -1;
21166 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21169 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21172 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21174 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21175 TargetLowering::DAGCombinerInfo &DCI,
21176 const X86Subtarget *Subtarget) {
21178 SDValue Cond = N->getOperand(0);
21179 // Get the LHS/RHS of the select.
21180 SDValue LHS = N->getOperand(1);
21181 SDValue RHS = N->getOperand(2);
21182 EVT VT = LHS.getValueType();
21183 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21185 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21186 // instructions match the semantics of the common C idiom x<y?x:y but not
21187 // x<=y?x:y, because of how they handle negative zero (which can be
21188 // ignored in unsafe-math mode).
21189 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21190 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21191 (Subtarget->hasSSE2() ||
21192 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21193 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21195 unsigned Opcode = 0;
21196 // Check for x CC y ? x : y.
21197 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21198 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21202 // Converting this to a min would handle NaNs incorrectly, and swapping
21203 // the operands would cause it to handle comparisons between positive
21204 // and negative zero incorrectly.
21205 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21206 if (!DAG.getTarget().Options.UnsafeFPMath &&
21207 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21209 std::swap(LHS, RHS);
21211 Opcode = X86ISD::FMIN;
21214 // Converting this to a min would handle comparisons between positive
21215 // and negative zero incorrectly.
21216 if (!DAG.getTarget().Options.UnsafeFPMath &&
21217 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21219 Opcode = X86ISD::FMIN;
21222 // Converting this to a min would handle both negative zeros and NaNs
21223 // incorrectly, but we can swap the operands to fix both.
21224 std::swap(LHS, RHS);
21228 Opcode = X86ISD::FMIN;
21232 // Converting this to a max would handle comparisons between positive
21233 // and negative zero incorrectly.
21234 if (!DAG.getTarget().Options.UnsafeFPMath &&
21235 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21237 Opcode = X86ISD::FMAX;
21240 // Converting this to a max would handle NaNs incorrectly, and swapping
21241 // the operands would cause it to handle comparisons between positive
21242 // and negative zero incorrectly.
21243 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21244 if (!DAG.getTarget().Options.UnsafeFPMath &&
21245 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21247 std::swap(LHS, RHS);
21249 Opcode = X86ISD::FMAX;
21252 // Converting this to a max would handle both negative zeros and NaNs
21253 // incorrectly, but we can swap the operands to fix both.
21254 std::swap(LHS, RHS);
21258 Opcode = X86ISD::FMAX;
21261 // Check for x CC y ? y : x -- a min/max with reversed arms.
21262 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21263 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21267 // Converting this to a min would handle comparisons between positive
21268 // and negative zero incorrectly, and swapping the operands would
21269 // cause it to handle NaNs incorrectly.
21270 if (!DAG.getTarget().Options.UnsafeFPMath &&
21271 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21272 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21274 std::swap(LHS, RHS);
21276 Opcode = X86ISD::FMIN;
21279 // Converting this to a min would handle NaNs incorrectly.
21280 if (!DAG.getTarget().Options.UnsafeFPMath &&
21281 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21283 Opcode = X86ISD::FMIN;
21286 // Converting this to a min would handle both negative zeros and NaNs
21287 // incorrectly, but we can swap the operands to fix both.
21288 std::swap(LHS, RHS);
21292 Opcode = X86ISD::FMIN;
21296 // Converting this to a max would handle NaNs incorrectly.
21297 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21299 Opcode = X86ISD::FMAX;
21302 // Converting this to a max would handle comparisons between positive
21303 // and negative zero incorrectly, and swapping the operands would
21304 // cause it to handle NaNs incorrectly.
21305 if (!DAG.getTarget().Options.UnsafeFPMath &&
21306 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21307 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21309 std::swap(LHS, RHS);
21311 Opcode = X86ISD::FMAX;
21314 // Converting this to a max would handle both negative zeros and NaNs
21315 // incorrectly, but we can swap the operands to fix both.
21316 std::swap(LHS, RHS);
21320 Opcode = X86ISD::FMAX;
21326 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21329 EVT CondVT = Cond.getValueType();
21330 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21331 CondVT.getVectorElementType() == MVT::i1) {
21332 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21333 // lowering on KNL. In this case we convert it to
21334 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21335 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21336 // Since SKX these selects have a proper lowering.
21337 EVT OpVT = LHS.getValueType();
21338 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21339 (OpVT.getVectorElementType() == MVT::i8 ||
21340 OpVT.getVectorElementType() == MVT::i16) &&
21341 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21342 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21343 DCI.AddToWorklist(Cond.getNode());
21344 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21347 // If this is a select between two integer constants, try to do some
21349 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21350 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21351 // Don't do this for crazy integer types.
21352 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21353 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21354 // so that TrueC (the true value) is larger than FalseC.
21355 bool NeedsCondInvert = false;
21357 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21358 // Efficiently invertible.
21359 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21360 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21361 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21362 NeedsCondInvert = true;
21363 std::swap(TrueC, FalseC);
21366 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21367 if (FalseC->getAPIntValue() == 0 &&
21368 TrueC->getAPIntValue().isPowerOf2()) {
21369 if (NeedsCondInvert) // Invert the condition if needed.
21370 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21371 DAG.getConstant(1, Cond.getValueType()));
21373 // Zero extend the condition if needed.
21374 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21376 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21377 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21378 DAG.getConstant(ShAmt, MVT::i8));
21381 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21382 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21383 if (NeedsCondInvert) // Invert the condition if needed.
21384 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21385 DAG.getConstant(1, Cond.getValueType()));
21387 // Zero extend the condition if needed.
21388 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21389 FalseC->getValueType(0), Cond);
21390 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21391 SDValue(FalseC, 0));
21394 // Optimize cases that will turn into an LEA instruction. This requires
21395 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21396 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21397 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21398 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21400 bool isFastMultiplier = false;
21402 switch ((unsigned char)Diff) {
21404 case 1: // result = add base, cond
21405 case 2: // result = lea base( , cond*2)
21406 case 3: // result = lea base(cond, cond*2)
21407 case 4: // result = lea base( , cond*4)
21408 case 5: // result = lea base(cond, cond*4)
21409 case 8: // result = lea base( , cond*8)
21410 case 9: // result = lea base(cond, cond*8)
21411 isFastMultiplier = true;
21416 if (isFastMultiplier) {
21417 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21418 if (NeedsCondInvert) // Invert the condition if needed.
21419 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21420 DAG.getConstant(1, Cond.getValueType()));
21422 // Zero extend the condition if needed.
21423 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21425 // Scale the condition by the difference.
21427 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21428 DAG.getConstant(Diff, Cond.getValueType()));
21430 // Add the base if non-zero.
21431 if (FalseC->getAPIntValue() != 0)
21432 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21433 SDValue(FalseC, 0));
21440 // Canonicalize max and min:
21441 // (x > y) ? x : y -> (x >= y) ? x : y
21442 // (x < y) ? x : y -> (x <= y) ? x : y
21443 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21444 // the need for an extra compare
21445 // against zero. e.g.
21446 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21448 // testl %edi, %edi
21450 // cmovgl %edi, %eax
21454 // cmovsl %eax, %edi
21455 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21456 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21457 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21458 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21463 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21464 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21465 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21466 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21471 // Early exit check
21472 if (!TLI.isTypeLegal(VT))
21475 // Match VSELECTs into subs with unsigned saturation.
21476 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21477 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21478 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21479 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21480 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21482 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21483 // left side invert the predicate to simplify logic below.
21485 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21487 CC = ISD::getSetCCInverse(CC, true);
21488 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21492 if (Other.getNode() && Other->getNumOperands() == 2 &&
21493 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21494 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21495 SDValue CondRHS = Cond->getOperand(1);
21497 // Look for a general sub with unsigned saturation first.
21498 // x >= y ? x-y : 0 --> subus x, y
21499 // x > y ? x-y : 0 --> subus x, y
21500 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21501 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21502 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21504 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21505 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21506 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21507 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21508 // If the RHS is a constant we have to reverse the const
21509 // canonicalization.
21510 // x > C-1 ? x+-C : 0 --> subus x, C
21511 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21512 CondRHSConst->getAPIntValue() ==
21513 (-OpRHSConst->getAPIntValue() - 1))
21514 return DAG.getNode(
21515 X86ISD::SUBUS, DL, VT, OpLHS,
21516 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21518 // Another special case: If C was a sign bit, the sub has been
21519 // canonicalized into a xor.
21520 // FIXME: Would it be better to use computeKnownBits to determine
21521 // whether it's safe to decanonicalize the xor?
21522 // x s< 0 ? x^C : 0 --> subus x, C
21523 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21524 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21525 OpRHSConst->getAPIntValue().isSignBit())
21526 // Note that we have to rebuild the RHS constant here to ensure we
21527 // don't rely on particular values of undef lanes.
21528 return DAG.getNode(
21529 X86ISD::SUBUS, DL, VT, OpLHS,
21530 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21535 // Try to match a min/max vector operation.
21536 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21537 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21538 unsigned Opc = ret.first;
21539 bool NeedSplit = ret.second;
21541 if (Opc && NeedSplit) {
21542 unsigned NumElems = VT.getVectorNumElements();
21543 // Extract the LHS vectors
21544 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21545 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21547 // Extract the RHS vectors
21548 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21549 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21551 // Create min/max for each subvector
21552 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21553 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21555 // Merge the result
21556 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21558 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21561 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21562 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21563 // Check if SETCC has already been promoted
21564 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21565 // Check that condition value type matches vselect operand type
21568 assert(Cond.getValueType().isVector() &&
21569 "vector select expects a vector selector!");
21571 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21572 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21574 if (!TValIsAllOnes && !FValIsAllZeros) {
21575 // Try invert the condition if true value is not all 1s and false value
21577 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21578 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21580 if (TValIsAllZeros || FValIsAllOnes) {
21581 SDValue CC = Cond.getOperand(2);
21582 ISD::CondCode NewCC =
21583 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21584 Cond.getOperand(0).getValueType().isInteger());
21585 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21586 std::swap(LHS, RHS);
21587 TValIsAllOnes = FValIsAllOnes;
21588 FValIsAllZeros = TValIsAllZeros;
21592 if (TValIsAllOnes || FValIsAllZeros) {
21595 if (TValIsAllOnes && FValIsAllZeros)
21597 else if (TValIsAllOnes)
21598 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21599 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21600 else if (FValIsAllZeros)
21601 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21602 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21604 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21608 // Try to fold this VSELECT into a MOVSS/MOVSD
21609 if (N->getOpcode() == ISD::VSELECT &&
21610 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21611 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21612 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21613 bool CanFold = false;
21614 unsigned NumElems = Cond.getNumOperands();
21618 if (isZero(Cond.getOperand(0))) {
21621 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21622 // fold (vselect <0,-1> -> (movsd A, B)
21623 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21624 CanFold = isAllOnes(Cond.getOperand(i));
21625 } else if (isAllOnes(Cond.getOperand(0))) {
21629 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21630 // fold (vselect <-1,0> -> (movsd B, A)
21631 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21632 CanFold = isZero(Cond.getOperand(i));
21636 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21637 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21638 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21641 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21642 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21643 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21644 // (v2i64 (bitcast B)))))
21646 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21647 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21648 // (v2f64 (bitcast B)))))
21650 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21651 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21652 // (v2i64 (bitcast A)))))
21654 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21655 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21656 // (v2f64 (bitcast A)))))
21658 CanFold = (isZero(Cond.getOperand(0)) &&
21659 isZero(Cond.getOperand(1)) &&
21660 isAllOnes(Cond.getOperand(2)) &&
21661 isAllOnes(Cond.getOperand(3)));
21663 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21664 isAllOnes(Cond.getOperand(1)) &&
21665 isZero(Cond.getOperand(2)) &&
21666 isZero(Cond.getOperand(3))) {
21668 std::swap(LHS, RHS);
21672 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21673 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21674 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21675 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21677 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21683 // If we know that this node is legal then we know that it is going to be
21684 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21685 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21686 // to simplify previous instructions.
21687 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21688 !DCI.isBeforeLegalize() &&
21689 // We explicitly check against v8i16 and v16i16 because, although
21690 // they're marked as Custom, they might only be legal when Cond is a
21691 // build_vector of constants. This will be taken care in a later
21693 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21694 VT != MVT::v8i16)) {
21695 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21697 // Don't optimize vector selects that map to mask-registers.
21701 // Check all uses of that condition operand to check whether it will be
21702 // consumed by non-BLEND instructions, which may depend on all bits are set
21704 for (SDNode::use_iterator I = Cond->use_begin(),
21705 E = Cond->use_end(); I != E; ++I)
21706 if (I->getOpcode() != ISD::VSELECT)
21707 // TODO: Add other opcodes eventually lowered into BLEND.
21710 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21711 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21713 APInt KnownZero, KnownOne;
21714 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21715 DCI.isBeforeLegalizeOps());
21716 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21717 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21718 DCI.CommitTargetLoweringOpt(TLO);
21721 // We should generate an X86ISD::BLENDI from a vselect if its argument
21722 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21723 // constants. This specific pattern gets generated when we split a
21724 // selector for a 512 bit vector in a machine without AVX512 (but with
21725 // 256-bit vectors), during legalization:
21727 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21729 // Iff we find this pattern and the build_vectors are built from
21730 // constants, we translate the vselect into a shuffle_vector that we
21731 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21732 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21733 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21734 if (Shuffle.getNode())
21741 // Check whether a boolean test is testing a boolean value generated by
21742 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21745 // Simplify the following patterns:
21746 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21747 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21748 // to (Op EFLAGS Cond)
21750 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21751 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21752 // to (Op EFLAGS !Cond)
21754 // where Op could be BRCOND or CMOV.
21756 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21757 // Quit if not CMP and SUB with its value result used.
21758 if (Cmp.getOpcode() != X86ISD::CMP &&
21759 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21762 // Quit if not used as a boolean value.
21763 if (CC != X86::COND_E && CC != X86::COND_NE)
21766 // Check CMP operands. One of them should be 0 or 1 and the other should be
21767 // an SetCC or extended from it.
21768 SDValue Op1 = Cmp.getOperand(0);
21769 SDValue Op2 = Cmp.getOperand(1);
21772 const ConstantSDNode* C = nullptr;
21773 bool needOppositeCond = (CC == X86::COND_E);
21774 bool checkAgainstTrue = false; // Is it a comparison against 1?
21776 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21778 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21780 else // Quit if all operands are not constants.
21783 if (C->getZExtValue() == 1) {
21784 needOppositeCond = !needOppositeCond;
21785 checkAgainstTrue = true;
21786 } else if (C->getZExtValue() != 0)
21787 // Quit if the constant is neither 0 or 1.
21790 bool truncatedToBoolWithAnd = false;
21791 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21792 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21793 SetCC.getOpcode() == ISD::TRUNCATE ||
21794 SetCC.getOpcode() == ISD::AND) {
21795 if (SetCC.getOpcode() == ISD::AND) {
21797 ConstantSDNode *CS;
21798 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21799 CS->getZExtValue() == 1)
21801 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21802 CS->getZExtValue() == 1)
21806 SetCC = SetCC.getOperand(OpIdx);
21807 truncatedToBoolWithAnd = true;
21809 SetCC = SetCC.getOperand(0);
21812 switch (SetCC.getOpcode()) {
21813 case X86ISD::SETCC_CARRY:
21814 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21815 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21816 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21817 // truncated to i1 using 'and'.
21818 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21820 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21821 "Invalid use of SETCC_CARRY!");
21823 case X86ISD::SETCC:
21824 // Set the condition code or opposite one if necessary.
21825 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21826 if (needOppositeCond)
21827 CC = X86::GetOppositeBranchCondition(CC);
21828 return SetCC.getOperand(1);
21829 case X86ISD::CMOV: {
21830 // Check whether false/true value has canonical one, i.e. 0 or 1.
21831 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21832 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21833 // Quit if true value is not a constant.
21836 // Quit if false value is not a constant.
21838 SDValue Op = SetCC.getOperand(0);
21839 // Skip 'zext' or 'trunc' node.
21840 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21841 Op.getOpcode() == ISD::TRUNCATE)
21842 Op = Op.getOperand(0);
21843 // A special case for rdrand/rdseed, where 0 is set if false cond is
21845 if ((Op.getOpcode() != X86ISD::RDRAND &&
21846 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21849 // Quit if false value is not the constant 0 or 1.
21850 bool FValIsFalse = true;
21851 if (FVal && FVal->getZExtValue() != 0) {
21852 if (FVal->getZExtValue() != 1)
21854 // If FVal is 1, opposite cond is needed.
21855 needOppositeCond = !needOppositeCond;
21856 FValIsFalse = false;
21858 // Quit if TVal is not the constant opposite of FVal.
21859 if (FValIsFalse && TVal->getZExtValue() != 1)
21861 if (!FValIsFalse && TVal->getZExtValue() != 0)
21863 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21864 if (needOppositeCond)
21865 CC = X86::GetOppositeBranchCondition(CC);
21866 return SetCC.getOperand(3);
21873 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21874 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21875 TargetLowering::DAGCombinerInfo &DCI,
21876 const X86Subtarget *Subtarget) {
21879 // If the flag operand isn't dead, don't touch this CMOV.
21880 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21883 SDValue FalseOp = N->getOperand(0);
21884 SDValue TrueOp = N->getOperand(1);
21885 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21886 SDValue Cond = N->getOperand(3);
21888 if (CC == X86::COND_E || CC == X86::COND_NE) {
21889 switch (Cond.getOpcode()) {
21893 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21894 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21895 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21901 Flags = checkBoolTestSetCCCombine(Cond, CC);
21902 if (Flags.getNode() &&
21903 // Extra check as FCMOV only supports a subset of X86 cond.
21904 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21905 SDValue Ops[] = { FalseOp, TrueOp,
21906 DAG.getConstant(CC, MVT::i8), Flags };
21907 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21910 // If this is a select between two integer constants, try to do some
21911 // optimizations. Note that the operands are ordered the opposite of SELECT
21913 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21914 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21915 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21916 // larger than FalseC (the false value).
21917 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21918 CC = X86::GetOppositeBranchCondition(CC);
21919 std::swap(TrueC, FalseC);
21920 std::swap(TrueOp, FalseOp);
21923 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21924 // This is efficient for any integer data type (including i8/i16) and
21926 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21927 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21928 DAG.getConstant(CC, MVT::i8), Cond);
21930 // Zero extend the condition if needed.
21931 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21933 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21934 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21935 DAG.getConstant(ShAmt, MVT::i8));
21936 if (N->getNumValues() == 2) // Dead flag value?
21937 return DCI.CombineTo(N, Cond, SDValue());
21941 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21942 // for any integer data type, including i8/i16.
21943 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21944 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21945 DAG.getConstant(CC, MVT::i8), Cond);
21947 // Zero extend the condition if needed.
21948 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21949 FalseC->getValueType(0), Cond);
21950 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21951 SDValue(FalseC, 0));
21953 if (N->getNumValues() == 2) // Dead flag value?
21954 return DCI.CombineTo(N, Cond, SDValue());
21958 // Optimize cases that will turn into an LEA instruction. This requires
21959 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21960 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21961 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21962 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21964 bool isFastMultiplier = false;
21966 switch ((unsigned char)Diff) {
21968 case 1: // result = add base, cond
21969 case 2: // result = lea base( , cond*2)
21970 case 3: // result = lea base(cond, cond*2)
21971 case 4: // result = lea base( , cond*4)
21972 case 5: // result = lea base(cond, cond*4)
21973 case 8: // result = lea base( , cond*8)
21974 case 9: // result = lea base(cond, cond*8)
21975 isFastMultiplier = true;
21980 if (isFastMultiplier) {
21981 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21982 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21983 DAG.getConstant(CC, MVT::i8), Cond);
21984 // Zero extend the condition if needed.
21985 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21987 // Scale the condition by the difference.
21989 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21990 DAG.getConstant(Diff, Cond.getValueType()));
21992 // Add the base if non-zero.
21993 if (FalseC->getAPIntValue() != 0)
21994 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21995 SDValue(FalseC, 0));
21996 if (N->getNumValues() == 2) // Dead flag value?
21997 return DCI.CombineTo(N, Cond, SDValue());
22004 // Handle these cases:
22005 // (select (x != c), e, c) -> select (x != c), e, x),
22006 // (select (x == c), c, e) -> select (x == c), x, e)
22007 // where the c is an integer constant, and the "select" is the combination
22008 // of CMOV and CMP.
22010 // The rationale for this change is that the conditional-move from a constant
22011 // needs two instructions, however, conditional-move from a register needs
22012 // only one instruction.
22014 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22015 // some instruction-combining opportunities. This opt needs to be
22016 // postponed as late as possible.
22018 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22019 // the DCI.xxxx conditions are provided to postpone the optimization as
22020 // late as possible.
22022 ConstantSDNode *CmpAgainst = nullptr;
22023 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22024 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22025 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22027 if (CC == X86::COND_NE &&
22028 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22029 CC = X86::GetOppositeBranchCondition(CC);
22030 std::swap(TrueOp, FalseOp);
22033 if (CC == X86::COND_E &&
22034 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22035 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22036 DAG.getConstant(CC, MVT::i8), Cond };
22037 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22045 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22046 const X86Subtarget *Subtarget) {
22047 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22049 default: return SDValue();
22050 // SSE/AVX/AVX2 blend intrinsics.
22051 case Intrinsic::x86_avx2_pblendvb:
22052 case Intrinsic::x86_avx2_pblendw:
22053 case Intrinsic::x86_avx2_pblendd_128:
22054 case Intrinsic::x86_avx2_pblendd_256:
22055 // Don't try to simplify this intrinsic if we don't have AVX2.
22056 if (!Subtarget->hasAVX2())
22059 case Intrinsic::x86_avx_blend_pd_256:
22060 case Intrinsic::x86_avx_blend_ps_256:
22061 case Intrinsic::x86_avx_blendv_pd_256:
22062 case Intrinsic::x86_avx_blendv_ps_256:
22063 // Don't try to simplify this intrinsic if we don't have AVX.
22064 if (!Subtarget->hasAVX())
22067 case Intrinsic::x86_sse41_pblendw:
22068 case Intrinsic::x86_sse41_blendpd:
22069 case Intrinsic::x86_sse41_blendps:
22070 case Intrinsic::x86_sse41_blendvps:
22071 case Intrinsic::x86_sse41_blendvpd:
22072 case Intrinsic::x86_sse41_pblendvb: {
22073 SDValue Op0 = N->getOperand(1);
22074 SDValue Op1 = N->getOperand(2);
22075 SDValue Mask = N->getOperand(3);
22077 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22078 if (!Subtarget->hasSSE41())
22081 // fold (blend A, A, Mask) -> A
22084 // fold (blend A, B, allZeros) -> A
22085 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22087 // fold (blend A, B, allOnes) -> B
22088 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22091 // Simplify the case where the mask is a constant i32 value.
22092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22093 if (C->isNullValue())
22095 if (C->isAllOnesValue())
22102 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22103 case Intrinsic::x86_sse2_psrai_w:
22104 case Intrinsic::x86_sse2_psrai_d:
22105 case Intrinsic::x86_avx2_psrai_w:
22106 case Intrinsic::x86_avx2_psrai_d:
22107 case Intrinsic::x86_sse2_psra_w:
22108 case Intrinsic::x86_sse2_psra_d:
22109 case Intrinsic::x86_avx2_psra_w:
22110 case Intrinsic::x86_avx2_psra_d: {
22111 SDValue Op0 = N->getOperand(1);
22112 SDValue Op1 = N->getOperand(2);
22113 EVT VT = Op0.getValueType();
22114 assert(VT.isVector() && "Expected a vector type!");
22116 if (isa<BuildVectorSDNode>(Op1))
22117 Op1 = Op1.getOperand(0);
22119 if (!isa<ConstantSDNode>(Op1))
22122 EVT SVT = VT.getVectorElementType();
22123 unsigned SVTBits = SVT.getSizeInBits();
22125 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22126 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22127 uint64_t ShAmt = C.getZExtValue();
22129 // Don't try to convert this shift into a ISD::SRA if the shift
22130 // count is bigger than or equal to the element size.
22131 if (ShAmt >= SVTBits)
22134 // Trivial case: if the shift count is zero, then fold this
22135 // into the first operand.
22139 // Replace this packed shift intrinsic with a target independent
22141 SDValue Splat = DAG.getConstant(C, VT);
22142 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22147 /// PerformMulCombine - Optimize a single multiply with constant into two
22148 /// in order to implement it with two cheaper instructions, e.g.
22149 /// LEA + SHL, LEA + LEA.
22150 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22151 TargetLowering::DAGCombinerInfo &DCI) {
22152 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22155 EVT VT = N->getValueType(0);
22156 if (VT != MVT::i64)
22159 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22162 uint64_t MulAmt = C->getZExtValue();
22163 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22166 uint64_t MulAmt1 = 0;
22167 uint64_t MulAmt2 = 0;
22168 if ((MulAmt % 9) == 0) {
22170 MulAmt2 = MulAmt / 9;
22171 } else if ((MulAmt % 5) == 0) {
22173 MulAmt2 = MulAmt / 5;
22174 } else if ((MulAmt % 3) == 0) {
22176 MulAmt2 = MulAmt / 3;
22179 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22182 if (isPowerOf2_64(MulAmt2) &&
22183 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22184 // If second multiplifer is pow2, issue it first. We want the multiply by
22185 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22187 std::swap(MulAmt1, MulAmt2);
22190 if (isPowerOf2_64(MulAmt1))
22191 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22192 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22194 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22195 DAG.getConstant(MulAmt1, VT));
22197 if (isPowerOf2_64(MulAmt2))
22198 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22199 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22201 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22202 DAG.getConstant(MulAmt2, VT));
22204 // Do not add new nodes to DAG combiner worklist.
22205 DCI.CombineTo(N, NewMul, false);
22210 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22211 SDValue N0 = N->getOperand(0);
22212 SDValue N1 = N->getOperand(1);
22213 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22214 EVT VT = N0.getValueType();
22216 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22217 // since the result of setcc_c is all zero's or all ones.
22218 if (VT.isInteger() && !VT.isVector() &&
22219 N1C && N0.getOpcode() == ISD::AND &&
22220 N0.getOperand(1).getOpcode() == ISD::Constant) {
22221 SDValue N00 = N0.getOperand(0);
22222 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22223 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22224 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22225 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22226 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22227 APInt ShAmt = N1C->getAPIntValue();
22228 Mask = Mask.shl(ShAmt);
22230 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22231 N00, DAG.getConstant(Mask, VT));
22235 // Hardware support for vector shifts is sparse which makes us scalarize the
22236 // vector operations in many cases. Also, on sandybridge ADD is faster than
22238 // (shl V, 1) -> add V,V
22239 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22240 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22241 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22242 // We shift all of the values by one. In many cases we do not have
22243 // hardware support for this operation. This is better expressed as an ADD
22245 if (N1SplatC->getZExtValue() == 1)
22246 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22252 /// \brief Returns a vector of 0s if the node in input is a vector logical
22253 /// shift by a constant amount which is known to be bigger than or equal
22254 /// to the vector element size in bits.
22255 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22256 const X86Subtarget *Subtarget) {
22257 EVT VT = N->getValueType(0);
22259 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22260 (!Subtarget->hasInt256() ||
22261 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22264 SDValue Amt = N->getOperand(1);
22266 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22267 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22268 APInt ShiftAmt = AmtSplat->getAPIntValue();
22269 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22271 // SSE2/AVX2 logical shifts always return a vector of 0s
22272 // if the shift amount is bigger than or equal to
22273 // the element size. The constant shift amount will be
22274 // encoded as a 8-bit immediate.
22275 if (ShiftAmt.trunc(8).uge(MaxAmount))
22276 return getZeroVector(VT, Subtarget, DAG, DL);
22282 /// PerformShiftCombine - Combine shifts.
22283 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22284 TargetLowering::DAGCombinerInfo &DCI,
22285 const X86Subtarget *Subtarget) {
22286 if (N->getOpcode() == ISD::SHL) {
22287 SDValue V = PerformSHLCombine(N, DAG);
22288 if (V.getNode()) return V;
22291 if (N->getOpcode() != ISD::SRA) {
22292 // Try to fold this logical shift into a zero vector.
22293 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22294 if (V.getNode()) return V;
22300 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22301 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22302 // and friends. Likewise for OR -> CMPNEQSS.
22303 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22304 TargetLowering::DAGCombinerInfo &DCI,
22305 const X86Subtarget *Subtarget) {
22308 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22309 // we're requiring SSE2 for both.
22310 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22311 SDValue N0 = N->getOperand(0);
22312 SDValue N1 = N->getOperand(1);
22313 SDValue CMP0 = N0->getOperand(1);
22314 SDValue CMP1 = N1->getOperand(1);
22317 // The SETCCs should both refer to the same CMP.
22318 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22321 SDValue CMP00 = CMP0->getOperand(0);
22322 SDValue CMP01 = CMP0->getOperand(1);
22323 EVT VT = CMP00.getValueType();
22325 if (VT == MVT::f32 || VT == MVT::f64) {
22326 bool ExpectingFlags = false;
22327 // Check for any users that want flags:
22328 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22329 !ExpectingFlags && UI != UE; ++UI)
22330 switch (UI->getOpcode()) {
22335 ExpectingFlags = true;
22337 case ISD::CopyToReg:
22338 case ISD::SIGN_EXTEND:
22339 case ISD::ZERO_EXTEND:
22340 case ISD::ANY_EXTEND:
22344 if (!ExpectingFlags) {
22345 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22346 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22348 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22349 X86::CondCode tmp = cc0;
22354 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22355 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22356 // FIXME: need symbolic constants for these magic numbers.
22357 // See X86ATTInstPrinter.cpp:printSSECC().
22358 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22359 if (Subtarget->hasAVX512()) {
22360 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22361 CMP01, DAG.getConstant(x86cc, MVT::i8));
22362 if (N->getValueType(0) != MVT::i1)
22363 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22367 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22368 CMP00.getValueType(), CMP00, CMP01,
22369 DAG.getConstant(x86cc, MVT::i8));
22371 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22372 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22374 if (is64BitFP && !Subtarget->is64Bit()) {
22375 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22376 // 64-bit integer, since that's not a legal type. Since
22377 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22378 // bits, but can do this little dance to extract the lowest 32 bits
22379 // and work with those going forward.
22380 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22382 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22384 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22385 Vector32, DAG.getIntPtrConstant(0));
22389 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22390 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22391 DAG.getConstant(1, IntVT));
22392 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22393 return OneBitOfTruth;
22401 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22402 /// so it can be folded inside ANDNP.
22403 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22404 EVT VT = N->getValueType(0);
22406 // Match direct AllOnes for 128 and 256-bit vectors
22407 if (ISD::isBuildVectorAllOnes(N))
22410 // Look through a bit convert.
22411 if (N->getOpcode() == ISD::BITCAST)
22412 N = N->getOperand(0).getNode();
22414 // Sometimes the operand may come from a insert_subvector building a 256-bit
22416 if (VT.is256BitVector() &&
22417 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22418 SDValue V1 = N->getOperand(0);
22419 SDValue V2 = N->getOperand(1);
22421 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22422 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22423 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22424 ISD::isBuildVectorAllOnes(V2.getNode()))
22431 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22432 // register. In most cases we actually compare or select YMM-sized registers
22433 // and mixing the two types creates horrible code. This method optimizes
22434 // some of the transition sequences.
22435 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22436 TargetLowering::DAGCombinerInfo &DCI,
22437 const X86Subtarget *Subtarget) {
22438 EVT VT = N->getValueType(0);
22439 if (!VT.is256BitVector())
22442 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22443 N->getOpcode() == ISD::ZERO_EXTEND ||
22444 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22446 SDValue Narrow = N->getOperand(0);
22447 EVT NarrowVT = Narrow->getValueType(0);
22448 if (!NarrowVT.is128BitVector())
22451 if (Narrow->getOpcode() != ISD::XOR &&
22452 Narrow->getOpcode() != ISD::AND &&
22453 Narrow->getOpcode() != ISD::OR)
22456 SDValue N0 = Narrow->getOperand(0);
22457 SDValue N1 = Narrow->getOperand(1);
22460 // The Left side has to be a trunc.
22461 if (N0.getOpcode() != ISD::TRUNCATE)
22464 // The type of the truncated inputs.
22465 EVT WideVT = N0->getOperand(0)->getValueType(0);
22469 // The right side has to be a 'trunc' or a constant vector.
22470 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22471 ConstantSDNode *RHSConstSplat = nullptr;
22472 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22473 RHSConstSplat = RHSBV->getConstantSplatNode();
22474 if (!RHSTrunc && !RHSConstSplat)
22477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22479 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22482 // Set N0 and N1 to hold the inputs to the new wide operation.
22483 N0 = N0->getOperand(0);
22484 if (RHSConstSplat) {
22485 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22486 SDValue(RHSConstSplat, 0));
22487 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22488 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22489 } else if (RHSTrunc) {
22490 N1 = N1->getOperand(0);
22493 // Generate the wide operation.
22494 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22495 unsigned Opcode = N->getOpcode();
22497 case ISD::ANY_EXTEND:
22499 case ISD::ZERO_EXTEND: {
22500 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22501 APInt Mask = APInt::getAllOnesValue(InBits);
22502 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22503 return DAG.getNode(ISD::AND, DL, VT,
22504 Op, DAG.getConstant(Mask, VT));
22506 case ISD::SIGN_EXTEND:
22507 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22508 Op, DAG.getValueType(NarrowVT));
22510 llvm_unreachable("Unexpected opcode");
22514 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22515 TargetLowering::DAGCombinerInfo &DCI,
22516 const X86Subtarget *Subtarget) {
22517 EVT VT = N->getValueType(0);
22518 if (DCI.isBeforeLegalizeOps())
22521 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22525 // Create BEXTR instructions
22526 // BEXTR is ((X >> imm) & (2**size-1))
22527 if (VT == MVT::i32 || VT == MVT::i64) {
22528 SDValue N0 = N->getOperand(0);
22529 SDValue N1 = N->getOperand(1);
22532 // Check for BEXTR.
22533 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22534 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22535 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22536 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22537 if (MaskNode && ShiftNode) {
22538 uint64_t Mask = MaskNode->getZExtValue();
22539 uint64_t Shift = ShiftNode->getZExtValue();
22540 if (isMask_64(Mask)) {
22541 uint64_t MaskSize = CountPopulation_64(Mask);
22542 if (Shift + MaskSize <= VT.getSizeInBits())
22543 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22544 DAG.getConstant(Shift | (MaskSize << 8), VT));
22552 // Want to form ANDNP nodes:
22553 // 1) In the hopes of then easily combining them with OR and AND nodes
22554 // to form PBLEND/PSIGN.
22555 // 2) To match ANDN packed intrinsics
22556 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22559 SDValue N0 = N->getOperand(0);
22560 SDValue N1 = N->getOperand(1);
22563 // Check LHS for vnot
22564 if (N0.getOpcode() == ISD::XOR &&
22565 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22566 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22567 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22569 // Check RHS for vnot
22570 if (N1.getOpcode() == ISD::XOR &&
22571 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22572 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22573 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22578 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22579 TargetLowering::DAGCombinerInfo &DCI,
22580 const X86Subtarget *Subtarget) {
22581 if (DCI.isBeforeLegalizeOps())
22584 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22588 SDValue N0 = N->getOperand(0);
22589 SDValue N1 = N->getOperand(1);
22590 EVT VT = N->getValueType(0);
22592 // look for psign/blend
22593 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22594 if (!Subtarget->hasSSSE3() ||
22595 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22598 // Canonicalize pandn to RHS
22599 if (N0.getOpcode() == X86ISD::ANDNP)
22601 // or (and (m, y), (pandn m, x))
22602 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22603 SDValue Mask = N1.getOperand(0);
22604 SDValue X = N1.getOperand(1);
22606 if (N0.getOperand(0) == Mask)
22607 Y = N0.getOperand(1);
22608 if (N0.getOperand(1) == Mask)
22609 Y = N0.getOperand(0);
22611 // Check to see if the mask appeared in both the AND and ANDNP and
22615 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22616 // Look through mask bitcast.
22617 if (Mask.getOpcode() == ISD::BITCAST)
22618 Mask = Mask.getOperand(0);
22619 if (X.getOpcode() == ISD::BITCAST)
22620 X = X.getOperand(0);
22621 if (Y.getOpcode() == ISD::BITCAST)
22622 Y = Y.getOperand(0);
22624 EVT MaskVT = Mask.getValueType();
22626 // Validate that the Mask operand is a vector sra node.
22627 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22628 // there is no psrai.b
22629 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22630 unsigned SraAmt = ~0;
22631 if (Mask.getOpcode() == ISD::SRA) {
22632 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22633 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22634 SraAmt = AmtConst->getZExtValue();
22635 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22636 SDValue SraC = Mask.getOperand(1);
22637 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22639 if ((SraAmt + 1) != EltBits)
22644 // Now we know we at least have a plendvb with the mask val. See if
22645 // we can form a psignb/w/d.
22646 // psign = x.type == y.type == mask.type && y = sub(0, x);
22647 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22648 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22649 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22650 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22651 "Unsupported VT for PSIGN");
22652 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22653 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22655 // PBLENDVB only available on SSE 4.1
22656 if (!Subtarget->hasSSE41())
22659 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22661 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22662 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22663 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22664 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22665 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22669 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22672 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22673 MachineFunction &MF = DAG.getMachineFunction();
22674 bool OptForSize = MF.getFunction()->getAttributes().
22675 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22677 // SHLD/SHRD instructions have lower register pressure, but on some
22678 // platforms they have higher latency than the equivalent
22679 // series of shifts/or that would otherwise be generated.
22680 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22681 // have higher latencies and we are not optimizing for size.
22682 if (!OptForSize && Subtarget->isSHLDSlow())
22685 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22687 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22689 if (!N0.hasOneUse() || !N1.hasOneUse())
22692 SDValue ShAmt0 = N0.getOperand(1);
22693 if (ShAmt0.getValueType() != MVT::i8)
22695 SDValue ShAmt1 = N1.getOperand(1);
22696 if (ShAmt1.getValueType() != MVT::i8)
22698 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22699 ShAmt0 = ShAmt0.getOperand(0);
22700 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22701 ShAmt1 = ShAmt1.getOperand(0);
22704 unsigned Opc = X86ISD::SHLD;
22705 SDValue Op0 = N0.getOperand(0);
22706 SDValue Op1 = N1.getOperand(0);
22707 if (ShAmt0.getOpcode() == ISD::SUB) {
22708 Opc = X86ISD::SHRD;
22709 std::swap(Op0, Op1);
22710 std::swap(ShAmt0, ShAmt1);
22713 unsigned Bits = VT.getSizeInBits();
22714 if (ShAmt1.getOpcode() == ISD::SUB) {
22715 SDValue Sum = ShAmt1.getOperand(0);
22716 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22717 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22718 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22719 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22720 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22721 return DAG.getNode(Opc, DL, VT,
22723 DAG.getNode(ISD::TRUNCATE, DL,
22726 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22727 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22729 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22730 return DAG.getNode(Opc, DL, VT,
22731 N0.getOperand(0), N1.getOperand(0),
22732 DAG.getNode(ISD::TRUNCATE, DL,
22739 // Generate NEG and CMOV for integer abs.
22740 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22741 EVT VT = N->getValueType(0);
22743 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22744 // 8-bit integer abs to NEG and CMOV.
22745 if (VT.isInteger() && VT.getSizeInBits() == 8)
22748 SDValue N0 = N->getOperand(0);
22749 SDValue N1 = N->getOperand(1);
22752 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22753 // and change it to SUB and CMOV.
22754 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22755 N0.getOpcode() == ISD::ADD &&
22756 N0.getOperand(1) == N1 &&
22757 N1.getOpcode() == ISD::SRA &&
22758 N1.getOperand(0) == N0.getOperand(0))
22759 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22760 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22761 // Generate SUB & CMOV.
22762 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22763 DAG.getConstant(0, VT), N0.getOperand(0));
22765 SDValue Ops[] = { N0.getOperand(0), Neg,
22766 DAG.getConstant(X86::COND_GE, MVT::i8),
22767 SDValue(Neg.getNode(), 1) };
22768 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22773 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22774 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22775 TargetLowering::DAGCombinerInfo &DCI,
22776 const X86Subtarget *Subtarget) {
22777 if (DCI.isBeforeLegalizeOps())
22780 if (Subtarget->hasCMov()) {
22781 SDValue RV = performIntegerAbsCombine(N, DAG);
22789 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22790 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22791 TargetLowering::DAGCombinerInfo &DCI,
22792 const X86Subtarget *Subtarget) {
22793 LoadSDNode *Ld = cast<LoadSDNode>(N);
22794 EVT RegVT = Ld->getValueType(0);
22795 EVT MemVT = Ld->getMemoryVT();
22797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22799 // On Sandybridge unaligned 256bit loads are inefficient.
22800 ISD::LoadExtType Ext = Ld->getExtensionType();
22801 unsigned Alignment = Ld->getAlignment();
22802 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22803 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22804 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22805 unsigned NumElems = RegVT.getVectorNumElements();
22809 SDValue Ptr = Ld->getBasePtr();
22810 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22812 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22814 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22815 Ld->getPointerInfo(), Ld->isVolatile(),
22816 Ld->isNonTemporal(), Ld->isInvariant(),
22818 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22819 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22820 Ld->getPointerInfo(), Ld->isVolatile(),
22821 Ld->isNonTemporal(), Ld->isInvariant(),
22822 std::min(16U, Alignment));
22823 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22825 Load2.getValue(1));
22827 SDValue NewVec = DAG.getUNDEF(RegVT);
22828 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22829 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22830 return DCI.CombineTo(N, NewVec, TF, true);
22836 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22837 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22838 const X86Subtarget *Subtarget) {
22839 StoreSDNode *St = cast<StoreSDNode>(N);
22840 EVT VT = St->getValue().getValueType();
22841 EVT StVT = St->getMemoryVT();
22843 SDValue StoredVal = St->getOperand(1);
22844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22846 // If we are saving a concatenation of two XMM registers, perform two stores.
22847 // On Sandy Bridge, 256-bit memory operations are executed by two
22848 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22849 // memory operation.
22850 unsigned Alignment = St->getAlignment();
22851 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22852 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22853 StVT == VT && !IsAligned) {
22854 unsigned NumElems = VT.getVectorNumElements();
22858 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22859 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22861 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22862 SDValue Ptr0 = St->getBasePtr();
22863 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22865 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22866 St->getPointerInfo(), St->isVolatile(),
22867 St->isNonTemporal(), Alignment);
22868 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22869 St->getPointerInfo(), St->isVolatile(),
22870 St->isNonTemporal(),
22871 std::min(16U, Alignment));
22872 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22875 // Optimize trunc store (of multiple scalars) to shuffle and store.
22876 // First, pack all of the elements in one place. Next, store to memory
22877 // in fewer chunks.
22878 if (St->isTruncatingStore() && VT.isVector()) {
22879 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22880 unsigned NumElems = VT.getVectorNumElements();
22881 assert(StVT != VT && "Cannot truncate to the same type");
22882 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22883 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22885 // From, To sizes and ElemCount must be pow of two
22886 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22887 // We are going to use the original vector elt for storing.
22888 // Accumulated smaller vector elements must be a multiple of the store size.
22889 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22891 unsigned SizeRatio = FromSz / ToSz;
22893 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22895 // Create a type on which we perform the shuffle
22896 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22897 StVT.getScalarType(), NumElems*SizeRatio);
22899 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22901 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22902 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22903 for (unsigned i = 0; i != NumElems; ++i)
22904 ShuffleVec[i] = i * SizeRatio;
22906 // Can't shuffle using an illegal type.
22907 if (!TLI.isTypeLegal(WideVecVT))
22910 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22911 DAG.getUNDEF(WideVecVT),
22913 // At this point all of the data is stored at the bottom of the
22914 // register. We now need to save it to mem.
22916 // Find the largest store unit
22917 MVT StoreType = MVT::i8;
22918 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22919 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22920 MVT Tp = (MVT::SimpleValueType)tp;
22921 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22925 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22926 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22927 (64 <= NumElems * ToSz))
22928 StoreType = MVT::f64;
22930 // Bitcast the original vector into a vector of store-size units
22931 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22932 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22933 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22934 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22935 SmallVector<SDValue, 8> Chains;
22936 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22937 TLI.getPointerTy());
22938 SDValue Ptr = St->getBasePtr();
22940 // Perform one or more big stores into memory.
22941 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22942 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22943 StoreType, ShuffWide,
22944 DAG.getIntPtrConstant(i));
22945 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22946 St->getPointerInfo(), St->isVolatile(),
22947 St->isNonTemporal(), St->getAlignment());
22948 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22949 Chains.push_back(Ch);
22952 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22955 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22956 // the FP state in cases where an emms may be missing.
22957 // A preferable solution to the general problem is to figure out the right
22958 // places to insert EMMS. This qualifies as a quick hack.
22960 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22961 if (VT.getSizeInBits() != 64)
22964 const Function *F = DAG.getMachineFunction().getFunction();
22965 bool NoImplicitFloatOps = F->getAttributes().
22966 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22967 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22968 && Subtarget->hasSSE2();
22969 if ((VT.isVector() ||
22970 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22971 isa<LoadSDNode>(St->getValue()) &&
22972 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22973 St->getChain().hasOneUse() && !St->isVolatile()) {
22974 SDNode* LdVal = St->getValue().getNode();
22975 LoadSDNode *Ld = nullptr;
22976 int TokenFactorIndex = -1;
22977 SmallVector<SDValue, 8> Ops;
22978 SDNode* ChainVal = St->getChain().getNode();
22979 // Must be a store of a load. We currently handle two cases: the load
22980 // is a direct child, and it's under an intervening TokenFactor. It is
22981 // possible to dig deeper under nested TokenFactors.
22982 if (ChainVal == LdVal)
22983 Ld = cast<LoadSDNode>(St->getChain());
22984 else if (St->getValue().hasOneUse() &&
22985 ChainVal->getOpcode() == ISD::TokenFactor) {
22986 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22987 if (ChainVal->getOperand(i).getNode() == LdVal) {
22988 TokenFactorIndex = i;
22989 Ld = cast<LoadSDNode>(St->getValue());
22991 Ops.push_back(ChainVal->getOperand(i));
22995 if (!Ld || !ISD::isNormalLoad(Ld))
22998 // If this is not the MMX case, i.e. we are just turning i64 load/store
22999 // into f64 load/store, avoid the transformation if there are multiple
23000 // uses of the loaded value.
23001 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23006 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23007 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23009 if (Subtarget->is64Bit() || F64IsLegal) {
23010 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23011 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23012 Ld->getPointerInfo(), Ld->isVolatile(),
23013 Ld->isNonTemporal(), Ld->isInvariant(),
23014 Ld->getAlignment());
23015 SDValue NewChain = NewLd.getValue(1);
23016 if (TokenFactorIndex != -1) {
23017 Ops.push_back(NewChain);
23018 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23020 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23021 St->getPointerInfo(),
23022 St->isVolatile(), St->isNonTemporal(),
23023 St->getAlignment());
23026 // Otherwise, lower to two pairs of 32-bit loads / stores.
23027 SDValue LoAddr = Ld->getBasePtr();
23028 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23029 DAG.getConstant(4, MVT::i32));
23031 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23032 Ld->getPointerInfo(),
23033 Ld->isVolatile(), Ld->isNonTemporal(),
23034 Ld->isInvariant(), Ld->getAlignment());
23035 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23036 Ld->getPointerInfo().getWithOffset(4),
23037 Ld->isVolatile(), Ld->isNonTemporal(),
23039 MinAlign(Ld->getAlignment(), 4));
23041 SDValue NewChain = LoLd.getValue(1);
23042 if (TokenFactorIndex != -1) {
23043 Ops.push_back(LoLd);
23044 Ops.push_back(HiLd);
23045 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23048 LoAddr = St->getBasePtr();
23049 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23050 DAG.getConstant(4, MVT::i32));
23052 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23053 St->getPointerInfo(),
23054 St->isVolatile(), St->isNonTemporal(),
23055 St->getAlignment());
23056 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23057 St->getPointerInfo().getWithOffset(4),
23059 St->isNonTemporal(),
23060 MinAlign(St->getAlignment(), 4));
23061 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23066 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23067 /// and return the operands for the horizontal operation in LHS and RHS. A
23068 /// horizontal operation performs the binary operation on successive elements
23069 /// of its first operand, then on successive elements of its second operand,
23070 /// returning the resulting values in a vector. For example, if
23071 /// A = < float a0, float a1, float a2, float a3 >
23073 /// B = < float b0, float b1, float b2, float b3 >
23074 /// then the result of doing a horizontal operation on A and B is
23075 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23076 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23077 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23078 /// set to A, RHS to B, and the routine returns 'true'.
23079 /// Note that the binary operation should have the property that if one of the
23080 /// operands is UNDEF then the result is UNDEF.
23081 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23082 // Look for the following pattern: if
23083 // A = < float a0, float a1, float a2, float a3 >
23084 // B = < float b0, float b1, float b2, float b3 >
23086 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23087 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23088 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23089 // which is A horizontal-op B.
23091 // At least one of the operands should be a vector shuffle.
23092 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23093 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23096 MVT VT = LHS.getSimpleValueType();
23098 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23099 "Unsupported vector type for horizontal add/sub");
23101 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23102 // operate independently on 128-bit lanes.
23103 unsigned NumElts = VT.getVectorNumElements();
23104 unsigned NumLanes = VT.getSizeInBits()/128;
23105 unsigned NumLaneElts = NumElts / NumLanes;
23106 assert((NumLaneElts % 2 == 0) &&
23107 "Vector type should have an even number of elements in each lane");
23108 unsigned HalfLaneElts = NumLaneElts/2;
23110 // View LHS in the form
23111 // LHS = VECTOR_SHUFFLE A, B, LMask
23112 // If LHS is not a shuffle then pretend it is the shuffle
23113 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23114 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23117 SmallVector<int, 16> LMask(NumElts);
23118 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23119 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23120 A = LHS.getOperand(0);
23121 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23122 B = LHS.getOperand(1);
23123 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23124 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23126 if (LHS.getOpcode() != ISD::UNDEF)
23128 for (unsigned i = 0; i != NumElts; ++i)
23132 // Likewise, view RHS in the form
23133 // RHS = VECTOR_SHUFFLE C, D, RMask
23135 SmallVector<int, 16> RMask(NumElts);
23136 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23137 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23138 C = RHS.getOperand(0);
23139 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23140 D = RHS.getOperand(1);
23141 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23142 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23144 if (RHS.getOpcode() != ISD::UNDEF)
23146 for (unsigned i = 0; i != NumElts; ++i)
23150 // Check that the shuffles are both shuffling the same vectors.
23151 if (!(A == C && B == D) && !(A == D && B == C))
23154 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23155 if (!A.getNode() && !B.getNode())
23158 // If A and B occur in reverse order in RHS, then "swap" them (which means
23159 // rewriting the mask).
23161 CommuteVectorShuffleMask(RMask, NumElts);
23163 // At this point LHS and RHS are equivalent to
23164 // LHS = VECTOR_SHUFFLE A, B, LMask
23165 // RHS = VECTOR_SHUFFLE A, B, RMask
23166 // Check that the masks correspond to performing a horizontal operation.
23167 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23168 for (unsigned i = 0; i != NumLaneElts; ++i) {
23169 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23171 // Ignore any UNDEF components.
23172 if (LIdx < 0 || RIdx < 0 ||
23173 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23174 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23177 // Check that successive elements are being operated on. If not, this is
23178 // not a horizontal operation.
23179 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23180 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23181 if (!(LIdx == Index && RIdx == Index + 1) &&
23182 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23187 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23188 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23192 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23193 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23194 const X86Subtarget *Subtarget) {
23195 EVT VT = N->getValueType(0);
23196 SDValue LHS = N->getOperand(0);
23197 SDValue RHS = N->getOperand(1);
23199 // Try to synthesize horizontal adds from adds of shuffles.
23200 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23201 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23202 isHorizontalBinOp(LHS, RHS, true))
23203 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23207 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23208 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23209 const X86Subtarget *Subtarget) {
23210 EVT VT = N->getValueType(0);
23211 SDValue LHS = N->getOperand(0);
23212 SDValue RHS = N->getOperand(1);
23214 // Try to synthesize horizontal subs from subs of shuffles.
23215 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23216 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23217 isHorizontalBinOp(LHS, RHS, false))
23218 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23222 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23223 /// X86ISD::FXOR nodes.
23224 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23225 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23226 // F[X]OR(0.0, x) -> x
23227 // F[X]OR(x, 0.0) -> x
23228 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23229 if (C->getValueAPF().isPosZero())
23230 return N->getOperand(1);
23231 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23232 if (C->getValueAPF().isPosZero())
23233 return N->getOperand(0);
23237 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23238 /// X86ISD::FMAX nodes.
23239 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23240 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23242 // Only perform optimizations if UnsafeMath is used.
23243 if (!DAG.getTarget().Options.UnsafeFPMath)
23246 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23247 // into FMINC and FMAXC, which are Commutative operations.
23248 unsigned NewOp = 0;
23249 switch (N->getOpcode()) {
23250 default: llvm_unreachable("unknown opcode");
23251 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23252 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23255 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23256 N->getOperand(0), N->getOperand(1));
23259 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23260 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23261 // FAND(0.0, x) -> 0.0
23262 // FAND(x, 0.0) -> 0.0
23263 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23264 if (C->getValueAPF().isPosZero())
23265 return N->getOperand(0);
23266 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23267 if (C->getValueAPF().isPosZero())
23268 return N->getOperand(1);
23272 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23273 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23274 // FANDN(x, 0.0) -> 0.0
23275 // FANDN(0.0, x) -> x
23276 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23277 if (C->getValueAPF().isPosZero())
23278 return N->getOperand(1);
23279 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23280 if (C->getValueAPF().isPosZero())
23281 return N->getOperand(1);
23285 static SDValue PerformBTCombine(SDNode *N,
23287 TargetLowering::DAGCombinerInfo &DCI) {
23288 // BT ignores high bits in the bit index operand.
23289 SDValue Op1 = N->getOperand(1);
23290 if (Op1.hasOneUse()) {
23291 unsigned BitWidth = Op1.getValueSizeInBits();
23292 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23293 APInt KnownZero, KnownOne;
23294 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23295 !DCI.isBeforeLegalizeOps());
23296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23297 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23298 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23299 DCI.CommitTargetLoweringOpt(TLO);
23304 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23305 SDValue Op = N->getOperand(0);
23306 if (Op.getOpcode() == ISD::BITCAST)
23307 Op = Op.getOperand(0);
23308 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23309 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23310 VT.getVectorElementType().getSizeInBits() ==
23311 OpVT.getVectorElementType().getSizeInBits()) {
23312 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23317 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23318 const X86Subtarget *Subtarget) {
23319 EVT VT = N->getValueType(0);
23320 if (!VT.isVector())
23323 SDValue N0 = N->getOperand(0);
23324 SDValue N1 = N->getOperand(1);
23325 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23328 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23329 // both SSE and AVX2 since there is no sign-extended shift right
23330 // operation on a vector with 64-bit elements.
23331 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23332 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23333 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23334 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23335 SDValue N00 = N0.getOperand(0);
23337 // EXTLOAD has a better solution on AVX2,
23338 // it may be replaced with X86ISD::VSEXT node.
23339 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23340 if (!ISD::isNormalLoad(N00.getNode()))
23343 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23344 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23346 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23352 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23353 TargetLowering::DAGCombinerInfo &DCI,
23354 const X86Subtarget *Subtarget) {
23355 if (!DCI.isBeforeLegalizeOps())
23358 if (!Subtarget->hasFp256())
23361 EVT VT = N->getValueType(0);
23362 if (VT.isVector() && VT.getSizeInBits() == 256) {
23363 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23371 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23372 const X86Subtarget* Subtarget) {
23374 EVT VT = N->getValueType(0);
23376 // Let legalize expand this if it isn't a legal type yet.
23377 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23380 EVT ScalarVT = VT.getScalarType();
23381 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23382 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23385 SDValue A = N->getOperand(0);
23386 SDValue B = N->getOperand(1);
23387 SDValue C = N->getOperand(2);
23389 bool NegA = (A.getOpcode() == ISD::FNEG);
23390 bool NegB = (B.getOpcode() == ISD::FNEG);
23391 bool NegC = (C.getOpcode() == ISD::FNEG);
23393 // Negative multiplication when NegA xor NegB
23394 bool NegMul = (NegA != NegB);
23396 A = A.getOperand(0);
23398 B = B.getOperand(0);
23400 C = C.getOperand(0);
23404 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23406 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23408 return DAG.getNode(Opcode, dl, VT, A, B, C);
23411 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23412 TargetLowering::DAGCombinerInfo &DCI,
23413 const X86Subtarget *Subtarget) {
23414 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23415 // (and (i32 x86isd::setcc_carry), 1)
23416 // This eliminates the zext. This transformation is necessary because
23417 // ISD::SETCC is always legalized to i8.
23419 SDValue N0 = N->getOperand(0);
23420 EVT VT = N->getValueType(0);
23422 if (N0.getOpcode() == ISD::AND &&
23424 N0.getOperand(0).hasOneUse()) {
23425 SDValue N00 = N0.getOperand(0);
23426 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23427 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23428 if (!C || C->getZExtValue() != 1)
23430 return DAG.getNode(ISD::AND, dl, VT,
23431 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23432 N00.getOperand(0), N00.getOperand(1)),
23433 DAG.getConstant(1, VT));
23437 if (N0.getOpcode() == ISD::TRUNCATE &&
23439 N0.getOperand(0).hasOneUse()) {
23440 SDValue N00 = N0.getOperand(0);
23441 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23442 return DAG.getNode(ISD::AND, dl, VT,
23443 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23444 N00.getOperand(0), N00.getOperand(1)),
23445 DAG.getConstant(1, VT));
23448 if (VT.is256BitVector()) {
23449 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23457 // Optimize x == -y --> x+y == 0
23458 // x != -y --> x+y != 0
23459 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23460 const X86Subtarget* Subtarget) {
23461 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23462 SDValue LHS = N->getOperand(0);
23463 SDValue RHS = N->getOperand(1);
23464 EVT VT = N->getValueType(0);
23467 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23468 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23469 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23470 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23471 LHS.getValueType(), RHS, LHS.getOperand(1));
23472 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23473 addV, DAG.getConstant(0, addV.getValueType()), CC);
23475 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23477 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23478 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23479 RHS.getValueType(), LHS, RHS.getOperand(1));
23480 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23481 addV, DAG.getConstant(0, addV.getValueType()), CC);
23484 if (VT.getScalarType() == MVT::i1) {
23485 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23486 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23487 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23488 if (!IsSEXT0 && !IsVZero0)
23490 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23491 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23492 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23494 if (!IsSEXT1 && !IsVZero1)
23497 if (IsSEXT0 && IsVZero1) {
23498 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23499 if (CC == ISD::SETEQ)
23500 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23501 return LHS.getOperand(0);
23503 if (IsSEXT1 && IsVZero0) {
23504 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23505 if (CC == ISD::SETEQ)
23506 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23507 return RHS.getOperand(0);
23514 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23515 const X86Subtarget *Subtarget) {
23517 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23518 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23519 "X86insertps is only defined for v4x32");
23521 SDValue Ld = N->getOperand(1);
23522 if (MayFoldLoad(Ld)) {
23523 // Extract the countS bits from the immediate so we can get the proper
23524 // address when narrowing the vector load to a specific element.
23525 // When the second source op is a memory address, interps doesn't use
23526 // countS and just gets an f32 from that address.
23527 unsigned DestIndex =
23528 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23529 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23533 // Create this as a scalar to vector to match the instruction pattern.
23534 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23535 // countS bits are ignored when loading from memory on insertps, which
23536 // means we don't need to explicitly set them to 0.
23537 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23538 LoadScalarToVector, N->getOperand(2));
23541 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23542 // as "sbb reg,reg", since it can be extended without zext and produces
23543 // an all-ones bit which is more useful than 0/1 in some cases.
23544 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23547 return DAG.getNode(ISD::AND, DL, VT,
23548 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23549 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23550 DAG.getConstant(1, VT));
23551 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23552 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23553 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23554 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23557 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23558 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23559 TargetLowering::DAGCombinerInfo &DCI,
23560 const X86Subtarget *Subtarget) {
23562 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23563 SDValue EFLAGS = N->getOperand(1);
23565 if (CC == X86::COND_A) {
23566 // Try to convert COND_A into COND_B in an attempt to facilitate
23567 // materializing "setb reg".
23569 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23570 // cannot take an immediate as its first operand.
23572 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23573 EFLAGS.getValueType().isInteger() &&
23574 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23575 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23576 EFLAGS.getNode()->getVTList(),
23577 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23578 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23579 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23583 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23584 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23586 if (CC == X86::COND_B)
23587 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23591 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23592 if (Flags.getNode()) {
23593 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23594 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23600 // Optimize branch condition evaluation.
23602 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23603 TargetLowering::DAGCombinerInfo &DCI,
23604 const X86Subtarget *Subtarget) {
23606 SDValue Chain = N->getOperand(0);
23607 SDValue Dest = N->getOperand(1);
23608 SDValue EFLAGS = N->getOperand(3);
23609 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23613 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23614 if (Flags.getNode()) {
23615 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23616 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23623 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23624 SelectionDAG &DAG) {
23625 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23626 // optimize away operation when it's from a constant.
23628 // The general transformation is:
23629 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23630 // AND(VECTOR_CMP(x,y), constant2)
23631 // constant2 = UNARYOP(constant)
23633 // Early exit if this isn't a vector operation, the operand of the
23634 // unary operation isn't a bitwise AND, or if the sizes of the operations
23635 // aren't the same.
23636 EVT VT = N->getValueType(0);
23637 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23638 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23639 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23642 // Now check that the other operand of the AND is a constant. We could
23643 // make the transformation for non-constant splats as well, but it's unclear
23644 // that would be a benefit as it would not eliminate any operations, just
23645 // perform one more step in scalar code before moving to the vector unit.
23646 if (BuildVectorSDNode *BV =
23647 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23648 // Bail out if the vector isn't a constant.
23649 if (!BV->isConstant())
23652 // Everything checks out. Build up the new and improved node.
23654 EVT IntVT = BV->getValueType(0);
23655 // Create a new constant of the appropriate type for the transformed
23657 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23658 // The AND node needs bitcasts to/from an integer vector type around it.
23659 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23660 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23661 N->getOperand(0)->getOperand(0), MaskConst);
23662 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23669 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23670 const X86TargetLowering *XTLI) {
23671 // First try to optimize away the conversion entirely when it's
23672 // conditionally from a constant. Vectors only.
23673 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23674 if (Res != SDValue())
23677 // Now move on to more general possibilities.
23678 SDValue Op0 = N->getOperand(0);
23679 EVT InVT = Op0->getValueType(0);
23681 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23682 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23684 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23685 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23686 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23689 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23690 // a 32-bit target where SSE doesn't support i64->FP operations.
23691 if (Op0.getOpcode() == ISD::LOAD) {
23692 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23693 EVT VT = Ld->getValueType(0);
23694 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23695 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23696 !XTLI->getSubtarget()->is64Bit() &&
23698 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23699 Ld->getChain(), Op0, DAG);
23700 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23707 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23708 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23709 X86TargetLowering::DAGCombinerInfo &DCI) {
23710 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23711 // the result is either zero or one (depending on the input carry bit).
23712 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23713 if (X86::isZeroNode(N->getOperand(0)) &&
23714 X86::isZeroNode(N->getOperand(1)) &&
23715 // We don't have a good way to replace an EFLAGS use, so only do this when
23717 SDValue(N, 1).use_empty()) {
23719 EVT VT = N->getValueType(0);
23720 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23721 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23722 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23723 DAG.getConstant(X86::COND_B,MVT::i8),
23725 DAG.getConstant(1, VT));
23726 return DCI.CombineTo(N, Res1, CarryOut);
23732 // fold (add Y, (sete X, 0)) -> adc 0, Y
23733 // (add Y, (setne X, 0)) -> sbb -1, Y
23734 // (sub (sete X, 0), Y) -> sbb 0, Y
23735 // (sub (setne X, 0), Y) -> adc -1, Y
23736 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23739 // Look through ZExts.
23740 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23741 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23744 SDValue SetCC = Ext.getOperand(0);
23745 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23748 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23749 if (CC != X86::COND_E && CC != X86::COND_NE)
23752 SDValue Cmp = SetCC.getOperand(1);
23753 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23754 !X86::isZeroNode(Cmp.getOperand(1)) ||
23755 !Cmp.getOperand(0).getValueType().isInteger())
23758 SDValue CmpOp0 = Cmp.getOperand(0);
23759 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23760 DAG.getConstant(1, CmpOp0.getValueType()));
23762 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23763 if (CC == X86::COND_NE)
23764 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23765 DL, OtherVal.getValueType(), OtherVal,
23766 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23767 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23768 DL, OtherVal.getValueType(), OtherVal,
23769 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23772 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23773 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23774 const X86Subtarget *Subtarget) {
23775 EVT VT = N->getValueType(0);
23776 SDValue Op0 = N->getOperand(0);
23777 SDValue Op1 = N->getOperand(1);
23779 // Try to synthesize horizontal adds from adds of shuffles.
23780 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23781 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23782 isHorizontalBinOp(Op0, Op1, true))
23783 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23785 return OptimizeConditionalInDecrement(N, DAG);
23788 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23789 const X86Subtarget *Subtarget) {
23790 SDValue Op0 = N->getOperand(0);
23791 SDValue Op1 = N->getOperand(1);
23793 // X86 can't encode an immediate LHS of a sub. See if we can push the
23794 // negation into a preceding instruction.
23795 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23796 // If the RHS of the sub is a XOR with one use and a constant, invert the
23797 // immediate. Then add one to the LHS of the sub so we can turn
23798 // X-Y -> X+~Y+1, saving one register.
23799 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23800 isa<ConstantSDNode>(Op1.getOperand(1))) {
23801 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23802 EVT VT = Op0.getValueType();
23803 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23805 DAG.getConstant(~XorC, VT));
23806 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23807 DAG.getConstant(C->getAPIntValue()+1, VT));
23811 // Try to synthesize horizontal adds from adds of shuffles.
23812 EVT VT = N->getValueType(0);
23813 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23814 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23815 isHorizontalBinOp(Op0, Op1, true))
23816 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23818 return OptimizeConditionalInDecrement(N, DAG);
23821 /// performVZEXTCombine - Performs build vector combines
23822 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23823 TargetLowering::DAGCombinerInfo &DCI,
23824 const X86Subtarget *Subtarget) {
23825 // (vzext (bitcast (vzext (x)) -> (vzext x)
23826 SDValue In = N->getOperand(0);
23827 while (In.getOpcode() == ISD::BITCAST)
23828 In = In.getOperand(0);
23830 if (In.getOpcode() != X86ISD::VZEXT)
23833 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23837 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23838 DAGCombinerInfo &DCI) const {
23839 SelectionDAG &DAG = DCI.DAG;
23840 switch (N->getOpcode()) {
23842 case ISD::EXTRACT_VECTOR_ELT:
23843 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23845 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23846 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23847 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23848 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23849 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23850 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23853 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23854 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23855 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23856 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23857 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23858 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23859 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23860 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23861 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23863 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23865 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23866 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23867 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23868 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23869 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23870 case ISD::ANY_EXTEND:
23871 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23872 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23873 case ISD::SIGN_EXTEND_INREG:
23874 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23875 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23876 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23877 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23878 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23879 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23880 case X86ISD::SHUFP: // Handle all target specific shuffles
23881 case X86ISD::PALIGNR:
23882 case X86ISD::UNPCKH:
23883 case X86ISD::UNPCKL:
23884 case X86ISD::MOVHLPS:
23885 case X86ISD::MOVLHPS:
23886 case X86ISD::PSHUFB:
23887 case X86ISD::PSHUFD:
23888 case X86ISD::PSHUFHW:
23889 case X86ISD::PSHUFLW:
23890 case X86ISD::MOVSS:
23891 case X86ISD::MOVSD:
23892 case X86ISD::VPERMILP:
23893 case X86ISD::VPERM2X128:
23894 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23895 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23896 case ISD::INTRINSIC_WO_CHAIN:
23897 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23898 case X86ISD::INSERTPS:
23899 return PerformINSERTPSCombine(N, DAG, Subtarget);
23900 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23906 /// isTypeDesirableForOp - Return true if the target has native support for
23907 /// the specified value type and it is 'desirable' to use the type for the
23908 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23909 /// instruction encodings are longer and some i16 instructions are slow.
23910 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23911 if (!isTypeLegal(VT))
23913 if (VT != MVT::i16)
23920 case ISD::SIGN_EXTEND:
23921 case ISD::ZERO_EXTEND:
23922 case ISD::ANY_EXTEND:
23935 /// IsDesirableToPromoteOp - This method query the target whether it is
23936 /// beneficial for dag combiner to promote the specified node. If true, it
23937 /// should return the desired promotion type by reference.
23938 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23939 EVT VT = Op.getValueType();
23940 if (VT != MVT::i16)
23943 bool Promote = false;
23944 bool Commute = false;
23945 switch (Op.getOpcode()) {
23948 LoadSDNode *LD = cast<LoadSDNode>(Op);
23949 // If the non-extending load has a single use and it's not live out, then it
23950 // might be folded.
23951 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23952 Op.hasOneUse()*/) {
23953 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23954 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23955 // The only case where we'd want to promote LOAD (rather then it being
23956 // promoted as an operand is when it's only use is liveout.
23957 if (UI->getOpcode() != ISD::CopyToReg)
23964 case ISD::SIGN_EXTEND:
23965 case ISD::ZERO_EXTEND:
23966 case ISD::ANY_EXTEND:
23971 SDValue N0 = Op.getOperand(0);
23972 // Look out for (store (shl (load), x)).
23973 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23986 SDValue N0 = Op.getOperand(0);
23987 SDValue N1 = Op.getOperand(1);
23988 if (!Commute && MayFoldLoad(N1))
23990 // Avoid disabling potential load folding opportunities.
23991 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23993 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24003 //===----------------------------------------------------------------------===//
24004 // X86 Inline Assembly Support
24005 //===----------------------------------------------------------------------===//
24008 // Helper to match a string separated by whitespace.
24009 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24010 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24012 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24013 StringRef piece(*args[i]);
24014 if (!s.startswith(piece)) // Check if the piece matches.
24017 s = s.substr(piece.size());
24018 StringRef::size_type pos = s.find_first_not_of(" \t");
24019 if (pos == 0) // We matched a prefix.
24027 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24030 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24032 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24033 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24034 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24035 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24037 if (AsmPieces.size() == 3)
24039 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24046 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24047 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24049 std::string AsmStr = IA->getAsmString();
24051 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24052 if (!Ty || Ty->getBitWidth() % 16 != 0)
24055 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24056 SmallVector<StringRef, 4> AsmPieces;
24057 SplitString(AsmStr, AsmPieces, ";\n");
24059 switch (AsmPieces.size()) {
24060 default: return false;
24062 // FIXME: this should verify that we are targeting a 486 or better. If not,
24063 // we will turn this bswap into something that will be lowered to logical
24064 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24065 // lower so don't worry about this.
24067 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24068 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24069 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24070 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24071 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24072 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24073 // No need to check constraints, nothing other than the equivalent of
24074 // "=r,0" would be valid here.
24075 return IntrinsicLowering::LowerToByteSwap(CI);
24078 // rorw $$8, ${0:w} --> llvm.bswap.i16
24079 if (CI->getType()->isIntegerTy(16) &&
24080 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24081 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24082 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24084 const std::string &ConstraintsStr = IA->getConstraintString();
24085 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24086 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24087 if (clobbersFlagRegisters(AsmPieces))
24088 return IntrinsicLowering::LowerToByteSwap(CI);
24092 if (CI->getType()->isIntegerTy(32) &&
24093 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24094 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24095 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24096 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24098 const std::string &ConstraintsStr = IA->getConstraintString();
24099 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24100 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24101 if (clobbersFlagRegisters(AsmPieces))
24102 return IntrinsicLowering::LowerToByteSwap(CI);
24105 if (CI->getType()->isIntegerTy(64)) {
24106 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24107 if (Constraints.size() >= 2 &&
24108 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24109 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24110 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24111 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24112 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24113 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24114 return IntrinsicLowering::LowerToByteSwap(CI);
24122 /// getConstraintType - Given a constraint letter, return the type of
24123 /// constraint it is for this target.
24124 X86TargetLowering::ConstraintType
24125 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24126 if (Constraint.size() == 1) {
24127 switch (Constraint[0]) {
24138 return C_RegisterClass;
24162 return TargetLowering::getConstraintType(Constraint);
24165 /// Examine constraint type and operand type and determine a weight value.
24166 /// This object must already have been set up with the operand type
24167 /// and the current alternative constraint selected.
24168 TargetLowering::ConstraintWeight
24169 X86TargetLowering::getSingleConstraintMatchWeight(
24170 AsmOperandInfo &info, const char *constraint) const {
24171 ConstraintWeight weight = CW_Invalid;
24172 Value *CallOperandVal = info.CallOperandVal;
24173 // If we don't have a value, we can't do a match,
24174 // but allow it at the lowest weight.
24175 if (!CallOperandVal)
24177 Type *type = CallOperandVal->getType();
24178 // Look at the constraint type.
24179 switch (*constraint) {
24181 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24192 if (CallOperandVal->getType()->isIntegerTy())
24193 weight = CW_SpecificReg;
24198 if (type->isFloatingPointTy())
24199 weight = CW_SpecificReg;
24202 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24203 weight = CW_SpecificReg;
24207 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24208 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24209 weight = CW_Register;
24212 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24213 if (C->getZExtValue() <= 31)
24214 weight = CW_Constant;
24218 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24219 if (C->getZExtValue() <= 63)
24220 weight = CW_Constant;
24224 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24225 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24226 weight = CW_Constant;
24230 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24231 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24232 weight = CW_Constant;
24236 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24237 if (C->getZExtValue() <= 3)
24238 weight = CW_Constant;
24242 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24243 if (C->getZExtValue() <= 0xff)
24244 weight = CW_Constant;
24249 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24250 weight = CW_Constant;
24254 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24255 if ((C->getSExtValue() >= -0x80000000LL) &&
24256 (C->getSExtValue() <= 0x7fffffffLL))
24257 weight = CW_Constant;
24261 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24262 if (C->getZExtValue() <= 0xffffffff)
24263 weight = CW_Constant;
24270 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24271 /// with another that has more specific requirements based on the type of the
24272 /// corresponding operand.
24273 const char *X86TargetLowering::
24274 LowerXConstraint(EVT ConstraintVT) const {
24275 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24276 // 'f' like normal targets.
24277 if (ConstraintVT.isFloatingPoint()) {
24278 if (Subtarget->hasSSE2())
24280 if (Subtarget->hasSSE1())
24284 return TargetLowering::LowerXConstraint(ConstraintVT);
24287 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24288 /// vector. If it is invalid, don't add anything to Ops.
24289 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24290 std::string &Constraint,
24291 std::vector<SDValue>&Ops,
24292 SelectionDAG &DAG) const {
24295 // Only support length 1 constraints for now.
24296 if (Constraint.length() > 1) return;
24298 char ConstraintLetter = Constraint[0];
24299 switch (ConstraintLetter) {
24302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24303 if (C->getZExtValue() <= 31) {
24304 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24311 if (C->getZExtValue() <= 63) {
24312 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24318 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24319 if (isInt<8>(C->getSExtValue())) {
24320 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24326 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24327 if (C->getZExtValue() <= 255) {
24328 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24334 // 32-bit signed value
24335 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24336 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24337 C->getSExtValue())) {
24338 // Widen to 64 bits here to get it sign extended.
24339 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24342 // FIXME gcc accepts some relocatable values here too, but only in certain
24343 // memory models; it's complicated.
24348 // 32-bit unsigned value
24349 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24350 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24351 C->getZExtValue())) {
24352 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24356 // FIXME gcc accepts some relocatable values here too, but only in certain
24357 // memory models; it's complicated.
24361 // Literal immediates are always ok.
24362 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24363 // Widen to 64 bits here to get it sign extended.
24364 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24368 // In any sort of PIC mode addresses need to be computed at runtime by
24369 // adding in a register or some sort of table lookup. These can't
24370 // be used as immediates.
24371 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24374 // If we are in non-pic codegen mode, we allow the address of a global (with
24375 // an optional displacement) to be used with 'i'.
24376 GlobalAddressSDNode *GA = nullptr;
24377 int64_t Offset = 0;
24379 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24381 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24382 Offset += GA->getOffset();
24384 } else if (Op.getOpcode() == ISD::ADD) {
24385 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24386 Offset += C->getZExtValue();
24387 Op = Op.getOperand(0);
24390 } else if (Op.getOpcode() == ISD::SUB) {
24391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24392 Offset += -C->getZExtValue();
24393 Op = Op.getOperand(0);
24398 // Otherwise, this isn't something we can handle, reject it.
24402 const GlobalValue *GV = GA->getGlobal();
24403 // If we require an extra load to get this address, as in PIC mode, we
24404 // can't accept it.
24405 if (isGlobalStubReference(
24406 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24409 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24410 GA->getValueType(0), Offset);
24415 if (Result.getNode()) {
24416 Ops.push_back(Result);
24419 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24422 std::pair<unsigned, const TargetRegisterClass*>
24423 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24425 // First, see if this is a constraint that directly corresponds to an LLVM
24427 if (Constraint.size() == 1) {
24428 // GCC Constraint Letters
24429 switch (Constraint[0]) {
24431 // TODO: Slight differences here in allocation order and leaving
24432 // RIP in the class. Do they matter any more here than they do
24433 // in the normal allocation?
24434 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24435 if (Subtarget->is64Bit()) {
24436 if (VT == MVT::i32 || VT == MVT::f32)
24437 return std::make_pair(0U, &X86::GR32RegClass);
24438 if (VT == MVT::i16)
24439 return std::make_pair(0U, &X86::GR16RegClass);
24440 if (VT == MVT::i8 || VT == MVT::i1)
24441 return std::make_pair(0U, &X86::GR8RegClass);
24442 if (VT == MVT::i64 || VT == MVT::f64)
24443 return std::make_pair(0U, &X86::GR64RegClass);
24446 // 32-bit fallthrough
24447 case 'Q': // Q_REGS
24448 if (VT == MVT::i32 || VT == MVT::f32)
24449 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24450 if (VT == MVT::i16)
24451 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24452 if (VT == MVT::i8 || VT == MVT::i1)
24453 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24454 if (VT == MVT::i64)
24455 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24457 case 'r': // GENERAL_REGS
24458 case 'l': // INDEX_REGS
24459 if (VT == MVT::i8 || VT == MVT::i1)
24460 return std::make_pair(0U, &X86::GR8RegClass);
24461 if (VT == MVT::i16)
24462 return std::make_pair(0U, &X86::GR16RegClass);
24463 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24464 return std::make_pair(0U, &X86::GR32RegClass);
24465 return std::make_pair(0U, &X86::GR64RegClass);
24466 case 'R': // LEGACY_REGS
24467 if (VT == MVT::i8 || VT == MVT::i1)
24468 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24469 if (VT == MVT::i16)
24470 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24471 if (VT == MVT::i32 || !Subtarget->is64Bit())
24472 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24473 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24474 case 'f': // FP Stack registers.
24475 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24476 // value to the correct fpstack register class.
24477 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24478 return std::make_pair(0U, &X86::RFP32RegClass);
24479 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24480 return std::make_pair(0U, &X86::RFP64RegClass);
24481 return std::make_pair(0U, &X86::RFP80RegClass);
24482 case 'y': // MMX_REGS if MMX allowed.
24483 if (!Subtarget->hasMMX()) break;
24484 return std::make_pair(0U, &X86::VR64RegClass);
24485 case 'Y': // SSE_REGS if SSE2 allowed
24486 if (!Subtarget->hasSSE2()) break;
24488 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24489 if (!Subtarget->hasSSE1()) break;
24491 switch (VT.SimpleTy) {
24493 // Scalar SSE types.
24496 return std::make_pair(0U, &X86::FR32RegClass);
24499 return std::make_pair(0U, &X86::FR64RegClass);
24507 return std::make_pair(0U, &X86::VR128RegClass);
24515 return std::make_pair(0U, &X86::VR256RegClass);
24520 return std::make_pair(0U, &X86::VR512RegClass);
24526 // Use the default implementation in TargetLowering to convert the register
24527 // constraint into a member of a register class.
24528 std::pair<unsigned, const TargetRegisterClass*> Res;
24529 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24531 // Not found as a standard register?
24533 // Map st(0) -> st(7) -> ST0
24534 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24535 tolower(Constraint[1]) == 's' &&
24536 tolower(Constraint[2]) == 't' &&
24537 Constraint[3] == '(' &&
24538 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24539 Constraint[5] == ')' &&
24540 Constraint[6] == '}') {
24542 Res.first = X86::FP0+Constraint[4]-'0';
24543 Res.second = &X86::RFP80RegClass;
24547 // GCC allows "st(0)" to be called just plain "st".
24548 if (StringRef("{st}").equals_lower(Constraint)) {
24549 Res.first = X86::FP0;
24550 Res.second = &X86::RFP80RegClass;
24555 if (StringRef("{flags}").equals_lower(Constraint)) {
24556 Res.first = X86::EFLAGS;
24557 Res.second = &X86::CCRRegClass;
24561 // 'A' means EAX + EDX.
24562 if (Constraint == "A") {
24563 Res.first = X86::EAX;
24564 Res.second = &X86::GR32_ADRegClass;
24570 // Otherwise, check to see if this is a register class of the wrong value
24571 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24572 // turn into {ax},{dx}.
24573 if (Res.second->hasType(VT))
24574 return Res; // Correct type already, nothing to do.
24576 // All of the single-register GCC register classes map their values onto
24577 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24578 // really want an 8-bit or 32-bit register, map to the appropriate register
24579 // class and return the appropriate register.
24580 if (Res.second == &X86::GR16RegClass) {
24581 if (VT == MVT::i8 || VT == MVT::i1) {
24582 unsigned DestReg = 0;
24583 switch (Res.first) {
24585 case X86::AX: DestReg = X86::AL; break;
24586 case X86::DX: DestReg = X86::DL; break;
24587 case X86::CX: DestReg = X86::CL; break;
24588 case X86::BX: DestReg = X86::BL; break;
24591 Res.first = DestReg;
24592 Res.second = &X86::GR8RegClass;
24594 } else if (VT == MVT::i32 || VT == MVT::f32) {
24595 unsigned DestReg = 0;
24596 switch (Res.first) {
24598 case X86::AX: DestReg = X86::EAX; break;
24599 case X86::DX: DestReg = X86::EDX; break;
24600 case X86::CX: DestReg = X86::ECX; break;
24601 case X86::BX: DestReg = X86::EBX; break;
24602 case X86::SI: DestReg = X86::ESI; break;
24603 case X86::DI: DestReg = X86::EDI; break;
24604 case X86::BP: DestReg = X86::EBP; break;
24605 case X86::SP: DestReg = X86::ESP; break;
24608 Res.first = DestReg;
24609 Res.second = &X86::GR32RegClass;
24611 } else if (VT == MVT::i64 || VT == MVT::f64) {
24612 unsigned DestReg = 0;
24613 switch (Res.first) {
24615 case X86::AX: DestReg = X86::RAX; break;
24616 case X86::DX: DestReg = X86::RDX; break;
24617 case X86::CX: DestReg = X86::RCX; break;
24618 case X86::BX: DestReg = X86::RBX; break;
24619 case X86::SI: DestReg = X86::RSI; break;
24620 case X86::DI: DestReg = X86::RDI; break;
24621 case X86::BP: DestReg = X86::RBP; break;
24622 case X86::SP: DestReg = X86::RSP; break;
24625 Res.first = DestReg;
24626 Res.second = &X86::GR64RegClass;
24629 } else if (Res.second == &X86::FR32RegClass ||
24630 Res.second == &X86::FR64RegClass ||
24631 Res.second == &X86::VR128RegClass ||
24632 Res.second == &X86::VR256RegClass ||
24633 Res.second == &X86::FR32XRegClass ||
24634 Res.second == &X86::FR64XRegClass ||
24635 Res.second == &X86::VR128XRegClass ||
24636 Res.second == &X86::VR256XRegClass ||
24637 Res.second == &X86::VR512RegClass) {
24638 // Handle references to XMM physical registers that got mapped into the
24639 // wrong class. This can happen with constraints like {xmm0} where the
24640 // target independent register mapper will just pick the first match it can
24641 // find, ignoring the required type.
24643 if (VT == MVT::f32 || VT == MVT::i32)
24644 Res.second = &X86::FR32RegClass;
24645 else if (VT == MVT::f64 || VT == MVT::i64)
24646 Res.second = &X86::FR64RegClass;
24647 else if (X86::VR128RegClass.hasType(VT))
24648 Res.second = &X86::VR128RegClass;
24649 else if (X86::VR256RegClass.hasType(VT))
24650 Res.second = &X86::VR256RegClass;
24651 else if (X86::VR512RegClass.hasType(VT))
24652 Res.second = &X86::VR512RegClass;
24658 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24660 // Scaling factors are not free at all.
24661 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24662 // will take 2 allocations in the out of order engine instead of 1
24663 // for plain addressing mode, i.e. inst (reg1).
24665 // vaddps (%rsi,%drx), %ymm0, %ymm1
24666 // Requires two allocations (one for the load, one for the computation)
24668 // vaddps (%rsi), %ymm0, %ymm1
24669 // Requires just 1 allocation, i.e., freeing allocations for other operations
24670 // and having less micro operations to execute.
24672 // For some X86 architectures, this is even worse because for instance for
24673 // stores, the complex addressing mode forces the instruction to use the
24674 // "load" ports instead of the dedicated "store" port.
24675 // E.g., on Haswell:
24676 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24677 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24678 if (isLegalAddressingMode(AM, Ty))
24679 // Scale represents reg2 * scale, thus account for 1
24680 // as soon as we use a second register.
24681 return AM.Scale != 0;
24685 bool X86TargetLowering::isTargetFTOL() const {
24686 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();