1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i16, Expand);
526 if (Subtarget->hasPOPCNT()) {
527 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
529 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
531 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
532 if (Subtarget->is64Bit())
533 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
536 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
538 if (!Subtarget->hasMOVBE())
539 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
541 // These should be promoted to a larger select which is supported.
542 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
543 // X86 wants to expand cmov itself.
544 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
546 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
556 if (Subtarget->is64Bit()) {
557 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
560 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
561 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
562 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
563 // support continuation, user-level threading, and etc.. As a result, no
564 // other SjLj exception interfaces are implemented and please don't build
565 // your own exception handling based on them.
566 // LLVM/Clang supports zero-cost DWARF exception handling.
567 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
568 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
571 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
572 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
574 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
575 if (Subtarget->is64Bit())
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
577 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
578 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
579 if (Subtarget->is64Bit()) {
580 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
583 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
584 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
586 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
587 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
589 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
596 if (Subtarget->hasSSE1())
597 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
599 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
601 // Expand certain atomics
602 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
604 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
605 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
606 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
609 if (Subtarget->hasCmpxchg16b()) {
610 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
613 // FIXME - use subtarget debug flags
614 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
615 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
616 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
619 if (Subtarget->is64Bit()) {
620 setExceptionPointerRegister(X86::RAX);
621 setExceptionSelectorRegister(X86::RDX);
623 setExceptionPointerRegister(X86::EAX);
624 setExceptionSelectorRegister(X86::EDX);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
627 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
629 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
630 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::TRAP, MVT::Other, Legal);
633 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
635 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
636 setOperationAction(ISD::VASTART , MVT::Other, Custom);
637 setOperationAction(ISD::VAEND , MVT::Other, Expand);
638 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
639 // TargetInfo::X86_64ABIBuiltinVaList
640 setOperationAction(ISD::VAARG , MVT::Other, Custom);
641 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
643 // TargetInfo::CharPtrBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Expand);
645 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
648 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
649 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
651 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
652 MVT::i64 : MVT::i32, Custom);
654 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
655 // f32 and f64 use SSE.
656 // Set up the FP register classes.
657 addRegisterClass(MVT::f32, &X86::FR32RegClass);
658 addRegisterClass(MVT::f64, &X86::FR64RegClass);
660 // Use ANDPD to simulate FABS.
661 setOperationAction(ISD::FABS , MVT::f64, Custom);
662 setOperationAction(ISD::FABS , MVT::f32, Custom);
664 // Use XORP to simulate FNEG.
665 setOperationAction(ISD::FNEG , MVT::f64, Custom);
666 setOperationAction(ISD::FNEG , MVT::f32, Custom);
668 // Use ANDPD and ORPD to simulate FCOPYSIGN.
669 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
670 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
672 // Lower this to FGETSIGNx86 plus an AND.
673 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
674 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
676 // We don't support sin/cos/fmod
677 setOperationAction(ISD::FSIN , MVT::f64, Expand);
678 setOperationAction(ISD::FCOS , MVT::f64, Expand);
679 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
680 setOperationAction(ISD::FSIN , MVT::f32, Expand);
681 setOperationAction(ISD::FCOS , MVT::f32, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
684 // Expand FP immediates into loads from the stack, except for the special
686 addLegalFPImmediate(APFloat(+0.0)); // xorpd
687 addLegalFPImmediate(APFloat(+0.0f)); // xorps
688 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
689 // Use SSE for f32, x87 for f64.
690 // Set up the FP register classes.
691 addRegisterClass(MVT::f32, &X86::FR32RegClass);
692 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
694 // Use ANDPS to simulate FABS.
695 setOperationAction(ISD::FABS , MVT::f32, Custom);
697 // Use XORP to simulate FNEG.
698 setOperationAction(ISD::FNEG , MVT::f32, Custom);
700 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
702 // Use ANDPS and ORPS to simulate FCOPYSIGN.
703 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
704 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
706 // We don't support sin/cos/fmod
707 setOperationAction(ISD::FSIN , MVT::f32, Expand);
708 setOperationAction(ISD::FCOS , MVT::f32, Expand);
709 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
711 // Special cases we handle for FP constants.
712 addLegalFPImmediate(APFloat(+0.0f)); // xorps
713 addLegalFPImmediate(APFloat(+0.0)); // FLD0
714 addLegalFPImmediate(APFloat(+1.0)); // FLD1
715 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
716 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
718 if (!TM.Options.UnsafeFPMath) {
719 setOperationAction(ISD::FSIN , MVT::f64, Expand);
720 setOperationAction(ISD::FCOS , MVT::f64, Expand);
721 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
723 } else if (!TM.Options.UseSoftFloat) {
724 // f32 and f64 in x87.
725 // Set up the FP register classes.
726 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
727 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
729 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
730 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
731 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
734 if (!TM.Options.UnsafeFPMath) {
735 setOperationAction(ISD::FSIN , MVT::f64, Expand);
736 setOperationAction(ISD::FSIN , MVT::f32, Expand);
737 setOperationAction(ISD::FCOS , MVT::f64, Expand);
738 setOperationAction(ISD::FCOS , MVT::f32, Expand);
739 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
742 addLegalFPImmediate(APFloat(+0.0)); // FLD0
743 addLegalFPImmediate(APFloat(+1.0)); // FLD1
744 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
745 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
746 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
747 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
748 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
749 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
752 // We don't support FMA.
753 setOperationAction(ISD::FMA, MVT::f64, Expand);
754 setOperationAction(ISD::FMA, MVT::f32, Expand);
756 // Long double always uses X87.
757 if (!TM.Options.UseSoftFloat) {
758 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
759 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
760 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
762 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
763 addLegalFPImmediate(TmpFlt); // FLD0
765 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
768 APFloat TmpFlt2(+1.0);
769 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
771 addLegalFPImmediate(TmpFlt2); // FLD1
772 TmpFlt2.changeSign();
773 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
776 if (!TM.Options.UnsafeFPMath) {
777 setOperationAction(ISD::FSIN , MVT::f80, Expand);
778 setOperationAction(ISD::FCOS , MVT::f80, Expand);
779 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
782 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
783 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
784 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
785 setOperationAction(ISD::FRINT, MVT::f80, Expand);
786 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
787 setOperationAction(ISD::FMA, MVT::f80, Expand);
790 // Always use a library call for pow.
791 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
792 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
795 setOperationAction(ISD::FLOG, MVT::f80, Expand);
796 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
798 setOperationAction(ISD::FEXP, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
873 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
874 setOperationAction(ISD::VSELECT, VT, Expand);
875 setOperationAction(ISD::SELECT_CC, VT, Expand);
876 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
877 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
878 setTruncStoreAction(VT,
879 (MVT::SimpleValueType)InnerVT, Expand);
880 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
881 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
885 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
886 // with -msoft-float, disable use of MMX as well.
887 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
888 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
889 // No operations on x86mmx supported, everything uses intrinsics.
892 // MMX-sized vectors (other than x86mmx) are expected to be expanded
893 // into smaller operations.
894 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
895 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
896 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
897 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
898 setOperationAction(ISD::AND, MVT::v8i8, Expand);
899 setOperationAction(ISD::AND, MVT::v4i16, Expand);
900 setOperationAction(ISD::AND, MVT::v2i32, Expand);
901 setOperationAction(ISD::AND, MVT::v1i64, Expand);
902 setOperationAction(ISD::OR, MVT::v8i8, Expand);
903 setOperationAction(ISD::OR, MVT::v4i16, Expand);
904 setOperationAction(ISD::OR, MVT::v2i32, Expand);
905 setOperationAction(ISD::OR, MVT::v1i64, Expand);
906 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
907 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
908 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
909 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
910 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
915 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
916 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
917 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
918 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
919 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
920 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
921 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
922 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
924 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
925 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
927 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
928 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
929 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
930 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
931 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
932 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
933 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
934 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
935 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
936 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
938 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
941 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
942 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
944 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
945 // registers cannot be used even for integer operations.
946 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
947 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
948 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
949 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
951 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
952 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
953 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
954 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
955 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
956 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
957 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
958 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
959 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
960 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
961 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
962 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
963 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
964 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
965 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
966 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
967 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
968 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
969 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
970 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
971 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
972 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
974 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
975 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
976 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
977 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
979 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
980 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
983 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
985 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
986 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
987 MVT VT = (MVT::SimpleValueType)i;
988 // Do not attempt to custom lower non-power-of-2 vectors
989 if (!isPowerOf2_32(VT.getVectorNumElements()))
991 // Do not attempt to custom lower non-128-bit vectors
992 if (!VT.is128BitVector())
994 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
995 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
999 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1000 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1002 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1003 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1006 if (Subtarget->is64Bit()) {
1007 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1008 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1011 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1012 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1013 MVT VT = (MVT::SimpleValueType)i;
1015 // Do not attempt to promote non-128-bit vectors
1016 if (!VT.is128BitVector())
1019 setOperationAction(ISD::AND, VT, Promote);
1020 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1021 setOperationAction(ISD::OR, VT, Promote);
1022 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1023 setOperationAction(ISD::XOR, VT, Promote);
1024 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1025 setOperationAction(ISD::LOAD, VT, Promote);
1026 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1027 setOperationAction(ISD::SELECT, VT, Promote);
1028 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1031 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1033 // Custom lower v2i64 and v2f64 selects.
1034 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1035 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1036 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1037 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1042 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1043 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1044 // As there is no 64-bit GPR available, we need build a special custom
1045 // sequence to convert from v2i32 to v2f32.
1046 if (!Subtarget->is64Bit())
1047 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1049 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1050 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1052 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1054 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1055 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1056 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1059 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1060 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1061 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1062 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1063 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1064 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1065 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1066 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1067 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1068 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1069 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1071 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1072 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1073 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1074 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1075 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1076 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1077 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1078 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1079 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1080 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1082 // FIXME: Do we need to handle scalar-to-vector here?
1083 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1085 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1086 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1088 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1089 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1090 // There is no BLENDI for byte vectors. We don't need to custom lower
1091 // some vselects for now.
1092 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1094 // i8 and i16 vectors are custom , because the source register and source
1095 // source memory operand types are not the same width. f32 vectors are
1096 // custom since the immediate controlling the insert encodes additional
1098 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1099 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1100 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1101 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1103 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1105 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1106 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1108 // FIXME: these should be Legal but thats only for the case where
1109 // the index is constant. For now custom expand to deal with that.
1110 if (Subtarget->is64Bit()) {
1111 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1112 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1116 if (Subtarget->hasSSE2()) {
1117 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1118 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1120 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1121 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1123 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1124 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1126 // In the customized shift lowering, the legal cases in AVX2 will be
1128 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1129 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1131 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1132 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1134 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1137 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1138 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1139 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1140 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1141 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1142 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1143 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1145 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1146 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1147 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1149 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1150 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1151 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1152 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1155 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1156 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1157 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1158 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1159 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1160 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1162 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1163 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1164 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1165 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1167 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1168 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1169 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1170 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1171 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1172 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1173 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1175 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1176 // even though v8i16 is a legal type.
1177 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1178 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1179 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1181 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1182 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1183 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1185 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1186 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1188 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1190 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1191 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1193 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1194 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1196 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1197 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1199 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1200 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1201 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1202 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1204 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1205 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1206 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1208 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1209 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1210 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1211 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1215 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1218 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1221 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1222 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1223 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1224 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1226 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1227 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1228 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1229 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1230 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1231 setOperationAction(ISD::FMA, MVT::f32, Legal);
1232 setOperationAction(ISD::FMA, MVT::f64, Legal);
1235 if (Subtarget->hasInt256()) {
1236 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1237 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1238 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1239 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1241 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1242 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1243 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1244 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1246 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1247 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1248 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1249 // Don't lower v32i8 because there is no 128-bit byte mul
1251 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1252 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1253 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1254 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1256 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1257 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1259 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1260 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1261 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1262 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1264 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1265 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1266 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1267 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1269 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1270 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1271 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1272 // Don't lower v32i8 because there is no 128-bit byte mul
1275 // In the customized shift lowering, the legal cases in AVX2 will be
1277 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1278 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1281 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1283 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1285 // Custom lower several nodes for 256-bit types.
1286 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1287 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1288 MVT VT = (MVT::SimpleValueType)i;
1290 // Extract subvector is special because the value type
1291 // (result) is 128-bit but the source is 256-bit wide.
1292 if (VT.is128BitVector())
1293 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1295 // Do not attempt to custom lower other non-256-bit vectors
1296 if (!VT.is256BitVector())
1299 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1300 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1301 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1302 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1303 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1304 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1305 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1308 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1309 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1310 MVT VT = (MVT::SimpleValueType)i;
1312 // Do not attempt to promote non-256-bit vectors
1313 if (!VT.is256BitVector())
1316 setOperationAction(ISD::AND, VT, Promote);
1317 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1318 setOperationAction(ISD::OR, VT, Promote);
1319 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1320 setOperationAction(ISD::XOR, VT, Promote);
1321 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1322 setOperationAction(ISD::LOAD, VT, Promote);
1323 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1324 setOperationAction(ISD::SELECT, VT, Promote);
1325 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1329 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1330 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1331 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1332 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1333 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1335 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1336 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1337 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1339 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1340 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1341 setOperationAction(ISD::XOR, MVT::i1, Legal);
1342 setOperationAction(ISD::OR, MVT::i1, Legal);
1343 setOperationAction(ISD::AND, MVT::i1, Legal);
1344 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1348 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1349 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1351 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1356 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1358 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1363 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1364 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1365 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1367 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1368 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1369 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1371 if (Subtarget->is64Bit()) {
1372 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1377 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1378 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1379 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1380 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1381 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1382 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1383 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1384 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1385 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1386 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1388 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1392 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1393 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1394 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1395 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1398 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1400 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1402 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1403 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1404 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1405 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1406 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1407 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1409 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1410 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1412 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1415 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1416 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1417 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1419 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1420 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1421 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1422 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1424 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1425 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1427 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1428 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1430 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1432 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1435 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1438 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1439 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1441 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1442 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1443 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1444 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1445 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1446 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1448 if (Subtarget->hasCDI()) {
1449 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1450 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1453 // Custom lower several nodes.
1454 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1455 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1456 MVT VT = (MVT::SimpleValueType)i;
1458 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1459 // Extract subvector is special because the value type
1460 // (result) is 256/128-bit but the source is 512-bit wide.
1461 if (VT.is128BitVector() || VT.is256BitVector())
1462 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1464 if (VT.getVectorElementType() == MVT::i1)
1465 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1467 // Do not attempt to custom lower other non-512-bit vectors
1468 if (!VT.is512BitVector())
1471 if ( EltSize >= 32) {
1472 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1473 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1474 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1475 setOperationAction(ISD::VSELECT, VT, Legal);
1476 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1477 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1478 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1481 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1482 MVT VT = (MVT::SimpleValueType)i;
1484 // Do not attempt to promote non-256-bit vectors
1485 if (!VT.is512BitVector())
1488 setOperationAction(ISD::SELECT, VT, Promote);
1489 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1493 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1494 // of this type with custom code.
1495 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1496 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1497 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1501 // We want to custom lower some of our intrinsics.
1502 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1503 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1504 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1505 if (!Subtarget->is64Bit())
1506 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1508 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1509 // handle type legalization for these operations here.
1511 // FIXME: We really should do custom legalization for addition and
1512 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1513 // than generic legalization for 64-bit multiplication-with-overflow, though.
1514 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1515 // Add/Sub/Mul with overflow operations are custom lowered.
1517 setOperationAction(ISD::SADDO, VT, Custom);
1518 setOperationAction(ISD::UADDO, VT, Custom);
1519 setOperationAction(ISD::SSUBO, VT, Custom);
1520 setOperationAction(ISD::USUBO, VT, Custom);
1521 setOperationAction(ISD::SMULO, VT, Custom);
1522 setOperationAction(ISD::UMULO, VT, Custom);
1525 // There are no 8-bit 3-address imul/mul instructions
1526 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1527 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1529 if (!Subtarget->is64Bit()) {
1530 // These libcalls are not available in 32-bit.
1531 setLibcallName(RTLIB::SHL_I128, nullptr);
1532 setLibcallName(RTLIB::SRL_I128, nullptr);
1533 setLibcallName(RTLIB::SRA_I128, nullptr);
1536 // Combine sin / cos into one node or libcall if possible.
1537 if (Subtarget->hasSinCos()) {
1538 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1539 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1540 if (Subtarget->isTargetDarwin()) {
1541 // For MacOSX, we don't want to the normal expansion of a libcall to
1542 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1544 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1545 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1549 if (Subtarget->isTargetWin64()) {
1550 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1551 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1552 setOperationAction(ISD::SREM, MVT::i128, Custom);
1553 setOperationAction(ISD::UREM, MVT::i128, Custom);
1554 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1555 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1558 // We have target-specific dag combine patterns for the following nodes:
1559 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1560 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1561 setTargetDAGCombine(ISD::VSELECT);
1562 setTargetDAGCombine(ISD::SELECT);
1563 setTargetDAGCombine(ISD::SHL);
1564 setTargetDAGCombine(ISD::SRA);
1565 setTargetDAGCombine(ISD::SRL);
1566 setTargetDAGCombine(ISD::OR);
1567 setTargetDAGCombine(ISD::AND);
1568 setTargetDAGCombine(ISD::ADD);
1569 setTargetDAGCombine(ISD::FADD);
1570 setTargetDAGCombine(ISD::FSUB);
1571 setTargetDAGCombine(ISD::FMA);
1572 setTargetDAGCombine(ISD::SUB);
1573 setTargetDAGCombine(ISD::LOAD);
1574 setTargetDAGCombine(ISD::STORE);
1575 setTargetDAGCombine(ISD::ZERO_EXTEND);
1576 setTargetDAGCombine(ISD::ANY_EXTEND);
1577 setTargetDAGCombine(ISD::SIGN_EXTEND);
1578 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1579 setTargetDAGCombine(ISD::TRUNCATE);
1580 setTargetDAGCombine(ISD::SINT_TO_FP);
1581 setTargetDAGCombine(ISD::SETCC);
1582 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1583 setTargetDAGCombine(ISD::BUILD_VECTOR);
1584 if (Subtarget->is64Bit())
1585 setTargetDAGCombine(ISD::MUL);
1586 setTargetDAGCombine(ISD::XOR);
1588 computeRegisterProperties();
1590 // On Darwin, -Os means optimize for size without hurting performance,
1591 // do not reduce the limit.
1592 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1593 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1594 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1595 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1596 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1597 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1598 setPrefLoopAlignment(4); // 2^4 bytes.
1600 // Predictable cmov don't hurt on atom because it's in-order.
1601 PredictableSelectIsExpensive = !Subtarget->isAtom();
1603 setPrefFunctionAlignment(4); // 2^4 bytes.
1606 TargetLoweringBase::LegalizeTypeAction
1607 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1608 if (ExperimentalVectorWideningLegalization &&
1609 VT.getVectorNumElements() != 1 &&
1610 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1611 return TypeWidenVector;
1613 return TargetLoweringBase::getPreferredVectorAction(VT);
1616 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1618 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1620 if (Subtarget->hasAVX512())
1621 switch(VT.getVectorNumElements()) {
1622 case 8: return MVT::v8i1;
1623 case 16: return MVT::v16i1;
1626 return VT.changeVectorElementTypeToInteger();
1629 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1630 /// the desired ByVal argument alignment.
1631 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1634 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1635 if (VTy->getBitWidth() == 128)
1637 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1638 unsigned EltAlign = 0;
1639 getMaxByValAlign(ATy->getElementType(), EltAlign);
1640 if (EltAlign > MaxAlign)
1641 MaxAlign = EltAlign;
1642 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1643 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1644 unsigned EltAlign = 0;
1645 getMaxByValAlign(STy->getElementType(i), EltAlign);
1646 if (EltAlign > MaxAlign)
1647 MaxAlign = EltAlign;
1654 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1655 /// function arguments in the caller parameter area. For X86, aggregates
1656 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1657 /// are at 4-byte boundaries.
1658 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1659 if (Subtarget->is64Bit()) {
1660 // Max of 8 and alignment of type.
1661 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1668 if (Subtarget->hasSSE1())
1669 getMaxByValAlign(Ty, Align);
1673 /// getOptimalMemOpType - Returns the target specific optimal type for load
1674 /// and store operations as a result of memset, memcpy, and memmove
1675 /// lowering. If DstAlign is zero that means it's safe to destination
1676 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1677 /// means there isn't a need to check it against alignment requirement,
1678 /// probably because the source does not need to be loaded. If 'IsMemset' is
1679 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1680 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1681 /// source is constant so it does not need to be loaded.
1682 /// It returns EVT::Other if the type should be determined using generic
1683 /// target-independent logic.
1685 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1686 unsigned DstAlign, unsigned SrcAlign,
1687 bool IsMemset, bool ZeroMemset,
1689 MachineFunction &MF) const {
1690 const Function *F = MF.getFunction();
1691 if ((!IsMemset || ZeroMemset) &&
1692 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1693 Attribute::NoImplicitFloat)) {
1695 (Subtarget->isUnalignedMemAccessFast() ||
1696 ((DstAlign == 0 || DstAlign >= 16) &&
1697 (SrcAlign == 0 || SrcAlign >= 16)))) {
1699 if (Subtarget->hasInt256())
1701 if (Subtarget->hasFp256())
1704 if (Subtarget->hasSSE2())
1706 if (Subtarget->hasSSE1())
1708 } else if (!MemcpyStrSrc && Size >= 8 &&
1709 !Subtarget->is64Bit() &&
1710 Subtarget->hasSSE2()) {
1711 // Do not use f64 to lower memcpy if source is string constant. It's
1712 // better to use i32 to avoid the loads.
1716 if (Subtarget->is64Bit() && Size >= 8)
1721 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1723 return X86ScalarSSEf32;
1724 else if (VT == MVT::f64)
1725 return X86ScalarSSEf64;
1730 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1734 *Fast = Subtarget->isUnalignedMemAccessFast();
1738 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1739 /// current function. The returned value is a member of the
1740 /// MachineJumpTableInfo::JTEntryKind enum.
1741 unsigned X86TargetLowering::getJumpTableEncoding() const {
1742 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1744 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1745 Subtarget->isPICStyleGOT())
1746 return MachineJumpTableInfo::EK_Custom32;
1748 // Otherwise, use the normal jump table encoding heuristics.
1749 return TargetLowering::getJumpTableEncoding();
1753 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1754 const MachineBasicBlock *MBB,
1755 unsigned uid,MCContext &Ctx) const{
1756 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1757 Subtarget->isPICStyleGOT());
1758 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1760 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1761 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1764 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1766 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1767 SelectionDAG &DAG) const {
1768 if (!Subtarget->is64Bit())
1769 // This doesn't have SDLoc associated with it, but is not really the
1770 // same as a Register.
1771 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1775 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1776 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1778 const MCExpr *X86TargetLowering::
1779 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1780 MCContext &Ctx) const {
1781 // X86-64 uses RIP relative addressing based on the jump table label.
1782 if (Subtarget->isPICStyleRIPRel())
1783 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1785 // Otherwise, the reference is relative to the PIC base.
1786 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1789 // FIXME: Why this routine is here? Move to RegInfo!
1790 std::pair<const TargetRegisterClass*, uint8_t>
1791 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1792 const TargetRegisterClass *RRC = nullptr;
1794 switch (VT.SimpleTy) {
1796 return TargetLowering::findRepresentativeClass(VT);
1797 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1798 RRC = Subtarget->is64Bit() ?
1799 (const TargetRegisterClass*)&X86::GR64RegClass :
1800 (const TargetRegisterClass*)&X86::GR32RegClass;
1803 RRC = &X86::VR64RegClass;
1805 case MVT::f32: case MVT::f64:
1806 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1807 case MVT::v4f32: case MVT::v2f64:
1808 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1810 RRC = &X86::VR128RegClass;
1813 return std::make_pair(RRC, Cost);
1816 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1817 unsigned &Offset) const {
1818 if (!Subtarget->isTargetLinux())
1821 if (Subtarget->is64Bit()) {
1822 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1824 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1836 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1837 unsigned DestAS) const {
1838 assert(SrcAS != DestAS && "Expected different address spaces!");
1840 return SrcAS < 256 && DestAS < 256;
1843 //===----------------------------------------------------------------------===//
1844 // Return Value Calling Convention Implementation
1845 //===----------------------------------------------------------------------===//
1847 #include "X86GenCallingConv.inc"
1850 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1851 MachineFunction &MF, bool isVarArg,
1852 const SmallVectorImpl<ISD::OutputArg> &Outs,
1853 LLVMContext &Context) const {
1854 SmallVector<CCValAssign, 16> RVLocs;
1855 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1857 return CCInfo.CheckReturn(Outs, RetCC_X86);
1860 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1861 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1866 X86TargetLowering::LowerReturn(SDValue Chain,
1867 CallingConv::ID CallConv, bool isVarArg,
1868 const SmallVectorImpl<ISD::OutputArg> &Outs,
1869 const SmallVectorImpl<SDValue> &OutVals,
1870 SDLoc dl, SelectionDAG &DAG) const {
1871 MachineFunction &MF = DAG.getMachineFunction();
1872 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1874 SmallVector<CCValAssign, 16> RVLocs;
1875 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1876 RVLocs, *DAG.getContext());
1877 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1880 SmallVector<SDValue, 6> RetOps;
1881 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1882 // Operand #1 = Bytes To Pop
1883 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1886 // Copy the result values into the output registers.
1887 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1888 CCValAssign &VA = RVLocs[i];
1889 assert(VA.isRegLoc() && "Can only return in registers!");
1890 SDValue ValToCopy = OutVals[i];
1891 EVT ValVT = ValToCopy.getValueType();
1893 // Promote values to the appropriate types
1894 if (VA.getLocInfo() == CCValAssign::SExt)
1895 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1896 else if (VA.getLocInfo() == CCValAssign::ZExt)
1897 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1898 else if (VA.getLocInfo() == CCValAssign::AExt)
1899 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1900 else if (VA.getLocInfo() == CCValAssign::BCvt)
1901 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1903 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1904 "Unexpected FP-extend for return value.");
1906 // If this is x86-64, and we disabled SSE, we can't return FP values,
1907 // or SSE or MMX vectors.
1908 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1909 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1910 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1911 report_fatal_error("SSE register return with SSE disabled");
1913 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1914 // llvm-gcc has never done it right and no one has noticed, so this
1915 // should be OK for now.
1916 if (ValVT == MVT::f64 &&
1917 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1918 report_fatal_error("SSE2 register return with SSE2 disabled");
1920 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1921 // the RET instruction and handled by the FP Stackifier.
1922 if (VA.getLocReg() == X86::ST0 ||
1923 VA.getLocReg() == X86::ST1) {
1924 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1925 // change the value to the FP stack register class.
1926 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1927 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1928 RetOps.push_back(ValToCopy);
1929 // Don't emit a copytoreg.
1933 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1934 // which is returned in RAX / RDX.
1935 if (Subtarget->is64Bit()) {
1936 if (ValVT == MVT::x86mmx) {
1937 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1938 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1939 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1941 // If we don't have SSE2 available, convert to v4f32 so the generated
1942 // register is legal.
1943 if (!Subtarget->hasSSE2())
1944 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1949 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1950 Flag = Chain.getValue(1);
1951 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1954 // The x86-64 ABIs require that for returning structs by value we copy
1955 // the sret argument into %rax/%eax (depending on ABI) for the return.
1956 // Win32 requires us to put the sret argument to %eax as well.
1957 // We saved the argument into a virtual register in the entry block,
1958 // so now we copy the value out and into %rax/%eax.
1959 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1960 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1961 MachineFunction &MF = DAG.getMachineFunction();
1962 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1963 unsigned Reg = FuncInfo->getSRetReturnReg();
1965 "SRetReturnReg should have been set in LowerFormalArguments().");
1966 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1969 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1970 X86::RAX : X86::EAX;
1971 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1972 Flag = Chain.getValue(1);
1974 // RAX/EAX now acts like a return value.
1975 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1978 RetOps[0] = Chain; // Update chain.
1980 // Add the flag if we have it.
1982 RetOps.push_back(Flag);
1984 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1987 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1988 if (N->getNumValues() != 1)
1990 if (!N->hasNUsesOfValue(1, 0))
1993 SDValue TCChain = Chain;
1994 SDNode *Copy = *N->use_begin();
1995 if (Copy->getOpcode() == ISD::CopyToReg) {
1996 // If the copy has a glue operand, we conservatively assume it isn't safe to
1997 // perform a tail call.
1998 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2000 TCChain = Copy->getOperand(0);
2001 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2004 bool HasRet = false;
2005 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2007 if (UI->getOpcode() != X86ISD::RET_FLAG)
2020 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2021 ISD::NodeType ExtendKind) const {
2023 // TODO: Is this also valid on 32-bit?
2024 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2025 ReturnMVT = MVT::i8;
2027 ReturnMVT = MVT::i32;
2029 MVT MinVT = getRegisterType(ReturnMVT);
2030 return VT.bitsLT(MinVT) ? MinVT : VT;
2033 /// LowerCallResult - Lower the result values of a call into the
2034 /// appropriate copies out of appropriate physical registers.
2037 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2038 CallingConv::ID CallConv, bool isVarArg,
2039 const SmallVectorImpl<ISD::InputArg> &Ins,
2040 SDLoc dl, SelectionDAG &DAG,
2041 SmallVectorImpl<SDValue> &InVals) const {
2043 // Assign locations to each value returned by this call.
2044 SmallVector<CCValAssign, 16> RVLocs;
2045 bool Is64Bit = Subtarget->is64Bit();
2046 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2047 DAG.getTarget(), RVLocs, *DAG.getContext());
2048 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2050 // Copy all of the result registers out of their specified physreg.
2051 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2052 CCValAssign &VA = RVLocs[i];
2053 EVT CopyVT = VA.getValVT();
2055 // If this is x86-64, and we disabled SSE, we can't return FP values
2056 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2057 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2058 report_fatal_error("SSE register return with SSE disabled");
2063 // If this is a call to a function that returns an fp value on the floating
2064 // point stack, we must guarantee the value is popped from the stack, so
2065 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2066 // if the return value is not used. We use the FpPOP_RETVAL instruction
2068 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2069 // If we prefer to use the value in xmm registers, copy it out as f80 and
2070 // use a truncate to move it from fp stack reg to xmm reg.
2071 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2072 SDValue Ops[] = { Chain, InFlag };
2073 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2074 MVT::Other, MVT::Glue, Ops), 1);
2075 Val = Chain.getValue(0);
2077 // Round the f80 to the right size, which also moves it to the appropriate
2079 if (CopyVT != VA.getValVT())
2080 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2081 // This truncation won't change the value.
2082 DAG.getIntPtrConstant(1));
2084 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2085 CopyVT, InFlag).getValue(1);
2086 Val = Chain.getValue(0);
2088 InFlag = Chain.getValue(2);
2089 InVals.push_back(Val);
2095 //===----------------------------------------------------------------------===//
2096 // C & StdCall & Fast Calling Convention implementation
2097 //===----------------------------------------------------------------------===//
2098 // StdCall calling convention seems to be standard for many Windows' API
2099 // routines and around. It differs from C calling convention just a little:
2100 // callee should clean up the stack, not caller. Symbols should be also
2101 // decorated in some fancy way :) It doesn't support any vector arguments.
2102 // For info on fast calling convention see Fast Calling Convention (tail call)
2103 // implementation LowerX86_32FastCCCallTo.
2105 /// CallIsStructReturn - Determines whether a call uses struct return
2107 enum StructReturnType {
2112 static StructReturnType
2113 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2115 return NotStructReturn;
2117 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2118 if (!Flags.isSRet())
2119 return NotStructReturn;
2120 if (Flags.isInReg())
2121 return RegStructReturn;
2122 return StackStructReturn;
2125 /// ArgsAreStructReturn - Determines whether a function uses struct
2126 /// return semantics.
2127 static StructReturnType
2128 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2130 return NotStructReturn;
2132 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2133 if (!Flags.isSRet())
2134 return NotStructReturn;
2135 if (Flags.isInReg())
2136 return RegStructReturn;
2137 return StackStructReturn;
2140 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2141 /// by "Src" to address "Dst" with size and alignment information specified by
2142 /// the specific parameter attribute. The copy will be passed as a byval
2143 /// function parameter.
2145 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2146 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2148 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2150 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2151 /*isVolatile*/false, /*AlwaysInline=*/true,
2152 MachinePointerInfo(), MachinePointerInfo());
2155 /// IsTailCallConvention - Return true if the calling convention is one that
2156 /// supports tail call optimization.
2157 static bool IsTailCallConvention(CallingConv::ID CC) {
2158 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2159 CC == CallingConv::HiPE);
2162 /// \brief Return true if the calling convention is a C calling convention.
2163 static bool IsCCallConvention(CallingConv::ID CC) {
2164 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2165 CC == CallingConv::X86_64_SysV);
2168 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2169 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2173 CallingConv::ID CalleeCC = CS.getCallingConv();
2174 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2180 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2181 /// a tailcall target by changing its ABI.
2182 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2183 bool GuaranteedTailCallOpt) {
2184 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2188 X86TargetLowering::LowerMemArgument(SDValue Chain,
2189 CallingConv::ID CallConv,
2190 const SmallVectorImpl<ISD::InputArg> &Ins,
2191 SDLoc dl, SelectionDAG &DAG,
2192 const CCValAssign &VA,
2193 MachineFrameInfo *MFI,
2195 // Create the nodes corresponding to a load from this parameter slot.
2196 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2197 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2198 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2199 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2202 // If value is passed by pointer we have address passed instead of the value
2204 if (VA.getLocInfo() == CCValAssign::Indirect)
2205 ValVT = VA.getLocVT();
2207 ValVT = VA.getValVT();
2209 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2210 // changed with more analysis.
2211 // In case of tail call optimization mark all arguments mutable. Since they
2212 // could be overwritten by lowering of arguments in case of a tail call.
2213 if (Flags.isByVal()) {
2214 unsigned Bytes = Flags.getByValSize();
2215 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2216 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2217 return DAG.getFrameIndex(FI, getPointerTy());
2219 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2220 VA.getLocMemOffset(), isImmutable);
2221 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2222 return DAG.getLoad(ValVT, dl, Chain, FIN,
2223 MachinePointerInfo::getFixedStack(FI),
2224 false, false, false, 0);
2229 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2230 CallingConv::ID CallConv,
2232 const SmallVectorImpl<ISD::InputArg> &Ins,
2235 SmallVectorImpl<SDValue> &InVals)
2237 MachineFunction &MF = DAG.getMachineFunction();
2238 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2240 const Function* Fn = MF.getFunction();
2241 if (Fn->hasExternalLinkage() &&
2242 Subtarget->isTargetCygMing() &&
2243 Fn->getName() == "main")
2244 FuncInfo->setForceFramePointer(true);
2246 MachineFrameInfo *MFI = MF.getFrameInfo();
2247 bool Is64Bit = Subtarget->is64Bit();
2248 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2250 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2251 "Var args not supported with calling convention fastcc, ghc or hipe");
2253 // Assign locations to all of the incoming arguments.
2254 SmallVector<CCValAssign, 16> ArgLocs;
2255 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2256 ArgLocs, *DAG.getContext());
2258 // Allocate shadow area for Win64
2260 CCInfo.AllocateStack(32, 8);
2262 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2264 unsigned LastVal = ~0U;
2266 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2267 CCValAssign &VA = ArgLocs[i];
2268 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2270 assert(VA.getValNo() != LastVal &&
2271 "Don't support value assigned to multiple locs yet");
2273 LastVal = VA.getValNo();
2275 if (VA.isRegLoc()) {
2276 EVT RegVT = VA.getLocVT();
2277 const TargetRegisterClass *RC;
2278 if (RegVT == MVT::i32)
2279 RC = &X86::GR32RegClass;
2280 else if (Is64Bit && RegVT == MVT::i64)
2281 RC = &X86::GR64RegClass;
2282 else if (RegVT == MVT::f32)
2283 RC = &X86::FR32RegClass;
2284 else if (RegVT == MVT::f64)
2285 RC = &X86::FR64RegClass;
2286 else if (RegVT.is512BitVector())
2287 RC = &X86::VR512RegClass;
2288 else if (RegVT.is256BitVector())
2289 RC = &X86::VR256RegClass;
2290 else if (RegVT.is128BitVector())
2291 RC = &X86::VR128RegClass;
2292 else if (RegVT == MVT::x86mmx)
2293 RC = &X86::VR64RegClass;
2294 else if (RegVT == MVT::i1)
2295 RC = &X86::VK1RegClass;
2296 else if (RegVT == MVT::v8i1)
2297 RC = &X86::VK8RegClass;
2298 else if (RegVT == MVT::v16i1)
2299 RC = &X86::VK16RegClass;
2301 llvm_unreachable("Unknown argument type!");
2303 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2304 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2306 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2307 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2309 if (VA.getLocInfo() == CCValAssign::SExt)
2310 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2311 DAG.getValueType(VA.getValVT()));
2312 else if (VA.getLocInfo() == CCValAssign::ZExt)
2313 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2314 DAG.getValueType(VA.getValVT()));
2315 else if (VA.getLocInfo() == CCValAssign::BCvt)
2316 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2318 if (VA.isExtInLoc()) {
2319 // Handle MMX values passed in XMM regs.
2320 if (RegVT.isVector())
2321 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2323 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2326 assert(VA.isMemLoc());
2327 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2330 // If value is passed via pointer - do a load.
2331 if (VA.getLocInfo() == CCValAssign::Indirect)
2332 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2333 MachinePointerInfo(), false, false, false, 0);
2335 InVals.push_back(ArgValue);
2338 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2339 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2340 // The x86-64 ABIs require that for returning structs by value we copy
2341 // the sret argument into %rax/%eax (depending on ABI) for the return.
2342 // Win32 requires us to put the sret argument to %eax as well.
2343 // Save the argument into a virtual register so that we can access it
2344 // from the return points.
2345 if (Ins[i].Flags.isSRet()) {
2346 unsigned Reg = FuncInfo->getSRetReturnReg();
2348 MVT PtrTy = getPointerTy();
2349 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2350 FuncInfo->setSRetReturnReg(Reg);
2352 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2353 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2359 unsigned StackSize = CCInfo.getNextStackOffset();
2360 // Align stack specially for tail calls.
2361 if (FuncIsMadeTailCallSafe(CallConv,
2362 MF.getTarget().Options.GuaranteedTailCallOpt))
2363 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2365 // If the function takes variable number of arguments, make a frame index for
2366 // the start of the first vararg value... for expansion of llvm.va_start.
2368 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2369 CallConv != CallingConv::X86_ThisCall)) {
2370 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2373 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2375 // FIXME: We should really autogenerate these arrays
2376 static const MCPhysReg GPR64ArgRegsWin64[] = {
2377 X86::RCX, X86::RDX, X86::R8, X86::R9
2379 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2380 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2382 static const MCPhysReg XMMArgRegs64Bit[] = {
2383 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2384 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2386 const MCPhysReg *GPR64ArgRegs;
2387 unsigned NumXMMRegs = 0;
2390 // The XMM registers which might contain var arg parameters are shadowed
2391 // in their paired GPR. So we only need to save the GPR to their home
2393 TotalNumIntRegs = 4;
2394 GPR64ArgRegs = GPR64ArgRegsWin64;
2396 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2397 GPR64ArgRegs = GPR64ArgRegs64Bit;
2399 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2402 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2405 bool NoImplicitFloatOps = Fn->getAttributes().
2406 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2407 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2408 "SSE register cannot be used when SSE is disabled!");
2409 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2410 NoImplicitFloatOps) &&
2411 "SSE register cannot be used when SSE is disabled!");
2412 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2413 !Subtarget->hasSSE1())
2414 // Kernel mode asks for SSE to be disabled, so don't push them
2416 TotalNumXMMRegs = 0;
2419 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
2420 // Get to the caller-allocated home save location. Add 8 to account
2421 // for the return address.
2422 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2423 FuncInfo->setRegSaveFrameIndex(
2424 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2425 // Fixup to set vararg frame on shadow area (4 x i64).
2427 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2429 // For X86-64, if there are vararg parameters that are passed via
2430 // registers, then we must store them to their spots on the stack so
2431 // they may be loaded by deferencing the result of va_next.
2432 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2433 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2434 FuncInfo->setRegSaveFrameIndex(
2435 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2439 // Store the integer parameter registers.
2440 SmallVector<SDValue, 8> MemOps;
2441 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2443 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2444 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2445 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2446 DAG.getIntPtrConstant(Offset));
2447 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2448 &X86::GR64RegClass);
2449 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2451 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2452 MachinePointerInfo::getFixedStack(
2453 FuncInfo->getRegSaveFrameIndex(), Offset),
2455 MemOps.push_back(Store);
2459 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2460 // Now store the XMM (fp + vector) parameter registers.
2461 SmallVector<SDValue, 11> SaveXMMOps;
2462 SaveXMMOps.push_back(Chain);
2464 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2465 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2466 SaveXMMOps.push_back(ALVal);
2468 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2469 FuncInfo->getRegSaveFrameIndex()));
2470 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2471 FuncInfo->getVarArgsFPOffset()));
2473 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2474 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2475 &X86::VR128RegClass);
2476 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2477 SaveXMMOps.push_back(Val);
2479 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2480 MVT::Other, SaveXMMOps));
2483 if (!MemOps.empty())
2484 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2488 // Some CCs need callee pop.
2489 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2490 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2491 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2493 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2494 // If this is an sret function, the return should pop the hidden pointer.
2495 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2496 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2497 argsAreStructReturn(Ins) == StackStructReturn)
2498 FuncInfo->setBytesToPopOnReturn(4);
2502 // RegSaveFrameIndex is X86-64 only.
2503 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2504 if (CallConv == CallingConv::X86_FastCall ||
2505 CallConv == CallingConv::X86_ThisCall)
2506 // fastcc functions can't have varargs.
2507 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2510 FuncInfo->setArgumentStackSize(StackSize);
2516 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2517 SDValue StackPtr, SDValue Arg,
2518 SDLoc dl, SelectionDAG &DAG,
2519 const CCValAssign &VA,
2520 ISD::ArgFlagsTy Flags) const {
2521 unsigned LocMemOffset = VA.getLocMemOffset();
2522 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2523 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2524 if (Flags.isByVal())
2525 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2527 return DAG.getStore(Chain, dl, Arg, PtrOff,
2528 MachinePointerInfo::getStack(LocMemOffset),
2532 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2533 /// optimization is performed and it is required.
2535 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2536 SDValue &OutRetAddr, SDValue Chain,
2537 bool IsTailCall, bool Is64Bit,
2538 int FPDiff, SDLoc dl) const {
2539 // Adjust the Return address stack slot.
2540 EVT VT = getPointerTy();
2541 OutRetAddr = getReturnAddressFrameIndex(DAG);
2543 // Load the "old" Return address.
2544 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2545 false, false, false, 0);
2546 return SDValue(OutRetAddr.getNode(), 1);
2549 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2550 /// optimization is performed and it is required (FPDiff!=0).
2551 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2552 SDValue Chain, SDValue RetAddrFrIdx,
2553 EVT PtrVT, unsigned SlotSize,
2554 int FPDiff, SDLoc dl) {
2555 // Store the return address to the appropriate stack slot.
2556 if (!FPDiff) return Chain;
2557 // Calculate the new stack slot for the return address.
2558 int NewReturnAddrFI =
2559 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2561 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2562 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2563 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2569 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2570 SmallVectorImpl<SDValue> &InVals) const {
2571 SelectionDAG &DAG = CLI.DAG;
2573 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2574 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2575 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2576 SDValue Chain = CLI.Chain;
2577 SDValue Callee = CLI.Callee;
2578 CallingConv::ID CallConv = CLI.CallConv;
2579 bool &isTailCall = CLI.IsTailCall;
2580 bool isVarArg = CLI.IsVarArg;
2582 MachineFunction &MF = DAG.getMachineFunction();
2583 bool Is64Bit = Subtarget->is64Bit();
2584 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2585 StructReturnType SR = callIsStructReturn(Outs);
2586 bool IsSibcall = false;
2588 if (MF.getTarget().Options.DisableTailCalls)
2591 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2593 // Force this to be a tail call. The verifier rules are enough to ensure
2594 // that we can lower this successfully without moving the return address
2597 } else if (isTailCall) {
2598 // Check if it's really possible to do a tail call.
2599 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2600 isVarArg, SR != NotStructReturn,
2601 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2602 Outs, OutVals, Ins, DAG);
2604 // Sibcalls are automatically detected tailcalls which do not require
2606 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2613 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2614 "Var args not supported with calling convention fastcc, ghc or hipe");
2616 // Analyze operands of the call, assigning locations to each operand.
2617 SmallVector<CCValAssign, 16> ArgLocs;
2618 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2619 ArgLocs, *DAG.getContext());
2621 // Allocate shadow area for Win64
2623 CCInfo.AllocateStack(32, 8);
2625 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2627 // Get a count of how many bytes are to be pushed on the stack.
2628 unsigned NumBytes = CCInfo.getNextStackOffset();
2630 // This is a sibcall. The memory operands are available in caller's
2631 // own caller's stack.
2633 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2634 IsTailCallConvention(CallConv))
2635 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2638 if (isTailCall && !IsSibcall && !IsMustTail) {
2639 // Lower arguments at fp - stackoffset + fpdiff.
2640 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2641 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2643 FPDiff = NumBytesCallerPushed - NumBytes;
2645 // Set the delta of movement of the returnaddr stackslot.
2646 // But only set if delta is greater than previous delta.
2647 if (FPDiff < X86Info->getTCReturnAddrDelta())
2648 X86Info->setTCReturnAddrDelta(FPDiff);
2651 unsigned NumBytesToPush = NumBytes;
2652 unsigned NumBytesToPop = NumBytes;
2654 // If we have an inalloca argument, all stack space has already been allocated
2655 // for us and be right at the top of the stack. We don't support multiple
2656 // arguments passed in memory when using inalloca.
2657 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2659 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2660 "an inalloca argument must be the only memory argument");
2664 Chain = DAG.getCALLSEQ_START(
2665 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2667 SDValue RetAddrFrIdx;
2668 // Load return address for tail calls.
2669 if (isTailCall && FPDiff)
2670 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2671 Is64Bit, FPDiff, dl);
2673 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2674 SmallVector<SDValue, 8> MemOpChains;
2677 // Walk the register/memloc assignments, inserting copies/loads. In the case
2678 // of tail call optimization arguments are handle later.
2679 const X86RegisterInfo *RegInfo =
2680 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
2681 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2682 // Skip inalloca arguments, they have already been written.
2683 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2684 if (Flags.isInAlloca())
2687 CCValAssign &VA = ArgLocs[i];
2688 EVT RegVT = VA.getLocVT();
2689 SDValue Arg = OutVals[i];
2690 bool isByVal = Flags.isByVal();
2692 // Promote the value if needed.
2693 switch (VA.getLocInfo()) {
2694 default: llvm_unreachable("Unknown loc info!");
2695 case CCValAssign::Full: break;
2696 case CCValAssign::SExt:
2697 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2699 case CCValAssign::ZExt:
2700 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2702 case CCValAssign::AExt:
2703 if (RegVT.is128BitVector()) {
2704 // Special case: passing MMX values in XMM registers.
2705 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2706 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2707 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2709 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2711 case CCValAssign::BCvt:
2712 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2714 case CCValAssign::Indirect: {
2715 // Store the argument.
2716 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2717 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2718 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2719 MachinePointerInfo::getFixedStack(FI),
2726 if (VA.isRegLoc()) {
2727 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2728 if (isVarArg && IsWin64) {
2729 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2730 // shadow reg if callee is a varargs function.
2731 unsigned ShadowReg = 0;
2732 switch (VA.getLocReg()) {
2733 case X86::XMM0: ShadowReg = X86::RCX; break;
2734 case X86::XMM1: ShadowReg = X86::RDX; break;
2735 case X86::XMM2: ShadowReg = X86::R8; break;
2736 case X86::XMM3: ShadowReg = X86::R9; break;
2739 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2741 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2742 assert(VA.isMemLoc());
2743 if (!StackPtr.getNode())
2744 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2746 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2747 dl, DAG, VA, Flags));
2751 if (!MemOpChains.empty())
2752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2754 if (Subtarget->isPICStyleGOT()) {
2755 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2758 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2759 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2761 // If we are tail calling and generating PIC/GOT style code load the
2762 // address of the callee into ECX. The value in ecx is used as target of
2763 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2764 // for tail calls on PIC/GOT architectures. Normally we would just put the
2765 // address of GOT into ebx and then call target@PLT. But for tail calls
2766 // ebx would be restored (since ebx is callee saved) before jumping to the
2769 // Note: The actual moving to ECX is done further down.
2770 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2771 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2772 !G->getGlobal()->hasProtectedVisibility())
2773 Callee = LowerGlobalAddress(Callee, DAG);
2774 else if (isa<ExternalSymbolSDNode>(Callee))
2775 Callee = LowerExternalSymbol(Callee, DAG);
2779 if (Is64Bit && isVarArg && !IsWin64) {
2780 // From AMD64 ABI document:
2781 // For calls that may call functions that use varargs or stdargs
2782 // (prototype-less calls or calls to functions containing ellipsis (...) in
2783 // the declaration) %al is used as hidden argument to specify the number
2784 // of SSE registers used. The contents of %al do not need to match exactly
2785 // the number of registers, but must be an ubound on the number of SSE
2786 // registers used and is in the range 0 - 8 inclusive.
2788 // Count the number of XMM registers allocated.
2789 static const MCPhysReg XMMArgRegs[] = {
2790 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2791 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2793 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2794 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2795 && "SSE registers cannot be used when SSE is disabled");
2797 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2798 DAG.getConstant(NumXMMRegs, MVT::i8)));
2801 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2802 // don't need this because the eligibility check rejects calls that require
2803 // shuffling arguments passed in memory.
2804 if (!IsSibcall && isTailCall) {
2805 // Force all the incoming stack arguments to be loaded from the stack
2806 // before any new outgoing arguments are stored to the stack, because the
2807 // outgoing stack slots may alias the incoming argument stack slots, and
2808 // the alias isn't otherwise explicit. This is slightly more conservative
2809 // than necessary, because it means that each store effectively depends
2810 // on every argument instead of just those arguments it would clobber.
2811 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2813 SmallVector<SDValue, 8> MemOpChains2;
2816 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2817 CCValAssign &VA = ArgLocs[i];
2820 assert(VA.isMemLoc());
2821 SDValue Arg = OutVals[i];
2822 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2823 // Skip inalloca arguments. They don't require any work.
2824 if (Flags.isInAlloca())
2826 // Create frame index.
2827 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2828 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2829 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2830 FIN = DAG.getFrameIndex(FI, getPointerTy());
2832 if (Flags.isByVal()) {
2833 // Copy relative to framepointer.
2834 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2835 if (!StackPtr.getNode())
2836 StackPtr = DAG.getCopyFromReg(Chain, dl,
2837 RegInfo->getStackRegister(),
2839 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2841 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2845 // Store relative to framepointer.
2846 MemOpChains2.push_back(
2847 DAG.getStore(ArgChain, dl, Arg, FIN,
2848 MachinePointerInfo::getFixedStack(FI),
2853 if (!MemOpChains2.empty())
2854 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2856 // Store the return address to the appropriate stack slot.
2857 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2858 getPointerTy(), RegInfo->getSlotSize(),
2862 // Build a sequence of copy-to-reg nodes chained together with token chain
2863 // and flag operands which copy the outgoing args into registers.
2865 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2866 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2867 RegsToPass[i].second, InFlag);
2868 InFlag = Chain.getValue(1);
2871 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2872 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2873 // In the 64-bit large code model, we have to make all calls
2874 // through a register, since the call instruction's 32-bit
2875 // pc-relative offset may not be large enough to hold the whole
2877 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2878 // If the callee is a GlobalAddress node (quite common, every direct call
2879 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2882 // We should use extra load for direct calls to dllimported functions in
2884 const GlobalValue *GV = G->getGlobal();
2885 if (!GV->hasDLLImportStorageClass()) {
2886 unsigned char OpFlags = 0;
2887 bool ExtraLoad = false;
2888 unsigned WrapperKind = ISD::DELETED_NODE;
2890 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2891 // external symbols most go through the PLT in PIC mode. If the symbol
2892 // has hidden or protected visibility, or if it is static or local, then
2893 // we don't need to use the PLT - we can directly call it.
2894 if (Subtarget->isTargetELF() &&
2895 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2896 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2897 OpFlags = X86II::MO_PLT;
2898 } else if (Subtarget->isPICStyleStubAny() &&
2899 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2900 (!Subtarget->getTargetTriple().isMacOSX() ||
2901 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2902 // PC-relative references to external symbols should go through $stub,
2903 // unless we're building with the leopard linker or later, which
2904 // automatically synthesizes these stubs.
2905 OpFlags = X86II::MO_DARWIN_STUB;
2906 } else if (Subtarget->isPICStyleRIPRel() &&
2907 isa<Function>(GV) &&
2908 cast<Function>(GV)->getAttributes().
2909 hasAttribute(AttributeSet::FunctionIndex,
2910 Attribute::NonLazyBind)) {
2911 // If the function is marked as non-lazy, generate an indirect call
2912 // which loads from the GOT directly. This avoids runtime overhead
2913 // at the cost of eager binding (and one extra byte of encoding).
2914 OpFlags = X86II::MO_GOTPCREL;
2915 WrapperKind = X86ISD::WrapperRIP;
2919 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2920 G->getOffset(), OpFlags);
2922 // Add a wrapper if needed.
2923 if (WrapperKind != ISD::DELETED_NODE)
2924 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2925 // Add extra indirection if needed.
2927 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2928 MachinePointerInfo::getGOT(),
2929 false, false, false, 0);
2931 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2932 unsigned char OpFlags = 0;
2934 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2935 // external symbols should go through the PLT.
2936 if (Subtarget->isTargetELF() &&
2937 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2938 OpFlags = X86II::MO_PLT;
2939 } else if (Subtarget->isPICStyleStubAny() &&
2940 (!Subtarget->getTargetTriple().isMacOSX() ||
2941 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2942 // PC-relative references to external symbols should go through $stub,
2943 // unless we're building with the leopard linker or later, which
2944 // automatically synthesizes these stubs.
2945 OpFlags = X86II::MO_DARWIN_STUB;
2948 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2952 // Returns a chain & a flag for retval copy to use.
2953 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2954 SmallVector<SDValue, 8> Ops;
2956 if (!IsSibcall && isTailCall) {
2957 Chain = DAG.getCALLSEQ_END(Chain,
2958 DAG.getIntPtrConstant(NumBytesToPop, true),
2959 DAG.getIntPtrConstant(0, true), InFlag, dl);
2960 InFlag = Chain.getValue(1);
2963 Ops.push_back(Chain);
2964 Ops.push_back(Callee);
2967 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2969 // Add argument registers to the end of the list so that they are known live
2971 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2972 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2973 RegsToPass[i].second.getValueType()));
2975 // Add a register mask operand representing the call-preserved registers.
2976 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
2977 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2978 assert(Mask && "Missing call preserved mask for calling convention");
2979 Ops.push_back(DAG.getRegisterMask(Mask));
2981 if (InFlag.getNode())
2982 Ops.push_back(InFlag);
2986 //// If this is the first return lowered for this function, add the regs
2987 //// to the liveout set for the function.
2988 // This isn't right, although it's probably harmless on x86; liveouts
2989 // should be computed from returns not tail calls. Consider a void
2990 // function making a tail call to a function returning int.
2991 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
2994 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
2995 InFlag = Chain.getValue(1);
2997 // Create the CALLSEQ_END node.
2998 unsigned NumBytesForCalleeToPop;
2999 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3000 DAG.getTarget().Options.GuaranteedTailCallOpt))
3001 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3002 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3003 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3004 SR == StackStructReturn)
3005 // If this is a call to a struct-return function, the callee
3006 // pops the hidden struct pointer, so we have to push it back.
3007 // This is common for Darwin/X86, Linux & Mingw32 targets.
3008 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3009 NumBytesForCalleeToPop = 4;
3011 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3013 // Returns a flag for retval copy to use.
3015 Chain = DAG.getCALLSEQ_END(Chain,
3016 DAG.getIntPtrConstant(NumBytesToPop, true),
3017 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3020 InFlag = Chain.getValue(1);
3023 // Handle result values, copying them out of physregs into vregs that we
3025 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3026 Ins, dl, DAG, InVals);
3029 //===----------------------------------------------------------------------===//
3030 // Fast Calling Convention (tail call) implementation
3031 //===----------------------------------------------------------------------===//
3033 // Like std call, callee cleans arguments, convention except that ECX is
3034 // reserved for storing the tail called function address. Only 2 registers are
3035 // free for argument passing (inreg). Tail call optimization is performed
3037 // * tailcallopt is enabled
3038 // * caller/callee are fastcc
3039 // On X86_64 architecture with GOT-style position independent code only local
3040 // (within module) calls are supported at the moment.
3041 // To keep the stack aligned according to platform abi the function
3042 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3043 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3044 // If a tail called function callee has more arguments than the caller the
3045 // caller needs to make sure that there is room to move the RETADDR to. This is
3046 // achieved by reserving an area the size of the argument delta right after the
3047 // original REtADDR, but before the saved framepointer or the spilled registers
3048 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3060 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3061 /// for a 16 byte align requirement.
3063 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3064 SelectionDAG& DAG) const {
3065 MachineFunction &MF = DAG.getMachineFunction();
3066 const TargetMachine &TM = MF.getTarget();
3067 const X86RegisterInfo *RegInfo =
3068 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3069 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3070 unsigned StackAlignment = TFI.getStackAlignment();
3071 uint64_t AlignMask = StackAlignment - 1;
3072 int64_t Offset = StackSize;
3073 unsigned SlotSize = RegInfo->getSlotSize();
3074 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3075 // Number smaller than 12 so just add the difference.
3076 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3078 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3079 Offset = ((~AlignMask) & Offset) + StackAlignment +
3080 (StackAlignment-SlotSize);
3085 /// MatchingStackOffset - Return true if the given stack call argument is
3086 /// already available in the same position (relatively) of the caller's
3087 /// incoming argument stack.
3089 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3090 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3091 const X86InstrInfo *TII) {
3092 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3094 if (Arg.getOpcode() == ISD::CopyFromReg) {
3095 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3096 if (!TargetRegisterInfo::isVirtualRegister(VR))
3098 MachineInstr *Def = MRI->getVRegDef(VR);
3101 if (!Flags.isByVal()) {
3102 if (!TII->isLoadFromStackSlot(Def, FI))
3105 unsigned Opcode = Def->getOpcode();
3106 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3107 Def->getOperand(1).isFI()) {
3108 FI = Def->getOperand(1).getIndex();
3109 Bytes = Flags.getByValSize();
3113 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3114 if (Flags.isByVal())
3115 // ByVal argument is passed in as a pointer but it's now being
3116 // dereferenced. e.g.
3117 // define @foo(%struct.X* %A) {
3118 // tail call @bar(%struct.X* byval %A)
3121 SDValue Ptr = Ld->getBasePtr();
3122 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3125 FI = FINode->getIndex();
3126 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3127 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3128 FI = FINode->getIndex();
3129 Bytes = Flags.getByValSize();
3133 assert(FI != INT_MAX);
3134 if (!MFI->isFixedObjectIndex(FI))
3136 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3139 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3140 /// for tail call optimization. Targets which want to do tail call
3141 /// optimization should implement this function.
3143 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3144 CallingConv::ID CalleeCC,
3146 bool isCalleeStructRet,
3147 bool isCallerStructRet,
3149 const SmallVectorImpl<ISD::OutputArg> &Outs,
3150 const SmallVectorImpl<SDValue> &OutVals,
3151 const SmallVectorImpl<ISD::InputArg> &Ins,
3152 SelectionDAG &DAG) const {
3153 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3156 // If -tailcallopt is specified, make fastcc functions tail-callable.
3157 const MachineFunction &MF = DAG.getMachineFunction();
3158 const Function *CallerF = MF.getFunction();
3160 // If the function return type is x86_fp80 and the callee return type is not,
3161 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3162 // perform a tailcall optimization here.
3163 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3166 CallingConv::ID CallerCC = CallerF->getCallingConv();
3167 bool CCMatch = CallerCC == CalleeCC;
3168 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3169 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3171 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3172 if (IsTailCallConvention(CalleeCC) && CCMatch)
3177 // Look for obvious safe cases to perform tail call optimization that do not
3178 // require ABI changes. This is what gcc calls sibcall.
3180 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3181 // emit a special epilogue.
3182 const X86RegisterInfo *RegInfo =
3183 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3184 if (RegInfo->needsStackRealignment(MF))
3187 // Also avoid sibcall optimization if either caller or callee uses struct
3188 // return semantics.
3189 if (isCalleeStructRet || isCallerStructRet)
3192 // An stdcall/thiscall caller is expected to clean up its arguments; the
3193 // callee isn't going to do that.
3194 // FIXME: this is more restrictive than needed. We could produce a tailcall
3195 // when the stack adjustment matches. For example, with a thiscall that takes
3196 // only one argument.
3197 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3198 CallerCC == CallingConv::X86_ThisCall))
3201 // Do not sibcall optimize vararg calls unless all arguments are passed via
3203 if (isVarArg && !Outs.empty()) {
3205 // Optimizing for varargs on Win64 is unlikely to be safe without
3206 // additional testing.
3207 if (IsCalleeWin64 || IsCallerWin64)
3210 SmallVector<CCValAssign, 16> ArgLocs;
3211 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3212 DAG.getTarget(), ArgLocs, *DAG.getContext());
3214 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3216 if (!ArgLocs[i].isRegLoc())
3220 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3221 // stack. Therefore, if it's not used by the call it is not safe to optimize
3222 // this into a sibcall.
3223 bool Unused = false;
3224 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3231 SmallVector<CCValAssign, 16> RVLocs;
3232 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3233 DAG.getTarget(), RVLocs, *DAG.getContext());
3234 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3235 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3236 CCValAssign &VA = RVLocs[i];
3237 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3242 // If the calling conventions do not match, then we'd better make sure the
3243 // results are returned in the same way as what the caller expects.
3245 SmallVector<CCValAssign, 16> RVLocs1;
3246 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3247 DAG.getTarget(), RVLocs1, *DAG.getContext());
3248 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3250 SmallVector<CCValAssign, 16> RVLocs2;
3251 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3252 DAG.getTarget(), RVLocs2, *DAG.getContext());
3253 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3255 if (RVLocs1.size() != RVLocs2.size())
3257 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3258 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3260 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3262 if (RVLocs1[i].isRegLoc()) {
3263 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3266 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3272 // If the callee takes no arguments then go on to check the results of the
3274 if (!Outs.empty()) {
3275 // Check if stack adjustment is needed. For now, do not do this if any
3276 // argument is passed on the stack.
3277 SmallVector<CCValAssign, 16> ArgLocs;
3278 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3279 DAG.getTarget(), ArgLocs, *DAG.getContext());
3281 // Allocate shadow area for Win64
3283 CCInfo.AllocateStack(32, 8);
3285 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3286 if (CCInfo.getNextStackOffset()) {
3287 MachineFunction &MF = DAG.getMachineFunction();
3288 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3291 // Check if the arguments are already laid out in the right way as
3292 // the caller's fixed stack objects.
3293 MachineFrameInfo *MFI = MF.getFrameInfo();
3294 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3295 const X86InstrInfo *TII =
3296 static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
3297 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3298 CCValAssign &VA = ArgLocs[i];
3299 SDValue Arg = OutVals[i];
3300 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3301 if (VA.getLocInfo() == CCValAssign::Indirect)
3303 if (!VA.isRegLoc()) {
3304 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3311 // If the tailcall address may be in a register, then make sure it's
3312 // possible to register allocate for it. In 32-bit, the call address can
3313 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3314 // callee-saved registers are restored. These happen to be the same
3315 // registers used to pass 'inreg' arguments so watch out for those.
3316 if (!Subtarget->is64Bit() &&
3317 ((!isa<GlobalAddressSDNode>(Callee) &&
3318 !isa<ExternalSymbolSDNode>(Callee)) ||
3319 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3320 unsigned NumInRegs = 0;
3321 // In PIC we need an extra register to formulate the address computation
3323 unsigned MaxInRegs =
3324 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3326 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3327 CCValAssign &VA = ArgLocs[i];
3330 unsigned Reg = VA.getLocReg();
3333 case X86::EAX: case X86::EDX: case X86::ECX:
3334 if (++NumInRegs == MaxInRegs)
3346 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3347 const TargetLibraryInfo *libInfo) const {
3348 return X86::createFastISel(funcInfo, libInfo);
3351 //===----------------------------------------------------------------------===//
3352 // Other Lowering Hooks
3353 //===----------------------------------------------------------------------===//
3355 static bool MayFoldLoad(SDValue Op) {
3356 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3359 static bool MayFoldIntoStore(SDValue Op) {
3360 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3363 static bool isTargetShuffle(unsigned Opcode) {
3365 default: return false;
3366 case X86ISD::PSHUFD:
3367 case X86ISD::PSHUFHW:
3368 case X86ISD::PSHUFLW:
3370 case X86ISD::PALIGNR:
3371 case X86ISD::MOVLHPS:
3372 case X86ISD::MOVLHPD:
3373 case X86ISD::MOVHLPS:
3374 case X86ISD::MOVLPS:
3375 case X86ISD::MOVLPD:
3376 case X86ISD::MOVSHDUP:
3377 case X86ISD::MOVSLDUP:
3378 case X86ISD::MOVDDUP:
3381 case X86ISD::UNPCKL:
3382 case X86ISD::UNPCKH:
3383 case X86ISD::VPERMILP:
3384 case X86ISD::VPERM2X128:
3385 case X86ISD::VPERMI:
3390 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3391 SDValue V1, SelectionDAG &DAG) {
3393 default: llvm_unreachable("Unknown x86 shuffle node");
3394 case X86ISD::MOVSHDUP:
3395 case X86ISD::MOVSLDUP:
3396 case X86ISD::MOVDDUP:
3397 return DAG.getNode(Opc, dl, VT, V1);
3401 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3402 SDValue V1, unsigned TargetMask,
3403 SelectionDAG &DAG) {
3405 default: llvm_unreachable("Unknown x86 shuffle node");
3406 case X86ISD::PSHUFD:
3407 case X86ISD::PSHUFHW:
3408 case X86ISD::PSHUFLW:
3409 case X86ISD::VPERMILP:
3410 case X86ISD::VPERMI:
3411 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3415 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3416 SDValue V1, SDValue V2, unsigned TargetMask,
3417 SelectionDAG &DAG) {
3419 default: llvm_unreachable("Unknown x86 shuffle node");
3420 case X86ISD::PALIGNR:
3422 case X86ISD::VPERM2X128:
3423 return DAG.getNode(Opc, dl, VT, V1, V2,
3424 DAG.getConstant(TargetMask, MVT::i8));
3428 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3429 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3431 default: llvm_unreachable("Unknown x86 shuffle node");
3432 case X86ISD::MOVLHPS:
3433 case X86ISD::MOVLHPD:
3434 case X86ISD::MOVHLPS:
3435 case X86ISD::MOVLPS:
3436 case X86ISD::MOVLPD:
3439 case X86ISD::UNPCKL:
3440 case X86ISD::UNPCKH:
3441 return DAG.getNode(Opc, dl, VT, V1, V2);
3445 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3446 MachineFunction &MF = DAG.getMachineFunction();
3447 const X86RegisterInfo *RegInfo =
3448 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3449 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3450 int ReturnAddrIndex = FuncInfo->getRAIndex();
3452 if (ReturnAddrIndex == 0) {
3453 // Set up a frame object for the return address.
3454 unsigned SlotSize = RegInfo->getSlotSize();
3455 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3458 FuncInfo->setRAIndex(ReturnAddrIndex);
3461 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3464 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3465 bool hasSymbolicDisplacement) {
3466 // Offset should fit into 32 bit immediate field.
3467 if (!isInt<32>(Offset))
3470 // If we don't have a symbolic displacement - we don't have any extra
3472 if (!hasSymbolicDisplacement)
3475 // FIXME: Some tweaks might be needed for medium code model.
3476 if (M != CodeModel::Small && M != CodeModel::Kernel)
3479 // For small code model we assume that latest object is 16MB before end of 31
3480 // bits boundary. We may also accept pretty large negative constants knowing
3481 // that all objects are in the positive half of address space.
3482 if (M == CodeModel::Small && Offset < 16*1024*1024)
3485 // For kernel code model we know that all object resist in the negative half
3486 // of 32bits address space. We may not accept negative offsets, since they may
3487 // be just off and we may accept pretty large positive ones.
3488 if (M == CodeModel::Kernel && Offset > 0)
3494 /// isCalleePop - Determines whether the callee is required to pop its
3495 /// own arguments. Callee pop is necessary to support tail calls.
3496 bool X86::isCalleePop(CallingConv::ID CallingConv,
3497 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3501 switch (CallingConv) {
3504 case CallingConv::X86_StdCall:
3506 case CallingConv::X86_FastCall:
3508 case CallingConv::X86_ThisCall:
3510 case CallingConv::Fast:
3512 case CallingConv::GHC:
3514 case CallingConv::HiPE:
3519 /// \brief Return true if the condition is an unsigned comparison operation.
3520 static bool isX86CCUnsigned(unsigned X86CC) {
3522 default: llvm_unreachable("Invalid integer condition!");
3523 case X86::COND_E: return true;
3524 case X86::COND_G: return false;
3525 case X86::COND_GE: return false;
3526 case X86::COND_L: return false;
3527 case X86::COND_LE: return false;
3528 case X86::COND_NE: return true;
3529 case X86::COND_B: return true;
3530 case X86::COND_A: return true;
3531 case X86::COND_BE: return true;
3532 case X86::COND_AE: return true;
3534 llvm_unreachable("covered switch fell through?!");
3537 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3538 /// specific condition code, returning the condition code and the LHS/RHS of the
3539 /// comparison to make.
3540 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3541 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3543 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3544 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3545 // X > -1 -> X == 0, jump !sign.
3546 RHS = DAG.getConstant(0, RHS.getValueType());
3547 return X86::COND_NS;
3549 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3550 // X < 0 -> X == 0, jump on sign.
3553 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3555 RHS = DAG.getConstant(0, RHS.getValueType());
3556 return X86::COND_LE;
3560 switch (SetCCOpcode) {
3561 default: llvm_unreachable("Invalid integer condition!");
3562 case ISD::SETEQ: return X86::COND_E;
3563 case ISD::SETGT: return X86::COND_G;
3564 case ISD::SETGE: return X86::COND_GE;
3565 case ISD::SETLT: return X86::COND_L;
3566 case ISD::SETLE: return X86::COND_LE;
3567 case ISD::SETNE: return X86::COND_NE;
3568 case ISD::SETULT: return X86::COND_B;
3569 case ISD::SETUGT: return X86::COND_A;
3570 case ISD::SETULE: return X86::COND_BE;
3571 case ISD::SETUGE: return X86::COND_AE;
3575 // First determine if it is required or is profitable to flip the operands.
3577 // If LHS is a foldable load, but RHS is not, flip the condition.
3578 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3579 !ISD::isNON_EXTLoad(RHS.getNode())) {
3580 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3581 std::swap(LHS, RHS);
3584 switch (SetCCOpcode) {
3590 std::swap(LHS, RHS);
3594 // On a floating point condition, the flags are set as follows:
3596 // 0 | 0 | 0 | X > Y
3597 // 0 | 0 | 1 | X < Y
3598 // 1 | 0 | 0 | X == Y
3599 // 1 | 1 | 1 | unordered
3600 switch (SetCCOpcode) {
3601 default: llvm_unreachable("Condcode should be pre-legalized away");
3603 case ISD::SETEQ: return X86::COND_E;
3604 case ISD::SETOLT: // flipped
3606 case ISD::SETGT: return X86::COND_A;
3607 case ISD::SETOLE: // flipped
3609 case ISD::SETGE: return X86::COND_AE;
3610 case ISD::SETUGT: // flipped
3612 case ISD::SETLT: return X86::COND_B;
3613 case ISD::SETUGE: // flipped
3615 case ISD::SETLE: return X86::COND_BE;
3617 case ISD::SETNE: return X86::COND_NE;
3618 case ISD::SETUO: return X86::COND_P;
3619 case ISD::SETO: return X86::COND_NP;
3621 case ISD::SETUNE: return X86::COND_INVALID;
3625 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3626 /// code. Current x86 isa includes the following FP cmov instructions:
3627 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3628 static bool hasFPCMov(unsigned X86CC) {
3644 /// isFPImmLegal - Returns true if the target can instruction select the
3645 /// specified FP immediate natively. If false, the legalizer will
3646 /// materialize the FP immediate as a load from a constant pool.
3647 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3648 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3649 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3655 /// \brief Returns true if it is beneficial to convert a load of a constant
3656 /// to just the constant itself.
3657 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3659 assert(Ty->isIntegerTy());
3661 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3662 if (BitSize == 0 || BitSize > 64)
3667 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3668 /// the specified range (L, H].
3669 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3670 return (Val < 0) || (Val >= Low && Val < Hi);
3673 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3674 /// specified value.
3675 static bool isUndefOrEqual(int Val, int CmpVal) {
3676 return (Val < 0 || Val == CmpVal);
3679 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3680 /// from position Pos and ending in Pos+Size, falls within the specified
3681 /// sequential range (L, L+Pos]. or is undef.
3682 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3683 unsigned Pos, unsigned Size, int Low) {
3684 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3685 if (!isUndefOrEqual(Mask[i], Low))
3690 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3691 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3692 /// the second operand.
3693 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3694 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3695 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3696 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3697 return (Mask[0] < 2 && Mask[1] < 2);
3701 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3702 /// is suitable for input to PSHUFHW.
3703 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3704 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3707 // Lower quadword copied in order or undef.
3708 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3711 // Upper quadword shuffled.
3712 for (unsigned i = 4; i != 8; ++i)
3713 if (!isUndefOrInRange(Mask[i], 4, 8))
3716 if (VT == MVT::v16i16) {
3717 // Lower quadword copied in order or undef.
3718 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3721 // Upper quadword shuffled.
3722 for (unsigned i = 12; i != 16; ++i)
3723 if (!isUndefOrInRange(Mask[i], 12, 16))
3730 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3731 /// is suitable for input to PSHUFLW.
3732 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3733 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3736 // Upper quadword copied in order.
3737 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3740 // Lower quadword shuffled.
3741 for (unsigned i = 0; i != 4; ++i)
3742 if (!isUndefOrInRange(Mask[i], 0, 4))
3745 if (VT == MVT::v16i16) {
3746 // Upper quadword copied in order.
3747 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3750 // Lower quadword shuffled.
3751 for (unsigned i = 8; i != 12; ++i)
3752 if (!isUndefOrInRange(Mask[i], 8, 12))
3759 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3760 /// is suitable for input to PALIGNR.
3761 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3762 const X86Subtarget *Subtarget) {
3763 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3764 (VT.is256BitVector() && !Subtarget->hasInt256()))
3767 unsigned NumElts = VT.getVectorNumElements();
3768 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3769 unsigned NumLaneElts = NumElts/NumLanes;
3771 // Do not handle 64-bit element shuffles with palignr.
3772 if (NumLaneElts == 2)
3775 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3777 for (i = 0; i != NumLaneElts; ++i) {
3782 // Lane is all undef, go to next lane
3783 if (i == NumLaneElts)
3786 int Start = Mask[i+l];
3788 // Make sure its in this lane in one of the sources
3789 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3790 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3793 // If not lane 0, then we must match lane 0
3794 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3797 // Correct second source to be contiguous with first source
3798 if (Start >= (int)NumElts)
3799 Start -= NumElts - NumLaneElts;
3801 // Make sure we're shifting in the right direction.
3802 if (Start <= (int)(i+l))
3807 // Check the rest of the elements to see if they are consecutive.
3808 for (++i; i != NumLaneElts; ++i) {
3809 int Idx = Mask[i+l];
3811 // Make sure its in this lane
3812 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3813 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3816 // If not lane 0, then we must match lane 0
3817 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3820 if (Idx >= (int)NumElts)
3821 Idx -= NumElts - NumLaneElts;
3823 if (!isUndefOrEqual(Idx, Start+i))
3832 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3833 /// the two vector operands have swapped position.
3834 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3835 unsigned NumElems) {
3836 for (unsigned i = 0; i != NumElems; ++i) {
3840 else if (idx < (int)NumElems)
3841 Mask[i] = idx + NumElems;
3843 Mask[i] = idx - NumElems;
3847 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3848 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3849 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3850 /// reverse of what x86 shuffles want.
3851 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3853 unsigned NumElems = VT.getVectorNumElements();
3854 unsigned NumLanes = VT.getSizeInBits()/128;
3855 unsigned NumLaneElems = NumElems/NumLanes;
3857 if (NumLaneElems != 2 && NumLaneElems != 4)
3860 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3861 bool symetricMaskRequired =
3862 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3864 // VSHUFPSY divides the resulting vector into 4 chunks.
3865 // The sources are also splitted into 4 chunks, and each destination
3866 // chunk must come from a different source chunk.
3868 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3869 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3871 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3872 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3874 // VSHUFPDY divides the resulting vector into 4 chunks.
3875 // The sources are also splitted into 4 chunks, and each destination
3876 // chunk must come from a different source chunk.
3878 // SRC1 => X3 X2 X1 X0
3879 // SRC2 => Y3 Y2 Y1 Y0
3881 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3883 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3884 unsigned HalfLaneElems = NumLaneElems/2;
3885 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3886 for (unsigned i = 0; i != NumLaneElems; ++i) {
3887 int Idx = Mask[i+l];
3888 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3889 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3891 // For VSHUFPSY, the mask of the second half must be the same as the
3892 // first but with the appropriate offsets. This works in the same way as
3893 // VPERMILPS works with masks.
3894 if (!symetricMaskRequired || Idx < 0)
3896 if (MaskVal[i] < 0) {
3897 MaskVal[i] = Idx - l;
3900 if ((signed)(Idx - l) != MaskVal[i])
3908 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3910 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3911 if (!VT.is128BitVector())
3914 unsigned NumElems = VT.getVectorNumElements();
3919 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3920 return isUndefOrEqual(Mask[0], 6) &&
3921 isUndefOrEqual(Mask[1], 7) &&
3922 isUndefOrEqual(Mask[2], 2) &&
3923 isUndefOrEqual(Mask[3], 3);
3926 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3927 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3929 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3930 if (!VT.is128BitVector())
3933 unsigned NumElems = VT.getVectorNumElements();
3938 return isUndefOrEqual(Mask[0], 2) &&
3939 isUndefOrEqual(Mask[1], 3) &&
3940 isUndefOrEqual(Mask[2], 2) &&
3941 isUndefOrEqual(Mask[3], 3);
3944 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3945 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3946 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3947 if (!VT.is128BitVector())
3950 unsigned NumElems = VT.getVectorNumElements();
3952 if (NumElems != 2 && NumElems != 4)
3955 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3956 if (!isUndefOrEqual(Mask[i], i + NumElems))
3959 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3960 if (!isUndefOrEqual(Mask[i], i))
3966 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3967 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3968 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3969 if (!VT.is128BitVector())
3972 unsigned NumElems = VT.getVectorNumElements();
3974 if (NumElems != 2 && NumElems != 4)
3977 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3978 if (!isUndefOrEqual(Mask[i], i))
3981 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3982 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3988 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
3989 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
3990 /// i. e: If all but one element come from the same vector.
3991 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
3992 // TODO: Deal with AVX's VINSERTPS
3993 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
3996 unsigned CorrectPosV1 = 0;
3997 unsigned CorrectPosV2 = 0;
3998 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
3999 if (Mask[i] == -1) {
4007 else if (Mask[i] == i + 4)
4011 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4012 // We have 3 elements (undefs count as elements from any vector) from one
4013 // vector, and one from another.
4020 // Some special combinations that can be optimized.
4023 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4024 SelectionDAG &DAG) {
4025 MVT VT = SVOp->getSimpleValueType(0);
4028 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4031 ArrayRef<int> Mask = SVOp->getMask();
4033 // These are the special masks that may be optimized.
4034 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4035 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4036 bool MatchEvenMask = true;
4037 bool MatchOddMask = true;
4038 for (int i=0; i<8; ++i) {
4039 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4040 MatchEvenMask = false;
4041 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4042 MatchOddMask = false;
4045 if (!MatchEvenMask && !MatchOddMask)
4048 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4050 SDValue Op0 = SVOp->getOperand(0);
4051 SDValue Op1 = SVOp->getOperand(1);
4053 if (MatchEvenMask) {
4054 // Shift the second operand right to 32 bits.
4055 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4056 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4058 // Shift the first operand left to 32 bits.
4059 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4060 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4062 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4063 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4066 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4067 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4068 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4069 bool HasInt256, bool V2IsSplat = false) {
4071 assert(VT.getSizeInBits() >= 128 &&
4072 "Unsupported vector type for unpckl");
4074 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4076 unsigned NumOf256BitLanes;
4077 unsigned NumElts = VT.getVectorNumElements();
4078 if (VT.is256BitVector()) {
4079 if (NumElts != 4 && NumElts != 8 &&
4080 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4083 NumOf256BitLanes = 1;
4084 } else if (VT.is512BitVector()) {
4085 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4086 "Unsupported vector type for unpckh");
4088 NumOf256BitLanes = 2;
4091 NumOf256BitLanes = 1;
4094 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4095 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4097 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4098 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4099 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4100 int BitI = Mask[l256*NumEltsInStride+l+i];
4101 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4102 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4104 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4106 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4114 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4115 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4116 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4117 bool HasInt256, bool V2IsSplat = false) {
4118 assert(VT.getSizeInBits() >= 128 &&
4119 "Unsupported vector type for unpckh");
4121 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4123 unsigned NumOf256BitLanes;
4124 unsigned NumElts = VT.getVectorNumElements();
4125 if (VT.is256BitVector()) {
4126 if (NumElts != 4 && NumElts != 8 &&
4127 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4130 NumOf256BitLanes = 1;
4131 } else if (VT.is512BitVector()) {
4132 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4133 "Unsupported vector type for unpckh");
4135 NumOf256BitLanes = 2;
4138 NumOf256BitLanes = 1;
4141 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4142 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4144 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4145 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4146 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4147 int BitI = Mask[l256*NumEltsInStride+l+i];
4148 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4149 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4151 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4153 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4161 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4162 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4164 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4165 unsigned NumElts = VT.getVectorNumElements();
4166 bool Is256BitVec = VT.is256BitVector();
4168 if (VT.is512BitVector())
4170 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4171 "Unsupported vector type for unpckh");
4173 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4174 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4177 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4178 // FIXME: Need a better way to get rid of this, there's no latency difference
4179 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4180 // the former later. We should also remove the "_undef" special mask.
4181 if (NumElts == 4 && Is256BitVec)
4184 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4185 // independently on 128-bit lanes.
4186 unsigned NumLanes = VT.getSizeInBits()/128;
4187 unsigned NumLaneElts = NumElts/NumLanes;
4189 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4190 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4191 int BitI = Mask[l+i];
4192 int BitI1 = Mask[l+i+1];
4194 if (!isUndefOrEqual(BitI, j))
4196 if (!isUndefOrEqual(BitI1, j))
4204 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4205 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4207 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4208 unsigned NumElts = VT.getVectorNumElements();
4210 if (VT.is512BitVector())
4213 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4214 "Unsupported vector type for unpckh");
4216 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4217 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4220 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4221 // independently on 128-bit lanes.
4222 unsigned NumLanes = VT.getSizeInBits()/128;
4223 unsigned NumLaneElts = NumElts/NumLanes;
4225 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4226 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4227 int BitI = Mask[l+i];
4228 int BitI1 = Mask[l+i+1];
4229 if (!isUndefOrEqual(BitI, j))
4231 if (!isUndefOrEqual(BitI1, j))
4238 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4239 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4240 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4241 if (!VT.is512BitVector())
4244 unsigned NumElts = VT.getVectorNumElements();
4245 unsigned HalfSize = NumElts/2;
4246 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4247 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4252 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4253 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4261 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4262 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4263 /// MOVSD, and MOVD, i.e. setting the lowest element.
4264 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4265 if (VT.getVectorElementType().getSizeInBits() < 32)
4267 if (!VT.is128BitVector())
4270 unsigned NumElts = VT.getVectorNumElements();
4272 if (!isUndefOrEqual(Mask[0], NumElts))
4275 for (unsigned i = 1; i != NumElts; ++i)
4276 if (!isUndefOrEqual(Mask[i], i))
4282 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4283 /// as permutations between 128-bit chunks or halves. As an example: this
4285 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4286 /// The first half comes from the second half of V1 and the second half from the
4287 /// the second half of V2.
4288 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4289 if (!HasFp256 || !VT.is256BitVector())
4292 // The shuffle result is divided into half A and half B. In total the two
4293 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4294 // B must come from C, D, E or F.
4295 unsigned HalfSize = VT.getVectorNumElements()/2;
4296 bool MatchA = false, MatchB = false;
4298 // Check if A comes from one of C, D, E, F.
4299 for (unsigned Half = 0; Half != 4; ++Half) {
4300 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4306 // Check if B comes from one of C, D, E, F.
4307 for (unsigned Half = 0; Half != 4; ++Half) {
4308 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4314 return MatchA && MatchB;
4317 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4318 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4319 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4320 MVT VT = SVOp->getSimpleValueType(0);
4322 unsigned HalfSize = VT.getVectorNumElements()/2;
4324 unsigned FstHalf = 0, SndHalf = 0;
4325 for (unsigned i = 0; i < HalfSize; ++i) {
4326 if (SVOp->getMaskElt(i) > 0) {
4327 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4331 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4332 if (SVOp->getMaskElt(i) > 0) {
4333 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4338 return (FstHalf | (SndHalf << 4));
4341 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4342 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4343 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4347 unsigned NumElts = VT.getVectorNumElements();
4349 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4350 for (unsigned i = 0; i != NumElts; ++i) {
4353 Imm8 |= Mask[i] << (i*2);
4358 unsigned LaneSize = 4;
4359 SmallVector<int, 4> MaskVal(LaneSize, -1);
4361 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4362 for (unsigned i = 0; i != LaneSize; ++i) {
4363 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4367 if (MaskVal[i] < 0) {
4368 MaskVal[i] = Mask[i+l] - l;
4369 Imm8 |= MaskVal[i] << (i*2);
4372 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4379 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4380 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4381 /// Note that VPERMIL mask matching is different depending whether theunderlying
4382 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4383 /// to the same elements of the low, but to the higher half of the source.
4384 /// In VPERMILPD the two lanes could be shuffled independently of each other
4385 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4386 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4387 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4388 if (VT.getSizeInBits() < 256 || EltSize < 32)
4390 bool symetricMaskRequired = (EltSize == 32);
4391 unsigned NumElts = VT.getVectorNumElements();
4393 unsigned NumLanes = VT.getSizeInBits()/128;
4394 unsigned LaneSize = NumElts/NumLanes;
4395 // 2 or 4 elements in one lane
4397 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4398 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4399 for (unsigned i = 0; i != LaneSize; ++i) {
4400 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4402 if (symetricMaskRequired) {
4403 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4404 ExpectedMaskVal[i] = Mask[i+l] - l;
4407 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4415 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4416 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4417 /// element of vector 2 and the other elements to come from vector 1 in order.
4418 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4419 bool V2IsSplat = false, bool V2IsUndef = false) {
4420 if (!VT.is128BitVector())
4423 unsigned NumOps = VT.getVectorNumElements();
4424 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4427 if (!isUndefOrEqual(Mask[0], 0))
4430 for (unsigned i = 1; i != NumOps; ++i)
4431 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4432 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4433 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4439 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4440 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4441 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4442 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4443 const X86Subtarget *Subtarget) {
4444 if (!Subtarget->hasSSE3())
4447 unsigned NumElems = VT.getVectorNumElements();
4449 if ((VT.is128BitVector() && NumElems != 4) ||
4450 (VT.is256BitVector() && NumElems != 8) ||
4451 (VT.is512BitVector() && NumElems != 16))
4454 // "i+1" is the value the indexed mask element must have
4455 for (unsigned i = 0; i != NumElems; i += 2)
4456 if (!isUndefOrEqual(Mask[i], i+1) ||
4457 !isUndefOrEqual(Mask[i+1], i+1))
4463 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4464 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4465 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4466 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4467 const X86Subtarget *Subtarget) {
4468 if (!Subtarget->hasSSE3())
4471 unsigned NumElems = VT.getVectorNumElements();
4473 if ((VT.is128BitVector() && NumElems != 4) ||
4474 (VT.is256BitVector() && NumElems != 8) ||
4475 (VT.is512BitVector() && NumElems != 16))
4478 // "i" is the value the indexed mask element must have
4479 for (unsigned i = 0; i != NumElems; i += 2)
4480 if (!isUndefOrEqual(Mask[i], i) ||
4481 !isUndefOrEqual(Mask[i+1], i))
4487 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4488 /// specifies a shuffle of elements that is suitable for input to 256-bit
4489 /// version of MOVDDUP.
4490 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4491 if (!HasFp256 || !VT.is256BitVector())
4494 unsigned NumElts = VT.getVectorNumElements();
4498 for (unsigned i = 0; i != NumElts/2; ++i)
4499 if (!isUndefOrEqual(Mask[i], 0))
4501 for (unsigned i = NumElts/2; i != NumElts; ++i)
4502 if (!isUndefOrEqual(Mask[i], NumElts/2))
4507 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4508 /// specifies a shuffle of elements that is suitable for input to 128-bit
4509 /// version of MOVDDUP.
4510 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4511 if (!VT.is128BitVector())
4514 unsigned e = VT.getVectorNumElements() / 2;
4515 for (unsigned i = 0; i != e; ++i)
4516 if (!isUndefOrEqual(Mask[i], i))
4518 for (unsigned i = 0; i != e; ++i)
4519 if (!isUndefOrEqual(Mask[e+i], i))
4524 /// isVEXTRACTIndex - Return true if the specified
4525 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4526 /// suitable for instruction that extract 128 or 256 bit vectors
4527 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4528 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4529 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4532 // The index should be aligned on a vecWidth-bit boundary.
4534 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4536 MVT VT = N->getSimpleValueType(0);
4537 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4538 bool Result = (Index * ElSize) % vecWidth == 0;
4543 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4544 /// operand specifies a subvector insert that is suitable for input to
4545 /// insertion of 128 or 256-bit subvectors
4546 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4547 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4548 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4550 // The index should be aligned on a vecWidth-bit boundary.
4552 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4554 MVT VT = N->getSimpleValueType(0);
4555 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4556 bool Result = (Index * ElSize) % vecWidth == 0;
4561 bool X86::isVINSERT128Index(SDNode *N) {
4562 return isVINSERTIndex(N, 128);
4565 bool X86::isVINSERT256Index(SDNode *N) {
4566 return isVINSERTIndex(N, 256);
4569 bool X86::isVEXTRACT128Index(SDNode *N) {
4570 return isVEXTRACTIndex(N, 128);
4573 bool X86::isVEXTRACT256Index(SDNode *N) {
4574 return isVEXTRACTIndex(N, 256);
4577 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4578 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4579 /// Handles 128-bit and 256-bit.
4580 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4581 MVT VT = N->getSimpleValueType(0);
4583 assert((VT.getSizeInBits() >= 128) &&
4584 "Unsupported vector type for PSHUF/SHUFP");
4586 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4587 // independently on 128-bit lanes.
4588 unsigned NumElts = VT.getVectorNumElements();
4589 unsigned NumLanes = VT.getSizeInBits()/128;
4590 unsigned NumLaneElts = NumElts/NumLanes;
4592 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4593 "Only supports 2, 4 or 8 elements per lane");
4595 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4597 for (unsigned i = 0; i != NumElts; ++i) {
4598 int Elt = N->getMaskElt(i);
4599 if (Elt < 0) continue;
4600 Elt &= NumLaneElts - 1;
4601 unsigned ShAmt = (i << Shift) % 8;
4602 Mask |= Elt << ShAmt;
4608 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4609 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4610 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4611 MVT VT = N->getSimpleValueType(0);
4613 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4614 "Unsupported vector type for PSHUFHW");
4616 unsigned NumElts = VT.getVectorNumElements();
4619 for (unsigned l = 0; l != NumElts; l += 8) {
4620 // 8 nodes per lane, but we only care about the last 4.
4621 for (unsigned i = 0; i < 4; ++i) {
4622 int Elt = N->getMaskElt(l+i+4);
4623 if (Elt < 0) continue;
4624 Elt &= 0x3; // only 2-bits.
4625 Mask |= Elt << (i * 2);
4632 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4633 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4634 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4635 MVT VT = N->getSimpleValueType(0);
4637 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4638 "Unsupported vector type for PSHUFHW");
4640 unsigned NumElts = VT.getVectorNumElements();
4643 for (unsigned l = 0; l != NumElts; l += 8) {
4644 // 8 nodes per lane, but we only care about the first 4.
4645 for (unsigned i = 0; i < 4; ++i) {
4646 int Elt = N->getMaskElt(l+i);
4647 if (Elt < 0) continue;
4648 Elt &= 0x3; // only 2-bits
4649 Mask |= Elt << (i * 2);
4656 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4657 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4658 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4659 MVT VT = SVOp->getSimpleValueType(0);
4660 unsigned EltSize = VT.is512BitVector() ? 1 :
4661 VT.getVectorElementType().getSizeInBits() >> 3;
4663 unsigned NumElts = VT.getVectorNumElements();
4664 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4665 unsigned NumLaneElts = NumElts/NumLanes;
4669 for (i = 0; i != NumElts; ++i) {
4670 Val = SVOp->getMaskElt(i);
4674 if (Val >= (int)NumElts)
4675 Val -= NumElts - NumLaneElts;
4677 assert(Val - i > 0 && "PALIGNR imm should be positive");
4678 return (Val - i) * EltSize;
4681 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4682 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4683 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4684 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4687 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4689 MVT VecVT = N->getOperand(0).getSimpleValueType();
4690 MVT ElVT = VecVT.getVectorElementType();
4692 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4693 return Index / NumElemsPerChunk;
4696 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4697 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4698 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4699 llvm_unreachable("Illegal insert subvector for VINSERT");
4702 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4704 MVT VecVT = N->getSimpleValueType(0);
4705 MVT ElVT = VecVT.getVectorElementType();
4707 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4708 return Index / NumElemsPerChunk;
4711 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4712 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4713 /// and VINSERTI128 instructions.
4714 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4715 return getExtractVEXTRACTImmediate(N, 128);
4718 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4719 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4720 /// and VINSERTI64x4 instructions.
4721 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4722 return getExtractVEXTRACTImmediate(N, 256);
4725 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4726 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4727 /// and VINSERTI128 instructions.
4728 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4729 return getInsertVINSERTImmediate(N, 128);
4732 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4733 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4734 /// and VINSERTI64x4 instructions.
4735 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4736 return getInsertVINSERTImmediate(N, 256);
4739 /// isZero - Returns true if Elt is a constant integer zero
4740 static bool isZero(SDValue V) {
4741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4742 return C && C->isNullValue();
4745 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4747 bool X86::isZeroNode(SDValue Elt) {
4750 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4751 return CFP->getValueAPF().isPosZero();
4755 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4756 /// their permute mask.
4757 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4758 SelectionDAG &DAG) {
4759 MVT VT = SVOp->getSimpleValueType(0);
4760 unsigned NumElems = VT.getVectorNumElements();
4761 SmallVector<int, 8> MaskVec;
4763 for (unsigned i = 0; i != NumElems; ++i) {
4764 int Idx = SVOp->getMaskElt(i);
4766 if (Idx < (int)NumElems)
4771 MaskVec.push_back(Idx);
4773 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4774 SVOp->getOperand(0), &MaskVec[0]);
4777 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4778 /// match movhlps. The lower half elements should come from upper half of
4779 /// V1 (and in order), and the upper half elements should come from the upper
4780 /// half of V2 (and in order).
4781 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4782 if (!VT.is128BitVector())
4784 if (VT.getVectorNumElements() != 4)
4786 for (unsigned i = 0, e = 2; i != e; ++i)
4787 if (!isUndefOrEqual(Mask[i], i+2))
4789 for (unsigned i = 2; i != 4; ++i)
4790 if (!isUndefOrEqual(Mask[i], i+4))
4795 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4796 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4798 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4799 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4801 N = N->getOperand(0).getNode();
4802 if (!ISD::isNON_EXTLoad(N))
4805 *LD = cast<LoadSDNode>(N);
4809 // Test whether the given value is a vector value which will be legalized
4811 static bool WillBeConstantPoolLoad(SDNode *N) {
4812 if (N->getOpcode() != ISD::BUILD_VECTOR)
4815 // Check for any non-constant elements.
4816 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4817 switch (N->getOperand(i).getNode()->getOpcode()) {
4819 case ISD::ConstantFP:
4826 // Vectors of all-zeros and all-ones are materialized with special
4827 // instructions rather than being loaded.
4828 return !ISD::isBuildVectorAllZeros(N) &&
4829 !ISD::isBuildVectorAllOnes(N);
4832 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4833 /// match movlp{s|d}. The lower half elements should come from lower half of
4834 /// V1 (and in order), and the upper half elements should come from the upper
4835 /// half of V2 (and in order). And since V1 will become the source of the
4836 /// MOVLP, it must be either a vector load or a scalar load to vector.
4837 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4838 ArrayRef<int> Mask, MVT VT) {
4839 if (!VT.is128BitVector())
4842 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4844 // Is V2 is a vector load, don't do this transformation. We will try to use
4845 // load folding shufps op.
4846 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4849 unsigned NumElems = VT.getVectorNumElements();
4851 if (NumElems != 2 && NumElems != 4)
4853 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4854 if (!isUndefOrEqual(Mask[i], i))
4856 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4857 if (!isUndefOrEqual(Mask[i], i+NumElems))
4862 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4863 /// to an zero vector.
4864 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4865 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4866 SDValue V1 = N->getOperand(0);
4867 SDValue V2 = N->getOperand(1);
4868 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4869 for (unsigned i = 0; i != NumElems; ++i) {
4870 int Idx = N->getMaskElt(i);
4871 if (Idx >= (int)NumElems) {
4872 unsigned Opc = V2.getOpcode();
4873 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4875 if (Opc != ISD::BUILD_VECTOR ||
4876 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4878 } else if (Idx >= 0) {
4879 unsigned Opc = V1.getOpcode();
4880 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4882 if (Opc != ISD::BUILD_VECTOR ||
4883 !X86::isZeroNode(V1.getOperand(Idx)))
4890 /// getZeroVector - Returns a vector of specified type with all zero elements.
4892 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4893 SelectionDAG &DAG, SDLoc dl) {
4894 assert(VT.isVector() && "Expected a vector type");
4896 // Always build SSE zero vectors as <4 x i32> bitcasted
4897 // to their dest type. This ensures they get CSE'd.
4899 if (VT.is128BitVector()) { // SSE
4900 if (Subtarget->hasSSE2()) { // SSE2
4901 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4902 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4904 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4905 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4907 } else if (VT.is256BitVector()) { // AVX
4908 if (Subtarget->hasInt256()) { // AVX2
4909 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4910 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4911 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4913 // 256-bit logic and arithmetic instructions in AVX are all
4914 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4915 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4916 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4917 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4919 } else if (VT.is512BitVector()) { // AVX-512
4920 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4921 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4922 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4923 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4924 } else if (VT.getScalarType() == MVT::i1) {
4925 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4926 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4927 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4928 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4930 llvm_unreachable("Unexpected vector type");
4932 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4935 /// getOnesVector - Returns a vector of specified type with all bits set.
4936 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4937 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4938 /// Then bitcast to their original type, ensuring they get CSE'd.
4939 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4941 assert(VT.isVector() && "Expected a vector type");
4943 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4945 if (VT.is256BitVector()) {
4946 if (HasInt256) { // AVX2
4947 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4948 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4950 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4951 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4953 } else if (VT.is128BitVector()) {
4954 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4956 llvm_unreachable("Unexpected vector type");
4958 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4961 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4962 /// that point to V2 points to its first element.
4963 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4964 for (unsigned i = 0; i != NumElems; ++i) {
4965 if (Mask[i] > (int)NumElems) {
4971 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4972 /// operation of specified width.
4973 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4975 unsigned NumElems = VT.getVectorNumElements();
4976 SmallVector<int, 8> Mask;
4977 Mask.push_back(NumElems);
4978 for (unsigned i = 1; i != NumElems; ++i)
4980 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4983 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4984 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4986 unsigned NumElems = VT.getVectorNumElements();
4987 SmallVector<int, 8> Mask;
4988 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4990 Mask.push_back(i + NumElems);
4992 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4995 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4996 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4998 unsigned NumElems = VT.getVectorNumElements();
4999 SmallVector<int, 8> Mask;
5000 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5001 Mask.push_back(i + Half);
5002 Mask.push_back(i + NumElems + Half);
5004 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5007 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5008 // a generic shuffle instruction because the target has no such instructions.
5009 // Generate shuffles which repeat i16 and i8 several times until they can be
5010 // represented by v4f32 and then be manipulated by target suported shuffles.
5011 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5012 MVT VT = V.getSimpleValueType();
5013 int NumElems = VT.getVectorNumElements();
5016 while (NumElems > 4) {
5017 if (EltNo < NumElems/2) {
5018 V = getUnpackl(DAG, dl, VT, V, V);
5020 V = getUnpackh(DAG, dl, VT, V, V);
5021 EltNo -= NumElems/2;
5028 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5029 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5030 MVT VT = V.getSimpleValueType();
5033 if (VT.is128BitVector()) {
5034 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5035 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5036 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5038 } else if (VT.is256BitVector()) {
5039 // To use VPERMILPS to splat scalars, the second half of indicies must
5040 // refer to the higher part, which is a duplication of the lower one,
5041 // because VPERMILPS can only handle in-lane permutations.
5042 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5043 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5045 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5046 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5049 llvm_unreachable("Vector size not supported");
5051 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5054 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5055 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5056 MVT SrcVT = SV->getSimpleValueType(0);
5057 SDValue V1 = SV->getOperand(0);
5060 int EltNo = SV->getSplatIndex();
5061 int NumElems = SrcVT.getVectorNumElements();
5062 bool Is256BitVec = SrcVT.is256BitVector();
5064 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5065 "Unknown how to promote splat for type");
5067 // Extract the 128-bit part containing the splat element and update
5068 // the splat element index when it refers to the higher register.
5070 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5071 if (EltNo >= NumElems/2)
5072 EltNo -= NumElems/2;
5075 // All i16 and i8 vector types can't be used directly by a generic shuffle
5076 // instruction because the target has no such instruction. Generate shuffles
5077 // which repeat i16 and i8 several times until they fit in i32, and then can
5078 // be manipulated by target suported shuffles.
5079 MVT EltVT = SrcVT.getVectorElementType();
5080 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5081 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5083 // Recreate the 256-bit vector and place the same 128-bit vector
5084 // into the low and high part. This is necessary because we want
5085 // to use VPERM* to shuffle the vectors
5087 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5090 return getLegalSplat(DAG, V1, EltNo);
5093 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5094 /// vector of zero or undef vector. This produces a shuffle where the low
5095 /// element of V2 is swizzled into the zero/undef vector, landing at element
5096 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5097 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5099 const X86Subtarget *Subtarget,
5100 SelectionDAG &DAG) {
5101 MVT VT = V2.getSimpleValueType();
5103 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5104 unsigned NumElems = VT.getVectorNumElements();
5105 SmallVector<int, 16> MaskVec;
5106 for (unsigned i = 0; i != NumElems; ++i)
5107 // If this is the insertion idx, put the low elt of V2 here.
5108 MaskVec.push_back(i == Idx ? NumElems : i);
5109 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5112 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5113 /// target specific opcode. Returns true if the Mask could be calculated.
5114 /// Sets IsUnary to true if only uses one source.
5115 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5116 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5117 unsigned NumElems = VT.getVectorNumElements();
5121 switch(N->getOpcode()) {
5123 ImmN = N->getOperand(N->getNumOperands()-1);
5124 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5126 case X86ISD::UNPCKH:
5127 DecodeUNPCKHMask(VT, Mask);
5129 case X86ISD::UNPCKL:
5130 DecodeUNPCKLMask(VT, Mask);
5132 case X86ISD::MOVHLPS:
5133 DecodeMOVHLPSMask(NumElems, Mask);
5135 case X86ISD::MOVLHPS:
5136 DecodeMOVLHPSMask(NumElems, Mask);
5138 case X86ISD::PALIGNR:
5139 ImmN = N->getOperand(N->getNumOperands()-1);
5140 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5142 case X86ISD::PSHUFD:
5143 case X86ISD::VPERMILP:
5144 ImmN = N->getOperand(N->getNumOperands()-1);
5145 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5148 case X86ISD::PSHUFHW:
5149 ImmN = N->getOperand(N->getNumOperands()-1);
5150 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5153 case X86ISD::PSHUFLW:
5154 ImmN = N->getOperand(N->getNumOperands()-1);
5155 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5158 case X86ISD::VPERMI:
5159 ImmN = N->getOperand(N->getNumOperands()-1);
5160 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5164 case X86ISD::MOVSD: {
5165 // The index 0 always comes from the first element of the second source,
5166 // this is why MOVSS and MOVSD are used in the first place. The other
5167 // elements come from the other positions of the first source vector
5168 Mask.push_back(NumElems);
5169 for (unsigned i = 1; i != NumElems; ++i) {
5174 case X86ISD::VPERM2X128:
5175 ImmN = N->getOperand(N->getNumOperands()-1);
5176 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5177 if (Mask.empty()) return false;
5179 case X86ISD::MOVDDUP:
5180 case X86ISD::MOVLHPD:
5181 case X86ISD::MOVLPD:
5182 case X86ISD::MOVLPS:
5183 case X86ISD::MOVSHDUP:
5184 case X86ISD::MOVSLDUP:
5185 // Not yet implemented
5187 default: llvm_unreachable("unknown target shuffle node");
5193 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5194 /// element of the result of the vector shuffle.
5195 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5198 return SDValue(); // Limit search depth.
5200 SDValue V = SDValue(N, 0);
5201 EVT VT = V.getValueType();
5202 unsigned Opcode = V.getOpcode();
5204 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5205 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5206 int Elt = SV->getMaskElt(Index);
5209 return DAG.getUNDEF(VT.getVectorElementType());
5211 unsigned NumElems = VT.getVectorNumElements();
5212 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5213 : SV->getOperand(1);
5214 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5217 // Recurse into target specific vector shuffles to find scalars.
5218 if (isTargetShuffle(Opcode)) {
5219 MVT ShufVT = V.getSimpleValueType();
5220 unsigned NumElems = ShufVT.getVectorNumElements();
5221 SmallVector<int, 16> ShuffleMask;
5224 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5227 int Elt = ShuffleMask[Index];
5229 return DAG.getUNDEF(ShufVT.getVectorElementType());
5231 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5233 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5237 // Actual nodes that may contain scalar elements
5238 if (Opcode == ISD::BITCAST) {
5239 V = V.getOperand(0);
5240 EVT SrcVT = V.getValueType();
5241 unsigned NumElems = VT.getVectorNumElements();
5243 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5247 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5248 return (Index == 0) ? V.getOperand(0)
5249 : DAG.getUNDEF(VT.getVectorElementType());
5251 if (V.getOpcode() == ISD::BUILD_VECTOR)
5252 return V.getOperand(Index);
5257 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5258 /// shuffle operation which come from a consecutively from a zero. The
5259 /// search can start in two different directions, from left or right.
5260 /// We count undefs as zeros until PreferredNum is reached.
5261 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5262 unsigned NumElems, bool ZerosFromLeft,
5264 unsigned PreferredNum = -1U) {
5265 unsigned NumZeros = 0;
5266 for (unsigned i = 0; i != NumElems; ++i) {
5267 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5268 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5272 if (X86::isZeroNode(Elt))
5274 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5275 NumZeros = std::min(NumZeros + 1, PreferredNum);
5283 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5284 /// correspond consecutively to elements from one of the vector operands,
5285 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5287 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5288 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5289 unsigned NumElems, unsigned &OpNum) {
5290 bool SeenV1 = false;
5291 bool SeenV2 = false;
5293 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5294 int Idx = SVOp->getMaskElt(i);
5295 // Ignore undef indicies
5299 if (Idx < (int)NumElems)
5304 // Only accept consecutive elements from the same vector
5305 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5309 OpNum = SeenV1 ? 0 : 1;
5313 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5314 /// logical left shift of a vector.
5315 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5316 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5318 SVOp->getSimpleValueType(0).getVectorNumElements();
5319 unsigned NumZeros = getNumOfConsecutiveZeros(
5320 SVOp, NumElems, false /* check zeros from right */, DAG,
5321 SVOp->getMaskElt(0));
5327 // Considering the elements in the mask that are not consecutive zeros,
5328 // check if they consecutively come from only one of the source vectors.
5330 // V1 = {X, A, B, C} 0
5332 // vector_shuffle V1, V2 <1, 2, 3, X>
5334 if (!isShuffleMaskConsecutive(SVOp,
5335 0, // Mask Start Index
5336 NumElems-NumZeros, // Mask End Index(exclusive)
5337 NumZeros, // Where to start looking in the src vector
5338 NumElems, // Number of elements in vector
5339 OpSrc)) // Which source operand ?
5344 ShVal = SVOp->getOperand(OpSrc);
5348 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5349 /// logical left shift of a vector.
5350 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5351 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5353 SVOp->getSimpleValueType(0).getVectorNumElements();
5354 unsigned NumZeros = getNumOfConsecutiveZeros(
5355 SVOp, NumElems, true /* check zeros from left */, DAG,
5356 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5362 // Considering the elements in the mask that are not consecutive zeros,
5363 // check if they consecutively come from only one of the source vectors.
5365 // 0 { A, B, X, X } = V2
5367 // vector_shuffle V1, V2 <X, X, 4, 5>
5369 if (!isShuffleMaskConsecutive(SVOp,
5370 NumZeros, // Mask Start Index
5371 NumElems, // Mask End Index(exclusive)
5372 0, // Where to start looking in the src vector
5373 NumElems, // Number of elements in vector
5374 OpSrc)) // Which source operand ?
5379 ShVal = SVOp->getOperand(OpSrc);
5383 /// isVectorShift - Returns true if the shuffle can be implemented as a
5384 /// logical left or right shift of a vector.
5385 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5386 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5387 // Although the logic below support any bitwidth size, there are no
5388 // shift instructions which handle more than 128-bit vectors.
5389 if (!SVOp->getSimpleValueType(0).is128BitVector())
5392 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5393 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5399 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5401 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5402 unsigned NumNonZero, unsigned NumZero,
5404 const X86Subtarget* Subtarget,
5405 const TargetLowering &TLI) {
5412 for (unsigned i = 0; i < 16; ++i) {
5413 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5414 if (ThisIsNonZero && First) {
5416 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5418 V = DAG.getUNDEF(MVT::v8i16);
5423 SDValue ThisElt, LastElt;
5424 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5425 if (LastIsNonZero) {
5426 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5427 MVT::i16, Op.getOperand(i-1));
5429 if (ThisIsNonZero) {
5430 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5431 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5432 ThisElt, DAG.getConstant(8, MVT::i8));
5434 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5438 if (ThisElt.getNode())
5439 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5440 DAG.getIntPtrConstant(i/2));
5444 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5447 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5449 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5450 unsigned NumNonZero, unsigned NumZero,
5452 const X86Subtarget* Subtarget,
5453 const TargetLowering &TLI) {
5460 for (unsigned i = 0; i < 8; ++i) {
5461 bool isNonZero = (NonZeros & (1 << i)) != 0;
5465 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5467 V = DAG.getUNDEF(MVT::v8i16);
5470 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5471 MVT::v8i16, V, Op.getOperand(i),
5472 DAG.getIntPtrConstant(i));
5479 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5480 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5481 unsigned NonZeros, unsigned NumNonZero,
5482 unsigned NumZero, SelectionDAG &DAG,
5483 const X86Subtarget *Subtarget,
5484 const TargetLowering &TLI) {
5485 // We know there's at least one non-zero element
5486 unsigned FirstNonZeroIdx = 0;
5487 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5488 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5489 X86::isZeroNode(FirstNonZero)) {
5491 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5494 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5495 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5498 SDValue V = FirstNonZero.getOperand(0);
5499 MVT VVT = V.getSimpleValueType();
5500 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5503 unsigned FirstNonZeroDst =
5504 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5505 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5506 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5507 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5509 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5510 SDValue Elem = Op.getOperand(Idx);
5511 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5514 // TODO: What else can be here? Deal with it.
5515 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5518 // TODO: Some optimizations are still possible here
5519 // ex: Getting one element from a vector, and the rest from another.
5520 if (Elem.getOperand(0) != V)
5523 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5526 else if (IncorrectIdx == -1U) {
5530 // There was already one element with an incorrect index.
5531 // We can't optimize this case to an insertps.
5535 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5537 EVT VT = Op.getSimpleValueType();
5538 unsigned ElementMoveMask = 0;
5539 if (IncorrectIdx == -1U)
5540 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5542 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5544 SDValue InsertpsMask =
5545 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5546 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5552 /// getVShift - Return a vector logical shift node.
5554 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5555 unsigned NumBits, SelectionDAG &DAG,
5556 const TargetLowering &TLI, SDLoc dl) {
5557 assert(VT.is128BitVector() && "Unknown type for VShift");
5558 EVT ShVT = MVT::v2i64;
5559 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5560 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5561 return DAG.getNode(ISD::BITCAST, dl, VT,
5562 DAG.getNode(Opc, dl, ShVT, SrcOp,
5563 DAG.getConstant(NumBits,
5564 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5568 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5570 // Check if the scalar load can be widened into a vector load. And if
5571 // the address is "base + cst" see if the cst can be "absorbed" into
5572 // the shuffle mask.
5573 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5574 SDValue Ptr = LD->getBasePtr();
5575 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5577 EVT PVT = LD->getValueType(0);
5578 if (PVT != MVT::i32 && PVT != MVT::f32)
5583 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5584 FI = FINode->getIndex();
5586 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5587 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5588 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5589 Offset = Ptr.getConstantOperandVal(1);
5590 Ptr = Ptr.getOperand(0);
5595 // FIXME: 256-bit vector instructions don't require a strict alignment,
5596 // improve this code to support it better.
5597 unsigned RequiredAlign = VT.getSizeInBits()/8;
5598 SDValue Chain = LD->getChain();
5599 // Make sure the stack object alignment is at least 16 or 32.
5600 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5601 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5602 if (MFI->isFixedObjectIndex(FI)) {
5603 // Can't change the alignment. FIXME: It's possible to compute
5604 // the exact stack offset and reference FI + adjust offset instead.
5605 // If someone *really* cares about this. That's the way to implement it.
5608 MFI->setObjectAlignment(FI, RequiredAlign);
5612 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5613 // Ptr + (Offset & ~15).
5616 if ((Offset % RequiredAlign) & 3)
5618 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5620 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5621 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5623 int EltNo = (Offset - StartOffset) >> 2;
5624 unsigned NumElems = VT.getVectorNumElements();
5626 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5627 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5628 LD->getPointerInfo().getWithOffset(StartOffset),
5629 false, false, false, 0);
5631 SmallVector<int, 8> Mask;
5632 for (unsigned i = 0; i != NumElems; ++i)
5633 Mask.push_back(EltNo);
5635 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5641 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5642 /// vector of type 'VT', see if the elements can be replaced by a single large
5643 /// load which has the same value as a build_vector whose operands are 'elts'.
5645 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5647 /// FIXME: we'd also like to handle the case where the last elements are zero
5648 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5649 /// There's even a handy isZeroNode for that purpose.
5650 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5651 SDLoc &DL, SelectionDAG &DAG,
5652 bool isAfterLegalize) {
5653 EVT EltVT = VT.getVectorElementType();
5654 unsigned NumElems = Elts.size();
5656 LoadSDNode *LDBase = nullptr;
5657 unsigned LastLoadedElt = -1U;
5659 // For each element in the initializer, see if we've found a load or an undef.
5660 // If we don't find an initial load element, or later load elements are
5661 // non-consecutive, bail out.
5662 for (unsigned i = 0; i < NumElems; ++i) {
5663 SDValue Elt = Elts[i];
5665 if (!Elt.getNode() ||
5666 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5669 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5671 LDBase = cast<LoadSDNode>(Elt.getNode());
5675 if (Elt.getOpcode() == ISD::UNDEF)
5678 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5679 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5684 // If we have found an entire vector of loads and undefs, then return a large
5685 // load of the entire vector width starting at the base pointer. If we found
5686 // consecutive loads for the low half, generate a vzext_load node.
5687 if (LastLoadedElt == NumElems - 1) {
5689 if (isAfterLegalize &&
5690 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5693 SDValue NewLd = SDValue();
5695 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5696 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5697 LDBase->getPointerInfo(),
5698 LDBase->isVolatile(), LDBase->isNonTemporal(),
5699 LDBase->isInvariant(), 0);
5700 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5701 LDBase->getPointerInfo(),
5702 LDBase->isVolatile(), LDBase->isNonTemporal(),
5703 LDBase->isInvariant(), LDBase->getAlignment());
5705 if (LDBase->hasAnyUseOfValue(1)) {
5706 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5708 SDValue(NewLd.getNode(), 1));
5709 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5710 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5711 SDValue(NewLd.getNode(), 1));
5716 if (NumElems == 4 && LastLoadedElt == 1 &&
5717 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5718 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5719 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5721 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5722 LDBase->getPointerInfo(),
5723 LDBase->getAlignment(),
5724 false/*isVolatile*/, true/*ReadMem*/,
5727 // Make sure the newly-created LOAD is in the same position as LDBase in
5728 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5729 // update uses of LDBase's output chain to use the TokenFactor.
5730 if (LDBase->hasAnyUseOfValue(1)) {
5731 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5732 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5733 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5734 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5735 SDValue(ResNode.getNode(), 1));
5738 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5743 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5744 /// to generate a splat value for the following cases:
5745 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5746 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5747 /// a scalar load, or a constant.
5748 /// The VBROADCAST node is returned when a pattern is found,
5749 /// or SDValue() otherwise.
5750 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5751 SelectionDAG &DAG) {
5752 if (!Subtarget->hasFp256())
5755 MVT VT = Op.getSimpleValueType();
5758 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5759 "Unsupported vector type for broadcast.");
5764 switch (Op.getOpcode()) {
5766 // Unknown pattern found.
5769 case ISD::BUILD_VECTOR: {
5770 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5771 BitVector UndefElements;
5772 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5774 // We need a splat of a single value to use broadcast, and it doesn't
5775 // make any sense if the value is only in one element of the vector.
5776 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5780 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5781 Ld.getOpcode() == ISD::ConstantFP);
5783 // Make sure that all of the users of a non-constant load are from the
5784 // BUILD_VECTOR node.
5785 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5790 case ISD::VECTOR_SHUFFLE: {
5791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5793 // Shuffles must have a splat mask where the first element is
5795 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5798 SDValue Sc = Op.getOperand(0);
5799 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5800 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5802 if (!Subtarget->hasInt256())
5805 // Use the register form of the broadcast instruction available on AVX2.
5806 if (VT.getSizeInBits() >= 256)
5807 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5808 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5811 Ld = Sc.getOperand(0);
5812 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5813 Ld.getOpcode() == ISD::ConstantFP);
5815 // The scalar_to_vector node and the suspected
5816 // load node must have exactly one user.
5817 // Constants may have multiple users.
5819 // AVX-512 has register version of the broadcast
5820 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5821 Ld.getValueType().getSizeInBits() >= 32;
5822 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5829 bool IsGE256 = (VT.getSizeInBits() >= 256);
5831 // Handle the broadcasting a single constant scalar from the constant pool
5832 // into a vector. On Sandybridge it is still better to load a constant vector
5833 // from the constant pool and not to broadcast it from a scalar.
5834 if (ConstSplatVal && Subtarget->hasInt256()) {
5835 EVT CVT = Ld.getValueType();
5836 assert(!CVT.isVector() && "Must not broadcast a vector type");
5837 unsigned ScalarSize = CVT.getSizeInBits();
5839 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5840 const Constant *C = nullptr;
5841 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5842 C = CI->getConstantIntValue();
5843 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5844 C = CF->getConstantFPValue();
5846 assert(C && "Invalid constant type");
5848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5849 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5850 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5851 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5852 MachinePointerInfo::getConstantPool(),
5853 false, false, false, Alignment);
5855 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5859 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5860 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5862 // Handle AVX2 in-register broadcasts.
5863 if (!IsLoad && Subtarget->hasInt256() &&
5864 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5865 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5867 // The scalar source must be a normal load.
5871 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5872 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5874 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5875 // double since there is no vbroadcastsd xmm
5876 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5877 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5878 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5881 // Unsupported broadcast.
5885 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5886 /// underlying vector and index.
5888 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5890 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5892 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5893 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5896 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5898 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5900 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5901 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5904 // In this case the vector is the extract_subvector expression and the index
5905 // is 2, as specified by the shuffle.
5906 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5907 SDValue ShuffleVec = SVOp->getOperand(0);
5908 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5909 assert(ShuffleVecVT.getVectorElementType() ==
5910 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5912 int ShuffleIdx = SVOp->getMaskElt(Idx);
5913 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5914 ExtractedFromVec = ShuffleVec;
5920 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5921 MVT VT = Op.getSimpleValueType();
5923 // Skip if insert_vec_elt is not supported.
5924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5925 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5929 unsigned NumElems = Op.getNumOperands();
5933 SmallVector<unsigned, 4> InsertIndices;
5934 SmallVector<int, 8> Mask(NumElems, -1);
5936 for (unsigned i = 0; i != NumElems; ++i) {
5937 unsigned Opc = Op.getOperand(i).getOpcode();
5939 if (Opc == ISD::UNDEF)
5942 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5943 // Quit if more than 1 elements need inserting.
5944 if (InsertIndices.size() > 1)
5947 InsertIndices.push_back(i);
5951 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5952 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5953 // Quit if non-constant index.
5954 if (!isa<ConstantSDNode>(ExtIdx))
5956 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5958 // Quit if extracted from vector of different type.
5959 if (ExtractedFromVec.getValueType() != VT)
5962 if (!VecIn1.getNode())
5963 VecIn1 = ExtractedFromVec;
5964 else if (VecIn1 != ExtractedFromVec) {
5965 if (!VecIn2.getNode())
5966 VecIn2 = ExtractedFromVec;
5967 else if (VecIn2 != ExtractedFromVec)
5968 // Quit if more than 2 vectors to shuffle
5972 if (ExtractedFromVec == VecIn1)
5974 else if (ExtractedFromVec == VecIn2)
5975 Mask[i] = Idx + NumElems;
5978 if (!VecIn1.getNode())
5981 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5982 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5983 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5984 unsigned Idx = InsertIndices[i];
5985 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5986 DAG.getIntPtrConstant(Idx));
5992 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5994 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5996 MVT VT = Op.getSimpleValueType();
5997 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5998 "Unexpected type in LowerBUILD_VECTORvXi1!");
6001 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6002 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6003 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6004 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6007 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6008 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6009 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6010 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6013 bool AllContants = true;
6014 uint64_t Immediate = 0;
6015 int NonConstIdx = -1;
6016 bool IsSplat = true;
6017 unsigned NumNonConsts = 0;
6018 unsigned NumConsts = 0;
6019 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6020 SDValue In = Op.getOperand(idx);
6021 if (In.getOpcode() == ISD::UNDEF)
6023 if (!isa<ConstantSDNode>(In)) {
6024 AllContants = false;
6030 if (cast<ConstantSDNode>(In)->getZExtValue())
6031 Immediate |= (1ULL << idx);
6033 if (In != Op.getOperand(0))
6038 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6039 DAG.getConstant(Immediate, MVT::i16));
6040 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6041 DAG.getIntPtrConstant(0));
6044 if (NumNonConsts == 1 && NonConstIdx != 0) {
6047 SDValue VecAsImm = DAG.getConstant(Immediate,
6048 MVT::getIntegerVT(VT.getSizeInBits()));
6049 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6052 DstVec = DAG.getUNDEF(VT);
6053 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6054 Op.getOperand(NonConstIdx),
6055 DAG.getIntPtrConstant(NonConstIdx));
6057 if (!IsSplat && (NonConstIdx != 0))
6058 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6059 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6062 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6063 DAG.getConstant(-1, SelectVT),
6064 DAG.getConstant(0, SelectVT));
6066 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6067 DAG.getConstant((Immediate | 1), SelectVT),
6068 DAG.getConstant(Immediate, SelectVT));
6069 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6072 /// \brief Return true if \p N implements a horizontal binop and return the
6073 /// operands for the horizontal binop into V0 and V1.
6075 /// This is a helper function of PerformBUILD_VECTORCombine.
6076 /// This function checks that the build_vector \p N in input implements a
6077 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6078 /// operation to match.
6079 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6080 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6081 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6084 /// This function only analyzes elements of \p N whose indices are
6085 /// in range [BaseIdx, LastIdx).
6086 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6088 unsigned BaseIdx, unsigned LastIdx,
6089 SDValue &V0, SDValue &V1) {
6090 EVT VT = N->getValueType(0);
6092 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6093 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6094 "Invalid Vector in input!");
6096 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6097 bool CanFold = true;
6098 unsigned ExpectedVExtractIdx = BaseIdx;
6099 unsigned NumElts = LastIdx - BaseIdx;
6100 V0 = DAG.getUNDEF(VT);
6101 V1 = DAG.getUNDEF(VT);
6103 // Check if N implements a horizontal binop.
6104 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6105 SDValue Op = N->getOperand(i + BaseIdx);
6108 if (Op->getOpcode() == ISD::UNDEF) {
6109 // Update the expected vector extract index.
6110 if (i * 2 == NumElts)
6111 ExpectedVExtractIdx = BaseIdx;
6112 ExpectedVExtractIdx += 2;
6116 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6121 SDValue Op0 = Op.getOperand(0);
6122 SDValue Op1 = Op.getOperand(1);
6124 // Try to match the following pattern:
6125 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6126 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6127 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6128 Op0.getOperand(0) == Op1.getOperand(0) &&
6129 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6130 isa<ConstantSDNode>(Op1.getOperand(1)));
6134 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6135 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6137 if (i * 2 < NumElts) {
6138 if (V0.getOpcode() == ISD::UNDEF)
6139 V0 = Op0.getOperand(0);
6141 if (V1.getOpcode() == ISD::UNDEF)
6142 V1 = Op0.getOperand(0);
6143 if (i * 2 == NumElts)
6144 ExpectedVExtractIdx = BaseIdx;
6147 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6148 if (I0 == ExpectedVExtractIdx)
6149 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6150 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6151 // Try to match the following dag sequence:
6152 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6153 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6157 ExpectedVExtractIdx += 2;
6163 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6164 /// a concat_vector.
6166 /// This is a helper function of PerformBUILD_VECTORCombine.
6167 /// This function expects two 256-bit vectors called V0 and V1.
6168 /// At first, each vector is split into two separate 128-bit vectors.
6169 /// Then, the resulting 128-bit vectors are used to implement two
6170 /// horizontal binary operations.
6172 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6174 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6175 /// the two new horizontal binop.
6176 /// When Mode is set, the first horizontal binop dag node would take as input
6177 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6178 /// horizontal binop dag node would take as input the lower 128-bit of V1
6179 /// and the upper 128-bit of V1.
6181 /// HADD V0_LO, V0_HI
6182 /// HADD V1_LO, V1_HI
6184 /// Otherwise, the first horizontal binop dag node takes as input the lower
6185 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6186 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6188 /// HADD V0_LO, V1_LO
6189 /// HADD V0_HI, V1_HI
6191 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6192 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6193 /// the upper 128-bits of the result.
6194 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6195 SDLoc DL, SelectionDAG &DAG,
6196 unsigned X86Opcode, bool Mode,
6197 bool isUndefLO, bool isUndefHI) {
6198 EVT VT = V0.getValueType();
6199 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6200 "Invalid nodes in input!");
6202 unsigned NumElts = VT.getVectorNumElements();
6203 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6204 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6205 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6206 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6207 EVT NewVT = V0_LO.getValueType();
6209 SDValue LO = DAG.getUNDEF(NewVT);
6210 SDValue HI = DAG.getUNDEF(NewVT);
6213 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6214 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6215 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6216 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6217 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6219 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6220 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6221 V1_LO->getOpcode() != ISD::UNDEF))
6222 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6224 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6225 V1_HI->getOpcode() != ISD::UNDEF))
6226 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6229 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6232 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6233 /// sequence of 'vadd + vsub + blendi'.
6234 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6235 const X86Subtarget *Subtarget) {
6237 EVT VT = BV->getValueType(0);
6238 unsigned NumElts = VT.getVectorNumElements();
6239 SDValue InVec0 = DAG.getUNDEF(VT);
6240 SDValue InVec1 = DAG.getUNDEF(VT);
6242 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6243 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6245 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6247 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6250 // Odd-numbered elements in the input build vector are obtained from
6251 // adding two integer/float elements.
6252 // Even-numbered elements in the input build vector are obtained from
6253 // subtracting two integer/float elements.
6254 unsigned ExpectedOpcode = ISD::FSUB;
6255 unsigned NextExpectedOpcode = ISD::FADD;
6256 bool AddFound = false;
6257 bool SubFound = false;
6259 for (unsigned i = 0, e = NumElts; i != e; i++) {
6260 SDValue Op = BV->getOperand(i);
6262 // Skip 'undef' values.
6263 unsigned Opcode = Op.getOpcode();
6264 if (Opcode == ISD::UNDEF) {
6265 std::swap(ExpectedOpcode, NextExpectedOpcode);
6269 // Early exit if we found an unexpected opcode.
6270 if (Opcode != ExpectedOpcode)
6273 SDValue Op0 = Op.getOperand(0);
6274 SDValue Op1 = Op.getOperand(1);
6276 // Try to match the following pattern:
6277 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6278 // Early exit if we cannot match that sequence.
6279 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6280 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6281 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6282 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6283 Op0.getOperand(1) != Op1.getOperand(1))
6286 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6290 // We found a valid add/sub node. Update the information accordingly.
6296 // Update InVec0 and InVec1.
6297 if (InVec0.getOpcode() == ISD::UNDEF)
6298 InVec0 = Op0.getOperand(0);
6299 if (InVec1.getOpcode() == ISD::UNDEF)
6300 InVec1 = Op1.getOperand(0);
6302 // Make sure that operands in input to each add/sub node always
6303 // come from a same pair of vectors.
6304 if (InVec0 != Op0.getOperand(0)) {
6305 if (ExpectedOpcode == ISD::FSUB)
6308 // FADD is commutable. Try to commute the operands
6309 // and then test again.
6310 std::swap(Op0, Op1);
6311 if (InVec0 != Op0.getOperand(0))
6315 if (InVec1 != Op1.getOperand(0))
6318 // Update the pair of expected opcodes.
6319 std::swap(ExpectedOpcode, NextExpectedOpcode);
6322 // Don't try to fold this build_vector into a VSELECT if it has
6323 // too many UNDEF operands.
6324 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6325 InVec1.getOpcode() != ISD::UNDEF) {
6326 // Emit a sequence of vector add and sub followed by a VSELECT.
6327 // The new VSELECT will be lowered into a BLENDI.
6328 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6329 // and emit a single ADDSUB instruction.
6330 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6331 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6333 // Construct the VSELECT mask.
6334 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6335 EVT SVT = MaskVT.getVectorElementType();
6336 unsigned SVTBits = SVT.getSizeInBits();
6337 SmallVector<SDValue, 8> Ops;
6339 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6340 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6341 APInt::getAllOnesValue(SVTBits);
6342 SDValue Constant = DAG.getConstant(Value, SVT);
6343 Ops.push_back(Constant);
6346 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6347 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6353 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6354 const X86Subtarget *Subtarget) {
6356 EVT VT = N->getValueType(0);
6357 unsigned NumElts = VT.getVectorNumElements();
6358 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6359 SDValue InVec0, InVec1;
6361 // Try to match an ADDSUB.
6362 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6363 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6364 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6365 if (Value.getNode())
6369 // Try to match horizontal ADD/SUB.
6370 unsigned NumUndefsLO = 0;
6371 unsigned NumUndefsHI = 0;
6372 unsigned Half = NumElts/2;
6374 // Count the number of UNDEF operands in the build_vector in input.
6375 for (unsigned i = 0, e = Half; i != e; ++i)
6376 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6379 for (unsigned i = Half, e = NumElts; i != e; ++i)
6380 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6383 // Early exit if this is either a build_vector of all UNDEFs or all the
6384 // operands but one are UNDEF.
6385 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6388 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6389 // Try to match an SSE3 float HADD/HSUB.
6390 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6391 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6393 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6394 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6395 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6396 // Try to match an SSSE3 integer HADD/HSUB.
6397 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6398 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6400 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6401 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6404 if (!Subtarget->hasAVX())
6407 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6408 // Try to match an AVX horizontal add/sub of packed single/double
6409 // precision floating point values from 256-bit vectors.
6410 SDValue InVec2, InVec3;
6411 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6412 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6413 ((InVec0.getOpcode() == ISD::UNDEF ||
6414 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6415 ((InVec1.getOpcode() == ISD::UNDEF ||
6416 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6417 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6419 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6420 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6421 ((InVec0.getOpcode() == ISD::UNDEF ||
6422 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6423 ((InVec1.getOpcode() == ISD::UNDEF ||
6424 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6425 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6426 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6427 // Try to match an AVX2 horizontal add/sub of signed integers.
6428 SDValue InVec2, InVec3;
6430 bool CanFold = true;
6432 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6433 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6434 ((InVec0.getOpcode() == ISD::UNDEF ||
6435 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6436 ((InVec1.getOpcode() == ISD::UNDEF ||
6437 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6438 X86Opcode = X86ISD::HADD;
6439 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6440 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6441 ((InVec0.getOpcode() == ISD::UNDEF ||
6442 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6443 ((InVec1.getOpcode() == ISD::UNDEF ||
6444 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6445 X86Opcode = X86ISD::HSUB;
6450 // Fold this build_vector into a single horizontal add/sub.
6451 // Do this only if the target has AVX2.
6452 if (Subtarget->hasAVX2())
6453 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6455 // Do not try to expand this build_vector into a pair of horizontal
6456 // add/sub if we can emit a pair of scalar add/sub.
6457 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6460 // Convert this build_vector into a pair of horizontal binop followed by
6462 bool isUndefLO = NumUndefsLO == Half;
6463 bool isUndefHI = NumUndefsHI == Half;
6464 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6465 isUndefLO, isUndefHI);
6469 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6470 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6472 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6473 X86Opcode = X86ISD::HADD;
6474 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6475 X86Opcode = X86ISD::HSUB;
6476 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6477 X86Opcode = X86ISD::FHADD;
6478 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6479 X86Opcode = X86ISD::FHSUB;
6483 // Don't try to expand this build_vector into a pair of horizontal add/sub
6484 // if we can simply emit a pair of scalar add/sub.
6485 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6488 // Convert this build_vector into two horizontal add/sub followed by
6490 bool isUndefLO = NumUndefsLO == Half;
6491 bool isUndefHI = NumUndefsHI == Half;
6492 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6493 isUndefLO, isUndefHI);
6500 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6503 MVT VT = Op.getSimpleValueType();
6504 MVT ExtVT = VT.getVectorElementType();
6505 unsigned NumElems = Op.getNumOperands();
6507 // Generate vectors for predicate vectors.
6508 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6509 return LowerBUILD_VECTORvXi1(Op, DAG);
6511 // Vectors containing all zeros can be matched by pxor and xorps later
6512 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6513 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6514 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6515 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6518 return getZeroVector(VT, Subtarget, DAG, dl);
6521 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6522 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6523 // vpcmpeqd on 256-bit vectors.
6524 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6525 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6528 if (!VT.is512BitVector())
6529 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6532 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6533 if (Broadcast.getNode())
6536 unsigned EVTBits = ExtVT.getSizeInBits();
6538 unsigned NumZero = 0;
6539 unsigned NumNonZero = 0;
6540 unsigned NonZeros = 0;
6541 bool IsAllConstants = true;
6542 SmallSet<SDValue, 8> Values;
6543 for (unsigned i = 0; i < NumElems; ++i) {
6544 SDValue Elt = Op.getOperand(i);
6545 if (Elt.getOpcode() == ISD::UNDEF)
6548 if (Elt.getOpcode() != ISD::Constant &&
6549 Elt.getOpcode() != ISD::ConstantFP)
6550 IsAllConstants = false;
6551 if (X86::isZeroNode(Elt))
6554 NonZeros |= (1 << i);
6559 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6560 if (NumNonZero == 0)
6561 return DAG.getUNDEF(VT);
6563 // Special case for single non-zero, non-undef, element.
6564 if (NumNonZero == 1) {
6565 unsigned Idx = countTrailingZeros(NonZeros);
6566 SDValue Item = Op.getOperand(Idx);
6568 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6569 // the value are obviously zero, truncate the value to i32 and do the
6570 // insertion that way. Only do this if the value is non-constant or if the
6571 // value is a constant being inserted into element 0. It is cheaper to do
6572 // a constant pool load than it is to do a movd + shuffle.
6573 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6574 (!IsAllConstants || Idx == 0)) {
6575 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6577 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6578 EVT VecVT = MVT::v4i32;
6579 unsigned VecElts = 4;
6581 // Truncate the value (which may itself be a constant) to i32, and
6582 // convert it to a vector with movd (S2V+shuffle to zero extend).
6583 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6584 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6585 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6587 // Now we have our 32-bit value zero extended in the low element of
6588 // a vector. If Idx != 0, swizzle it into place.
6590 SmallVector<int, 4> Mask;
6591 Mask.push_back(Idx);
6592 for (unsigned i = 1; i != VecElts; ++i)
6594 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6597 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6601 // If we have a constant or non-constant insertion into the low element of
6602 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6603 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6604 // depending on what the source datatype is.
6607 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6609 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6610 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6611 if (VT.is256BitVector() || VT.is512BitVector()) {
6612 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6613 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6614 Item, DAG.getIntPtrConstant(0));
6616 assert(VT.is128BitVector() && "Expected an SSE value type!");
6617 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6618 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6619 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6622 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6623 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6624 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6625 if (VT.is256BitVector()) {
6626 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6627 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6629 assert(VT.is128BitVector() && "Expected an SSE value type!");
6630 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6632 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6636 // Is it a vector logical left shift?
6637 if (NumElems == 2 && Idx == 1 &&
6638 X86::isZeroNode(Op.getOperand(0)) &&
6639 !X86::isZeroNode(Op.getOperand(1))) {
6640 unsigned NumBits = VT.getSizeInBits();
6641 return getVShift(true, VT,
6642 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6643 VT, Op.getOperand(1)),
6644 NumBits/2, DAG, *this, dl);
6647 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6650 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6651 // is a non-constant being inserted into an element other than the low one,
6652 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6653 // movd/movss) to move this into the low element, then shuffle it into
6655 if (EVTBits == 32) {
6656 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6658 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6659 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6660 SmallVector<int, 8> MaskVec;
6661 for (unsigned i = 0; i != NumElems; ++i)
6662 MaskVec.push_back(i == Idx ? 0 : 1);
6663 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6667 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6668 if (Values.size() == 1) {
6669 if (EVTBits == 32) {
6670 // Instead of a shuffle like this:
6671 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6672 // Check if it's possible to issue this instead.
6673 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6674 unsigned Idx = countTrailingZeros(NonZeros);
6675 SDValue Item = Op.getOperand(Idx);
6676 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6677 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6682 // A vector full of immediates; various special cases are already
6683 // handled, so this is best done with a single constant-pool load.
6687 // For AVX-length vectors, build the individual 128-bit pieces and use
6688 // shuffles to put them in place.
6689 if (VT.is256BitVector() || VT.is512BitVector()) {
6690 SmallVector<SDValue, 64> V;
6691 for (unsigned i = 0; i != NumElems; ++i)
6692 V.push_back(Op.getOperand(i));
6694 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6696 // Build both the lower and upper subvector.
6697 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6698 makeArrayRef(&V[0], NumElems/2));
6699 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6700 makeArrayRef(&V[NumElems / 2], NumElems/2));
6702 // Recreate the wider vector with the lower and upper part.
6703 if (VT.is256BitVector())
6704 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6705 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6708 // Let legalizer expand 2-wide build_vectors.
6709 if (EVTBits == 64) {
6710 if (NumNonZero == 1) {
6711 // One half is zero or undef.
6712 unsigned Idx = countTrailingZeros(NonZeros);
6713 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6714 Op.getOperand(Idx));
6715 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6720 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6721 if (EVTBits == 8 && NumElems == 16) {
6722 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6724 if (V.getNode()) return V;
6727 if (EVTBits == 16 && NumElems == 8) {
6728 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6730 if (V.getNode()) return V;
6733 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6734 if (EVTBits == 32 && NumElems == 4) {
6735 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6736 NumZero, DAG, Subtarget, *this);
6741 // If element VT is == 32 bits, turn it into a number of shuffles.
6742 SmallVector<SDValue, 8> V(NumElems);
6743 if (NumElems == 4 && NumZero > 0) {
6744 for (unsigned i = 0; i < 4; ++i) {
6745 bool isZero = !(NonZeros & (1 << i));
6747 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6749 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6752 for (unsigned i = 0; i < 2; ++i) {
6753 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6756 V[i] = V[i*2]; // Must be a zero vector.
6759 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6762 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6765 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6770 bool Reverse1 = (NonZeros & 0x3) == 2;
6771 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6775 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6776 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6778 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6781 if (Values.size() > 1 && VT.is128BitVector()) {
6782 // Check for a build vector of consecutive loads.
6783 for (unsigned i = 0; i < NumElems; ++i)
6784 V[i] = Op.getOperand(i);
6786 // Check for elements which are consecutive loads.
6787 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6791 // Check for a build vector from mostly shuffle plus few inserting.
6792 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6796 // For SSE 4.1, use insertps to put the high elements into the low element.
6797 if (getSubtarget()->hasSSE41()) {
6799 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6800 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6802 Result = DAG.getUNDEF(VT);
6804 for (unsigned i = 1; i < NumElems; ++i) {
6805 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6806 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6807 Op.getOperand(i), DAG.getIntPtrConstant(i));
6812 // Otherwise, expand into a number of unpckl*, start by extending each of
6813 // our (non-undef) elements to the full vector width with the element in the
6814 // bottom slot of the vector (which generates no code for SSE).
6815 for (unsigned i = 0; i < NumElems; ++i) {
6816 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6817 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6819 V[i] = DAG.getUNDEF(VT);
6822 // Next, we iteratively mix elements, e.g. for v4f32:
6823 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6824 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6825 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6826 unsigned EltStride = NumElems >> 1;
6827 while (EltStride != 0) {
6828 for (unsigned i = 0; i < EltStride; ++i) {
6829 // If V[i+EltStride] is undef and this is the first round of mixing,
6830 // then it is safe to just drop this shuffle: V[i] is already in the
6831 // right place, the one element (since it's the first round) being
6832 // inserted as undef can be dropped. This isn't safe for successive
6833 // rounds because they will permute elements within both vectors.
6834 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6835 EltStride == NumElems/2)
6838 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6847 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6848 // to create 256-bit vectors from two other 128-bit ones.
6849 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6851 MVT ResVT = Op.getSimpleValueType();
6853 assert((ResVT.is256BitVector() ||
6854 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6856 SDValue V1 = Op.getOperand(0);
6857 SDValue V2 = Op.getOperand(1);
6858 unsigned NumElems = ResVT.getVectorNumElements();
6859 if(ResVT.is256BitVector())
6860 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6862 if (Op.getNumOperands() == 4) {
6863 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6864 ResVT.getVectorNumElements()/2);
6865 SDValue V3 = Op.getOperand(2);
6866 SDValue V4 = Op.getOperand(3);
6867 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6868 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6870 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6873 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6874 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6875 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6876 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6877 Op.getNumOperands() == 4)));
6879 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6880 // from two other 128-bit ones.
6882 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6883 return LowerAVXCONCAT_VECTORS(Op, DAG);
6887 //===----------------------------------------------------------------------===//
6888 // Vector shuffle lowering
6890 // This is an experimental code path for lowering vector shuffles on x86. It is
6891 // designed to handle arbitrary vector shuffles and blends, gracefully
6892 // degrading performance as necessary. It works hard to recognize idiomatic
6893 // shuffles and lower them to optimal instruction patterns without leaving
6894 // a framework that allows reasonably efficient handling of all vector shuffle
6896 //===----------------------------------------------------------------------===//
6898 /// \brief Tiny helper function to identify a no-op mask.
6900 /// This is a somewhat boring predicate function. It checks whether the mask
6901 /// array input, which is assumed to be a single-input shuffle mask of the kind
6902 /// used by the X86 shuffle instructions (not a fully general
6903 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6904 /// in-place shuffle are 'no-op's.
6905 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6906 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6907 if (Mask[i] != -1 && Mask[i] != i)
6912 /// \brief Helper function to classify a mask as a single-input mask.
6914 /// This isn't a generic single-input test because in the vector shuffle
6915 /// lowering we canonicalize single inputs to be the first input operand. This
6916 /// means we can more quickly test for a single input by only checking whether
6917 /// an input from the second operand exists. We also assume that the size of
6918 /// mask corresponds to the size of the input vectors which isn't true in the
6919 /// fully general case.
6920 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6922 if (M >= (int)Mask.size())
6927 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6929 /// This helper function produces an 8-bit shuffle immediate corresponding to
6930 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6931 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6934 /// NB: We rely heavily on "undef" masks preserving the input lane.
6935 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6936 SelectionDAG &DAG) {
6937 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6938 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6939 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6940 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6941 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6944 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6945 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6946 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6947 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6948 return DAG.getConstant(Imm, MVT::i8);
6951 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
6953 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
6954 /// support for floating point shuffles but not integer shuffles. These
6955 /// instructions will incur a domain crossing penalty on some chips though so
6956 /// it is better to avoid lowering through this for integer vectors where
6958 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6959 const X86Subtarget *Subtarget,
6960 SelectionDAG &DAG) {
6962 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
6963 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6964 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6965 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6966 ArrayRef<int> Mask = SVOp->getMask();
6967 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
6969 if (isSingleInputShuffleMask(Mask)) {
6970 // Straight shuffle of a single input vector. Simulate this by using the
6971 // single input as both of the "inputs" to this instruction..
6972 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
6973 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
6974 DAG.getConstant(SHUFPDMask, MVT::i8));
6976 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
6977 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
6979 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
6980 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
6981 DAG.getConstant(SHUFPDMask, MVT::i8));
6984 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
6986 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
6987 /// the integer unit to minimize domain crossing penalties. However, for blends
6988 /// it falls back to the floating point shuffle operation with appropriate bit
6990 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6991 const X86Subtarget *Subtarget,
6992 SelectionDAG &DAG) {
6994 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
6995 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6996 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6998 ArrayRef<int> Mask = SVOp->getMask();
6999 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7001 if (isSingleInputShuffleMask(Mask)) {
7002 // Straight shuffle of a single input vector. For everything from SSE2
7003 // onward this has a single fast instruction with no scary immediates.
7004 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7005 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7006 int WidenedMask[4] = {
7007 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7008 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7010 ISD::BITCAST, DL, MVT::v2i64,
7011 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7012 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7015 // We implement this with SHUFPD which is pretty lame because it will likely
7016 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7017 // However, all the alternatives are still more cycles and newer chips don't
7018 // have this problem. It would be really nice if x86 had better shuffles here.
7019 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7020 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7021 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7022 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7025 /// \brief Lower 4-lane 32-bit floating point shuffles.
7027 /// Uses instructions exclusively from the floating point unit to minimize
7028 /// domain crossing penalties, as these are sufficient to implement all v4f32
7030 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7031 const X86Subtarget *Subtarget,
7032 SelectionDAG &DAG) {
7034 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7035 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7036 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7038 ArrayRef<int> Mask = SVOp->getMask();
7039 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7041 SDValue LowV = V1, HighV = V2;
7042 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7045 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7047 if (NumV2Elements == 0)
7048 // Straight shuffle of a single input vector. We pass the input vector to
7049 // both operands to simulate this with a SHUFPS.
7050 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7051 getV4X86ShuffleImm8ForMask(Mask, DAG));
7053 if (NumV2Elements == 1) {
7055 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7057 // Compute the index adjacent to V2Index and in the same half by toggling
7059 int V2AdjIndex = V2Index ^ 1;
7061 if (Mask[V2AdjIndex] == -1) {
7062 // Handles all the cases where we have a single V2 element and an undef.
7063 // This will only ever happen in the high lanes because we commute the
7064 // vector otherwise.
7066 std::swap(LowV, HighV);
7067 NewMask[V2Index] -= 4;
7069 // Handle the case where the V2 element ends up adjacent to a V1 element.
7070 // To make this work, blend them together as the first step.
7071 int V1Index = V2AdjIndex;
7072 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7073 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7074 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7076 // Now proceed to reconstruct the final blend as we have the necessary
7077 // high or low half formed.
7084 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7085 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7087 } else if (NumV2Elements == 2) {
7088 if (Mask[0] < 4 && Mask[1] < 4) {
7089 // Handle the easy case where we have V1 in the low lanes and V2 in the
7090 // high lanes. We never see this reversed because we sort the shuffle.
7094 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7095 // trying to place elements directly, just blend them and set up the final
7096 // shuffle to place them.
7098 // The first two blend mask elements are for V1, the second two are for
7100 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7101 Mask[2] < 4 ? Mask[2] : Mask[3],
7102 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7103 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7104 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7105 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7107 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7110 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7111 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7112 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7113 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7116 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7117 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7120 /// \brief Lower 4-lane i32 vector shuffles.
7122 /// We try to handle these with integer-domain shuffles where we can, but for
7123 /// blends we use the floating point domain blend instructions.
7124 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7125 const X86Subtarget *Subtarget,
7126 SelectionDAG &DAG) {
7128 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7129 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7130 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7132 ArrayRef<int> Mask = SVOp->getMask();
7133 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7135 if (isSingleInputShuffleMask(Mask))
7136 // Straight shuffle of a single input vector. For everything from SSE2
7137 // onward this has a single fast instruction with no scary immediates.
7138 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7139 getV4X86ShuffleImm8ForMask(Mask, DAG));
7141 // We implement this with SHUFPS because it can blend from two vectors.
7142 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7143 // up the inputs, bypassing domain shift penalties that we would encur if we
7144 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7146 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7147 DAG.getVectorShuffle(
7149 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7150 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7153 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7154 /// shuffle lowering, and the most complex part.
7156 /// The lowering strategy is to try to form pairs of input lanes which are
7157 /// targeted at the same half of the final vector, and then use a dword shuffle
7158 /// to place them onto the right half, and finally unpack the paired lanes into
7159 /// their final position.
7161 /// The exact breakdown of how to form these dword pairs and align them on the
7162 /// correct sides is really tricky. See the comments within the function for
7163 /// more of the details.
7164 static SDValue lowerV8I16SingleInputVectorShuffle(
7165 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7166 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7167 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7168 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7169 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7171 SmallVector<int, 4> LoInputs;
7172 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7173 [](int M) { return M >= 0; });
7174 std::sort(LoInputs.begin(), LoInputs.end());
7175 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7176 SmallVector<int, 4> HiInputs;
7177 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7178 [](int M) { return M >= 0; });
7179 std::sort(HiInputs.begin(), HiInputs.end());
7180 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7182 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7183 int NumHToL = LoInputs.size() - NumLToL;
7185 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7186 int NumHToH = HiInputs.size() - NumLToH;
7187 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7188 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7189 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7190 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7192 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7193 // such inputs we can swap two of the dwords across the half mark and end up
7194 // with <=2 inputs to each half in each half. Once there, we can fall through
7195 // to the generic code below. For example:
7197 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7198 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7200 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7202 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7203 int ThreeInputHalfSum, int OneInputHalfOffset) {
7204 // Compute the index of dword with only one word among the three inputs in
7205 // a half by taking the sum of the half with three inputs and subtracting
7206 // the sum of the actual three inputs. The difference is the remaining
7208 int DWordA = (ThreeInputHalfSum -
7209 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7211 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7213 int PSHUFDMask[] = {0, 1, 2, 3};
7214 PSHUFDMask[DWordA] = DWordB;
7215 PSHUFDMask[DWordB] = DWordA;
7216 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7217 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7218 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7219 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7221 // Adjust the mask to match the new locations of A and B.
7223 if (M != -1 && M/2 == DWordA)
7224 M = 2 * DWordB + M % 2;
7225 else if (M != -1 && M/2 == DWordB)
7226 M = 2 * DWordA + M % 2;
7228 // Recurse back into this routine to re-compute state now that this isn't
7229 // a 3 and 1 problem.
7230 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7233 if (NumLToL == 3 && NumHToL == 1)
7234 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7235 else if (NumLToL == 1 && NumHToL == 3)
7236 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7237 else if (NumLToH == 1 && NumHToH == 3)
7238 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7239 else if (NumLToH == 3 && NumHToH == 1)
7240 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7242 // At this point there are at most two inputs to the low and high halves from
7243 // each half. That means the inputs can always be grouped into dwords and
7244 // those dwords can then be moved to the correct half with a dword shuffle.
7245 // We use at most one low and one high word shuffle to collect these paired
7246 // inputs into dwords, and finally a dword shuffle to place them.
7247 int PSHUFLMask[4] = {-1, -1, -1, -1};
7248 int PSHUFHMask[4] = {-1, -1, -1, -1};
7249 int PSHUFDMask[4] = {-1, -1, -1, -1};
7251 // First fix the masks for all the inputs that are staying in their
7252 // original halves. This will then dictate the targets of the cross-half
7254 auto fixInPlaceInputs = [&PSHUFDMask](
7255 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7256 MutableArrayRef<int> HalfMask, int HalfOffset) {
7257 if (InPlaceInputs.empty())
7259 if (InPlaceInputs.size() == 1) {
7260 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7261 InPlaceInputs[0] - HalfOffset;
7262 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7266 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7267 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7268 InPlaceInputs[0] - HalfOffset;
7269 // Put the second input next to the first so that they are packed into
7270 // a dword. We find the adjacent index by toggling the low bit.
7271 int AdjIndex = InPlaceInputs[0] ^ 1;
7272 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7273 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7274 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7276 if (!HToLInputs.empty())
7277 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7278 if (!LToHInputs.empty())
7279 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7281 // Now gather the cross-half inputs and place them into a free dword of
7282 // their target half.
7283 // FIXME: This operation could almost certainly be simplified dramatically to
7284 // look more like the 3-1 fixing operation.
7285 auto moveInputsToRightHalf = [&PSHUFDMask](
7286 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7287 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7288 int SourceOffset, int DestOffset) {
7289 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7290 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7292 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7294 int LowWord = Word & ~1;
7295 int HighWord = Word | 1;
7296 return isWordClobbered(SourceHalfMask, LowWord) ||
7297 isWordClobbered(SourceHalfMask, HighWord);
7300 if (IncomingInputs.empty())
7303 if (ExistingInputs.empty()) {
7304 // Map any dwords with inputs from them into the right half.
7305 for (int Input : IncomingInputs) {
7306 // If the source half mask maps over the inputs, turn those into
7307 // swaps and use the swapped lane.
7308 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7309 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7310 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7311 Input - SourceOffset;
7312 // We have to swap the uses in our half mask in one sweep.
7313 for (int &M : HalfMask)
7314 if (M == SourceHalfMask[Input - SourceOffset])
7316 else if (M == Input)
7317 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7319 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7320 Input - SourceOffset &&
7321 "Previous placement doesn't match!");
7323 // Note that this correctly re-maps both when we do a swap and when
7324 // we observe the other side of the swap above. We rely on that to
7325 // avoid swapping the members of the input list directly.
7326 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7329 // Map the input's dword into the correct half.
7330 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7331 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7333 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7335 "Previous placement doesn't match!");
7338 // And just directly shift any other-half mask elements to be same-half
7339 // as we will have mirrored the dword containing the element into the
7340 // same position within that half.
7341 for (int &M : HalfMask)
7342 if (M >= SourceOffset && M < SourceOffset + 4) {
7343 M = M - SourceOffset + DestOffset;
7344 assert(M >= 0 && "This should never wrap below zero!");
7349 // Ensure we have the input in a viable dword of its current half. This
7350 // is particularly tricky because the original position may be clobbered
7351 // by inputs being moved and *staying* in that half.
7352 if (IncomingInputs.size() == 1) {
7353 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7354 int InputFixed = std::find(std::begin(SourceHalfMask),
7355 std::end(SourceHalfMask), -1) -
7356 std::begin(SourceHalfMask) + SourceOffset;
7357 SourceHalfMask[InputFixed - SourceOffset] =
7358 IncomingInputs[0] - SourceOffset;
7359 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7361 IncomingInputs[0] = InputFixed;
7363 } else if (IncomingInputs.size() == 2) {
7364 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7365 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7366 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7367 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7368 "Not all dwords can be clobbered!");
7369 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7370 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7371 for (int &M : HalfMask)
7372 if (M == IncomingInputs[0])
7373 M = SourceDWordBase + SourceOffset;
7374 else if (M == IncomingInputs[1])
7375 M = SourceDWordBase + 1 + SourceOffset;
7376 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7377 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7380 llvm_unreachable("Unhandled input size!");
7383 // Now hoist the DWord down to the right half.
7384 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7385 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7386 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7387 for (int Input : IncomingInputs)
7388 std::replace(HalfMask.begin(), HalfMask.end(), Input,
7389 FreeDWord * 2 + Input % 2);
7391 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7392 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7393 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7394 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7396 // Now enact all the shuffles we've computed to move the inputs into their
7398 if (!isNoopShuffleMask(PSHUFLMask))
7399 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7400 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7401 if (!isNoopShuffleMask(PSHUFHMask))
7402 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7403 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7404 if (!isNoopShuffleMask(PSHUFDMask))
7405 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7406 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7407 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7408 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7410 // At this point, each half should contain all its inputs, and we can then
7411 // just shuffle them into their final position.
7412 assert(std::count_if(LoMask.begin(), LoMask.end(),
7413 [](int M) { return M >= 4; }) == 0 &&
7414 "Failed to lift all the high half inputs to the low mask!");
7415 assert(std::count_if(HiMask.begin(), HiMask.end(),
7416 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7417 "Failed to lift all the low half inputs to the high mask!");
7419 // Do a half shuffle for the low mask.
7420 if (!isNoopShuffleMask(LoMask))
7421 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7422 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7424 // Do a half shuffle with the high mask after shifting its values down.
7425 for (int &M : HiMask)
7428 if (!isNoopShuffleMask(HiMask))
7429 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7430 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7435 /// \brief Detect whether the mask pattern should be lowered through
7438 /// This essentially tests whether viewing the mask as an interleaving of two
7439 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7440 /// lowering it through interleaving is a significantly better strategy.
7441 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7442 int NumEvenInputs[2] = {0, 0};
7443 int NumOddInputs[2] = {0, 0};
7444 int NumLoInputs[2] = {0, 0};
7445 int NumHiInputs[2] = {0, 0};
7446 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7450 int InputIdx = Mask[i] >= Size;
7453 ++NumLoInputs[InputIdx];
7455 ++NumHiInputs[InputIdx];
7458 ++NumEvenInputs[InputIdx];
7460 ++NumOddInputs[InputIdx];
7463 // The minimum number of cross-input results for both the interleaved and
7464 // split cases. If interleaving results in fewer cross-input results, return
7466 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7467 NumEvenInputs[0] + NumOddInputs[1]);
7468 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7469 NumLoInputs[0] + NumHiInputs[1]);
7470 return InterleavedCrosses < SplitCrosses;
7473 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7475 /// This strategy only works when the inputs from each vector fit into a single
7476 /// half of that vector, and generally there are not so many inputs as to leave
7477 /// the in-place shuffles required highly constrained (and thus expensive). It
7478 /// shifts all the inputs into a single side of both input vectors and then
7479 /// uses an unpack to interleave these inputs in a single vector. At that
7480 /// point, we will fall back on the generic single input shuffle lowering.
7481 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7483 MutableArrayRef<int> Mask,
7484 const X86Subtarget *Subtarget,
7485 SelectionDAG &DAG) {
7486 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7487 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7488 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7489 for (int i = 0; i < 8; ++i)
7490 if (Mask[i] >= 0 && Mask[i] < 4)
7491 LoV1Inputs.push_back(i);
7492 else if (Mask[i] >= 4 && Mask[i] < 8)
7493 HiV1Inputs.push_back(i);
7494 else if (Mask[i] >= 8 && Mask[i] < 12)
7495 LoV2Inputs.push_back(i);
7496 else if (Mask[i] >= 12)
7497 HiV2Inputs.push_back(i);
7499 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7500 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7503 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7504 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7505 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7507 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7508 HiV1Inputs.size() + HiV2Inputs.size();
7510 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7511 ArrayRef<int> HiInputs, bool MoveToLo,
7513 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7514 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7515 if (BadInputs.empty())
7518 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7519 int MoveOffset = MoveToLo ? 0 : 4;
7521 if (GoodInputs.empty()) {
7522 for (int BadInput : BadInputs) {
7523 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7524 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7527 if (GoodInputs.size() == 2) {
7528 // If the low inputs are spread across two dwords, pack them into
7530 MoveMask[Mask[GoodInputs[0]] % 2 + MoveOffset] =
7531 Mask[GoodInputs[0]] - MaskOffset;
7532 MoveMask[Mask[GoodInputs[1]] % 2 + MoveOffset] =
7533 Mask[GoodInputs[1]] - MaskOffset;
7534 Mask[GoodInputs[0]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7535 Mask[GoodInputs[1]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7537 // Otherwise pin the low inputs.
7538 for (int GoodInput : GoodInputs)
7539 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7543 std::find(std::begin(MoveMask) + MoveOffset, std::end(MoveMask), -1) -
7544 std::begin(MoveMask);
7545 assert(MoveMaskIdx >= MoveOffset && "Established above");
7547 if (BadInputs.size() == 2) {
7548 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7549 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7550 MoveMask[MoveMaskIdx + Mask[BadInputs[0]] % 2] =
7551 Mask[BadInputs[0]] - MaskOffset;
7552 MoveMask[MoveMaskIdx + Mask[BadInputs[1]] % 2] =
7553 Mask[BadInputs[1]] - MaskOffset;
7554 Mask[BadInputs[0]] = MoveMaskIdx + Mask[BadInputs[0]] % 2 + MaskOffset;
7555 Mask[BadInputs[1]] = MoveMaskIdx + Mask[BadInputs[1]] % 2 + MaskOffset;
7557 assert(BadInputs.size() == 1 && "All sizes handled");
7558 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7559 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7563 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7566 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7568 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7571 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7572 // cross-half traffic in the final shuffle.
7574 // Munge the mask to be a single-input mask after the unpack merges the
7578 M = 2 * (M % 4) + (M / 8);
7580 return DAG.getVectorShuffle(
7581 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7582 DL, MVT::v8i16, V1, V2),
7583 DAG.getUNDEF(MVT::v8i16), Mask);
7586 /// \brief Generic lowering of 8-lane i16 shuffles.
7588 /// This handles both single-input shuffles and combined shuffle/blends with
7589 /// two inputs. The single input shuffles are immediately delegated to
7590 /// a dedicated lowering routine.
7592 /// The blends are lowered in one of three fundamental ways. If there are few
7593 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7594 /// of the input is significantly cheaper when lowered as an interleaving of
7595 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7596 /// halves of the inputs separately (making them have relatively few inputs)
7597 /// and then concatenate them.
7598 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7599 const X86Subtarget *Subtarget,
7600 SelectionDAG &DAG) {
7602 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7603 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7604 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7605 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7606 ArrayRef<int> OrigMask = SVOp->getMask();
7607 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7608 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7609 MutableArrayRef<int> Mask(MaskStorage);
7611 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7613 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7614 auto isV2 = [](int M) { return M >= 8; };
7616 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7617 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7619 if (NumV2Inputs == 0)
7620 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7622 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7623 "to be V1-input shuffles.");
7625 if (NumV1Inputs + NumV2Inputs <= 4)
7626 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7628 // Check whether an interleaving lowering is likely to be more efficient.
7629 // This isn't perfect but it is a strong heuristic that tends to work well on
7630 // the kinds of shuffles that show up in practice.
7632 // FIXME: Handle 1x, 2x, and 4x interleaving.
7633 if (shouldLowerAsInterleaving(Mask)) {
7634 // FIXME: Figure out whether we should pack these into the low or high
7637 int EMask[8], OMask[8];
7638 for (int i = 0; i < 4; ++i) {
7639 EMask[i] = Mask[2*i];
7640 OMask[i] = Mask[2*i + 1];
7645 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7646 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7648 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7651 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7652 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7654 for (int i = 0; i < 4; ++i) {
7655 LoBlendMask[i] = Mask[i];
7656 HiBlendMask[i] = Mask[i + 4];
7659 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7660 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7661 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7662 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7664 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7665 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7668 /// \brief Generic lowering of v16i8 shuffles.
7670 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7671 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7672 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7673 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7675 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7676 const X86Subtarget *Subtarget,
7677 SelectionDAG &DAG) {
7679 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7680 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7681 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7683 ArrayRef<int> OrigMask = SVOp->getMask();
7684 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7685 int MaskStorage[16] = {
7686 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7687 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7688 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7689 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7690 MutableArrayRef<int> Mask(MaskStorage);
7691 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7692 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7694 // For single-input shuffles, there are some nicer lowering tricks we can use.
7695 if (isSingleInputShuffleMask(Mask)) {
7696 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7697 // Notably, this handles splat and partial-splat shuffles more efficiently.
7699 // FIXME: We should check for other patterns which can be widened into an
7700 // i16 shuffle as well.
7701 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7702 for (int i = 0; i < 16; i += 2) {
7703 if (Mask[i] != Mask[i + 1])
7708 if (canWidenViaDuplication(Mask)) {
7709 SmallVector<int, 4> LoInputs;
7710 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7711 [](int M) { return M >= 0 && M < 8; });
7712 std::sort(LoInputs.begin(), LoInputs.end());
7713 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7715 SmallVector<int, 4> HiInputs;
7716 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7717 [](int M) { return M >= 8; });
7718 std::sort(HiInputs.begin(), HiInputs.end());
7719 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7722 bool TargetLo = LoInputs.size() >= HiInputs.size();
7723 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7724 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7727 SmallDenseMap<int, int, 8> LaneMap;
7728 for (int i = 0; i < 16; ++i)
7730 for (int I : InPlaceInputs) {
7734 int FreeByteIdx = 0;
7735 int TargetOffset = TargetLo ? 0 : 8;
7736 for (int I : MovingInputs) {
7737 // Walk the free index into the byte mask until we find an unoccupied
7738 // spot. We bound this to 8 steps to catch bugs, the pigeonhole
7739 // principle indicates that there *must* be a spot as we can only have
7740 // 8 duplicated inputs. We have to walk the index using modular
7741 // arithmetic to wrap around as necessary.
7742 // FIXME: We could do a much better job of picking an inexpensive slot
7743 // so this doesn't go through the worst case for the byte shuffle.
7744 for (int j = 0; j < 8 && ByteMask[FreeByteIdx + TargetOffset] != -1;
7745 ++j, FreeByteIdx = (FreeByteIdx + 1) % 8)
7747 assert(ByteMask[FreeByteIdx + TargetOffset] == -1 &&
7748 "Failed to find a free byte!");
7749 ByteMask[FreeByteIdx + TargetOffset] = I;
7750 LaneMap[I] = FreeByteIdx + TargetOffset;
7752 V1 = DAG.getVectorShuffle(MVT::v16i8, DL, V1, DAG.getUNDEF(MVT::v16i8),
7758 // Unpack the bytes to form the i16s that will be shuffled into place.
7759 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7760 MVT::v16i8, V1, V1);
7762 int I16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7763 for (int i = 0; i < 16; i += 2) {
7765 I16Shuffle[i / 2] = Mask[i] - (TargetLo ? 0 : 8);
7766 assert(I16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7768 return DAG.getVectorShuffle(MVT::v8i16, DL,
7769 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7770 DAG.getUNDEF(MVT::v8i16), I16Shuffle);
7774 // Check whether an interleaving lowering is likely to be more efficient.
7775 // This isn't perfect but it is a strong heuristic that tends to work well on
7776 // the kinds of shuffles that show up in practice.
7778 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7779 if (shouldLowerAsInterleaving(Mask)) {
7780 // FIXME: Figure out whether we should pack these into the low or high
7783 int EMask[16], OMask[16];
7784 for (int i = 0; i < 8; ++i) {
7785 EMask[i] = Mask[2*i];
7786 OMask[i] = Mask[2*i + 1];
7791 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7792 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7794 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7796 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
7798 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7799 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, Zero));
7801 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7802 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, Zero));
7804 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7805 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V2, Zero));
7807 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7808 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V2, Zero));
7810 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7811 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7812 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7813 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7815 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
7816 MutableArrayRef<int> V1HalfBlendMask,
7817 MutableArrayRef<int> V2HalfBlendMask) {
7818 for (int i = 0; i < 8; ++i)
7819 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
7820 V1HalfBlendMask[i] = HalfMask[i];
7822 } else if (HalfMask[i] >= 16) {
7823 V2HalfBlendMask[i] = HalfMask[i] - 16;
7824 HalfMask[i] = i + 8;
7827 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
7828 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
7830 SDValue V1Lo = DAG.getVectorShuffle(MVT::v8i16, DL, LoV1, HiV1, V1LoBlendMask);
7831 SDValue V2Lo = DAG.getVectorShuffle(MVT::v8i16, DL, LoV2, HiV2, V2LoBlendMask);
7832 SDValue V1Hi = DAG.getVectorShuffle(MVT::v8i16, DL, LoV1, HiV1, V1HiBlendMask);
7833 SDValue V2Hi = DAG.getVectorShuffle(MVT::v8i16, DL, LoV2, HiV2, V2HiBlendMask);
7835 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
7836 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
7838 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
7841 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
7843 /// This routine breaks down the specific type of 128-bit shuffle and
7844 /// dispatches to the lowering routines accordingly.
7845 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7846 MVT VT, const X86Subtarget *Subtarget,
7847 SelectionDAG &DAG) {
7848 switch (VT.SimpleTy) {
7850 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7852 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7854 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7856 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7858 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
7860 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
7863 llvm_unreachable("Unimplemented!");
7867 /// \brief Tiny helper function to test whether adjacent masks are sequential.
7868 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
7869 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7870 if (Mask[i] + 1 != Mask[i+1])
7876 /// \brief Top-level lowering for x86 vector shuffles.
7878 /// This handles decomposition, canonicalization, and lowering of all x86
7879 /// vector shuffles. Most of the specific lowering strategies are encapsulated
7880 /// above in helper routines. The canonicalization attempts to widen shuffles
7881 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
7882 /// s.t. only one of the two inputs needs to be tested, etc.
7883 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7884 SelectionDAG &DAG) {
7885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7886 ArrayRef<int> Mask = SVOp->getMask();
7887 SDValue V1 = Op.getOperand(0);
7888 SDValue V2 = Op.getOperand(1);
7889 MVT VT = Op.getSimpleValueType();
7890 int NumElements = VT.getVectorNumElements();
7893 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7895 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7896 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7897 if (V1IsUndef && V2IsUndef)
7898 return DAG.getUNDEF(VT);
7900 // When we create a shuffle node we put the UNDEF node to second operand,
7901 // but in some cases the first operand may be transformed to UNDEF.
7902 // In this case we should just commute the node.
7904 return CommuteVectorShuffle(SVOp, DAG);
7906 // Check for non-undef masks pointing at an undef vector and make the masks
7907 // undef as well. This makes it easier to match the shuffle based solely on
7911 if (M >= NumElements) {
7912 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
7913 for (int &M : NewMask)
7914 if (M >= NumElements)
7916 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
7919 // For integer vector shuffles, try to collapse them into a shuffle of fewer
7920 // lanes but wider integers. We cap this to not form integers larger than i64
7921 // but it might be interesting to form i128 integers to handle flipping the
7922 // low and high halves of AVX 256-bit vectors.
7923 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
7924 areAdjacentMasksSequential(Mask)) {
7925 SmallVector<int, 8> NewMask;
7926 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7927 NewMask.push_back(Mask[i] / 2);
7929 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
7930 VT.getVectorNumElements() / 2);
7931 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
7932 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
7933 return DAG.getNode(ISD::BITCAST, dl, VT,
7934 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
7937 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
7938 for (int M : SVOp->getMask())
7941 else if (M < NumElements)
7946 // Commute the shuffle as needed such that more elements come from V1 than
7947 // V2. This allows us to match the shuffle pattern strictly on how many
7948 // elements come from V1 without handling the symmetric cases.
7949 if (NumV2Elements > NumV1Elements)
7950 return CommuteVectorShuffle(SVOp, DAG);
7952 // When the number of V1 and V2 elements are the same, try to minimize the
7953 // number of uses of V2 in the low half of the vector.
7954 if (NumV1Elements == NumV2Elements) {
7955 int LowV1Elements = 0, LowV2Elements = 0;
7956 for (int M : SVOp->getMask().slice(0, NumElements / 2))
7957 if (M >= NumElements)
7961 if (LowV2Elements > LowV1Elements)
7962 return CommuteVectorShuffle(SVOp, DAG);
7965 // For each vector width, delegate to a specialized lowering routine.
7966 if (VT.getSizeInBits() == 128)
7967 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
7969 llvm_unreachable("Unimplemented!");
7973 //===----------------------------------------------------------------------===//
7974 // Legacy vector shuffle lowering
7976 // This code is the legacy code handling vector shuffles until the above
7977 // replaces its functionality and performance.
7978 //===----------------------------------------------------------------------===//
7980 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
7981 bool hasInt256, unsigned *MaskOut = nullptr) {
7982 MVT EltVT = VT.getVectorElementType();
7984 // There is no blend with immediate in AVX-512.
7985 if (VT.is512BitVector())
7988 if (!hasSSE41 || EltVT == MVT::i8)
7990 if (!hasInt256 && VT == MVT::v16i16)
7993 unsigned MaskValue = 0;
7994 unsigned NumElems = VT.getVectorNumElements();
7995 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
7996 unsigned NumLanes = (NumElems - 1) / 8 + 1;
7997 unsigned NumElemsInLane = NumElems / NumLanes;
7999 // Blend for v16i16 should be symetric for the both lanes.
8000 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8002 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8003 int EltIdx = MaskVals[i];
8005 if ((EltIdx < 0 || EltIdx == (int)i) &&
8006 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8009 if (((unsigned)EltIdx == (i + NumElems)) &&
8010 (SndLaneEltIdx < 0 ||
8011 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8012 MaskValue |= (1 << i);
8018 *MaskOut = MaskValue;
8022 // Try to lower a shuffle node into a simple blend instruction.
8023 // This function assumes isBlendMask returns true for this
8024 // SuffleVectorSDNode
8025 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8027 const X86Subtarget *Subtarget,
8028 SelectionDAG &DAG) {
8029 MVT VT = SVOp->getSimpleValueType(0);
8030 MVT EltVT = VT.getVectorElementType();
8031 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8032 Subtarget->hasInt256() && "Trying to lower a "
8033 "VECTOR_SHUFFLE to a Blend but "
8034 "with the wrong mask"));
8035 SDValue V1 = SVOp->getOperand(0);
8036 SDValue V2 = SVOp->getOperand(1);
8038 unsigned NumElems = VT.getVectorNumElements();
8040 // Convert i32 vectors to floating point if it is not AVX2.
8041 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8043 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8044 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8046 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8047 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8050 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8051 DAG.getConstant(MaskValue, MVT::i32));
8052 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8055 /// In vector type \p VT, return true if the element at index \p InputIdx
8056 /// falls on a different 128-bit lane than \p OutputIdx.
8057 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8058 unsigned OutputIdx) {
8059 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8060 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8063 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8064 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8065 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8066 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8068 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8069 SelectionDAG &DAG) {
8070 MVT VT = V1.getSimpleValueType();
8071 assert(VT.is128BitVector() || VT.is256BitVector());
8073 MVT EltVT = VT.getVectorElementType();
8074 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8075 unsigned NumElts = VT.getVectorNumElements();
8077 SmallVector<SDValue, 32> PshufbMask;
8078 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8079 int InputIdx = MaskVals[OutputIdx];
8080 unsigned InputByteIdx;
8082 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8083 InputByteIdx = 0x80;
8085 // Cross lane is not allowed.
8086 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8088 InputByteIdx = InputIdx * EltSizeInBytes;
8089 // Index is an byte offset within the 128-bit lane.
8090 InputByteIdx &= 0xf;
8093 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8094 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8095 if (InputByteIdx != 0x80)
8100 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8102 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8103 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8104 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8107 // v8i16 shuffles - Prefer shuffles in the following order:
8108 // 1. [all] pshuflw, pshufhw, optional move
8109 // 2. [ssse3] 1 x pshufb
8110 // 3. [ssse3] 2 x pshufb + 1 x por
8111 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8113 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8114 SelectionDAG &DAG) {
8115 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8116 SDValue V1 = SVOp->getOperand(0);
8117 SDValue V2 = SVOp->getOperand(1);
8119 SmallVector<int, 8> MaskVals;
8121 // Determine if more than 1 of the words in each of the low and high quadwords
8122 // of the result come from the same quadword of one of the two inputs. Undef
8123 // mask values count as coming from any quadword, for better codegen.
8125 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8126 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8127 unsigned LoQuad[] = { 0, 0, 0, 0 };
8128 unsigned HiQuad[] = { 0, 0, 0, 0 };
8129 // Indices of quads used.
8130 std::bitset<4> InputQuads;
8131 for (unsigned i = 0; i < 8; ++i) {
8132 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8133 int EltIdx = SVOp->getMaskElt(i);
8134 MaskVals.push_back(EltIdx);
8143 InputQuads.set(EltIdx / 4);
8146 int BestLoQuad = -1;
8147 unsigned MaxQuad = 1;
8148 for (unsigned i = 0; i < 4; ++i) {
8149 if (LoQuad[i] > MaxQuad) {
8151 MaxQuad = LoQuad[i];
8155 int BestHiQuad = -1;
8157 for (unsigned i = 0; i < 4; ++i) {
8158 if (HiQuad[i] > MaxQuad) {
8160 MaxQuad = HiQuad[i];
8164 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8165 // of the two input vectors, shuffle them into one input vector so only a
8166 // single pshufb instruction is necessary. If there are more than 2 input
8167 // quads, disable the next transformation since it does not help SSSE3.
8168 bool V1Used = InputQuads[0] || InputQuads[1];
8169 bool V2Used = InputQuads[2] || InputQuads[3];
8170 if (Subtarget->hasSSSE3()) {
8171 if (InputQuads.count() == 2 && V1Used && V2Used) {
8172 BestLoQuad = InputQuads[0] ? 0 : 1;
8173 BestHiQuad = InputQuads[2] ? 2 : 3;
8175 if (InputQuads.count() > 2) {
8181 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8182 // the shuffle mask. If a quad is scored as -1, that means that it contains
8183 // words from all 4 input quadwords.
8185 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8187 BestLoQuad < 0 ? 0 : BestLoQuad,
8188 BestHiQuad < 0 ? 1 : BestHiQuad
8190 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8191 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8192 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8193 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8195 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8196 // source words for the shuffle, to aid later transformations.
8197 bool AllWordsInNewV = true;
8198 bool InOrder[2] = { true, true };
8199 for (unsigned i = 0; i != 8; ++i) {
8200 int idx = MaskVals[i];
8202 InOrder[i/4] = false;
8203 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8205 AllWordsInNewV = false;
8209 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8210 if (AllWordsInNewV) {
8211 for (int i = 0; i != 8; ++i) {
8212 int idx = MaskVals[i];
8215 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8216 if ((idx != i) && idx < 4)
8218 if ((idx != i) && idx > 3)
8227 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8228 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8229 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8230 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8231 unsigned TargetMask = 0;
8232 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8233 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8234 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8235 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8236 getShufflePSHUFLWImmediate(SVOp);
8237 V1 = NewV.getOperand(0);
8238 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8242 // Promote splats to a larger type which usually leads to more efficient code.
8243 // FIXME: Is this true if pshufb is available?
8244 if (SVOp->isSplat())
8245 return PromoteSplat(SVOp, DAG);
8247 // If we have SSSE3, and all words of the result are from 1 input vector,
8248 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8249 // is present, fall back to case 4.
8250 if (Subtarget->hasSSSE3()) {
8251 SmallVector<SDValue,16> pshufbMask;
8253 // If we have elements from both input vectors, set the high bit of the
8254 // shuffle mask element to zero out elements that come from V2 in the V1
8255 // mask, and elements that come from V1 in the V2 mask, so that the two
8256 // results can be OR'd together.
8257 bool TwoInputs = V1Used && V2Used;
8258 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8260 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8262 // Calculate the shuffle mask for the second input, shuffle it, and
8263 // OR it with the first shuffled input.
8264 CommuteVectorShuffleMask(MaskVals, 8);
8265 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8266 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8267 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8270 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8271 // and update MaskVals with new element order.
8272 std::bitset<8> InOrder;
8273 if (BestLoQuad >= 0) {
8274 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8275 for (int i = 0; i != 4; ++i) {
8276 int idx = MaskVals[i];
8279 } else if ((idx / 4) == BestLoQuad) {
8284 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8287 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8289 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8291 getShufflePSHUFLWImmediate(SVOp), DAG);
8295 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8296 // and update MaskVals with the new element order.
8297 if (BestHiQuad >= 0) {
8298 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8299 for (unsigned i = 4; i != 8; ++i) {
8300 int idx = MaskVals[i];
8303 } else if ((idx / 4) == BestHiQuad) {
8304 MaskV[i] = (idx & 3) + 4;
8308 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8311 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8313 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8315 getShufflePSHUFHWImmediate(SVOp), DAG);
8319 // In case BestHi & BestLo were both -1, which means each quadword has a word
8320 // from each of the four input quadwords, calculate the InOrder bitvector now
8321 // before falling through to the insert/extract cleanup.
8322 if (BestLoQuad == -1 && BestHiQuad == -1) {
8324 for (int i = 0; i != 8; ++i)
8325 if (MaskVals[i] < 0 || MaskVals[i] == i)
8329 // The other elements are put in the right place using pextrw and pinsrw.
8330 for (unsigned i = 0; i != 8; ++i) {
8333 int EltIdx = MaskVals[i];
8336 SDValue ExtOp = (EltIdx < 8) ?
8337 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8338 DAG.getIntPtrConstant(EltIdx)) :
8339 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8340 DAG.getIntPtrConstant(EltIdx - 8));
8341 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8342 DAG.getIntPtrConstant(i));
8347 /// \brief v16i16 shuffles
8349 /// FIXME: We only support generation of a single pshufb currently. We can
8350 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8351 /// well (e.g 2 x pshufb + 1 x por).
8353 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8355 SDValue V1 = SVOp->getOperand(0);
8356 SDValue V2 = SVOp->getOperand(1);
8359 if (V2.getOpcode() != ISD::UNDEF)
8362 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8363 return getPSHUFB(MaskVals, V1, dl, DAG);
8366 // v16i8 shuffles - Prefer shuffles in the following order:
8367 // 1. [ssse3] 1 x pshufb
8368 // 2. [ssse3] 2 x pshufb + 1 x por
8369 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8370 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8371 const X86Subtarget* Subtarget,
8372 SelectionDAG &DAG) {
8373 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8374 SDValue V1 = SVOp->getOperand(0);
8375 SDValue V2 = SVOp->getOperand(1);
8377 ArrayRef<int> MaskVals = SVOp->getMask();
8379 // Promote splats to a larger type which usually leads to more efficient code.
8380 // FIXME: Is this true if pshufb is available?
8381 if (SVOp->isSplat())
8382 return PromoteSplat(SVOp, DAG);
8384 // If we have SSSE3, case 1 is generated when all result bytes come from
8385 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8386 // present, fall back to case 3.
8388 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8389 if (Subtarget->hasSSSE3()) {
8390 SmallVector<SDValue,16> pshufbMask;
8392 // If all result elements are from one input vector, then only translate
8393 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8395 // Otherwise, we have elements from both input vectors, and must zero out
8396 // elements that come from V2 in the first mask, and V1 in the second mask
8397 // so that we can OR them together.
8398 for (unsigned i = 0; i != 16; ++i) {
8399 int EltIdx = MaskVals[i];
8400 if (EltIdx < 0 || EltIdx >= 16)
8402 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8404 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8405 DAG.getNode(ISD::BUILD_VECTOR, dl,
8406 MVT::v16i8, pshufbMask));
8408 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8409 // the 2nd operand if it's undefined or zero.
8410 if (V2.getOpcode() == ISD::UNDEF ||
8411 ISD::isBuildVectorAllZeros(V2.getNode()))
8414 // Calculate the shuffle mask for the second input, shuffle it, and
8415 // OR it with the first shuffled input.
8417 for (unsigned i = 0; i != 16; ++i) {
8418 int EltIdx = MaskVals[i];
8419 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8420 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8422 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8423 DAG.getNode(ISD::BUILD_VECTOR, dl,
8424 MVT::v16i8, pshufbMask));
8425 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8428 // No SSSE3 - Calculate in place words and then fix all out of place words
8429 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8430 // the 16 different words that comprise the two doublequadword input vectors.
8431 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8432 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8434 for (int i = 0; i != 8; ++i) {
8435 int Elt0 = MaskVals[i*2];
8436 int Elt1 = MaskVals[i*2+1];
8438 // This word of the result is all undef, skip it.
8439 if (Elt0 < 0 && Elt1 < 0)
8442 // This word of the result is already in the correct place, skip it.
8443 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8446 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8447 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8450 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8451 // using a single extract together, load it and store it.
8452 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8453 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8454 DAG.getIntPtrConstant(Elt1 / 2));
8455 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8456 DAG.getIntPtrConstant(i));
8460 // If Elt1 is defined, extract it from the appropriate source. If the
8461 // source byte is not also odd, shift the extracted word left 8 bits
8462 // otherwise clear the bottom 8 bits if we need to do an or.
8464 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8465 DAG.getIntPtrConstant(Elt1 / 2));
8466 if ((Elt1 & 1) == 0)
8467 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8469 TLI.getShiftAmountTy(InsElt.getValueType())));
8471 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8472 DAG.getConstant(0xFF00, MVT::i16));
8474 // If Elt0 is defined, extract it from the appropriate source. If the
8475 // source byte is not also even, shift the extracted word right 8 bits. If
8476 // Elt1 was also defined, OR the extracted values together before
8477 // inserting them in the result.
8479 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8480 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8481 if ((Elt0 & 1) != 0)
8482 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8484 TLI.getShiftAmountTy(InsElt0.getValueType())));
8486 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8487 DAG.getConstant(0x00FF, MVT::i16));
8488 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8491 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8492 DAG.getIntPtrConstant(i));
8494 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8497 // v32i8 shuffles - Translate to VPSHUFB if possible.
8499 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8500 const X86Subtarget *Subtarget,
8501 SelectionDAG &DAG) {
8502 MVT VT = SVOp->getSimpleValueType(0);
8503 SDValue V1 = SVOp->getOperand(0);
8504 SDValue V2 = SVOp->getOperand(1);
8506 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8508 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8509 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8510 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8512 // VPSHUFB may be generated if
8513 // (1) one of input vector is undefined or zeroinitializer.
8514 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8515 // And (2) the mask indexes don't cross the 128-bit lane.
8516 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8517 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8520 if (V1IsAllZero && !V2IsAllZero) {
8521 CommuteVectorShuffleMask(MaskVals, 32);
8524 return getPSHUFB(MaskVals, V1, dl, DAG);
8527 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8528 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8529 /// done when every pair / quad of shuffle mask elements point to elements in
8530 /// the right sequence. e.g.
8531 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8533 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8534 SelectionDAG &DAG) {
8535 MVT VT = SVOp->getSimpleValueType(0);
8537 unsigned NumElems = VT.getVectorNumElements();
8540 switch (VT.SimpleTy) {
8541 default: llvm_unreachable("Unexpected!");
8544 return SDValue(SVOp, 0);
8545 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8546 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8547 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8548 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8549 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8550 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8553 SmallVector<int, 8> MaskVec;
8554 for (unsigned i = 0; i != NumElems; i += Scale) {
8556 for (unsigned j = 0; j != Scale; ++j) {
8557 int EltIdx = SVOp->getMaskElt(i+j);
8561 StartIdx = (EltIdx / Scale);
8562 if (EltIdx != (int)(StartIdx*Scale + j))
8565 MaskVec.push_back(StartIdx);
8568 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8569 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8570 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8573 /// getVZextMovL - Return a zero-extending vector move low node.
8575 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8576 SDValue SrcOp, SelectionDAG &DAG,
8577 const X86Subtarget *Subtarget, SDLoc dl) {
8578 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8579 LoadSDNode *LD = nullptr;
8580 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8581 LD = dyn_cast<LoadSDNode>(SrcOp);
8583 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8585 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8586 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8587 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8588 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8589 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8591 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8592 return DAG.getNode(ISD::BITCAST, dl, VT,
8593 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8594 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8602 return DAG.getNode(ISD::BITCAST, dl, VT,
8603 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8604 DAG.getNode(ISD::BITCAST, dl,
8608 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8609 /// which could not be matched by any known target speficic shuffle
8611 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8613 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8614 if (NewOp.getNode())
8617 MVT VT = SVOp->getSimpleValueType(0);
8619 unsigned NumElems = VT.getVectorNumElements();
8620 unsigned NumLaneElems = NumElems / 2;
8623 MVT EltVT = VT.getVectorElementType();
8624 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8627 SmallVector<int, 16> Mask;
8628 for (unsigned l = 0; l < 2; ++l) {
8629 // Build a shuffle mask for the output, discovering on the fly which
8630 // input vectors to use as shuffle operands (recorded in InputUsed).
8631 // If building a suitable shuffle vector proves too hard, then bail
8632 // out with UseBuildVector set.
8633 bool UseBuildVector = false;
8634 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8635 unsigned LaneStart = l * NumLaneElems;
8636 for (unsigned i = 0; i != NumLaneElems; ++i) {
8637 // The mask element. This indexes into the input.
8638 int Idx = SVOp->getMaskElt(i+LaneStart);
8640 // the mask element does not index into any input vector.
8645 // The input vector this mask element indexes into.
8646 int Input = Idx / NumLaneElems;
8648 // Turn the index into an offset from the start of the input vector.
8649 Idx -= Input * NumLaneElems;
8651 // Find or create a shuffle vector operand to hold this input.
8653 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8654 if (InputUsed[OpNo] == Input)
8655 // This input vector is already an operand.
8657 if (InputUsed[OpNo] < 0) {
8658 // Create a new operand for this input vector.
8659 InputUsed[OpNo] = Input;
8664 if (OpNo >= array_lengthof(InputUsed)) {
8665 // More than two input vectors used! Give up on trying to create a
8666 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8667 UseBuildVector = true;
8671 // Add the mask index for the new shuffle vector.
8672 Mask.push_back(Idx + OpNo * NumLaneElems);
8675 if (UseBuildVector) {
8676 SmallVector<SDValue, 16> SVOps;
8677 for (unsigned i = 0; i != NumLaneElems; ++i) {
8678 // The mask element. This indexes into the input.
8679 int Idx = SVOp->getMaskElt(i+LaneStart);
8681 SVOps.push_back(DAG.getUNDEF(EltVT));
8685 // The input vector this mask element indexes into.
8686 int Input = Idx / NumElems;
8688 // Turn the index into an offset from the start of the input vector.
8689 Idx -= Input * NumElems;
8691 // Extract the vector element by hand.
8692 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
8693 SVOp->getOperand(Input),
8694 DAG.getIntPtrConstant(Idx)));
8697 // Construct the output using a BUILD_VECTOR.
8698 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8699 } else if (InputUsed[0] < 0) {
8700 // No input vectors were used! The result is undefined.
8701 Output[l] = DAG.getUNDEF(NVT);
8703 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
8704 (InputUsed[0] % 2) * NumLaneElems,
8706 // If only one input was used, use an undefined vector for the other.
8707 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
8708 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
8709 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
8710 // At least one input vector was used. Create a new shuffle vector.
8711 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8717 // Concatenate the result back
8718 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
8721 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
8722 /// 4 elements, and match them with several different shuffle types.
8724 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8725 SDValue V1 = SVOp->getOperand(0);
8726 SDValue V2 = SVOp->getOperand(1);
8728 MVT VT = SVOp->getSimpleValueType(0);
8730 assert(VT.is128BitVector() && "Unsupported vector size");
8732 std::pair<int, int> Locs[4];
8733 int Mask1[] = { -1, -1, -1, -1 };
8734 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
8738 for (unsigned i = 0; i != 4; ++i) {
8739 int Idx = PermMask[i];
8741 Locs[i] = std::make_pair(-1, -1);
8743 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
8745 Locs[i] = std::make_pair(0, NumLo);
8749 Locs[i] = std::make_pair(1, NumHi);
8751 Mask1[2+NumHi] = Idx;
8757 if (NumLo <= 2 && NumHi <= 2) {
8758 // If no more than two elements come from either vector. This can be
8759 // implemented with two shuffles. First shuffle gather the elements.
8760 // The second shuffle, which takes the first shuffle as both of its
8761 // vector operands, put the elements into the right order.
8762 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8764 int Mask2[] = { -1, -1, -1, -1 };
8766 for (unsigned i = 0; i != 4; ++i)
8767 if (Locs[i].first != -1) {
8768 unsigned Idx = (i < 2) ? 0 : 4;
8769 Idx += Locs[i].first * 2 + Locs[i].second;
8773 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
8776 if (NumLo == 3 || NumHi == 3) {
8777 // Otherwise, we must have three elements from one vector, call it X, and
8778 // one element from the other, call it Y. First, use a shufps to build an
8779 // intermediate vector with the one element from Y and the element from X
8780 // that will be in the same half in the final destination (the indexes don't
8781 // matter). Then, use a shufps to build the final vector, taking the half
8782 // containing the element from Y from the intermediate, and the other half
8785 // Normalize it so the 3 elements come from V1.
8786 CommuteVectorShuffleMask(PermMask, 4);
8790 // Find the element from V2.
8792 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
8793 int Val = PermMask[HiIndex];
8800 Mask1[0] = PermMask[HiIndex];
8802 Mask1[2] = PermMask[HiIndex^1];
8804 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8807 Mask1[0] = PermMask[0];
8808 Mask1[1] = PermMask[1];
8809 Mask1[2] = HiIndex & 1 ? 6 : 4;
8810 Mask1[3] = HiIndex & 1 ? 4 : 6;
8811 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8814 Mask1[0] = HiIndex & 1 ? 2 : 0;
8815 Mask1[1] = HiIndex & 1 ? 0 : 2;
8816 Mask1[2] = PermMask[2];
8817 Mask1[3] = PermMask[3];
8822 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
8825 // Break it into (shuffle shuffle_hi, shuffle_lo).
8826 int LoMask[] = { -1, -1, -1, -1 };
8827 int HiMask[] = { -1, -1, -1, -1 };
8829 int *MaskPtr = LoMask;
8830 unsigned MaskIdx = 0;
8833 for (unsigned i = 0; i != 4; ++i) {
8840 int Idx = PermMask[i];
8842 Locs[i] = std::make_pair(-1, -1);
8843 } else if (Idx < 4) {
8844 Locs[i] = std::make_pair(MaskIdx, LoIdx);
8845 MaskPtr[LoIdx] = Idx;
8848 Locs[i] = std::make_pair(MaskIdx, HiIdx);
8849 MaskPtr[HiIdx] = Idx;
8854 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
8855 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
8856 int MaskOps[] = { -1, -1, -1, -1 };
8857 for (unsigned i = 0; i != 4; ++i)
8858 if (Locs[i].first != -1)
8859 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
8860 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
8863 static bool MayFoldVectorLoad(SDValue V) {
8864 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
8865 V = V.getOperand(0);
8867 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
8868 V = V.getOperand(0);
8869 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
8870 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
8871 // BUILD_VECTOR (load), undef
8872 V = V.getOperand(0);
8874 return MayFoldLoad(V);
8878 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
8879 MVT VT = Op.getSimpleValueType();
8881 // Canonizalize to v2f64.
8882 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
8883 return DAG.getNode(ISD::BITCAST, dl, VT,
8884 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
8889 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
8891 SDValue V1 = Op.getOperand(0);
8892 SDValue V2 = Op.getOperand(1);
8893 MVT VT = Op.getSimpleValueType();
8895 assert(VT != MVT::v2i64 && "unsupported shuffle type");
8897 if (HasSSE2 && VT == MVT::v2f64)
8898 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
8900 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
8901 return DAG.getNode(ISD::BITCAST, dl, VT,
8902 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
8903 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
8904 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
8908 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
8909 SDValue V1 = Op.getOperand(0);
8910 SDValue V2 = Op.getOperand(1);
8911 MVT VT = Op.getSimpleValueType();
8913 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
8914 "unsupported shuffle type");
8916 if (V2.getOpcode() == ISD::UNDEF)
8920 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
8924 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
8925 SDValue V1 = Op.getOperand(0);
8926 SDValue V2 = Op.getOperand(1);
8927 MVT VT = Op.getSimpleValueType();
8928 unsigned NumElems = VT.getVectorNumElements();
8930 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
8931 // operand of these instructions is only memory, so check if there's a
8932 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
8934 bool CanFoldLoad = false;
8936 // Trivial case, when V2 comes from a load.
8937 if (MayFoldVectorLoad(V2))
8940 // When V1 is a load, it can be folded later into a store in isel, example:
8941 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
8943 // (MOVLPSmr addr:$src1, VR128:$src2)
8944 // So, recognize this potential and also use MOVLPS or MOVLPD
8945 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
8948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8950 if (HasSSE2 && NumElems == 2)
8951 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
8954 // If we don't care about the second element, proceed to use movss.
8955 if (SVOp->getMaskElt(1) != -1)
8956 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
8959 // movl and movlp will both match v2i64, but v2i64 is never matched by
8960 // movl earlier because we make it strict to avoid messing with the movlp load
8961 // folding logic (see the code above getMOVLP call). Match it here then,
8962 // this is horrible, but will stay like this until we move all shuffle
8963 // matching to x86 specific nodes. Note that for the 1st condition all
8964 // types are matched with movsd.
8966 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
8967 // as to remove this logic from here, as much as possible
8968 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
8969 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
8970 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
8973 assert(VT != MVT::v4i32 && "unsupported shuffle type");
8975 // Invert the operand order and use SHUFPS to match it.
8976 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
8977 getShuffleSHUFImmediate(SVOp), DAG);
8980 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
8981 SelectionDAG &DAG) {
8983 MVT VT = Load->getSimpleValueType(0);
8984 MVT EVT = VT.getVectorElementType();
8985 SDValue Addr = Load->getOperand(1);
8986 SDValue NewAddr = DAG.getNode(
8987 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
8988 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
8991 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
8992 DAG.getMachineFunction().getMachineMemOperand(
8993 Load->getMemOperand(), 0, EVT.getStoreSize()));
8997 // It is only safe to call this function if isINSERTPSMask is true for
8998 // this shufflevector mask.
8999 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9000 SelectionDAG &DAG) {
9001 // Generate an insertps instruction when inserting an f32 from memory onto a
9002 // v4f32 or when copying a member from one v4f32 to another.
9003 // We also use it for transferring i32 from one register to another,
9004 // since it simply copies the same bits.
9005 // If we're transferring an i32 from memory to a specific element in a
9006 // register, we output a generic DAG that will match the PINSRD
9008 MVT VT = SVOp->getSimpleValueType(0);
9009 MVT EVT = VT.getVectorElementType();
9010 SDValue V1 = SVOp->getOperand(0);
9011 SDValue V2 = SVOp->getOperand(1);
9012 auto Mask = SVOp->getMask();
9013 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9014 "unsupported vector type for insertps/pinsrd");
9016 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9017 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9018 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9026 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9029 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9030 "More than one element from V1 and from V2, or no elements from one "
9031 "of the vectors. This case should not have returned true from "
9036 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9039 unsigned SrcIndex = Mask[DestIndex] % 4;
9040 if (MayFoldLoad(From)) {
9041 // Trivial case, when From comes from a load and is only used by the
9042 // shuffle. Make it use insertps from the vector that we need from that
9045 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9046 if (!NewLoad.getNode())
9049 if (EVT == MVT::f32) {
9050 // Create this as a scalar to vector to match the instruction pattern.
9051 SDValue LoadScalarToVector =
9052 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9053 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9054 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9056 } else { // EVT == MVT::i32
9057 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9058 // instruction, to match the PINSRD instruction, which loads an i32 to a
9059 // certain vector element.
9060 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9061 DAG.getConstant(DestIndex, MVT::i32));
9065 // Vector-element-to-vector
9066 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9067 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9070 // Reduce a vector shuffle to zext.
9071 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9072 SelectionDAG &DAG) {
9073 // PMOVZX is only available from SSE41.
9074 if (!Subtarget->hasSSE41())
9077 MVT VT = Op.getSimpleValueType();
9079 // Only AVX2 support 256-bit vector integer extending.
9080 if (!Subtarget->hasInt256() && VT.is256BitVector())
9083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9085 SDValue V1 = Op.getOperand(0);
9086 SDValue V2 = Op.getOperand(1);
9087 unsigned NumElems = VT.getVectorNumElements();
9089 // Extending is an unary operation and the element type of the source vector
9090 // won't be equal to or larger than i64.
9091 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9092 VT.getVectorElementType() == MVT::i64)
9095 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9096 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9097 while ((1U << Shift) < NumElems) {
9098 if (SVOp->getMaskElt(1U << Shift) == 1)
9101 // The maximal ratio is 8, i.e. from i8 to i64.
9106 // Check the shuffle mask.
9107 unsigned Mask = (1U << Shift) - 1;
9108 for (unsigned i = 0; i != NumElems; ++i) {
9109 int EltIdx = SVOp->getMaskElt(i);
9110 if ((i & Mask) != 0 && EltIdx != -1)
9112 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9116 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9117 MVT NeVT = MVT::getIntegerVT(NBits);
9118 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9120 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9123 // Simplify the operand as it's prepared to be fed into shuffle.
9124 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9125 if (V1.getOpcode() == ISD::BITCAST &&
9126 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9127 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9128 V1.getOperand(0).getOperand(0)
9129 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9130 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9131 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9132 ConstantSDNode *CIdx =
9133 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9134 // If it's foldable, i.e. normal load with single use, we will let code
9135 // selection to fold it. Otherwise, we will short the conversion sequence.
9136 if (CIdx && CIdx->getZExtValue() == 0 &&
9137 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9138 MVT FullVT = V.getSimpleValueType();
9139 MVT V1VT = V1.getSimpleValueType();
9140 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9141 // The "ext_vec_elt" node is wider than the result node.
9142 // In this case we should extract subvector from V.
9143 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9144 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9145 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9146 FullVT.getVectorNumElements()/Ratio);
9147 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9148 DAG.getIntPtrConstant(0));
9150 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9154 return DAG.getNode(ISD::BITCAST, DL, VT,
9155 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9158 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9159 SelectionDAG &DAG) {
9160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9161 MVT VT = Op.getSimpleValueType();
9163 SDValue V1 = Op.getOperand(0);
9164 SDValue V2 = Op.getOperand(1);
9166 if (isZeroShuffle(SVOp))
9167 return getZeroVector(VT, Subtarget, DAG, dl);
9169 // Handle splat operations
9170 if (SVOp->isSplat()) {
9171 // Use vbroadcast whenever the splat comes from a foldable load
9172 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9173 if (Broadcast.getNode())
9177 // Check integer expanding shuffles.
9178 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9179 if (NewOp.getNode())
9182 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9184 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9186 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9187 if (NewOp.getNode())
9188 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9189 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9190 // FIXME: Figure out a cleaner way to do this.
9191 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9192 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9193 if (NewOp.getNode()) {
9194 MVT NewVT = NewOp.getSimpleValueType();
9195 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9196 NewVT, true, false))
9197 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9200 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9201 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9202 if (NewOp.getNode()) {
9203 MVT NewVT = NewOp.getSimpleValueType();
9204 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9205 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9214 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9216 SDValue V1 = Op.getOperand(0);
9217 SDValue V2 = Op.getOperand(1);
9218 MVT VT = Op.getSimpleValueType();
9220 unsigned NumElems = VT.getVectorNumElements();
9221 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9222 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9223 bool V1IsSplat = false;
9224 bool V2IsSplat = false;
9225 bool HasSSE2 = Subtarget->hasSSE2();
9226 bool HasFp256 = Subtarget->hasFp256();
9227 bool HasInt256 = Subtarget->hasInt256();
9228 MachineFunction &MF = DAG.getMachineFunction();
9229 bool OptForSize = MF.getFunction()->getAttributes().
9230 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9232 // Check if we should use the experimental vector shuffle lowering. If so,
9233 // delegate completely to that code path.
9234 if (ExperimentalVectorShuffleLowering)
9235 return lowerVectorShuffle(Op, Subtarget, DAG);
9237 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9239 if (V1IsUndef && V2IsUndef)
9240 return DAG.getUNDEF(VT);
9242 // When we create a shuffle node we put the UNDEF node to second operand,
9243 // but in some cases the first operand may be transformed to UNDEF.
9244 // In this case we should just commute the node.
9246 return CommuteVectorShuffle(SVOp, DAG);
9248 // Vector shuffle lowering takes 3 steps:
9250 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9251 // narrowing and commutation of operands should be handled.
9252 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9254 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9255 // so the shuffle can be broken into other shuffles and the legalizer can
9256 // try the lowering again.
9258 // The general idea is that no vector_shuffle operation should be left to
9259 // be matched during isel, all of them must be converted to a target specific
9262 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9263 // narrowing and commutation of operands should be handled. The actual code
9264 // doesn't include all of those, work in progress...
9265 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9266 if (NewOp.getNode())
9269 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9271 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9272 // unpckh_undef). Only use pshufd if speed is more important than size.
9273 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9274 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9275 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9276 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9278 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9279 V2IsUndef && MayFoldVectorLoad(V1))
9280 return getMOVDDup(Op, dl, V1, DAG);
9282 if (isMOVHLPS_v_undef_Mask(M, VT))
9283 return getMOVHighToLow(Op, dl, DAG);
9285 // Use to match splats
9286 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9287 (VT == MVT::v2f64 || VT == MVT::v2i64))
9288 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9290 if (isPSHUFDMask(M, VT)) {
9291 // The actual implementation will match the mask in the if above and then
9292 // during isel it can match several different instructions, not only pshufd
9293 // as its name says, sad but true, emulate the behavior for now...
9294 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9295 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9297 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9299 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9300 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9302 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9303 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9306 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9310 if (isPALIGNRMask(M, VT, Subtarget))
9311 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9312 getShufflePALIGNRImmediate(SVOp),
9315 // Check if this can be converted into a logical shift.
9316 bool isLeft = false;
9319 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9320 if (isShift && ShVal.hasOneUse()) {
9321 // If the shifted value has multiple uses, it may be cheaper to use
9322 // v_set0 + movlhps or movhlps, etc.
9323 MVT EltVT = VT.getVectorElementType();
9324 ShAmt *= EltVT.getSizeInBits();
9325 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9328 if (isMOVLMask(M, VT)) {
9329 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9330 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9331 if (!isMOVLPMask(M, VT)) {
9332 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9333 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9335 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9336 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9340 // FIXME: fold these into legal mask.
9341 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9342 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9344 if (isMOVHLPSMask(M, VT))
9345 return getMOVHighToLow(Op, dl, DAG);
9347 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9348 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9350 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9351 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9353 if (isMOVLPMask(M, VT))
9354 return getMOVLP(Op, dl, DAG, HasSSE2);
9356 if (ShouldXformToMOVHLPS(M, VT) ||
9357 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9358 return CommuteVectorShuffle(SVOp, DAG);
9361 // No better options. Use a vshldq / vsrldq.
9362 MVT EltVT = VT.getVectorElementType();
9363 ShAmt *= EltVT.getSizeInBits();
9364 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9367 bool Commuted = false;
9368 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9369 // 1,1,1,1 -> v8i16 though.
9370 BitVector UndefElements;
9371 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9372 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9374 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9375 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9378 // Canonicalize the splat or undef, if present, to be on the RHS.
9379 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9380 CommuteVectorShuffleMask(M, NumElems);
9382 std::swap(V1IsSplat, V2IsSplat);
9386 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9387 // Shuffling low element of v1 into undef, just return v1.
9390 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9391 // the instruction selector will not match, so get a canonical MOVL with
9392 // swapped operands to undo the commute.
9393 return getMOVL(DAG, dl, VT, V2, V1);
9396 if (isUNPCKLMask(M, VT, HasInt256))
9397 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9399 if (isUNPCKHMask(M, VT, HasInt256))
9400 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9403 // Normalize mask so all entries that point to V2 points to its first
9404 // element then try to match unpck{h|l} again. If match, return a
9405 // new vector_shuffle with the corrected mask.p
9406 SmallVector<int, 8> NewMask(M.begin(), M.end());
9407 NormalizeMask(NewMask, NumElems);
9408 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9409 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9410 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9411 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9415 // Commute is back and try unpck* again.
9416 // FIXME: this seems wrong.
9417 CommuteVectorShuffleMask(M, NumElems);
9419 std::swap(V1IsSplat, V2IsSplat);
9421 if (isUNPCKLMask(M, VT, HasInt256))
9422 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9424 if (isUNPCKHMask(M, VT, HasInt256))
9425 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9428 // Normalize the node to match x86 shuffle ops if needed
9429 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9430 return CommuteVectorShuffle(SVOp, DAG);
9432 // The checks below are all present in isShuffleMaskLegal, but they are
9433 // inlined here right now to enable us to directly emit target specific
9434 // nodes, and remove one by one until they don't return Op anymore.
9436 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9437 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9438 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9439 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9442 if (isPSHUFHWMask(M, VT, HasInt256))
9443 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9444 getShufflePSHUFHWImmediate(SVOp),
9447 if (isPSHUFLWMask(M, VT, HasInt256))
9448 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9449 getShufflePSHUFLWImmediate(SVOp),
9453 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9455 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9457 if (isSHUFPMask(M, VT))
9458 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9459 getShuffleSHUFImmediate(SVOp), DAG);
9461 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9462 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9463 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9464 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9466 //===--------------------------------------------------------------------===//
9467 // Generate target specific nodes for 128 or 256-bit shuffles only
9468 // supported in the AVX instruction set.
9471 // Handle VMOVDDUPY permutations
9472 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9473 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9475 // Handle VPERMILPS/D* permutations
9476 if (isVPERMILPMask(M, VT)) {
9477 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9478 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9479 getShuffleSHUFImmediate(SVOp), DAG);
9480 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9481 getShuffleSHUFImmediate(SVOp), DAG);
9485 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9486 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9487 Idx*(NumElems/2), DAG, dl);
9489 // Handle VPERM2F128/VPERM2I128 permutations
9490 if (isVPERM2X128Mask(M, VT, HasFp256))
9491 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9492 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9494 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9495 return getINSERTPS(SVOp, dl, DAG);
9498 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9499 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9501 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9502 VT.is512BitVector()) {
9503 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9504 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9505 SmallVector<SDValue, 16> permclMask;
9506 for (unsigned i = 0; i != NumElems; ++i) {
9507 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9510 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9512 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9513 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9514 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9515 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9516 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9519 //===--------------------------------------------------------------------===//
9520 // Since no target specific shuffle was selected for this generic one,
9521 // lower it into other known shuffles. FIXME: this isn't true yet, but
9522 // this is the plan.
9525 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9526 if (VT == MVT::v8i16) {
9527 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9528 if (NewOp.getNode())
9532 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9533 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9534 if (NewOp.getNode())
9538 if (VT == MVT::v16i8) {
9539 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9540 if (NewOp.getNode())
9544 if (VT == MVT::v32i8) {
9545 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9546 if (NewOp.getNode())
9550 // Handle all 128-bit wide vectors with 4 elements, and match them with
9551 // several different shuffle types.
9552 if (NumElems == 4 && VT.is128BitVector())
9553 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9555 // Handle general 256-bit shuffles
9556 if (VT.is256BitVector())
9557 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9562 // This function assumes its argument is a BUILD_VECTOR of constants or
9563 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9565 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9566 unsigned &MaskValue) {
9568 unsigned NumElems = BuildVector->getNumOperands();
9569 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9570 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9571 unsigned NumElemsInLane = NumElems / NumLanes;
9573 // Blend for v16i16 should be symetric for the both lanes.
9574 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9575 SDValue EltCond = BuildVector->getOperand(i);
9576 SDValue SndLaneEltCond =
9577 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9579 int Lane1Cond = -1, Lane2Cond = -1;
9580 if (isa<ConstantSDNode>(EltCond))
9581 Lane1Cond = !isZero(EltCond);
9582 if (isa<ConstantSDNode>(SndLaneEltCond))
9583 Lane2Cond = !isZero(SndLaneEltCond);
9585 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9586 // Lane1Cond != 0, means we want the first argument.
9587 // Lane1Cond == 0, means we want the second argument.
9588 // The encoding of this argument is 0 for the first argument, 1
9589 // for the second. Therefore, invert the condition.
9590 MaskValue |= !Lane1Cond << i;
9591 else if (Lane1Cond < 0)
9592 MaskValue |= !Lane2Cond << i;
9599 // Try to lower a vselect node into a simple blend instruction.
9600 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9601 SelectionDAG &DAG) {
9602 SDValue Cond = Op.getOperand(0);
9603 SDValue LHS = Op.getOperand(1);
9604 SDValue RHS = Op.getOperand(2);
9606 MVT VT = Op.getSimpleValueType();
9607 MVT EltVT = VT.getVectorElementType();
9608 unsigned NumElems = VT.getVectorNumElements();
9610 // There is no blend with immediate in AVX-512.
9611 if (VT.is512BitVector())
9614 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9616 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9619 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9622 // Check the mask for BLEND and build the value.
9623 unsigned MaskValue = 0;
9624 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9627 // Convert i32 vectors to floating point if it is not AVX2.
9628 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9630 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9631 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9633 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9634 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9637 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9638 DAG.getConstant(MaskValue, MVT::i32));
9639 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9642 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9643 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9644 if (BlendOp.getNode())
9647 // Some types for vselect were previously set to Expand, not Legal or
9648 // Custom. Return an empty SDValue so we fall-through to Expand, after
9649 // the Custom lowering phase.
9650 MVT VT = Op.getSimpleValueType();
9651 switch (VT.SimpleTy) {
9659 // We couldn't create a "Blend with immediate" node.
9660 // This node should still be legal, but we'll have to emit a blendv*
9665 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9666 MVT VT = Op.getSimpleValueType();
9669 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
9672 if (VT.getSizeInBits() == 8) {
9673 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
9674 Op.getOperand(0), Op.getOperand(1));
9675 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9676 DAG.getValueType(VT));
9677 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9680 if (VT.getSizeInBits() == 16) {
9681 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9682 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
9684 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9685 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9686 DAG.getNode(ISD::BITCAST, dl,
9690 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
9691 Op.getOperand(0), Op.getOperand(1));
9692 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9693 DAG.getValueType(VT));
9694 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9697 if (VT == MVT::f32) {
9698 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
9699 // the result back to FR32 register. It's only worth matching if the
9700 // result has a single use which is a store or a bitcast to i32. And in
9701 // the case of a store, it's not worth it if the index is a constant 0,
9702 // because a MOVSSmr can be used instead, which is smaller and faster.
9703 if (!Op.hasOneUse())
9705 SDNode *User = *Op.getNode()->use_begin();
9706 if ((User->getOpcode() != ISD::STORE ||
9707 (isa<ConstantSDNode>(Op.getOperand(1)) &&
9708 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
9709 (User->getOpcode() != ISD::BITCAST ||
9710 User->getValueType(0) != MVT::i32))
9712 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9713 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
9716 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
9719 if (VT == MVT::i32 || VT == MVT::i64) {
9720 // ExtractPS/pextrq works with constant index.
9721 if (isa<ConstantSDNode>(Op.getOperand(1)))
9727 /// Extract one bit from mask vector, like v16i1 or v8i1.
9728 /// AVX-512 feature.
9730 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
9731 SDValue Vec = Op.getOperand(0);
9733 MVT VecVT = Vec.getSimpleValueType();
9734 SDValue Idx = Op.getOperand(1);
9735 MVT EltVT = Op.getSimpleValueType();
9737 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
9739 // variable index can't be handled in mask registers,
9740 // extend vector to VR512
9741 if (!isa<ConstantSDNode>(Idx)) {
9742 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9743 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
9744 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
9745 ExtVT.getVectorElementType(), Ext, Idx);
9746 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
9749 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9750 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9751 unsigned MaxSift = rc->getSize()*8 - 1;
9752 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
9753 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9754 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
9755 DAG.getConstant(MaxSift, MVT::i8));
9756 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
9757 DAG.getIntPtrConstant(0));
9761 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
9762 SelectionDAG &DAG) const {
9764 SDValue Vec = Op.getOperand(0);
9765 MVT VecVT = Vec.getSimpleValueType();
9766 SDValue Idx = Op.getOperand(1);
9768 if (Op.getSimpleValueType() == MVT::i1)
9769 return ExtractBitFromMaskVector(Op, DAG);
9771 if (!isa<ConstantSDNode>(Idx)) {
9772 if (VecVT.is512BitVector() ||
9773 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
9774 VecVT.getVectorElementType().getSizeInBits() == 32)) {
9777 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
9778 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
9779 MaskEltVT.getSizeInBits());
9781 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
9782 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
9783 getZeroVector(MaskVT, Subtarget, DAG, dl),
9784 Idx, DAG.getConstant(0, getPointerTy()));
9785 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
9786 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
9787 Perm, DAG.getConstant(0, getPointerTy()));
9792 // If this is a 256-bit vector result, first extract the 128-bit vector and
9793 // then extract the element from the 128-bit vector.
9794 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
9796 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9797 // Get the 128-bit vector.
9798 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
9799 MVT EltVT = VecVT.getVectorElementType();
9801 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
9803 //if (IdxVal >= NumElems/2)
9804 // IdxVal -= NumElems/2;
9805 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
9806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
9807 DAG.getConstant(IdxVal, MVT::i32));
9810 assert(VecVT.is128BitVector() && "Unexpected vector length");
9812 if (Subtarget->hasSSE41()) {
9813 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
9818 MVT VT = Op.getSimpleValueType();
9819 // TODO: handle v16i8.
9820 if (VT.getSizeInBits() == 16) {
9821 SDValue Vec = Op.getOperand(0);
9822 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9824 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9825 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9826 DAG.getNode(ISD::BITCAST, dl,
9829 // Transform it so it match pextrw which produces a 32-bit result.
9830 MVT EltVT = MVT::i32;
9831 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
9832 Op.getOperand(0), Op.getOperand(1));
9833 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
9834 DAG.getValueType(VT));
9835 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9838 if (VT.getSizeInBits() == 32) {
9839 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9843 // SHUFPS the element to the lowest double word, then movss.
9844 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
9845 MVT VVT = Op.getOperand(0).getSimpleValueType();
9846 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9847 DAG.getUNDEF(VVT), Mask);
9848 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9849 DAG.getIntPtrConstant(0));
9852 if (VT.getSizeInBits() == 64) {
9853 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
9854 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
9855 // to match extract_elt for f64.
9856 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9860 // UNPCKHPD the element to the lowest double word, then movsd.
9861 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
9862 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
9863 int Mask[2] = { 1, -1 };
9864 MVT VVT = Op.getOperand(0).getSimpleValueType();
9865 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9866 DAG.getUNDEF(VVT), Mask);
9867 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9868 DAG.getIntPtrConstant(0));
9874 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9875 MVT VT = Op.getSimpleValueType();
9876 MVT EltVT = VT.getVectorElementType();
9879 SDValue N0 = Op.getOperand(0);
9880 SDValue N1 = Op.getOperand(1);
9881 SDValue N2 = Op.getOperand(2);
9883 if (!VT.is128BitVector())
9886 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
9887 isa<ConstantSDNode>(N2)) {
9889 if (VT == MVT::v8i16)
9890 Opc = X86ISD::PINSRW;
9891 else if (VT == MVT::v16i8)
9892 Opc = X86ISD::PINSRB;
9894 Opc = X86ISD::PINSRB;
9896 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
9898 if (N1.getValueType() != MVT::i32)
9899 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
9900 if (N2.getValueType() != MVT::i32)
9901 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
9902 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
9905 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
9906 // Bits [7:6] of the constant are the source select. This will always be
9907 // zero here. The DAG Combiner may combine an extract_elt index into these
9908 // bits. For example (insert (extract, 3), 2) could be matched by putting
9909 // the '3' into bits [7:6] of X86ISD::INSERTPS.
9910 // Bits [5:4] of the constant are the destination select. This is the
9911 // value of the incoming immediate.
9912 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
9913 // combine either bitwise AND or insert of float 0.0 to set these bits.
9914 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
9915 // Create this as a scalar to vector..
9916 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
9917 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
9920 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
9921 // PINSR* works with constant index.
9927 /// Insert one bit to mask vector, like v16i1 or v8i1.
9928 /// AVX-512 feature.
9930 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
9932 SDValue Vec = Op.getOperand(0);
9933 SDValue Elt = Op.getOperand(1);
9934 SDValue Idx = Op.getOperand(2);
9935 MVT VecVT = Vec.getSimpleValueType();
9937 if (!isa<ConstantSDNode>(Idx)) {
9938 // Non constant index. Extend source and destination,
9939 // insert element and then truncate the result.
9940 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9941 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
9942 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
9943 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
9944 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
9945 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
9948 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9949 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
9950 if (Vec.getOpcode() == ISD::UNDEF)
9951 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9952 DAG.getConstant(IdxVal, MVT::i8));
9953 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9954 unsigned MaxSift = rc->getSize()*8 - 1;
9955 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9956 DAG.getConstant(MaxSift, MVT::i8));
9957 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
9958 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9959 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
9962 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
9963 MVT VT = Op.getSimpleValueType();
9964 MVT EltVT = VT.getVectorElementType();
9966 if (EltVT == MVT::i1)
9967 return InsertBitToMaskVector(Op, DAG);
9970 SDValue N0 = Op.getOperand(0);
9971 SDValue N1 = Op.getOperand(1);
9972 SDValue N2 = Op.getOperand(2);
9974 // If this is a 256-bit vector result, first extract the 128-bit vector,
9975 // insert the element into the extracted half and then place it back.
9976 if (VT.is256BitVector() || VT.is512BitVector()) {
9977 if (!isa<ConstantSDNode>(N2))
9980 // Get the desired 128-bit vector half.
9981 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
9982 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
9984 // Insert the element into the desired half.
9985 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
9986 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
9988 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
9989 DAG.getConstant(IdxIn128, MVT::i32));
9991 // Insert the changed part back to the 256-bit vector
9992 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
9995 if (Subtarget->hasSSE41())
9996 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
9998 if (EltVT == MVT::i8)
10001 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10002 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10003 // as its second argument.
10004 if (N1.getValueType() != MVT::i32)
10005 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10006 if (N2.getValueType() != MVT::i32)
10007 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10008 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10013 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10015 MVT OpVT = Op.getSimpleValueType();
10017 // If this is a 256-bit vector result, first insert into a 128-bit
10018 // vector and then insert into the 256-bit vector.
10019 if (!OpVT.is128BitVector()) {
10020 // Insert into a 128-bit vector.
10021 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10022 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10023 OpVT.getVectorNumElements() / SizeFactor);
10025 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10027 // Insert the 128-bit vector.
10028 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10031 if (OpVT == MVT::v1i64 &&
10032 Op.getOperand(0).getValueType() == MVT::i64)
10033 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10035 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10036 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10037 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10038 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10041 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10042 // a simple subregister reference or explicit instructions to grab
10043 // upper bits of a vector.
10044 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10045 SelectionDAG &DAG) {
10047 SDValue In = Op.getOperand(0);
10048 SDValue Idx = Op.getOperand(1);
10049 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10050 MVT ResVT = Op.getSimpleValueType();
10051 MVT InVT = In.getSimpleValueType();
10053 if (Subtarget->hasFp256()) {
10054 if (ResVT.is128BitVector() &&
10055 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10056 isa<ConstantSDNode>(Idx)) {
10057 return Extract128BitVector(In, IdxVal, DAG, dl);
10059 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10060 isa<ConstantSDNode>(Idx)) {
10061 return Extract256BitVector(In, IdxVal, DAG, dl);
10067 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10068 // simple superregister reference or explicit instructions to insert
10069 // the upper bits of a vector.
10070 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10071 SelectionDAG &DAG) {
10072 if (Subtarget->hasFp256()) {
10073 SDLoc dl(Op.getNode());
10074 SDValue Vec = Op.getNode()->getOperand(0);
10075 SDValue SubVec = Op.getNode()->getOperand(1);
10076 SDValue Idx = Op.getNode()->getOperand(2);
10078 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10079 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10080 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10081 isa<ConstantSDNode>(Idx)) {
10082 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10083 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10086 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10087 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10088 isa<ConstantSDNode>(Idx)) {
10089 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10090 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10096 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10097 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10098 // one of the above mentioned nodes. It has to be wrapped because otherwise
10099 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10100 // be used to form addressing mode. These wrapped nodes will be selected
10103 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10104 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10107 // global base reg.
10108 unsigned char OpFlag = 0;
10109 unsigned WrapperKind = X86ISD::Wrapper;
10110 CodeModel::Model M = DAG.getTarget().getCodeModel();
10112 if (Subtarget->isPICStyleRIPRel() &&
10113 (M == CodeModel::Small || M == CodeModel::Kernel))
10114 WrapperKind = X86ISD::WrapperRIP;
10115 else if (Subtarget->isPICStyleGOT())
10116 OpFlag = X86II::MO_GOTOFF;
10117 else if (Subtarget->isPICStyleStubPIC())
10118 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10120 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10121 CP->getAlignment(),
10122 CP->getOffset(), OpFlag);
10124 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10125 // With PIC, the address is actually $g + Offset.
10127 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10128 DAG.getNode(X86ISD::GlobalBaseReg,
10129 SDLoc(), getPointerTy()),
10136 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10137 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10139 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10140 // global base reg.
10141 unsigned char OpFlag = 0;
10142 unsigned WrapperKind = X86ISD::Wrapper;
10143 CodeModel::Model M = DAG.getTarget().getCodeModel();
10145 if (Subtarget->isPICStyleRIPRel() &&
10146 (M == CodeModel::Small || M == CodeModel::Kernel))
10147 WrapperKind = X86ISD::WrapperRIP;
10148 else if (Subtarget->isPICStyleGOT())
10149 OpFlag = X86II::MO_GOTOFF;
10150 else if (Subtarget->isPICStyleStubPIC())
10151 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10153 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10156 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10158 // With PIC, the address is actually $g + Offset.
10160 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10161 DAG.getNode(X86ISD::GlobalBaseReg,
10162 SDLoc(), getPointerTy()),
10169 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10170 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10172 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10173 // global base reg.
10174 unsigned char OpFlag = 0;
10175 unsigned WrapperKind = X86ISD::Wrapper;
10176 CodeModel::Model M = DAG.getTarget().getCodeModel();
10178 if (Subtarget->isPICStyleRIPRel() &&
10179 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10180 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10181 OpFlag = X86II::MO_GOTPCREL;
10182 WrapperKind = X86ISD::WrapperRIP;
10183 } else if (Subtarget->isPICStyleGOT()) {
10184 OpFlag = X86II::MO_GOT;
10185 } else if (Subtarget->isPICStyleStubPIC()) {
10186 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10187 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10188 OpFlag = X86II::MO_DARWIN_NONLAZY;
10191 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10194 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10196 // With PIC, the address is actually $g + Offset.
10197 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10198 !Subtarget->is64Bit()) {
10199 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10200 DAG.getNode(X86ISD::GlobalBaseReg,
10201 SDLoc(), getPointerTy()),
10205 // For symbols that require a load from a stub to get the address, emit the
10207 if (isGlobalStubReference(OpFlag))
10208 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10209 MachinePointerInfo::getGOT(), false, false, false, 0);
10215 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10216 // Create the TargetBlockAddressAddress node.
10217 unsigned char OpFlags =
10218 Subtarget->ClassifyBlockAddressReference();
10219 CodeModel::Model M = DAG.getTarget().getCodeModel();
10220 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10221 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10223 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10226 if (Subtarget->isPICStyleRIPRel() &&
10227 (M == CodeModel::Small || M == CodeModel::Kernel))
10228 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10230 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10232 // With PIC, the address is actually $g + Offset.
10233 if (isGlobalRelativeToPICBase(OpFlags)) {
10234 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10235 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10243 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10244 int64_t Offset, SelectionDAG &DAG) const {
10245 // Create the TargetGlobalAddress node, folding in the constant
10246 // offset if it is legal.
10247 unsigned char OpFlags =
10248 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10249 CodeModel::Model M = DAG.getTarget().getCodeModel();
10251 if (OpFlags == X86II::MO_NO_FLAG &&
10252 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10253 // A direct static reference to a global.
10254 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10257 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10260 if (Subtarget->isPICStyleRIPRel() &&
10261 (M == CodeModel::Small || M == CodeModel::Kernel))
10262 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10264 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10266 // With PIC, the address is actually $g + Offset.
10267 if (isGlobalRelativeToPICBase(OpFlags)) {
10268 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10269 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10273 // For globals that require a load from a stub to get the address, emit the
10275 if (isGlobalStubReference(OpFlags))
10276 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10277 MachinePointerInfo::getGOT(), false, false, false, 0);
10279 // If there was a non-zero offset that we didn't fold, create an explicit
10280 // addition for it.
10282 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10283 DAG.getConstant(Offset, getPointerTy()));
10289 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10290 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10291 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10292 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10296 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10297 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10298 unsigned char OperandFlags, bool LocalDynamic = false) {
10299 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10300 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10302 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10303 GA->getValueType(0),
10307 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10311 SDValue Ops[] = { Chain, TGA, *InFlag };
10312 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10314 SDValue Ops[] = { Chain, TGA };
10315 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10318 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10319 MFI->setAdjustsStack(true);
10321 SDValue Flag = Chain.getValue(1);
10322 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10325 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10327 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10330 SDLoc dl(GA); // ? function entry point might be better
10331 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10332 DAG.getNode(X86ISD::GlobalBaseReg,
10333 SDLoc(), PtrVT), InFlag);
10334 InFlag = Chain.getValue(1);
10336 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10339 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10341 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10343 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10344 X86::RAX, X86II::MO_TLSGD);
10347 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10353 // Get the start address of the TLS block for this module.
10354 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10355 .getInfo<X86MachineFunctionInfo>();
10356 MFI->incNumLocalDynamicTLSAccesses();
10360 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10361 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10364 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10365 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10366 InFlag = Chain.getValue(1);
10367 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10368 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10371 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10375 unsigned char OperandFlags = X86II::MO_DTPOFF;
10376 unsigned WrapperKind = X86ISD::Wrapper;
10377 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10378 GA->getValueType(0),
10379 GA->getOffset(), OperandFlags);
10380 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10382 // Add x@dtpoff with the base.
10383 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10386 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10387 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10388 const EVT PtrVT, TLSModel::Model model,
10389 bool is64Bit, bool isPIC) {
10392 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10393 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10394 is64Bit ? 257 : 256));
10396 SDValue ThreadPointer =
10397 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10398 MachinePointerInfo(Ptr), false, false, false, 0);
10400 unsigned char OperandFlags = 0;
10401 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10403 unsigned WrapperKind = X86ISD::Wrapper;
10404 if (model == TLSModel::LocalExec) {
10405 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10406 } else if (model == TLSModel::InitialExec) {
10408 OperandFlags = X86II::MO_GOTTPOFF;
10409 WrapperKind = X86ISD::WrapperRIP;
10411 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10414 llvm_unreachable("Unexpected model");
10417 // emit "addl x@ntpoff,%eax" (local exec)
10418 // or "addl x@indntpoff,%eax" (initial exec)
10419 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10421 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10422 GA->getOffset(), OperandFlags);
10423 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10425 if (model == TLSModel::InitialExec) {
10426 if (isPIC && !is64Bit) {
10427 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10428 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10432 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10433 MachinePointerInfo::getGOT(), false, false, false, 0);
10436 // The address of the thread local variable is the add of the thread
10437 // pointer with the offset of the variable.
10438 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10442 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10444 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10445 const GlobalValue *GV = GA->getGlobal();
10447 if (Subtarget->isTargetELF()) {
10448 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10451 case TLSModel::GeneralDynamic:
10452 if (Subtarget->is64Bit())
10453 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10454 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10455 case TLSModel::LocalDynamic:
10456 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10457 Subtarget->is64Bit());
10458 case TLSModel::InitialExec:
10459 case TLSModel::LocalExec:
10460 return LowerToTLSExecModel(
10461 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10462 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10464 llvm_unreachable("Unknown TLS model.");
10467 if (Subtarget->isTargetDarwin()) {
10468 // Darwin only has one model of TLS. Lower to that.
10469 unsigned char OpFlag = 0;
10470 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10471 X86ISD::WrapperRIP : X86ISD::Wrapper;
10473 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10474 // global base reg.
10475 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10476 !Subtarget->is64Bit();
10478 OpFlag = X86II::MO_TLVP_PIC_BASE;
10480 OpFlag = X86II::MO_TLVP;
10482 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10483 GA->getValueType(0),
10484 GA->getOffset(), OpFlag);
10485 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10487 // With PIC32, the address is actually $g + Offset.
10489 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10490 DAG.getNode(X86ISD::GlobalBaseReg,
10491 SDLoc(), getPointerTy()),
10494 // Lowering the machine isd will make sure everything is in the right
10496 SDValue Chain = DAG.getEntryNode();
10497 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10498 SDValue Args[] = { Chain, Offset };
10499 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10501 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10502 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10503 MFI->setAdjustsStack(true);
10505 // And our return value (tls address) is in the standard call return value
10507 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10508 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10509 Chain.getValue(1));
10512 if (Subtarget->isTargetKnownWindowsMSVC() ||
10513 Subtarget->isTargetWindowsGNU()) {
10514 // Just use the implicit TLS architecture
10515 // Need to generate someting similar to:
10516 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10518 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10519 // mov rcx, qword [rdx+rcx*8]
10520 // mov eax, .tls$:tlsvar
10521 // [rax+rcx] contains the address
10522 // Windows 64bit: gs:0x58
10523 // Windows 32bit: fs:__tls_array
10526 SDValue Chain = DAG.getEntryNode();
10528 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10529 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10530 // use its literal value of 0x2C.
10531 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10532 ? Type::getInt8PtrTy(*DAG.getContext(),
10534 : Type::getInt32PtrTy(*DAG.getContext(),
10538 Subtarget->is64Bit()
10539 ? DAG.getIntPtrConstant(0x58)
10540 : (Subtarget->isTargetWindowsGNU()
10541 ? DAG.getIntPtrConstant(0x2C)
10542 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10544 SDValue ThreadPointer =
10545 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10546 MachinePointerInfo(Ptr), false, false, false, 0);
10548 // Load the _tls_index variable
10549 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10550 if (Subtarget->is64Bit())
10551 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10552 IDX, MachinePointerInfo(), MVT::i32,
10555 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10556 false, false, false, 0);
10558 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10560 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10562 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10563 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10564 false, false, false, 0);
10566 // Get the offset of start of .tls section
10567 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10568 GA->getValueType(0),
10569 GA->getOffset(), X86II::MO_SECREL);
10570 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10572 // The address of the thread local variable is the add of the thread
10573 // pointer with the offset of the variable.
10574 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10577 llvm_unreachable("TLS not implemented for this target.");
10580 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10581 /// and take a 2 x i32 value to shift plus a shift amount.
10582 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10583 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10584 MVT VT = Op.getSimpleValueType();
10585 unsigned VTBits = VT.getSizeInBits();
10587 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10588 SDValue ShOpLo = Op.getOperand(0);
10589 SDValue ShOpHi = Op.getOperand(1);
10590 SDValue ShAmt = Op.getOperand(2);
10591 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10592 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10594 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10595 DAG.getConstant(VTBits - 1, MVT::i8));
10596 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10597 DAG.getConstant(VTBits - 1, MVT::i8))
10598 : DAG.getConstant(0, VT);
10600 SDValue Tmp2, Tmp3;
10601 if (Op.getOpcode() == ISD::SHL_PARTS) {
10602 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10603 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10605 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10606 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10609 // If the shift amount is larger or equal than the width of a part we can't
10610 // rely on the results of shld/shrd. Insert a test and select the appropriate
10611 // values for large shift amounts.
10612 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10613 DAG.getConstant(VTBits, MVT::i8));
10614 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10615 AndNode, DAG.getConstant(0, MVT::i8));
10618 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10619 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10620 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10622 if (Op.getOpcode() == ISD::SHL_PARTS) {
10623 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10624 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10626 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10627 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10630 SDValue Ops[2] = { Lo, Hi };
10631 return DAG.getMergeValues(Ops, dl);
10634 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10635 SelectionDAG &DAG) const {
10636 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10638 if (SrcVT.isVector())
10641 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10642 "Unknown SINT_TO_FP to lower!");
10644 // These are really Legal; return the operand so the caller accepts it as
10646 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10648 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10649 Subtarget->is64Bit()) {
10654 unsigned Size = SrcVT.getSizeInBits()/8;
10655 MachineFunction &MF = DAG.getMachineFunction();
10656 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10657 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10658 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10660 MachinePointerInfo::getFixedStack(SSFI),
10662 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10665 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
10667 SelectionDAG &DAG) const {
10671 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10673 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10675 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10677 unsigned ByteSize = SrcVT.getSizeInBits()/8;
10679 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10680 MachineMemOperand *MMO;
10682 int SSFI = FI->getIndex();
10684 DAG.getMachineFunction()
10685 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10686 MachineMemOperand::MOLoad, ByteSize, ByteSize);
10688 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10689 StackSlot = StackSlot.getOperand(1);
10691 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10692 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10694 Tys, Ops, SrcVT, MMO);
10697 Chain = Result.getValue(1);
10698 SDValue InFlag = Result.getValue(2);
10700 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10701 // shouldn't be necessary except that RFP cannot be live across
10702 // multiple blocks. When stackifier is fixed, they can be uncoupled.
10703 MachineFunction &MF = DAG.getMachineFunction();
10704 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10705 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
10706 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10707 Tys = DAG.getVTList(MVT::Other);
10709 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
10711 MachineMemOperand *MMO =
10712 DAG.getMachineFunction()
10713 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10714 MachineMemOperand::MOStore, SSFISize, SSFISize);
10716 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
10717 Ops, Op.getValueType(), MMO);
10718 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
10719 MachinePointerInfo::getFixedStack(SSFI),
10720 false, false, false, 0);
10726 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
10727 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
10728 SelectionDAG &DAG) const {
10729 // This algorithm is not obvious. Here it is what we're trying to output:
10732 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
10733 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
10735 haddpd %xmm0, %xmm0
10737 pshufd $0x4e, %xmm0, %xmm1
10743 LLVMContext *Context = DAG.getContext();
10745 // Build some magic constants.
10746 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
10747 Constant *C0 = ConstantDataVector::get(*Context, CV0);
10748 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
10750 SmallVector<Constant*,2> CV1;
10752 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10753 APInt(64, 0x4330000000000000ULL))));
10755 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10756 APInt(64, 0x4530000000000000ULL))));
10757 Constant *C1 = ConstantVector::get(CV1);
10758 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
10760 // Load the 64-bit value into an XMM register.
10761 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10763 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10764 MachinePointerInfo::getConstantPool(),
10765 false, false, false, 16);
10766 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10767 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10770 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
10771 MachinePointerInfo::getConstantPool(),
10772 false, false, false, 16);
10773 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
10774 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
10777 if (Subtarget->hasSSE3()) {
10778 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
10779 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
10781 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10782 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10784 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10785 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
10789 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
10790 DAG.getIntPtrConstant(0));
10793 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
10794 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
10795 SelectionDAG &DAG) const {
10797 // FP constant to bias correct the final result.
10798 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
10801 // Load the 32-bit value into an XMM register.
10802 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
10805 // Zero out the upper parts of the register.
10806 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
10808 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10809 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
10810 DAG.getIntPtrConstant(0));
10812 // Or the load with the bias.
10813 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10814 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10815 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10816 MVT::v2f64, Load)),
10817 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10818 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10819 MVT::v2f64, Bias)));
10820 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10821 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
10822 DAG.getIntPtrConstant(0));
10824 // Subtract the bias.
10825 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
10827 // Handle final rounding.
10828 EVT DestVT = Op.getValueType();
10830 if (DestVT.bitsLT(MVT::f64))
10831 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
10832 DAG.getIntPtrConstant(0));
10833 if (DestVT.bitsGT(MVT::f64))
10834 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
10836 // Handle final rounding.
10840 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
10841 SelectionDAG &DAG) const {
10842 SDValue N0 = Op.getOperand(0);
10843 MVT SVT = N0.getSimpleValueType();
10846 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
10847 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
10848 "Custom UINT_TO_FP is not supported!");
10850 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
10851 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
10852 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
10855 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
10856 SelectionDAG &DAG) const {
10857 SDValue N0 = Op.getOperand(0);
10860 if (Op.getValueType().isVector())
10861 return lowerUINT_TO_FP_vec(Op, DAG);
10863 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
10864 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
10865 // the optimization here.
10866 if (DAG.SignBitIsZero(N0))
10867 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
10869 MVT SrcVT = N0.getSimpleValueType();
10870 MVT DstVT = Op.getSimpleValueType();
10871 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
10872 return LowerUINT_TO_FP_i64(Op, DAG);
10873 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
10874 return LowerUINT_TO_FP_i32(Op, DAG);
10875 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
10878 // Make a 64-bit buffer, and use it to build an FILD.
10879 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
10880 if (SrcVT == MVT::i32) {
10881 SDValue WordOff = DAG.getConstant(4, getPointerTy());
10882 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
10883 getPointerTy(), StackSlot, WordOff);
10884 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10885 StackSlot, MachinePointerInfo(),
10887 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
10888 OffsetSlot, MachinePointerInfo(),
10890 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
10894 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
10895 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10896 StackSlot, MachinePointerInfo(),
10898 // For i64 source, we need to add the appropriate power of 2 if the input
10899 // was negative. This is the same as the optimization in
10900 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
10901 // we must be careful to do the computation in x87 extended precision, not
10902 // in SSE. (The generic code can't know it's OK to do this, or how to.)
10903 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
10904 MachineMemOperand *MMO =
10905 DAG.getMachineFunction()
10906 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10907 MachineMemOperand::MOLoad, 8, 8);
10909 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
10910 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
10911 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
10914 APInt FF(32, 0x5F800000ULL);
10916 // Check whether the sign bit is set.
10917 SDValue SignSet = DAG.getSetCC(dl,
10918 getSetCCResultType(*DAG.getContext(), MVT::i64),
10919 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
10922 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
10923 SDValue FudgePtr = DAG.getConstantPool(
10924 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
10927 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
10928 SDValue Zero = DAG.getIntPtrConstant(0);
10929 SDValue Four = DAG.getIntPtrConstant(4);
10930 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
10932 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
10934 // Load the value out, extending it from f32 to f80.
10935 // FIXME: Avoid the extend by constructing the right constant pool?
10936 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
10937 FudgePtr, MachinePointerInfo::getConstantPool(),
10938 MVT::f32, false, false, 4);
10939 // Extend everything to 80 bits to force it to be done on x87.
10940 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
10941 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
10944 std::pair<SDValue,SDValue>
10945 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
10946 bool IsSigned, bool IsReplace) const {
10949 EVT DstTy = Op.getValueType();
10951 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
10952 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
10956 assert(DstTy.getSimpleVT() <= MVT::i64 &&
10957 DstTy.getSimpleVT() >= MVT::i16 &&
10958 "Unknown FP_TO_INT to lower!");
10960 // These are really Legal.
10961 if (DstTy == MVT::i32 &&
10962 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10963 return std::make_pair(SDValue(), SDValue());
10964 if (Subtarget->is64Bit() &&
10965 DstTy == MVT::i64 &&
10966 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10967 return std::make_pair(SDValue(), SDValue());
10969 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
10970 // stack slot, or into the FTOL runtime function.
10971 MachineFunction &MF = DAG.getMachineFunction();
10972 unsigned MemSize = DstTy.getSizeInBits()/8;
10973 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
10974 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10977 if (!IsSigned && isIntegerTypeFTOL(DstTy))
10978 Opc = X86ISD::WIN_FTOL;
10980 switch (DstTy.getSimpleVT().SimpleTy) {
10981 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
10982 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
10983 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
10984 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
10987 SDValue Chain = DAG.getEntryNode();
10988 SDValue Value = Op.getOperand(0);
10989 EVT TheVT = Op.getOperand(0).getValueType();
10990 // FIXME This causes a redundant load/store if the SSE-class value is already
10991 // in memory, such as if it is on the callstack.
10992 if (isScalarFPTypeInSSEReg(TheVT)) {
10993 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
10994 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
10995 MachinePointerInfo::getFixedStack(SSFI),
10997 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
10999 Chain, StackSlot, DAG.getValueType(TheVT)
11002 MachineMemOperand *MMO =
11003 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11004 MachineMemOperand::MOLoad, MemSize, MemSize);
11005 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11006 Chain = Value.getValue(1);
11007 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11008 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11011 MachineMemOperand *MMO =
11012 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11013 MachineMemOperand::MOStore, MemSize, MemSize);
11015 if (Opc != X86ISD::WIN_FTOL) {
11016 // Build the FP_TO_INT*_IN_MEM
11017 SDValue Ops[] = { Chain, Value, StackSlot };
11018 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11020 return std::make_pair(FIST, StackSlot);
11022 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11023 DAG.getVTList(MVT::Other, MVT::Glue),
11025 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11026 MVT::i32, ftol.getValue(1));
11027 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11028 MVT::i32, eax.getValue(2));
11029 SDValue Ops[] = { eax, edx };
11030 SDValue pair = IsReplace
11031 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11032 : DAG.getMergeValues(Ops, DL);
11033 return std::make_pair(pair, SDValue());
11037 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11038 const X86Subtarget *Subtarget) {
11039 MVT VT = Op->getSimpleValueType(0);
11040 SDValue In = Op->getOperand(0);
11041 MVT InVT = In.getSimpleValueType();
11044 // Optimize vectors in AVX mode:
11047 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11048 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11049 // Concat upper and lower parts.
11052 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11053 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11054 // Concat upper and lower parts.
11057 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11058 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11059 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11062 if (Subtarget->hasInt256())
11063 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11065 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11066 SDValue Undef = DAG.getUNDEF(InVT);
11067 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11068 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11069 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11071 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11072 VT.getVectorNumElements()/2);
11074 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11075 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11077 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11080 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11081 SelectionDAG &DAG) {
11082 MVT VT = Op->getSimpleValueType(0);
11083 SDValue In = Op->getOperand(0);
11084 MVT InVT = In.getSimpleValueType();
11086 unsigned int NumElts = VT.getVectorNumElements();
11087 if (NumElts != 8 && NumElts != 16)
11090 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11091 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11093 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11094 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11095 // Now we have only mask extension
11096 assert(InVT.getVectorElementType() == MVT::i1);
11097 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11098 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11099 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11100 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11101 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11102 MachinePointerInfo::getConstantPool(),
11103 false, false, false, Alignment);
11105 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11106 if (VT.is512BitVector())
11108 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11111 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11112 SelectionDAG &DAG) {
11113 if (Subtarget->hasFp256()) {
11114 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11122 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11123 SelectionDAG &DAG) {
11125 MVT VT = Op.getSimpleValueType();
11126 SDValue In = Op.getOperand(0);
11127 MVT SVT = In.getSimpleValueType();
11129 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11130 return LowerZERO_EXTEND_AVX512(Op, DAG);
11132 if (Subtarget->hasFp256()) {
11133 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11138 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11139 VT.getVectorNumElements() != SVT.getVectorNumElements());
11143 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11145 MVT VT = Op.getSimpleValueType();
11146 SDValue In = Op.getOperand(0);
11147 MVT InVT = In.getSimpleValueType();
11149 if (VT == MVT::i1) {
11150 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11151 "Invalid scalar TRUNCATE operation");
11152 if (InVT == MVT::i32)
11154 if (InVT.getSizeInBits() == 64)
11155 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11156 else if (InVT.getSizeInBits() < 32)
11157 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11158 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11160 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11161 "Invalid TRUNCATE operation");
11163 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11164 if (VT.getVectorElementType().getSizeInBits() >=8)
11165 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11167 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11168 unsigned NumElts = InVT.getVectorNumElements();
11169 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11170 if (InVT.getSizeInBits() < 512) {
11171 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11172 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11176 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11177 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11178 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11179 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11180 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11181 MachinePointerInfo::getConstantPool(),
11182 false, false, false, Alignment);
11183 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11184 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11185 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11188 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11189 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11190 if (Subtarget->hasInt256()) {
11191 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11192 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11193 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11195 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11196 DAG.getIntPtrConstant(0));
11199 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11200 DAG.getIntPtrConstant(0));
11201 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11202 DAG.getIntPtrConstant(2));
11203 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11204 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11205 static const int ShufMask[] = {0, 2, 4, 6};
11206 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11209 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11210 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11211 if (Subtarget->hasInt256()) {
11212 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11214 SmallVector<SDValue,32> pshufbMask;
11215 for (unsigned i = 0; i < 2; ++i) {
11216 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11217 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11218 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11219 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11220 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11221 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11222 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11223 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11224 for (unsigned j = 0; j < 8; ++j)
11225 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11227 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11228 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11229 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11231 static const int ShufMask[] = {0, 2, -1, -1};
11232 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11234 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11235 DAG.getIntPtrConstant(0));
11236 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11239 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11240 DAG.getIntPtrConstant(0));
11242 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11243 DAG.getIntPtrConstant(4));
11245 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11246 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11248 // The PSHUFB mask:
11249 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11250 -1, -1, -1, -1, -1, -1, -1, -1};
11252 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11253 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11254 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11256 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11257 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11259 // The MOVLHPS Mask:
11260 static const int ShufMask2[] = {0, 1, 4, 5};
11261 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11262 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11265 // Handle truncation of V256 to V128 using shuffles.
11266 if (!VT.is128BitVector() || !InVT.is256BitVector())
11269 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11271 unsigned NumElems = VT.getVectorNumElements();
11272 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11274 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11275 // Prepare truncation shuffle mask
11276 for (unsigned i = 0; i != NumElems; ++i)
11277 MaskVec[i] = i * 2;
11278 SDValue V = DAG.getVectorShuffle(NVT, DL,
11279 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11280 DAG.getUNDEF(NVT), &MaskVec[0]);
11281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11282 DAG.getIntPtrConstant(0));
11285 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11286 SelectionDAG &DAG) const {
11287 assert(!Op.getSimpleValueType().isVector());
11289 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11290 /*IsSigned=*/ true, /*IsReplace=*/ false);
11291 SDValue FIST = Vals.first, StackSlot = Vals.second;
11292 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11293 if (!FIST.getNode()) return Op;
11295 if (StackSlot.getNode())
11296 // Load the result.
11297 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11298 FIST, StackSlot, MachinePointerInfo(),
11299 false, false, false, 0);
11301 // The node is the result.
11305 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11306 SelectionDAG &DAG) const {
11307 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11308 /*IsSigned=*/ false, /*IsReplace=*/ false);
11309 SDValue FIST = Vals.first, StackSlot = Vals.second;
11310 assert(FIST.getNode() && "Unexpected failure");
11312 if (StackSlot.getNode())
11313 // Load the result.
11314 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11315 FIST, StackSlot, MachinePointerInfo(),
11316 false, false, false, 0);
11318 // The node is the result.
11322 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11324 MVT VT = Op.getSimpleValueType();
11325 SDValue In = Op.getOperand(0);
11326 MVT SVT = In.getSimpleValueType();
11328 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11330 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11331 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11332 In, DAG.getUNDEF(SVT)));
11335 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11336 LLVMContext *Context = DAG.getContext();
11338 MVT VT = Op.getSimpleValueType();
11340 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11341 if (VT.isVector()) {
11342 EltVT = VT.getVectorElementType();
11343 NumElts = VT.getVectorNumElements();
11346 if (EltVT == MVT::f64)
11347 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11348 APInt(64, ~(1ULL << 63))));
11350 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11351 APInt(32, ~(1U << 31))));
11352 C = ConstantVector::getSplat(NumElts, C);
11353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11354 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11355 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11356 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11357 MachinePointerInfo::getConstantPool(),
11358 false, false, false, Alignment);
11359 if (VT.isVector()) {
11360 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11361 return DAG.getNode(ISD::BITCAST, dl, VT,
11362 DAG.getNode(ISD::AND, dl, ANDVT,
11363 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11365 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11367 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11370 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11371 LLVMContext *Context = DAG.getContext();
11373 MVT VT = Op.getSimpleValueType();
11375 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11376 if (VT.isVector()) {
11377 EltVT = VT.getVectorElementType();
11378 NumElts = VT.getVectorNumElements();
11381 if (EltVT == MVT::f64)
11382 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11383 APInt(64, 1ULL << 63)));
11385 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11386 APInt(32, 1U << 31)));
11387 C = ConstantVector::getSplat(NumElts, C);
11388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11389 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11390 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11391 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11392 MachinePointerInfo::getConstantPool(),
11393 false, false, false, Alignment);
11394 if (VT.isVector()) {
11395 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11396 return DAG.getNode(ISD::BITCAST, dl, VT,
11397 DAG.getNode(ISD::XOR, dl, XORVT,
11398 DAG.getNode(ISD::BITCAST, dl, XORVT,
11400 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11403 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11406 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11408 LLVMContext *Context = DAG.getContext();
11409 SDValue Op0 = Op.getOperand(0);
11410 SDValue Op1 = Op.getOperand(1);
11412 MVT VT = Op.getSimpleValueType();
11413 MVT SrcVT = Op1.getSimpleValueType();
11415 // If second operand is smaller, extend it first.
11416 if (SrcVT.bitsLT(VT)) {
11417 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11420 // And if it is bigger, shrink it first.
11421 if (SrcVT.bitsGT(VT)) {
11422 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11426 // At this point the operands and the result should have the same
11427 // type, and that won't be f80 since that is not custom lowered.
11429 // First get the sign bit of second operand.
11430 SmallVector<Constant*,4> CV;
11431 if (SrcVT == MVT::f64) {
11432 const fltSemantics &Sem = APFloat::IEEEdouble;
11433 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11434 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11436 const fltSemantics &Sem = APFloat::IEEEsingle;
11437 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11438 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11439 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11440 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11442 Constant *C = ConstantVector::get(CV);
11443 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11444 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11445 MachinePointerInfo::getConstantPool(),
11446 false, false, false, 16);
11447 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11449 // Shift sign bit right or left if the two operands have different types.
11450 if (SrcVT.bitsGT(VT)) {
11451 // Op0 is MVT::f32, Op1 is MVT::f64.
11452 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11453 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11454 DAG.getConstant(32, MVT::i32));
11455 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11456 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11457 DAG.getIntPtrConstant(0));
11460 // Clear first operand sign bit.
11462 if (VT == MVT::f64) {
11463 const fltSemantics &Sem = APFloat::IEEEdouble;
11464 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11465 APInt(64, ~(1ULL << 63)))));
11466 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11468 const fltSemantics &Sem = APFloat::IEEEsingle;
11469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11470 APInt(32, ~(1U << 31)))));
11471 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11472 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11473 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11475 C = ConstantVector::get(CV);
11476 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11477 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11478 MachinePointerInfo::getConstantPool(),
11479 false, false, false, 16);
11480 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11482 // Or the value with the sign bit.
11483 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11486 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11487 SDValue N0 = Op.getOperand(0);
11489 MVT VT = Op.getSimpleValueType();
11491 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11492 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11493 DAG.getConstant(1, VT));
11494 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11497 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11499 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11500 SelectionDAG &DAG) {
11501 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11503 if (!Subtarget->hasSSE41())
11506 if (!Op->hasOneUse())
11509 SDNode *N = Op.getNode();
11512 SmallVector<SDValue, 8> Opnds;
11513 DenseMap<SDValue, unsigned> VecInMap;
11514 SmallVector<SDValue, 8> VecIns;
11515 EVT VT = MVT::Other;
11517 // Recognize a special case where a vector is casted into wide integer to
11519 Opnds.push_back(N->getOperand(0));
11520 Opnds.push_back(N->getOperand(1));
11522 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11523 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11524 // BFS traverse all OR'd operands.
11525 if (I->getOpcode() == ISD::OR) {
11526 Opnds.push_back(I->getOperand(0));
11527 Opnds.push_back(I->getOperand(1));
11528 // Re-evaluate the number of nodes to be traversed.
11529 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11533 // Quit if a non-EXTRACT_VECTOR_ELT
11534 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11537 // Quit if without a constant index.
11538 SDValue Idx = I->getOperand(1);
11539 if (!isa<ConstantSDNode>(Idx))
11542 SDValue ExtractedFromVec = I->getOperand(0);
11543 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11544 if (M == VecInMap.end()) {
11545 VT = ExtractedFromVec.getValueType();
11546 // Quit if not 128/256-bit vector.
11547 if (!VT.is128BitVector() && !VT.is256BitVector())
11549 // Quit if not the same type.
11550 if (VecInMap.begin() != VecInMap.end() &&
11551 VT != VecInMap.begin()->first.getValueType())
11553 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11554 VecIns.push_back(ExtractedFromVec);
11556 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11559 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11560 "Not extracted from 128-/256-bit vector.");
11562 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11564 for (DenseMap<SDValue, unsigned>::const_iterator
11565 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11566 // Quit if not all elements are used.
11567 if (I->second != FullMask)
11571 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11573 // Cast all vectors into TestVT for PTEST.
11574 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11575 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11577 // If more than one full vectors are evaluated, OR them first before PTEST.
11578 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11579 // Each iteration will OR 2 nodes and append the result until there is only
11580 // 1 node left, i.e. the final OR'd value of all vectors.
11581 SDValue LHS = VecIns[Slot];
11582 SDValue RHS = VecIns[Slot + 1];
11583 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11586 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11587 VecIns.back(), VecIns.back());
11590 /// \brief return true if \c Op has a use that doesn't just read flags.
11591 static bool hasNonFlagsUse(SDValue Op) {
11592 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11594 SDNode *User = *UI;
11595 unsigned UOpNo = UI.getOperandNo();
11596 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11597 // Look pass truncate.
11598 UOpNo = User->use_begin().getOperandNo();
11599 User = *User->use_begin();
11602 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11603 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11609 /// Emit nodes that will be selected as "test Op0,Op0", or something
11611 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11612 SelectionDAG &DAG) const {
11613 if (Op.getValueType() == MVT::i1)
11614 // KORTEST instruction should be selected
11615 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11616 DAG.getConstant(0, Op.getValueType()));
11618 // CF and OF aren't always set the way we want. Determine which
11619 // of these we need.
11620 bool NeedCF = false;
11621 bool NeedOF = false;
11624 case X86::COND_A: case X86::COND_AE:
11625 case X86::COND_B: case X86::COND_BE:
11628 case X86::COND_G: case X86::COND_GE:
11629 case X86::COND_L: case X86::COND_LE:
11630 case X86::COND_O: case X86::COND_NO: {
11631 // Check if we really need to set the
11632 // Overflow flag. If NoSignedWrap is present
11633 // that is not actually needed.
11634 switch (Op->getOpcode()) {
11639 const BinaryWithFlagsSDNode *BinNode =
11640 cast<BinaryWithFlagsSDNode>(Op.getNode());
11641 if (BinNode->hasNoSignedWrap())
11651 // See if we can use the EFLAGS value from the operand instead of
11652 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11653 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11654 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11655 // Emit a CMP with 0, which is the TEST pattern.
11656 //if (Op.getValueType() == MVT::i1)
11657 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11658 // DAG.getConstant(0, MVT::i1));
11659 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11660 DAG.getConstant(0, Op.getValueType()));
11662 unsigned Opcode = 0;
11663 unsigned NumOperands = 0;
11665 // Truncate operations may prevent the merge of the SETCC instruction
11666 // and the arithmetic instruction before it. Attempt to truncate the operands
11667 // of the arithmetic instruction and use a reduced bit-width instruction.
11668 bool NeedTruncation = false;
11669 SDValue ArithOp = Op;
11670 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11671 SDValue Arith = Op->getOperand(0);
11672 // Both the trunc and the arithmetic op need to have one user each.
11673 if (Arith->hasOneUse())
11674 switch (Arith.getOpcode()) {
11681 NeedTruncation = true;
11687 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11688 // which may be the result of a CAST. We use the variable 'Op', which is the
11689 // non-casted variable when we check for possible users.
11690 switch (ArithOp.getOpcode()) {
11692 // Due to an isel shortcoming, be conservative if this add is likely to be
11693 // selected as part of a load-modify-store instruction. When the root node
11694 // in a match is a store, isel doesn't know how to remap non-chain non-flag
11695 // uses of other nodes in the match, such as the ADD in this case. This
11696 // leads to the ADD being left around and reselected, with the result being
11697 // two adds in the output. Alas, even if none our users are stores, that
11698 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11699 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11700 // climbing the DAG back to the root, and it doesn't seem to be worth the
11702 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11703 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11704 if (UI->getOpcode() != ISD::CopyToReg &&
11705 UI->getOpcode() != ISD::SETCC &&
11706 UI->getOpcode() != ISD::STORE)
11709 if (ConstantSDNode *C =
11710 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
11711 // An add of one will be selected as an INC.
11712 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
11713 Opcode = X86ISD::INC;
11718 // An add of negative one (subtract of one) will be selected as a DEC.
11719 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
11720 Opcode = X86ISD::DEC;
11726 // Otherwise use a regular EFLAGS-setting add.
11727 Opcode = X86ISD::ADD;
11732 // If we have a constant logical shift that's only used in a comparison
11733 // against zero turn it into an equivalent AND. This allows turning it into
11734 // a TEST instruction later.
11735 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
11736 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
11737 EVT VT = Op.getValueType();
11738 unsigned BitWidth = VT.getSizeInBits();
11739 unsigned ShAmt = Op->getConstantOperandVal(1);
11740 if (ShAmt >= BitWidth) // Avoid undefined shifts.
11742 APInt Mask = ArithOp.getOpcode() == ISD::SRL
11743 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
11744 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
11745 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
11747 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
11748 DAG.getConstant(Mask, VT));
11749 DAG.ReplaceAllUsesWith(Op, New);
11755 // If the primary and result isn't used, don't bother using X86ISD::AND,
11756 // because a TEST instruction will be better.
11757 if (!hasNonFlagsUse(Op))
11763 // Due to the ISEL shortcoming noted above, be conservative if this op is
11764 // likely to be selected as part of a load-modify-store instruction.
11765 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11766 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11767 if (UI->getOpcode() == ISD::STORE)
11770 // Otherwise use a regular EFLAGS-setting instruction.
11771 switch (ArithOp.getOpcode()) {
11772 default: llvm_unreachable("unexpected operator!");
11773 case ISD::SUB: Opcode = X86ISD::SUB; break;
11774 case ISD::XOR: Opcode = X86ISD::XOR; break;
11775 case ISD::AND: Opcode = X86ISD::AND; break;
11777 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
11778 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
11779 if (EFLAGS.getNode())
11782 Opcode = X86ISD::OR;
11796 return SDValue(Op.getNode(), 1);
11802 // If we found that truncation is beneficial, perform the truncation and
11804 if (NeedTruncation) {
11805 EVT VT = Op.getValueType();
11806 SDValue WideVal = Op->getOperand(0);
11807 EVT WideVT = WideVal.getValueType();
11808 unsigned ConvertedOp = 0;
11809 // Use a target machine opcode to prevent further DAGCombine
11810 // optimizations that may separate the arithmetic operations
11811 // from the setcc node.
11812 switch (WideVal.getOpcode()) {
11814 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
11815 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
11816 case ISD::AND: ConvertedOp = X86ISD::AND; break;
11817 case ISD::OR: ConvertedOp = X86ISD::OR; break;
11818 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
11822 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11823 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
11824 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
11825 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
11826 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
11832 // Emit a CMP with 0, which is the TEST pattern.
11833 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11834 DAG.getConstant(0, Op.getValueType()));
11836 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11837 SmallVector<SDValue, 4> Ops;
11838 for (unsigned i = 0; i != NumOperands; ++i)
11839 Ops.push_back(Op.getOperand(i));
11841 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
11842 DAG.ReplaceAllUsesWith(Op, New);
11843 return SDValue(New.getNode(), 1);
11846 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
11848 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
11849 SDLoc dl, SelectionDAG &DAG) const {
11850 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
11851 if (C->getAPIntValue() == 0)
11852 return EmitTest(Op0, X86CC, dl, DAG);
11854 if (Op0.getValueType() == MVT::i1)
11855 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
11858 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
11859 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
11860 // Do the comparison at i32 if it's smaller, besides the Atom case.
11861 // This avoids subregister aliasing issues. Keep the smaller reference
11862 // if we're optimizing for size, however, as that'll allow better folding
11863 // of memory operations.
11864 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
11865 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
11866 AttributeSet::FunctionIndex, Attribute::MinSize) &&
11867 !Subtarget->isAtom()) {
11868 unsigned ExtendOp =
11869 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
11870 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
11871 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
11873 // Use SUB instead of CMP to enable CSE between SUB and CMP.
11874 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
11875 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
11877 return SDValue(Sub.getNode(), 1);
11879 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
11882 /// Convert a comparison if required by the subtarget.
11883 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
11884 SelectionDAG &DAG) const {
11885 // If the subtarget does not support the FUCOMI instruction, floating-point
11886 // comparisons have to be converted.
11887 if (Subtarget->hasCMov() ||
11888 Cmp.getOpcode() != X86ISD::CMP ||
11889 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
11890 !Cmp.getOperand(1).getValueType().isFloatingPoint())
11893 // The instruction selector will select an FUCOM instruction instead of
11894 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
11895 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
11896 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
11898 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
11899 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
11900 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
11901 DAG.getConstant(8, MVT::i8));
11902 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
11903 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
11906 static bool isAllOnes(SDValue V) {
11907 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
11908 return C && C->isAllOnesValue();
11911 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
11912 /// if it's possible.
11913 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
11914 SDLoc dl, SelectionDAG &DAG) const {
11915 SDValue Op0 = And.getOperand(0);
11916 SDValue Op1 = And.getOperand(1);
11917 if (Op0.getOpcode() == ISD::TRUNCATE)
11918 Op0 = Op0.getOperand(0);
11919 if (Op1.getOpcode() == ISD::TRUNCATE)
11920 Op1 = Op1.getOperand(0);
11923 if (Op1.getOpcode() == ISD::SHL)
11924 std::swap(Op0, Op1);
11925 if (Op0.getOpcode() == ISD::SHL) {
11926 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
11927 if (And00C->getZExtValue() == 1) {
11928 // If we looked past a truncate, check that it's only truncating away
11930 unsigned BitWidth = Op0.getValueSizeInBits();
11931 unsigned AndBitWidth = And.getValueSizeInBits();
11932 if (BitWidth > AndBitWidth) {
11934 DAG.computeKnownBits(Op0, Zeros, Ones);
11935 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
11939 RHS = Op0.getOperand(1);
11941 } else if (Op1.getOpcode() == ISD::Constant) {
11942 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
11943 uint64_t AndRHSVal = AndRHS->getZExtValue();
11944 SDValue AndLHS = Op0;
11946 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11947 LHS = AndLHS.getOperand(0);
11948 RHS = AndLHS.getOperand(1);
11951 // Use BT if the immediate can't be encoded in a TEST instruction.
11952 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
11954 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
11958 if (LHS.getNode()) {
11959 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
11960 // instruction. Since the shift amount is in-range-or-undefined, we know
11961 // that doing a bittest on the i32 value is ok. We extend to i32 because
11962 // the encoding for the i16 version is larger than the i32 version.
11963 // Also promote i16 to i32 for performance / code size reason.
11964 if (LHS.getValueType() == MVT::i8 ||
11965 LHS.getValueType() == MVT::i16)
11966 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
11968 // If the operand types disagree, extend the shift amount to match. Since
11969 // BT ignores high bits (like shifts) we can use anyextend.
11970 if (LHS.getValueType() != RHS.getValueType())
11971 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
11973 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
11974 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
11975 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11976 DAG.getConstant(Cond, MVT::i8), BT);
11982 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
11984 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
11989 // SSE Condition code mapping:
11998 switch (SetCCOpcode) {
11999 default: llvm_unreachable("Unexpected SETCC condition");
12001 case ISD::SETEQ: SSECC = 0; break;
12003 case ISD::SETGT: Swap = true; // Fallthrough
12005 case ISD::SETOLT: SSECC = 1; break;
12007 case ISD::SETGE: Swap = true; // Fallthrough
12009 case ISD::SETOLE: SSECC = 2; break;
12010 case ISD::SETUO: SSECC = 3; break;
12012 case ISD::SETNE: SSECC = 4; break;
12013 case ISD::SETULE: Swap = true; // Fallthrough
12014 case ISD::SETUGE: SSECC = 5; break;
12015 case ISD::SETULT: Swap = true; // Fallthrough
12016 case ISD::SETUGT: SSECC = 6; break;
12017 case ISD::SETO: SSECC = 7; break;
12019 case ISD::SETONE: SSECC = 8; break;
12022 std::swap(Op0, Op1);
12027 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12028 // ones, and then concatenate the result back.
12029 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12030 MVT VT = Op.getSimpleValueType();
12032 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12033 "Unsupported value type for operation");
12035 unsigned NumElems = VT.getVectorNumElements();
12037 SDValue CC = Op.getOperand(2);
12039 // Extract the LHS vectors
12040 SDValue LHS = Op.getOperand(0);
12041 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12042 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12044 // Extract the RHS vectors
12045 SDValue RHS = Op.getOperand(1);
12046 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12047 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12049 // Issue the operation on the smaller types and concatenate the result back
12050 MVT EltVT = VT.getVectorElementType();
12051 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12052 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12053 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12054 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12057 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12058 const X86Subtarget *Subtarget) {
12059 SDValue Op0 = Op.getOperand(0);
12060 SDValue Op1 = Op.getOperand(1);
12061 SDValue CC = Op.getOperand(2);
12062 MVT VT = Op.getSimpleValueType();
12065 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12066 Op.getValueType().getScalarType() == MVT::i1 &&
12067 "Cannot set masked compare for this operation");
12069 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12071 bool Unsigned = false;
12074 switch (SetCCOpcode) {
12075 default: llvm_unreachable("Unexpected SETCC condition");
12076 case ISD::SETNE: SSECC = 4; break;
12077 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12078 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12079 case ISD::SETLT: Swap = true; //fall-through
12080 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12081 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12082 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12083 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12084 case ISD::SETULE: Unsigned = true; //fall-through
12085 case ISD::SETLE: SSECC = 2; break;
12089 std::swap(Op0, Op1);
12091 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12092 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12093 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12094 DAG.getConstant(SSECC, MVT::i8));
12097 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12098 /// operand \p Op1. If non-trivial (for example because it's not constant)
12099 /// return an empty value.
12100 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12102 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12106 MVT VT = Op1.getSimpleValueType();
12107 MVT EVT = VT.getVectorElementType();
12108 unsigned n = VT.getVectorNumElements();
12109 SmallVector<SDValue, 8> ULTOp1;
12111 for (unsigned i = 0; i < n; ++i) {
12112 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12113 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12116 // Avoid underflow.
12117 APInt Val = Elt->getAPIntValue();
12121 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12124 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12127 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12128 SelectionDAG &DAG) {
12129 SDValue Op0 = Op.getOperand(0);
12130 SDValue Op1 = Op.getOperand(1);
12131 SDValue CC = Op.getOperand(2);
12132 MVT VT = Op.getSimpleValueType();
12133 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12134 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12139 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12140 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12143 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12144 unsigned Opc = X86ISD::CMPP;
12145 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12146 assert(VT.getVectorNumElements() <= 16);
12147 Opc = X86ISD::CMPM;
12149 // In the two special cases we can't handle, emit two comparisons.
12152 unsigned CombineOpc;
12153 if (SetCCOpcode == ISD::SETUEQ) {
12154 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12156 assert(SetCCOpcode == ISD::SETONE);
12157 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12160 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12161 DAG.getConstant(CC0, MVT::i8));
12162 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12163 DAG.getConstant(CC1, MVT::i8));
12164 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12166 // Handle all other FP comparisons here.
12167 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12168 DAG.getConstant(SSECC, MVT::i8));
12171 // Break 256-bit integer vector compare into smaller ones.
12172 if (VT.is256BitVector() && !Subtarget->hasInt256())
12173 return Lower256IntVSETCC(Op, DAG);
12175 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12176 EVT OpVT = Op1.getValueType();
12177 if (Subtarget->hasAVX512()) {
12178 if (Op1.getValueType().is512BitVector() ||
12179 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12180 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12182 // In AVX-512 architecture setcc returns mask with i1 elements,
12183 // But there is no compare instruction for i8 and i16 elements.
12184 // We are not talking about 512-bit operands in this case, these
12185 // types are illegal.
12187 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12188 OpVT.getVectorElementType().getSizeInBits() >= 8))
12189 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12190 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12193 // We are handling one of the integer comparisons here. Since SSE only has
12194 // GT and EQ comparisons for integer, swapping operands and multiple
12195 // operations may be required for some comparisons.
12197 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12198 bool Subus = false;
12200 switch (SetCCOpcode) {
12201 default: llvm_unreachable("Unexpected SETCC condition");
12202 case ISD::SETNE: Invert = true;
12203 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12204 case ISD::SETLT: Swap = true;
12205 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12206 case ISD::SETGE: Swap = true;
12207 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12208 Invert = true; break;
12209 case ISD::SETULT: Swap = true;
12210 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12211 FlipSigns = true; break;
12212 case ISD::SETUGE: Swap = true;
12213 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12214 FlipSigns = true; Invert = true; break;
12217 // Special case: Use min/max operations for SETULE/SETUGE
12218 MVT VET = VT.getVectorElementType();
12220 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12221 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12224 switch (SetCCOpcode) {
12226 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12227 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12230 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12233 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12234 if (!MinMax && hasSubus) {
12235 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12237 // t = psubus Op0, Op1
12238 // pcmpeq t, <0..0>
12239 switch (SetCCOpcode) {
12241 case ISD::SETULT: {
12242 // If the comparison is against a constant we can turn this into a
12243 // setule. With psubus, setule does not require a swap. This is
12244 // beneficial because the constant in the register is no longer
12245 // destructed as the destination so it can be hoisted out of a loop.
12246 // Only do this pre-AVX since vpcmp* is no longer destructive.
12247 if (Subtarget->hasAVX())
12249 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12250 if (ULEOp1.getNode()) {
12252 Subus = true; Invert = false; Swap = false;
12256 // Psubus is better than flip-sign because it requires no inversion.
12257 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12258 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12262 Opc = X86ISD::SUBUS;
12268 std::swap(Op0, Op1);
12270 // Check that the operation in question is available (most are plain SSE2,
12271 // but PCMPGTQ and PCMPEQQ have different requirements).
12272 if (VT == MVT::v2i64) {
12273 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12274 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12276 // First cast everything to the right type.
12277 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12278 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12280 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12281 // bits of the inputs before performing those operations. The lower
12282 // compare is always unsigned.
12285 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12287 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12288 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12289 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12290 Sign, Zero, Sign, Zero);
12292 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12293 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12295 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12296 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12297 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12299 // Create masks for only the low parts/high parts of the 64 bit integers.
12300 static const int MaskHi[] = { 1, 1, 3, 3 };
12301 static const int MaskLo[] = { 0, 0, 2, 2 };
12302 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12303 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12304 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12306 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12307 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12310 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12312 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12315 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12316 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12317 // pcmpeqd + pshufd + pand.
12318 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12320 // First cast everything to the right type.
12321 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12322 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12325 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12327 // Make sure the lower and upper halves are both all-ones.
12328 static const int Mask[] = { 1, 0, 3, 2 };
12329 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12330 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12333 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12335 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12339 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12340 // bits of the inputs before performing those operations.
12342 EVT EltVT = VT.getVectorElementType();
12343 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12344 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12345 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12348 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12350 // If the logical-not of the result is required, perform that now.
12352 Result = DAG.getNOT(dl, Result, VT);
12355 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12358 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12359 getZeroVector(VT, Subtarget, DAG, dl));
12364 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12366 MVT VT = Op.getSimpleValueType();
12368 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12370 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12371 && "SetCC type must be 8-bit or 1-bit integer");
12372 SDValue Op0 = Op.getOperand(0);
12373 SDValue Op1 = Op.getOperand(1);
12375 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12377 // Optimize to BT if possible.
12378 // Lower (X & (1 << N)) == 0 to BT(X, N).
12379 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12380 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12381 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12382 Op1.getOpcode() == ISD::Constant &&
12383 cast<ConstantSDNode>(Op1)->isNullValue() &&
12384 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12385 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12386 if (NewSetCC.getNode())
12390 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12392 if (Op1.getOpcode() == ISD::Constant &&
12393 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12394 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12395 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12397 // If the input is a setcc, then reuse the input setcc or use a new one with
12398 // the inverted condition.
12399 if (Op0.getOpcode() == X86ISD::SETCC) {
12400 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12401 bool Invert = (CC == ISD::SETNE) ^
12402 cast<ConstantSDNode>(Op1)->isNullValue();
12406 CCode = X86::GetOppositeBranchCondition(CCode);
12407 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12408 DAG.getConstant(CCode, MVT::i8),
12409 Op0.getOperand(1));
12411 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12415 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12416 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12417 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12419 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12420 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12423 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12424 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12425 if (X86CC == X86::COND_INVALID)
12428 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12429 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12430 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12431 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12433 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12437 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12438 static bool isX86LogicalCmp(SDValue Op) {
12439 unsigned Opc = Op.getNode()->getOpcode();
12440 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12441 Opc == X86ISD::SAHF)
12443 if (Op.getResNo() == 1 &&
12444 (Opc == X86ISD::ADD ||
12445 Opc == X86ISD::SUB ||
12446 Opc == X86ISD::ADC ||
12447 Opc == X86ISD::SBB ||
12448 Opc == X86ISD::SMUL ||
12449 Opc == X86ISD::UMUL ||
12450 Opc == X86ISD::INC ||
12451 Opc == X86ISD::DEC ||
12452 Opc == X86ISD::OR ||
12453 Opc == X86ISD::XOR ||
12454 Opc == X86ISD::AND))
12457 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12463 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12464 if (V.getOpcode() != ISD::TRUNCATE)
12467 SDValue VOp0 = V.getOperand(0);
12468 unsigned InBits = VOp0.getValueSizeInBits();
12469 unsigned Bits = V.getValueSizeInBits();
12470 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12473 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12474 bool addTest = true;
12475 SDValue Cond = Op.getOperand(0);
12476 SDValue Op1 = Op.getOperand(1);
12477 SDValue Op2 = Op.getOperand(2);
12479 EVT VT = Op1.getValueType();
12482 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12483 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12484 // sequence later on.
12485 if (Cond.getOpcode() == ISD::SETCC &&
12486 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12487 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12488 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12489 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12490 int SSECC = translateX86FSETCC(
12491 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12494 if (Subtarget->hasAVX512()) {
12495 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12496 DAG.getConstant(SSECC, MVT::i8));
12497 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12499 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12500 DAG.getConstant(SSECC, MVT::i8));
12501 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12502 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12503 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12507 if (Cond.getOpcode() == ISD::SETCC) {
12508 SDValue NewCond = LowerSETCC(Cond, DAG);
12509 if (NewCond.getNode())
12513 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12514 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12515 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12516 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12517 if (Cond.getOpcode() == X86ISD::SETCC &&
12518 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12519 isZero(Cond.getOperand(1).getOperand(1))) {
12520 SDValue Cmp = Cond.getOperand(1);
12522 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12524 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12525 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12526 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12528 SDValue CmpOp0 = Cmp.getOperand(0);
12529 // Apply further optimizations for special cases
12530 // (select (x != 0), -1, 0) -> neg & sbb
12531 // (select (x == 0), 0, -1) -> neg & sbb
12532 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12533 if (YC->isNullValue() &&
12534 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12535 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12536 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12537 DAG.getConstant(0, CmpOp0.getValueType()),
12539 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12540 DAG.getConstant(X86::COND_B, MVT::i8),
12541 SDValue(Neg.getNode(), 1));
12545 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12546 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12547 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12549 SDValue Res = // Res = 0 or -1.
12550 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12551 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12553 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12554 Res = DAG.getNOT(DL, Res, Res.getValueType());
12556 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12557 if (!N2C || !N2C->isNullValue())
12558 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12563 // Look past (and (setcc_carry (cmp ...)), 1).
12564 if (Cond.getOpcode() == ISD::AND &&
12565 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12566 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12567 if (C && C->getAPIntValue() == 1)
12568 Cond = Cond.getOperand(0);
12571 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12572 // setting operand in place of the X86ISD::SETCC.
12573 unsigned CondOpcode = Cond.getOpcode();
12574 if (CondOpcode == X86ISD::SETCC ||
12575 CondOpcode == X86ISD::SETCC_CARRY) {
12576 CC = Cond.getOperand(0);
12578 SDValue Cmp = Cond.getOperand(1);
12579 unsigned Opc = Cmp.getOpcode();
12580 MVT VT = Op.getSimpleValueType();
12582 bool IllegalFPCMov = false;
12583 if (VT.isFloatingPoint() && !VT.isVector() &&
12584 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12585 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12587 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12588 Opc == X86ISD::BT) { // FIXME
12592 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12593 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12594 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12595 Cond.getOperand(0).getValueType() != MVT::i8)) {
12596 SDValue LHS = Cond.getOperand(0);
12597 SDValue RHS = Cond.getOperand(1);
12598 unsigned X86Opcode;
12601 switch (CondOpcode) {
12602 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12603 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12604 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12605 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12606 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12607 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12608 default: llvm_unreachable("unexpected overflowing operator");
12610 if (CondOpcode == ISD::UMULO)
12611 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12614 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12616 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12618 if (CondOpcode == ISD::UMULO)
12619 Cond = X86Op.getValue(2);
12621 Cond = X86Op.getValue(1);
12623 CC = DAG.getConstant(X86Cond, MVT::i8);
12628 // Look pass the truncate if the high bits are known zero.
12629 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12630 Cond = Cond.getOperand(0);
12632 // We know the result of AND is compared against zero. Try to match
12634 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12635 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12636 if (NewSetCC.getNode()) {
12637 CC = NewSetCC.getOperand(0);
12638 Cond = NewSetCC.getOperand(1);
12645 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12646 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12649 // a < b ? -1 : 0 -> RES = ~setcc_carry
12650 // a < b ? 0 : -1 -> RES = setcc_carry
12651 // a >= b ? -1 : 0 -> RES = setcc_carry
12652 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12653 if (Cond.getOpcode() == X86ISD::SUB) {
12654 Cond = ConvertCmpIfNecessary(Cond, DAG);
12655 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12657 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12658 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12659 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12660 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12661 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12662 return DAG.getNOT(DL, Res, Res.getValueType());
12667 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12668 // widen the cmov and push the truncate through. This avoids introducing a new
12669 // branch during isel and doesn't add any extensions.
12670 if (Op.getValueType() == MVT::i8 &&
12671 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12672 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12673 if (T1.getValueType() == T2.getValueType() &&
12674 // Blacklist CopyFromReg to avoid partial register stalls.
12675 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12676 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12677 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12678 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12682 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12683 // condition is true.
12684 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12685 SDValue Ops[] = { Op2, Op1, CC, Cond };
12686 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12689 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
12690 MVT VT = Op->getSimpleValueType(0);
12691 SDValue In = Op->getOperand(0);
12692 MVT InVT = In.getSimpleValueType();
12695 unsigned int NumElts = VT.getVectorNumElements();
12696 if (NumElts != 8 && NumElts != 16)
12699 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12700 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12703 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12705 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
12706 Constant *C = ConstantInt::get(*DAG.getContext(),
12707 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
12709 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12710 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12711 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
12712 MachinePointerInfo::getConstantPool(),
12713 false, false, false, Alignment);
12714 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
12715 if (VT.is512BitVector())
12717 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
12720 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12721 SelectionDAG &DAG) {
12722 MVT VT = Op->getSimpleValueType(0);
12723 SDValue In = Op->getOperand(0);
12724 MVT InVT = In.getSimpleValueType();
12727 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12728 return LowerSIGN_EXTEND_AVX512(Op, DAG);
12730 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
12731 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
12732 (VT != MVT::v16i16 || InVT != MVT::v16i8))
12735 if (Subtarget->hasInt256())
12736 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12738 // Optimize vectors in AVX mode
12739 // Sign extend v8i16 to v8i32 and
12742 // Divide input vector into two parts
12743 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
12744 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
12745 // concat the vectors to original VT
12747 unsigned NumElems = InVT.getVectorNumElements();
12748 SDValue Undef = DAG.getUNDEF(InVT);
12750 SmallVector<int,8> ShufMask1(NumElems, -1);
12751 for (unsigned i = 0; i != NumElems/2; ++i)
12754 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
12756 SmallVector<int,8> ShufMask2(NumElems, -1);
12757 for (unsigned i = 0; i != NumElems/2; ++i)
12758 ShufMask2[i] = i + NumElems/2;
12760 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
12762 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
12763 VT.getVectorNumElements()/2);
12765 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
12766 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
12768 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12771 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
12772 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
12773 // from the AND / OR.
12774 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
12775 Opc = Op.getOpcode();
12776 if (Opc != ISD::OR && Opc != ISD::AND)
12778 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12779 Op.getOperand(0).hasOneUse() &&
12780 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
12781 Op.getOperand(1).hasOneUse());
12784 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
12785 // 1 and that the SETCC node has a single use.
12786 static bool isXor1OfSetCC(SDValue Op) {
12787 if (Op.getOpcode() != ISD::XOR)
12789 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12790 if (N1C && N1C->getAPIntValue() == 1) {
12791 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12792 Op.getOperand(0).hasOneUse();
12797 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
12798 bool addTest = true;
12799 SDValue Chain = Op.getOperand(0);
12800 SDValue Cond = Op.getOperand(1);
12801 SDValue Dest = Op.getOperand(2);
12804 bool Inverted = false;
12806 if (Cond.getOpcode() == ISD::SETCC) {
12807 // Check for setcc([su]{add,sub,mul}o == 0).
12808 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
12809 isa<ConstantSDNode>(Cond.getOperand(1)) &&
12810 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
12811 Cond.getOperand(0).getResNo() == 1 &&
12812 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
12813 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
12814 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
12815 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
12816 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
12817 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
12819 Cond = Cond.getOperand(0);
12821 SDValue NewCond = LowerSETCC(Cond, DAG);
12822 if (NewCond.getNode())
12827 // FIXME: LowerXALUO doesn't handle these!!
12828 else if (Cond.getOpcode() == X86ISD::ADD ||
12829 Cond.getOpcode() == X86ISD::SUB ||
12830 Cond.getOpcode() == X86ISD::SMUL ||
12831 Cond.getOpcode() == X86ISD::UMUL)
12832 Cond = LowerXALUO(Cond, DAG);
12835 // Look pass (and (setcc_carry (cmp ...)), 1).
12836 if (Cond.getOpcode() == ISD::AND &&
12837 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12838 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12839 if (C && C->getAPIntValue() == 1)
12840 Cond = Cond.getOperand(0);
12843 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12844 // setting operand in place of the X86ISD::SETCC.
12845 unsigned CondOpcode = Cond.getOpcode();
12846 if (CondOpcode == X86ISD::SETCC ||
12847 CondOpcode == X86ISD::SETCC_CARRY) {
12848 CC = Cond.getOperand(0);
12850 SDValue Cmp = Cond.getOperand(1);
12851 unsigned Opc = Cmp.getOpcode();
12852 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
12853 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
12857 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
12861 // These can only come from an arithmetic instruction with overflow,
12862 // e.g. SADDO, UADDO.
12863 Cond = Cond.getNode()->getOperand(1);
12869 CondOpcode = Cond.getOpcode();
12870 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12871 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12872 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12873 Cond.getOperand(0).getValueType() != MVT::i8)) {
12874 SDValue LHS = Cond.getOperand(0);
12875 SDValue RHS = Cond.getOperand(1);
12876 unsigned X86Opcode;
12879 // Keep this in sync with LowerXALUO, otherwise we might create redundant
12880 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
12882 switch (CondOpcode) {
12883 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12885 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12887 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
12890 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12891 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12895 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
12898 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12899 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12900 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12901 default: llvm_unreachable("unexpected overflowing operator");
12904 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
12905 if (CondOpcode == ISD::UMULO)
12906 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12909 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12911 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
12913 if (CondOpcode == ISD::UMULO)
12914 Cond = X86Op.getValue(2);
12916 Cond = X86Op.getValue(1);
12918 CC = DAG.getConstant(X86Cond, MVT::i8);
12922 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
12923 SDValue Cmp = Cond.getOperand(0).getOperand(1);
12924 if (CondOpc == ISD::OR) {
12925 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
12926 // two branches instead of an explicit OR instruction with a
12928 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12929 isX86LogicalCmp(Cmp)) {
12930 CC = Cond.getOperand(0).getOperand(0);
12931 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12932 Chain, Dest, CC, Cmp);
12933 CC = Cond.getOperand(1).getOperand(0);
12937 } else { // ISD::AND
12938 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
12939 // two branches instead of an explicit AND instruction with a
12940 // separate test. However, we only do this if this block doesn't
12941 // have a fall-through edge, because this requires an explicit
12942 // jmp when the condition is false.
12943 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12944 isX86LogicalCmp(Cmp) &&
12945 Op.getNode()->hasOneUse()) {
12946 X86::CondCode CCode =
12947 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12948 CCode = X86::GetOppositeBranchCondition(CCode);
12949 CC = DAG.getConstant(CCode, MVT::i8);
12950 SDNode *User = *Op.getNode()->use_begin();
12951 // Look for an unconditional branch following this conditional branch.
12952 // We need this because we need to reverse the successors in order
12953 // to implement FCMP_OEQ.
12954 if (User->getOpcode() == ISD::BR) {
12955 SDValue FalseBB = User->getOperand(1);
12957 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
12958 assert(NewBR == User);
12962 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12963 Chain, Dest, CC, Cmp);
12964 X86::CondCode CCode =
12965 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
12966 CCode = X86::GetOppositeBranchCondition(CCode);
12967 CC = DAG.getConstant(CCode, MVT::i8);
12973 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
12974 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
12975 // It should be transformed during dag combiner except when the condition
12976 // is set by a arithmetics with overflow node.
12977 X86::CondCode CCode =
12978 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12979 CCode = X86::GetOppositeBranchCondition(CCode);
12980 CC = DAG.getConstant(CCode, MVT::i8);
12981 Cond = Cond.getOperand(0).getOperand(1);
12983 } else if (Cond.getOpcode() == ISD::SETCC &&
12984 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
12985 // For FCMP_OEQ, we can emit
12986 // two branches instead of an explicit AND instruction with a
12987 // separate test. However, we only do this if this block doesn't
12988 // have a fall-through edge, because this requires an explicit
12989 // jmp when the condition is false.
12990 if (Op.getNode()->hasOneUse()) {
12991 SDNode *User = *Op.getNode()->use_begin();
12992 // Look for an unconditional branch following this conditional branch.
12993 // We need this because we need to reverse the successors in order
12994 // to implement FCMP_OEQ.
12995 if (User->getOpcode() == ISD::BR) {
12996 SDValue FalseBB = User->getOperand(1);
12998 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
12999 assert(NewBR == User);
13003 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13004 Cond.getOperand(0), Cond.getOperand(1));
13005 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13006 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13007 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13008 Chain, Dest, CC, Cmp);
13009 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13014 } else if (Cond.getOpcode() == ISD::SETCC &&
13015 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13016 // For FCMP_UNE, we can emit
13017 // two branches instead of an explicit AND instruction with a
13018 // separate test. However, we only do this if this block doesn't
13019 // have a fall-through edge, because this requires an explicit
13020 // jmp when the condition is false.
13021 if (Op.getNode()->hasOneUse()) {
13022 SDNode *User = *Op.getNode()->use_begin();
13023 // Look for an unconditional branch following this conditional branch.
13024 // We need this because we need to reverse the successors in order
13025 // to implement FCMP_UNE.
13026 if (User->getOpcode() == ISD::BR) {
13027 SDValue FalseBB = User->getOperand(1);
13029 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13030 assert(NewBR == User);
13033 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13034 Cond.getOperand(0), Cond.getOperand(1));
13035 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13036 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13037 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13038 Chain, Dest, CC, Cmp);
13039 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13049 // Look pass the truncate if the high bits are known zero.
13050 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13051 Cond = Cond.getOperand(0);
13053 // We know the result of AND is compared against zero. Try to match
13055 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13056 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13057 if (NewSetCC.getNode()) {
13058 CC = NewSetCC.getOperand(0);
13059 Cond = NewSetCC.getOperand(1);
13066 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13067 CC = DAG.getConstant(X86Cond, MVT::i8);
13068 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13070 Cond = ConvertCmpIfNecessary(Cond, DAG);
13071 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13072 Chain, Dest, CC, Cond);
13075 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13076 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13077 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13078 // that the guard pages used by the OS virtual memory manager are allocated in
13079 // correct sequence.
13081 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13082 SelectionDAG &DAG) const {
13083 MachineFunction &MF = DAG.getMachineFunction();
13084 bool SplitStack = MF.shouldSplitStack();
13085 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13091 SDNode* Node = Op.getNode();
13093 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13094 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13095 " not tell us which reg is the stack pointer!");
13096 EVT VT = Node->getValueType(0);
13097 SDValue Tmp1 = SDValue(Node, 0);
13098 SDValue Tmp2 = SDValue(Node, 1);
13099 SDValue Tmp3 = Node->getOperand(2);
13100 SDValue Chain = Tmp1.getOperand(0);
13102 // Chain the dynamic stack allocation so that it doesn't modify the stack
13103 // pointer when other instructions are using the stack.
13104 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13107 SDValue Size = Tmp2.getOperand(1);
13108 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13109 Chain = SP.getValue(1);
13110 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13111 const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
13112 unsigned StackAlign = TFI.getStackAlignment();
13113 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13114 if (Align > StackAlign)
13115 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13116 DAG.getConstant(-(uint64_t)Align, VT));
13117 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13119 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13120 DAG.getIntPtrConstant(0, true), SDValue(),
13123 SDValue Ops[2] = { Tmp1, Tmp2 };
13124 return DAG.getMergeValues(Ops, dl);
13128 SDValue Chain = Op.getOperand(0);
13129 SDValue Size = Op.getOperand(1);
13130 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13131 EVT VT = Op.getNode()->getValueType(0);
13133 bool Is64Bit = Subtarget->is64Bit();
13134 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13137 MachineRegisterInfo &MRI = MF.getRegInfo();
13140 // The 64 bit implementation of segmented stacks needs to clobber both r10
13141 // r11. This makes it impossible to use it along with nested parameters.
13142 const Function *F = MF.getFunction();
13144 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13146 if (I->hasNestAttr())
13147 report_fatal_error("Cannot use segmented stacks with functions that "
13148 "have nested arguments.");
13151 const TargetRegisterClass *AddrRegClass =
13152 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13153 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13154 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13155 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13156 DAG.getRegister(Vreg, SPTy));
13157 SDValue Ops1[2] = { Value, Chain };
13158 return DAG.getMergeValues(Ops1, dl);
13161 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13163 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13164 Flag = Chain.getValue(1);
13165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13167 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13169 const X86RegisterInfo *RegInfo =
13170 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
13171 unsigned SPReg = RegInfo->getStackRegister();
13172 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13173 Chain = SP.getValue(1);
13176 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13177 DAG.getConstant(-(uint64_t)Align, VT));
13178 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13181 SDValue Ops1[2] = { SP, Chain };
13182 return DAG.getMergeValues(Ops1, dl);
13186 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13187 MachineFunction &MF = DAG.getMachineFunction();
13188 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13190 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13193 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13194 // vastart just stores the address of the VarArgsFrameIndex slot into the
13195 // memory location argument.
13196 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13198 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13199 MachinePointerInfo(SV), false, false, 0);
13203 // gp_offset (0 - 6 * 8)
13204 // fp_offset (48 - 48 + 8 * 16)
13205 // overflow_arg_area (point to parameters coming in memory).
13207 SmallVector<SDValue, 8> MemOps;
13208 SDValue FIN = Op.getOperand(1);
13210 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13211 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13213 FIN, MachinePointerInfo(SV), false, false, 0);
13214 MemOps.push_back(Store);
13217 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13218 FIN, DAG.getIntPtrConstant(4));
13219 Store = DAG.getStore(Op.getOperand(0), DL,
13220 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13222 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13223 MemOps.push_back(Store);
13225 // Store ptr to overflow_arg_area
13226 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13227 FIN, DAG.getIntPtrConstant(4));
13228 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13230 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13231 MachinePointerInfo(SV, 8),
13233 MemOps.push_back(Store);
13235 // Store ptr to reg_save_area.
13236 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13237 FIN, DAG.getIntPtrConstant(8));
13238 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13240 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13241 MachinePointerInfo(SV, 16), false, false, 0);
13242 MemOps.push_back(Store);
13243 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13246 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13247 assert(Subtarget->is64Bit() &&
13248 "LowerVAARG only handles 64-bit va_arg!");
13249 assert((Subtarget->isTargetLinux() ||
13250 Subtarget->isTargetDarwin()) &&
13251 "Unhandled target in LowerVAARG");
13252 assert(Op.getNode()->getNumOperands() == 4);
13253 SDValue Chain = Op.getOperand(0);
13254 SDValue SrcPtr = Op.getOperand(1);
13255 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13256 unsigned Align = Op.getConstantOperandVal(3);
13259 EVT ArgVT = Op.getNode()->getValueType(0);
13260 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13261 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13264 // Decide which area this value should be read from.
13265 // TODO: Implement the AMD64 ABI in its entirety. This simple
13266 // selection mechanism works only for the basic types.
13267 if (ArgVT == MVT::f80) {
13268 llvm_unreachable("va_arg for f80 not yet implemented");
13269 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13270 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13271 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13272 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13274 llvm_unreachable("Unhandled argument type in LowerVAARG");
13277 if (ArgMode == 2) {
13278 // Sanity Check: Make sure using fp_offset makes sense.
13279 assert(!DAG.getTarget().Options.UseSoftFloat &&
13280 !(DAG.getMachineFunction()
13281 .getFunction()->getAttributes()
13282 .hasAttribute(AttributeSet::FunctionIndex,
13283 Attribute::NoImplicitFloat)) &&
13284 Subtarget->hasSSE1());
13287 // Insert VAARG_64 node into the DAG
13288 // VAARG_64 returns two values: Variable Argument Address, Chain
13289 SmallVector<SDValue, 11> InstOps;
13290 InstOps.push_back(Chain);
13291 InstOps.push_back(SrcPtr);
13292 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13293 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13294 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13295 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13296 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13297 VTs, InstOps, MVT::i64,
13298 MachinePointerInfo(SV),
13300 /*Volatile=*/false,
13302 /*WriteMem=*/true);
13303 Chain = VAARG.getValue(1);
13305 // Load the next argument and return it
13306 return DAG.getLoad(ArgVT, dl,
13309 MachinePointerInfo(),
13310 false, false, false, 0);
13313 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13314 SelectionDAG &DAG) {
13315 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13316 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13317 SDValue Chain = Op.getOperand(0);
13318 SDValue DstPtr = Op.getOperand(1);
13319 SDValue SrcPtr = Op.getOperand(2);
13320 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13321 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13324 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13325 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13327 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13330 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13331 // amount is a constant. Takes immediate version of shift as input.
13332 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13333 SDValue SrcOp, uint64_t ShiftAmt,
13334 SelectionDAG &DAG) {
13335 MVT ElementType = VT.getVectorElementType();
13337 // Fold this packed shift into its first operand if ShiftAmt is 0.
13341 // Check for ShiftAmt >= element width
13342 if (ShiftAmt >= ElementType.getSizeInBits()) {
13343 if (Opc == X86ISD::VSRAI)
13344 ShiftAmt = ElementType.getSizeInBits() - 1;
13346 return DAG.getConstant(0, VT);
13349 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13350 && "Unknown target vector shift-by-constant node");
13352 // Fold this packed vector shift into a build vector if SrcOp is a
13353 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13354 if (VT == SrcOp.getSimpleValueType() &&
13355 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13356 SmallVector<SDValue, 8> Elts;
13357 unsigned NumElts = SrcOp->getNumOperands();
13358 ConstantSDNode *ND;
13361 default: llvm_unreachable(nullptr);
13362 case X86ISD::VSHLI:
13363 for (unsigned i=0; i!=NumElts; ++i) {
13364 SDValue CurrentOp = SrcOp->getOperand(i);
13365 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13366 Elts.push_back(CurrentOp);
13369 ND = cast<ConstantSDNode>(CurrentOp);
13370 const APInt &C = ND->getAPIntValue();
13371 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13374 case X86ISD::VSRLI:
13375 for (unsigned i=0; i!=NumElts; ++i) {
13376 SDValue CurrentOp = SrcOp->getOperand(i);
13377 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13378 Elts.push_back(CurrentOp);
13381 ND = cast<ConstantSDNode>(CurrentOp);
13382 const APInt &C = ND->getAPIntValue();
13383 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13386 case X86ISD::VSRAI:
13387 for (unsigned i=0; i!=NumElts; ++i) {
13388 SDValue CurrentOp = SrcOp->getOperand(i);
13389 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13390 Elts.push_back(CurrentOp);
13393 ND = cast<ConstantSDNode>(CurrentOp);
13394 const APInt &C = ND->getAPIntValue();
13395 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13400 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13403 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13406 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13407 // may or may not be a constant. Takes immediate version of shift as input.
13408 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13409 SDValue SrcOp, SDValue ShAmt,
13410 SelectionDAG &DAG) {
13411 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13413 // Catch shift-by-constant.
13414 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13415 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13416 CShAmt->getZExtValue(), DAG);
13418 // Change opcode to non-immediate version
13420 default: llvm_unreachable("Unknown target vector shift node");
13421 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13422 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13423 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13426 // Need to build a vector containing shift amount
13427 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13430 ShOps[1] = DAG.getConstant(0, MVT::i32);
13431 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13432 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13434 // The return type has to be a 128-bit type with the same element
13435 // type as the input type.
13436 MVT EltVT = VT.getVectorElementType();
13437 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13439 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13440 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13443 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13445 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13447 default: return SDValue(); // Don't custom lower most intrinsics.
13448 // Comparison intrinsics.
13449 case Intrinsic::x86_sse_comieq_ss:
13450 case Intrinsic::x86_sse_comilt_ss:
13451 case Intrinsic::x86_sse_comile_ss:
13452 case Intrinsic::x86_sse_comigt_ss:
13453 case Intrinsic::x86_sse_comige_ss:
13454 case Intrinsic::x86_sse_comineq_ss:
13455 case Intrinsic::x86_sse_ucomieq_ss:
13456 case Intrinsic::x86_sse_ucomilt_ss:
13457 case Intrinsic::x86_sse_ucomile_ss:
13458 case Intrinsic::x86_sse_ucomigt_ss:
13459 case Intrinsic::x86_sse_ucomige_ss:
13460 case Intrinsic::x86_sse_ucomineq_ss:
13461 case Intrinsic::x86_sse2_comieq_sd:
13462 case Intrinsic::x86_sse2_comilt_sd:
13463 case Intrinsic::x86_sse2_comile_sd:
13464 case Intrinsic::x86_sse2_comigt_sd:
13465 case Intrinsic::x86_sse2_comige_sd:
13466 case Intrinsic::x86_sse2_comineq_sd:
13467 case Intrinsic::x86_sse2_ucomieq_sd:
13468 case Intrinsic::x86_sse2_ucomilt_sd:
13469 case Intrinsic::x86_sse2_ucomile_sd:
13470 case Intrinsic::x86_sse2_ucomigt_sd:
13471 case Intrinsic::x86_sse2_ucomige_sd:
13472 case Intrinsic::x86_sse2_ucomineq_sd: {
13476 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13477 case Intrinsic::x86_sse_comieq_ss:
13478 case Intrinsic::x86_sse2_comieq_sd:
13479 Opc = X86ISD::COMI;
13482 case Intrinsic::x86_sse_comilt_ss:
13483 case Intrinsic::x86_sse2_comilt_sd:
13484 Opc = X86ISD::COMI;
13487 case Intrinsic::x86_sse_comile_ss:
13488 case Intrinsic::x86_sse2_comile_sd:
13489 Opc = X86ISD::COMI;
13492 case Intrinsic::x86_sse_comigt_ss:
13493 case Intrinsic::x86_sse2_comigt_sd:
13494 Opc = X86ISD::COMI;
13497 case Intrinsic::x86_sse_comige_ss:
13498 case Intrinsic::x86_sse2_comige_sd:
13499 Opc = X86ISD::COMI;
13502 case Intrinsic::x86_sse_comineq_ss:
13503 case Intrinsic::x86_sse2_comineq_sd:
13504 Opc = X86ISD::COMI;
13507 case Intrinsic::x86_sse_ucomieq_ss:
13508 case Intrinsic::x86_sse2_ucomieq_sd:
13509 Opc = X86ISD::UCOMI;
13512 case Intrinsic::x86_sse_ucomilt_ss:
13513 case Intrinsic::x86_sse2_ucomilt_sd:
13514 Opc = X86ISD::UCOMI;
13517 case Intrinsic::x86_sse_ucomile_ss:
13518 case Intrinsic::x86_sse2_ucomile_sd:
13519 Opc = X86ISD::UCOMI;
13522 case Intrinsic::x86_sse_ucomigt_ss:
13523 case Intrinsic::x86_sse2_ucomigt_sd:
13524 Opc = X86ISD::UCOMI;
13527 case Intrinsic::x86_sse_ucomige_ss:
13528 case Intrinsic::x86_sse2_ucomige_sd:
13529 Opc = X86ISD::UCOMI;
13532 case Intrinsic::x86_sse_ucomineq_ss:
13533 case Intrinsic::x86_sse2_ucomineq_sd:
13534 Opc = X86ISD::UCOMI;
13539 SDValue LHS = Op.getOperand(1);
13540 SDValue RHS = Op.getOperand(2);
13541 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
13542 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
13543 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
13544 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13545 DAG.getConstant(X86CC, MVT::i8), Cond);
13546 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13549 // Arithmetic intrinsics.
13550 case Intrinsic::x86_sse2_pmulu_dq:
13551 case Intrinsic::x86_avx2_pmulu_dq:
13552 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
13553 Op.getOperand(1), Op.getOperand(2));
13555 case Intrinsic::x86_sse41_pmuldq:
13556 case Intrinsic::x86_avx2_pmul_dq:
13557 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
13558 Op.getOperand(1), Op.getOperand(2));
13560 case Intrinsic::x86_sse2_pmulhu_w:
13561 case Intrinsic::x86_avx2_pmulhu_w:
13562 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
13563 Op.getOperand(1), Op.getOperand(2));
13565 case Intrinsic::x86_sse2_pmulh_w:
13566 case Intrinsic::x86_avx2_pmulh_w:
13567 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
13568 Op.getOperand(1), Op.getOperand(2));
13570 // SSE2/AVX2 sub with unsigned saturation intrinsics
13571 case Intrinsic::x86_sse2_psubus_b:
13572 case Intrinsic::x86_sse2_psubus_w:
13573 case Intrinsic::x86_avx2_psubus_b:
13574 case Intrinsic::x86_avx2_psubus_w:
13575 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
13576 Op.getOperand(1), Op.getOperand(2));
13578 // SSE3/AVX horizontal add/sub intrinsics
13579 case Intrinsic::x86_sse3_hadd_ps:
13580 case Intrinsic::x86_sse3_hadd_pd:
13581 case Intrinsic::x86_avx_hadd_ps_256:
13582 case Intrinsic::x86_avx_hadd_pd_256:
13583 case Intrinsic::x86_sse3_hsub_ps:
13584 case Intrinsic::x86_sse3_hsub_pd:
13585 case Intrinsic::x86_avx_hsub_ps_256:
13586 case Intrinsic::x86_avx_hsub_pd_256:
13587 case Intrinsic::x86_ssse3_phadd_w_128:
13588 case Intrinsic::x86_ssse3_phadd_d_128:
13589 case Intrinsic::x86_avx2_phadd_w:
13590 case Intrinsic::x86_avx2_phadd_d:
13591 case Intrinsic::x86_ssse3_phsub_w_128:
13592 case Intrinsic::x86_ssse3_phsub_d_128:
13593 case Intrinsic::x86_avx2_phsub_w:
13594 case Intrinsic::x86_avx2_phsub_d: {
13597 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13598 case Intrinsic::x86_sse3_hadd_ps:
13599 case Intrinsic::x86_sse3_hadd_pd:
13600 case Intrinsic::x86_avx_hadd_ps_256:
13601 case Intrinsic::x86_avx_hadd_pd_256:
13602 Opcode = X86ISD::FHADD;
13604 case Intrinsic::x86_sse3_hsub_ps:
13605 case Intrinsic::x86_sse3_hsub_pd:
13606 case Intrinsic::x86_avx_hsub_ps_256:
13607 case Intrinsic::x86_avx_hsub_pd_256:
13608 Opcode = X86ISD::FHSUB;
13610 case Intrinsic::x86_ssse3_phadd_w_128:
13611 case Intrinsic::x86_ssse3_phadd_d_128:
13612 case Intrinsic::x86_avx2_phadd_w:
13613 case Intrinsic::x86_avx2_phadd_d:
13614 Opcode = X86ISD::HADD;
13616 case Intrinsic::x86_ssse3_phsub_w_128:
13617 case Intrinsic::x86_ssse3_phsub_d_128:
13618 case Intrinsic::x86_avx2_phsub_w:
13619 case Intrinsic::x86_avx2_phsub_d:
13620 Opcode = X86ISD::HSUB;
13623 return DAG.getNode(Opcode, dl, Op.getValueType(),
13624 Op.getOperand(1), Op.getOperand(2));
13627 // SSE2/SSE41/AVX2 integer max/min intrinsics.
13628 case Intrinsic::x86_sse2_pmaxu_b:
13629 case Intrinsic::x86_sse41_pmaxuw:
13630 case Intrinsic::x86_sse41_pmaxud:
13631 case Intrinsic::x86_avx2_pmaxu_b:
13632 case Intrinsic::x86_avx2_pmaxu_w:
13633 case Intrinsic::x86_avx2_pmaxu_d:
13634 case Intrinsic::x86_sse2_pminu_b:
13635 case Intrinsic::x86_sse41_pminuw:
13636 case Intrinsic::x86_sse41_pminud:
13637 case Intrinsic::x86_avx2_pminu_b:
13638 case Intrinsic::x86_avx2_pminu_w:
13639 case Intrinsic::x86_avx2_pminu_d:
13640 case Intrinsic::x86_sse41_pmaxsb:
13641 case Intrinsic::x86_sse2_pmaxs_w:
13642 case Intrinsic::x86_sse41_pmaxsd:
13643 case Intrinsic::x86_avx2_pmaxs_b:
13644 case Intrinsic::x86_avx2_pmaxs_w:
13645 case Intrinsic::x86_avx2_pmaxs_d:
13646 case Intrinsic::x86_sse41_pminsb:
13647 case Intrinsic::x86_sse2_pmins_w:
13648 case Intrinsic::x86_sse41_pminsd:
13649 case Intrinsic::x86_avx2_pmins_b:
13650 case Intrinsic::x86_avx2_pmins_w:
13651 case Intrinsic::x86_avx2_pmins_d: {
13654 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13655 case Intrinsic::x86_sse2_pmaxu_b:
13656 case Intrinsic::x86_sse41_pmaxuw:
13657 case Intrinsic::x86_sse41_pmaxud:
13658 case Intrinsic::x86_avx2_pmaxu_b:
13659 case Intrinsic::x86_avx2_pmaxu_w:
13660 case Intrinsic::x86_avx2_pmaxu_d:
13661 Opcode = X86ISD::UMAX;
13663 case Intrinsic::x86_sse2_pminu_b:
13664 case Intrinsic::x86_sse41_pminuw:
13665 case Intrinsic::x86_sse41_pminud:
13666 case Intrinsic::x86_avx2_pminu_b:
13667 case Intrinsic::x86_avx2_pminu_w:
13668 case Intrinsic::x86_avx2_pminu_d:
13669 Opcode = X86ISD::UMIN;
13671 case Intrinsic::x86_sse41_pmaxsb:
13672 case Intrinsic::x86_sse2_pmaxs_w:
13673 case Intrinsic::x86_sse41_pmaxsd:
13674 case Intrinsic::x86_avx2_pmaxs_b:
13675 case Intrinsic::x86_avx2_pmaxs_w:
13676 case Intrinsic::x86_avx2_pmaxs_d:
13677 Opcode = X86ISD::SMAX;
13679 case Intrinsic::x86_sse41_pminsb:
13680 case Intrinsic::x86_sse2_pmins_w:
13681 case Intrinsic::x86_sse41_pminsd:
13682 case Intrinsic::x86_avx2_pmins_b:
13683 case Intrinsic::x86_avx2_pmins_w:
13684 case Intrinsic::x86_avx2_pmins_d:
13685 Opcode = X86ISD::SMIN;
13688 return DAG.getNode(Opcode, dl, Op.getValueType(),
13689 Op.getOperand(1), Op.getOperand(2));
13692 // SSE/SSE2/AVX floating point max/min intrinsics.
13693 case Intrinsic::x86_sse_max_ps:
13694 case Intrinsic::x86_sse2_max_pd:
13695 case Intrinsic::x86_avx_max_ps_256:
13696 case Intrinsic::x86_avx_max_pd_256:
13697 case Intrinsic::x86_sse_min_ps:
13698 case Intrinsic::x86_sse2_min_pd:
13699 case Intrinsic::x86_avx_min_ps_256:
13700 case Intrinsic::x86_avx_min_pd_256: {
13703 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13704 case Intrinsic::x86_sse_max_ps:
13705 case Intrinsic::x86_sse2_max_pd:
13706 case Intrinsic::x86_avx_max_ps_256:
13707 case Intrinsic::x86_avx_max_pd_256:
13708 Opcode = X86ISD::FMAX;
13710 case Intrinsic::x86_sse_min_ps:
13711 case Intrinsic::x86_sse2_min_pd:
13712 case Intrinsic::x86_avx_min_ps_256:
13713 case Intrinsic::x86_avx_min_pd_256:
13714 Opcode = X86ISD::FMIN;
13717 return DAG.getNode(Opcode, dl, Op.getValueType(),
13718 Op.getOperand(1), Op.getOperand(2));
13721 // AVX2 variable shift intrinsics
13722 case Intrinsic::x86_avx2_psllv_d:
13723 case Intrinsic::x86_avx2_psllv_q:
13724 case Intrinsic::x86_avx2_psllv_d_256:
13725 case Intrinsic::x86_avx2_psllv_q_256:
13726 case Intrinsic::x86_avx2_psrlv_d:
13727 case Intrinsic::x86_avx2_psrlv_q:
13728 case Intrinsic::x86_avx2_psrlv_d_256:
13729 case Intrinsic::x86_avx2_psrlv_q_256:
13730 case Intrinsic::x86_avx2_psrav_d:
13731 case Intrinsic::x86_avx2_psrav_d_256: {
13734 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13735 case Intrinsic::x86_avx2_psllv_d:
13736 case Intrinsic::x86_avx2_psllv_q:
13737 case Intrinsic::x86_avx2_psllv_d_256:
13738 case Intrinsic::x86_avx2_psllv_q_256:
13741 case Intrinsic::x86_avx2_psrlv_d:
13742 case Intrinsic::x86_avx2_psrlv_q:
13743 case Intrinsic::x86_avx2_psrlv_d_256:
13744 case Intrinsic::x86_avx2_psrlv_q_256:
13747 case Intrinsic::x86_avx2_psrav_d:
13748 case Intrinsic::x86_avx2_psrav_d_256:
13752 return DAG.getNode(Opcode, dl, Op.getValueType(),
13753 Op.getOperand(1), Op.getOperand(2));
13756 case Intrinsic::x86_sse2_packssdw_128:
13757 case Intrinsic::x86_sse2_packsswb_128:
13758 case Intrinsic::x86_avx2_packssdw:
13759 case Intrinsic::x86_avx2_packsswb:
13760 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
13761 Op.getOperand(1), Op.getOperand(2));
13763 case Intrinsic::x86_sse2_packuswb_128:
13764 case Intrinsic::x86_sse41_packusdw:
13765 case Intrinsic::x86_avx2_packuswb:
13766 case Intrinsic::x86_avx2_packusdw:
13767 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
13768 Op.getOperand(1), Op.getOperand(2));
13770 case Intrinsic::x86_ssse3_pshuf_b_128:
13771 case Intrinsic::x86_avx2_pshuf_b:
13772 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
13773 Op.getOperand(1), Op.getOperand(2));
13775 case Intrinsic::x86_sse2_pshuf_d:
13776 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
13777 Op.getOperand(1), Op.getOperand(2));
13779 case Intrinsic::x86_sse2_pshufl_w:
13780 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
13781 Op.getOperand(1), Op.getOperand(2));
13783 case Intrinsic::x86_sse2_pshufh_w:
13784 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
13785 Op.getOperand(1), Op.getOperand(2));
13787 case Intrinsic::x86_ssse3_psign_b_128:
13788 case Intrinsic::x86_ssse3_psign_w_128:
13789 case Intrinsic::x86_ssse3_psign_d_128:
13790 case Intrinsic::x86_avx2_psign_b:
13791 case Intrinsic::x86_avx2_psign_w:
13792 case Intrinsic::x86_avx2_psign_d:
13793 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
13794 Op.getOperand(1), Op.getOperand(2));
13796 case Intrinsic::x86_sse41_insertps:
13797 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
13798 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13800 case Intrinsic::x86_avx_vperm2f128_ps_256:
13801 case Intrinsic::x86_avx_vperm2f128_pd_256:
13802 case Intrinsic::x86_avx_vperm2f128_si_256:
13803 case Intrinsic::x86_avx2_vperm2i128:
13804 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
13805 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13807 case Intrinsic::x86_avx2_permd:
13808 case Intrinsic::x86_avx2_permps:
13809 // Operands intentionally swapped. Mask is last operand to intrinsic,
13810 // but second operand for node/instruction.
13811 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
13812 Op.getOperand(2), Op.getOperand(1));
13814 case Intrinsic::x86_sse_sqrt_ps:
13815 case Intrinsic::x86_sse2_sqrt_pd:
13816 case Intrinsic::x86_avx_sqrt_ps_256:
13817 case Intrinsic::x86_avx_sqrt_pd_256:
13818 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
13820 // ptest and testp intrinsics. The intrinsic these come from are designed to
13821 // return an integer value, not just an instruction so lower it to the ptest
13822 // or testp pattern and a setcc for the result.
13823 case Intrinsic::x86_sse41_ptestz:
13824 case Intrinsic::x86_sse41_ptestc:
13825 case Intrinsic::x86_sse41_ptestnzc:
13826 case Intrinsic::x86_avx_ptestz_256:
13827 case Intrinsic::x86_avx_ptestc_256:
13828 case Intrinsic::x86_avx_ptestnzc_256:
13829 case Intrinsic::x86_avx_vtestz_ps:
13830 case Intrinsic::x86_avx_vtestc_ps:
13831 case Intrinsic::x86_avx_vtestnzc_ps:
13832 case Intrinsic::x86_avx_vtestz_pd:
13833 case Intrinsic::x86_avx_vtestc_pd:
13834 case Intrinsic::x86_avx_vtestnzc_pd:
13835 case Intrinsic::x86_avx_vtestz_ps_256:
13836 case Intrinsic::x86_avx_vtestc_ps_256:
13837 case Intrinsic::x86_avx_vtestnzc_ps_256:
13838 case Intrinsic::x86_avx_vtestz_pd_256:
13839 case Intrinsic::x86_avx_vtestc_pd_256:
13840 case Intrinsic::x86_avx_vtestnzc_pd_256: {
13841 bool IsTestPacked = false;
13844 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
13845 case Intrinsic::x86_avx_vtestz_ps:
13846 case Intrinsic::x86_avx_vtestz_pd:
13847 case Intrinsic::x86_avx_vtestz_ps_256:
13848 case Intrinsic::x86_avx_vtestz_pd_256:
13849 IsTestPacked = true; // Fallthrough
13850 case Intrinsic::x86_sse41_ptestz:
13851 case Intrinsic::x86_avx_ptestz_256:
13853 X86CC = X86::COND_E;
13855 case Intrinsic::x86_avx_vtestc_ps:
13856 case Intrinsic::x86_avx_vtestc_pd:
13857 case Intrinsic::x86_avx_vtestc_ps_256:
13858 case Intrinsic::x86_avx_vtestc_pd_256:
13859 IsTestPacked = true; // Fallthrough
13860 case Intrinsic::x86_sse41_ptestc:
13861 case Intrinsic::x86_avx_ptestc_256:
13863 X86CC = X86::COND_B;
13865 case Intrinsic::x86_avx_vtestnzc_ps:
13866 case Intrinsic::x86_avx_vtestnzc_pd:
13867 case Intrinsic::x86_avx_vtestnzc_ps_256:
13868 case Intrinsic::x86_avx_vtestnzc_pd_256:
13869 IsTestPacked = true; // Fallthrough
13870 case Intrinsic::x86_sse41_ptestnzc:
13871 case Intrinsic::x86_avx_ptestnzc_256:
13873 X86CC = X86::COND_A;
13877 SDValue LHS = Op.getOperand(1);
13878 SDValue RHS = Op.getOperand(2);
13879 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
13880 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
13881 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13882 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
13883 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13885 case Intrinsic::x86_avx512_kortestz_w:
13886 case Intrinsic::x86_avx512_kortestc_w: {
13887 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
13888 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
13889 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
13890 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13891 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
13892 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
13893 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13896 // SSE/AVX shift intrinsics
13897 case Intrinsic::x86_sse2_psll_w:
13898 case Intrinsic::x86_sse2_psll_d:
13899 case Intrinsic::x86_sse2_psll_q:
13900 case Intrinsic::x86_avx2_psll_w:
13901 case Intrinsic::x86_avx2_psll_d:
13902 case Intrinsic::x86_avx2_psll_q:
13903 case Intrinsic::x86_sse2_psrl_w:
13904 case Intrinsic::x86_sse2_psrl_d:
13905 case Intrinsic::x86_sse2_psrl_q:
13906 case Intrinsic::x86_avx2_psrl_w:
13907 case Intrinsic::x86_avx2_psrl_d:
13908 case Intrinsic::x86_avx2_psrl_q:
13909 case Intrinsic::x86_sse2_psra_w:
13910 case Intrinsic::x86_sse2_psra_d:
13911 case Intrinsic::x86_avx2_psra_w:
13912 case Intrinsic::x86_avx2_psra_d: {
13915 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13916 case Intrinsic::x86_sse2_psll_w:
13917 case Intrinsic::x86_sse2_psll_d:
13918 case Intrinsic::x86_sse2_psll_q:
13919 case Intrinsic::x86_avx2_psll_w:
13920 case Intrinsic::x86_avx2_psll_d:
13921 case Intrinsic::x86_avx2_psll_q:
13922 Opcode = X86ISD::VSHL;
13924 case Intrinsic::x86_sse2_psrl_w:
13925 case Intrinsic::x86_sse2_psrl_d:
13926 case Intrinsic::x86_sse2_psrl_q:
13927 case Intrinsic::x86_avx2_psrl_w:
13928 case Intrinsic::x86_avx2_psrl_d:
13929 case Intrinsic::x86_avx2_psrl_q:
13930 Opcode = X86ISD::VSRL;
13932 case Intrinsic::x86_sse2_psra_w:
13933 case Intrinsic::x86_sse2_psra_d:
13934 case Intrinsic::x86_avx2_psra_w:
13935 case Intrinsic::x86_avx2_psra_d:
13936 Opcode = X86ISD::VSRA;
13939 return DAG.getNode(Opcode, dl, Op.getValueType(),
13940 Op.getOperand(1), Op.getOperand(2));
13943 // SSE/AVX immediate shift intrinsics
13944 case Intrinsic::x86_sse2_pslli_w:
13945 case Intrinsic::x86_sse2_pslli_d:
13946 case Intrinsic::x86_sse2_pslli_q:
13947 case Intrinsic::x86_avx2_pslli_w:
13948 case Intrinsic::x86_avx2_pslli_d:
13949 case Intrinsic::x86_avx2_pslli_q:
13950 case Intrinsic::x86_sse2_psrli_w:
13951 case Intrinsic::x86_sse2_psrli_d:
13952 case Intrinsic::x86_sse2_psrli_q:
13953 case Intrinsic::x86_avx2_psrli_w:
13954 case Intrinsic::x86_avx2_psrli_d:
13955 case Intrinsic::x86_avx2_psrli_q:
13956 case Intrinsic::x86_sse2_psrai_w:
13957 case Intrinsic::x86_sse2_psrai_d:
13958 case Intrinsic::x86_avx2_psrai_w:
13959 case Intrinsic::x86_avx2_psrai_d: {
13962 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13963 case Intrinsic::x86_sse2_pslli_w:
13964 case Intrinsic::x86_sse2_pslli_d:
13965 case Intrinsic::x86_sse2_pslli_q:
13966 case Intrinsic::x86_avx2_pslli_w:
13967 case Intrinsic::x86_avx2_pslli_d:
13968 case Intrinsic::x86_avx2_pslli_q:
13969 Opcode = X86ISD::VSHLI;
13971 case Intrinsic::x86_sse2_psrli_w:
13972 case Intrinsic::x86_sse2_psrli_d:
13973 case Intrinsic::x86_sse2_psrli_q:
13974 case Intrinsic::x86_avx2_psrli_w:
13975 case Intrinsic::x86_avx2_psrli_d:
13976 case Intrinsic::x86_avx2_psrli_q:
13977 Opcode = X86ISD::VSRLI;
13979 case Intrinsic::x86_sse2_psrai_w:
13980 case Intrinsic::x86_sse2_psrai_d:
13981 case Intrinsic::x86_avx2_psrai_w:
13982 case Intrinsic::x86_avx2_psrai_d:
13983 Opcode = X86ISD::VSRAI;
13986 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
13987 Op.getOperand(1), Op.getOperand(2), DAG);
13990 case Intrinsic::x86_sse42_pcmpistria128:
13991 case Intrinsic::x86_sse42_pcmpestria128:
13992 case Intrinsic::x86_sse42_pcmpistric128:
13993 case Intrinsic::x86_sse42_pcmpestric128:
13994 case Intrinsic::x86_sse42_pcmpistrio128:
13995 case Intrinsic::x86_sse42_pcmpestrio128:
13996 case Intrinsic::x86_sse42_pcmpistris128:
13997 case Intrinsic::x86_sse42_pcmpestris128:
13998 case Intrinsic::x86_sse42_pcmpistriz128:
13999 case Intrinsic::x86_sse42_pcmpestriz128: {
14003 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14004 case Intrinsic::x86_sse42_pcmpistria128:
14005 Opcode = X86ISD::PCMPISTRI;
14006 X86CC = X86::COND_A;
14008 case Intrinsic::x86_sse42_pcmpestria128:
14009 Opcode = X86ISD::PCMPESTRI;
14010 X86CC = X86::COND_A;
14012 case Intrinsic::x86_sse42_pcmpistric128:
14013 Opcode = X86ISD::PCMPISTRI;
14014 X86CC = X86::COND_B;
14016 case Intrinsic::x86_sse42_pcmpestric128:
14017 Opcode = X86ISD::PCMPESTRI;
14018 X86CC = X86::COND_B;
14020 case Intrinsic::x86_sse42_pcmpistrio128:
14021 Opcode = X86ISD::PCMPISTRI;
14022 X86CC = X86::COND_O;
14024 case Intrinsic::x86_sse42_pcmpestrio128:
14025 Opcode = X86ISD::PCMPESTRI;
14026 X86CC = X86::COND_O;
14028 case Intrinsic::x86_sse42_pcmpistris128:
14029 Opcode = X86ISD::PCMPISTRI;
14030 X86CC = X86::COND_S;
14032 case Intrinsic::x86_sse42_pcmpestris128:
14033 Opcode = X86ISD::PCMPESTRI;
14034 X86CC = X86::COND_S;
14036 case Intrinsic::x86_sse42_pcmpistriz128:
14037 Opcode = X86ISD::PCMPISTRI;
14038 X86CC = X86::COND_E;
14040 case Intrinsic::x86_sse42_pcmpestriz128:
14041 Opcode = X86ISD::PCMPESTRI;
14042 X86CC = X86::COND_E;
14045 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14046 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14047 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14048 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14049 DAG.getConstant(X86CC, MVT::i8),
14050 SDValue(PCMP.getNode(), 1));
14051 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14054 case Intrinsic::x86_sse42_pcmpistri128:
14055 case Intrinsic::x86_sse42_pcmpestri128: {
14057 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14058 Opcode = X86ISD::PCMPISTRI;
14060 Opcode = X86ISD::PCMPESTRI;
14062 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14063 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14064 return DAG.getNode(Opcode, dl, VTs, NewOps);
14066 case Intrinsic::x86_fma_vfmadd_ps:
14067 case Intrinsic::x86_fma_vfmadd_pd:
14068 case Intrinsic::x86_fma_vfmsub_ps:
14069 case Intrinsic::x86_fma_vfmsub_pd:
14070 case Intrinsic::x86_fma_vfnmadd_ps:
14071 case Intrinsic::x86_fma_vfnmadd_pd:
14072 case Intrinsic::x86_fma_vfnmsub_ps:
14073 case Intrinsic::x86_fma_vfnmsub_pd:
14074 case Intrinsic::x86_fma_vfmaddsub_ps:
14075 case Intrinsic::x86_fma_vfmaddsub_pd:
14076 case Intrinsic::x86_fma_vfmsubadd_ps:
14077 case Intrinsic::x86_fma_vfmsubadd_pd:
14078 case Intrinsic::x86_fma_vfmadd_ps_256:
14079 case Intrinsic::x86_fma_vfmadd_pd_256:
14080 case Intrinsic::x86_fma_vfmsub_ps_256:
14081 case Intrinsic::x86_fma_vfmsub_pd_256:
14082 case Intrinsic::x86_fma_vfnmadd_ps_256:
14083 case Intrinsic::x86_fma_vfnmadd_pd_256:
14084 case Intrinsic::x86_fma_vfnmsub_ps_256:
14085 case Intrinsic::x86_fma_vfnmsub_pd_256:
14086 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14087 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14088 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14089 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14090 case Intrinsic::x86_fma_vfmadd_ps_512:
14091 case Intrinsic::x86_fma_vfmadd_pd_512:
14092 case Intrinsic::x86_fma_vfmsub_ps_512:
14093 case Intrinsic::x86_fma_vfmsub_pd_512:
14094 case Intrinsic::x86_fma_vfnmadd_ps_512:
14095 case Intrinsic::x86_fma_vfnmadd_pd_512:
14096 case Intrinsic::x86_fma_vfnmsub_ps_512:
14097 case Intrinsic::x86_fma_vfnmsub_pd_512:
14098 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14099 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14100 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14101 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14104 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14105 case Intrinsic::x86_fma_vfmadd_ps:
14106 case Intrinsic::x86_fma_vfmadd_pd:
14107 case Intrinsic::x86_fma_vfmadd_ps_256:
14108 case Intrinsic::x86_fma_vfmadd_pd_256:
14109 case Intrinsic::x86_fma_vfmadd_ps_512:
14110 case Intrinsic::x86_fma_vfmadd_pd_512:
14111 Opc = X86ISD::FMADD;
14113 case Intrinsic::x86_fma_vfmsub_ps:
14114 case Intrinsic::x86_fma_vfmsub_pd:
14115 case Intrinsic::x86_fma_vfmsub_ps_256:
14116 case Intrinsic::x86_fma_vfmsub_pd_256:
14117 case Intrinsic::x86_fma_vfmsub_ps_512:
14118 case Intrinsic::x86_fma_vfmsub_pd_512:
14119 Opc = X86ISD::FMSUB;
14121 case Intrinsic::x86_fma_vfnmadd_ps:
14122 case Intrinsic::x86_fma_vfnmadd_pd:
14123 case Intrinsic::x86_fma_vfnmadd_ps_256:
14124 case Intrinsic::x86_fma_vfnmadd_pd_256:
14125 case Intrinsic::x86_fma_vfnmadd_ps_512:
14126 case Intrinsic::x86_fma_vfnmadd_pd_512:
14127 Opc = X86ISD::FNMADD;
14129 case Intrinsic::x86_fma_vfnmsub_ps:
14130 case Intrinsic::x86_fma_vfnmsub_pd:
14131 case Intrinsic::x86_fma_vfnmsub_ps_256:
14132 case Intrinsic::x86_fma_vfnmsub_pd_256:
14133 case Intrinsic::x86_fma_vfnmsub_ps_512:
14134 case Intrinsic::x86_fma_vfnmsub_pd_512:
14135 Opc = X86ISD::FNMSUB;
14137 case Intrinsic::x86_fma_vfmaddsub_ps:
14138 case Intrinsic::x86_fma_vfmaddsub_pd:
14139 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14140 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14141 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14142 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14143 Opc = X86ISD::FMADDSUB;
14145 case Intrinsic::x86_fma_vfmsubadd_ps:
14146 case Intrinsic::x86_fma_vfmsubadd_pd:
14147 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14148 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14149 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14150 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14151 Opc = X86ISD::FMSUBADD;
14155 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14156 Op.getOperand(2), Op.getOperand(3));
14161 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14162 SDValue Src, SDValue Mask, SDValue Base,
14163 SDValue Index, SDValue ScaleOp, SDValue Chain,
14164 const X86Subtarget * Subtarget) {
14166 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14167 assert(C && "Invalid scale type");
14168 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14169 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14170 Index.getSimpleValueType().getVectorNumElements());
14172 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14174 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14176 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14177 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14178 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14179 SDValue Segment = DAG.getRegister(0, MVT::i32);
14180 if (Src.getOpcode() == ISD::UNDEF)
14181 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14182 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14183 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14184 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14185 return DAG.getMergeValues(RetOps, dl);
14188 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14189 SDValue Src, SDValue Mask, SDValue Base,
14190 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14192 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14193 assert(C && "Invalid scale type");
14194 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14195 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14196 SDValue Segment = DAG.getRegister(0, MVT::i32);
14197 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14198 Index.getSimpleValueType().getVectorNumElements());
14200 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14202 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14204 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14205 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14206 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14207 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14208 return SDValue(Res, 1);
14211 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14212 SDValue Mask, SDValue Base, SDValue Index,
14213 SDValue ScaleOp, SDValue Chain) {
14215 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14216 assert(C && "Invalid scale type");
14217 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14218 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14219 SDValue Segment = DAG.getRegister(0, MVT::i32);
14221 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14223 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14225 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14227 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14228 //SDVTList VTs = DAG.getVTList(MVT::Other);
14229 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14230 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14231 return SDValue(Res, 0);
14234 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14235 // read performance monitor counters (x86_rdpmc).
14236 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14237 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14238 SmallVectorImpl<SDValue> &Results) {
14239 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14240 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14243 // The ECX register is used to select the index of the performance counter
14245 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14247 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14249 // Reads the content of a 64-bit performance counter and returns it in the
14250 // registers EDX:EAX.
14251 if (Subtarget->is64Bit()) {
14252 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14253 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14256 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14257 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14260 Chain = HI.getValue(1);
14262 if (Subtarget->is64Bit()) {
14263 // The EAX register is loaded with the low-order 32 bits. The EDX register
14264 // is loaded with the supported high-order bits of the counter.
14265 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14266 DAG.getConstant(32, MVT::i8));
14267 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14268 Results.push_back(Chain);
14272 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14273 SDValue Ops[] = { LO, HI };
14274 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14275 Results.push_back(Pair);
14276 Results.push_back(Chain);
14279 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14280 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14281 // also used to custom lower READCYCLECOUNTER nodes.
14282 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14283 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14284 SmallVectorImpl<SDValue> &Results) {
14285 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14286 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14289 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14290 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14291 // and the EAX register is loaded with the low-order 32 bits.
14292 if (Subtarget->is64Bit()) {
14293 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14294 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14297 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14298 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14301 SDValue Chain = HI.getValue(1);
14303 if (Opcode == X86ISD::RDTSCP_DAG) {
14304 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14306 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14307 // the ECX register. Add 'ecx' explicitly to the chain.
14308 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14310 // Explicitly store the content of ECX at the location passed in input
14311 // to the 'rdtscp' intrinsic.
14312 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14313 MachinePointerInfo(), false, false, 0);
14316 if (Subtarget->is64Bit()) {
14317 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14318 // the EAX register is loaded with the low-order 32 bits.
14319 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14320 DAG.getConstant(32, MVT::i8));
14321 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14322 Results.push_back(Chain);
14326 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14327 SDValue Ops[] = { LO, HI };
14328 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14329 Results.push_back(Pair);
14330 Results.push_back(Chain);
14333 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14334 SelectionDAG &DAG) {
14335 SmallVector<SDValue, 2> Results;
14337 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14339 return DAG.getMergeValues(Results, DL);
14342 enum IntrinsicType {
14343 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14346 struct IntrinsicData {
14347 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14348 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14349 IntrinsicType Type;
14354 std::map < unsigned, IntrinsicData> IntrMap;
14355 static void InitIntinsicsMap() {
14356 static bool Initialized = false;
14359 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14360 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14361 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14362 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14363 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14364 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14365 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14366 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14367 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14368 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14369 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14370 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14371 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14372 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14373 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14374 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14375 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14376 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14378 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14379 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14380 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14381 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14382 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14383 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14384 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14385 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14386 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14387 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14388 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14389 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14390 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14391 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14392 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14393 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14395 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14396 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14397 X86::VGATHERPF1QPSm)));
14398 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14399 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14400 X86::VGATHERPF1QPDm)));
14401 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14402 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14403 X86::VGATHERPF1DPDm)));
14404 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14405 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14406 X86::VGATHERPF1DPSm)));
14407 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14408 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14409 X86::VSCATTERPF1QPSm)));
14410 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14411 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14412 X86::VSCATTERPF1QPDm)));
14413 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14414 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14415 X86::VSCATTERPF1DPDm)));
14416 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14417 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14418 X86::VSCATTERPF1DPSm)));
14419 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14420 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14421 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14422 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14423 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14424 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14425 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14426 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14427 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14428 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14429 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14430 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14431 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14432 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14433 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14434 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14435 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14436 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14437 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14438 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14439 Initialized = true;
14442 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14443 SelectionDAG &DAG) {
14444 InitIntinsicsMap();
14445 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14446 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14447 if (itr == IntrMap.end())
14451 IntrinsicData Intr = itr->second;
14452 switch(Intr.Type) {
14455 // Emit the node with the right value type.
14456 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14457 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
14459 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14460 // Otherwise return the value from Rand, which is always 0, casted to i32.
14461 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14462 DAG.getConstant(1, Op->getValueType(1)),
14463 DAG.getConstant(X86::COND_B, MVT::i32),
14464 SDValue(Result.getNode(), 1) };
14465 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14466 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14469 // Return { result, isValid, chain }.
14470 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14471 SDValue(Result.getNode(), 2));
14474 //gather(v1, mask, index, base, scale);
14475 SDValue Chain = Op.getOperand(0);
14476 SDValue Src = Op.getOperand(2);
14477 SDValue Base = Op.getOperand(3);
14478 SDValue Index = Op.getOperand(4);
14479 SDValue Mask = Op.getOperand(5);
14480 SDValue Scale = Op.getOperand(6);
14481 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14485 //scatter(base, mask, index, v1, scale);
14486 SDValue Chain = Op.getOperand(0);
14487 SDValue Base = Op.getOperand(2);
14488 SDValue Mask = Op.getOperand(3);
14489 SDValue Index = Op.getOperand(4);
14490 SDValue Src = Op.getOperand(5);
14491 SDValue Scale = Op.getOperand(6);
14492 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14495 SDValue Hint = Op.getOperand(6);
14497 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14498 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14499 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14500 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
14501 SDValue Chain = Op.getOperand(0);
14502 SDValue Mask = Op.getOperand(2);
14503 SDValue Index = Op.getOperand(3);
14504 SDValue Base = Op.getOperand(4);
14505 SDValue Scale = Op.getOperand(5);
14506 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
14508 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
14510 SmallVector<SDValue, 2> Results;
14511 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
14512 return DAG.getMergeValues(Results, dl);
14514 // Read Performance Monitoring Counters.
14516 SmallVector<SDValue, 2> Results;
14517 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
14518 return DAG.getMergeValues(Results, dl);
14520 // XTEST intrinsics.
14522 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
14523 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
14524 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14525 DAG.getConstant(X86::COND_NE, MVT::i8),
14527 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
14528 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
14529 Ret, SDValue(InTrans.getNode(), 1));
14532 llvm_unreachable("Unknown Intrinsic Type");
14535 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
14536 SelectionDAG &DAG) const {
14537 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14538 MFI->setReturnAddressIsTaken(true);
14540 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
14543 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14545 EVT PtrVT = getPointerTy();
14548 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
14549 const X86RegisterInfo *RegInfo =
14550 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14551 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
14552 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14553 DAG.getNode(ISD::ADD, dl, PtrVT,
14554 FrameAddr, Offset),
14555 MachinePointerInfo(), false, false, false, 0);
14558 // Just load the return address.
14559 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
14560 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14561 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
14564 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
14565 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14566 MFI->setFrameAddressIsTaken(true);
14568 EVT VT = Op.getValueType();
14569 SDLoc dl(Op); // FIXME probably not meaningful
14570 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14571 const X86RegisterInfo *RegInfo =
14572 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14573 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14574 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
14575 (FrameReg == X86::EBP && VT == MVT::i32)) &&
14576 "Invalid Frame Register!");
14577 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
14579 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
14580 MachinePointerInfo(),
14581 false, false, false, 0);
14585 // FIXME? Maybe this could be a TableGen attribute on some registers and
14586 // this table could be generated automatically from RegInfo.
14587 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
14589 unsigned Reg = StringSwitch<unsigned>(RegName)
14590 .Case("esp", X86::ESP)
14591 .Case("rsp", X86::RSP)
14595 report_fatal_error("Invalid register name global variable");
14598 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
14599 SelectionDAG &DAG) const {
14600 const X86RegisterInfo *RegInfo =
14601 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14602 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
14605 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
14606 SDValue Chain = Op.getOperand(0);
14607 SDValue Offset = Op.getOperand(1);
14608 SDValue Handler = Op.getOperand(2);
14611 EVT PtrVT = getPointerTy();
14612 const X86RegisterInfo *RegInfo =
14613 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14614 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14615 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
14616 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
14617 "Invalid Frame Register!");
14618 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
14619 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
14621 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
14622 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
14623 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
14624 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
14626 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
14628 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
14629 DAG.getRegister(StoreAddrReg, PtrVT));
14632 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
14633 SelectionDAG &DAG) const {
14635 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
14636 DAG.getVTList(MVT::i32, MVT::Other),
14637 Op.getOperand(0), Op.getOperand(1));
14640 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
14641 SelectionDAG &DAG) const {
14643 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
14644 Op.getOperand(0), Op.getOperand(1));
14647 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
14648 return Op.getOperand(0);
14651 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
14652 SelectionDAG &DAG) const {
14653 SDValue Root = Op.getOperand(0);
14654 SDValue Trmp = Op.getOperand(1); // trampoline
14655 SDValue FPtr = Op.getOperand(2); // nested function
14656 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
14659 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14660 const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
14662 if (Subtarget->is64Bit()) {
14663 SDValue OutChains[6];
14665 // Large code-model.
14666 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
14667 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
14669 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
14670 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
14672 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
14674 // Load the pointer to the nested function into R11.
14675 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
14676 SDValue Addr = Trmp;
14677 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14678 Addr, MachinePointerInfo(TrmpAddr),
14681 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14682 DAG.getConstant(2, MVT::i64));
14683 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
14684 MachinePointerInfo(TrmpAddr, 2),
14687 // Load the 'nest' parameter value into R10.
14688 // R10 is specified in X86CallingConv.td
14689 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
14690 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14691 DAG.getConstant(10, MVT::i64));
14692 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14693 Addr, MachinePointerInfo(TrmpAddr, 10),
14696 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14697 DAG.getConstant(12, MVT::i64));
14698 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
14699 MachinePointerInfo(TrmpAddr, 12),
14702 // Jump to the nested function.
14703 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
14704 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14705 DAG.getConstant(20, MVT::i64));
14706 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14707 Addr, MachinePointerInfo(TrmpAddr, 20),
14710 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
14711 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14712 DAG.getConstant(22, MVT::i64));
14713 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
14714 MachinePointerInfo(TrmpAddr, 22),
14717 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14719 const Function *Func =
14720 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
14721 CallingConv::ID CC = Func->getCallingConv();
14726 llvm_unreachable("Unsupported calling convention");
14727 case CallingConv::C:
14728 case CallingConv::X86_StdCall: {
14729 // Pass 'nest' parameter in ECX.
14730 // Must be kept in sync with X86CallingConv.td
14731 NestReg = X86::ECX;
14733 // Check that ECX wasn't needed by an 'inreg' parameter.
14734 FunctionType *FTy = Func->getFunctionType();
14735 const AttributeSet &Attrs = Func->getAttributes();
14737 if (!Attrs.isEmpty() && !Func->isVarArg()) {
14738 unsigned InRegCount = 0;
14741 for (FunctionType::param_iterator I = FTy->param_begin(),
14742 E = FTy->param_end(); I != E; ++I, ++Idx)
14743 if (Attrs.hasAttribute(Idx, Attribute::InReg))
14744 // FIXME: should only count parameters that are lowered to integers.
14745 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
14747 if (InRegCount > 2) {
14748 report_fatal_error("Nest register in use - reduce number of inreg"
14754 case CallingConv::X86_FastCall:
14755 case CallingConv::X86_ThisCall:
14756 case CallingConv::Fast:
14757 // Pass 'nest' parameter in EAX.
14758 // Must be kept in sync with X86CallingConv.td
14759 NestReg = X86::EAX;
14763 SDValue OutChains[4];
14764 SDValue Addr, Disp;
14766 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14767 DAG.getConstant(10, MVT::i32));
14768 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
14770 // This is storing the opcode for MOV32ri.
14771 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
14772 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
14773 OutChains[0] = DAG.getStore(Root, dl,
14774 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
14775 Trmp, MachinePointerInfo(TrmpAddr),
14778 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14779 DAG.getConstant(1, MVT::i32));
14780 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
14781 MachinePointerInfo(TrmpAddr, 1),
14784 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
14785 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14786 DAG.getConstant(5, MVT::i32));
14787 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
14788 MachinePointerInfo(TrmpAddr, 5),
14791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14792 DAG.getConstant(6, MVT::i32));
14793 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
14794 MachinePointerInfo(TrmpAddr, 6),
14797 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14801 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
14802 SelectionDAG &DAG) const {
14804 The rounding mode is in bits 11:10 of FPSR, and has the following
14806 00 Round to nearest
14811 FLT_ROUNDS, on the other hand, expects the following:
14818 To perform the conversion, we do:
14819 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
14822 MachineFunction &MF = DAG.getMachineFunction();
14823 const TargetMachine &TM = MF.getTarget();
14824 const TargetFrameLowering &TFI = *TM.getFrameLowering();
14825 unsigned StackAlignment = TFI.getStackAlignment();
14826 MVT VT = Op.getSimpleValueType();
14829 // Save FP Control Word to stack slot
14830 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
14831 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14833 MachineMemOperand *MMO =
14834 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14835 MachineMemOperand::MOStore, 2, 2);
14837 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
14838 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
14839 DAG.getVTList(MVT::Other),
14840 Ops, MVT::i16, MMO);
14842 // Load FP Control Word from stack slot
14843 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
14844 MachinePointerInfo(), false, false, false, 0);
14846 // Transform as necessary
14848 DAG.getNode(ISD::SRL, DL, MVT::i16,
14849 DAG.getNode(ISD::AND, DL, MVT::i16,
14850 CWD, DAG.getConstant(0x800, MVT::i16)),
14851 DAG.getConstant(11, MVT::i8));
14853 DAG.getNode(ISD::SRL, DL, MVT::i16,
14854 DAG.getNode(ISD::AND, DL, MVT::i16,
14855 CWD, DAG.getConstant(0x400, MVT::i16)),
14856 DAG.getConstant(9, MVT::i8));
14859 DAG.getNode(ISD::AND, DL, MVT::i16,
14860 DAG.getNode(ISD::ADD, DL, MVT::i16,
14861 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
14862 DAG.getConstant(1, MVT::i16)),
14863 DAG.getConstant(3, MVT::i16));
14865 return DAG.getNode((VT.getSizeInBits() < 16 ?
14866 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
14869 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
14870 MVT VT = Op.getSimpleValueType();
14872 unsigned NumBits = VT.getSizeInBits();
14875 Op = Op.getOperand(0);
14876 if (VT == MVT::i8) {
14877 // Zero extend to i32 since there is not an i8 bsr.
14879 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14882 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
14883 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14884 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14886 // If src is zero (i.e. bsr sets ZF), returns NumBits.
14889 DAG.getConstant(NumBits+NumBits-1, OpVT),
14890 DAG.getConstant(X86::COND_E, MVT::i8),
14893 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
14895 // Finally xor with NumBits-1.
14896 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14899 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14903 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
14904 MVT VT = Op.getSimpleValueType();
14906 unsigned NumBits = VT.getSizeInBits();
14909 Op = Op.getOperand(0);
14910 if (VT == MVT::i8) {
14911 // Zero extend to i32 since there is not an i8 bsr.
14913 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14916 // Issue a bsr (scan bits in reverse).
14917 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14918 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14920 // And xor with NumBits-1.
14921 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14924 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14928 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
14929 MVT VT = Op.getSimpleValueType();
14930 unsigned NumBits = VT.getSizeInBits();
14932 Op = Op.getOperand(0);
14934 // Issue a bsf (scan bits forward) which also sets EFLAGS.
14935 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14936 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
14938 // If src is zero (i.e. bsf sets ZF), returns NumBits.
14941 DAG.getConstant(NumBits, VT),
14942 DAG.getConstant(X86::COND_E, MVT::i8),
14945 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
14948 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
14949 // ones, and then concatenate the result back.
14950 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
14951 MVT VT = Op.getSimpleValueType();
14953 assert(VT.is256BitVector() && VT.isInteger() &&
14954 "Unsupported value type for operation");
14956 unsigned NumElems = VT.getVectorNumElements();
14959 // Extract the LHS vectors
14960 SDValue LHS = Op.getOperand(0);
14961 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14962 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14964 // Extract the RHS vectors
14965 SDValue RHS = Op.getOperand(1);
14966 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14967 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14969 MVT EltVT = VT.getVectorElementType();
14970 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14972 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14973 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
14974 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
14977 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
14978 assert(Op.getSimpleValueType().is256BitVector() &&
14979 Op.getSimpleValueType().isInteger() &&
14980 "Only handle AVX 256-bit vector integer operation");
14981 return Lower256IntArith(Op, DAG);
14984 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
14985 assert(Op.getSimpleValueType().is256BitVector() &&
14986 Op.getSimpleValueType().isInteger() &&
14987 "Only handle AVX 256-bit vector integer operation");
14988 return Lower256IntArith(Op, DAG);
14991 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
14992 SelectionDAG &DAG) {
14994 MVT VT = Op.getSimpleValueType();
14996 // Decompose 256-bit ops into smaller 128-bit ops.
14997 if (VT.is256BitVector() && !Subtarget->hasInt256())
14998 return Lower256IntArith(Op, DAG);
15000 SDValue A = Op.getOperand(0);
15001 SDValue B = Op.getOperand(1);
15003 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15004 if (VT == MVT::v4i32) {
15005 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15006 "Should not custom lower when pmuldq is available!");
15008 // Extract the odd parts.
15009 static const int UnpackMask[] = { 1, -1, 3, -1 };
15010 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15011 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15013 // Multiply the even parts.
15014 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15015 // Now multiply odd parts.
15016 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15018 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15019 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15021 // Merge the two vectors back together with a shuffle. This expands into 2
15023 static const int ShufMask[] = { 0, 4, 2, 6 };
15024 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15027 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15028 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15030 // Ahi = psrlqi(a, 32);
15031 // Bhi = psrlqi(b, 32);
15033 // AloBlo = pmuludq(a, b);
15034 // AloBhi = pmuludq(a, Bhi);
15035 // AhiBlo = pmuludq(Ahi, b);
15037 // AloBhi = psllqi(AloBhi, 32);
15038 // AhiBlo = psllqi(AhiBlo, 32);
15039 // return AloBlo + AloBhi + AhiBlo;
15041 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15042 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15044 // Bit cast to 32-bit vectors for MULUDQ
15045 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15046 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15047 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15048 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15049 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15050 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15052 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15053 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15054 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15056 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15057 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15059 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15060 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15063 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15064 assert(Subtarget->isTargetWin64() && "Unexpected target");
15065 EVT VT = Op.getValueType();
15066 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15067 "Unexpected return type for lowering");
15071 switch (Op->getOpcode()) {
15072 default: llvm_unreachable("Unexpected request for libcall!");
15073 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15074 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15075 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15076 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15077 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15078 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15082 SDValue InChain = DAG.getEntryNode();
15084 TargetLowering::ArgListTy Args;
15085 TargetLowering::ArgListEntry Entry;
15086 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15087 EVT ArgVT = Op->getOperand(i).getValueType();
15088 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15089 "Unexpected argument type for lowering");
15090 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15091 Entry.Node = StackPtr;
15092 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15094 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15095 Entry.Ty = PointerType::get(ArgTy,0);
15096 Entry.isSExt = false;
15097 Entry.isZExt = false;
15098 Args.push_back(Entry);
15101 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15104 TargetLowering::CallLoweringInfo CLI(DAG);
15105 CLI.setDebugLoc(dl).setChain(InChain)
15106 .setCallee(getLibcallCallingConv(LC),
15107 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15108 Callee, std::move(Args), 0)
15109 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15111 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15112 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15115 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15116 SelectionDAG &DAG) {
15117 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15118 EVT VT = Op0.getValueType();
15121 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15122 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15124 // Get the high parts.
15125 const int Mask[] = {1, 2, 3, 4, 5, 6, 7, 8};
15126 SDValue Hi0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15127 SDValue Hi1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15129 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15131 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15132 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15134 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15135 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15136 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15137 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15138 DAG.getNode(Opcode, dl, MulVT, Hi0, Hi1));
15140 // Shuffle it back into the right order.
15141 const int HighMask[] = {1, 5, 3, 7, 9, 13, 11, 15};
15142 SDValue Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15143 const int LowMask[] = {0, 4, 2, 6, 8, 12, 10, 14};
15144 SDValue Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15146 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15147 // unsigned multiply.
15148 if (IsSigned && !Subtarget->hasSSE41()) {
15150 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15151 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15152 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15153 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15154 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15156 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15157 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15160 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Highs, Lows);
15163 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15164 const X86Subtarget *Subtarget) {
15165 MVT VT = Op.getSimpleValueType();
15167 SDValue R = Op.getOperand(0);
15168 SDValue Amt = Op.getOperand(1);
15170 // Optimize shl/srl/sra with constant shift amount.
15171 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15172 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15173 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15175 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15176 (Subtarget->hasInt256() &&
15177 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15178 (Subtarget->hasAVX512() &&
15179 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15180 if (Op.getOpcode() == ISD::SHL)
15181 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15183 if (Op.getOpcode() == ISD::SRL)
15184 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15186 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15187 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15191 if (VT == MVT::v16i8) {
15192 if (Op.getOpcode() == ISD::SHL) {
15193 // Make a large shift.
15194 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15195 MVT::v8i16, R, ShiftAmt,
15197 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15198 // Zero out the rightmost bits.
15199 SmallVector<SDValue, 16> V(16,
15200 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15202 return DAG.getNode(ISD::AND, dl, VT, SHL,
15203 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15205 if (Op.getOpcode() == ISD::SRL) {
15206 // Make a large shift.
15207 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15208 MVT::v8i16, R, ShiftAmt,
15210 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15211 // Zero out the leftmost bits.
15212 SmallVector<SDValue, 16> V(16,
15213 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15215 return DAG.getNode(ISD::AND, dl, VT, SRL,
15216 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15218 if (Op.getOpcode() == ISD::SRA) {
15219 if (ShiftAmt == 7) {
15220 // R s>> 7 === R s< 0
15221 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15222 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15225 // R s>> a === ((R u>> a) ^ m) - m
15226 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15227 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15229 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15230 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15231 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15234 llvm_unreachable("Unknown shift opcode.");
15237 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15238 if (Op.getOpcode() == ISD::SHL) {
15239 // Make a large shift.
15240 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15241 MVT::v16i16, R, ShiftAmt,
15243 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15244 // Zero out the rightmost bits.
15245 SmallVector<SDValue, 32> V(32,
15246 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15248 return DAG.getNode(ISD::AND, dl, VT, SHL,
15249 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15251 if (Op.getOpcode() == ISD::SRL) {
15252 // Make a large shift.
15253 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15254 MVT::v16i16, R, ShiftAmt,
15256 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15257 // Zero out the leftmost bits.
15258 SmallVector<SDValue, 32> V(32,
15259 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15261 return DAG.getNode(ISD::AND, dl, VT, SRL,
15262 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15264 if (Op.getOpcode() == ISD::SRA) {
15265 if (ShiftAmt == 7) {
15266 // R s>> 7 === R s< 0
15267 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15268 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15271 // R s>> a === ((R u>> a) ^ m) - m
15272 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15273 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15275 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15276 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15277 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15280 llvm_unreachable("Unknown shift opcode.");
15285 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15286 if (!Subtarget->is64Bit() &&
15287 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15288 Amt.getOpcode() == ISD::BITCAST &&
15289 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15290 Amt = Amt.getOperand(0);
15291 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15292 VT.getVectorNumElements();
15293 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15294 uint64_t ShiftAmt = 0;
15295 for (unsigned i = 0; i != Ratio; ++i) {
15296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15300 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15302 // Check remaining shift amounts.
15303 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15304 uint64_t ShAmt = 0;
15305 for (unsigned j = 0; j != Ratio; ++j) {
15306 ConstantSDNode *C =
15307 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15311 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15313 if (ShAmt != ShiftAmt)
15316 switch (Op.getOpcode()) {
15318 llvm_unreachable("Unknown shift opcode!");
15320 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15323 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15326 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15334 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15335 const X86Subtarget* Subtarget) {
15336 MVT VT = Op.getSimpleValueType();
15338 SDValue R = Op.getOperand(0);
15339 SDValue Amt = Op.getOperand(1);
15341 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15342 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15343 (Subtarget->hasInt256() &&
15344 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15345 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15346 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15348 EVT EltVT = VT.getVectorElementType();
15350 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15351 unsigned NumElts = VT.getVectorNumElements();
15353 for (i = 0; i != NumElts; ++i) {
15354 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15358 for (j = i; j != NumElts; ++j) {
15359 SDValue Arg = Amt.getOperand(j);
15360 if (Arg.getOpcode() == ISD::UNDEF) continue;
15361 if (Arg != Amt.getOperand(i))
15364 if (i != NumElts && j == NumElts)
15365 BaseShAmt = Amt.getOperand(i);
15367 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15368 Amt = Amt.getOperand(0);
15369 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15370 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15371 SDValue InVec = Amt.getOperand(0);
15372 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15373 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15375 for (; i != NumElts; ++i) {
15376 SDValue Arg = InVec.getOperand(i);
15377 if (Arg.getOpcode() == ISD::UNDEF) continue;
15381 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15382 if (ConstantSDNode *C =
15383 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15384 unsigned SplatIdx =
15385 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15386 if (C->getZExtValue() == SplatIdx)
15387 BaseShAmt = InVec.getOperand(1);
15390 if (!BaseShAmt.getNode())
15391 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15392 DAG.getIntPtrConstant(0));
15396 if (BaseShAmt.getNode()) {
15397 if (EltVT.bitsGT(MVT::i32))
15398 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15399 else if (EltVT.bitsLT(MVT::i32))
15400 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15402 switch (Op.getOpcode()) {
15404 llvm_unreachable("Unknown shift opcode!");
15406 switch (VT.SimpleTy) {
15407 default: return SDValue();
15416 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15419 switch (VT.SimpleTy) {
15420 default: return SDValue();
15427 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15430 switch (VT.SimpleTy) {
15431 default: return SDValue();
15440 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15446 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15447 if (!Subtarget->is64Bit() &&
15448 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15449 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15450 Amt.getOpcode() == ISD::BITCAST &&
15451 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15452 Amt = Amt.getOperand(0);
15453 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15454 VT.getVectorNumElements();
15455 std::vector<SDValue> Vals(Ratio);
15456 for (unsigned i = 0; i != Ratio; ++i)
15457 Vals[i] = Amt.getOperand(i);
15458 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15459 for (unsigned j = 0; j != Ratio; ++j)
15460 if (Vals[j] != Amt.getOperand(i + j))
15463 switch (Op.getOpcode()) {
15465 llvm_unreachable("Unknown shift opcode!");
15467 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15469 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
15471 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
15478 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
15479 SelectionDAG &DAG) {
15480 MVT VT = Op.getSimpleValueType();
15482 SDValue R = Op.getOperand(0);
15483 SDValue Amt = Op.getOperand(1);
15486 assert(VT.isVector() && "Custom lowering only for vector shifts!");
15487 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
15489 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
15493 V = LowerScalarVariableShift(Op, DAG, Subtarget);
15497 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
15499 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
15500 if (Subtarget->hasInt256()) {
15501 if (Op.getOpcode() == ISD::SRL &&
15502 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15503 VT == MVT::v4i64 || VT == MVT::v8i32))
15505 if (Op.getOpcode() == ISD::SHL &&
15506 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15507 VT == MVT::v4i64 || VT == MVT::v8i32))
15509 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15513 // If possible, lower this packed shift into a vector multiply instead of
15514 // expanding it into a sequence of scalar shifts.
15515 // Do this only if the vector shift count is a constant build_vector.
15516 if (Op.getOpcode() == ISD::SHL &&
15517 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
15518 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
15519 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15520 SmallVector<SDValue, 8> Elts;
15521 EVT SVT = VT.getScalarType();
15522 unsigned SVTBits = SVT.getSizeInBits();
15523 const APInt &One = APInt(SVTBits, 1);
15524 unsigned NumElems = VT.getVectorNumElements();
15526 for (unsigned i=0; i !=NumElems; ++i) {
15527 SDValue Op = Amt->getOperand(i);
15528 if (Op->getOpcode() == ISD::UNDEF) {
15529 Elts.push_back(Op);
15533 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
15534 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
15535 uint64_t ShAmt = C.getZExtValue();
15536 if (ShAmt >= SVTBits) {
15537 Elts.push_back(DAG.getUNDEF(SVT));
15540 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
15542 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15543 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
15546 // Lower SHL with variable shift amount.
15547 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
15548 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
15550 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
15551 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
15552 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
15553 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
15556 // If possible, lower this shift as a sequence of two shifts by
15557 // constant plus a MOVSS/MOVSD instead of scalarizing it.
15559 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15561 // Could be rewritten as:
15562 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
15564 // The advantage is that the two shifts from the example would be
15565 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
15566 // the vector shift into four scalar shifts plus four pairs of vector
15568 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
15569 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15570 unsigned TargetOpcode = X86ISD::MOVSS;
15571 bool CanBeSimplified;
15572 // The splat value for the first packed shift (the 'X' from the example).
15573 SDValue Amt1 = Amt->getOperand(0);
15574 // The splat value for the second packed shift (the 'Y' from the example).
15575 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
15576 Amt->getOperand(2);
15578 // See if it is possible to replace this node with a sequence of
15579 // two shifts followed by a MOVSS/MOVSD
15580 if (VT == MVT::v4i32) {
15581 // Check if it is legal to use a MOVSS.
15582 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
15583 Amt2 == Amt->getOperand(3);
15584 if (!CanBeSimplified) {
15585 // Otherwise, check if we can still simplify this node using a MOVSD.
15586 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
15587 Amt->getOperand(2) == Amt->getOperand(3);
15588 TargetOpcode = X86ISD::MOVSD;
15589 Amt2 = Amt->getOperand(2);
15592 // Do similar checks for the case where the machine value type
15594 CanBeSimplified = Amt1 == Amt->getOperand(1);
15595 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
15596 CanBeSimplified = Amt2 == Amt->getOperand(i);
15598 if (!CanBeSimplified) {
15599 TargetOpcode = X86ISD::MOVSD;
15600 CanBeSimplified = true;
15601 Amt2 = Amt->getOperand(4);
15602 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
15603 CanBeSimplified = Amt1 == Amt->getOperand(i);
15604 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
15605 CanBeSimplified = Amt2 == Amt->getOperand(j);
15609 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
15610 isa<ConstantSDNode>(Amt2)) {
15611 // Replace this node with two shifts followed by a MOVSS/MOVSD.
15612 EVT CastVT = MVT::v4i32;
15614 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
15615 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
15617 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
15618 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
15619 if (TargetOpcode == X86ISD::MOVSD)
15620 CastVT = MVT::v2i64;
15621 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
15622 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
15623 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
15625 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15629 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
15630 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
15633 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
15634 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
15636 // Turn 'a' into a mask suitable for VSELECT
15637 SDValue VSelM = DAG.getConstant(0x80, VT);
15638 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15639 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15641 SDValue CM1 = DAG.getConstant(0x0f, VT);
15642 SDValue CM2 = DAG.getConstant(0x3f, VT);
15644 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
15645 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
15646 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
15647 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15648 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15651 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15652 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15653 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15655 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
15656 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
15657 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
15658 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15659 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15662 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15663 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15664 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15666 // return VSELECT(r, r+r, a);
15667 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
15668 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
15672 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
15673 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
15674 // solution better.
15675 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
15676 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15678 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
15679 R = DAG.getNode(ExtOpc, dl, NewVT, R);
15680 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
15681 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15682 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
15685 // Decompose 256-bit shifts into smaller 128-bit shifts.
15686 if (VT.is256BitVector()) {
15687 unsigned NumElems = VT.getVectorNumElements();
15688 MVT EltVT = VT.getVectorElementType();
15689 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15691 // Extract the two vectors
15692 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
15693 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
15695 // Recreate the shift amount vectors
15696 SDValue Amt1, Amt2;
15697 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15698 // Constant shift amount
15699 SmallVector<SDValue, 4> Amt1Csts;
15700 SmallVector<SDValue, 4> Amt2Csts;
15701 for (unsigned i = 0; i != NumElems/2; ++i)
15702 Amt1Csts.push_back(Amt->getOperand(i));
15703 for (unsigned i = NumElems/2; i != NumElems; ++i)
15704 Amt2Csts.push_back(Amt->getOperand(i));
15706 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
15707 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
15709 // Variable shift amount
15710 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
15711 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
15714 // Issue new vector shifts for the smaller types
15715 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
15716 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
15718 // Concatenate the result back
15719 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
15725 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
15726 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
15727 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
15728 // looks for this combo and may remove the "setcc" instruction if the "setcc"
15729 // has only one use.
15730 SDNode *N = Op.getNode();
15731 SDValue LHS = N->getOperand(0);
15732 SDValue RHS = N->getOperand(1);
15733 unsigned BaseOp = 0;
15736 switch (Op.getOpcode()) {
15737 default: llvm_unreachable("Unknown ovf instruction!");
15739 // A subtract of one will be selected as a INC. Note that INC doesn't
15740 // set CF, so we can't do this for UADDO.
15741 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15743 BaseOp = X86ISD::INC;
15744 Cond = X86::COND_O;
15747 BaseOp = X86ISD::ADD;
15748 Cond = X86::COND_O;
15751 BaseOp = X86ISD::ADD;
15752 Cond = X86::COND_B;
15755 // A subtract of one will be selected as a DEC. Note that DEC doesn't
15756 // set CF, so we can't do this for USUBO.
15757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15759 BaseOp = X86ISD::DEC;
15760 Cond = X86::COND_O;
15763 BaseOp = X86ISD::SUB;
15764 Cond = X86::COND_O;
15767 BaseOp = X86ISD::SUB;
15768 Cond = X86::COND_B;
15771 BaseOp = X86ISD::SMUL;
15772 Cond = X86::COND_O;
15774 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
15775 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
15777 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
15780 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15781 DAG.getConstant(X86::COND_O, MVT::i32),
15782 SDValue(Sum.getNode(), 2));
15784 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15788 // Also sets EFLAGS.
15789 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
15790 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
15793 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
15794 DAG.getConstant(Cond, MVT::i32),
15795 SDValue(Sum.getNode(), 1));
15797 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15800 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
15801 SelectionDAG &DAG) const {
15803 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
15804 MVT VT = Op.getSimpleValueType();
15806 if (!Subtarget->hasSSE2() || !VT.isVector())
15809 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
15810 ExtraVT.getScalarType().getSizeInBits();
15812 switch (VT.SimpleTy) {
15813 default: return SDValue();
15816 if (!Subtarget->hasFp256())
15818 if (!Subtarget->hasInt256()) {
15819 // needs to be split
15820 unsigned NumElems = VT.getVectorNumElements();
15822 // Extract the LHS vectors
15823 SDValue LHS = Op.getOperand(0);
15824 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15825 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15827 MVT EltVT = VT.getVectorElementType();
15828 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15830 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15831 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
15832 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
15834 SDValue Extra = DAG.getValueType(ExtraVT);
15836 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
15837 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
15839 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
15844 SDValue Op0 = Op.getOperand(0);
15845 SDValue Op00 = Op0.getOperand(0);
15847 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
15848 if (Op0.getOpcode() == ISD::BITCAST &&
15849 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
15850 // (sext (vzext x)) -> (vsext x)
15851 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
15852 if (Tmp1.getNode()) {
15853 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15854 // This folding is only valid when the in-reg type is a vector of i8,
15856 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
15857 ExtraEltVT == MVT::i32) {
15858 SDValue Tmp1Op0 = Tmp1.getOperand(0);
15859 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
15860 "This optimization is invalid without a VZEXT.");
15861 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
15867 // If the above didn't work, then just use Shift-Left + Shift-Right.
15868 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
15870 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
15876 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
15877 SelectionDAG &DAG) {
15879 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
15880 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
15881 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
15882 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
15884 // The only fence that needs an instruction is a sequentially-consistent
15885 // cross-thread fence.
15886 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
15887 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
15888 // no-sse2). There isn't any reason to disable it if the target processor
15890 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
15891 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
15893 SDValue Chain = Op.getOperand(0);
15894 SDValue Zero = DAG.getConstant(0, MVT::i32);
15896 DAG.getRegister(X86::ESP, MVT::i32), // Base
15897 DAG.getTargetConstant(1, MVT::i8), // Scale
15898 DAG.getRegister(0, MVT::i32), // Index
15899 DAG.getTargetConstant(0, MVT::i32), // Disp
15900 DAG.getRegister(0, MVT::i32), // Segment.
15904 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
15905 return SDValue(Res, 0);
15908 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
15909 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
15912 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
15913 SelectionDAG &DAG) {
15914 MVT T = Op.getSimpleValueType();
15918 switch(T.SimpleTy) {
15919 default: llvm_unreachable("Invalid value type!");
15920 case MVT::i8: Reg = X86::AL; size = 1; break;
15921 case MVT::i16: Reg = X86::AX; size = 2; break;
15922 case MVT::i32: Reg = X86::EAX; size = 4; break;
15924 assert(Subtarget->is64Bit() && "Node not type legal!");
15925 Reg = X86::RAX; size = 8;
15928 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
15929 Op.getOperand(2), SDValue());
15930 SDValue Ops[] = { cpIn.getValue(0),
15933 DAG.getTargetConstant(size, MVT::i8),
15934 cpIn.getValue(1) };
15935 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15936 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
15937 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
15941 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
15942 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
15943 MVT::i32, cpOut.getValue(2));
15944 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
15945 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
15947 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
15948 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
15949 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
15953 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
15954 SelectionDAG &DAG) {
15955 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
15956 MVT DstVT = Op.getSimpleValueType();
15958 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
15959 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
15960 if (DstVT != MVT::f64)
15961 // This conversion needs to be expanded.
15964 SDValue InVec = Op->getOperand(0);
15966 unsigned NumElts = SrcVT.getVectorNumElements();
15967 EVT SVT = SrcVT.getVectorElementType();
15969 // Widen the vector in input in the case of MVT::v2i32.
15970 // Example: from MVT::v2i32 to MVT::v4i32.
15971 SmallVector<SDValue, 16> Elts;
15972 for (unsigned i = 0, e = NumElts; i != e; ++i)
15973 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
15974 DAG.getIntPtrConstant(i)));
15976 // Explicitly mark the extra elements as Undef.
15977 SDValue Undef = DAG.getUNDEF(SVT);
15978 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
15979 Elts.push_back(Undef);
15981 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
15982 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
15983 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
15984 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
15985 DAG.getIntPtrConstant(0));
15988 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
15989 Subtarget->hasMMX() && "Unexpected custom BITCAST");
15990 assert((DstVT == MVT::i64 ||
15991 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
15992 "Unexpected custom BITCAST");
15993 // i64 <=> MMX conversions are Legal.
15994 if (SrcVT==MVT::i64 && DstVT.isVector())
15996 if (DstVT==MVT::i64 && SrcVT.isVector())
15998 // MMX <=> MMX conversions are Legal.
15999 if (SrcVT.isVector() && DstVT.isVector())
16001 // All other conversions need to be expanded.
16005 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16006 SDNode *Node = Op.getNode();
16008 EVT T = Node->getValueType(0);
16009 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16010 DAG.getConstant(0, T), Node->getOperand(2));
16011 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16012 cast<AtomicSDNode>(Node)->getMemoryVT(),
16013 Node->getOperand(0),
16014 Node->getOperand(1), negOp,
16015 cast<AtomicSDNode>(Node)->getMemOperand(),
16016 cast<AtomicSDNode>(Node)->getOrdering(),
16017 cast<AtomicSDNode>(Node)->getSynchScope());
16020 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16021 SDNode *Node = Op.getNode();
16023 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16025 // Convert seq_cst store -> xchg
16026 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16027 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16028 // (The only way to get a 16-byte store is cmpxchg16b)
16029 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16030 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16031 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16032 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16033 cast<AtomicSDNode>(Node)->getMemoryVT(),
16034 Node->getOperand(0),
16035 Node->getOperand(1), Node->getOperand(2),
16036 cast<AtomicSDNode>(Node)->getMemOperand(),
16037 cast<AtomicSDNode>(Node)->getOrdering(),
16038 cast<AtomicSDNode>(Node)->getSynchScope());
16039 return Swap.getValue(1);
16041 // Other atomic stores have a simple pattern.
16045 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16046 EVT VT = Op.getNode()->getSimpleValueType(0);
16048 // Let legalize expand this if it isn't a legal type yet.
16049 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16052 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16055 bool ExtraOp = false;
16056 switch (Op.getOpcode()) {
16057 default: llvm_unreachable("Invalid code");
16058 case ISD::ADDC: Opc = X86ISD::ADD; break;
16059 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16060 case ISD::SUBC: Opc = X86ISD::SUB; break;
16061 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16065 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16067 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16068 Op.getOperand(1), Op.getOperand(2));
16071 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16072 SelectionDAG &DAG) {
16073 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16075 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16076 // which returns the values as { float, float } (in XMM0) or
16077 // { double, double } (which is returned in XMM0, XMM1).
16079 SDValue Arg = Op.getOperand(0);
16080 EVT ArgVT = Arg.getValueType();
16081 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16083 TargetLowering::ArgListTy Args;
16084 TargetLowering::ArgListEntry Entry;
16088 Entry.isSExt = false;
16089 Entry.isZExt = false;
16090 Args.push_back(Entry);
16092 bool isF64 = ArgVT == MVT::f64;
16093 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16094 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16095 // the results are returned via SRet in memory.
16096 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16098 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16100 Type *RetTy = isF64
16101 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16102 : (Type*)VectorType::get(ArgTy, 4);
16104 TargetLowering::CallLoweringInfo CLI(DAG);
16105 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16106 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16108 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16111 // Returned in xmm0 and xmm1.
16112 return CallResult.first;
16114 // Returned in bits 0:31 and 32:64 xmm0.
16115 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16116 CallResult.first, DAG.getIntPtrConstant(0));
16117 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16118 CallResult.first, DAG.getIntPtrConstant(1));
16119 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16120 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16123 /// LowerOperation - Provide custom lowering hooks for some operations.
16125 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16126 switch (Op.getOpcode()) {
16127 default: llvm_unreachable("Should not custom lower this!");
16128 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16129 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16130 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16131 return LowerCMP_SWAP(Op, Subtarget, DAG);
16132 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16133 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16134 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16135 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16136 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16137 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16138 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16139 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16140 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16141 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16142 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16143 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16144 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16145 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16146 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16147 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16148 case ISD::SHL_PARTS:
16149 case ISD::SRA_PARTS:
16150 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16151 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16152 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16153 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16154 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16155 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16156 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16157 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16158 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16159 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16160 case ISD::FABS: return LowerFABS(Op, DAG);
16161 case ISD::FNEG: return LowerFNEG(Op, DAG);
16162 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16163 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16164 case ISD::SETCC: return LowerSETCC(Op, DAG);
16165 case ISD::SELECT: return LowerSELECT(Op, DAG);
16166 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16167 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16168 case ISD::VASTART: return LowerVASTART(Op, DAG);
16169 case ISD::VAARG: return LowerVAARG(Op, DAG);
16170 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16171 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16172 case ISD::INTRINSIC_VOID:
16173 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16174 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16175 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16176 case ISD::FRAME_TO_ARGS_OFFSET:
16177 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16178 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16179 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16180 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16181 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16182 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16183 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16184 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16185 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16186 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16187 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16188 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16189 case ISD::UMUL_LOHI:
16190 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16193 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16199 case ISD::UMULO: return LowerXALUO(Op, DAG);
16200 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16201 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16205 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16206 case ISD::ADD: return LowerADD(Op, DAG);
16207 case ISD::SUB: return LowerSUB(Op, DAG);
16208 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16212 static void ReplaceATOMIC_LOAD(SDNode *Node,
16213 SmallVectorImpl<SDValue> &Results,
16214 SelectionDAG &DAG) {
16216 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16218 // Convert wide load -> cmpxchg8b/cmpxchg16b
16219 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16220 // (The only way to get a 16-byte load is cmpxchg16b)
16221 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16222 SDValue Zero = DAG.getConstant(0, VT);
16223 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16225 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16226 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16227 cast<AtomicSDNode>(Node)->getMemOperand(),
16228 cast<AtomicSDNode>(Node)->getOrdering(),
16229 cast<AtomicSDNode>(Node)->getOrdering(),
16230 cast<AtomicSDNode>(Node)->getSynchScope());
16231 Results.push_back(Swap.getValue(0));
16232 Results.push_back(Swap.getValue(2));
16235 /// ReplaceNodeResults - Replace a node with an illegal result type
16236 /// with a new node built out of custom code.
16237 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16238 SmallVectorImpl<SDValue>&Results,
16239 SelectionDAG &DAG) const {
16241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16242 switch (N->getOpcode()) {
16244 llvm_unreachable("Do not know how to custom type legalize this operation!");
16245 case ISD::SIGN_EXTEND_INREG:
16250 // We don't want to expand or promote these.
16257 case ISD::UDIVREM: {
16258 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16259 Results.push_back(V);
16262 case ISD::FP_TO_SINT:
16263 case ISD::FP_TO_UINT: {
16264 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16266 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16269 std::pair<SDValue,SDValue> Vals =
16270 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16271 SDValue FIST = Vals.first, StackSlot = Vals.second;
16272 if (FIST.getNode()) {
16273 EVT VT = N->getValueType(0);
16274 // Return a load from the stack slot.
16275 if (StackSlot.getNode())
16276 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16277 MachinePointerInfo(),
16278 false, false, false, 0));
16280 Results.push_back(FIST);
16284 case ISD::UINT_TO_FP: {
16285 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16286 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16287 N->getValueType(0) != MVT::v2f32)
16289 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16291 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16293 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16294 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16295 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16296 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16297 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16298 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16301 case ISD::FP_ROUND: {
16302 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16304 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16305 Results.push_back(V);
16308 case ISD::INTRINSIC_W_CHAIN: {
16309 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16311 default : llvm_unreachable("Do not know how to custom type "
16312 "legalize this intrinsic operation!");
16313 case Intrinsic::x86_rdtsc:
16314 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16316 case Intrinsic::x86_rdtscp:
16317 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16319 case Intrinsic::x86_rdpmc:
16320 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16323 case ISD::READCYCLECOUNTER: {
16324 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16327 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16328 EVT T = N->getValueType(0);
16329 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16330 bool Regs64bit = T == MVT::i128;
16331 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16332 SDValue cpInL, cpInH;
16333 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16334 DAG.getConstant(0, HalfT));
16335 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16336 DAG.getConstant(1, HalfT));
16337 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16338 Regs64bit ? X86::RAX : X86::EAX,
16340 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16341 Regs64bit ? X86::RDX : X86::EDX,
16342 cpInH, cpInL.getValue(1));
16343 SDValue swapInL, swapInH;
16344 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16345 DAG.getConstant(0, HalfT));
16346 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16347 DAG.getConstant(1, HalfT));
16348 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16349 Regs64bit ? X86::RBX : X86::EBX,
16350 swapInL, cpInH.getValue(1));
16351 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16352 Regs64bit ? X86::RCX : X86::ECX,
16353 swapInH, swapInL.getValue(1));
16354 SDValue Ops[] = { swapInH.getValue(0),
16356 swapInH.getValue(1) };
16357 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16358 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16359 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16360 X86ISD::LCMPXCHG8_DAG;
16361 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16362 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16363 Regs64bit ? X86::RAX : X86::EAX,
16364 HalfT, Result.getValue(1));
16365 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16366 Regs64bit ? X86::RDX : X86::EDX,
16367 HalfT, cpOutL.getValue(2));
16368 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16370 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16371 MVT::i32, cpOutH.getValue(2));
16373 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16374 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16375 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16377 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16378 Results.push_back(Success);
16379 Results.push_back(EFLAGS.getValue(1));
16382 case ISD::ATOMIC_SWAP:
16383 case ISD::ATOMIC_LOAD_ADD:
16384 case ISD::ATOMIC_LOAD_SUB:
16385 case ISD::ATOMIC_LOAD_AND:
16386 case ISD::ATOMIC_LOAD_OR:
16387 case ISD::ATOMIC_LOAD_XOR:
16388 case ISD::ATOMIC_LOAD_NAND:
16389 case ISD::ATOMIC_LOAD_MIN:
16390 case ISD::ATOMIC_LOAD_MAX:
16391 case ISD::ATOMIC_LOAD_UMIN:
16392 case ISD::ATOMIC_LOAD_UMAX:
16393 // Delegate to generic TypeLegalization. Situations we can really handle
16394 // should have already been dealt with by X86AtomicExpand.cpp.
16396 case ISD::ATOMIC_LOAD: {
16397 ReplaceATOMIC_LOAD(N, Results, DAG);
16400 case ISD::BITCAST: {
16401 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16402 EVT DstVT = N->getValueType(0);
16403 EVT SrcVT = N->getOperand(0)->getValueType(0);
16405 if (SrcVT != MVT::f64 ||
16406 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16409 unsigned NumElts = DstVT.getVectorNumElements();
16410 EVT SVT = DstVT.getVectorElementType();
16411 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16412 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16413 MVT::v2f64, N->getOperand(0));
16414 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16416 if (ExperimentalVectorWideningLegalization) {
16417 // If we are legalizing vectors by widening, we already have the desired
16418 // legal vector type, just return it.
16419 Results.push_back(ToVecInt);
16423 SmallVector<SDValue, 8> Elts;
16424 for (unsigned i = 0, e = NumElts; i != e; ++i)
16425 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16426 ToVecInt, DAG.getIntPtrConstant(i)));
16428 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16433 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
16435 default: return nullptr;
16436 case X86ISD::BSF: return "X86ISD::BSF";
16437 case X86ISD::BSR: return "X86ISD::BSR";
16438 case X86ISD::SHLD: return "X86ISD::SHLD";
16439 case X86ISD::SHRD: return "X86ISD::SHRD";
16440 case X86ISD::FAND: return "X86ISD::FAND";
16441 case X86ISD::FANDN: return "X86ISD::FANDN";
16442 case X86ISD::FOR: return "X86ISD::FOR";
16443 case X86ISD::FXOR: return "X86ISD::FXOR";
16444 case X86ISD::FSRL: return "X86ISD::FSRL";
16445 case X86ISD::FILD: return "X86ISD::FILD";
16446 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16447 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16448 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16449 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16450 case X86ISD::FLD: return "X86ISD::FLD";
16451 case X86ISD::FST: return "X86ISD::FST";
16452 case X86ISD::CALL: return "X86ISD::CALL";
16453 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16454 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16455 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16456 case X86ISD::BT: return "X86ISD::BT";
16457 case X86ISD::CMP: return "X86ISD::CMP";
16458 case X86ISD::COMI: return "X86ISD::COMI";
16459 case X86ISD::UCOMI: return "X86ISD::UCOMI";
16460 case X86ISD::CMPM: return "X86ISD::CMPM";
16461 case X86ISD::CMPMU: return "X86ISD::CMPMU";
16462 case X86ISD::SETCC: return "X86ISD::SETCC";
16463 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16464 case X86ISD::FSETCC: return "X86ISD::FSETCC";
16465 case X86ISD::CMOV: return "X86ISD::CMOV";
16466 case X86ISD::BRCOND: return "X86ISD::BRCOND";
16467 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16468 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16469 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16470 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16471 case X86ISD::Wrapper: return "X86ISD::Wrapper";
16472 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
16473 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
16474 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
16475 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
16476 case X86ISD::PINSRB: return "X86ISD::PINSRB";
16477 case X86ISD::PINSRW: return "X86ISD::PINSRW";
16478 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
16479 case X86ISD::ANDNP: return "X86ISD::ANDNP";
16480 case X86ISD::PSIGN: return "X86ISD::PSIGN";
16481 case X86ISD::BLENDV: return "X86ISD::BLENDV";
16482 case X86ISD::BLENDI: return "X86ISD::BLENDI";
16483 case X86ISD::SUBUS: return "X86ISD::SUBUS";
16484 case X86ISD::HADD: return "X86ISD::HADD";
16485 case X86ISD::HSUB: return "X86ISD::HSUB";
16486 case X86ISD::FHADD: return "X86ISD::FHADD";
16487 case X86ISD::FHSUB: return "X86ISD::FHSUB";
16488 case X86ISD::UMAX: return "X86ISD::UMAX";
16489 case X86ISD::UMIN: return "X86ISD::UMIN";
16490 case X86ISD::SMAX: return "X86ISD::SMAX";
16491 case X86ISD::SMIN: return "X86ISD::SMIN";
16492 case X86ISD::FMAX: return "X86ISD::FMAX";
16493 case X86ISD::FMIN: return "X86ISD::FMIN";
16494 case X86ISD::FMAXC: return "X86ISD::FMAXC";
16495 case X86ISD::FMINC: return "X86ISD::FMINC";
16496 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
16497 case X86ISD::FRCP: return "X86ISD::FRCP";
16498 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
16499 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
16500 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
16501 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
16502 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
16503 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
16504 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
16505 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
16506 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
16507 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
16508 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
16509 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
16510 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
16511 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
16512 case X86ISD::VZEXT: return "X86ISD::VZEXT";
16513 case X86ISD::VSEXT: return "X86ISD::VSEXT";
16514 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
16515 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
16516 case X86ISD::VINSERT: return "X86ISD::VINSERT";
16517 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
16518 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
16519 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
16520 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
16521 case X86ISD::VSHL: return "X86ISD::VSHL";
16522 case X86ISD::VSRL: return "X86ISD::VSRL";
16523 case X86ISD::VSRA: return "X86ISD::VSRA";
16524 case X86ISD::VSHLI: return "X86ISD::VSHLI";
16525 case X86ISD::VSRLI: return "X86ISD::VSRLI";
16526 case X86ISD::VSRAI: return "X86ISD::VSRAI";
16527 case X86ISD::CMPP: return "X86ISD::CMPP";
16528 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
16529 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
16530 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
16531 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
16532 case X86ISD::ADD: return "X86ISD::ADD";
16533 case X86ISD::SUB: return "X86ISD::SUB";
16534 case X86ISD::ADC: return "X86ISD::ADC";
16535 case X86ISD::SBB: return "X86ISD::SBB";
16536 case X86ISD::SMUL: return "X86ISD::SMUL";
16537 case X86ISD::UMUL: return "X86ISD::UMUL";
16538 case X86ISD::INC: return "X86ISD::INC";
16539 case X86ISD::DEC: return "X86ISD::DEC";
16540 case X86ISD::OR: return "X86ISD::OR";
16541 case X86ISD::XOR: return "X86ISD::XOR";
16542 case X86ISD::AND: return "X86ISD::AND";
16543 case X86ISD::BEXTR: return "X86ISD::BEXTR";
16544 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
16545 case X86ISD::PTEST: return "X86ISD::PTEST";
16546 case X86ISD::TESTP: return "X86ISD::TESTP";
16547 case X86ISD::TESTM: return "X86ISD::TESTM";
16548 case X86ISD::TESTNM: return "X86ISD::TESTNM";
16549 case X86ISD::KORTEST: return "X86ISD::KORTEST";
16550 case X86ISD::PACKSS: return "X86ISD::PACKSS";
16551 case X86ISD::PACKUS: return "X86ISD::PACKUS";
16552 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
16553 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
16554 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
16555 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
16556 case X86ISD::SHUFP: return "X86ISD::SHUFP";
16557 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
16558 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
16559 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
16560 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
16561 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
16562 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
16563 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
16564 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
16565 case X86ISD::MOVSD: return "X86ISD::MOVSD";
16566 case X86ISD::MOVSS: return "X86ISD::MOVSS";
16567 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
16568 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
16569 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
16570 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
16571 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
16572 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
16573 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
16574 case X86ISD::VPERMV: return "X86ISD::VPERMV";
16575 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
16576 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
16577 case X86ISD::VPERMI: return "X86ISD::VPERMI";
16578 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
16579 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
16580 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
16581 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
16582 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
16583 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
16584 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
16585 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
16586 case X86ISD::SAHF: return "X86ISD::SAHF";
16587 case X86ISD::RDRAND: return "X86ISD::RDRAND";
16588 case X86ISD::RDSEED: return "X86ISD::RDSEED";
16589 case X86ISD::FMADD: return "X86ISD::FMADD";
16590 case X86ISD::FMSUB: return "X86ISD::FMSUB";
16591 case X86ISD::FNMADD: return "X86ISD::FNMADD";
16592 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
16593 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
16594 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
16595 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
16596 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
16597 case X86ISD::XTEST: return "X86ISD::XTEST";
16601 // isLegalAddressingMode - Return true if the addressing mode represented
16602 // by AM is legal for this target, for a load/store of the specified type.
16603 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
16605 // X86 supports extremely general addressing modes.
16606 CodeModel::Model M = getTargetMachine().getCodeModel();
16607 Reloc::Model R = getTargetMachine().getRelocationModel();
16609 // X86 allows a sign-extended 32-bit immediate field as a displacement.
16610 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16615 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
16617 // If a reference to this global requires an extra load, we can't fold it.
16618 if (isGlobalStubReference(GVFlags))
16621 // If BaseGV requires a register for the PIC base, we cannot also have a
16622 // BaseReg specified.
16623 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
16626 // If lower 4G is not available, then we must use rip-relative addressing.
16627 if ((M != CodeModel::Small || R != Reloc::Static) &&
16628 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
16632 switch (AM.Scale) {
16638 // These scales always work.
16643 // These scales are formed with basereg+scalereg. Only accept if there is
16648 default: // Other stuff never works.
16655 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
16656 unsigned Bits = Ty->getScalarSizeInBits();
16658 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
16659 // particularly cheaper than those without.
16663 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
16664 // variable shifts just as cheap as scalar ones.
16665 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
16668 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
16669 // fully general vector.
16673 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
16674 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16676 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
16677 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
16678 return NumBits1 > NumBits2;
16681 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
16682 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16685 if (!isTypeLegal(EVT::getEVT(Ty1)))
16688 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
16690 // Assuming the caller doesn't have a zeroext or signext return parameter,
16691 // truncation all the way down to i1 is valid.
16695 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
16696 return isInt<32>(Imm);
16699 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
16700 // Can also use sub to handle negated immediates.
16701 return isInt<32>(Imm);
16704 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
16705 if (!VT1.isInteger() || !VT2.isInteger())
16707 unsigned NumBits1 = VT1.getSizeInBits();
16708 unsigned NumBits2 = VT2.getSizeInBits();
16709 return NumBits1 > NumBits2;
16712 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
16713 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16714 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
16717 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
16718 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16719 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
16722 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
16723 EVT VT1 = Val.getValueType();
16724 if (isZExtFree(VT1, VT2))
16727 if (Val.getOpcode() != ISD::LOAD)
16730 if (!VT1.isSimple() || !VT1.isInteger() ||
16731 !VT2.isSimple() || !VT2.isInteger())
16734 switch (VT1.getSimpleVT().SimpleTy) {
16739 // X86 has 8, 16, and 32-bit zero-extending loads.
16747 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
16748 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
16751 VT = VT.getScalarType();
16753 if (!VT.isSimple())
16756 switch (VT.getSimpleVT().SimpleTy) {
16767 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
16768 // i16 instructions are longer (0x66 prefix) and potentially slower.
16769 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
16772 /// isShuffleMaskLegal - Targets can use this to indicate that they only
16773 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
16774 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
16775 /// are assumed to be legal.
16777 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
16779 if (!VT.isSimple())
16782 MVT SVT = VT.getSimpleVT();
16784 // Very little shuffling can be done for 64-bit vectors right now.
16785 if (VT.getSizeInBits() == 64)
16788 // If this is a single-input shuffle with no 128 bit lane crossings we can
16789 // lower it into pshufb.
16790 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
16791 (SVT.is256BitVector() && Subtarget->hasInt256())) {
16792 bool isLegal = true;
16793 for (unsigned I = 0, E = M.size(); I != E; ++I) {
16794 if (M[I] >= (int)SVT.getVectorNumElements() ||
16795 ShuffleCrosses128bitLane(SVT, I, M[I])) {
16804 // FIXME: blends, shifts.
16805 return (SVT.getVectorNumElements() == 2 ||
16806 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
16807 isMOVLMask(M, SVT) ||
16808 isSHUFPMask(M, SVT) ||
16809 isPSHUFDMask(M, SVT) ||
16810 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
16811 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
16812 isPALIGNRMask(M, SVT, Subtarget) ||
16813 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
16814 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
16815 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16816 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16817 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
16821 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
16823 if (!VT.isSimple())
16826 MVT SVT = VT.getSimpleVT();
16827 unsigned NumElts = SVT.getVectorNumElements();
16828 // FIXME: This collection of masks seems suspect.
16831 if (NumElts == 4 && SVT.is128BitVector()) {
16832 return (isMOVLMask(Mask, SVT) ||
16833 isCommutedMOVLMask(Mask, SVT, true) ||
16834 isSHUFPMask(Mask, SVT) ||
16835 isSHUFPMask(Mask, SVT, /* Commuted */ true));
16840 //===----------------------------------------------------------------------===//
16841 // X86 Scheduler Hooks
16842 //===----------------------------------------------------------------------===//
16844 /// Utility function to emit xbegin specifying the start of an RTM region.
16845 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
16846 const TargetInstrInfo *TII) {
16847 DebugLoc DL = MI->getDebugLoc();
16849 const BasicBlock *BB = MBB->getBasicBlock();
16850 MachineFunction::iterator I = MBB;
16853 // For the v = xbegin(), we generate
16864 MachineBasicBlock *thisMBB = MBB;
16865 MachineFunction *MF = MBB->getParent();
16866 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16867 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16868 MF->insert(I, mainMBB);
16869 MF->insert(I, sinkMBB);
16871 // Transfer the remainder of BB and its successor edges to sinkMBB.
16872 sinkMBB->splice(sinkMBB->begin(), MBB,
16873 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16874 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16878 // # fallthrough to mainMBB
16879 // # abortion to sinkMBB
16880 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
16881 thisMBB->addSuccessor(mainMBB);
16882 thisMBB->addSuccessor(sinkMBB);
16886 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
16887 mainMBB->addSuccessor(sinkMBB);
16890 // EAX is live into the sinkMBB
16891 sinkMBB->addLiveIn(X86::EAX);
16892 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16893 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16896 MI->eraseFromParent();
16900 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
16901 // or XMM0_V32I8 in AVX all of this code can be replaced with that
16902 // in the .td file.
16903 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
16904 const TargetInstrInfo *TII) {
16906 switch (MI->getOpcode()) {
16907 default: llvm_unreachable("illegal opcode!");
16908 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
16909 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
16910 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
16911 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
16912 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
16913 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
16914 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
16915 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
16918 DebugLoc dl = MI->getDebugLoc();
16919 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16921 unsigned NumArgs = MI->getNumOperands();
16922 for (unsigned i = 1; i < NumArgs; ++i) {
16923 MachineOperand &Op = MI->getOperand(i);
16924 if (!(Op.isReg() && Op.isImplicit()))
16925 MIB.addOperand(Op);
16927 if (MI->hasOneMemOperand())
16928 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16930 BuildMI(*BB, MI, dl,
16931 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16932 .addReg(X86::XMM0);
16934 MI->eraseFromParent();
16938 // FIXME: Custom handling because TableGen doesn't support multiple implicit
16939 // defs in an instruction pattern
16940 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
16941 const TargetInstrInfo *TII) {
16943 switch (MI->getOpcode()) {
16944 default: llvm_unreachable("illegal opcode!");
16945 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
16946 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
16947 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
16948 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
16949 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
16950 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
16951 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
16952 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
16955 DebugLoc dl = MI->getDebugLoc();
16956 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16958 unsigned NumArgs = MI->getNumOperands(); // remove the results
16959 for (unsigned i = 1; i < NumArgs; ++i) {
16960 MachineOperand &Op = MI->getOperand(i);
16961 if (!(Op.isReg() && Op.isImplicit()))
16962 MIB.addOperand(Op);
16964 if (MI->hasOneMemOperand())
16965 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16967 BuildMI(*BB, MI, dl,
16968 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16971 MI->eraseFromParent();
16975 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
16976 const TargetInstrInfo *TII,
16977 const X86Subtarget* Subtarget) {
16978 DebugLoc dl = MI->getDebugLoc();
16980 // Address into RAX/EAX, other two args into ECX, EDX.
16981 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
16982 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
16983 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
16984 for (int i = 0; i < X86::AddrNumOperands; ++i)
16985 MIB.addOperand(MI->getOperand(i));
16987 unsigned ValOps = X86::AddrNumOperands;
16988 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
16989 .addReg(MI->getOperand(ValOps).getReg());
16990 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
16991 .addReg(MI->getOperand(ValOps+1).getReg());
16993 // The instruction doesn't actually take any operands though.
16994 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
16996 MI->eraseFromParent(); // The pseudo is gone now.
17000 MachineBasicBlock *
17001 X86TargetLowering::EmitVAARG64WithCustomInserter(
17003 MachineBasicBlock *MBB) const {
17004 // Emit va_arg instruction on X86-64.
17006 // Operands to this pseudo-instruction:
17007 // 0 ) Output : destination address (reg)
17008 // 1-5) Input : va_list address (addr, i64mem)
17009 // 6 ) ArgSize : Size (in bytes) of vararg type
17010 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17011 // 8 ) Align : Alignment of type
17012 // 9 ) EFLAGS (implicit-def)
17014 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17015 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17017 unsigned DestReg = MI->getOperand(0).getReg();
17018 MachineOperand &Base = MI->getOperand(1);
17019 MachineOperand &Scale = MI->getOperand(2);
17020 MachineOperand &Index = MI->getOperand(3);
17021 MachineOperand &Disp = MI->getOperand(4);
17022 MachineOperand &Segment = MI->getOperand(5);
17023 unsigned ArgSize = MI->getOperand(6).getImm();
17024 unsigned ArgMode = MI->getOperand(7).getImm();
17025 unsigned Align = MI->getOperand(8).getImm();
17027 // Memory Reference
17028 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17029 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17030 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17032 // Machine Information
17033 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17034 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17035 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17036 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17037 DebugLoc DL = MI->getDebugLoc();
17039 // struct va_list {
17042 // i64 overflow_area (address)
17043 // i64 reg_save_area (address)
17045 // sizeof(va_list) = 24
17046 // alignment(va_list) = 8
17048 unsigned TotalNumIntRegs = 6;
17049 unsigned TotalNumXMMRegs = 8;
17050 bool UseGPOffset = (ArgMode == 1);
17051 bool UseFPOffset = (ArgMode == 2);
17052 unsigned MaxOffset = TotalNumIntRegs * 8 +
17053 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17055 /* Align ArgSize to a multiple of 8 */
17056 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17057 bool NeedsAlign = (Align > 8);
17059 MachineBasicBlock *thisMBB = MBB;
17060 MachineBasicBlock *overflowMBB;
17061 MachineBasicBlock *offsetMBB;
17062 MachineBasicBlock *endMBB;
17064 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17065 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17066 unsigned OffsetReg = 0;
17068 if (!UseGPOffset && !UseFPOffset) {
17069 // If we only pull from the overflow region, we don't create a branch.
17070 // We don't need to alter control flow.
17071 OffsetDestReg = 0; // unused
17072 OverflowDestReg = DestReg;
17074 offsetMBB = nullptr;
17075 overflowMBB = thisMBB;
17078 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17079 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17080 // If not, pull from overflow_area. (branch to overflowMBB)
17085 // offsetMBB overflowMBB
17090 // Registers for the PHI in endMBB
17091 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17092 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17094 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17095 MachineFunction *MF = MBB->getParent();
17096 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17097 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17098 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17100 MachineFunction::iterator MBBIter = MBB;
17103 // Insert the new basic blocks
17104 MF->insert(MBBIter, offsetMBB);
17105 MF->insert(MBBIter, overflowMBB);
17106 MF->insert(MBBIter, endMBB);
17108 // Transfer the remainder of MBB and its successor edges to endMBB.
17109 endMBB->splice(endMBB->begin(), thisMBB,
17110 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17111 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17113 // Make offsetMBB and overflowMBB successors of thisMBB
17114 thisMBB->addSuccessor(offsetMBB);
17115 thisMBB->addSuccessor(overflowMBB);
17117 // endMBB is a successor of both offsetMBB and overflowMBB
17118 offsetMBB->addSuccessor(endMBB);
17119 overflowMBB->addSuccessor(endMBB);
17121 // Load the offset value into a register
17122 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17123 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17127 .addDisp(Disp, UseFPOffset ? 4 : 0)
17128 .addOperand(Segment)
17129 .setMemRefs(MMOBegin, MMOEnd);
17131 // Check if there is enough room left to pull this argument.
17132 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17134 .addImm(MaxOffset + 8 - ArgSizeA8);
17136 // Branch to "overflowMBB" if offset >= max
17137 // Fall through to "offsetMBB" otherwise
17138 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17139 .addMBB(overflowMBB);
17142 // In offsetMBB, emit code to use the reg_save_area.
17144 assert(OffsetReg != 0);
17146 // Read the reg_save_area address.
17147 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17148 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17153 .addOperand(Segment)
17154 .setMemRefs(MMOBegin, MMOEnd);
17156 // Zero-extend the offset
17157 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17158 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17161 .addImm(X86::sub_32bit);
17163 // Add the offset to the reg_save_area to get the final address.
17164 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17165 .addReg(OffsetReg64)
17166 .addReg(RegSaveReg);
17168 // Compute the offset for the next argument
17169 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17170 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17172 .addImm(UseFPOffset ? 16 : 8);
17174 // Store it back into the va_list.
17175 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17179 .addDisp(Disp, UseFPOffset ? 4 : 0)
17180 .addOperand(Segment)
17181 .addReg(NextOffsetReg)
17182 .setMemRefs(MMOBegin, MMOEnd);
17185 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17190 // Emit code to use overflow area
17193 // Load the overflow_area address into a register.
17194 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17195 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17200 .addOperand(Segment)
17201 .setMemRefs(MMOBegin, MMOEnd);
17203 // If we need to align it, do so. Otherwise, just copy the address
17204 // to OverflowDestReg.
17206 // Align the overflow address
17207 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17208 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17210 // aligned_addr = (addr + (align-1)) & ~(align-1)
17211 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17212 .addReg(OverflowAddrReg)
17215 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17217 .addImm(~(uint64_t)(Align-1));
17219 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17220 .addReg(OverflowAddrReg);
17223 // Compute the next overflow address after this argument.
17224 // (the overflow address should be kept 8-byte aligned)
17225 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17226 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17227 .addReg(OverflowDestReg)
17228 .addImm(ArgSizeA8);
17230 // Store the new overflow address.
17231 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17236 .addOperand(Segment)
17237 .addReg(NextAddrReg)
17238 .setMemRefs(MMOBegin, MMOEnd);
17240 // If we branched, emit the PHI to the front of endMBB.
17242 BuildMI(*endMBB, endMBB->begin(), DL,
17243 TII->get(X86::PHI), DestReg)
17244 .addReg(OffsetDestReg).addMBB(offsetMBB)
17245 .addReg(OverflowDestReg).addMBB(overflowMBB);
17248 // Erase the pseudo instruction
17249 MI->eraseFromParent();
17254 MachineBasicBlock *
17255 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17257 MachineBasicBlock *MBB) const {
17258 // Emit code to save XMM registers to the stack. The ABI says that the
17259 // number of registers to save is given in %al, so it's theoretically
17260 // possible to do an indirect jump trick to avoid saving all of them,
17261 // however this code takes a simpler approach and just executes all
17262 // of the stores if %al is non-zero. It's less code, and it's probably
17263 // easier on the hardware branch predictor, and stores aren't all that
17264 // expensive anyway.
17266 // Create the new basic blocks. One block contains all the XMM stores,
17267 // and one block is the final destination regardless of whether any
17268 // stores were performed.
17269 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17270 MachineFunction *F = MBB->getParent();
17271 MachineFunction::iterator MBBIter = MBB;
17273 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17274 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17275 F->insert(MBBIter, XMMSaveMBB);
17276 F->insert(MBBIter, EndMBB);
17278 // Transfer the remainder of MBB and its successor edges to EndMBB.
17279 EndMBB->splice(EndMBB->begin(), MBB,
17280 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17281 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17283 // The original block will now fall through to the XMM save block.
17284 MBB->addSuccessor(XMMSaveMBB);
17285 // The XMMSaveMBB will fall through to the end block.
17286 XMMSaveMBB->addSuccessor(EndMBB);
17288 // Now add the instructions.
17289 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17290 DebugLoc DL = MI->getDebugLoc();
17292 unsigned CountReg = MI->getOperand(0).getReg();
17293 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17294 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17296 if (!Subtarget->isTargetWin64()) {
17297 // If %al is 0, branch around the XMM save block.
17298 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17299 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17300 MBB->addSuccessor(EndMBB);
17303 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17304 // that was just emitted, but clearly shouldn't be "saved".
17305 assert((MI->getNumOperands() <= 3 ||
17306 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17307 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17308 && "Expected last argument to be EFLAGS");
17309 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17310 // In the XMM save block, save all the XMM argument registers.
17311 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17312 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17313 MachineMemOperand *MMO =
17314 F->getMachineMemOperand(
17315 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17316 MachineMemOperand::MOStore,
17317 /*Size=*/16, /*Align=*/16);
17318 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17319 .addFrameIndex(RegSaveFrameIndex)
17320 .addImm(/*Scale=*/1)
17321 .addReg(/*IndexReg=*/0)
17322 .addImm(/*Disp=*/Offset)
17323 .addReg(/*Segment=*/0)
17324 .addReg(MI->getOperand(i).getReg())
17325 .addMemOperand(MMO);
17328 MI->eraseFromParent(); // The pseudo instruction is gone now.
17333 // The EFLAGS operand of SelectItr might be missing a kill marker
17334 // because there were multiple uses of EFLAGS, and ISel didn't know
17335 // which to mark. Figure out whether SelectItr should have had a
17336 // kill marker, and set it if it should. Returns the correct kill
17338 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17339 MachineBasicBlock* BB,
17340 const TargetRegisterInfo* TRI) {
17341 // Scan forward through BB for a use/def of EFLAGS.
17342 MachineBasicBlock::iterator miI(std::next(SelectItr));
17343 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17344 const MachineInstr& mi = *miI;
17345 if (mi.readsRegister(X86::EFLAGS))
17347 if (mi.definesRegister(X86::EFLAGS))
17348 break; // Should have kill-flag - update below.
17351 // If we hit the end of the block, check whether EFLAGS is live into a
17353 if (miI == BB->end()) {
17354 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17355 sEnd = BB->succ_end();
17356 sItr != sEnd; ++sItr) {
17357 MachineBasicBlock* succ = *sItr;
17358 if (succ->isLiveIn(X86::EFLAGS))
17363 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17364 // out. SelectMI should have a kill flag on EFLAGS.
17365 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17369 MachineBasicBlock *
17370 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17371 MachineBasicBlock *BB) const {
17372 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17373 DebugLoc DL = MI->getDebugLoc();
17375 // To "insert" a SELECT_CC instruction, we actually have to insert the
17376 // diamond control-flow pattern. The incoming instruction knows the
17377 // destination vreg to set, the condition code register to branch on, the
17378 // true/false values to select between, and a branch opcode to use.
17379 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17380 MachineFunction::iterator It = BB;
17386 // cmpTY ccX, r1, r2
17388 // fallthrough --> copy0MBB
17389 MachineBasicBlock *thisMBB = BB;
17390 MachineFunction *F = BB->getParent();
17391 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17392 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17393 F->insert(It, copy0MBB);
17394 F->insert(It, sinkMBB);
17396 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17397 // live into the sink and copy blocks.
17398 const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
17399 if (!MI->killsRegister(X86::EFLAGS) &&
17400 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17401 copy0MBB->addLiveIn(X86::EFLAGS);
17402 sinkMBB->addLiveIn(X86::EFLAGS);
17405 // Transfer the remainder of BB and its successor edges to sinkMBB.
17406 sinkMBB->splice(sinkMBB->begin(), BB,
17407 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17408 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17410 // Add the true and fallthrough blocks as its successors.
17411 BB->addSuccessor(copy0MBB);
17412 BB->addSuccessor(sinkMBB);
17414 // Create the conditional branch instruction.
17416 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17417 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17420 // %FalseValue = ...
17421 // # fallthrough to sinkMBB
17422 copy0MBB->addSuccessor(sinkMBB);
17425 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17427 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17428 TII->get(X86::PHI), MI->getOperand(0).getReg())
17429 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17430 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17432 MI->eraseFromParent(); // The pseudo instruction is gone now.
17436 MachineBasicBlock *
17437 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
17438 bool Is64Bit) const {
17439 MachineFunction *MF = BB->getParent();
17440 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17441 DebugLoc DL = MI->getDebugLoc();
17442 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17444 assert(MF->shouldSplitStack());
17446 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17447 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17450 // ... [Till the alloca]
17451 // If stacklet is not large enough, jump to mallocMBB
17454 // Allocate by subtracting from RSP
17455 // Jump to continueMBB
17458 // Allocate by call to runtime
17462 // [rest of original BB]
17465 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17466 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17467 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17469 MachineRegisterInfo &MRI = MF->getRegInfo();
17470 const TargetRegisterClass *AddrRegClass =
17471 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
17473 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17474 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17475 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
17476 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
17477 sizeVReg = MI->getOperand(1).getReg(),
17478 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
17480 MachineFunction::iterator MBBIter = BB;
17483 MF->insert(MBBIter, bumpMBB);
17484 MF->insert(MBBIter, mallocMBB);
17485 MF->insert(MBBIter, continueMBB);
17487 continueMBB->splice(continueMBB->begin(), BB,
17488 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17489 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
17491 // Add code to the main basic block to check if the stack limit has been hit,
17492 // and if so, jump to mallocMBB otherwise to bumpMBB.
17493 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
17494 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
17495 .addReg(tmpSPVReg).addReg(sizeVReg);
17496 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
17497 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
17498 .addReg(SPLimitVReg);
17499 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
17501 // bumpMBB simply decreases the stack pointer, since we know the current
17502 // stacklet has enough space.
17503 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
17504 .addReg(SPLimitVReg);
17505 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
17506 .addReg(SPLimitVReg);
17507 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17509 // Calls into a routine in libgcc to allocate more space from the heap.
17510 const uint32_t *RegMask =
17511 MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17513 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
17515 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
17516 .addExternalSymbol("__morestack_allocate_stack_space")
17517 .addRegMask(RegMask)
17518 .addReg(X86::RDI, RegState::Implicit)
17519 .addReg(X86::RAX, RegState::ImplicitDefine);
17521 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
17523 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
17524 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
17525 .addExternalSymbol("__morestack_allocate_stack_space")
17526 .addRegMask(RegMask)
17527 .addReg(X86::EAX, RegState::ImplicitDefine);
17531 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
17534 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17535 .addReg(Is64Bit ? X86::RAX : X86::EAX);
17536 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17538 // Set up the CFG correctly.
17539 BB->addSuccessor(bumpMBB);
17540 BB->addSuccessor(mallocMBB);
17541 mallocMBB->addSuccessor(continueMBB);
17542 bumpMBB->addSuccessor(continueMBB);
17544 // Take care of the PHI nodes.
17545 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
17546 MI->getOperand(0).getReg())
17547 .addReg(mallocPtrVReg).addMBB(mallocMBB)
17548 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
17550 // Delete the original pseudo instruction.
17551 MI->eraseFromParent();
17554 return continueMBB;
17557 MachineBasicBlock *
17558 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
17559 MachineBasicBlock *BB) const {
17560 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17561 DebugLoc DL = MI->getDebugLoc();
17563 assert(!Subtarget->isTargetMacho());
17565 // The lowering is pretty easy: we're just emitting the call to _alloca. The
17566 // non-trivial part is impdef of ESP.
17568 if (Subtarget->isTargetWin64()) {
17569 if (Subtarget->isTargetCygMing()) {
17570 // ___chkstk(Mingw64):
17571 // Clobbers R10, R11, RAX and EFLAGS.
17573 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17574 .addExternalSymbol("___chkstk")
17575 .addReg(X86::RAX, RegState::Implicit)
17576 .addReg(X86::RSP, RegState::Implicit)
17577 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
17578 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
17579 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17581 // __chkstk(MSVCRT): does not update stack pointer.
17582 // Clobbers R10, R11 and EFLAGS.
17583 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17584 .addExternalSymbol("__chkstk")
17585 .addReg(X86::RAX, RegState::Implicit)
17586 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17587 // RAX has the offset to be subtracted from RSP.
17588 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
17593 const char *StackProbeSymbol =
17594 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
17596 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
17597 .addExternalSymbol(StackProbeSymbol)
17598 .addReg(X86::EAX, RegState::Implicit)
17599 .addReg(X86::ESP, RegState::Implicit)
17600 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
17601 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
17602 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17605 MI->eraseFromParent(); // The pseudo instruction is gone now.
17609 MachineBasicBlock *
17610 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
17611 MachineBasicBlock *BB) const {
17612 // This is pretty easy. We're taking the value that we received from
17613 // our load from the relocation, sticking it in either RDI (x86-64)
17614 // or EAX and doing an indirect call. The return value will then
17615 // be in the normal return register.
17616 MachineFunction *F = BB->getParent();
17617 const X86InstrInfo *TII
17618 = static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
17619 DebugLoc DL = MI->getDebugLoc();
17621 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
17622 assert(MI->getOperand(3).isGlobal() && "This should be a global");
17624 // Get a register mask for the lowered call.
17625 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
17626 // proper register mask.
17627 const uint32_t *RegMask =
17628 F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17629 if (Subtarget->is64Bit()) {
17630 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17631 TII->get(X86::MOV64rm), X86::RDI)
17633 .addImm(0).addReg(0)
17634 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17635 MI->getOperand(3).getTargetFlags())
17637 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
17638 addDirectMem(MIB, X86::RDI);
17639 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
17640 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
17641 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17642 TII->get(X86::MOV32rm), X86::EAX)
17644 .addImm(0).addReg(0)
17645 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17646 MI->getOperand(3).getTargetFlags())
17648 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17649 addDirectMem(MIB, X86::EAX);
17650 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17652 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17653 TII->get(X86::MOV32rm), X86::EAX)
17654 .addReg(TII->getGlobalBaseReg(F))
17655 .addImm(0).addReg(0)
17656 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17657 MI->getOperand(3).getTargetFlags())
17659 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17660 addDirectMem(MIB, X86::EAX);
17661 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17664 MI->eraseFromParent(); // The pseudo instruction is gone now.
17668 MachineBasicBlock *
17669 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
17670 MachineBasicBlock *MBB) const {
17671 DebugLoc DL = MI->getDebugLoc();
17672 MachineFunction *MF = MBB->getParent();
17673 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17674 MachineRegisterInfo &MRI = MF->getRegInfo();
17676 const BasicBlock *BB = MBB->getBasicBlock();
17677 MachineFunction::iterator I = MBB;
17680 // Memory Reference
17681 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17682 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17685 unsigned MemOpndSlot = 0;
17687 unsigned CurOp = 0;
17689 DstReg = MI->getOperand(CurOp++).getReg();
17690 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
17691 assert(RC->hasType(MVT::i32) && "Invalid destination!");
17692 unsigned mainDstReg = MRI.createVirtualRegister(RC);
17693 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
17695 MemOpndSlot = CurOp;
17697 MVT PVT = getPointerTy();
17698 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17699 "Invalid Pointer Size!");
17701 // For v = setjmp(buf), we generate
17704 // buf[LabelOffset] = restoreMBB
17705 // SjLjSetup restoreMBB
17711 // v = phi(main, restore)
17716 MachineBasicBlock *thisMBB = MBB;
17717 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17718 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17719 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
17720 MF->insert(I, mainMBB);
17721 MF->insert(I, sinkMBB);
17722 MF->push_back(restoreMBB);
17724 MachineInstrBuilder MIB;
17726 // Transfer the remainder of BB and its successor edges to sinkMBB.
17727 sinkMBB->splice(sinkMBB->begin(), MBB,
17728 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17729 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17732 unsigned PtrStoreOpc = 0;
17733 unsigned LabelReg = 0;
17734 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17735 Reloc::Model RM = MF->getTarget().getRelocationModel();
17736 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
17737 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
17739 // Prepare IP either in reg or imm.
17740 if (!UseImmLabel) {
17741 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
17742 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
17743 LabelReg = MRI.createVirtualRegister(PtrRC);
17744 if (Subtarget->is64Bit()) {
17745 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
17749 .addMBB(restoreMBB)
17752 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
17753 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
17754 .addReg(XII->getGlobalBaseReg(MF))
17757 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
17761 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
17763 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
17764 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17765 if (i == X86::AddrDisp)
17766 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
17768 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
17771 MIB.addReg(LabelReg);
17773 MIB.addMBB(restoreMBB);
17774 MIB.setMemRefs(MMOBegin, MMOEnd);
17776 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
17777 .addMBB(restoreMBB);
17779 const X86RegisterInfo *RegInfo =
17780 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17781 MIB.addRegMask(RegInfo->getNoPreservedMask());
17782 thisMBB->addSuccessor(mainMBB);
17783 thisMBB->addSuccessor(restoreMBB);
17787 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
17788 mainMBB->addSuccessor(sinkMBB);
17791 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17792 TII->get(X86::PHI), DstReg)
17793 .addReg(mainDstReg).addMBB(mainMBB)
17794 .addReg(restoreDstReg).addMBB(restoreMBB);
17797 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
17798 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
17799 restoreMBB->addSuccessor(sinkMBB);
17801 MI->eraseFromParent();
17805 MachineBasicBlock *
17806 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
17807 MachineBasicBlock *MBB) const {
17808 DebugLoc DL = MI->getDebugLoc();
17809 MachineFunction *MF = MBB->getParent();
17810 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17811 MachineRegisterInfo &MRI = MF->getRegInfo();
17813 // Memory Reference
17814 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17815 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17817 MVT PVT = getPointerTy();
17818 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17819 "Invalid Pointer Size!");
17821 const TargetRegisterClass *RC =
17822 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
17823 unsigned Tmp = MRI.createVirtualRegister(RC);
17824 // Since FP is only updated here but NOT referenced, it's treated as GPR.
17825 const X86RegisterInfo *RegInfo =
17826 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17827 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
17828 unsigned SP = RegInfo->getStackRegister();
17830 MachineInstrBuilder MIB;
17832 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17833 const int64_t SPOffset = 2 * PVT.getStoreSize();
17835 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
17836 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
17839 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
17840 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
17841 MIB.addOperand(MI->getOperand(i));
17842 MIB.setMemRefs(MMOBegin, MMOEnd);
17844 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
17845 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17846 if (i == X86::AddrDisp)
17847 MIB.addDisp(MI->getOperand(i), LabelOffset);
17849 MIB.addOperand(MI->getOperand(i));
17851 MIB.setMemRefs(MMOBegin, MMOEnd);
17853 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
17854 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17855 if (i == X86::AddrDisp)
17856 MIB.addDisp(MI->getOperand(i), SPOffset);
17858 MIB.addOperand(MI->getOperand(i));
17860 MIB.setMemRefs(MMOBegin, MMOEnd);
17862 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
17864 MI->eraseFromParent();
17868 // Replace 213-type (isel default) FMA3 instructions with 231-type for
17869 // accumulator loops. Writing back to the accumulator allows the coalescer
17870 // to remove extra copies in the loop.
17871 MachineBasicBlock *
17872 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
17873 MachineBasicBlock *MBB) const {
17874 MachineOperand &AddendOp = MI->getOperand(3);
17876 // Bail out early if the addend isn't a register - we can't switch these.
17877 if (!AddendOp.isReg())
17880 MachineFunction &MF = *MBB->getParent();
17881 MachineRegisterInfo &MRI = MF.getRegInfo();
17883 // Check whether the addend is defined by a PHI:
17884 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
17885 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
17886 if (!AddendDef.isPHI())
17889 // Look for the following pattern:
17891 // %addend = phi [%entry, 0], [%loop, %result]
17893 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
17897 // %addend = phi [%entry, 0], [%loop, %result]
17899 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
17901 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
17902 assert(AddendDef.getOperand(i).isReg());
17903 MachineOperand PHISrcOp = AddendDef.getOperand(i);
17904 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
17905 if (&PHISrcInst == MI) {
17906 // Found a matching instruction.
17907 unsigned NewFMAOpc = 0;
17908 switch (MI->getOpcode()) {
17909 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
17910 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
17911 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
17912 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
17913 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
17914 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
17915 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
17916 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
17917 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
17918 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
17919 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
17920 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
17921 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
17922 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
17923 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
17924 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
17925 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
17926 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
17927 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
17928 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
17929 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
17930 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
17931 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
17932 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
17933 default: llvm_unreachable("Unrecognized FMA variant.");
17936 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
17937 MachineInstrBuilder MIB =
17938 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
17939 .addOperand(MI->getOperand(0))
17940 .addOperand(MI->getOperand(3))
17941 .addOperand(MI->getOperand(2))
17942 .addOperand(MI->getOperand(1));
17943 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
17944 MI->eraseFromParent();
17951 MachineBasicBlock *
17952 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
17953 MachineBasicBlock *BB) const {
17954 switch (MI->getOpcode()) {
17955 default: llvm_unreachable("Unexpected instr type to insert");
17956 case X86::TAILJMPd64:
17957 case X86::TAILJMPr64:
17958 case X86::TAILJMPm64:
17959 llvm_unreachable("TAILJMP64 would not be touched here.");
17960 case X86::TCRETURNdi64:
17961 case X86::TCRETURNri64:
17962 case X86::TCRETURNmi64:
17964 case X86::WIN_ALLOCA:
17965 return EmitLoweredWinAlloca(MI, BB);
17966 case X86::SEG_ALLOCA_32:
17967 return EmitLoweredSegAlloca(MI, BB, false);
17968 case X86::SEG_ALLOCA_64:
17969 return EmitLoweredSegAlloca(MI, BB, true);
17970 case X86::TLSCall_32:
17971 case X86::TLSCall_64:
17972 return EmitLoweredTLSCall(MI, BB);
17973 case X86::CMOV_GR8:
17974 case X86::CMOV_FR32:
17975 case X86::CMOV_FR64:
17976 case X86::CMOV_V4F32:
17977 case X86::CMOV_V2F64:
17978 case X86::CMOV_V2I64:
17979 case X86::CMOV_V8F32:
17980 case X86::CMOV_V4F64:
17981 case X86::CMOV_V4I64:
17982 case X86::CMOV_V16F32:
17983 case X86::CMOV_V8F64:
17984 case X86::CMOV_V8I64:
17985 case X86::CMOV_GR16:
17986 case X86::CMOV_GR32:
17987 case X86::CMOV_RFP32:
17988 case X86::CMOV_RFP64:
17989 case X86::CMOV_RFP80:
17990 return EmitLoweredSelect(MI, BB);
17992 case X86::FP32_TO_INT16_IN_MEM:
17993 case X86::FP32_TO_INT32_IN_MEM:
17994 case X86::FP32_TO_INT64_IN_MEM:
17995 case X86::FP64_TO_INT16_IN_MEM:
17996 case X86::FP64_TO_INT32_IN_MEM:
17997 case X86::FP64_TO_INT64_IN_MEM:
17998 case X86::FP80_TO_INT16_IN_MEM:
17999 case X86::FP80_TO_INT32_IN_MEM:
18000 case X86::FP80_TO_INT64_IN_MEM: {
18001 MachineFunction *F = BB->getParent();
18002 const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
18003 DebugLoc DL = MI->getDebugLoc();
18005 // Change the floating point control register to use "round towards zero"
18006 // mode when truncating to an integer value.
18007 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18008 addFrameReference(BuildMI(*BB, MI, DL,
18009 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18011 // Load the old value of the high byte of the control word...
18013 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18014 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18017 // Set the high part to be round to zero...
18018 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18021 // Reload the modified control word now...
18022 addFrameReference(BuildMI(*BB, MI, DL,
18023 TII->get(X86::FLDCW16m)), CWFrameIdx);
18025 // Restore the memory image of control word to original value
18026 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18029 // Get the X86 opcode to use.
18031 switch (MI->getOpcode()) {
18032 default: llvm_unreachable("illegal opcode!");
18033 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18034 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18035 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18036 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18037 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18038 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18039 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18040 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18041 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18045 MachineOperand &Op = MI->getOperand(0);
18047 AM.BaseType = X86AddressMode::RegBase;
18048 AM.Base.Reg = Op.getReg();
18050 AM.BaseType = X86AddressMode::FrameIndexBase;
18051 AM.Base.FrameIndex = Op.getIndex();
18053 Op = MI->getOperand(1);
18055 AM.Scale = Op.getImm();
18056 Op = MI->getOperand(2);
18058 AM.IndexReg = Op.getImm();
18059 Op = MI->getOperand(3);
18060 if (Op.isGlobal()) {
18061 AM.GV = Op.getGlobal();
18063 AM.Disp = Op.getImm();
18065 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18066 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18068 // Reload the original control word now.
18069 addFrameReference(BuildMI(*BB, MI, DL,
18070 TII->get(X86::FLDCW16m)), CWFrameIdx);
18072 MI->eraseFromParent(); // The pseudo instruction is gone now.
18075 // String/text processing lowering.
18076 case X86::PCMPISTRM128REG:
18077 case X86::VPCMPISTRM128REG:
18078 case X86::PCMPISTRM128MEM:
18079 case X86::VPCMPISTRM128MEM:
18080 case X86::PCMPESTRM128REG:
18081 case X86::VPCMPESTRM128REG:
18082 case X86::PCMPESTRM128MEM:
18083 case X86::VPCMPESTRM128MEM:
18084 assert(Subtarget->hasSSE42() &&
18085 "Target must have SSE4.2 or AVX features enabled");
18086 return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18088 // String/text processing lowering.
18089 case X86::PCMPISTRIREG:
18090 case X86::VPCMPISTRIREG:
18091 case X86::PCMPISTRIMEM:
18092 case X86::VPCMPISTRIMEM:
18093 case X86::PCMPESTRIREG:
18094 case X86::VPCMPESTRIREG:
18095 case X86::PCMPESTRIMEM:
18096 case X86::VPCMPESTRIMEM:
18097 assert(Subtarget->hasSSE42() &&
18098 "Target must have SSE4.2 or AVX features enabled");
18099 return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18101 // Thread synchronization.
18103 return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
18107 return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18109 case X86::VASTART_SAVE_XMM_REGS:
18110 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18112 case X86::VAARG_64:
18113 return EmitVAARG64WithCustomInserter(MI, BB);
18115 case X86::EH_SjLj_SetJmp32:
18116 case X86::EH_SjLj_SetJmp64:
18117 return emitEHSjLjSetJmp(MI, BB);
18119 case X86::EH_SjLj_LongJmp32:
18120 case X86::EH_SjLj_LongJmp64:
18121 return emitEHSjLjLongJmp(MI, BB);
18123 case TargetOpcode::STACKMAP:
18124 case TargetOpcode::PATCHPOINT:
18125 return emitPatchPoint(MI, BB);
18127 case X86::VFMADDPDr213r:
18128 case X86::VFMADDPSr213r:
18129 case X86::VFMADDSDr213r:
18130 case X86::VFMADDSSr213r:
18131 case X86::VFMSUBPDr213r:
18132 case X86::VFMSUBPSr213r:
18133 case X86::VFMSUBSDr213r:
18134 case X86::VFMSUBSSr213r:
18135 case X86::VFNMADDPDr213r:
18136 case X86::VFNMADDPSr213r:
18137 case X86::VFNMADDSDr213r:
18138 case X86::VFNMADDSSr213r:
18139 case X86::VFNMSUBPDr213r:
18140 case X86::VFNMSUBPSr213r:
18141 case X86::VFNMSUBSDr213r:
18142 case X86::VFNMSUBSSr213r:
18143 case X86::VFMADDPDr213rY:
18144 case X86::VFMADDPSr213rY:
18145 case X86::VFMSUBPDr213rY:
18146 case X86::VFMSUBPSr213rY:
18147 case X86::VFNMADDPDr213rY:
18148 case X86::VFNMADDPSr213rY:
18149 case X86::VFNMSUBPDr213rY:
18150 case X86::VFNMSUBPSr213rY:
18151 return emitFMA3Instr(MI, BB);
18155 //===----------------------------------------------------------------------===//
18156 // X86 Optimization Hooks
18157 //===----------------------------------------------------------------------===//
18159 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18162 const SelectionDAG &DAG,
18163 unsigned Depth) const {
18164 unsigned BitWidth = KnownZero.getBitWidth();
18165 unsigned Opc = Op.getOpcode();
18166 assert((Opc >= ISD::BUILTIN_OP_END ||
18167 Opc == ISD::INTRINSIC_WO_CHAIN ||
18168 Opc == ISD::INTRINSIC_W_CHAIN ||
18169 Opc == ISD::INTRINSIC_VOID) &&
18170 "Should use MaskedValueIsZero if you don't know whether Op"
18171 " is a target node!");
18173 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18187 // These nodes' second result is a boolean.
18188 if (Op.getResNo() == 0)
18191 case X86ISD::SETCC:
18192 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18194 case ISD::INTRINSIC_WO_CHAIN: {
18195 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18196 unsigned NumLoBits = 0;
18199 case Intrinsic::x86_sse_movmsk_ps:
18200 case Intrinsic::x86_avx_movmsk_ps_256:
18201 case Intrinsic::x86_sse2_movmsk_pd:
18202 case Intrinsic::x86_avx_movmsk_pd_256:
18203 case Intrinsic::x86_mmx_pmovmskb:
18204 case Intrinsic::x86_sse2_pmovmskb_128:
18205 case Intrinsic::x86_avx2_pmovmskb: {
18206 // High bits of movmskp{s|d}, pmovmskb are known zero.
18208 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18209 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18210 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18211 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18212 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18213 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18214 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18215 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18217 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18226 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18228 const SelectionDAG &,
18229 unsigned Depth) const {
18230 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18231 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18232 return Op.getValueType().getScalarType().getSizeInBits();
18238 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18239 /// node is a GlobalAddress + offset.
18240 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18241 const GlobalValue* &GA,
18242 int64_t &Offset) const {
18243 if (N->getOpcode() == X86ISD::Wrapper) {
18244 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18245 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18246 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18250 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18253 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18254 /// same as extracting the high 128-bit part of 256-bit vector and then
18255 /// inserting the result into the low part of a new 256-bit vector
18256 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18257 EVT VT = SVOp->getValueType(0);
18258 unsigned NumElems = VT.getVectorNumElements();
18260 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18261 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18262 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18263 SVOp->getMaskElt(j) >= 0)
18269 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18270 /// same as extracting the low 128-bit part of 256-bit vector and then
18271 /// inserting the result into the high part of a new 256-bit vector
18272 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18273 EVT VT = SVOp->getValueType(0);
18274 unsigned NumElems = VT.getVectorNumElements();
18276 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18277 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18278 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18279 SVOp->getMaskElt(j) >= 0)
18285 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18286 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18287 TargetLowering::DAGCombinerInfo &DCI,
18288 const X86Subtarget* Subtarget) {
18290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18291 SDValue V1 = SVOp->getOperand(0);
18292 SDValue V2 = SVOp->getOperand(1);
18293 EVT VT = SVOp->getValueType(0);
18294 unsigned NumElems = VT.getVectorNumElements();
18296 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18297 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18301 // V UNDEF BUILD_VECTOR UNDEF
18303 // CONCAT_VECTOR CONCAT_VECTOR
18306 // RESULT: V + zero extended
18308 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18309 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18310 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18313 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18316 // To match the shuffle mask, the first half of the mask should
18317 // be exactly the first vector, and all the rest a splat with the
18318 // first element of the second one.
18319 for (unsigned i = 0; i != NumElems/2; ++i)
18320 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18321 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18324 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18325 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18326 if (Ld->hasNUsesOfValue(1, 0)) {
18327 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18328 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18330 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18332 Ld->getPointerInfo(),
18333 Ld->getAlignment(),
18334 false/*isVolatile*/, true/*ReadMem*/,
18335 false/*WriteMem*/);
18337 // Make sure the newly-created LOAD is in the same position as Ld in
18338 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18339 // and update uses of Ld's output chain to use the TokenFactor.
18340 if (Ld->hasAnyUseOfValue(1)) {
18341 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18342 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18343 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18344 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18345 SDValue(ResNode.getNode(), 1));
18348 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18352 // Emit a zeroed vector and insert the desired subvector on its
18354 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18355 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18356 return DCI.CombineTo(N, InsV);
18359 //===--------------------------------------------------------------------===//
18360 // Combine some shuffles into subvector extracts and inserts:
18363 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18364 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18365 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18366 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18367 return DCI.CombineTo(N, InsV);
18370 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18371 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18372 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18373 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18374 return DCI.CombineTo(N, InsV);
18380 /// \brief Get the PSHUF-style mask from PSHUF node.
18382 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
18383 /// PSHUF-style masks that can be reused with such instructions.
18384 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
18385 SmallVector<int, 4> Mask;
18387 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
18391 switch (N.getOpcode()) {
18392 case X86ISD::PSHUFD:
18394 case X86ISD::PSHUFLW:
18397 case X86ISD::PSHUFHW:
18398 Mask.erase(Mask.begin(), Mask.begin() + 4);
18399 for (int &M : Mask)
18403 llvm_unreachable("No valid shuffle instruction found!");
18407 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
18409 /// We walk up the chain and look for a combinable shuffle, skipping over
18410 /// shuffles that we could hoist this shuffle's transformation past without
18411 /// altering anything.
18412 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
18414 TargetLowering::DAGCombinerInfo &DCI) {
18415 assert(N.getOpcode() == X86ISD::PSHUFD &&
18416 "Called with something other than an x86 128-bit half shuffle!");
18419 // Walk up a single-use chain looking for a combinable shuffle.
18420 SDValue V = N.getOperand(0);
18421 for (; V.hasOneUse(); V = V.getOperand(0)) {
18422 switch (V.getOpcode()) {
18424 return false; // Nothing combined!
18427 // Skip bitcasts as we always know the type for the target specific
18431 case X86ISD::PSHUFD:
18432 // Found another dword shuffle.
18435 case X86ISD::PSHUFLW:
18436 // Check that the low words (being shuffled) are the identity in the
18437 // dword shuffle, and the high words are self-contained.
18438 if (Mask[0] != 0 || Mask[1] != 1 ||
18439 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
18444 case X86ISD::PSHUFHW:
18445 // Check that the high words (being shuffled) are the identity in the
18446 // dword shuffle, and the low words are self-contained.
18447 if (Mask[2] != 2 || Mask[3] != 3 ||
18448 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
18453 // Break out of the loop if we break out of the switch.
18457 if (!V.hasOneUse())
18458 // We fell out of the loop without finding a viable combining instruction.
18461 // Record the old value to use in RAUW-ing.
18464 // Merge this node's mask and our incoming mask.
18465 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18466 for (int &M : Mask)
18468 V = DAG.getNode(X86ISD::PSHUFD, DL, V.getValueType(), V.getOperand(0),
18469 getV4X86ShuffleImm8ForMask(Mask, DAG));
18471 // It is possible that one of the combinable shuffles was completely absorbed
18472 // by the other, just replace it and revisit all users in that case.
18473 if (Old.getNode() == V.getNode()) {
18474 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
18478 // Replace N with its operand as we're going to combine that shuffle away.
18479 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18481 // Replace the combinable shuffle with the combined one, updating all users
18482 // so that we re-evaluate the chain here.
18483 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18487 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
18489 /// We walk up the chain, skipping shuffles of the other half and looking
18490 /// through shuffles which switch halves trying to find a shuffle of the same
18491 /// pair of dwords.
18492 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
18494 TargetLowering::DAGCombinerInfo &DCI) {
18496 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
18497 "Called with something other than an x86 128-bit half shuffle!");
18499 unsigned CombineOpcode = N.getOpcode();
18501 // Walk up a single-use chain looking for a combinable shuffle.
18502 SDValue V = N.getOperand(0);
18503 for (; V.hasOneUse(); V = V.getOperand(0)) {
18504 switch (V.getOpcode()) {
18506 return false; // Nothing combined!
18509 // Skip bitcasts as we always know the type for the target specific
18513 case X86ISD::PSHUFLW:
18514 case X86ISD::PSHUFHW:
18515 if (V.getOpcode() == CombineOpcode)
18518 // Other-half shuffles are no-ops.
18521 case X86ISD::PSHUFD: {
18522 // We can only handle pshufd if the half we are combining either stays in
18523 // its half, or switches to the other half. Bail if one of these isn't
18525 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18526 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
18527 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
18528 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
18531 // Map the mask through the pshufd and keep walking up the chain.
18532 for (int i = 0; i < 4; ++i)
18533 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
18535 // Switch halves if the pshufd does.
18537 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18541 // Break out of the loop if we break out of the switch.
18545 if (!V.hasOneUse())
18546 // We fell out of the loop without finding a viable combining instruction.
18549 // Record the old value to use in RAUW-ing.
18552 // Merge this node's mask and our incoming mask (adjusted to account for all
18553 // the pshufd instructions encountered).
18554 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18555 for (int &M : Mask)
18557 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
18558 getV4X86ShuffleImm8ForMask(Mask, DAG));
18560 // Replace N with its operand as we're going to combine that shuffle away.
18561 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18563 // Replace the combinable shuffle with the combined one, updating all users
18564 // so that we re-evaluate the chain here.
18565 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18569 /// \brief Try to combine x86 target specific shuffles.
18570 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
18571 TargetLowering::DAGCombinerInfo &DCI,
18572 const X86Subtarget *Subtarget) {
18574 MVT VT = N.getSimpleValueType();
18575 SmallVector<int, 4> Mask;
18577 switch (N.getOpcode()) {
18578 case X86ISD::PSHUFD:
18579 case X86ISD::PSHUFLW:
18580 case X86ISD::PSHUFHW:
18581 Mask = getPSHUFShuffleMask(N);
18582 assert(Mask.size() == 4);
18588 // Nuke no-op shuffles that show up after combining.
18589 if (isNoopShuffleMask(Mask))
18590 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
18592 // Look for simplifications involving one or two shuffle instructions.
18593 SDValue V = N.getOperand(0);
18594 switch (N.getOpcode()) {
18597 case X86ISD::PSHUFLW:
18598 case X86ISD::PSHUFHW:
18599 assert(VT == MVT::v8i16);
18602 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
18603 return SDValue(); // We combined away this shuffle, so we're done.
18605 // See if this reduces to a PSHUFD which is no more expensive and can
18606 // combine with more operations.
18607 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
18608 areAdjacentMasksSequential(Mask)) {
18609 int DMask[] = {-1, -1, -1, -1};
18610 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
18611 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
18612 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
18613 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
18614 DCI.AddToWorklist(V.getNode());
18615 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
18616 getV4X86ShuffleImm8ForMask(DMask, DAG));
18617 DCI.AddToWorklist(V.getNode());
18618 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
18623 case X86ISD::PSHUFD:
18624 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
18625 return SDValue(); // We combined away this shuffle.
18633 /// PerformShuffleCombine - Performs several different shuffle combines.
18634 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
18635 TargetLowering::DAGCombinerInfo &DCI,
18636 const X86Subtarget *Subtarget) {
18638 SDValue N0 = N->getOperand(0);
18639 SDValue N1 = N->getOperand(1);
18640 EVT VT = N->getValueType(0);
18642 // Canonicalize shuffles that perform 'addsub' on packed float vectors
18643 // according to the rule:
18644 // (shuffle (FADD A, B), (FSUB A, B), Mask) ->
18645 // (shuffle (FSUB A, -B), (FADD A, -B), Mask)
18647 // Where 'Mask' is:
18648 // <0,5,2,7> -- for v4f32 and v4f64 shuffles;
18649 // <0,3> -- for v2f64 shuffles;
18650 // <0,9,2,11,4,13,6,15> -- for v8f32 shuffles.
18652 // This helps pattern-matching more SSE3/AVX ADDSUB instructions
18653 // during ISel stage.
18654 if (N->getOpcode() == ISD::VECTOR_SHUFFLE &&
18655 ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18656 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18657 N0->getOpcode() == ISD::FADD && N1->getOpcode() == ISD::FSUB &&
18658 // Operands to the FADD and FSUB must be the same.
18659 ((N0->getOperand(0) == N1->getOperand(0) &&
18660 N0->getOperand(1) == N1->getOperand(1)) ||
18661 // FADD is commutable. See if by commuting the operands of the FADD
18662 // we would still be able to match the operands of the FSUB dag node.
18663 (N0->getOperand(1) == N1->getOperand(0) &&
18664 N0->getOperand(0) == N1->getOperand(1))) &&
18665 N0->getOperand(0)->getOpcode() != ISD::UNDEF &&
18666 N0->getOperand(1)->getOpcode() != ISD::UNDEF) {
18668 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
18669 unsigned NumElts = VT.getVectorNumElements();
18670 ArrayRef<int> Mask = SV->getMask();
18671 bool CanFold = true;
18673 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i)
18674 CanFold = Mask[i] == (int)((i & 1) ? i + NumElts : i);
18677 SDValue Op0 = N1->getOperand(0);
18678 SDValue Op1 = DAG.getNode(ISD::FNEG, dl, VT, N1->getOperand(1));
18679 SDValue Sub = DAG.getNode(ISD::FSUB, dl, VT, Op0, Op1);
18680 SDValue Add = DAG.getNode(ISD::FADD, dl, VT, Op0, Op1);
18681 return DAG.getVectorShuffle(VT, dl, Sub, Add, Mask);
18685 // Don't create instructions with illegal types after legalize types has run.
18686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18687 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
18690 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
18691 if (Subtarget->hasFp256() && VT.is256BitVector() &&
18692 N->getOpcode() == ISD::VECTOR_SHUFFLE)
18693 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
18695 // During Type Legalization, when promoting illegal vector types,
18696 // the backend might introduce new shuffle dag nodes and bitcasts.
18698 // This code performs the following transformation:
18699 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
18700 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
18702 // We do this only if both the bitcast and the BINOP dag nodes have
18703 // one use. Also, perform this transformation only if the new binary
18704 // operation is legal. This is to avoid introducing dag nodes that
18705 // potentially need to be further expanded (or custom lowered) into a
18706 // less optimal sequence of dag nodes.
18707 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
18708 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
18709 N0.getOpcode() == ISD::BITCAST) {
18710 SDValue BC0 = N0.getOperand(0);
18711 EVT SVT = BC0.getValueType();
18712 unsigned Opcode = BC0.getOpcode();
18713 unsigned NumElts = VT.getVectorNumElements();
18715 if (BC0.hasOneUse() && SVT.isVector() &&
18716 SVT.getVectorNumElements() * 2 == NumElts &&
18717 TLI.isOperationLegal(Opcode, VT)) {
18718 bool CanFold = false;
18730 unsigned SVTNumElts = SVT.getVectorNumElements();
18731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18732 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
18733 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
18734 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
18735 CanFold = SVOp->getMaskElt(i) < 0;
18738 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
18739 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
18740 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
18741 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
18746 // Only handle 128 wide vector from here on.
18747 if (!VT.is128BitVector())
18750 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
18751 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
18752 // consecutive, non-overlapping, and in the right order.
18753 SmallVector<SDValue, 16> Elts;
18754 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
18755 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
18757 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
18761 if (isTargetShuffle(N->getOpcode())) {
18763 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
18764 if (Shuffle.getNode())
18771 /// PerformTruncateCombine - Converts truncate operation to
18772 /// a sequence of vector shuffle operations.
18773 /// It is possible when we truncate 256-bit vector to 128-bit vector
18774 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
18775 TargetLowering::DAGCombinerInfo &DCI,
18776 const X86Subtarget *Subtarget) {
18780 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
18781 /// specific shuffle of a load can be folded into a single element load.
18782 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
18783 /// shuffles have been customed lowered so we need to handle those here.
18784 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
18785 TargetLowering::DAGCombinerInfo &DCI) {
18786 if (DCI.isBeforeLegalizeOps())
18789 SDValue InVec = N->getOperand(0);
18790 SDValue EltNo = N->getOperand(1);
18792 if (!isa<ConstantSDNode>(EltNo))
18795 EVT VT = InVec.getValueType();
18797 bool HasShuffleIntoBitcast = false;
18798 if (InVec.getOpcode() == ISD::BITCAST) {
18799 // Don't duplicate a load with other uses.
18800 if (!InVec.hasOneUse())
18802 EVT BCVT = InVec.getOperand(0).getValueType();
18803 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
18805 InVec = InVec.getOperand(0);
18806 HasShuffleIntoBitcast = true;
18809 if (!isTargetShuffle(InVec.getOpcode()))
18812 // Don't duplicate a load with other uses.
18813 if (!InVec.hasOneUse())
18816 SmallVector<int, 16> ShuffleMask;
18818 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
18822 // Select the input vector, guarding against out of range extract vector.
18823 unsigned NumElems = VT.getVectorNumElements();
18824 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
18825 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
18826 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
18827 : InVec.getOperand(1);
18829 // If inputs to shuffle are the same for both ops, then allow 2 uses
18830 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
18832 if (LdNode.getOpcode() == ISD::BITCAST) {
18833 // Don't duplicate a load with other uses.
18834 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
18837 AllowedUses = 1; // only allow 1 load use if we have a bitcast
18838 LdNode = LdNode.getOperand(0);
18841 if (!ISD::isNormalLoad(LdNode.getNode()))
18844 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
18846 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
18849 if (HasShuffleIntoBitcast) {
18850 // If there's a bitcast before the shuffle, check if the load type and
18851 // alignment is valid.
18852 unsigned Align = LN0->getAlignment();
18853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18854 unsigned NewAlign = TLI.getDataLayout()->
18855 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
18857 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
18861 // All checks match so transform back to vector_shuffle so that DAG combiner
18862 // can finish the job
18865 // Create shuffle node taking into account the case that its a unary shuffle
18866 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
18867 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
18868 InVec.getOperand(0), Shuffle,
18870 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
18871 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
18875 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
18876 /// generation and convert it from being a bunch of shuffles and extracts
18877 /// to a simple store and scalar loads to extract the elements.
18878 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
18879 TargetLowering::DAGCombinerInfo &DCI) {
18880 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
18881 if (NewOp.getNode())
18884 SDValue InputVector = N->getOperand(0);
18886 // Detect whether we are trying to convert from mmx to i32 and the bitcast
18887 // from mmx to v2i32 has a single usage.
18888 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
18889 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
18890 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
18891 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
18892 N->getValueType(0),
18893 InputVector.getNode()->getOperand(0));
18895 // Only operate on vectors of 4 elements, where the alternative shuffling
18896 // gets to be more expensive.
18897 if (InputVector.getValueType() != MVT::v4i32)
18900 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
18901 // single use which is a sign-extend or zero-extend, and all elements are
18903 SmallVector<SDNode *, 4> Uses;
18904 unsigned ExtractedElements = 0;
18905 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
18906 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
18907 if (UI.getUse().getResNo() != InputVector.getResNo())
18910 SDNode *Extract = *UI;
18911 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
18914 if (Extract->getValueType(0) != MVT::i32)
18916 if (!Extract->hasOneUse())
18918 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
18919 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
18921 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
18924 // Record which element was extracted.
18925 ExtractedElements |=
18926 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
18928 Uses.push_back(Extract);
18931 // If not all the elements were used, this may not be worthwhile.
18932 if (ExtractedElements != 15)
18935 // Ok, we've now decided to do the transformation.
18936 SDLoc dl(InputVector);
18938 // Store the value to a temporary stack slot.
18939 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
18940 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
18941 MachinePointerInfo(), false, false, 0);
18943 // Replace each use (extract) with a load of the appropriate element.
18944 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
18945 UE = Uses.end(); UI != UE; ++UI) {
18946 SDNode *Extract = *UI;
18948 // cOMpute the element's address.
18949 SDValue Idx = Extract->getOperand(1);
18951 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
18952 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
18953 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18954 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
18956 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
18957 StackPtr, OffsetVal);
18959 // Load the scalar.
18960 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
18961 ScalarAddr, MachinePointerInfo(),
18962 false, false, false, 0);
18964 // Replace the exact with the load.
18965 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
18968 // The replacement was made in place; don't return anything.
18972 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
18973 static std::pair<unsigned, bool>
18974 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
18975 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
18976 if (!VT.isVector())
18977 return std::make_pair(0, false);
18979 bool NeedSplit = false;
18980 switch (VT.getSimpleVT().SimpleTy) {
18981 default: return std::make_pair(0, false);
18985 if (!Subtarget->hasAVX2())
18987 if (!Subtarget->hasAVX())
18988 return std::make_pair(0, false);
18993 if (!Subtarget->hasSSE2())
18994 return std::make_pair(0, false);
18997 // SSE2 has only a small subset of the operations.
18998 bool hasUnsigned = Subtarget->hasSSE41() ||
18999 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19000 bool hasSigned = Subtarget->hasSSE41() ||
19001 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19003 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19006 // Check for x CC y ? x : y.
19007 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19008 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19013 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19016 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19019 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19022 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19024 // Check for x CC y ? y : x -- a min/max with reversed arms.
19025 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19026 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19031 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19034 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19037 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19040 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19044 return std::make_pair(Opc, NeedSplit);
19048 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19049 const X86Subtarget *Subtarget) {
19051 SDValue Cond = N->getOperand(0);
19052 SDValue LHS = N->getOperand(1);
19053 SDValue RHS = N->getOperand(2);
19055 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19056 SDValue CondSrc = Cond->getOperand(0);
19057 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19058 Cond = CondSrc->getOperand(0);
19061 MVT VT = N->getSimpleValueType(0);
19062 MVT EltVT = VT.getVectorElementType();
19063 unsigned NumElems = VT.getVectorNumElements();
19064 // There is no blend with immediate in AVX-512.
19065 if (VT.is512BitVector())
19068 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19070 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19073 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19076 unsigned MaskValue = 0;
19077 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19080 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19081 for (unsigned i = 0; i < NumElems; ++i) {
19082 // Be sure we emit undef where we can.
19083 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19084 ShuffleMask[i] = -1;
19086 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19089 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19092 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19094 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19095 TargetLowering::DAGCombinerInfo &DCI,
19096 const X86Subtarget *Subtarget) {
19098 SDValue Cond = N->getOperand(0);
19099 // Get the LHS/RHS of the select.
19100 SDValue LHS = N->getOperand(1);
19101 SDValue RHS = N->getOperand(2);
19102 EVT VT = LHS.getValueType();
19103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19105 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19106 // instructions match the semantics of the common C idiom x<y?x:y but not
19107 // x<=y?x:y, because of how they handle negative zero (which can be
19108 // ignored in unsafe-math mode).
19109 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19110 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
19111 (Subtarget->hasSSE2() ||
19112 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
19113 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19115 unsigned Opcode = 0;
19116 // Check for x CC y ? x : y.
19117 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19118 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19122 // Converting this to a min would handle NaNs incorrectly, and swapping
19123 // the operands would cause it to handle comparisons between positive
19124 // and negative zero incorrectly.
19125 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19126 if (!DAG.getTarget().Options.UnsafeFPMath &&
19127 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19129 std::swap(LHS, RHS);
19131 Opcode = X86ISD::FMIN;
19134 // Converting this to a min would handle comparisons between positive
19135 // and negative zero incorrectly.
19136 if (!DAG.getTarget().Options.UnsafeFPMath &&
19137 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19139 Opcode = X86ISD::FMIN;
19142 // Converting this to a min would handle both negative zeros and NaNs
19143 // incorrectly, but we can swap the operands to fix both.
19144 std::swap(LHS, RHS);
19148 Opcode = X86ISD::FMIN;
19152 // Converting this to a max would handle comparisons between positive
19153 // and negative zero incorrectly.
19154 if (!DAG.getTarget().Options.UnsafeFPMath &&
19155 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19157 Opcode = X86ISD::FMAX;
19160 // Converting this to a max would handle NaNs incorrectly, and swapping
19161 // the operands would cause it to handle comparisons between positive
19162 // and negative zero incorrectly.
19163 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19164 if (!DAG.getTarget().Options.UnsafeFPMath &&
19165 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19167 std::swap(LHS, RHS);
19169 Opcode = X86ISD::FMAX;
19172 // Converting this to a max would handle both negative zeros and NaNs
19173 // incorrectly, but we can swap the operands to fix both.
19174 std::swap(LHS, RHS);
19178 Opcode = X86ISD::FMAX;
19181 // Check for x CC y ? y : x -- a min/max with reversed arms.
19182 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19183 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19187 // Converting this to a min would handle comparisons between positive
19188 // and negative zero incorrectly, and swapping the operands would
19189 // cause it to handle NaNs incorrectly.
19190 if (!DAG.getTarget().Options.UnsafeFPMath &&
19191 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
19192 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19194 std::swap(LHS, RHS);
19196 Opcode = X86ISD::FMIN;
19199 // Converting this to a min would handle NaNs incorrectly.
19200 if (!DAG.getTarget().Options.UnsafeFPMath &&
19201 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
19203 Opcode = X86ISD::FMIN;
19206 // Converting this to a min would handle both negative zeros and NaNs
19207 // incorrectly, but we can swap the operands to fix both.
19208 std::swap(LHS, RHS);
19212 Opcode = X86ISD::FMIN;
19216 // Converting this to a max would handle NaNs incorrectly.
19217 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19219 Opcode = X86ISD::FMAX;
19222 // Converting this to a max would handle comparisons between positive
19223 // and negative zero incorrectly, and swapping the operands would
19224 // cause it to handle NaNs incorrectly.
19225 if (!DAG.getTarget().Options.UnsafeFPMath &&
19226 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
19227 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19229 std::swap(LHS, RHS);
19231 Opcode = X86ISD::FMAX;
19234 // Converting this to a max would handle both negative zeros and NaNs
19235 // incorrectly, but we can swap the operands to fix both.
19236 std::swap(LHS, RHS);
19240 Opcode = X86ISD::FMAX;
19246 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
19249 EVT CondVT = Cond.getValueType();
19250 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
19251 CondVT.getVectorElementType() == MVT::i1) {
19252 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
19253 // lowering on AVX-512. In this case we convert it to
19254 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
19255 // The same situation for all 128 and 256-bit vectors of i8 and i16
19256 EVT OpVT = LHS.getValueType();
19257 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
19258 (OpVT.getVectorElementType() == MVT::i8 ||
19259 OpVT.getVectorElementType() == MVT::i16)) {
19260 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
19261 DCI.AddToWorklist(Cond.getNode());
19262 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
19265 // If this is a select between two integer constants, try to do some
19267 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
19268 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
19269 // Don't do this for crazy integer types.
19270 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
19271 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
19272 // so that TrueC (the true value) is larger than FalseC.
19273 bool NeedsCondInvert = false;
19275 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
19276 // Efficiently invertible.
19277 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
19278 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
19279 isa<ConstantSDNode>(Cond.getOperand(1))))) {
19280 NeedsCondInvert = true;
19281 std::swap(TrueC, FalseC);
19284 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
19285 if (FalseC->getAPIntValue() == 0 &&
19286 TrueC->getAPIntValue().isPowerOf2()) {
19287 if (NeedsCondInvert) // Invert the condition if needed.
19288 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19289 DAG.getConstant(1, Cond.getValueType()));
19291 // Zero extend the condition if needed.
19292 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
19294 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19295 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
19296 DAG.getConstant(ShAmt, MVT::i8));
19299 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
19300 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19301 if (NeedsCondInvert) // Invert the condition if needed.
19302 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19303 DAG.getConstant(1, Cond.getValueType()));
19305 // Zero extend the condition if needed.
19306 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19307 FalseC->getValueType(0), Cond);
19308 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19309 SDValue(FalseC, 0));
19312 // Optimize cases that will turn into an LEA instruction. This requires
19313 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19314 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19315 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19316 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19318 bool isFastMultiplier = false;
19320 switch ((unsigned char)Diff) {
19322 case 1: // result = add base, cond
19323 case 2: // result = lea base( , cond*2)
19324 case 3: // result = lea base(cond, cond*2)
19325 case 4: // result = lea base( , cond*4)
19326 case 5: // result = lea base(cond, cond*4)
19327 case 8: // result = lea base( , cond*8)
19328 case 9: // result = lea base(cond, cond*8)
19329 isFastMultiplier = true;
19334 if (isFastMultiplier) {
19335 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19336 if (NeedsCondInvert) // Invert the condition if needed.
19337 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19338 DAG.getConstant(1, Cond.getValueType()));
19340 // Zero extend the condition if needed.
19341 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19343 // Scale the condition by the difference.
19345 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19346 DAG.getConstant(Diff, Cond.getValueType()));
19348 // Add the base if non-zero.
19349 if (FalseC->getAPIntValue() != 0)
19350 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19351 SDValue(FalseC, 0));
19358 // Canonicalize max and min:
19359 // (x > y) ? x : y -> (x >= y) ? x : y
19360 // (x < y) ? x : y -> (x <= y) ? x : y
19361 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
19362 // the need for an extra compare
19363 // against zero. e.g.
19364 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
19366 // testl %edi, %edi
19368 // cmovgl %edi, %eax
19372 // cmovsl %eax, %edi
19373 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
19374 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19375 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19376 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19381 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
19382 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
19383 Cond.getOperand(0), Cond.getOperand(1), NewCC);
19384 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
19389 // Early exit check
19390 if (!TLI.isTypeLegal(VT))
19393 // Match VSELECTs into subs with unsigned saturation.
19394 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19395 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
19396 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
19397 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
19398 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19400 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
19401 // left side invert the predicate to simplify logic below.
19403 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
19405 CC = ISD::getSetCCInverse(CC, true);
19406 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
19410 if (Other.getNode() && Other->getNumOperands() == 2 &&
19411 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
19412 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
19413 SDValue CondRHS = Cond->getOperand(1);
19415 // Look for a general sub with unsigned saturation first.
19416 // x >= y ? x-y : 0 --> subus x, y
19417 // x > y ? x-y : 0 --> subus x, y
19418 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
19419 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
19420 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
19422 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
19423 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
19424 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
19425 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
19426 // If the RHS is a constant we have to reverse the const
19427 // canonicalization.
19428 // x > C-1 ? x+-C : 0 --> subus x, C
19429 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
19430 CondRHSConst->getAPIntValue() ==
19431 (-OpRHSConst->getAPIntValue() - 1))
19432 return DAG.getNode(
19433 X86ISD::SUBUS, DL, VT, OpLHS,
19434 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
19436 // Another special case: If C was a sign bit, the sub has been
19437 // canonicalized into a xor.
19438 // FIXME: Would it be better to use computeKnownBits to determine
19439 // whether it's safe to decanonicalize the xor?
19440 // x s< 0 ? x^C : 0 --> subus x, C
19441 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
19442 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
19443 OpRHSConst->getAPIntValue().isSignBit())
19444 // Note that we have to rebuild the RHS constant here to ensure we
19445 // don't rely on particular values of undef lanes.
19446 return DAG.getNode(
19447 X86ISD::SUBUS, DL, VT, OpLHS,
19448 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
19453 // Try to match a min/max vector operation.
19454 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
19455 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
19456 unsigned Opc = ret.first;
19457 bool NeedSplit = ret.second;
19459 if (Opc && NeedSplit) {
19460 unsigned NumElems = VT.getVectorNumElements();
19461 // Extract the LHS vectors
19462 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
19463 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
19465 // Extract the RHS vectors
19466 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
19467 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
19469 // Create min/max for each subvector
19470 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
19471 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
19473 // Merge the result
19474 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
19476 return DAG.getNode(Opc, DL, VT, LHS, RHS);
19479 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
19480 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19481 // Check if SETCC has already been promoted
19482 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
19483 // Check that condition value type matches vselect operand type
19486 assert(Cond.getValueType().isVector() &&
19487 "vector select expects a vector selector!");
19489 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
19490 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
19492 if (!TValIsAllOnes && !FValIsAllZeros) {
19493 // Try invert the condition if true value is not all 1s and false value
19495 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
19496 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
19498 if (TValIsAllZeros || FValIsAllOnes) {
19499 SDValue CC = Cond.getOperand(2);
19500 ISD::CondCode NewCC =
19501 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
19502 Cond.getOperand(0).getValueType().isInteger());
19503 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
19504 std::swap(LHS, RHS);
19505 TValIsAllOnes = FValIsAllOnes;
19506 FValIsAllZeros = TValIsAllZeros;
19510 if (TValIsAllOnes || FValIsAllZeros) {
19513 if (TValIsAllOnes && FValIsAllZeros)
19515 else if (TValIsAllOnes)
19516 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
19517 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
19518 else if (FValIsAllZeros)
19519 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
19520 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
19522 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
19526 // Try to fold this VSELECT into a MOVSS/MOVSD
19527 if (N->getOpcode() == ISD::VSELECT &&
19528 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
19529 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
19530 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
19531 bool CanFold = false;
19532 unsigned NumElems = Cond.getNumOperands();
19536 if (isZero(Cond.getOperand(0))) {
19539 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
19540 // fold (vselect <0,-1> -> (movsd A, B)
19541 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19542 CanFold = isAllOnes(Cond.getOperand(i));
19543 } else if (isAllOnes(Cond.getOperand(0))) {
19547 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
19548 // fold (vselect <-1,0> -> (movsd B, A)
19549 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19550 CanFold = isZero(Cond.getOperand(i));
19554 if (VT == MVT::v4i32 || VT == MVT::v4f32)
19555 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
19556 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
19559 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
19560 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
19561 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19562 // (v2i64 (bitcast B)))))
19564 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
19565 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
19566 // (v2f64 (bitcast B)))))
19568 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
19569 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19570 // (v2i64 (bitcast A)))))
19572 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
19573 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
19574 // (v2f64 (bitcast A)))))
19576 CanFold = (isZero(Cond.getOperand(0)) &&
19577 isZero(Cond.getOperand(1)) &&
19578 isAllOnes(Cond.getOperand(2)) &&
19579 isAllOnes(Cond.getOperand(3)));
19581 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
19582 isAllOnes(Cond.getOperand(1)) &&
19583 isZero(Cond.getOperand(2)) &&
19584 isZero(Cond.getOperand(3))) {
19586 std::swap(LHS, RHS);
19590 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
19591 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
19592 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
19593 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
19595 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
19601 // If we know that this node is legal then we know that it is going to be
19602 // matched by one of the SSE/AVX BLEND instructions. These instructions only
19603 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
19604 // to simplify previous instructions.
19605 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
19606 !DCI.isBeforeLegalize() &&
19607 // We explicitly check against v8i16 and v16i16 because, although
19608 // they're marked as Custom, they might only be legal when Cond is a
19609 // build_vector of constants. This will be taken care in a later
19611 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
19612 VT != MVT::v8i16)) {
19613 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
19615 // Don't optimize vector selects that map to mask-registers.
19619 // Check all uses of that condition operand to check whether it will be
19620 // consumed by non-BLEND instructions, which may depend on all bits are set
19622 for (SDNode::use_iterator I = Cond->use_begin(),
19623 E = Cond->use_end(); I != E; ++I)
19624 if (I->getOpcode() != ISD::VSELECT)
19625 // TODO: Add other opcodes eventually lowered into BLEND.
19628 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
19629 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
19631 APInt KnownZero, KnownOne;
19632 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
19633 DCI.isBeforeLegalizeOps());
19634 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
19635 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
19636 DCI.CommitTargetLoweringOpt(TLO);
19639 // We should generate an X86ISD::BLENDI from a vselect if its argument
19640 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19641 // constants. This specific pattern gets generated when we split a
19642 // selector for a 512 bit vector in a machine without AVX512 (but with
19643 // 256-bit vectors), during legalization:
19645 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
19647 // Iff we find this pattern and the build_vectors are built from
19648 // constants, we translate the vselect into a shuffle_vector that we
19649 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
19650 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
19651 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
19652 if (Shuffle.getNode())
19659 // Check whether a boolean test is testing a boolean value generated by
19660 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
19663 // Simplify the following patterns:
19664 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19665 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
19666 // to (Op EFLAGS Cond)
19668 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
19669 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
19670 // to (Op EFLAGS !Cond)
19672 // where Op could be BRCOND or CMOV.
19674 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
19675 // Quit if not CMP and SUB with its value result used.
19676 if (Cmp.getOpcode() != X86ISD::CMP &&
19677 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
19680 // Quit if not used as a boolean value.
19681 if (CC != X86::COND_E && CC != X86::COND_NE)
19684 // Check CMP operands. One of them should be 0 or 1 and the other should be
19685 // an SetCC or extended from it.
19686 SDValue Op1 = Cmp.getOperand(0);
19687 SDValue Op2 = Cmp.getOperand(1);
19690 const ConstantSDNode* C = nullptr;
19691 bool needOppositeCond = (CC == X86::COND_E);
19692 bool checkAgainstTrue = false; // Is it a comparison against 1?
19694 if ((C = dyn_cast<ConstantSDNode>(Op1)))
19696 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
19698 else // Quit if all operands are not constants.
19701 if (C->getZExtValue() == 1) {
19702 needOppositeCond = !needOppositeCond;
19703 checkAgainstTrue = true;
19704 } else if (C->getZExtValue() != 0)
19705 // Quit if the constant is neither 0 or 1.
19708 bool truncatedToBoolWithAnd = false;
19709 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
19710 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
19711 SetCC.getOpcode() == ISD::TRUNCATE ||
19712 SetCC.getOpcode() == ISD::AND) {
19713 if (SetCC.getOpcode() == ISD::AND) {
19715 ConstantSDNode *CS;
19716 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
19717 CS->getZExtValue() == 1)
19719 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
19720 CS->getZExtValue() == 1)
19724 SetCC = SetCC.getOperand(OpIdx);
19725 truncatedToBoolWithAnd = true;
19727 SetCC = SetCC.getOperand(0);
19730 switch (SetCC.getOpcode()) {
19731 case X86ISD::SETCC_CARRY:
19732 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
19733 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
19734 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
19735 // truncated to i1 using 'and'.
19736 if (checkAgainstTrue && !truncatedToBoolWithAnd)
19738 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
19739 "Invalid use of SETCC_CARRY!");
19741 case X86ISD::SETCC:
19742 // Set the condition code or opposite one if necessary.
19743 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
19744 if (needOppositeCond)
19745 CC = X86::GetOppositeBranchCondition(CC);
19746 return SetCC.getOperand(1);
19747 case X86ISD::CMOV: {
19748 // Check whether false/true value has canonical one, i.e. 0 or 1.
19749 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
19750 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
19751 // Quit if true value is not a constant.
19754 // Quit if false value is not a constant.
19756 SDValue Op = SetCC.getOperand(0);
19757 // Skip 'zext' or 'trunc' node.
19758 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
19759 Op.getOpcode() == ISD::TRUNCATE)
19760 Op = Op.getOperand(0);
19761 // A special case for rdrand/rdseed, where 0 is set if false cond is
19763 if ((Op.getOpcode() != X86ISD::RDRAND &&
19764 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
19767 // Quit if false value is not the constant 0 or 1.
19768 bool FValIsFalse = true;
19769 if (FVal && FVal->getZExtValue() != 0) {
19770 if (FVal->getZExtValue() != 1)
19772 // If FVal is 1, opposite cond is needed.
19773 needOppositeCond = !needOppositeCond;
19774 FValIsFalse = false;
19776 // Quit if TVal is not the constant opposite of FVal.
19777 if (FValIsFalse && TVal->getZExtValue() != 1)
19779 if (!FValIsFalse && TVal->getZExtValue() != 0)
19781 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
19782 if (needOppositeCond)
19783 CC = X86::GetOppositeBranchCondition(CC);
19784 return SetCC.getOperand(3);
19791 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
19792 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
19793 TargetLowering::DAGCombinerInfo &DCI,
19794 const X86Subtarget *Subtarget) {
19797 // If the flag operand isn't dead, don't touch this CMOV.
19798 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
19801 SDValue FalseOp = N->getOperand(0);
19802 SDValue TrueOp = N->getOperand(1);
19803 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
19804 SDValue Cond = N->getOperand(3);
19806 if (CC == X86::COND_E || CC == X86::COND_NE) {
19807 switch (Cond.getOpcode()) {
19811 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
19812 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
19813 return (CC == X86::COND_E) ? FalseOp : TrueOp;
19819 Flags = checkBoolTestSetCCCombine(Cond, CC);
19820 if (Flags.getNode() &&
19821 // Extra check as FCMOV only supports a subset of X86 cond.
19822 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
19823 SDValue Ops[] = { FalseOp, TrueOp,
19824 DAG.getConstant(CC, MVT::i8), Flags };
19825 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
19828 // If this is a select between two integer constants, try to do some
19829 // optimizations. Note that the operands are ordered the opposite of SELECT
19831 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
19832 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
19833 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
19834 // larger than FalseC (the false value).
19835 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
19836 CC = X86::GetOppositeBranchCondition(CC);
19837 std::swap(TrueC, FalseC);
19838 std::swap(TrueOp, FalseOp);
19841 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
19842 // This is efficient for any integer data type (including i8/i16) and
19844 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
19845 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19846 DAG.getConstant(CC, MVT::i8), Cond);
19848 // Zero extend the condition if needed.
19849 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
19851 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19852 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
19853 DAG.getConstant(ShAmt, MVT::i8));
19854 if (N->getNumValues() == 2) // Dead flag value?
19855 return DCI.CombineTo(N, Cond, SDValue());
19859 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
19860 // for any integer data type, including i8/i16.
19861 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19862 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19863 DAG.getConstant(CC, MVT::i8), Cond);
19865 // Zero extend the condition if needed.
19866 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19867 FalseC->getValueType(0), Cond);
19868 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19869 SDValue(FalseC, 0));
19871 if (N->getNumValues() == 2) // Dead flag value?
19872 return DCI.CombineTo(N, Cond, SDValue());
19876 // Optimize cases that will turn into an LEA instruction. This requires
19877 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19878 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19879 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19880 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19882 bool isFastMultiplier = false;
19884 switch ((unsigned char)Diff) {
19886 case 1: // result = add base, cond
19887 case 2: // result = lea base( , cond*2)
19888 case 3: // result = lea base(cond, cond*2)
19889 case 4: // result = lea base( , cond*4)
19890 case 5: // result = lea base(cond, cond*4)
19891 case 8: // result = lea base( , cond*8)
19892 case 9: // result = lea base(cond, cond*8)
19893 isFastMultiplier = true;
19898 if (isFastMultiplier) {
19899 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19900 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19901 DAG.getConstant(CC, MVT::i8), Cond);
19902 // Zero extend the condition if needed.
19903 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19905 // Scale the condition by the difference.
19907 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19908 DAG.getConstant(Diff, Cond.getValueType()));
19910 // Add the base if non-zero.
19911 if (FalseC->getAPIntValue() != 0)
19912 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19913 SDValue(FalseC, 0));
19914 if (N->getNumValues() == 2) // Dead flag value?
19915 return DCI.CombineTo(N, Cond, SDValue());
19922 // Handle these cases:
19923 // (select (x != c), e, c) -> select (x != c), e, x),
19924 // (select (x == c), c, e) -> select (x == c), x, e)
19925 // where the c is an integer constant, and the "select" is the combination
19926 // of CMOV and CMP.
19928 // The rationale for this change is that the conditional-move from a constant
19929 // needs two instructions, however, conditional-move from a register needs
19930 // only one instruction.
19932 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
19933 // some instruction-combining opportunities. This opt needs to be
19934 // postponed as late as possible.
19936 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
19937 // the DCI.xxxx conditions are provided to postpone the optimization as
19938 // late as possible.
19940 ConstantSDNode *CmpAgainst = nullptr;
19941 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
19942 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
19943 !isa<ConstantSDNode>(Cond.getOperand(0))) {
19945 if (CC == X86::COND_NE &&
19946 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
19947 CC = X86::GetOppositeBranchCondition(CC);
19948 std::swap(TrueOp, FalseOp);
19951 if (CC == X86::COND_E &&
19952 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
19953 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
19954 DAG.getConstant(CC, MVT::i8), Cond };
19955 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
19963 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
19964 const X86Subtarget *Subtarget) {
19965 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
19967 default: return SDValue();
19968 // SSE/AVX/AVX2 blend intrinsics.
19969 case Intrinsic::x86_avx2_pblendvb:
19970 case Intrinsic::x86_avx2_pblendw:
19971 case Intrinsic::x86_avx2_pblendd_128:
19972 case Intrinsic::x86_avx2_pblendd_256:
19973 // Don't try to simplify this intrinsic if we don't have AVX2.
19974 if (!Subtarget->hasAVX2())
19977 case Intrinsic::x86_avx_blend_pd_256:
19978 case Intrinsic::x86_avx_blend_ps_256:
19979 case Intrinsic::x86_avx_blendv_pd_256:
19980 case Intrinsic::x86_avx_blendv_ps_256:
19981 // Don't try to simplify this intrinsic if we don't have AVX.
19982 if (!Subtarget->hasAVX())
19985 case Intrinsic::x86_sse41_pblendw:
19986 case Intrinsic::x86_sse41_blendpd:
19987 case Intrinsic::x86_sse41_blendps:
19988 case Intrinsic::x86_sse41_blendvps:
19989 case Intrinsic::x86_sse41_blendvpd:
19990 case Intrinsic::x86_sse41_pblendvb: {
19991 SDValue Op0 = N->getOperand(1);
19992 SDValue Op1 = N->getOperand(2);
19993 SDValue Mask = N->getOperand(3);
19995 // Don't try to simplify this intrinsic if we don't have SSE4.1.
19996 if (!Subtarget->hasSSE41())
19999 // fold (blend A, A, Mask) -> A
20002 // fold (blend A, B, allZeros) -> A
20003 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20005 // fold (blend A, B, allOnes) -> B
20006 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20009 // Simplify the case where the mask is a constant i32 value.
20010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20011 if (C->isNullValue())
20013 if (C->isAllOnesValue())
20020 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20021 case Intrinsic::x86_sse2_psrai_w:
20022 case Intrinsic::x86_sse2_psrai_d:
20023 case Intrinsic::x86_avx2_psrai_w:
20024 case Intrinsic::x86_avx2_psrai_d:
20025 case Intrinsic::x86_sse2_psra_w:
20026 case Intrinsic::x86_sse2_psra_d:
20027 case Intrinsic::x86_avx2_psra_w:
20028 case Intrinsic::x86_avx2_psra_d: {
20029 SDValue Op0 = N->getOperand(1);
20030 SDValue Op1 = N->getOperand(2);
20031 EVT VT = Op0.getValueType();
20032 assert(VT.isVector() && "Expected a vector type!");
20034 if (isa<BuildVectorSDNode>(Op1))
20035 Op1 = Op1.getOperand(0);
20037 if (!isa<ConstantSDNode>(Op1))
20040 EVT SVT = VT.getVectorElementType();
20041 unsigned SVTBits = SVT.getSizeInBits();
20043 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20044 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20045 uint64_t ShAmt = C.getZExtValue();
20047 // Don't try to convert this shift into a ISD::SRA if the shift
20048 // count is bigger than or equal to the element size.
20049 if (ShAmt >= SVTBits)
20052 // Trivial case: if the shift count is zero, then fold this
20053 // into the first operand.
20057 // Replace this packed shift intrinsic with a target independent
20059 SDValue Splat = DAG.getConstant(C, VT);
20060 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20065 /// PerformMulCombine - Optimize a single multiply with constant into two
20066 /// in order to implement it with two cheaper instructions, e.g.
20067 /// LEA + SHL, LEA + LEA.
20068 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20069 TargetLowering::DAGCombinerInfo &DCI) {
20070 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20073 EVT VT = N->getValueType(0);
20074 if (VT != MVT::i64)
20077 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20080 uint64_t MulAmt = C->getZExtValue();
20081 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20084 uint64_t MulAmt1 = 0;
20085 uint64_t MulAmt2 = 0;
20086 if ((MulAmt % 9) == 0) {
20088 MulAmt2 = MulAmt / 9;
20089 } else if ((MulAmt % 5) == 0) {
20091 MulAmt2 = MulAmt / 5;
20092 } else if ((MulAmt % 3) == 0) {
20094 MulAmt2 = MulAmt / 3;
20097 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20100 if (isPowerOf2_64(MulAmt2) &&
20101 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20102 // If second multiplifer is pow2, issue it first. We want the multiply by
20103 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20105 std::swap(MulAmt1, MulAmt2);
20108 if (isPowerOf2_64(MulAmt1))
20109 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20110 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
20112 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
20113 DAG.getConstant(MulAmt1, VT));
20115 if (isPowerOf2_64(MulAmt2))
20116 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
20117 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
20119 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
20120 DAG.getConstant(MulAmt2, VT));
20122 // Do not add new nodes to DAG combiner worklist.
20123 DCI.CombineTo(N, NewMul, false);
20128 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
20129 SDValue N0 = N->getOperand(0);
20130 SDValue N1 = N->getOperand(1);
20131 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
20132 EVT VT = N0.getValueType();
20134 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
20135 // since the result of setcc_c is all zero's or all ones.
20136 if (VT.isInteger() && !VT.isVector() &&
20137 N1C && N0.getOpcode() == ISD::AND &&
20138 N0.getOperand(1).getOpcode() == ISD::Constant) {
20139 SDValue N00 = N0.getOperand(0);
20140 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
20141 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20142 N00.getOpcode() == ISD::ZERO_EXTEND) &&
20143 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
20144 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
20145 APInt ShAmt = N1C->getAPIntValue();
20146 Mask = Mask.shl(ShAmt);
20148 return DAG.getNode(ISD::AND, SDLoc(N), VT,
20149 N00, DAG.getConstant(Mask, VT));
20153 // Hardware support for vector shifts is sparse which makes us scalarize the
20154 // vector operations in many cases. Also, on sandybridge ADD is faster than
20156 // (shl V, 1) -> add V,V
20157 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
20158 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
20159 assert(N0.getValueType().isVector() && "Invalid vector shift type");
20160 // We shift all of the values by one. In many cases we do not have
20161 // hardware support for this operation. This is better expressed as an ADD
20163 if (N1SplatC->getZExtValue() == 1)
20164 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
20170 /// \brief Returns a vector of 0s if the node in input is a vector logical
20171 /// shift by a constant amount which is known to be bigger than or equal
20172 /// to the vector element size in bits.
20173 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
20174 const X86Subtarget *Subtarget) {
20175 EVT VT = N->getValueType(0);
20177 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
20178 (!Subtarget->hasInt256() ||
20179 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
20182 SDValue Amt = N->getOperand(1);
20184 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
20185 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
20186 APInt ShiftAmt = AmtSplat->getAPIntValue();
20187 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
20189 // SSE2/AVX2 logical shifts always return a vector of 0s
20190 // if the shift amount is bigger than or equal to
20191 // the element size. The constant shift amount will be
20192 // encoded as a 8-bit immediate.
20193 if (ShiftAmt.trunc(8).uge(MaxAmount))
20194 return getZeroVector(VT, Subtarget, DAG, DL);
20200 /// PerformShiftCombine - Combine shifts.
20201 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
20202 TargetLowering::DAGCombinerInfo &DCI,
20203 const X86Subtarget *Subtarget) {
20204 if (N->getOpcode() == ISD::SHL) {
20205 SDValue V = PerformSHLCombine(N, DAG);
20206 if (V.getNode()) return V;
20209 if (N->getOpcode() != ISD::SRA) {
20210 // Try to fold this logical shift into a zero vector.
20211 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
20212 if (V.getNode()) return V;
20218 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
20219 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
20220 // and friends. Likewise for OR -> CMPNEQSS.
20221 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
20222 TargetLowering::DAGCombinerInfo &DCI,
20223 const X86Subtarget *Subtarget) {
20226 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
20227 // we're requiring SSE2 for both.
20228 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
20229 SDValue N0 = N->getOperand(0);
20230 SDValue N1 = N->getOperand(1);
20231 SDValue CMP0 = N0->getOperand(1);
20232 SDValue CMP1 = N1->getOperand(1);
20235 // The SETCCs should both refer to the same CMP.
20236 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
20239 SDValue CMP00 = CMP0->getOperand(0);
20240 SDValue CMP01 = CMP0->getOperand(1);
20241 EVT VT = CMP00.getValueType();
20243 if (VT == MVT::f32 || VT == MVT::f64) {
20244 bool ExpectingFlags = false;
20245 // Check for any users that want flags:
20246 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
20247 !ExpectingFlags && UI != UE; ++UI)
20248 switch (UI->getOpcode()) {
20253 ExpectingFlags = true;
20255 case ISD::CopyToReg:
20256 case ISD::SIGN_EXTEND:
20257 case ISD::ZERO_EXTEND:
20258 case ISD::ANY_EXTEND:
20262 if (!ExpectingFlags) {
20263 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
20264 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
20266 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
20267 X86::CondCode tmp = cc0;
20272 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
20273 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
20274 // FIXME: need symbolic constants for these magic numbers.
20275 // See X86ATTInstPrinter.cpp:printSSECC().
20276 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
20277 if (Subtarget->hasAVX512()) {
20278 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
20279 CMP01, DAG.getConstant(x86cc, MVT::i8));
20280 if (N->getValueType(0) != MVT::i1)
20281 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
20285 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
20286 CMP00.getValueType(), CMP00, CMP01,
20287 DAG.getConstant(x86cc, MVT::i8));
20289 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
20290 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
20292 if (is64BitFP && !Subtarget->is64Bit()) {
20293 // On a 32-bit target, we cannot bitcast the 64-bit float to a
20294 // 64-bit integer, since that's not a legal type. Since
20295 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
20296 // bits, but can do this little dance to extract the lowest 32 bits
20297 // and work with those going forward.
20298 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
20300 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
20302 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
20303 Vector32, DAG.getIntPtrConstant(0));
20307 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
20308 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
20309 DAG.getConstant(1, IntVT));
20310 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
20311 return OneBitOfTruth;
20319 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
20320 /// so it can be folded inside ANDNP.
20321 static bool CanFoldXORWithAllOnes(const SDNode *N) {
20322 EVT VT = N->getValueType(0);
20324 // Match direct AllOnes for 128 and 256-bit vectors
20325 if (ISD::isBuildVectorAllOnes(N))
20328 // Look through a bit convert.
20329 if (N->getOpcode() == ISD::BITCAST)
20330 N = N->getOperand(0).getNode();
20332 // Sometimes the operand may come from a insert_subvector building a 256-bit
20334 if (VT.is256BitVector() &&
20335 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
20336 SDValue V1 = N->getOperand(0);
20337 SDValue V2 = N->getOperand(1);
20339 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
20340 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
20341 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
20342 ISD::isBuildVectorAllOnes(V2.getNode()))
20349 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
20350 // register. In most cases we actually compare or select YMM-sized registers
20351 // and mixing the two types creates horrible code. This method optimizes
20352 // some of the transition sequences.
20353 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
20354 TargetLowering::DAGCombinerInfo &DCI,
20355 const X86Subtarget *Subtarget) {
20356 EVT VT = N->getValueType(0);
20357 if (!VT.is256BitVector())
20360 assert((N->getOpcode() == ISD::ANY_EXTEND ||
20361 N->getOpcode() == ISD::ZERO_EXTEND ||
20362 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
20364 SDValue Narrow = N->getOperand(0);
20365 EVT NarrowVT = Narrow->getValueType(0);
20366 if (!NarrowVT.is128BitVector())
20369 if (Narrow->getOpcode() != ISD::XOR &&
20370 Narrow->getOpcode() != ISD::AND &&
20371 Narrow->getOpcode() != ISD::OR)
20374 SDValue N0 = Narrow->getOperand(0);
20375 SDValue N1 = Narrow->getOperand(1);
20378 // The Left side has to be a trunc.
20379 if (N0.getOpcode() != ISD::TRUNCATE)
20382 // The type of the truncated inputs.
20383 EVT WideVT = N0->getOperand(0)->getValueType(0);
20387 // The right side has to be a 'trunc' or a constant vector.
20388 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
20389 ConstantSDNode *RHSConstSplat = nullptr;
20390 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
20391 RHSConstSplat = RHSBV->getConstantSplatNode();
20392 if (!RHSTrunc && !RHSConstSplat)
20395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20397 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
20400 // Set N0 and N1 to hold the inputs to the new wide operation.
20401 N0 = N0->getOperand(0);
20402 if (RHSConstSplat) {
20403 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
20404 SDValue(RHSConstSplat, 0));
20405 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
20406 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
20407 } else if (RHSTrunc) {
20408 N1 = N1->getOperand(0);
20411 // Generate the wide operation.
20412 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
20413 unsigned Opcode = N->getOpcode();
20415 case ISD::ANY_EXTEND:
20417 case ISD::ZERO_EXTEND: {
20418 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
20419 APInt Mask = APInt::getAllOnesValue(InBits);
20420 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
20421 return DAG.getNode(ISD::AND, DL, VT,
20422 Op, DAG.getConstant(Mask, VT));
20424 case ISD::SIGN_EXTEND:
20425 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
20426 Op, DAG.getValueType(NarrowVT));
20428 llvm_unreachable("Unexpected opcode");
20432 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
20433 TargetLowering::DAGCombinerInfo &DCI,
20434 const X86Subtarget *Subtarget) {
20435 EVT VT = N->getValueType(0);
20436 if (DCI.isBeforeLegalizeOps())
20439 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20443 // Create BEXTR instructions
20444 // BEXTR is ((X >> imm) & (2**size-1))
20445 if (VT == MVT::i32 || VT == MVT::i64) {
20446 SDValue N0 = N->getOperand(0);
20447 SDValue N1 = N->getOperand(1);
20450 // Check for BEXTR.
20451 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
20452 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
20453 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
20454 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20455 if (MaskNode && ShiftNode) {
20456 uint64_t Mask = MaskNode->getZExtValue();
20457 uint64_t Shift = ShiftNode->getZExtValue();
20458 if (isMask_64(Mask)) {
20459 uint64_t MaskSize = CountPopulation_64(Mask);
20460 if (Shift + MaskSize <= VT.getSizeInBits())
20461 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
20462 DAG.getConstant(Shift | (MaskSize << 8), VT));
20470 // Want to form ANDNP nodes:
20471 // 1) In the hopes of then easily combining them with OR and AND nodes
20472 // to form PBLEND/PSIGN.
20473 // 2) To match ANDN packed intrinsics
20474 if (VT != MVT::v2i64 && VT != MVT::v4i64)
20477 SDValue N0 = N->getOperand(0);
20478 SDValue N1 = N->getOperand(1);
20481 // Check LHS for vnot
20482 if (N0.getOpcode() == ISD::XOR &&
20483 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
20484 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
20485 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
20487 // Check RHS for vnot
20488 if (N1.getOpcode() == ISD::XOR &&
20489 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
20490 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
20491 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
20496 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
20497 TargetLowering::DAGCombinerInfo &DCI,
20498 const X86Subtarget *Subtarget) {
20499 if (DCI.isBeforeLegalizeOps())
20502 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20506 SDValue N0 = N->getOperand(0);
20507 SDValue N1 = N->getOperand(1);
20508 EVT VT = N->getValueType(0);
20510 // look for psign/blend
20511 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
20512 if (!Subtarget->hasSSSE3() ||
20513 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
20516 // Canonicalize pandn to RHS
20517 if (N0.getOpcode() == X86ISD::ANDNP)
20519 // or (and (m, y), (pandn m, x))
20520 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
20521 SDValue Mask = N1.getOperand(0);
20522 SDValue X = N1.getOperand(1);
20524 if (N0.getOperand(0) == Mask)
20525 Y = N0.getOperand(1);
20526 if (N0.getOperand(1) == Mask)
20527 Y = N0.getOperand(0);
20529 // Check to see if the mask appeared in both the AND and ANDNP and
20533 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
20534 // Look through mask bitcast.
20535 if (Mask.getOpcode() == ISD::BITCAST)
20536 Mask = Mask.getOperand(0);
20537 if (X.getOpcode() == ISD::BITCAST)
20538 X = X.getOperand(0);
20539 if (Y.getOpcode() == ISD::BITCAST)
20540 Y = Y.getOperand(0);
20542 EVT MaskVT = Mask.getValueType();
20544 // Validate that the Mask operand is a vector sra node.
20545 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
20546 // there is no psrai.b
20547 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
20548 unsigned SraAmt = ~0;
20549 if (Mask.getOpcode() == ISD::SRA) {
20550 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
20551 if (auto *AmtConst = AmtBV->getConstantSplatNode())
20552 SraAmt = AmtConst->getZExtValue();
20553 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
20554 SDValue SraC = Mask.getOperand(1);
20555 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
20557 if ((SraAmt + 1) != EltBits)
20562 // Now we know we at least have a plendvb with the mask val. See if
20563 // we can form a psignb/w/d.
20564 // psign = x.type == y.type == mask.type && y = sub(0, x);
20565 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
20566 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
20567 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
20568 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
20569 "Unsupported VT for PSIGN");
20570 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
20571 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20573 // PBLENDVB only available on SSE 4.1
20574 if (!Subtarget->hasSSE41())
20577 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
20579 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
20580 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
20581 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
20582 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
20583 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20587 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
20590 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
20591 MachineFunction &MF = DAG.getMachineFunction();
20592 bool OptForSize = MF.getFunction()->getAttributes().
20593 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
20595 // SHLD/SHRD instructions have lower register pressure, but on some
20596 // platforms they have higher latency than the equivalent
20597 // series of shifts/or that would otherwise be generated.
20598 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
20599 // have higher latencies and we are not optimizing for size.
20600 if (!OptForSize && Subtarget->isSHLDSlow())
20603 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
20605 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
20607 if (!N0.hasOneUse() || !N1.hasOneUse())
20610 SDValue ShAmt0 = N0.getOperand(1);
20611 if (ShAmt0.getValueType() != MVT::i8)
20613 SDValue ShAmt1 = N1.getOperand(1);
20614 if (ShAmt1.getValueType() != MVT::i8)
20616 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
20617 ShAmt0 = ShAmt0.getOperand(0);
20618 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
20619 ShAmt1 = ShAmt1.getOperand(0);
20622 unsigned Opc = X86ISD::SHLD;
20623 SDValue Op0 = N0.getOperand(0);
20624 SDValue Op1 = N1.getOperand(0);
20625 if (ShAmt0.getOpcode() == ISD::SUB) {
20626 Opc = X86ISD::SHRD;
20627 std::swap(Op0, Op1);
20628 std::swap(ShAmt0, ShAmt1);
20631 unsigned Bits = VT.getSizeInBits();
20632 if (ShAmt1.getOpcode() == ISD::SUB) {
20633 SDValue Sum = ShAmt1.getOperand(0);
20634 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
20635 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
20636 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
20637 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
20638 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
20639 return DAG.getNode(Opc, DL, VT,
20641 DAG.getNode(ISD::TRUNCATE, DL,
20644 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
20645 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
20647 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
20648 return DAG.getNode(Opc, DL, VT,
20649 N0.getOperand(0), N1.getOperand(0),
20650 DAG.getNode(ISD::TRUNCATE, DL,
20657 // Generate NEG and CMOV for integer abs.
20658 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
20659 EVT VT = N->getValueType(0);
20661 // Since X86 does not have CMOV for 8-bit integer, we don't convert
20662 // 8-bit integer abs to NEG and CMOV.
20663 if (VT.isInteger() && VT.getSizeInBits() == 8)
20666 SDValue N0 = N->getOperand(0);
20667 SDValue N1 = N->getOperand(1);
20670 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
20671 // and change it to SUB and CMOV.
20672 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
20673 N0.getOpcode() == ISD::ADD &&
20674 N0.getOperand(1) == N1 &&
20675 N1.getOpcode() == ISD::SRA &&
20676 N1.getOperand(0) == N0.getOperand(0))
20677 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
20678 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
20679 // Generate SUB & CMOV.
20680 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
20681 DAG.getConstant(0, VT), N0.getOperand(0));
20683 SDValue Ops[] = { N0.getOperand(0), Neg,
20684 DAG.getConstant(X86::COND_GE, MVT::i8),
20685 SDValue(Neg.getNode(), 1) };
20686 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
20691 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
20692 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
20693 TargetLowering::DAGCombinerInfo &DCI,
20694 const X86Subtarget *Subtarget) {
20695 if (DCI.isBeforeLegalizeOps())
20698 if (Subtarget->hasCMov()) {
20699 SDValue RV = performIntegerAbsCombine(N, DAG);
20707 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
20708 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
20709 TargetLowering::DAGCombinerInfo &DCI,
20710 const X86Subtarget *Subtarget) {
20711 LoadSDNode *Ld = cast<LoadSDNode>(N);
20712 EVT RegVT = Ld->getValueType(0);
20713 EVT MemVT = Ld->getMemoryVT();
20715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20716 unsigned RegSz = RegVT.getSizeInBits();
20718 // On Sandybridge unaligned 256bit loads are inefficient.
20719 ISD::LoadExtType Ext = Ld->getExtensionType();
20720 unsigned Alignment = Ld->getAlignment();
20721 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
20722 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
20723 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
20724 unsigned NumElems = RegVT.getVectorNumElements();
20728 SDValue Ptr = Ld->getBasePtr();
20729 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
20731 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20733 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20734 Ld->getPointerInfo(), Ld->isVolatile(),
20735 Ld->isNonTemporal(), Ld->isInvariant(),
20737 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20738 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20739 Ld->getPointerInfo(), Ld->isVolatile(),
20740 Ld->isNonTemporal(), Ld->isInvariant(),
20741 std::min(16U, Alignment));
20742 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20744 Load2.getValue(1));
20746 SDValue NewVec = DAG.getUNDEF(RegVT);
20747 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
20748 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
20749 return DCI.CombineTo(N, NewVec, TF, true);
20752 // If this is a vector EXT Load then attempt to optimize it using a
20753 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
20754 // expansion is still better than scalar code.
20755 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
20756 // emit a shuffle and a arithmetic shift.
20757 // TODO: It is possible to support ZExt by zeroing the undef values
20758 // during the shuffle phase or after the shuffle.
20759 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
20760 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
20761 assert(MemVT != RegVT && "Cannot extend to the same type");
20762 assert(MemVT.isVector() && "Must load a vector from memory");
20764 unsigned NumElems = RegVT.getVectorNumElements();
20765 unsigned MemSz = MemVT.getSizeInBits();
20766 assert(RegSz > MemSz && "Register size must be greater than the mem size");
20768 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
20771 // All sizes must be a power of two.
20772 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
20775 // Attempt to load the original value using scalar loads.
20776 // Find the largest scalar type that divides the total loaded size.
20777 MVT SclrLoadTy = MVT::i8;
20778 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20779 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20780 MVT Tp = (MVT::SimpleValueType)tp;
20781 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
20786 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20787 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
20789 SclrLoadTy = MVT::f64;
20791 // Calculate the number of scalar loads that we need to perform
20792 // in order to load our vector from memory.
20793 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
20794 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
20797 unsigned loadRegZize = RegSz;
20798 if (Ext == ISD::SEXTLOAD && RegSz == 256)
20801 // Represent our vector as a sequence of elements which are the
20802 // largest scalar that we can load.
20803 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
20804 loadRegZize/SclrLoadTy.getSizeInBits());
20806 // Represent the data using the same element type that is stored in
20807 // memory. In practice, we ''widen'' MemVT.
20809 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20810 loadRegZize/MemVT.getScalarType().getSizeInBits());
20812 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
20813 "Invalid vector type");
20815 // We can't shuffle using an illegal type.
20816 if (!TLI.isTypeLegal(WideVecVT))
20819 SmallVector<SDValue, 8> Chains;
20820 SDValue Ptr = Ld->getBasePtr();
20821 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
20822 TLI.getPointerTy());
20823 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
20825 for (unsigned i = 0; i < NumLoads; ++i) {
20826 // Perform a single load.
20827 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
20828 Ptr, Ld->getPointerInfo(),
20829 Ld->isVolatile(), Ld->isNonTemporal(),
20830 Ld->isInvariant(), Ld->getAlignment());
20831 Chains.push_back(ScalarLoad.getValue(1));
20832 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
20833 // another round of DAGCombining.
20835 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
20837 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
20838 ScalarLoad, DAG.getIntPtrConstant(i));
20840 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20843 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
20845 // Bitcast the loaded value to a vector of the original element type, in
20846 // the size of the target vector type.
20847 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
20848 unsigned SizeRatio = RegSz/MemSz;
20850 if (Ext == ISD::SEXTLOAD) {
20851 // If we have SSE4.1 we can directly emit a VSEXT node.
20852 if (Subtarget->hasSSE41()) {
20853 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
20854 return DCI.CombineTo(N, Sext, TF, true);
20857 // Otherwise we'll shuffle the small elements in the high bits of the
20858 // larger type and perform an arithmetic shift. If the shift is not legal
20859 // it's better to scalarize.
20860 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
20863 // Redistribute the loaded elements into the different locations.
20864 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20865 for (unsigned i = 0; i != NumElems; ++i)
20866 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
20868 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20869 DAG.getUNDEF(WideVecVT),
20872 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20874 // Build the arithmetic shift.
20875 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
20876 MemVT.getVectorElementType().getSizeInBits();
20877 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
20878 DAG.getConstant(Amt, RegVT));
20880 return DCI.CombineTo(N, Shuff, TF, true);
20883 // Redistribute the loaded elements into the different locations.
20884 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20885 for (unsigned i = 0; i != NumElems; ++i)
20886 ShuffleVec[i*SizeRatio] = i;
20888 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20889 DAG.getUNDEF(WideVecVT),
20892 // Bitcast to the requested type.
20893 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20894 // Replace the original load with the new sequence
20895 // and return the new chain.
20896 return DCI.CombineTo(N, Shuff, TF, true);
20902 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
20903 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
20904 const X86Subtarget *Subtarget) {
20905 StoreSDNode *St = cast<StoreSDNode>(N);
20906 EVT VT = St->getValue().getValueType();
20907 EVT StVT = St->getMemoryVT();
20909 SDValue StoredVal = St->getOperand(1);
20910 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20912 // If we are saving a concatenation of two XMM registers, perform two stores.
20913 // On Sandy Bridge, 256-bit memory operations are executed by two
20914 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
20915 // memory operation.
20916 unsigned Alignment = St->getAlignment();
20917 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
20918 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
20919 StVT == VT && !IsAligned) {
20920 unsigned NumElems = VT.getVectorNumElements();
20924 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
20925 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
20927 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
20928 SDValue Ptr0 = St->getBasePtr();
20929 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
20931 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
20932 St->getPointerInfo(), St->isVolatile(),
20933 St->isNonTemporal(), Alignment);
20934 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
20935 St->getPointerInfo(), St->isVolatile(),
20936 St->isNonTemporal(),
20937 std::min(16U, Alignment));
20938 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
20941 // Optimize trunc store (of multiple scalars) to shuffle and store.
20942 // First, pack all of the elements in one place. Next, store to memory
20943 // in fewer chunks.
20944 if (St->isTruncatingStore() && VT.isVector()) {
20945 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20946 unsigned NumElems = VT.getVectorNumElements();
20947 assert(StVT != VT && "Cannot truncate to the same type");
20948 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
20949 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
20951 // From, To sizes and ElemCount must be pow of two
20952 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
20953 // We are going to use the original vector elt for storing.
20954 // Accumulated smaller vector elements must be a multiple of the store size.
20955 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
20957 unsigned SizeRatio = FromSz / ToSz;
20959 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
20961 // Create a type on which we perform the shuffle
20962 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
20963 StVT.getScalarType(), NumElems*SizeRatio);
20965 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
20967 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
20968 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20969 for (unsigned i = 0; i != NumElems; ++i)
20970 ShuffleVec[i] = i * SizeRatio;
20972 // Can't shuffle using an illegal type.
20973 if (!TLI.isTypeLegal(WideVecVT))
20976 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
20977 DAG.getUNDEF(WideVecVT),
20979 // At this point all of the data is stored at the bottom of the
20980 // register. We now need to save it to mem.
20982 // Find the largest store unit
20983 MVT StoreType = MVT::i8;
20984 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20985 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20986 MVT Tp = (MVT::SimpleValueType)tp;
20987 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
20991 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20992 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
20993 (64 <= NumElems * ToSz))
20994 StoreType = MVT::f64;
20996 // Bitcast the original vector into a vector of store-size units
20997 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
20998 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
20999 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21000 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21001 SmallVector<SDValue, 8> Chains;
21002 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21003 TLI.getPointerTy());
21004 SDValue Ptr = St->getBasePtr();
21006 // Perform one or more big stores into memory.
21007 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21008 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21009 StoreType, ShuffWide,
21010 DAG.getIntPtrConstant(i));
21011 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21012 St->getPointerInfo(), St->isVolatile(),
21013 St->isNonTemporal(), St->getAlignment());
21014 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21015 Chains.push_back(Ch);
21018 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21021 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21022 // the FP state in cases where an emms may be missing.
21023 // A preferable solution to the general problem is to figure out the right
21024 // places to insert EMMS. This qualifies as a quick hack.
21026 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21027 if (VT.getSizeInBits() != 64)
21030 const Function *F = DAG.getMachineFunction().getFunction();
21031 bool NoImplicitFloatOps = F->getAttributes().
21032 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21033 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21034 && Subtarget->hasSSE2();
21035 if ((VT.isVector() ||
21036 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21037 isa<LoadSDNode>(St->getValue()) &&
21038 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21039 St->getChain().hasOneUse() && !St->isVolatile()) {
21040 SDNode* LdVal = St->getValue().getNode();
21041 LoadSDNode *Ld = nullptr;
21042 int TokenFactorIndex = -1;
21043 SmallVector<SDValue, 8> Ops;
21044 SDNode* ChainVal = St->getChain().getNode();
21045 // Must be a store of a load. We currently handle two cases: the load
21046 // is a direct child, and it's under an intervening TokenFactor. It is
21047 // possible to dig deeper under nested TokenFactors.
21048 if (ChainVal == LdVal)
21049 Ld = cast<LoadSDNode>(St->getChain());
21050 else if (St->getValue().hasOneUse() &&
21051 ChainVal->getOpcode() == ISD::TokenFactor) {
21052 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21053 if (ChainVal->getOperand(i).getNode() == LdVal) {
21054 TokenFactorIndex = i;
21055 Ld = cast<LoadSDNode>(St->getValue());
21057 Ops.push_back(ChainVal->getOperand(i));
21061 if (!Ld || !ISD::isNormalLoad(Ld))
21064 // If this is not the MMX case, i.e. we are just turning i64 load/store
21065 // into f64 load/store, avoid the transformation if there are multiple
21066 // uses of the loaded value.
21067 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21072 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21073 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21075 if (Subtarget->is64Bit() || F64IsLegal) {
21076 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21077 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21078 Ld->getPointerInfo(), Ld->isVolatile(),
21079 Ld->isNonTemporal(), Ld->isInvariant(),
21080 Ld->getAlignment());
21081 SDValue NewChain = NewLd.getValue(1);
21082 if (TokenFactorIndex != -1) {
21083 Ops.push_back(NewChain);
21084 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21086 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21087 St->getPointerInfo(),
21088 St->isVolatile(), St->isNonTemporal(),
21089 St->getAlignment());
21092 // Otherwise, lower to two pairs of 32-bit loads / stores.
21093 SDValue LoAddr = Ld->getBasePtr();
21094 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21095 DAG.getConstant(4, MVT::i32));
21097 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21098 Ld->getPointerInfo(),
21099 Ld->isVolatile(), Ld->isNonTemporal(),
21100 Ld->isInvariant(), Ld->getAlignment());
21101 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21102 Ld->getPointerInfo().getWithOffset(4),
21103 Ld->isVolatile(), Ld->isNonTemporal(),
21105 MinAlign(Ld->getAlignment(), 4));
21107 SDValue NewChain = LoLd.getValue(1);
21108 if (TokenFactorIndex != -1) {
21109 Ops.push_back(LoLd);
21110 Ops.push_back(HiLd);
21111 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21114 LoAddr = St->getBasePtr();
21115 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21116 DAG.getConstant(4, MVT::i32));
21118 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21119 St->getPointerInfo(),
21120 St->isVolatile(), St->isNonTemporal(),
21121 St->getAlignment());
21122 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21123 St->getPointerInfo().getWithOffset(4),
21125 St->isNonTemporal(),
21126 MinAlign(St->getAlignment(), 4));
21127 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21132 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21133 /// and return the operands for the horizontal operation in LHS and RHS. A
21134 /// horizontal operation performs the binary operation on successive elements
21135 /// of its first operand, then on successive elements of its second operand,
21136 /// returning the resulting values in a vector. For example, if
21137 /// A = < float a0, float a1, float a2, float a3 >
21139 /// B = < float b0, float b1, float b2, float b3 >
21140 /// then the result of doing a horizontal operation on A and B is
21141 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21142 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21143 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21144 /// set to A, RHS to B, and the routine returns 'true'.
21145 /// Note that the binary operation should have the property that if one of the
21146 /// operands is UNDEF then the result is UNDEF.
21147 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21148 // Look for the following pattern: if
21149 // A = < float a0, float a1, float a2, float a3 >
21150 // B = < float b0, float b1, float b2, float b3 >
21152 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21153 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21154 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21155 // which is A horizontal-op B.
21157 // At least one of the operands should be a vector shuffle.
21158 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21159 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21162 MVT VT = LHS.getSimpleValueType();
21164 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21165 "Unsupported vector type for horizontal add/sub");
21167 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21168 // operate independently on 128-bit lanes.
21169 unsigned NumElts = VT.getVectorNumElements();
21170 unsigned NumLanes = VT.getSizeInBits()/128;
21171 unsigned NumLaneElts = NumElts / NumLanes;
21172 assert((NumLaneElts % 2 == 0) &&
21173 "Vector type should have an even number of elements in each lane");
21174 unsigned HalfLaneElts = NumLaneElts/2;
21176 // View LHS in the form
21177 // LHS = VECTOR_SHUFFLE A, B, LMask
21178 // If LHS is not a shuffle then pretend it is the shuffle
21179 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21180 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21183 SmallVector<int, 16> LMask(NumElts);
21184 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21185 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21186 A = LHS.getOperand(0);
21187 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21188 B = LHS.getOperand(1);
21189 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21190 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21192 if (LHS.getOpcode() != ISD::UNDEF)
21194 for (unsigned i = 0; i != NumElts; ++i)
21198 // Likewise, view RHS in the form
21199 // RHS = VECTOR_SHUFFLE C, D, RMask
21201 SmallVector<int, 16> RMask(NumElts);
21202 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21203 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21204 C = RHS.getOperand(0);
21205 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21206 D = RHS.getOperand(1);
21207 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21208 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21210 if (RHS.getOpcode() != ISD::UNDEF)
21212 for (unsigned i = 0; i != NumElts; ++i)
21216 // Check that the shuffles are both shuffling the same vectors.
21217 if (!(A == C && B == D) && !(A == D && B == C))
21220 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21221 if (!A.getNode() && !B.getNode())
21224 // If A and B occur in reverse order in RHS, then "swap" them (which means
21225 // rewriting the mask).
21227 CommuteVectorShuffleMask(RMask, NumElts);
21229 // At this point LHS and RHS are equivalent to
21230 // LHS = VECTOR_SHUFFLE A, B, LMask
21231 // RHS = VECTOR_SHUFFLE A, B, RMask
21232 // Check that the masks correspond to performing a horizontal operation.
21233 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21234 for (unsigned i = 0; i != NumLaneElts; ++i) {
21235 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21237 // Ignore any UNDEF components.
21238 if (LIdx < 0 || RIdx < 0 ||
21239 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21240 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21243 // Check that successive elements are being operated on. If not, this is
21244 // not a horizontal operation.
21245 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21246 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21247 if (!(LIdx == Index && RIdx == Index + 1) &&
21248 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21253 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21254 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21258 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
21259 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
21260 const X86Subtarget *Subtarget) {
21261 EVT VT = N->getValueType(0);
21262 SDValue LHS = N->getOperand(0);
21263 SDValue RHS = N->getOperand(1);
21265 // Try to synthesize horizontal adds from adds of shuffles.
21266 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21267 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21268 isHorizontalBinOp(LHS, RHS, true))
21269 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21273 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
21274 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
21275 const X86Subtarget *Subtarget) {
21276 EVT VT = N->getValueType(0);
21277 SDValue LHS = N->getOperand(0);
21278 SDValue RHS = N->getOperand(1);
21280 // Try to synthesize horizontal subs from subs of shuffles.
21281 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21282 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21283 isHorizontalBinOp(LHS, RHS, false))
21284 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21288 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
21289 /// X86ISD::FXOR nodes.
21290 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
21291 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
21292 // F[X]OR(0.0, x) -> x
21293 // F[X]OR(x, 0.0) -> x
21294 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21295 if (C->getValueAPF().isPosZero())
21296 return N->getOperand(1);
21297 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21298 if (C->getValueAPF().isPosZero())
21299 return N->getOperand(0);
21303 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
21304 /// X86ISD::FMAX nodes.
21305 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
21306 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
21308 // Only perform optimizations if UnsafeMath is used.
21309 if (!DAG.getTarget().Options.UnsafeFPMath)
21312 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
21313 // into FMINC and FMAXC, which are Commutative operations.
21314 unsigned NewOp = 0;
21315 switch (N->getOpcode()) {
21316 default: llvm_unreachable("unknown opcode");
21317 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
21318 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
21321 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
21322 N->getOperand(0), N->getOperand(1));
21325 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
21326 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
21327 // FAND(0.0, x) -> 0.0
21328 // FAND(x, 0.0) -> 0.0
21329 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21330 if (C->getValueAPF().isPosZero())
21331 return N->getOperand(0);
21332 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21333 if (C->getValueAPF().isPosZero())
21334 return N->getOperand(1);
21338 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
21339 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
21340 // FANDN(x, 0.0) -> 0.0
21341 // FANDN(0.0, x) -> x
21342 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21343 if (C->getValueAPF().isPosZero())
21344 return N->getOperand(1);
21345 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21346 if (C->getValueAPF().isPosZero())
21347 return N->getOperand(1);
21351 static SDValue PerformBTCombine(SDNode *N,
21353 TargetLowering::DAGCombinerInfo &DCI) {
21354 // BT ignores high bits in the bit index operand.
21355 SDValue Op1 = N->getOperand(1);
21356 if (Op1.hasOneUse()) {
21357 unsigned BitWidth = Op1.getValueSizeInBits();
21358 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
21359 APInt KnownZero, KnownOne;
21360 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
21361 !DCI.isBeforeLegalizeOps());
21362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21363 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
21364 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
21365 DCI.CommitTargetLoweringOpt(TLO);
21370 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
21371 SDValue Op = N->getOperand(0);
21372 if (Op.getOpcode() == ISD::BITCAST)
21373 Op = Op.getOperand(0);
21374 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
21375 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
21376 VT.getVectorElementType().getSizeInBits() ==
21377 OpVT.getVectorElementType().getSizeInBits()) {
21378 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
21383 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
21384 const X86Subtarget *Subtarget) {
21385 EVT VT = N->getValueType(0);
21386 if (!VT.isVector())
21389 SDValue N0 = N->getOperand(0);
21390 SDValue N1 = N->getOperand(1);
21391 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
21394 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
21395 // both SSE and AVX2 since there is no sign-extended shift right
21396 // operation on a vector with 64-bit elements.
21397 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
21398 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
21399 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
21400 N0.getOpcode() == ISD::SIGN_EXTEND)) {
21401 SDValue N00 = N0.getOperand(0);
21403 // EXTLOAD has a better solution on AVX2,
21404 // it may be replaced with X86ISD::VSEXT node.
21405 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
21406 if (!ISD::isNormalLoad(N00.getNode()))
21409 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
21410 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
21412 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
21418 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
21419 TargetLowering::DAGCombinerInfo &DCI,
21420 const X86Subtarget *Subtarget) {
21421 if (!DCI.isBeforeLegalizeOps())
21424 if (!Subtarget->hasFp256())
21427 EVT VT = N->getValueType(0);
21428 if (VT.isVector() && VT.getSizeInBits() == 256) {
21429 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21437 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
21438 const X86Subtarget* Subtarget) {
21440 EVT VT = N->getValueType(0);
21442 // Let legalize expand this if it isn't a legal type yet.
21443 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
21446 EVT ScalarVT = VT.getScalarType();
21447 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
21448 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
21451 SDValue A = N->getOperand(0);
21452 SDValue B = N->getOperand(1);
21453 SDValue C = N->getOperand(2);
21455 bool NegA = (A.getOpcode() == ISD::FNEG);
21456 bool NegB = (B.getOpcode() == ISD::FNEG);
21457 bool NegC = (C.getOpcode() == ISD::FNEG);
21459 // Negative multiplication when NegA xor NegB
21460 bool NegMul = (NegA != NegB);
21462 A = A.getOperand(0);
21464 B = B.getOperand(0);
21466 C = C.getOperand(0);
21470 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
21472 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
21474 return DAG.getNode(Opcode, dl, VT, A, B, C);
21477 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
21478 TargetLowering::DAGCombinerInfo &DCI,
21479 const X86Subtarget *Subtarget) {
21480 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
21481 // (and (i32 x86isd::setcc_carry), 1)
21482 // This eliminates the zext. This transformation is necessary because
21483 // ISD::SETCC is always legalized to i8.
21485 SDValue N0 = N->getOperand(0);
21486 EVT VT = N->getValueType(0);
21488 if (N0.getOpcode() == ISD::AND &&
21490 N0.getOperand(0).hasOneUse()) {
21491 SDValue N00 = N0.getOperand(0);
21492 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21493 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21494 if (!C || C->getZExtValue() != 1)
21496 return DAG.getNode(ISD::AND, dl, VT,
21497 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21498 N00.getOperand(0), N00.getOperand(1)),
21499 DAG.getConstant(1, VT));
21503 if (N0.getOpcode() == ISD::TRUNCATE &&
21505 N0.getOperand(0).hasOneUse()) {
21506 SDValue N00 = N0.getOperand(0);
21507 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21508 return DAG.getNode(ISD::AND, dl, VT,
21509 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21510 N00.getOperand(0), N00.getOperand(1)),
21511 DAG.getConstant(1, VT));
21514 if (VT.is256BitVector()) {
21515 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21523 // Optimize x == -y --> x+y == 0
21524 // x != -y --> x+y != 0
21525 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
21526 const X86Subtarget* Subtarget) {
21527 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
21528 SDValue LHS = N->getOperand(0);
21529 SDValue RHS = N->getOperand(1);
21530 EVT VT = N->getValueType(0);
21533 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
21534 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
21535 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
21536 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21537 LHS.getValueType(), RHS, LHS.getOperand(1));
21538 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21539 addV, DAG.getConstant(0, addV.getValueType()), CC);
21541 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
21542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
21543 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
21544 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21545 RHS.getValueType(), LHS, RHS.getOperand(1));
21546 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21547 addV, DAG.getConstant(0, addV.getValueType()), CC);
21550 if (VT.getScalarType() == MVT::i1) {
21551 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21552 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21553 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
21554 if (!IsSEXT0 && !IsVZero0)
21556 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
21557 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21558 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
21560 if (!IsSEXT1 && !IsVZero1)
21563 if (IsSEXT0 && IsVZero1) {
21564 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
21565 if (CC == ISD::SETEQ)
21566 return DAG.getNOT(DL, LHS.getOperand(0), VT);
21567 return LHS.getOperand(0);
21569 if (IsSEXT1 && IsVZero0) {
21570 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
21571 if (CC == ISD::SETEQ)
21572 return DAG.getNOT(DL, RHS.getOperand(0), VT);
21573 return RHS.getOperand(0);
21580 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
21581 const X86Subtarget *Subtarget) {
21583 MVT VT = N->getOperand(1)->getSimpleValueType(0);
21584 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
21585 "X86insertps is only defined for v4x32");
21587 SDValue Ld = N->getOperand(1);
21588 if (MayFoldLoad(Ld)) {
21589 // Extract the countS bits from the immediate so we can get the proper
21590 // address when narrowing the vector load to a specific element.
21591 // When the second source op is a memory address, interps doesn't use
21592 // countS and just gets an f32 from that address.
21593 unsigned DestIndex =
21594 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
21595 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
21599 // Create this as a scalar to vector to match the instruction pattern.
21600 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
21601 // countS bits are ignored when loading from memory on insertps, which
21602 // means we don't need to explicitly set them to 0.
21603 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
21604 LoadScalarToVector, N->getOperand(2));
21607 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
21608 // as "sbb reg,reg", since it can be extended without zext and produces
21609 // an all-ones bit which is more useful than 0/1 in some cases.
21610 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
21613 return DAG.getNode(ISD::AND, DL, VT,
21614 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21615 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
21616 DAG.getConstant(1, VT));
21617 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
21618 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
21619 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21620 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
21623 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
21624 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
21625 TargetLowering::DAGCombinerInfo &DCI,
21626 const X86Subtarget *Subtarget) {
21628 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
21629 SDValue EFLAGS = N->getOperand(1);
21631 if (CC == X86::COND_A) {
21632 // Try to convert COND_A into COND_B in an attempt to facilitate
21633 // materializing "setb reg".
21635 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
21636 // cannot take an immediate as its first operand.
21638 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
21639 EFLAGS.getValueType().isInteger() &&
21640 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
21641 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
21642 EFLAGS.getNode()->getVTList(),
21643 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
21644 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
21645 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
21649 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
21650 // a zext and produces an all-ones bit which is more useful than 0/1 in some
21652 if (CC == X86::COND_B)
21653 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
21657 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21658 if (Flags.getNode()) {
21659 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21660 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
21666 // Optimize branch condition evaluation.
21668 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
21669 TargetLowering::DAGCombinerInfo &DCI,
21670 const X86Subtarget *Subtarget) {
21672 SDValue Chain = N->getOperand(0);
21673 SDValue Dest = N->getOperand(1);
21674 SDValue EFLAGS = N->getOperand(3);
21675 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
21679 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21680 if (Flags.getNode()) {
21681 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21682 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
21689 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
21690 const X86TargetLowering *XTLI) {
21691 SDValue Op0 = N->getOperand(0);
21692 EVT InVT = Op0->getValueType(0);
21694 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
21695 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
21697 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21698 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
21699 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
21702 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
21703 // a 32-bit target where SSE doesn't support i64->FP operations.
21704 if (Op0.getOpcode() == ISD::LOAD) {
21705 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
21706 EVT VT = Ld->getValueType(0);
21707 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
21708 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
21709 !XTLI->getSubtarget()->is64Bit() &&
21711 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
21712 Ld->getChain(), Op0, DAG);
21713 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
21720 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
21721 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
21722 X86TargetLowering::DAGCombinerInfo &DCI) {
21723 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
21724 // the result is either zero or one (depending on the input carry bit).
21725 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
21726 if (X86::isZeroNode(N->getOperand(0)) &&
21727 X86::isZeroNode(N->getOperand(1)) &&
21728 // We don't have a good way to replace an EFLAGS use, so only do this when
21730 SDValue(N, 1).use_empty()) {
21732 EVT VT = N->getValueType(0);
21733 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
21734 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
21735 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
21736 DAG.getConstant(X86::COND_B,MVT::i8),
21738 DAG.getConstant(1, VT));
21739 return DCI.CombineTo(N, Res1, CarryOut);
21745 // fold (add Y, (sete X, 0)) -> adc 0, Y
21746 // (add Y, (setne X, 0)) -> sbb -1, Y
21747 // (sub (sete X, 0), Y) -> sbb 0, Y
21748 // (sub (setne X, 0), Y) -> adc -1, Y
21749 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
21752 // Look through ZExts.
21753 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
21754 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
21757 SDValue SetCC = Ext.getOperand(0);
21758 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
21761 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
21762 if (CC != X86::COND_E && CC != X86::COND_NE)
21765 SDValue Cmp = SetCC.getOperand(1);
21766 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
21767 !X86::isZeroNode(Cmp.getOperand(1)) ||
21768 !Cmp.getOperand(0).getValueType().isInteger())
21771 SDValue CmpOp0 = Cmp.getOperand(0);
21772 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
21773 DAG.getConstant(1, CmpOp0.getValueType()));
21775 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
21776 if (CC == X86::COND_NE)
21777 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
21778 DL, OtherVal.getValueType(), OtherVal,
21779 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
21780 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
21781 DL, OtherVal.getValueType(), OtherVal,
21782 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
21785 /// PerformADDCombine - Do target-specific dag combines on integer adds.
21786 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
21787 const X86Subtarget *Subtarget) {
21788 EVT VT = N->getValueType(0);
21789 SDValue Op0 = N->getOperand(0);
21790 SDValue Op1 = N->getOperand(1);
21792 // Try to synthesize horizontal adds from adds of shuffles.
21793 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21794 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21795 isHorizontalBinOp(Op0, Op1, true))
21796 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
21798 return OptimizeConditionalInDecrement(N, DAG);
21801 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
21802 const X86Subtarget *Subtarget) {
21803 SDValue Op0 = N->getOperand(0);
21804 SDValue Op1 = N->getOperand(1);
21806 // X86 can't encode an immediate LHS of a sub. See if we can push the
21807 // negation into a preceding instruction.
21808 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
21809 // If the RHS of the sub is a XOR with one use and a constant, invert the
21810 // immediate. Then add one to the LHS of the sub so we can turn
21811 // X-Y -> X+~Y+1, saving one register.
21812 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
21813 isa<ConstantSDNode>(Op1.getOperand(1))) {
21814 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
21815 EVT VT = Op0.getValueType();
21816 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
21818 DAG.getConstant(~XorC, VT));
21819 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
21820 DAG.getConstant(C->getAPIntValue()+1, VT));
21824 // Try to synthesize horizontal adds from adds of shuffles.
21825 EVT VT = N->getValueType(0);
21826 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21827 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21828 isHorizontalBinOp(Op0, Op1, true))
21829 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
21831 return OptimizeConditionalInDecrement(N, DAG);
21834 /// performVZEXTCombine - Performs build vector combines
21835 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
21836 TargetLowering::DAGCombinerInfo &DCI,
21837 const X86Subtarget *Subtarget) {
21838 // (vzext (bitcast (vzext (x)) -> (vzext x)
21839 SDValue In = N->getOperand(0);
21840 while (In.getOpcode() == ISD::BITCAST)
21841 In = In.getOperand(0);
21843 if (In.getOpcode() != X86ISD::VZEXT)
21846 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
21850 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
21851 DAGCombinerInfo &DCI) const {
21852 SelectionDAG &DAG = DCI.DAG;
21853 switch (N->getOpcode()) {
21855 case ISD::EXTRACT_VECTOR_ELT:
21856 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
21858 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
21859 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
21860 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
21861 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
21862 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
21863 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
21866 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
21867 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
21868 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
21869 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
21870 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
21871 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
21872 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
21873 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
21874 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
21876 case X86ISD::FOR: return PerformFORCombine(N, DAG);
21878 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
21879 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
21880 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
21881 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
21882 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
21883 case ISD::ANY_EXTEND:
21884 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
21885 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
21886 case ISD::SIGN_EXTEND_INREG:
21887 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
21888 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
21889 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
21890 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
21891 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
21892 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
21893 case X86ISD::SHUFP: // Handle all target specific shuffles
21894 case X86ISD::PALIGNR:
21895 case X86ISD::UNPCKH:
21896 case X86ISD::UNPCKL:
21897 case X86ISD::MOVHLPS:
21898 case X86ISD::MOVLHPS:
21899 case X86ISD::PSHUFD:
21900 case X86ISD::PSHUFHW:
21901 case X86ISD::PSHUFLW:
21902 case X86ISD::MOVSS:
21903 case X86ISD::MOVSD:
21904 case X86ISD::VPERMILP:
21905 case X86ISD::VPERM2X128:
21906 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
21907 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
21908 case ISD::INTRINSIC_WO_CHAIN:
21909 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
21910 case X86ISD::INSERTPS:
21911 return PerformINSERTPSCombine(N, DAG, Subtarget);
21912 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
21918 /// isTypeDesirableForOp - Return true if the target has native support for
21919 /// the specified value type and it is 'desirable' to use the type for the
21920 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
21921 /// instruction encodings are longer and some i16 instructions are slow.
21922 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
21923 if (!isTypeLegal(VT))
21925 if (VT != MVT::i16)
21932 case ISD::SIGN_EXTEND:
21933 case ISD::ZERO_EXTEND:
21934 case ISD::ANY_EXTEND:
21947 /// IsDesirableToPromoteOp - This method query the target whether it is
21948 /// beneficial for dag combiner to promote the specified node. If true, it
21949 /// should return the desired promotion type by reference.
21950 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
21951 EVT VT = Op.getValueType();
21952 if (VT != MVT::i16)
21955 bool Promote = false;
21956 bool Commute = false;
21957 switch (Op.getOpcode()) {
21960 LoadSDNode *LD = cast<LoadSDNode>(Op);
21961 // If the non-extending load has a single use and it's not live out, then it
21962 // might be folded.
21963 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
21964 Op.hasOneUse()*/) {
21965 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
21966 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
21967 // The only case where we'd want to promote LOAD (rather then it being
21968 // promoted as an operand is when it's only use is liveout.
21969 if (UI->getOpcode() != ISD::CopyToReg)
21976 case ISD::SIGN_EXTEND:
21977 case ISD::ZERO_EXTEND:
21978 case ISD::ANY_EXTEND:
21983 SDValue N0 = Op.getOperand(0);
21984 // Look out for (store (shl (load), x)).
21985 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
21998 SDValue N0 = Op.getOperand(0);
21999 SDValue N1 = Op.getOperand(1);
22000 if (!Commute && MayFoldLoad(N1))
22002 // Avoid disabling potential load folding opportunities.
22003 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22005 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22015 //===----------------------------------------------------------------------===//
22016 // X86 Inline Assembly Support
22017 //===----------------------------------------------------------------------===//
22020 // Helper to match a string separated by whitespace.
22021 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22022 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22024 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22025 StringRef piece(*args[i]);
22026 if (!s.startswith(piece)) // Check if the piece matches.
22029 s = s.substr(piece.size());
22030 StringRef::size_type pos = s.find_first_not_of(" \t");
22031 if (pos == 0) // We matched a prefix.
22039 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22042 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22044 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22045 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22046 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22047 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22049 if (AsmPieces.size() == 3)
22051 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22058 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22059 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22061 std::string AsmStr = IA->getAsmString();
22063 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22064 if (!Ty || Ty->getBitWidth() % 16 != 0)
22067 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22068 SmallVector<StringRef, 4> AsmPieces;
22069 SplitString(AsmStr, AsmPieces, ";\n");
22071 switch (AsmPieces.size()) {
22072 default: return false;
22074 // FIXME: this should verify that we are targeting a 486 or better. If not,
22075 // we will turn this bswap into something that will be lowered to logical
22076 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22077 // lower so don't worry about this.
22079 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22080 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22081 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22082 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22083 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22084 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22085 // No need to check constraints, nothing other than the equivalent of
22086 // "=r,0" would be valid here.
22087 return IntrinsicLowering::LowerToByteSwap(CI);
22090 // rorw $$8, ${0:w} --> llvm.bswap.i16
22091 if (CI->getType()->isIntegerTy(16) &&
22092 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22093 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22094 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22096 const std::string &ConstraintsStr = IA->getConstraintString();
22097 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22098 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22099 if (clobbersFlagRegisters(AsmPieces))
22100 return IntrinsicLowering::LowerToByteSwap(CI);
22104 if (CI->getType()->isIntegerTy(32) &&
22105 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22106 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22107 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22108 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22110 const std::string &ConstraintsStr = IA->getConstraintString();
22111 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22112 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22113 if (clobbersFlagRegisters(AsmPieces))
22114 return IntrinsicLowering::LowerToByteSwap(CI);
22117 if (CI->getType()->isIntegerTy(64)) {
22118 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22119 if (Constraints.size() >= 2 &&
22120 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22121 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22122 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22123 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22124 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22125 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22126 return IntrinsicLowering::LowerToByteSwap(CI);
22134 /// getConstraintType - Given a constraint letter, return the type of
22135 /// constraint it is for this target.
22136 X86TargetLowering::ConstraintType
22137 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22138 if (Constraint.size() == 1) {
22139 switch (Constraint[0]) {
22150 return C_RegisterClass;
22174 return TargetLowering::getConstraintType(Constraint);
22177 /// Examine constraint type and operand type and determine a weight value.
22178 /// This object must already have been set up with the operand type
22179 /// and the current alternative constraint selected.
22180 TargetLowering::ConstraintWeight
22181 X86TargetLowering::getSingleConstraintMatchWeight(
22182 AsmOperandInfo &info, const char *constraint) const {
22183 ConstraintWeight weight = CW_Invalid;
22184 Value *CallOperandVal = info.CallOperandVal;
22185 // If we don't have a value, we can't do a match,
22186 // but allow it at the lowest weight.
22187 if (!CallOperandVal)
22189 Type *type = CallOperandVal->getType();
22190 // Look at the constraint type.
22191 switch (*constraint) {
22193 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22204 if (CallOperandVal->getType()->isIntegerTy())
22205 weight = CW_SpecificReg;
22210 if (type->isFloatingPointTy())
22211 weight = CW_SpecificReg;
22214 if (type->isX86_MMXTy() && Subtarget->hasMMX())
22215 weight = CW_SpecificReg;
22219 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22220 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22221 weight = CW_Register;
22224 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22225 if (C->getZExtValue() <= 31)
22226 weight = CW_Constant;
22230 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22231 if (C->getZExtValue() <= 63)
22232 weight = CW_Constant;
22236 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22237 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22238 weight = CW_Constant;
22242 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22243 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22244 weight = CW_Constant;
22248 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22249 if (C->getZExtValue() <= 3)
22250 weight = CW_Constant;
22254 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22255 if (C->getZExtValue() <= 0xff)
22256 weight = CW_Constant;
22261 if (dyn_cast<ConstantFP>(CallOperandVal)) {
22262 weight = CW_Constant;
22266 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22267 if ((C->getSExtValue() >= -0x80000000LL) &&
22268 (C->getSExtValue() <= 0x7fffffffLL))
22269 weight = CW_Constant;
22273 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22274 if (C->getZExtValue() <= 0xffffffff)
22275 weight = CW_Constant;
22282 /// LowerXConstraint - try to replace an X constraint, which matches anything,
22283 /// with another that has more specific requirements based on the type of the
22284 /// corresponding operand.
22285 const char *X86TargetLowering::
22286 LowerXConstraint(EVT ConstraintVT) const {
22287 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
22288 // 'f' like normal targets.
22289 if (ConstraintVT.isFloatingPoint()) {
22290 if (Subtarget->hasSSE2())
22292 if (Subtarget->hasSSE1())
22296 return TargetLowering::LowerXConstraint(ConstraintVT);
22299 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
22300 /// vector. If it is invalid, don't add anything to Ops.
22301 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
22302 std::string &Constraint,
22303 std::vector<SDValue>&Ops,
22304 SelectionDAG &DAG) const {
22307 // Only support length 1 constraints for now.
22308 if (Constraint.length() > 1) return;
22310 char ConstraintLetter = Constraint[0];
22311 switch (ConstraintLetter) {
22314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22315 if (C->getZExtValue() <= 31) {
22316 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22323 if (C->getZExtValue() <= 63) {
22324 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22331 if (isInt<8>(C->getSExtValue())) {
22332 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22339 if (C->getZExtValue() <= 255) {
22340 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22346 // 32-bit signed value
22347 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22348 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22349 C->getSExtValue())) {
22350 // Widen to 64 bits here to get it sign extended.
22351 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
22354 // FIXME gcc accepts some relocatable values here too, but only in certain
22355 // memory models; it's complicated.
22360 // 32-bit unsigned value
22361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22362 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22363 C->getZExtValue())) {
22364 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22368 // FIXME gcc accepts some relocatable values here too, but only in certain
22369 // memory models; it's complicated.
22373 // Literal immediates are always ok.
22374 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
22375 // Widen to 64 bits here to get it sign extended.
22376 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
22380 // In any sort of PIC mode addresses need to be computed at runtime by
22381 // adding in a register or some sort of table lookup. These can't
22382 // be used as immediates.
22383 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
22386 // If we are in non-pic codegen mode, we allow the address of a global (with
22387 // an optional displacement) to be used with 'i'.
22388 GlobalAddressSDNode *GA = nullptr;
22389 int64_t Offset = 0;
22391 // Match either (GA), (GA+C), (GA+C1+C2), etc.
22393 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
22394 Offset += GA->getOffset();
22396 } else if (Op.getOpcode() == ISD::ADD) {
22397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22398 Offset += C->getZExtValue();
22399 Op = Op.getOperand(0);
22402 } else if (Op.getOpcode() == ISD::SUB) {
22403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22404 Offset += -C->getZExtValue();
22405 Op = Op.getOperand(0);
22410 // Otherwise, this isn't something we can handle, reject it.
22414 const GlobalValue *GV = GA->getGlobal();
22415 // If we require an extra load to get this address, as in PIC mode, we
22416 // can't accept it.
22417 if (isGlobalStubReference(
22418 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
22421 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
22422 GA->getValueType(0), Offset);
22427 if (Result.getNode()) {
22428 Ops.push_back(Result);
22431 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
22434 std::pair<unsigned, const TargetRegisterClass*>
22435 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
22437 // First, see if this is a constraint that directly corresponds to an LLVM
22439 if (Constraint.size() == 1) {
22440 // GCC Constraint Letters
22441 switch (Constraint[0]) {
22443 // TODO: Slight differences here in allocation order and leaving
22444 // RIP in the class. Do they matter any more here than they do
22445 // in the normal allocation?
22446 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
22447 if (Subtarget->is64Bit()) {
22448 if (VT == MVT::i32 || VT == MVT::f32)
22449 return std::make_pair(0U, &X86::GR32RegClass);
22450 if (VT == MVT::i16)
22451 return std::make_pair(0U, &X86::GR16RegClass);
22452 if (VT == MVT::i8 || VT == MVT::i1)
22453 return std::make_pair(0U, &X86::GR8RegClass);
22454 if (VT == MVT::i64 || VT == MVT::f64)
22455 return std::make_pair(0U, &X86::GR64RegClass);
22458 // 32-bit fallthrough
22459 case 'Q': // Q_REGS
22460 if (VT == MVT::i32 || VT == MVT::f32)
22461 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
22462 if (VT == MVT::i16)
22463 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
22464 if (VT == MVT::i8 || VT == MVT::i1)
22465 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
22466 if (VT == MVT::i64)
22467 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
22469 case 'r': // GENERAL_REGS
22470 case 'l': // INDEX_REGS
22471 if (VT == MVT::i8 || VT == MVT::i1)
22472 return std::make_pair(0U, &X86::GR8RegClass);
22473 if (VT == MVT::i16)
22474 return std::make_pair(0U, &X86::GR16RegClass);
22475 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
22476 return std::make_pair(0U, &X86::GR32RegClass);
22477 return std::make_pair(0U, &X86::GR64RegClass);
22478 case 'R': // LEGACY_REGS
22479 if (VT == MVT::i8 || VT == MVT::i1)
22480 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
22481 if (VT == MVT::i16)
22482 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
22483 if (VT == MVT::i32 || !Subtarget->is64Bit())
22484 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
22485 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
22486 case 'f': // FP Stack registers.
22487 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
22488 // value to the correct fpstack register class.
22489 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
22490 return std::make_pair(0U, &X86::RFP32RegClass);
22491 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
22492 return std::make_pair(0U, &X86::RFP64RegClass);
22493 return std::make_pair(0U, &X86::RFP80RegClass);
22494 case 'y': // MMX_REGS if MMX allowed.
22495 if (!Subtarget->hasMMX()) break;
22496 return std::make_pair(0U, &X86::VR64RegClass);
22497 case 'Y': // SSE_REGS if SSE2 allowed
22498 if (!Subtarget->hasSSE2()) break;
22500 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
22501 if (!Subtarget->hasSSE1()) break;
22503 switch (VT.SimpleTy) {
22505 // Scalar SSE types.
22508 return std::make_pair(0U, &X86::FR32RegClass);
22511 return std::make_pair(0U, &X86::FR64RegClass);
22519 return std::make_pair(0U, &X86::VR128RegClass);
22527 return std::make_pair(0U, &X86::VR256RegClass);
22532 return std::make_pair(0U, &X86::VR512RegClass);
22538 // Use the default implementation in TargetLowering to convert the register
22539 // constraint into a member of a register class.
22540 std::pair<unsigned, const TargetRegisterClass*> Res;
22541 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
22543 // Not found as a standard register?
22545 // Map st(0) -> st(7) -> ST0
22546 if (Constraint.size() == 7 && Constraint[0] == '{' &&
22547 tolower(Constraint[1]) == 's' &&
22548 tolower(Constraint[2]) == 't' &&
22549 Constraint[3] == '(' &&
22550 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
22551 Constraint[5] == ')' &&
22552 Constraint[6] == '}') {
22554 Res.first = X86::ST0+Constraint[4]-'0';
22555 Res.second = &X86::RFP80RegClass;
22559 // GCC allows "st(0)" to be called just plain "st".
22560 if (StringRef("{st}").equals_lower(Constraint)) {
22561 Res.first = X86::ST0;
22562 Res.second = &X86::RFP80RegClass;
22567 if (StringRef("{flags}").equals_lower(Constraint)) {
22568 Res.first = X86::EFLAGS;
22569 Res.second = &X86::CCRRegClass;
22573 // 'A' means EAX + EDX.
22574 if (Constraint == "A") {
22575 Res.first = X86::EAX;
22576 Res.second = &X86::GR32_ADRegClass;
22582 // Otherwise, check to see if this is a register class of the wrong value
22583 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
22584 // turn into {ax},{dx}.
22585 if (Res.second->hasType(VT))
22586 return Res; // Correct type already, nothing to do.
22588 // All of the single-register GCC register classes map their values onto
22589 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
22590 // really want an 8-bit or 32-bit register, map to the appropriate register
22591 // class and return the appropriate register.
22592 if (Res.second == &X86::GR16RegClass) {
22593 if (VT == MVT::i8 || VT == MVT::i1) {
22594 unsigned DestReg = 0;
22595 switch (Res.first) {
22597 case X86::AX: DestReg = X86::AL; break;
22598 case X86::DX: DestReg = X86::DL; break;
22599 case X86::CX: DestReg = X86::CL; break;
22600 case X86::BX: DestReg = X86::BL; break;
22603 Res.first = DestReg;
22604 Res.second = &X86::GR8RegClass;
22606 } else if (VT == MVT::i32 || VT == MVT::f32) {
22607 unsigned DestReg = 0;
22608 switch (Res.first) {
22610 case X86::AX: DestReg = X86::EAX; break;
22611 case X86::DX: DestReg = X86::EDX; break;
22612 case X86::CX: DestReg = X86::ECX; break;
22613 case X86::BX: DestReg = X86::EBX; break;
22614 case X86::SI: DestReg = X86::ESI; break;
22615 case X86::DI: DestReg = X86::EDI; break;
22616 case X86::BP: DestReg = X86::EBP; break;
22617 case X86::SP: DestReg = X86::ESP; break;
22620 Res.first = DestReg;
22621 Res.second = &X86::GR32RegClass;
22623 } else if (VT == MVT::i64 || VT == MVT::f64) {
22624 unsigned DestReg = 0;
22625 switch (Res.first) {
22627 case X86::AX: DestReg = X86::RAX; break;
22628 case X86::DX: DestReg = X86::RDX; break;
22629 case X86::CX: DestReg = X86::RCX; break;
22630 case X86::BX: DestReg = X86::RBX; break;
22631 case X86::SI: DestReg = X86::RSI; break;
22632 case X86::DI: DestReg = X86::RDI; break;
22633 case X86::BP: DestReg = X86::RBP; break;
22634 case X86::SP: DestReg = X86::RSP; break;
22637 Res.first = DestReg;
22638 Res.second = &X86::GR64RegClass;
22641 } else if (Res.second == &X86::FR32RegClass ||
22642 Res.second == &X86::FR64RegClass ||
22643 Res.second == &X86::VR128RegClass ||
22644 Res.second == &X86::VR256RegClass ||
22645 Res.second == &X86::FR32XRegClass ||
22646 Res.second == &X86::FR64XRegClass ||
22647 Res.second == &X86::VR128XRegClass ||
22648 Res.second == &X86::VR256XRegClass ||
22649 Res.second == &X86::VR512RegClass) {
22650 // Handle references to XMM physical registers that got mapped into the
22651 // wrong class. This can happen with constraints like {xmm0} where the
22652 // target independent register mapper will just pick the first match it can
22653 // find, ignoring the required type.
22655 if (VT == MVT::f32 || VT == MVT::i32)
22656 Res.second = &X86::FR32RegClass;
22657 else if (VT == MVT::f64 || VT == MVT::i64)
22658 Res.second = &X86::FR64RegClass;
22659 else if (X86::VR128RegClass.hasType(VT))
22660 Res.second = &X86::VR128RegClass;
22661 else if (X86::VR256RegClass.hasType(VT))
22662 Res.second = &X86::VR256RegClass;
22663 else if (X86::VR512RegClass.hasType(VT))
22664 Res.second = &X86::VR512RegClass;
22670 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
22672 // Scaling factors are not free at all.
22673 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
22674 // will take 2 allocations in the out of order engine instead of 1
22675 // for plain addressing mode, i.e. inst (reg1).
22677 // vaddps (%rsi,%drx), %ymm0, %ymm1
22678 // Requires two allocations (one for the load, one for the computation)
22680 // vaddps (%rsi), %ymm0, %ymm1
22681 // Requires just 1 allocation, i.e., freeing allocations for other operations
22682 // and having less micro operations to execute.
22684 // For some X86 architectures, this is even worse because for instance for
22685 // stores, the complex addressing mode forces the instruction to use the
22686 // "load" ports instead of the dedicated "store" port.
22687 // E.g., on Haswell:
22688 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
22689 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
22690 if (isLegalAddressingMode(AM, Ty))
22691 // Scale represents reg2 * scale, thus account for 1
22692 // as soon as we use a second register.
22693 return AM.Scale != 0;
22697 bool X86TargetLowering::isTargetFTOL() const {
22698 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();