1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (Subtarget->hasXOP()) {
1054 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1055 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1056 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1057 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1058 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1059 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1060 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1061 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1064 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1065 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1066 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1070 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1072 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1073 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1077 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1086 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1087 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1089 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1090 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1099 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1100 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1102 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1103 // even though v8i16 is a legal type.
1104 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1105 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1106 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1108 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1110 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1112 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1113 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1115 for (MVT VT : MVT::fp_vector_valuetypes())
1116 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1118 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1119 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1121 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1122 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1124 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1125 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1132 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1136 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1139 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1142 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1143 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1144 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1145 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1146 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1147 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1149 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1150 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1151 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1152 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1154 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1155 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1156 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1157 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1158 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1161 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1163 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1164 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1165 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1167 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1168 setOperationAction(ISD::FMA, MVT::f32, Legal);
1169 setOperationAction(ISD::FMA, MVT::f64, Legal);
1172 if (Subtarget->hasInt256()) {
1173 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1174 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1175 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1176 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1179 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1180 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1183 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1184 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1185 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1186 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1188 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1189 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1190 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1191 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1193 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1194 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1195 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1196 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1197 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1198 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1199 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1200 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1201 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1202 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1203 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1204 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1206 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1207 // when we have a 256bit-wide blend with immediate.
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1210 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1211 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1212 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1213 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1214 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1215 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1218 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1223 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1225 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1226 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1227 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1228 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1232 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1235 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1236 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1237 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1238 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1240 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1241 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1243 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1244 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1245 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1247 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1248 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1249 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1250 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1251 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1254 // In the customized shift lowering, the legal cases in AVX2 will be
1256 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1257 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1259 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1260 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1262 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1263 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1265 // Custom lower several nodes for 256-bit types.
1266 for (MVT VT : MVT::vector_valuetypes()) {
1267 if (VT.getScalarSizeInBits() >= 32) {
1268 setOperationAction(ISD::MLOAD, VT, Legal);
1269 setOperationAction(ISD::MSTORE, VT, Legal);
1271 // Extract subvector is special because the value type
1272 // (result) is 128-bit but the source is 256-bit wide.
1273 if (VT.is128BitVector()) {
1274 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1276 // Do not attempt to custom lower other non-256-bit vectors
1277 if (!VT.is256BitVector())
1280 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1281 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1282 setOperationAction(ISD::VSELECT, VT, Custom);
1283 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1284 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1285 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1286 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1287 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1290 if (Subtarget->hasInt256())
1291 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1293 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1294 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1295 MVT VT = (MVT::SimpleValueType)i;
1297 // Do not attempt to promote non-256-bit vectors
1298 if (!VT.is256BitVector())
1301 setOperationAction(ISD::AND, VT, Promote);
1302 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1303 setOperationAction(ISD::OR, VT, Promote);
1304 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1305 setOperationAction(ISD::XOR, VT, Promote);
1306 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1307 setOperationAction(ISD::LOAD, VT, Promote);
1308 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1309 setOperationAction(ISD::SELECT, VT, Promote);
1310 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1314 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1315 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1316 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1317 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1318 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1320 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1321 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1322 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1324 for (MVT VT : MVT::fp_vector_valuetypes())
1325 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1327 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1328 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1329 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1330 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1331 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1332 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1333 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1334 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1335 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1336 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1337 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1338 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1340 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1341 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1342 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1343 setOperationAction(ISD::XOR, MVT::i1, Legal);
1344 setOperationAction(ISD::OR, MVT::i1, Legal);
1345 setOperationAction(ISD::AND, MVT::i1, Legal);
1346 setOperationAction(ISD::SUB, MVT::i1, Custom);
1347 setOperationAction(ISD::ADD, MVT::i1, Custom);
1348 setOperationAction(ISD::MUL, MVT::i1, Custom);
1349 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1350 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1352 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1353 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1355 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1356 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1357 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1358 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1360 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1362 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1363 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1364 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1365 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1366 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1367 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1368 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1369 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1371 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1372 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1373 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1374 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1375 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1377 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1378 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1379 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1380 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1382 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1383 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1384 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1385 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1386 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1388 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1389 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1390 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1391 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1392 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1393 if (Subtarget->hasVLX()){
1394 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1395 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1396 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1397 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1398 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1400 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1401 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1402 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1403 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1404 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1406 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1407 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1408 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1409 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1410 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1411 if (Subtarget->hasDQI()) {
1412 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1413 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1416 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1417 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1419 if (Subtarget->hasVLX()) {
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1422 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1424 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1430 if (Subtarget->hasVLX()) {
1431 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1432 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1433 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1434 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1435 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1436 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1437 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1440 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1441 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1443 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1444 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1445 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1446 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1447 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1452 if (Subtarget->hasDQI()) {
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1454 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1456 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1457 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1458 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1459 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1460 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1461 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1462 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1463 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1464 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1465 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1467 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1473 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1474 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1476 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1478 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1480 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1481 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1482 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1483 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1484 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1485 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1490 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1491 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1492 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1493 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1494 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1496 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1497 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1499 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1500 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1502 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1503 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1505 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1507 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1508 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1510 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1511 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1513 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1514 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1516 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1517 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1518 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1519 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1520 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1521 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1523 if (Subtarget->hasCDI()) {
1524 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1525 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1529 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1530 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1531 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1532 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1533 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1534 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1538 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1539 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1541 if (Subtarget->hasVLX()) {
1542 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1543 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1544 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1545 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1546 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1547 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1548 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1551 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1552 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1553 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1554 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1556 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1557 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1558 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1559 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1560 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1561 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1562 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1563 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1565 } // Subtarget->hasCDI()
1567 if (Subtarget->hasDQI()) {
1568 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1569 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1570 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1572 // Custom lower several nodes.
1573 for (MVT VT : MVT::vector_valuetypes()) {
1574 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1576 setOperationAction(ISD::AND, VT, Legal);
1577 setOperationAction(ISD::OR, VT, Legal);
1578 setOperationAction(ISD::XOR, VT, Legal);
1580 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1581 setOperationAction(ISD::MGATHER, VT, Custom);
1582 setOperationAction(ISD::MSCATTER, VT, Custom);
1584 // Extract subvector is special because the value type
1585 // (result) is 256/128-bit but the source is 512-bit wide.
1586 if (VT.is128BitVector() || VT.is256BitVector()) {
1587 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1589 if (VT.getVectorElementType() == MVT::i1)
1590 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1592 // Do not attempt to custom lower other non-512-bit vectors
1593 if (!VT.is512BitVector())
1596 if (EltSize >= 32) {
1597 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1598 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1599 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1600 setOperationAction(ISD::VSELECT, VT, Legal);
1601 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1602 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1603 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1604 setOperationAction(ISD::MLOAD, VT, Legal);
1605 setOperationAction(ISD::MSTORE, VT, Legal);
1608 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1609 MVT VT = (MVT::SimpleValueType)i;
1611 // Do not attempt to promote non-512-bit vectors.
1612 if (!VT.is512BitVector())
1615 setOperationAction(ISD::SELECT, VT, Promote);
1616 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1620 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1621 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1622 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1624 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1625 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1627 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1628 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1629 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1630 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1631 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1632 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1633 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1634 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1635 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1636 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1637 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1638 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1640 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1641 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1644 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1645 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1646 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1647 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1648 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1649 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1650 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1651 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1652 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1653 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1655 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1656 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1660 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1661 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1662 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1663 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1664 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1665 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1669 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1670 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1671 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1672 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1673 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1674 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1675 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1676 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1678 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1679 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1680 if (Subtarget->hasVLX())
1681 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1683 if (Subtarget->hasCDI()) {
1684 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1685 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1686 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1687 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1690 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1691 const MVT VT = (MVT::SimpleValueType)i;
1693 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1695 // Do not attempt to promote non-512-bit vectors.
1696 if (!VT.is512BitVector())
1700 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1701 setOperationAction(ISD::VSELECT, VT, Legal);
1706 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1707 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1708 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1710 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1711 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1714 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1715 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1716 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1717 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1718 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1719 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1720 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1721 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1723 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1724 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1725 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1726 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1727 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1728 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1729 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1730 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1732 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1733 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1734 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1735 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1736 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1737 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1738 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1739 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1742 // We want to custom lower some of our intrinsics.
1743 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1744 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1745 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1746 if (!Subtarget->is64Bit())
1747 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1749 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1750 // handle type legalization for these operations here.
1752 // FIXME: We really should do custom legalization for addition and
1753 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1754 // than generic legalization for 64-bit multiplication-with-overflow, though.
1755 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1756 // Add/Sub/Mul with overflow operations are custom lowered.
1758 setOperationAction(ISD::SADDO, VT, Custom);
1759 setOperationAction(ISD::UADDO, VT, Custom);
1760 setOperationAction(ISD::SSUBO, VT, Custom);
1761 setOperationAction(ISD::USUBO, VT, Custom);
1762 setOperationAction(ISD::SMULO, VT, Custom);
1763 setOperationAction(ISD::UMULO, VT, Custom);
1766 if (!Subtarget->is64Bit()) {
1767 // These libcalls are not available in 32-bit.
1768 setLibcallName(RTLIB::SHL_I128, nullptr);
1769 setLibcallName(RTLIB::SRL_I128, nullptr);
1770 setLibcallName(RTLIB::SRA_I128, nullptr);
1773 // Combine sin / cos into one node or libcall if possible.
1774 if (Subtarget->hasSinCos()) {
1775 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1776 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1777 if (Subtarget->isTargetDarwin()) {
1778 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1779 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1780 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1781 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1785 if (Subtarget->isTargetWin64()) {
1786 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1787 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1788 setOperationAction(ISD::SREM, MVT::i128, Custom);
1789 setOperationAction(ISD::UREM, MVT::i128, Custom);
1790 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1791 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1794 // We have target-specific dag combine patterns for the following nodes:
1795 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1796 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1797 setTargetDAGCombine(ISD::BITCAST);
1798 setTargetDAGCombine(ISD::VSELECT);
1799 setTargetDAGCombine(ISD::SELECT);
1800 setTargetDAGCombine(ISD::SHL);
1801 setTargetDAGCombine(ISD::SRA);
1802 setTargetDAGCombine(ISD::SRL);
1803 setTargetDAGCombine(ISD::OR);
1804 setTargetDAGCombine(ISD::AND);
1805 setTargetDAGCombine(ISD::ADD);
1806 setTargetDAGCombine(ISD::FADD);
1807 setTargetDAGCombine(ISD::FSUB);
1808 setTargetDAGCombine(ISD::FMA);
1809 setTargetDAGCombine(ISD::SUB);
1810 setTargetDAGCombine(ISD::LOAD);
1811 setTargetDAGCombine(ISD::MLOAD);
1812 setTargetDAGCombine(ISD::STORE);
1813 setTargetDAGCombine(ISD::MSTORE);
1814 setTargetDAGCombine(ISD::ZERO_EXTEND);
1815 setTargetDAGCombine(ISD::ANY_EXTEND);
1816 setTargetDAGCombine(ISD::SIGN_EXTEND);
1817 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1818 setTargetDAGCombine(ISD::SINT_TO_FP);
1819 setTargetDAGCombine(ISD::UINT_TO_FP);
1820 setTargetDAGCombine(ISD::SETCC);
1821 setTargetDAGCombine(ISD::BUILD_VECTOR);
1822 setTargetDAGCombine(ISD::MUL);
1823 setTargetDAGCombine(ISD::XOR);
1825 computeRegisterProperties(Subtarget->getRegisterInfo());
1827 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1828 MaxStoresPerMemsetOptSize = 8;
1829 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1830 MaxStoresPerMemcpyOptSize = 4;
1831 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1832 MaxStoresPerMemmoveOptSize = 4;
1833 setPrefLoopAlignment(4); // 2^4 bytes.
1835 // A predictable cmov does not hurt on an in-order CPU.
1836 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1837 PredictableSelectIsExpensive = !Subtarget->isAtom();
1838 EnableExtLdPromotion = true;
1839 setPrefFunctionAlignment(4); // 2^4 bytes.
1841 verifyIntrinsicTables();
1844 // This has so far only been implemented for 64-bit MachO.
1845 bool X86TargetLowering::useLoadStackGuardNode() const {
1846 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1849 TargetLoweringBase::LegalizeTypeAction
1850 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1851 if (ExperimentalVectorWideningLegalization &&
1852 VT.getVectorNumElements() != 1 &&
1853 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1854 return TypeWidenVector;
1856 return TargetLoweringBase::getPreferredVectorAction(VT);
1859 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1862 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1864 const unsigned NumElts = VT.getVectorNumElements();
1865 const EVT EltVT = VT.getVectorElementType();
1866 if (VT.is512BitVector()) {
1867 if (Subtarget->hasAVX512())
1868 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1869 EltVT == MVT::f32 || EltVT == MVT::f64)
1871 case 8: return MVT::v8i1;
1872 case 16: return MVT::v16i1;
1874 if (Subtarget->hasBWI())
1875 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1877 case 32: return MVT::v32i1;
1878 case 64: return MVT::v64i1;
1882 if (VT.is256BitVector() || VT.is128BitVector()) {
1883 if (Subtarget->hasVLX())
1884 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1885 EltVT == MVT::f32 || EltVT == MVT::f64)
1887 case 2: return MVT::v2i1;
1888 case 4: return MVT::v4i1;
1889 case 8: return MVT::v8i1;
1891 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1892 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1894 case 8: return MVT::v8i1;
1895 case 16: return MVT::v16i1;
1896 case 32: return MVT::v32i1;
1900 return VT.changeVectorElementTypeToInteger();
1903 /// Helper for getByValTypeAlignment to determine
1904 /// the desired ByVal argument alignment.
1905 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1908 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1909 if (VTy->getBitWidth() == 128)
1911 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1912 unsigned EltAlign = 0;
1913 getMaxByValAlign(ATy->getElementType(), EltAlign);
1914 if (EltAlign > MaxAlign)
1915 MaxAlign = EltAlign;
1916 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1917 for (auto *EltTy : STy->elements()) {
1918 unsigned EltAlign = 0;
1919 getMaxByValAlign(EltTy, EltAlign);
1920 if (EltAlign > MaxAlign)
1921 MaxAlign = EltAlign;
1928 /// Return the desired alignment for ByVal aggregate
1929 /// function arguments in the caller parameter area. For X86, aggregates
1930 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1931 /// are at 4-byte boundaries.
1932 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1933 const DataLayout &DL) const {
1934 if (Subtarget->is64Bit()) {
1935 // Max of 8 and alignment of type.
1936 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1943 if (Subtarget->hasSSE1())
1944 getMaxByValAlign(Ty, Align);
1948 /// Returns the target specific optimal type for load
1949 /// and store operations as a result of memset, memcpy, and memmove
1950 /// lowering. If DstAlign is zero that means it's safe to destination
1951 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1952 /// means there isn't a need to check it against alignment requirement,
1953 /// probably because the source does not need to be loaded. If 'IsMemset' is
1954 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1955 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1956 /// source is constant so it does not need to be loaded.
1957 /// It returns EVT::Other if the type should be determined using generic
1958 /// target-independent logic.
1960 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1961 unsigned DstAlign, unsigned SrcAlign,
1962 bool IsMemset, bool ZeroMemset,
1964 MachineFunction &MF) const {
1965 const Function *F = MF.getFunction();
1966 if ((!IsMemset || ZeroMemset) &&
1967 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1969 (!Subtarget->isUnalignedMem16Slow() ||
1970 ((DstAlign == 0 || DstAlign >= 16) &&
1971 (SrcAlign == 0 || SrcAlign >= 16)))) {
1973 // FIXME: Check if unaligned 32-byte accesses are slow.
1974 if (Subtarget->hasInt256())
1976 if (Subtarget->hasFp256())
1979 if (Subtarget->hasSSE2())
1981 if (Subtarget->hasSSE1())
1983 } else if (!MemcpyStrSrc && Size >= 8 &&
1984 !Subtarget->is64Bit() &&
1985 Subtarget->hasSSE2()) {
1986 // Do not use f64 to lower memcpy if source is string constant. It's
1987 // better to use i32 to avoid the loads.
1991 // This is a compromise. If we reach here, unaligned accesses may be slow on
1992 // this target. However, creating smaller, aligned accesses could be even
1993 // slower and would certainly be a lot more code.
1994 if (Subtarget->is64Bit() && Size >= 8)
1999 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2001 return X86ScalarSSEf32;
2002 else if (VT == MVT::f64)
2003 return X86ScalarSSEf64;
2008 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2013 switch (VT.getSizeInBits()) {
2015 // 8-byte and under are always assumed to be fast.
2019 *Fast = !Subtarget->isUnalignedMem16Slow();
2022 *Fast = !Subtarget->isUnalignedMem32Slow();
2024 // TODO: What about AVX-512 (512-bit) accesses?
2027 // Misaligned accesses of any size are always allowed.
2031 /// Return the entry encoding for a jump table in the
2032 /// current function. The returned value is a member of the
2033 /// MachineJumpTableInfo::JTEntryKind enum.
2034 unsigned X86TargetLowering::getJumpTableEncoding() const {
2035 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2037 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2038 Subtarget->isPICStyleGOT())
2039 return MachineJumpTableInfo::EK_Custom32;
2041 // Otherwise, use the normal jump table encoding heuristics.
2042 return TargetLowering::getJumpTableEncoding();
2045 bool X86TargetLowering::useSoftFloat() const {
2046 return Subtarget->useSoftFloat();
2050 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2051 const MachineBasicBlock *MBB,
2052 unsigned uid,MCContext &Ctx) const{
2053 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2054 Subtarget->isPICStyleGOT());
2055 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2057 return MCSymbolRefExpr::create(MBB->getSymbol(),
2058 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2061 /// Returns relocation base for the given PIC jumptable.
2062 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2063 SelectionDAG &DAG) const {
2064 if (!Subtarget->is64Bit())
2065 // This doesn't have SDLoc associated with it, but is not really the
2066 // same as a Register.
2067 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2068 getPointerTy(DAG.getDataLayout()));
2072 /// This returns the relocation base for the given PIC jumptable,
2073 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2074 const MCExpr *X86TargetLowering::
2075 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2076 MCContext &Ctx) const {
2077 // X86-64 uses RIP relative addressing based on the jump table label.
2078 if (Subtarget->isPICStyleRIPRel())
2079 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2081 // Otherwise, the reference is relative to the PIC base.
2082 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2085 std::pair<const TargetRegisterClass *, uint8_t>
2086 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2088 const TargetRegisterClass *RRC = nullptr;
2090 switch (VT.SimpleTy) {
2092 return TargetLowering::findRepresentativeClass(TRI, VT);
2093 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2094 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2097 RRC = &X86::VR64RegClass;
2099 case MVT::f32: case MVT::f64:
2100 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2101 case MVT::v4f32: case MVT::v2f64:
2102 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2104 RRC = &X86::VR128RegClass;
2107 return std::make_pair(RRC, Cost);
2110 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2111 unsigned &Offset) const {
2112 if (!Subtarget->isTargetLinux())
2115 if (Subtarget->is64Bit()) {
2116 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2118 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2130 /// Android provides a fixed TLS slot for the SafeStack pointer.
2131 /// See the definition of TLS_SLOT_SAFESTACK in
2132 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2133 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2134 unsigned &Offset) const {
2135 if (!Subtarget->isTargetAndroid())
2138 if (Subtarget->is64Bit()) {
2139 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2141 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2153 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2154 unsigned DestAS) const {
2155 assert(SrcAS != DestAS && "Expected different address spaces!");
2157 return SrcAS < 256 && DestAS < 256;
2160 //===----------------------------------------------------------------------===//
2161 // Return Value Calling Convention Implementation
2162 //===----------------------------------------------------------------------===//
2164 #include "X86GenCallingConv.inc"
2166 bool X86TargetLowering::CanLowerReturn(
2167 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2168 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2169 SmallVector<CCValAssign, 16> RVLocs;
2170 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2171 return CCInfo.CheckReturn(Outs, RetCC_X86);
2174 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2175 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2180 X86TargetLowering::LowerReturn(SDValue Chain,
2181 CallingConv::ID CallConv, bool isVarArg,
2182 const SmallVectorImpl<ISD::OutputArg> &Outs,
2183 const SmallVectorImpl<SDValue> &OutVals,
2184 SDLoc dl, SelectionDAG &DAG) const {
2185 MachineFunction &MF = DAG.getMachineFunction();
2186 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2188 SmallVector<CCValAssign, 16> RVLocs;
2189 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2190 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2193 SmallVector<SDValue, 6> RetOps;
2194 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2195 // Operand #1 = Bytes To Pop
2196 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2199 // Copy the result values into the output registers.
2200 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2201 CCValAssign &VA = RVLocs[i];
2202 assert(VA.isRegLoc() && "Can only return in registers!");
2203 SDValue ValToCopy = OutVals[i];
2204 EVT ValVT = ValToCopy.getValueType();
2206 // Promote values to the appropriate types.
2207 if (VA.getLocInfo() == CCValAssign::SExt)
2208 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2209 else if (VA.getLocInfo() == CCValAssign::ZExt)
2210 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2211 else if (VA.getLocInfo() == CCValAssign::AExt) {
2212 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2213 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2215 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2217 else if (VA.getLocInfo() == CCValAssign::BCvt)
2218 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2220 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2221 "Unexpected FP-extend for return value.");
2223 // If this is x86-64, and we disabled SSE, we can't return FP values,
2224 // or SSE or MMX vectors.
2225 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2226 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2227 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2228 report_fatal_error("SSE register return with SSE disabled");
2230 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2231 // llvm-gcc has never done it right and no one has noticed, so this
2232 // should be OK for now.
2233 if (ValVT == MVT::f64 &&
2234 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2235 report_fatal_error("SSE2 register return with SSE2 disabled");
2237 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2238 // the RET instruction and handled by the FP Stackifier.
2239 if (VA.getLocReg() == X86::FP0 ||
2240 VA.getLocReg() == X86::FP1) {
2241 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2242 // change the value to the FP stack register class.
2243 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2244 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2245 RetOps.push_back(ValToCopy);
2246 // Don't emit a copytoreg.
2250 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2251 // which is returned in RAX / RDX.
2252 if (Subtarget->is64Bit()) {
2253 if (ValVT == MVT::x86mmx) {
2254 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2255 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2256 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2258 // If we don't have SSE2 available, convert to v4f32 so the generated
2259 // register is legal.
2260 if (!Subtarget->hasSSE2())
2261 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2266 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2267 Flag = Chain.getValue(1);
2268 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2271 // All x86 ABIs require that for returning structs by value we copy
2272 // the sret argument into %rax/%eax (depending on ABI) for the return.
2273 // We saved the argument into a virtual register in the entry block,
2274 // so now we copy the value out and into %rax/%eax.
2276 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2277 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2278 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2279 // either case FuncInfo->setSRetReturnReg() will have been called.
2280 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2281 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2282 getPointerTy(MF.getDataLayout()));
2285 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2286 X86::RAX : X86::EAX;
2287 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2288 Flag = Chain.getValue(1);
2290 // RAX/EAX now acts like a return value.
2292 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2295 RetOps[0] = Chain; // Update chain.
2297 // Add the flag if we have it.
2299 RetOps.push_back(Flag);
2301 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2304 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2305 if (N->getNumValues() != 1)
2307 if (!N->hasNUsesOfValue(1, 0))
2310 SDValue TCChain = Chain;
2311 SDNode *Copy = *N->use_begin();
2312 if (Copy->getOpcode() == ISD::CopyToReg) {
2313 // If the copy has a glue operand, we conservatively assume it isn't safe to
2314 // perform a tail call.
2315 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2317 TCChain = Copy->getOperand(0);
2318 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2321 bool HasRet = false;
2322 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2324 if (UI->getOpcode() != X86ISD::RET_FLAG)
2326 // If we are returning more than one value, we can definitely
2327 // not make a tail call see PR19530
2328 if (UI->getNumOperands() > 4)
2330 if (UI->getNumOperands() == 4 &&
2331 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2344 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2345 ISD::NodeType ExtendKind) const {
2347 // TODO: Is this also valid on 32-bit?
2348 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2349 ReturnMVT = MVT::i8;
2351 ReturnMVT = MVT::i32;
2353 EVT MinVT = getRegisterType(Context, ReturnMVT);
2354 return VT.bitsLT(MinVT) ? MinVT : VT;
2357 /// Lower the result values of a call into the
2358 /// appropriate copies out of appropriate physical registers.
2361 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2362 CallingConv::ID CallConv, bool isVarArg,
2363 const SmallVectorImpl<ISD::InputArg> &Ins,
2364 SDLoc dl, SelectionDAG &DAG,
2365 SmallVectorImpl<SDValue> &InVals) const {
2367 // Assign locations to each value returned by this call.
2368 SmallVector<CCValAssign, 16> RVLocs;
2369 bool Is64Bit = Subtarget->is64Bit();
2370 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2372 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2374 // Copy all of the result registers out of their specified physreg.
2375 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2376 CCValAssign &VA = RVLocs[i];
2377 EVT CopyVT = VA.getLocVT();
2379 // If this is x86-64, and we disabled SSE, we can't return FP values
2380 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2381 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2382 report_fatal_error("SSE register return with SSE disabled");
2385 // If we prefer to use the value in xmm registers, copy it out as f80 and
2386 // use a truncate to move it from fp stack reg to xmm reg.
2387 bool RoundAfterCopy = false;
2388 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2389 isScalarFPTypeInSSEReg(VA.getValVT())) {
2391 RoundAfterCopy = (CopyVT != VA.getLocVT());
2394 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2395 CopyVT, InFlag).getValue(1);
2396 SDValue Val = Chain.getValue(0);
2399 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2400 // This truncation won't change the value.
2401 DAG.getIntPtrConstant(1, dl));
2403 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2404 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2406 InFlag = Chain.getValue(2);
2407 InVals.push_back(Val);
2413 //===----------------------------------------------------------------------===//
2414 // C & StdCall & Fast Calling Convention implementation
2415 //===----------------------------------------------------------------------===//
2416 // StdCall calling convention seems to be standard for many Windows' API
2417 // routines and around. It differs from C calling convention just a little:
2418 // callee should clean up the stack, not caller. Symbols should be also
2419 // decorated in some fancy way :) It doesn't support any vector arguments.
2420 // For info on fast calling convention see Fast Calling Convention (tail call)
2421 // implementation LowerX86_32FastCCCallTo.
2423 /// CallIsStructReturn - Determines whether a call uses struct return
2425 enum StructReturnType {
2430 static StructReturnType
2431 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2433 return NotStructReturn;
2435 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2436 if (!Flags.isSRet())
2437 return NotStructReturn;
2438 if (Flags.isInReg())
2439 return RegStructReturn;
2440 return StackStructReturn;
2443 /// Determines whether a function uses struct return semantics.
2444 static StructReturnType
2445 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2447 return NotStructReturn;
2449 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2450 if (!Flags.isSRet())
2451 return NotStructReturn;
2452 if (Flags.isInReg())
2453 return RegStructReturn;
2454 return StackStructReturn;
2457 /// Make a copy of an aggregate at address specified by "Src" to address
2458 /// "Dst" with size and alignment information specified by the specific
2459 /// parameter attribute. The copy will be passed as a byval function parameter.
2461 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2462 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2464 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2466 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2467 /*isVolatile*/false, /*AlwaysInline=*/true,
2468 /*isTailCall*/false,
2469 MachinePointerInfo(), MachinePointerInfo());
2472 /// Return true if the calling convention is one that we can guarantee TCO for.
2473 static bool canGuaranteeTCO(CallingConv::ID CC) {
2474 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2475 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2478 /// \brief Return true if the calling convention is a C calling convention.
2479 static bool isCCallConvention(CallingConv::ID CC) {
2480 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2481 CC == CallingConv::X86_64_SysV);
2484 /// Return true if we might ever do TCO for calls with this calling convention.
2485 static bool mayTailCallThisCC(CallingConv::ID CC) {
2486 return isCCallConvention(CC) || canGuaranteeTCO(CC);
2489 /// Return true if the function is being made into a tailcall target by
2490 /// changing its ABI.
2491 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2492 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2495 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2497 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2498 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2502 CallingConv::ID CalleeCC = CS.getCallingConv();
2503 if (!mayTailCallThisCC(CalleeCC))
2510 X86TargetLowering::LowerMemArgument(SDValue Chain,
2511 CallingConv::ID CallConv,
2512 const SmallVectorImpl<ISD::InputArg> &Ins,
2513 SDLoc dl, SelectionDAG &DAG,
2514 const CCValAssign &VA,
2515 MachineFrameInfo *MFI,
2517 // Create the nodes corresponding to a load from this parameter slot.
2518 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2519 bool AlwaysUseMutable = shouldGuaranteeTCO(
2520 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2521 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2524 // If value is passed by pointer we have address passed instead of the value
2526 bool ExtendedInMem = VA.isExtInLoc() &&
2527 VA.getValVT().getScalarType() == MVT::i1;
2529 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2530 ValVT = VA.getLocVT();
2532 ValVT = VA.getValVT();
2534 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2535 // changed with more analysis.
2536 // In case of tail call optimization mark all arguments mutable. Since they
2537 // could be overwritten by lowering of arguments in case of a tail call.
2538 if (Flags.isByVal()) {
2539 unsigned Bytes = Flags.getByValSize();
2540 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2541 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2542 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2544 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2545 VA.getLocMemOffset(), isImmutable);
2546 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2547 SDValue Val = DAG.getLoad(
2548 ValVT, dl, Chain, FIN,
2549 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2551 return ExtendedInMem ?
2552 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2556 // FIXME: Get this from tablegen.
2557 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2558 const X86Subtarget *Subtarget) {
2559 assert(Subtarget->is64Bit());
2561 if (Subtarget->isCallingConvWin64(CallConv)) {
2562 static const MCPhysReg GPR64ArgRegsWin64[] = {
2563 X86::RCX, X86::RDX, X86::R8, X86::R9
2565 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2568 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2569 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2571 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2574 // FIXME: Get this from tablegen.
2575 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2576 CallingConv::ID CallConv,
2577 const X86Subtarget *Subtarget) {
2578 assert(Subtarget->is64Bit());
2579 if (Subtarget->isCallingConvWin64(CallConv)) {
2580 // The XMM registers which might contain var arg parameters are shadowed
2581 // in their paired GPR. So we only need to save the GPR to their home
2583 // TODO: __vectorcall will change this.
2587 const Function *Fn = MF.getFunction();
2588 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2589 bool isSoftFloat = Subtarget->useSoftFloat();
2590 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2591 "SSE register cannot be used when SSE is disabled!");
2592 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2593 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2597 static const MCPhysReg XMMArgRegs64Bit[] = {
2598 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2599 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2601 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2604 SDValue X86TargetLowering::LowerFormalArguments(
2605 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2606 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2607 SmallVectorImpl<SDValue> &InVals) const {
2608 MachineFunction &MF = DAG.getMachineFunction();
2609 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2610 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2612 const Function* Fn = MF.getFunction();
2613 if (Fn->hasExternalLinkage() &&
2614 Subtarget->isTargetCygMing() &&
2615 Fn->getName() == "main")
2616 FuncInfo->setForceFramePointer(true);
2618 MachineFrameInfo *MFI = MF.getFrameInfo();
2619 bool Is64Bit = Subtarget->is64Bit();
2620 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2622 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2623 "Var args not supported with calling convention fastcc, ghc or hipe");
2625 // Assign locations to all of the incoming arguments.
2626 SmallVector<CCValAssign, 16> ArgLocs;
2627 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2629 // Allocate shadow area for Win64
2631 CCInfo.AllocateStack(32, 8);
2633 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2635 unsigned LastVal = ~0U;
2637 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2638 CCValAssign &VA = ArgLocs[i];
2639 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2641 assert(VA.getValNo() != LastVal &&
2642 "Don't support value assigned to multiple locs yet");
2644 LastVal = VA.getValNo();
2646 if (VA.isRegLoc()) {
2647 EVT RegVT = VA.getLocVT();
2648 const TargetRegisterClass *RC;
2649 if (RegVT == MVT::i32)
2650 RC = &X86::GR32RegClass;
2651 else if (Is64Bit && RegVT == MVT::i64)
2652 RC = &X86::GR64RegClass;
2653 else if (RegVT == MVT::f32)
2654 RC = &X86::FR32RegClass;
2655 else if (RegVT == MVT::f64)
2656 RC = &X86::FR64RegClass;
2657 else if (RegVT.is512BitVector())
2658 RC = &X86::VR512RegClass;
2659 else if (RegVT.is256BitVector())
2660 RC = &X86::VR256RegClass;
2661 else if (RegVT.is128BitVector())
2662 RC = &X86::VR128RegClass;
2663 else if (RegVT == MVT::x86mmx)
2664 RC = &X86::VR64RegClass;
2665 else if (RegVT == MVT::i1)
2666 RC = &X86::VK1RegClass;
2667 else if (RegVT == MVT::v8i1)
2668 RC = &X86::VK8RegClass;
2669 else if (RegVT == MVT::v16i1)
2670 RC = &X86::VK16RegClass;
2671 else if (RegVT == MVT::v32i1)
2672 RC = &X86::VK32RegClass;
2673 else if (RegVT == MVT::v64i1)
2674 RC = &X86::VK64RegClass;
2676 llvm_unreachable("Unknown argument type!");
2678 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2679 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2681 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2682 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2684 if (VA.getLocInfo() == CCValAssign::SExt)
2685 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2686 DAG.getValueType(VA.getValVT()));
2687 else if (VA.getLocInfo() == CCValAssign::ZExt)
2688 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2689 DAG.getValueType(VA.getValVT()));
2690 else if (VA.getLocInfo() == CCValAssign::BCvt)
2691 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2693 if (VA.isExtInLoc()) {
2694 // Handle MMX values passed in XMM regs.
2695 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2696 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2698 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2701 assert(VA.isMemLoc());
2702 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2705 // If value is passed via pointer - do a load.
2706 if (VA.getLocInfo() == CCValAssign::Indirect)
2707 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2708 MachinePointerInfo(), false, false, false, 0);
2710 InVals.push_back(ArgValue);
2713 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2714 // All x86 ABIs require that for returning structs by value we copy the
2715 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2716 // the argument into a virtual register so that we can access it from the
2718 if (Ins[i].Flags.isSRet()) {
2719 unsigned Reg = FuncInfo->getSRetReturnReg();
2721 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2722 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2723 FuncInfo->setSRetReturnReg(Reg);
2725 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2726 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2731 unsigned StackSize = CCInfo.getNextStackOffset();
2732 // Align stack specially for tail calls.
2733 if (shouldGuaranteeTCO(CallConv,
2734 MF.getTarget().Options.GuaranteedTailCallOpt))
2735 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2737 // If the function takes variable number of arguments, make a frame index for
2738 // the start of the first vararg value... for expansion of llvm.va_start. We
2739 // can skip this if there are no va_start calls.
2740 if (MFI->hasVAStart() &&
2741 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2742 CallConv != CallingConv::X86_ThisCall))) {
2743 FuncInfo->setVarArgsFrameIndex(
2744 MFI->CreateFixedObject(1, StackSize, true));
2747 MachineModuleInfo &MMI = MF.getMMI();
2749 // Figure out if XMM registers are in use.
2750 assert(!(Subtarget->useSoftFloat() &&
2751 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2752 "SSE register cannot be used when SSE is disabled!");
2754 // 64-bit calling conventions support varargs and register parameters, so we
2755 // have to do extra work to spill them in the prologue.
2756 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2757 // Find the first unallocated argument registers.
2758 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2759 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2760 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2761 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2762 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2763 "SSE register cannot be used when SSE is disabled!");
2765 // Gather all the live in physical registers.
2766 SmallVector<SDValue, 6> LiveGPRs;
2767 SmallVector<SDValue, 8> LiveXMMRegs;
2769 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2770 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2772 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2774 if (!ArgXMMs.empty()) {
2775 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2776 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2777 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2778 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2779 LiveXMMRegs.push_back(
2780 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2785 // Get to the caller-allocated home save location. Add 8 to account
2786 // for the return address.
2787 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2788 FuncInfo->setRegSaveFrameIndex(
2789 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2790 // Fixup to set vararg frame on shadow area (4 x i64).
2792 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2794 // For X86-64, if there are vararg parameters that are passed via
2795 // registers, then we must store them to their spots on the stack so
2796 // they may be loaded by deferencing the result of va_next.
2797 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2798 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2799 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2800 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2803 // Store the integer parameter registers.
2804 SmallVector<SDValue, 8> MemOps;
2805 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2806 getPointerTy(DAG.getDataLayout()));
2807 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2808 for (SDValue Val : LiveGPRs) {
2809 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2810 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2812 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2813 MachinePointerInfo::getFixedStack(
2814 DAG.getMachineFunction(),
2815 FuncInfo->getRegSaveFrameIndex(), Offset),
2817 MemOps.push_back(Store);
2821 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2822 // Now store the XMM (fp + vector) parameter registers.
2823 SmallVector<SDValue, 12> SaveXMMOps;
2824 SaveXMMOps.push_back(Chain);
2825 SaveXMMOps.push_back(ALVal);
2826 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2827 FuncInfo->getRegSaveFrameIndex(), dl));
2828 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2829 FuncInfo->getVarArgsFPOffset(), dl));
2830 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2832 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2833 MVT::Other, SaveXMMOps));
2836 if (!MemOps.empty())
2837 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2840 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2841 // Find the largest legal vector type.
2842 MVT VecVT = MVT::Other;
2843 // FIXME: Only some x86_32 calling conventions support AVX512.
2844 if (Subtarget->hasAVX512() &&
2845 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2846 CallConv == CallingConv::Intel_OCL_BI)))
2847 VecVT = MVT::v16f32;
2848 else if (Subtarget->hasAVX())
2850 else if (Subtarget->hasSSE2())
2853 // We forward some GPRs and some vector types.
2854 SmallVector<MVT, 2> RegParmTypes;
2855 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2856 RegParmTypes.push_back(IntVT);
2857 if (VecVT != MVT::Other)
2858 RegParmTypes.push_back(VecVT);
2860 // Compute the set of forwarded registers. The rest are scratch.
2861 SmallVectorImpl<ForwardedRegister> &Forwards =
2862 FuncInfo->getForwardedMustTailRegParms();
2863 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2865 // Conservatively forward AL on x86_64, since it might be used for varargs.
2866 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2867 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2868 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2871 // Copy all forwards from physical to virtual registers.
2872 for (ForwardedRegister &F : Forwards) {
2873 // FIXME: Can we use a less constrained schedule?
2874 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2875 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2876 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2880 // Some CCs need callee pop.
2881 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2882 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2883 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2885 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2886 // If this is an sret function, the return should pop the hidden pointer.
2887 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2888 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2889 argsAreStructReturn(Ins) == StackStructReturn)
2890 FuncInfo->setBytesToPopOnReturn(4);
2894 // RegSaveFrameIndex is X86-64 only.
2895 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2896 if (CallConv == CallingConv::X86_FastCall ||
2897 CallConv == CallingConv::X86_ThisCall)
2898 // fastcc functions can't have varargs.
2899 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2902 FuncInfo->setArgumentStackSize(StackSize);
2904 if (MMI.hasWinEHFuncInfo(Fn)) {
2906 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2907 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2908 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2909 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2910 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2911 MachinePointerInfo::getFixedStack(
2912 DAG.getMachineFunction(), UnwindHelpFI),
2913 /*isVolatile=*/true,
2914 /*isNonTemporal=*/false, /*Alignment=*/0);
2916 // Functions using Win32 EH are considered to have opaque SP adjustments
2917 // to force local variables to be addressed from the frame or base
2919 MFI->setHasOpaqueSPAdjustment(true);
2927 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2928 SDValue StackPtr, SDValue Arg,
2929 SDLoc dl, SelectionDAG &DAG,
2930 const CCValAssign &VA,
2931 ISD::ArgFlagsTy Flags) const {
2932 unsigned LocMemOffset = VA.getLocMemOffset();
2933 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2934 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2936 if (Flags.isByVal())
2937 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2939 return DAG.getStore(
2940 Chain, dl, Arg, PtrOff,
2941 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2945 /// Emit a load of return address if tail call
2946 /// optimization is performed and it is required.
2948 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2949 SDValue &OutRetAddr, SDValue Chain,
2950 bool IsTailCall, bool Is64Bit,
2951 int FPDiff, SDLoc dl) const {
2952 // Adjust the Return address stack slot.
2953 EVT VT = getPointerTy(DAG.getDataLayout());
2954 OutRetAddr = getReturnAddressFrameIndex(DAG);
2956 // Load the "old" Return address.
2957 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2958 false, false, false, 0);
2959 return SDValue(OutRetAddr.getNode(), 1);
2962 /// Emit a store of the return address if tail call
2963 /// optimization is performed and it is required (FPDiff!=0).
2964 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2965 SDValue Chain, SDValue RetAddrFrIdx,
2966 EVT PtrVT, unsigned SlotSize,
2967 int FPDiff, SDLoc dl) {
2968 // Store the return address to the appropriate stack slot.
2969 if (!FPDiff) return Chain;
2970 // Calculate the new stack slot for the return address.
2971 int NewReturnAddrFI =
2972 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2974 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2975 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2976 MachinePointerInfo::getFixedStack(
2977 DAG.getMachineFunction(), NewReturnAddrFI),
2982 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2983 /// operation of specified width.
2984 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2986 unsigned NumElems = VT.getVectorNumElements();
2987 SmallVector<int, 8> Mask;
2988 Mask.push_back(NumElems);
2989 for (unsigned i = 1; i != NumElems; ++i)
2991 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2995 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2996 SmallVectorImpl<SDValue> &InVals) const {
2997 SelectionDAG &DAG = CLI.DAG;
2999 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3000 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3001 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3002 SDValue Chain = CLI.Chain;
3003 SDValue Callee = CLI.Callee;
3004 CallingConv::ID CallConv = CLI.CallConv;
3005 bool &isTailCall = CLI.IsTailCall;
3006 bool isVarArg = CLI.IsVarArg;
3008 MachineFunction &MF = DAG.getMachineFunction();
3009 bool Is64Bit = Subtarget->is64Bit();
3010 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3011 StructReturnType SR = callIsStructReturn(Outs);
3012 bool IsSibcall = false;
3013 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3014 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3016 if (Attr.getValueAsString() == "true")
3019 if (Subtarget->isPICStyleGOT() &&
3020 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3021 // If we are using a GOT, disable tail calls to external symbols with
3022 // default visibility. Tail calling such a symbol requires using a GOT
3023 // relocation, which forces early binding of the symbol. This breaks code
3024 // that require lazy function symbol resolution. Using musttail or
3025 // GuaranteedTailCallOpt will override this.
3026 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3027 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3028 G->getGlobal()->hasDefaultVisibility()))
3032 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3034 // Force this to be a tail call. The verifier rules are enough to ensure
3035 // that we can lower this successfully without moving the return address
3038 } else if (isTailCall) {
3039 // Check if it's really possible to do a tail call.
3040 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3041 isVarArg, SR != NotStructReturn,
3042 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3043 Outs, OutVals, Ins, DAG);
3045 // Sibcalls are automatically detected tailcalls which do not require
3047 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3054 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3055 "Var args not supported with calling convention fastcc, ghc or hipe");
3057 // Analyze operands of the call, assigning locations to each operand.
3058 SmallVector<CCValAssign, 16> ArgLocs;
3059 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3061 // Allocate shadow area for Win64
3063 CCInfo.AllocateStack(32, 8);
3065 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3067 // Get a count of how many bytes are to be pushed on the stack.
3068 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3070 // This is a sibcall. The memory operands are available in caller's
3071 // own caller's stack.
3073 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3074 canGuaranteeTCO(CallConv))
3075 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3078 if (isTailCall && !IsSibcall && !IsMustTail) {
3079 // Lower arguments at fp - stackoffset + fpdiff.
3080 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3082 FPDiff = NumBytesCallerPushed - NumBytes;
3084 // Set the delta of movement of the returnaddr stackslot.
3085 // But only set if delta is greater than previous delta.
3086 if (FPDiff < X86Info->getTCReturnAddrDelta())
3087 X86Info->setTCReturnAddrDelta(FPDiff);
3090 unsigned NumBytesToPush = NumBytes;
3091 unsigned NumBytesToPop = NumBytes;
3093 // If we have an inalloca argument, all stack space has already been allocated
3094 // for us and be right at the top of the stack. We don't support multiple
3095 // arguments passed in memory when using inalloca.
3096 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3098 if (!ArgLocs.back().isMemLoc())
3099 report_fatal_error("cannot use inalloca attribute on a register "
3101 if (ArgLocs.back().getLocMemOffset() != 0)
3102 report_fatal_error("any parameter with the inalloca attribute must be "
3103 "the only memory argument");
3107 Chain = DAG.getCALLSEQ_START(
3108 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3110 SDValue RetAddrFrIdx;
3111 // Load return address for tail calls.
3112 if (isTailCall && FPDiff)
3113 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3114 Is64Bit, FPDiff, dl);
3116 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3117 SmallVector<SDValue, 8> MemOpChains;
3120 // Walk the register/memloc assignments, inserting copies/loads. In the case
3121 // of tail call optimization arguments are handle later.
3122 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3123 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3124 // Skip inalloca arguments, they have already been written.
3125 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3126 if (Flags.isInAlloca())
3129 CCValAssign &VA = ArgLocs[i];
3130 EVT RegVT = VA.getLocVT();
3131 SDValue Arg = OutVals[i];
3132 bool isByVal = Flags.isByVal();
3134 // Promote the value if needed.
3135 switch (VA.getLocInfo()) {
3136 default: llvm_unreachable("Unknown loc info!");
3137 case CCValAssign::Full: break;
3138 case CCValAssign::SExt:
3139 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3141 case CCValAssign::ZExt:
3142 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3144 case CCValAssign::AExt:
3145 if (Arg.getValueType().isVector() &&
3146 Arg.getValueType().getScalarType() == MVT::i1)
3147 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3148 else if (RegVT.is128BitVector()) {
3149 // Special case: passing MMX values in XMM registers.
3150 Arg = DAG.getBitcast(MVT::i64, Arg);
3151 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3152 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3154 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3156 case CCValAssign::BCvt:
3157 Arg = DAG.getBitcast(RegVT, Arg);
3159 case CCValAssign::Indirect: {
3160 // Store the argument.
3161 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3162 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3163 Chain = DAG.getStore(
3164 Chain, dl, Arg, SpillSlot,
3165 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3172 if (VA.isRegLoc()) {
3173 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3174 if (isVarArg && IsWin64) {
3175 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3176 // shadow reg if callee is a varargs function.
3177 unsigned ShadowReg = 0;
3178 switch (VA.getLocReg()) {
3179 case X86::XMM0: ShadowReg = X86::RCX; break;
3180 case X86::XMM1: ShadowReg = X86::RDX; break;
3181 case X86::XMM2: ShadowReg = X86::R8; break;
3182 case X86::XMM3: ShadowReg = X86::R9; break;
3185 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3187 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3188 assert(VA.isMemLoc());
3189 if (!StackPtr.getNode())
3190 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3191 getPointerTy(DAG.getDataLayout()));
3192 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3193 dl, DAG, VA, Flags));
3197 if (!MemOpChains.empty())
3198 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3200 if (Subtarget->isPICStyleGOT()) {
3201 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3204 RegsToPass.push_back(std::make_pair(
3205 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3206 getPointerTy(DAG.getDataLayout()))));
3208 // If we are tail calling and generating PIC/GOT style code load the
3209 // address of the callee into ECX. The value in ecx is used as target of
3210 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3211 // for tail calls on PIC/GOT architectures. Normally we would just put the
3212 // address of GOT into ebx and then call target@PLT. But for tail calls
3213 // ebx would be restored (since ebx is callee saved) before jumping to the
3216 // Note: The actual moving to ECX is done further down.
3217 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3218 if (G && !G->getGlobal()->hasLocalLinkage() &&
3219 G->getGlobal()->hasDefaultVisibility())
3220 Callee = LowerGlobalAddress(Callee, DAG);
3221 else if (isa<ExternalSymbolSDNode>(Callee))
3222 Callee = LowerExternalSymbol(Callee, DAG);
3226 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3227 // From AMD64 ABI document:
3228 // For calls that may call functions that use varargs or stdargs
3229 // (prototype-less calls or calls to functions containing ellipsis (...) in
3230 // the declaration) %al is used as hidden argument to specify the number
3231 // of SSE registers used. The contents of %al do not need to match exactly
3232 // the number of registers, but must be an ubound on the number of SSE
3233 // registers used and is in the range 0 - 8 inclusive.
3235 // Count the number of XMM registers allocated.
3236 static const MCPhysReg XMMArgRegs[] = {
3237 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3238 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3240 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3241 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3242 && "SSE registers cannot be used when SSE is disabled");
3244 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3245 DAG.getConstant(NumXMMRegs, dl,
3249 if (isVarArg && IsMustTail) {
3250 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3251 for (const auto &F : Forwards) {
3252 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3253 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3257 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3258 // don't need this because the eligibility check rejects calls that require
3259 // shuffling arguments passed in memory.
3260 if (!IsSibcall && isTailCall) {
3261 // Force all the incoming stack arguments to be loaded from the stack
3262 // before any new outgoing arguments are stored to the stack, because the
3263 // outgoing stack slots may alias the incoming argument stack slots, and
3264 // the alias isn't otherwise explicit. This is slightly more conservative
3265 // than necessary, because it means that each store effectively depends
3266 // on every argument instead of just those arguments it would clobber.
3267 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3269 SmallVector<SDValue, 8> MemOpChains2;
3272 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3273 CCValAssign &VA = ArgLocs[i];
3276 assert(VA.isMemLoc());
3277 SDValue Arg = OutVals[i];
3278 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3279 // Skip inalloca arguments. They don't require any work.
3280 if (Flags.isInAlloca())
3282 // Create frame index.
3283 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3284 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3285 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3286 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3288 if (Flags.isByVal()) {
3289 // Copy relative to framepointer.
3290 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3291 if (!StackPtr.getNode())
3292 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3293 getPointerTy(DAG.getDataLayout()));
3294 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3297 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3301 // Store relative to framepointer.
3302 MemOpChains2.push_back(DAG.getStore(
3303 ArgChain, dl, Arg, FIN,
3304 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3309 if (!MemOpChains2.empty())
3310 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3312 // Store the return address to the appropriate stack slot.
3313 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3314 getPointerTy(DAG.getDataLayout()),
3315 RegInfo->getSlotSize(), FPDiff, dl);
3318 // Build a sequence of copy-to-reg nodes chained together with token chain
3319 // and flag operands which copy the outgoing args into registers.
3321 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3322 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3323 RegsToPass[i].second, InFlag);
3324 InFlag = Chain.getValue(1);
3327 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3328 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3329 // In the 64-bit large code model, we have to make all calls
3330 // through a register, since the call instruction's 32-bit
3331 // pc-relative offset may not be large enough to hold the whole
3333 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3334 // If the callee is a GlobalAddress node (quite common, every direct call
3335 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3337 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3339 // We should use extra load for direct calls to dllimported functions in
3341 const GlobalValue *GV = G->getGlobal();
3342 if (!GV->hasDLLImportStorageClass()) {
3343 unsigned char OpFlags = 0;
3344 bool ExtraLoad = false;
3345 unsigned WrapperKind = ISD::DELETED_NODE;
3347 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3348 // external symbols most go through the PLT in PIC mode. If the symbol
3349 // has hidden or protected visibility, or if it is static or local, then
3350 // we don't need to use the PLT - we can directly call it.
3351 if (Subtarget->isTargetELF() &&
3352 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3353 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3354 OpFlags = X86II::MO_PLT;
3355 } else if (Subtarget->isPICStyleStubAny() &&
3356 !GV->isStrongDefinitionForLinker() &&
3357 (!Subtarget->getTargetTriple().isMacOSX() ||
3358 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3359 // PC-relative references to external symbols should go through $stub,
3360 // unless we're building with the leopard linker or later, which
3361 // automatically synthesizes these stubs.
3362 OpFlags = X86II::MO_DARWIN_STUB;
3363 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3364 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3365 // If the function is marked as non-lazy, generate an indirect call
3366 // which loads from the GOT directly. This avoids runtime overhead
3367 // at the cost of eager binding (and one extra byte of encoding).
3368 OpFlags = X86II::MO_GOTPCREL;
3369 WrapperKind = X86ISD::WrapperRIP;
3373 Callee = DAG.getTargetGlobalAddress(
3374 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3376 // Add a wrapper if needed.
3377 if (WrapperKind != ISD::DELETED_NODE)
3378 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3379 getPointerTy(DAG.getDataLayout()), Callee);
3380 // Add extra indirection if needed.
3382 Callee = DAG.getLoad(
3383 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3384 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3387 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3388 unsigned char OpFlags = 0;
3390 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3391 // external symbols should go through the PLT.
3392 if (Subtarget->isTargetELF() &&
3393 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3394 OpFlags = X86II::MO_PLT;
3395 } else if (Subtarget->isPICStyleStubAny() &&
3396 (!Subtarget->getTargetTriple().isMacOSX() ||
3397 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3398 // PC-relative references to external symbols should go through $stub,
3399 // unless we're building with the leopard linker or later, which
3400 // automatically synthesizes these stubs.
3401 OpFlags = X86II::MO_DARWIN_STUB;
3404 Callee = DAG.getTargetExternalSymbol(
3405 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3406 } else if (Subtarget->isTarget64BitILP32() &&
3407 Callee->getValueType(0) == MVT::i32) {
3408 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3409 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3412 // Returns a chain & a flag for retval copy to use.
3413 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3414 SmallVector<SDValue, 8> Ops;
3416 if (!IsSibcall && isTailCall) {
3417 Chain = DAG.getCALLSEQ_END(Chain,
3418 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3419 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3420 InFlag = Chain.getValue(1);
3423 Ops.push_back(Chain);
3424 Ops.push_back(Callee);
3427 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3429 // Add argument registers to the end of the list so that they are known live
3431 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3432 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3433 RegsToPass[i].second.getValueType()));
3435 // Add a register mask operand representing the call-preserved registers.
3436 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3437 assert(Mask && "Missing call preserved mask for calling convention");
3439 // If this is an invoke in a 32-bit function using a funclet-based
3440 // personality, assume the function clobbers all registers. If an exception
3441 // is thrown, the runtime will not restore CSRs.
3442 // FIXME: Model this more precisely so that we can register allocate across
3443 // the normal edge and spill and fill across the exceptional edge.
3444 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3445 const Function *CallerFn = MF.getFunction();
3446 EHPersonality Pers =
3447 CallerFn->hasPersonalityFn()
3448 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3449 : EHPersonality::Unknown;
3450 if (isFuncletEHPersonality(Pers))
3451 Mask = RegInfo->getNoPreservedMask();
3454 Ops.push_back(DAG.getRegisterMask(Mask));
3456 if (InFlag.getNode())
3457 Ops.push_back(InFlag);
3461 //// If this is the first return lowered for this function, add the regs
3462 //// to the liveout set for the function.
3463 // This isn't right, although it's probably harmless on x86; liveouts
3464 // should be computed from returns not tail calls. Consider a void
3465 // function making a tail call to a function returning int.
3466 MF.getFrameInfo()->setHasTailCall();
3467 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3470 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3471 InFlag = Chain.getValue(1);
3473 // Create the CALLSEQ_END node.
3474 unsigned NumBytesForCalleeToPop;
3475 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3476 DAG.getTarget().Options.GuaranteedTailCallOpt))
3477 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3478 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3479 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3480 SR == StackStructReturn)
3481 // If this is a call to a struct-return function, the callee
3482 // pops the hidden struct pointer, so we have to push it back.
3483 // This is common for Darwin/X86, Linux & Mingw32 targets.
3484 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3485 NumBytesForCalleeToPop = 4;
3487 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3489 // Returns a flag for retval copy to use.
3491 Chain = DAG.getCALLSEQ_END(Chain,
3492 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3493 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3496 InFlag = Chain.getValue(1);
3499 // Handle result values, copying them out of physregs into vregs that we
3501 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3502 Ins, dl, DAG, InVals);
3505 //===----------------------------------------------------------------------===//
3506 // Fast Calling Convention (tail call) implementation
3507 //===----------------------------------------------------------------------===//
3509 // Like std call, callee cleans arguments, convention except that ECX is
3510 // reserved for storing the tail called function address. Only 2 registers are
3511 // free for argument passing (inreg). Tail call optimization is performed
3513 // * tailcallopt is enabled
3514 // * caller/callee are fastcc
3515 // On X86_64 architecture with GOT-style position independent code only local
3516 // (within module) calls are supported at the moment.
3517 // To keep the stack aligned according to platform abi the function
3518 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3519 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3520 // If a tail called function callee has more arguments than the caller the
3521 // caller needs to make sure that there is room to move the RETADDR to. This is
3522 // achieved by reserving an area the size of the argument delta right after the
3523 // original RETADDR, but before the saved framepointer or the spilled registers
3524 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3536 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3539 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3540 SelectionDAG& DAG) const {
3541 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3542 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3543 unsigned StackAlignment = TFI.getStackAlignment();
3544 uint64_t AlignMask = StackAlignment - 1;
3545 int64_t Offset = StackSize;
3546 unsigned SlotSize = RegInfo->getSlotSize();
3547 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3548 // Number smaller than 12 so just add the difference.
3549 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3551 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3552 Offset = ((~AlignMask) & Offset) + StackAlignment +
3553 (StackAlignment-SlotSize);
3558 /// Return true if the given stack call argument is already available in the
3559 /// same position (relatively) of the caller's incoming argument stack.
3561 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3562 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3563 const X86InstrInfo *TII) {
3564 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3566 if (Arg.getOpcode() == ISD::CopyFromReg) {
3567 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3568 if (!TargetRegisterInfo::isVirtualRegister(VR))
3570 MachineInstr *Def = MRI->getVRegDef(VR);
3573 if (!Flags.isByVal()) {
3574 if (!TII->isLoadFromStackSlot(Def, FI))
3577 unsigned Opcode = Def->getOpcode();
3578 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3579 Opcode == X86::LEA64_32r) &&
3580 Def->getOperand(1).isFI()) {
3581 FI = Def->getOperand(1).getIndex();
3582 Bytes = Flags.getByValSize();
3586 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3587 if (Flags.isByVal())
3588 // ByVal argument is passed in as a pointer but it's now being
3589 // dereferenced. e.g.
3590 // define @foo(%struct.X* %A) {
3591 // tail call @bar(%struct.X* byval %A)
3594 SDValue Ptr = Ld->getBasePtr();
3595 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3598 FI = FINode->getIndex();
3599 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3600 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3601 FI = FINode->getIndex();
3602 Bytes = Flags.getByValSize();
3606 assert(FI != INT_MAX);
3607 if (!MFI->isFixedObjectIndex(FI))
3609 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3612 /// Check whether the call is eligible for tail call optimization. Targets
3613 /// that want to do tail call optimization should implement this function.
3614 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3615 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3616 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3617 const SmallVectorImpl<ISD::OutputArg> &Outs,
3618 const SmallVectorImpl<SDValue> &OutVals,
3619 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3620 if (!mayTailCallThisCC(CalleeCC))
3623 // If -tailcallopt is specified, make fastcc functions tail-callable.
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const Function *CallerF = MF.getFunction();
3627 // If the function return type is x86_fp80 and the callee return type is not,
3628 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3629 // perform a tailcall optimization here.
3630 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3633 CallingConv::ID CallerCC = CallerF->getCallingConv();
3634 bool CCMatch = CallerCC == CalleeCC;
3635 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3636 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3638 // Win64 functions have extra shadow space for argument homing. Don't do the
3639 // sibcall if the caller and callee have mismatched expectations for this
3641 if (IsCalleeWin64 != IsCallerWin64)
3644 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3645 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3650 // Look for obvious safe cases to perform tail call optimization that do not
3651 // require ABI changes. This is what gcc calls sibcall.
3653 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3654 // emit a special epilogue.
3655 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3656 if (RegInfo->needsStackRealignment(MF))
3659 // Also avoid sibcall optimization if either caller or callee uses struct
3660 // return semantics.
3661 if (isCalleeStructRet || isCallerStructRet)
3664 // Don't do TCO when the current function is expected to clear its stack and
3665 // the callee's convention does not match.
3666 // FIXME: this is more restrictive than needed. We could produce a tailcall
3667 // when the stack adjustment matches. For example, with a thiscall that takes
3668 // only one argument.
3669 bool CallerPopsArgs =
3670 X86::isCalleePop(CallerCC, Subtarget->is64Bit(), CallerF->isVarArg(),
3671 /*GuaranteeTCO=*/false);
3672 if (CallerPopsArgs && !CCMatch)
3675 // Do not sibcall optimize vararg calls unless all arguments are passed via
3677 if (isVarArg && !Outs.empty()) {
3679 // Optimizing for varargs on Win64 is unlikely to be safe without
3680 // additional testing.
3681 if (IsCalleeWin64 || IsCallerWin64)
3684 SmallVector<CCValAssign, 16> ArgLocs;
3685 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3688 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3689 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3690 if (!ArgLocs[i].isRegLoc())
3694 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3695 // stack. Therefore, if it's not used by the call it is not safe to optimize
3696 // this into a sibcall.
3697 bool Unused = false;
3698 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3705 SmallVector<CCValAssign, 16> RVLocs;
3706 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3708 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3709 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3710 CCValAssign &VA = RVLocs[i];
3711 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3716 // If the calling conventions do not match, then we'd better make sure the
3717 // results are returned in the same way as what the caller expects.
3719 SmallVector<CCValAssign, 16> RVLocs1;
3720 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3722 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3724 SmallVector<CCValAssign, 16> RVLocs2;
3725 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3727 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3729 if (RVLocs1.size() != RVLocs2.size())
3731 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3732 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3734 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3736 if (RVLocs1[i].isRegLoc()) {
3737 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3740 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3746 // If the callee takes no arguments then go on to check the results of the
3748 if (!Outs.empty()) {
3749 // Check if stack adjustment is needed. For now, do not do this if any
3750 // argument is passed on the stack.
3751 SmallVector<CCValAssign, 16> ArgLocs;
3752 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3755 // Allocate shadow area for Win64
3757 CCInfo.AllocateStack(32, 8);
3759 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3760 if (CCInfo.getNextStackOffset()) {
3761 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3764 // Check if the arguments are already laid out in the right way as
3765 // the caller's fixed stack objects.
3766 MachineFrameInfo *MFI = MF.getFrameInfo();
3767 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3768 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3769 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3770 CCValAssign &VA = ArgLocs[i];
3771 SDValue Arg = OutVals[i];
3772 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3773 if (VA.getLocInfo() == CCValAssign::Indirect)
3775 if (!VA.isRegLoc()) {
3776 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3783 // If the tailcall address may be in a register, then make sure it's
3784 // possible to register allocate for it. In 32-bit, the call address can
3785 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3786 // callee-saved registers are restored. These happen to be the same
3787 // registers used to pass 'inreg' arguments so watch out for those.
3788 if (!Subtarget->is64Bit() &&
3789 ((!isa<GlobalAddressSDNode>(Callee) &&
3790 !isa<ExternalSymbolSDNode>(Callee)) ||
3791 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3792 unsigned NumInRegs = 0;
3793 // In PIC we need an extra register to formulate the address computation
3795 unsigned MaxInRegs =
3796 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3798 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3799 CCValAssign &VA = ArgLocs[i];
3802 unsigned Reg = VA.getLocReg();
3805 case X86::EAX: case X86::EDX: case X86::ECX:
3806 if (++NumInRegs == MaxInRegs)
3818 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3819 const TargetLibraryInfo *libInfo) const {
3820 return X86::createFastISel(funcInfo, libInfo);
3823 //===----------------------------------------------------------------------===//
3824 // Other Lowering Hooks
3825 //===----------------------------------------------------------------------===//
3827 static bool MayFoldLoad(SDValue Op) {
3828 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3831 static bool MayFoldIntoStore(SDValue Op) {
3832 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3835 static bool isTargetShuffle(unsigned Opcode) {
3837 default: return false;
3838 case X86ISD::BLENDI:
3839 case X86ISD::PSHUFB:
3840 case X86ISD::PSHUFD:
3841 case X86ISD::PSHUFHW:
3842 case X86ISD::PSHUFLW:
3844 case X86ISD::PALIGNR:
3845 case X86ISD::MOVLHPS:
3846 case X86ISD::MOVLHPD:
3847 case X86ISD::MOVHLPS:
3848 case X86ISD::MOVLPS:
3849 case X86ISD::MOVLPD:
3850 case X86ISD::MOVSHDUP:
3851 case X86ISD::MOVSLDUP:
3852 case X86ISD::MOVDDUP:
3855 case X86ISD::UNPCKL:
3856 case X86ISD::UNPCKH:
3857 case X86ISD::VPERMILPI:
3858 case X86ISD::VPERM2X128:
3859 case X86ISD::VPERMI:
3860 case X86ISD::VPERMV:
3861 case X86ISD::VPERMV3:
3866 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3867 SDValue V1, unsigned TargetMask,
3868 SelectionDAG &DAG) {
3870 default: llvm_unreachable("Unknown x86 shuffle node");
3871 case X86ISD::PSHUFD:
3872 case X86ISD::PSHUFHW:
3873 case X86ISD::PSHUFLW:
3874 case X86ISD::VPERMILPI:
3875 case X86ISD::VPERMI:
3876 return DAG.getNode(Opc, dl, VT, V1,
3877 DAG.getConstant(TargetMask, dl, MVT::i8));
3881 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3882 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3884 default: llvm_unreachable("Unknown x86 shuffle node");
3885 case X86ISD::MOVLHPS:
3886 case X86ISD::MOVLHPD:
3887 case X86ISD::MOVHLPS:
3888 case X86ISD::MOVLPS:
3889 case X86ISD::MOVLPD:
3892 case X86ISD::UNPCKL:
3893 case X86ISD::UNPCKH:
3894 return DAG.getNode(Opc, dl, VT, V1, V2);
3898 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3899 MachineFunction &MF = DAG.getMachineFunction();
3900 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3901 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3902 int ReturnAddrIndex = FuncInfo->getRAIndex();
3904 if (ReturnAddrIndex == 0) {
3905 // Set up a frame object for the return address.
3906 unsigned SlotSize = RegInfo->getSlotSize();
3907 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3910 FuncInfo->setRAIndex(ReturnAddrIndex);
3913 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3916 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3917 bool hasSymbolicDisplacement) {
3918 // Offset should fit into 32 bit immediate field.
3919 if (!isInt<32>(Offset))
3922 // If we don't have a symbolic displacement - we don't have any extra
3924 if (!hasSymbolicDisplacement)
3927 // FIXME: Some tweaks might be needed for medium code model.
3928 if (M != CodeModel::Small && M != CodeModel::Kernel)
3931 // For small code model we assume that latest object is 16MB before end of 31
3932 // bits boundary. We may also accept pretty large negative constants knowing
3933 // that all objects are in the positive half of address space.
3934 if (M == CodeModel::Small && Offset < 16*1024*1024)
3937 // For kernel code model we know that all object resist in the negative half
3938 // of 32bits address space. We may not accept negative offsets, since they may
3939 // be just off and we may accept pretty large positive ones.
3940 if (M == CodeModel::Kernel && Offset >= 0)
3946 /// Determines whether the callee is required to pop its own arguments.
3947 /// Callee pop is necessary to support tail calls.
3948 bool X86::isCalleePop(CallingConv::ID CallingConv,
3949 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3950 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3951 // can guarantee TCO.
3952 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3955 switch (CallingConv) {
3958 case CallingConv::X86_StdCall:
3959 case CallingConv::X86_FastCall:
3960 case CallingConv::X86_ThisCall:
3961 case CallingConv::X86_VectorCall:
3966 /// \brief Return true if the condition is an unsigned comparison operation.
3967 static bool isX86CCUnsigned(unsigned X86CC) {
3969 default: llvm_unreachable("Invalid integer condition!");
3970 case X86::COND_E: return true;
3971 case X86::COND_G: return false;
3972 case X86::COND_GE: return false;
3973 case X86::COND_L: return false;
3974 case X86::COND_LE: return false;
3975 case X86::COND_NE: return true;
3976 case X86::COND_B: return true;
3977 case X86::COND_A: return true;
3978 case X86::COND_BE: return true;
3979 case X86::COND_AE: return true;
3981 llvm_unreachable("covered switch fell through?!");
3984 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3985 /// condition code, returning the condition code and the LHS/RHS of the
3986 /// comparison to make.
3987 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3988 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3990 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3991 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3992 // X > -1 -> X == 0, jump !sign.
3993 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3994 return X86::COND_NS;
3996 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3997 // X < 0 -> X == 0, jump on sign.
4000 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4002 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4003 return X86::COND_LE;
4007 switch (SetCCOpcode) {
4008 default: llvm_unreachable("Invalid integer condition!");
4009 case ISD::SETEQ: return X86::COND_E;
4010 case ISD::SETGT: return X86::COND_G;
4011 case ISD::SETGE: return X86::COND_GE;
4012 case ISD::SETLT: return X86::COND_L;
4013 case ISD::SETLE: return X86::COND_LE;
4014 case ISD::SETNE: return X86::COND_NE;
4015 case ISD::SETULT: return X86::COND_B;
4016 case ISD::SETUGT: return X86::COND_A;
4017 case ISD::SETULE: return X86::COND_BE;
4018 case ISD::SETUGE: return X86::COND_AE;
4022 // First determine if it is required or is profitable to flip the operands.
4024 // If LHS is a foldable load, but RHS is not, flip the condition.
4025 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4026 !ISD::isNON_EXTLoad(RHS.getNode())) {
4027 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4028 std::swap(LHS, RHS);
4031 switch (SetCCOpcode) {
4037 std::swap(LHS, RHS);
4041 // On a floating point condition, the flags are set as follows:
4043 // 0 | 0 | 0 | X > Y
4044 // 0 | 0 | 1 | X < Y
4045 // 1 | 0 | 0 | X == Y
4046 // 1 | 1 | 1 | unordered
4047 switch (SetCCOpcode) {
4048 default: llvm_unreachable("Condcode should be pre-legalized away");
4050 case ISD::SETEQ: return X86::COND_E;
4051 case ISD::SETOLT: // flipped
4053 case ISD::SETGT: return X86::COND_A;
4054 case ISD::SETOLE: // flipped
4056 case ISD::SETGE: return X86::COND_AE;
4057 case ISD::SETUGT: // flipped
4059 case ISD::SETLT: return X86::COND_B;
4060 case ISD::SETUGE: // flipped
4062 case ISD::SETLE: return X86::COND_BE;
4064 case ISD::SETNE: return X86::COND_NE;
4065 case ISD::SETUO: return X86::COND_P;
4066 case ISD::SETO: return X86::COND_NP;
4068 case ISD::SETUNE: return X86::COND_INVALID;
4072 /// Is there a floating point cmov for the specific X86 condition code?
4073 /// Current x86 isa includes the following FP cmov instructions:
4074 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4075 static bool hasFPCMov(unsigned X86CC) {
4091 /// Returns true if the target can instruction select the
4092 /// specified FP immediate natively. If false, the legalizer will
4093 /// materialize the FP immediate as a load from a constant pool.
4094 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4095 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4096 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4102 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4103 ISD::LoadExtType ExtTy,
4105 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4106 // relocation target a movq or addq instruction: don't let the load shrink.
4107 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4108 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4109 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4110 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4114 /// \brief Returns true if it is beneficial to convert a load of a constant
4115 /// to just the constant itself.
4116 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4118 assert(Ty->isIntegerTy());
4120 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4121 if (BitSize == 0 || BitSize > 64)
4126 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4127 unsigned Index) const {
4128 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4131 return (Index == 0 || Index == ResVT.getVectorNumElements());
4134 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4135 // Speculate cttz only if we can directly use TZCNT.
4136 return Subtarget->hasBMI();
4139 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4140 // Speculate ctlz only if we can directly use LZCNT.
4141 return Subtarget->hasLZCNT();
4144 /// Return true if every element in Mask, beginning
4145 /// from position Pos and ending in Pos+Size is undef.
4146 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4147 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4153 /// Return true if Val is undef or if its value falls within the
4154 /// specified range (L, H].
4155 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4156 return (Val < 0) || (Val >= Low && Val < Hi);
4159 /// Val is either less than zero (undef) or equal to the specified value.
4160 static bool isUndefOrEqual(int Val, int CmpVal) {
4161 return (Val < 0 || Val == CmpVal);
4164 /// Return true if every element in Mask, beginning
4165 /// from position Pos and ending in Pos+Size, falls within the specified
4166 /// sequential range (Low, Low+Size]. or is undef.
4167 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4168 unsigned Pos, unsigned Size, int Low) {
4169 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4170 if (!isUndefOrEqual(Mask[i], Low))
4175 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4176 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4177 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4178 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4179 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4182 // The index should be aligned on a vecWidth-bit boundary.
4184 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4186 MVT VT = N->getSimpleValueType(0);
4187 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4188 bool Result = (Index * ElSize) % vecWidth == 0;
4193 /// Return true if the specified INSERT_SUBVECTOR
4194 /// operand specifies a subvector insert that is suitable for input to
4195 /// insertion of 128 or 256-bit subvectors
4196 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4197 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4198 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4200 // The index should be aligned on a vecWidth-bit boundary.
4202 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4204 MVT VT = N->getSimpleValueType(0);
4205 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4206 bool Result = (Index * ElSize) % vecWidth == 0;
4211 bool X86::isVINSERT128Index(SDNode *N) {
4212 return isVINSERTIndex(N, 128);
4215 bool X86::isVINSERT256Index(SDNode *N) {
4216 return isVINSERTIndex(N, 256);
4219 bool X86::isVEXTRACT128Index(SDNode *N) {
4220 return isVEXTRACTIndex(N, 128);
4223 bool X86::isVEXTRACT256Index(SDNode *N) {
4224 return isVEXTRACTIndex(N, 256);
4227 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4228 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4229 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4230 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4233 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4235 MVT VecVT = N->getOperand(0).getSimpleValueType();
4236 MVT ElVT = VecVT.getVectorElementType();
4238 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4239 return Index / NumElemsPerChunk;
4242 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4243 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4244 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4245 llvm_unreachable("Illegal insert subvector for VINSERT");
4248 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4250 MVT VecVT = N->getSimpleValueType(0);
4251 MVT ElVT = VecVT.getVectorElementType();
4253 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4254 return Index / NumElemsPerChunk;
4257 /// Return the appropriate immediate to extract the specified
4258 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4259 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4260 return getExtractVEXTRACTImmediate(N, 128);
4263 /// Return the appropriate immediate to extract the specified
4264 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4265 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4266 return getExtractVEXTRACTImmediate(N, 256);
4269 /// Return the appropriate immediate to insert at the specified
4270 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4271 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4272 return getInsertVINSERTImmediate(N, 128);
4275 /// Return the appropriate immediate to insert at the specified
4276 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4277 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4278 return getInsertVINSERTImmediate(N, 256);
4281 /// Returns true if V is a constant integer zero.
4282 static bool isZero(SDValue V) {
4283 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4284 return C && C->isNullValue();
4287 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4288 bool X86::isZeroNode(SDValue Elt) {
4291 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4292 return CFP->getValueAPF().isPosZero();
4296 // Build a vector of constants
4297 // Use an UNDEF node if MaskElt == -1.
4298 // Spilt 64-bit constants in the 32-bit mode.
4299 static SDValue getConstVector(ArrayRef<int> Values, EVT VT,
4301 SDLoc dl, bool IsMask = false) {
4303 SmallVector<SDValue, 32> Ops;
4306 EVT ConstVecVT = VT;
4307 unsigned NumElts = VT.getVectorNumElements();
4308 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4309 if (!In64BitMode && VT.getScalarType() == MVT::i64) {
4310 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4314 EVT EltVT = ConstVecVT.getScalarType();
4315 for (unsigned i = 0; i < NumElts; ++i) {
4316 bool IsUndef = Values[i] < 0 && IsMask;
4317 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4318 DAG.getConstant(Values[i], dl, EltVT);
4319 Ops.push_back(OpNode);
4321 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4322 DAG.getConstant(0, dl, EltVT));
4324 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4326 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4330 /// Returns a vector of specified type with all zero elements.
4331 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4332 SelectionDAG &DAG, SDLoc dl) {
4333 assert(VT.isVector() && "Expected a vector type");
4335 // Always build SSE zero vectors as <4 x i32> bitcasted
4336 // to their dest type. This ensures they get CSE'd.
4338 if (VT.is128BitVector()) { // SSE
4339 if (Subtarget->hasSSE2()) { // SSE2
4340 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4341 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4343 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4344 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4346 } else if (VT.is256BitVector()) { // AVX
4347 if (Subtarget->hasInt256()) { // AVX2
4348 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4349 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4350 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4352 // 256-bit logic and arithmetic instructions in AVX are all
4353 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4354 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4355 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4356 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4358 } else if (VT.is512BitVector()) { // AVX-512
4359 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4360 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4361 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4362 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4363 } else if (VT.getScalarType() == MVT::i1) {
4365 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4366 && "Unexpected vector type");
4367 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4368 && "Unexpected vector type");
4369 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4370 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4371 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4373 llvm_unreachable("Unexpected vector type");
4375 return DAG.getBitcast(VT, Vec);
4378 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4379 SelectionDAG &DAG, SDLoc dl,
4380 unsigned vectorWidth) {
4381 assert((vectorWidth == 128 || vectorWidth == 256) &&
4382 "Unsupported vector width");
4383 EVT VT = Vec.getValueType();
4384 EVT ElVT = VT.getVectorElementType();
4385 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4386 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4387 VT.getVectorNumElements()/Factor);
4389 // Extract from UNDEF is UNDEF.
4390 if (Vec.getOpcode() == ISD::UNDEF)
4391 return DAG.getUNDEF(ResultVT);
4393 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4394 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4396 // This is the index of the first element of the vectorWidth-bit chunk
4398 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4401 // If the input is a buildvector just emit a smaller one.
4402 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4403 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4404 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4407 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4408 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4411 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4412 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4413 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4414 /// instructions or a simple subregister reference. Idx is an index in the
4415 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4416 /// lowering EXTRACT_VECTOR_ELT operations easier.
4417 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4418 SelectionDAG &DAG, SDLoc dl) {
4419 assert((Vec.getValueType().is256BitVector() ||
4420 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4421 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4424 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4425 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4426 SelectionDAG &DAG, SDLoc dl) {
4427 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4428 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4431 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4432 unsigned IdxVal, SelectionDAG &DAG,
4433 SDLoc dl, unsigned vectorWidth) {
4434 assert((vectorWidth == 128 || vectorWidth == 256) &&
4435 "Unsupported vector width");
4436 // Inserting UNDEF is Result
4437 if (Vec.getOpcode() == ISD::UNDEF)
4439 EVT VT = Vec.getValueType();
4440 EVT ElVT = VT.getVectorElementType();
4441 EVT ResultVT = Result.getValueType();
4443 // Insert the relevant vectorWidth bits.
4444 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4446 // This is the index of the first element of the vectorWidth-bit chunk
4448 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4451 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4452 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4455 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4456 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4457 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4458 /// simple superregister reference. Idx is an index in the 128 bits
4459 /// we want. It need not be aligned to a 128-bit boundary. That makes
4460 /// lowering INSERT_VECTOR_ELT operations easier.
4461 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4462 SelectionDAG &DAG, SDLoc dl) {
4463 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4465 // For insertion into the zero index (low half) of a 256-bit vector, it is
4466 // more efficient to generate a blend with immediate instead of an insert*128.
4467 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4468 // extend the subvector to the size of the result vector. Make sure that
4469 // we are not recursing on that node by checking for undef here.
4470 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4471 Result.getOpcode() != ISD::UNDEF) {
4472 EVT ResultVT = Result.getValueType();
4473 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4474 SDValue Undef = DAG.getUNDEF(ResultVT);
4475 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4478 // The blend instruction, and therefore its mask, depend on the data type.
4479 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4480 if (ScalarType.isFloatingPoint()) {
4481 // Choose either vblendps (float) or vblendpd (double).
4482 unsigned ScalarSize = ScalarType.getSizeInBits();
4483 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4484 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4485 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4486 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4489 const X86Subtarget &Subtarget =
4490 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4492 // AVX2 is needed for 256-bit integer blend support.
4493 // Integers must be cast to 32-bit because there is only vpblendd;
4494 // vpblendw can't be used for this because it has a handicapped mask.
4496 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4497 // is still more efficient than using the wrong domain vinsertf128 that
4498 // will be created by InsertSubVector().
4499 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4501 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4502 Vec256 = DAG.getBitcast(CastVT, Vec256);
4503 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4504 return DAG.getBitcast(ResultVT, Vec256);
4507 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4510 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4511 SelectionDAG &DAG, SDLoc dl) {
4512 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4513 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4516 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4517 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4518 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4519 /// large BUILD_VECTORS.
4520 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4521 unsigned NumElems, SelectionDAG &DAG,
4523 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4524 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4527 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4528 unsigned NumElems, SelectionDAG &DAG,
4530 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4531 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4534 /// Returns a vector of specified type with all bits set.
4535 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4536 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4537 /// Then bitcast to their original type, ensuring they get CSE'd.
4538 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4539 SelectionDAG &DAG, SDLoc dl) {
4540 assert(VT.isVector() && "Expected a vector type");
4542 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4544 if (VT.is512BitVector()) {
4545 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4546 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4547 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4548 } else if (VT.is256BitVector()) {
4549 if (Subtarget->hasInt256()) { // AVX2
4550 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4551 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4553 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4554 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4556 } else if (VT.is128BitVector()) {
4557 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4559 llvm_unreachable("Unexpected vector type");
4561 return DAG.getBitcast(VT, Vec);
4564 /// Returns a vector_shuffle node for an unpackl operation.
4565 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4567 unsigned NumElems = VT.getVectorNumElements();
4568 SmallVector<int, 8> Mask;
4569 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4571 Mask.push_back(i + NumElems);
4573 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4576 /// Returns a vector_shuffle node for an unpackh operation.
4577 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4579 unsigned NumElems = VT.getVectorNumElements();
4580 SmallVector<int, 8> Mask;
4581 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4582 Mask.push_back(i + Half);
4583 Mask.push_back(i + NumElems + Half);
4585 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4588 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4589 /// This produces a shuffle where the low element of V2 is swizzled into the
4590 /// zero/undef vector, landing at element Idx.
4591 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4592 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4594 const X86Subtarget *Subtarget,
4595 SelectionDAG &DAG) {
4596 MVT VT = V2.getSimpleValueType();
4598 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4599 unsigned NumElems = VT.getVectorNumElements();
4600 SmallVector<int, 16> MaskVec;
4601 for (unsigned i = 0; i != NumElems; ++i)
4602 // If this is the insertion idx, put the low elt of V2 here.
4603 MaskVec.push_back(i == Idx ? NumElems : i);
4604 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4607 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4608 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4609 /// uses one source. Note that this will set IsUnary for shuffles which use a
4610 /// single input multiple times, and in those cases it will
4611 /// adjust the mask to only have indices within that single input.
4612 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4613 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4614 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4615 unsigned NumElems = VT.getVectorNumElements();
4619 bool IsFakeUnary = false;
4620 switch(N->getOpcode()) {
4621 case X86ISD::BLENDI:
4622 ImmN = N->getOperand(N->getNumOperands()-1);
4623 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4626 ImmN = N->getOperand(N->getNumOperands()-1);
4627 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4628 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4630 case X86ISD::UNPCKH:
4631 DecodeUNPCKHMask(VT, Mask);
4632 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4634 case X86ISD::UNPCKL:
4635 DecodeUNPCKLMask(VT, Mask);
4636 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4638 case X86ISD::MOVHLPS:
4639 DecodeMOVHLPSMask(NumElems, Mask);
4640 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4642 case X86ISD::MOVLHPS:
4643 DecodeMOVLHPSMask(NumElems, Mask);
4644 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4646 case X86ISD::PALIGNR:
4647 ImmN = N->getOperand(N->getNumOperands()-1);
4648 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4650 case X86ISD::PSHUFD:
4651 case X86ISD::VPERMILPI:
4652 ImmN = N->getOperand(N->getNumOperands()-1);
4653 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4656 case X86ISD::PSHUFHW:
4657 ImmN = N->getOperand(N->getNumOperands()-1);
4658 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4661 case X86ISD::PSHUFLW:
4662 ImmN = N->getOperand(N->getNumOperands()-1);
4663 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4666 case X86ISD::PSHUFB: {
4668 SDValue MaskNode = N->getOperand(1);
4669 while (MaskNode->getOpcode() == ISD::BITCAST)
4670 MaskNode = MaskNode->getOperand(0);
4672 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4673 // If we have a build-vector, then things are easy.
4674 EVT VT = MaskNode.getValueType();
4675 assert(VT.isVector() &&
4676 "Can't produce a non-vector with a build_vector!");
4677 if (!VT.isInteger())
4680 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4682 SmallVector<uint64_t, 32> RawMask;
4683 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4684 SDValue Op = MaskNode->getOperand(i);
4685 if (Op->getOpcode() == ISD::UNDEF) {
4686 RawMask.push_back((uint64_t)SM_SentinelUndef);
4689 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4692 APInt MaskElement = CN->getAPIntValue();
4694 // We now have to decode the element which could be any integer size and
4695 // extract each byte of it.
4696 for (int j = 0; j < NumBytesPerElement; ++j) {
4697 // Note that this is x86 and so always little endian: the low byte is
4698 // the first byte of the mask.
4699 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4700 MaskElement = MaskElement.lshr(8);
4703 DecodePSHUFBMask(RawMask, Mask);
4707 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4711 SDValue Ptr = MaskLoad->getBasePtr();
4712 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4713 Ptr->getOpcode() == X86ISD::WrapperRIP)
4714 Ptr = Ptr->getOperand(0);
4716 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4717 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4720 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4721 DecodePSHUFBMask(C, Mask);
4729 case X86ISD::VPERMI:
4730 ImmN = N->getOperand(N->getNumOperands()-1);
4731 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4736 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4738 case X86ISD::VPERM2X128:
4739 ImmN = N->getOperand(N->getNumOperands()-1);
4740 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4741 if (Mask.empty()) return false;
4742 // Mask only contains negative index if an element is zero.
4743 if (std::any_of(Mask.begin(), Mask.end(),
4744 [](int M){ return M == SM_SentinelZero; }))
4747 case X86ISD::MOVSLDUP:
4748 DecodeMOVSLDUPMask(VT, Mask);
4751 case X86ISD::MOVSHDUP:
4752 DecodeMOVSHDUPMask(VT, Mask);
4755 case X86ISD::MOVDDUP:
4756 DecodeMOVDDUPMask(VT, Mask);
4759 case X86ISD::MOVLHPD:
4760 case X86ISD::MOVLPD:
4761 case X86ISD::MOVLPS:
4762 // Not yet implemented
4764 case X86ISD::VPERMV: {
4766 SDValue MaskNode = N->getOperand(0);
4767 while (MaskNode->getOpcode() == ISD::BITCAST)
4768 MaskNode = MaskNode->getOperand(0);
4770 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4771 SmallVector<uint64_t, 32> RawMask;
4772 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4773 // If we have a build-vector, then things are easy.
4774 assert(MaskNode.getValueType().isInteger() &&
4775 MaskNode.getValueType().getVectorNumElements() ==
4776 VT.getVectorNumElements());
4778 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4779 SDValue Op = MaskNode->getOperand(i);
4780 if (Op->getOpcode() == ISD::UNDEF)
4781 RawMask.push_back((uint64_t)SM_SentinelUndef);
4782 else if (isa<ConstantSDNode>(Op)) {
4783 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4784 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4788 DecodeVPERMVMask(RawMask, Mask);
4791 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4792 unsigned NumEltsInMask = MaskNode->getNumOperands();
4793 MaskNode = MaskNode->getOperand(0);
4794 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4796 APInt MaskEltValue = CN->getAPIntValue();
4797 for (unsigned i = 0; i < NumEltsInMask; ++i)
4798 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4799 DecodeVPERMVMask(RawMask, Mask);
4802 // It may be a scalar load
4805 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4809 SDValue Ptr = MaskLoad->getBasePtr();
4810 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4811 Ptr->getOpcode() == X86ISD::WrapperRIP)
4812 Ptr = Ptr->getOperand(0);
4814 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4815 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4818 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4820 DecodeVPERMVMask(C, VT, Mask);
4827 case X86ISD::VPERMV3: {
4829 SDValue MaskNode = N->getOperand(1);
4830 while (MaskNode->getOpcode() == ISD::BITCAST)
4831 MaskNode = MaskNode->getOperand(1);
4833 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4834 // If we have a build-vector, then things are easy.
4835 assert(MaskNode.getValueType().isInteger() &&
4836 MaskNode.getValueType().getVectorNumElements() ==
4837 VT.getVectorNumElements());
4839 SmallVector<uint64_t, 32> RawMask;
4840 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4842 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4843 SDValue Op = MaskNode->getOperand(i);
4844 if (Op->getOpcode() == ISD::UNDEF)
4845 RawMask.push_back((uint64_t)SM_SentinelUndef);
4847 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4850 APInt MaskElement = CN->getAPIntValue();
4851 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4854 DecodeVPERMV3Mask(RawMask, Mask);
4858 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4862 SDValue Ptr = MaskLoad->getBasePtr();
4863 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4864 Ptr->getOpcode() == X86ISD::WrapperRIP)
4865 Ptr = Ptr->getOperand(0);
4867 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4868 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4871 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4873 DecodeVPERMV3Mask(C, VT, Mask);
4880 default: llvm_unreachable("unknown target shuffle node");
4883 // If we have a fake unary shuffle, the shuffle mask is spread across two
4884 // inputs that are actually the same node. Re-map the mask to always point
4885 // into the first input.
4888 if (M >= (int)Mask.size())
4894 /// Returns the scalar element that will make up the ith
4895 /// element of the result of the vector shuffle.
4896 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4899 return SDValue(); // Limit search depth.
4901 SDValue V = SDValue(N, 0);
4902 EVT VT = V.getValueType();
4903 unsigned Opcode = V.getOpcode();
4905 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4906 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4907 int Elt = SV->getMaskElt(Index);
4910 return DAG.getUNDEF(VT.getVectorElementType());
4912 unsigned NumElems = VT.getVectorNumElements();
4913 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4914 : SV->getOperand(1);
4915 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4918 // Recurse into target specific vector shuffles to find scalars.
4919 if (isTargetShuffle(Opcode)) {
4920 MVT ShufVT = V.getSimpleValueType();
4921 unsigned NumElems = ShufVT.getVectorNumElements();
4922 SmallVector<int, 16> ShuffleMask;
4925 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4928 int Elt = ShuffleMask[Index];
4930 return DAG.getUNDEF(ShufVT.getVectorElementType());
4932 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4934 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4938 // Actual nodes that may contain scalar elements
4939 if (Opcode == ISD::BITCAST) {
4940 V = V.getOperand(0);
4941 EVT SrcVT = V.getValueType();
4942 unsigned NumElems = VT.getVectorNumElements();
4944 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4948 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4949 return (Index == 0) ? V.getOperand(0)
4950 : DAG.getUNDEF(VT.getVectorElementType());
4952 if (V.getOpcode() == ISD::BUILD_VECTOR)
4953 return V.getOperand(Index);
4958 /// Custom lower build_vector of v16i8.
4959 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4960 unsigned NumNonZero, unsigned NumZero,
4962 const X86Subtarget* Subtarget,
4963 const TargetLowering &TLI) {
4971 // SSE4.1 - use PINSRB to insert each byte directly.
4972 if (Subtarget->hasSSE41()) {
4973 for (unsigned i = 0; i < 16; ++i) {
4974 bool isNonZero = (NonZeros & (1 << i)) != 0;
4978 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4980 V = DAG.getUNDEF(MVT::v16i8);
4983 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4984 MVT::v16i8, V, Op.getOperand(i),
4985 DAG.getIntPtrConstant(i, dl));
4992 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4993 for (unsigned i = 0; i < 16; ++i) {
4994 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4995 if (ThisIsNonZero && First) {
4997 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4999 V = DAG.getUNDEF(MVT::v8i16);
5004 SDValue ThisElt, LastElt;
5005 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5006 if (LastIsNonZero) {
5007 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5008 MVT::i16, Op.getOperand(i-1));
5010 if (ThisIsNonZero) {
5011 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5012 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5013 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5015 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5019 if (ThisElt.getNode())
5020 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5021 DAG.getIntPtrConstant(i/2, dl));
5025 return DAG.getBitcast(MVT::v16i8, V);
5028 /// Custom lower build_vector of v8i16.
5029 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5030 unsigned NumNonZero, unsigned NumZero,
5032 const X86Subtarget* Subtarget,
5033 const TargetLowering &TLI) {
5040 for (unsigned i = 0; i < 8; ++i) {
5041 bool isNonZero = (NonZeros & (1 << i)) != 0;
5045 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5047 V = DAG.getUNDEF(MVT::v8i16);
5050 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5051 MVT::v8i16, V, Op.getOperand(i),
5052 DAG.getIntPtrConstant(i, dl));
5059 /// Custom lower build_vector of v4i32 or v4f32.
5060 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5061 const X86Subtarget *Subtarget,
5062 const TargetLowering &TLI) {
5063 // Find all zeroable elements.
5064 std::bitset<4> Zeroable;
5065 for (int i=0; i < 4; ++i) {
5066 SDValue Elt = Op->getOperand(i);
5067 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5069 assert(Zeroable.size() - Zeroable.count() > 1 &&
5070 "We expect at least two non-zero elements!");
5072 // We only know how to deal with build_vector nodes where elements are either
5073 // zeroable or extract_vector_elt with constant index.
5074 SDValue FirstNonZero;
5075 unsigned FirstNonZeroIdx;
5076 for (unsigned i=0; i < 4; ++i) {
5079 SDValue Elt = Op->getOperand(i);
5080 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5081 !isa<ConstantSDNode>(Elt.getOperand(1)))
5083 // Make sure that this node is extracting from a 128-bit vector.
5084 MVT VT = Elt.getOperand(0).getSimpleValueType();
5085 if (!VT.is128BitVector())
5087 if (!FirstNonZero.getNode()) {
5089 FirstNonZeroIdx = i;
5093 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5094 SDValue V1 = FirstNonZero.getOperand(0);
5095 MVT VT = V1.getSimpleValueType();
5097 // See if this build_vector can be lowered as a blend with zero.
5099 unsigned EltMaskIdx, EltIdx;
5101 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5102 if (Zeroable[EltIdx]) {
5103 // The zero vector will be on the right hand side.
5104 Mask[EltIdx] = EltIdx+4;
5108 Elt = Op->getOperand(EltIdx);
5109 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5110 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5111 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5113 Mask[EltIdx] = EltIdx;
5117 // Let the shuffle legalizer deal with blend operations.
5118 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5119 if (V1.getSimpleValueType() != VT)
5120 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5121 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5124 // See if we can lower this build_vector to a INSERTPS.
5125 if (!Subtarget->hasSSE41())
5128 SDValue V2 = Elt.getOperand(0);
5129 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5132 bool CanFold = true;
5133 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5137 SDValue Current = Op->getOperand(i);
5138 SDValue SrcVector = Current->getOperand(0);
5141 CanFold = SrcVector == V1 &&
5142 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5148 assert(V1.getNode() && "Expected at least two non-zero elements!");
5149 if (V1.getSimpleValueType() != MVT::v4f32)
5150 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5151 if (V2.getSimpleValueType() != MVT::v4f32)
5152 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5154 // Ok, we can emit an INSERTPS instruction.
5155 unsigned ZMask = Zeroable.to_ulong();
5157 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5158 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5160 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5161 DAG.getIntPtrConstant(InsertPSMask, DL));
5162 return DAG.getBitcast(VT, Result);
5165 /// Return a vector logical shift node.
5166 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5167 unsigned NumBits, SelectionDAG &DAG,
5168 const TargetLowering &TLI, SDLoc dl) {
5169 assert(VT.is128BitVector() && "Unknown type for VShift");
5170 MVT ShVT = MVT::v2i64;
5171 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5172 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5173 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5174 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5175 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5176 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5180 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5182 // Check if the scalar load can be widened into a vector load. And if
5183 // the address is "base + cst" see if the cst can be "absorbed" into
5184 // the shuffle mask.
5185 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5186 SDValue Ptr = LD->getBasePtr();
5187 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5189 EVT PVT = LD->getValueType(0);
5190 if (PVT != MVT::i32 && PVT != MVT::f32)
5195 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5196 FI = FINode->getIndex();
5198 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5199 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5200 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5201 Offset = Ptr.getConstantOperandVal(1);
5202 Ptr = Ptr.getOperand(0);
5207 // FIXME: 256-bit vector instructions don't require a strict alignment,
5208 // improve this code to support it better.
5209 unsigned RequiredAlign = VT.getSizeInBits()/8;
5210 SDValue Chain = LD->getChain();
5211 // Make sure the stack object alignment is at least 16 or 32.
5212 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5213 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5214 if (MFI->isFixedObjectIndex(FI)) {
5215 // Can't change the alignment. FIXME: It's possible to compute
5216 // the exact stack offset and reference FI + adjust offset instead.
5217 // If someone *really* cares about this. That's the way to implement it.
5220 MFI->setObjectAlignment(FI, RequiredAlign);
5224 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5225 // Ptr + (Offset & ~15).
5228 if ((Offset % RequiredAlign) & 3)
5230 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5233 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5234 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5237 int EltNo = (Offset - StartOffset) >> 2;
5238 unsigned NumElems = VT.getVectorNumElements();
5240 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5241 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5242 LD->getPointerInfo().getWithOffset(StartOffset),
5243 false, false, false, 0);
5245 SmallVector<int, 8> Mask(NumElems, EltNo);
5247 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5253 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5254 /// elements can be replaced by a single large load which has the same value as
5255 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5257 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5259 /// FIXME: we'd also like to handle the case where the last elements are zero
5260 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5261 /// There's even a handy isZeroNode for that purpose.
5262 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5263 SDLoc &DL, SelectionDAG &DAG,
5264 bool isAfterLegalize) {
5265 unsigned NumElems = Elts.size();
5267 LoadSDNode *LDBase = nullptr;
5268 unsigned LastLoadedElt = -1U;
5270 // For each element in the initializer, see if we've found a load or an undef.
5271 // If we don't find an initial load element, or later load elements are
5272 // non-consecutive, bail out.
5273 for (unsigned i = 0; i < NumElems; ++i) {
5274 SDValue Elt = Elts[i];
5275 // Look through a bitcast.
5276 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5277 Elt = Elt.getOperand(0);
5278 if (!Elt.getNode() ||
5279 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5282 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5284 LDBase = cast<LoadSDNode>(Elt.getNode());
5288 if (Elt.getOpcode() == ISD::UNDEF)
5291 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5292 EVT LdVT = Elt.getValueType();
5293 // Each loaded element must be the correct fractional portion of the
5294 // requested vector load.
5295 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5297 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5302 // If we have found an entire vector of loads and undefs, then return a large
5303 // load of the entire vector width starting at the base pointer. If we found
5304 // consecutive loads for the low half, generate a vzext_load node.
5305 if (LastLoadedElt == NumElems - 1) {
5306 assert(LDBase && "Did not find base load for merging consecutive loads");
5307 EVT EltVT = LDBase->getValueType(0);
5308 // Ensure that the input vector size for the merged loads matches the
5309 // cumulative size of the input elements.
5310 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5313 if (isAfterLegalize &&
5314 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5317 SDValue NewLd = SDValue();
5319 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5320 LDBase->getPointerInfo(), LDBase->isVolatile(),
5321 LDBase->isNonTemporal(), LDBase->isInvariant(),
5322 LDBase->getAlignment());
5324 if (LDBase->hasAnyUseOfValue(1)) {
5325 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5327 SDValue(NewLd.getNode(), 1));
5328 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5329 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5330 SDValue(NewLd.getNode(), 1));
5336 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5337 //of a v4i32 / v4f32. It's probably worth generalizing.
5338 EVT EltVT = VT.getVectorElementType();
5339 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5340 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5341 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5342 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5344 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5345 LDBase->getPointerInfo(),
5346 LDBase->getAlignment(),
5347 false/*isVolatile*/, true/*ReadMem*/,
5350 // Make sure the newly-created LOAD is in the same position as LDBase in
5351 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5352 // update uses of LDBase's output chain to use the TokenFactor.
5353 if (LDBase->hasAnyUseOfValue(1)) {
5354 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5355 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5356 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5357 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5358 SDValue(ResNode.getNode(), 1));
5361 return DAG.getBitcast(VT, ResNode);
5366 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5367 /// to generate a splat value for the following cases:
5368 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5369 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5370 /// a scalar load, or a constant.
5371 /// The VBROADCAST node is returned when a pattern is found,
5372 /// or SDValue() otherwise.
5373 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5374 SelectionDAG &DAG) {
5375 // VBROADCAST requires AVX.
5376 // TODO: Splats could be generated for non-AVX CPUs using SSE
5377 // instructions, but there's less potential gain for only 128-bit vectors.
5378 if (!Subtarget->hasAVX())
5381 MVT VT = Op.getSimpleValueType();
5384 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5385 "Unsupported vector type for broadcast.");
5390 switch (Op.getOpcode()) {
5392 // Unknown pattern found.
5395 case ISD::BUILD_VECTOR: {
5396 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5397 BitVector UndefElements;
5398 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5400 // We need a splat of a single value to use broadcast, and it doesn't
5401 // make any sense if the value is only in one element of the vector.
5402 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5406 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5407 Ld.getOpcode() == ISD::ConstantFP);
5409 // Make sure that all of the users of a non-constant load are from the
5410 // BUILD_VECTOR node.
5411 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5416 case ISD::VECTOR_SHUFFLE: {
5417 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5419 // Shuffles must have a splat mask where the first element is
5421 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5424 SDValue Sc = Op.getOperand(0);
5425 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5426 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5428 if (!Subtarget->hasInt256())
5431 // Use the register form of the broadcast instruction available on AVX2.
5432 if (VT.getSizeInBits() >= 256)
5433 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5434 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5437 Ld = Sc.getOperand(0);
5438 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5439 Ld.getOpcode() == ISD::ConstantFP);
5441 // The scalar_to_vector node and the suspected
5442 // load node must have exactly one user.
5443 // Constants may have multiple users.
5445 // AVX-512 has register version of the broadcast
5446 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5447 Ld.getValueType().getSizeInBits() >= 32;
5448 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5455 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5456 bool IsGE256 = (VT.getSizeInBits() >= 256);
5458 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5459 // instruction to save 8 or more bytes of constant pool data.
5460 // TODO: If multiple splats are generated to load the same constant,
5461 // it may be detrimental to overall size. There needs to be a way to detect
5462 // that condition to know if this is truly a size win.
5463 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5465 // Handle broadcasting a single constant scalar from the constant pool
5467 // On Sandybridge (no AVX2), it is still better to load a constant vector
5468 // from the constant pool and not to broadcast it from a scalar.
5469 // But override that restriction when optimizing for size.
5470 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5471 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5472 EVT CVT = Ld.getValueType();
5473 assert(!CVT.isVector() && "Must not broadcast a vector type");
5475 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5476 // For size optimization, also splat v2f64 and v2i64, and for size opt
5477 // with AVX2, also splat i8 and i16.
5478 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5479 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5480 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5481 const Constant *C = nullptr;
5482 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5483 C = CI->getConstantIntValue();
5484 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5485 C = CF->getConstantFPValue();
5487 assert(C && "Invalid constant type");
5489 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5491 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5492 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5494 CVT, dl, DAG.getEntryNode(), CP,
5495 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5496 false, false, Alignment);
5498 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5502 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5504 // Handle AVX2 in-register broadcasts.
5505 if (!IsLoad && Subtarget->hasInt256() &&
5506 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5507 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5509 // The scalar source must be a normal load.
5513 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5514 (Subtarget->hasVLX() && ScalarSize == 64))
5515 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5517 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5518 // double since there is no vbroadcastsd xmm
5519 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5520 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5521 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5524 // Unsupported broadcast.
5528 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5529 /// underlying vector and index.
5531 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5533 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5535 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5536 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5539 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5541 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5543 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5544 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5547 // In this case the vector is the extract_subvector expression and the index
5548 // is 2, as specified by the shuffle.
5549 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5550 SDValue ShuffleVec = SVOp->getOperand(0);
5551 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5552 assert(ShuffleVecVT.getVectorElementType() ==
5553 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5555 int ShuffleIdx = SVOp->getMaskElt(Idx);
5556 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5557 ExtractedFromVec = ShuffleVec;
5563 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5564 MVT VT = Op.getSimpleValueType();
5566 // Skip if insert_vec_elt is not supported.
5567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5568 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5572 unsigned NumElems = Op.getNumOperands();
5576 SmallVector<unsigned, 4> InsertIndices;
5577 SmallVector<int, 8> Mask(NumElems, -1);
5579 for (unsigned i = 0; i != NumElems; ++i) {
5580 unsigned Opc = Op.getOperand(i).getOpcode();
5582 if (Opc == ISD::UNDEF)
5585 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5586 // Quit if more than 1 elements need inserting.
5587 if (InsertIndices.size() > 1)
5590 InsertIndices.push_back(i);
5594 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5595 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5596 // Quit if non-constant index.
5597 if (!isa<ConstantSDNode>(ExtIdx))
5599 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5601 // Quit if extracted from vector of different type.
5602 if (ExtractedFromVec.getValueType() != VT)
5605 if (!VecIn1.getNode())
5606 VecIn1 = ExtractedFromVec;
5607 else if (VecIn1 != ExtractedFromVec) {
5608 if (!VecIn2.getNode())
5609 VecIn2 = ExtractedFromVec;
5610 else if (VecIn2 != ExtractedFromVec)
5611 // Quit if more than 2 vectors to shuffle
5615 if (ExtractedFromVec == VecIn1)
5617 else if (ExtractedFromVec == VecIn2)
5618 Mask[i] = Idx + NumElems;
5621 if (!VecIn1.getNode())
5624 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5625 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5626 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5627 unsigned Idx = InsertIndices[i];
5628 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5629 DAG.getIntPtrConstant(Idx, DL));
5635 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5636 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5637 Op.getScalarValueSizeInBits() == 1 &&
5638 "Can not convert non-constant vector");
5639 uint64_t Immediate = 0;
5640 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5641 SDValue In = Op.getOperand(idx);
5642 if (In.getOpcode() != ISD::UNDEF)
5643 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5647 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5648 return DAG.getConstant(Immediate, dl, VT);
5650 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5652 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5654 MVT VT = Op.getSimpleValueType();
5655 assert((VT.getVectorElementType() == MVT::i1) &&
5656 "Unexpected type in LowerBUILD_VECTORvXi1!");
5659 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5660 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5661 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5662 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5665 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5666 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5667 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5668 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5671 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5672 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5673 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5674 return DAG.getBitcast(VT, Imm);
5675 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5676 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5677 DAG.getIntPtrConstant(0, dl));
5680 // Vector has one or more non-const elements
5681 uint64_t Immediate = 0;
5682 SmallVector<unsigned, 16> NonConstIdx;
5683 bool IsSplat = true;
5684 bool HasConstElts = false;
5686 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5687 SDValue In = Op.getOperand(idx);
5688 if (In.getOpcode() == ISD::UNDEF)
5690 if (!isa<ConstantSDNode>(In))
5691 NonConstIdx.push_back(idx);
5693 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5694 HasConstElts = true;
5698 else if (In != Op.getOperand(SplatIdx))
5702 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5704 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5705 DAG.getConstant(1, dl, VT),
5706 DAG.getConstant(0, dl, VT));
5708 // insert elements one by one
5712 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5713 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5715 else if (HasConstElts)
5716 Imm = DAG.getConstant(0, dl, VT);
5718 Imm = DAG.getUNDEF(VT);
5719 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5720 DstVec = DAG.getBitcast(VT, Imm);
5722 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5723 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5724 DAG.getIntPtrConstant(0, dl));
5727 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5728 unsigned InsertIdx = NonConstIdx[i];
5729 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5730 Op.getOperand(InsertIdx),
5731 DAG.getIntPtrConstant(InsertIdx, dl));
5736 /// \brief Return true if \p N implements a horizontal binop and return the
5737 /// operands for the horizontal binop into V0 and V1.
5739 /// This is a helper function of LowerToHorizontalOp().
5740 /// This function checks that the build_vector \p N in input implements a
5741 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5742 /// operation to match.
5743 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5744 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5745 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5748 /// This function only analyzes elements of \p N whose indices are
5749 /// in range [BaseIdx, LastIdx).
5750 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5752 unsigned BaseIdx, unsigned LastIdx,
5753 SDValue &V0, SDValue &V1) {
5754 EVT VT = N->getValueType(0);
5756 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5757 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5758 "Invalid Vector in input!");
5760 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5761 bool CanFold = true;
5762 unsigned ExpectedVExtractIdx = BaseIdx;
5763 unsigned NumElts = LastIdx - BaseIdx;
5764 V0 = DAG.getUNDEF(VT);
5765 V1 = DAG.getUNDEF(VT);
5767 // Check if N implements a horizontal binop.
5768 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5769 SDValue Op = N->getOperand(i + BaseIdx);
5772 if (Op->getOpcode() == ISD::UNDEF) {
5773 // Update the expected vector extract index.
5774 if (i * 2 == NumElts)
5775 ExpectedVExtractIdx = BaseIdx;
5776 ExpectedVExtractIdx += 2;
5780 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5785 SDValue Op0 = Op.getOperand(0);
5786 SDValue Op1 = Op.getOperand(1);
5788 // Try to match the following pattern:
5789 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5790 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5791 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5792 Op0.getOperand(0) == Op1.getOperand(0) &&
5793 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5794 isa<ConstantSDNode>(Op1.getOperand(1)));
5798 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5799 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5801 if (i * 2 < NumElts) {
5802 if (V0.getOpcode() == ISD::UNDEF) {
5803 V0 = Op0.getOperand(0);
5804 if (V0.getValueType() != VT)
5808 if (V1.getOpcode() == ISD::UNDEF) {
5809 V1 = Op0.getOperand(0);
5810 if (V1.getValueType() != VT)
5813 if (i * 2 == NumElts)
5814 ExpectedVExtractIdx = BaseIdx;
5817 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5818 if (I0 == ExpectedVExtractIdx)
5819 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5820 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5821 // Try to match the following dag sequence:
5822 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5823 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5827 ExpectedVExtractIdx += 2;
5833 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5834 /// a concat_vector.
5836 /// This is a helper function of LowerToHorizontalOp().
5837 /// This function expects two 256-bit vectors called V0 and V1.
5838 /// At first, each vector is split into two separate 128-bit vectors.
5839 /// Then, the resulting 128-bit vectors are used to implement two
5840 /// horizontal binary operations.
5842 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5844 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5845 /// the two new horizontal binop.
5846 /// When Mode is set, the first horizontal binop dag node would take as input
5847 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5848 /// horizontal binop dag node would take as input the lower 128-bit of V1
5849 /// and the upper 128-bit of V1.
5851 /// HADD V0_LO, V0_HI
5852 /// HADD V1_LO, V1_HI
5854 /// Otherwise, the first horizontal binop dag node takes as input the lower
5855 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5856 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5858 /// HADD V0_LO, V1_LO
5859 /// HADD V0_HI, V1_HI
5861 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5862 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5863 /// the upper 128-bits of the result.
5864 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5865 SDLoc DL, SelectionDAG &DAG,
5866 unsigned X86Opcode, bool Mode,
5867 bool isUndefLO, bool isUndefHI) {
5868 EVT VT = V0.getValueType();
5869 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5870 "Invalid nodes in input!");
5872 unsigned NumElts = VT.getVectorNumElements();
5873 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5874 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5875 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5876 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5877 EVT NewVT = V0_LO.getValueType();
5879 SDValue LO = DAG.getUNDEF(NewVT);
5880 SDValue HI = DAG.getUNDEF(NewVT);
5883 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5884 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5885 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5886 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5887 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5889 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5890 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5891 V1_LO->getOpcode() != ISD::UNDEF))
5892 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5894 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5895 V1_HI->getOpcode() != ISD::UNDEF))
5896 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5899 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5902 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5904 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5905 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5906 EVT VT = BV->getValueType(0);
5907 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5908 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5912 unsigned NumElts = VT.getVectorNumElements();
5913 SDValue InVec0 = DAG.getUNDEF(VT);
5914 SDValue InVec1 = DAG.getUNDEF(VT);
5916 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5917 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5919 // Odd-numbered elements in the input build vector are obtained from
5920 // adding two integer/float elements.
5921 // Even-numbered elements in the input build vector are obtained from
5922 // subtracting two integer/float elements.
5923 unsigned ExpectedOpcode = ISD::FSUB;
5924 unsigned NextExpectedOpcode = ISD::FADD;
5925 bool AddFound = false;
5926 bool SubFound = false;
5928 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5929 SDValue Op = BV->getOperand(i);
5931 // Skip 'undef' values.
5932 unsigned Opcode = Op.getOpcode();
5933 if (Opcode == ISD::UNDEF) {
5934 std::swap(ExpectedOpcode, NextExpectedOpcode);
5938 // Early exit if we found an unexpected opcode.
5939 if (Opcode != ExpectedOpcode)
5942 SDValue Op0 = Op.getOperand(0);
5943 SDValue Op1 = Op.getOperand(1);
5945 // Try to match the following pattern:
5946 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5947 // Early exit if we cannot match that sequence.
5948 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5949 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5950 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5951 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5952 Op0.getOperand(1) != Op1.getOperand(1))
5955 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5959 // We found a valid add/sub node. Update the information accordingly.
5965 // Update InVec0 and InVec1.
5966 if (InVec0.getOpcode() == ISD::UNDEF) {
5967 InVec0 = Op0.getOperand(0);
5968 if (InVec0.getValueType() != VT)
5971 if (InVec1.getOpcode() == ISD::UNDEF) {
5972 InVec1 = Op1.getOperand(0);
5973 if (InVec1.getValueType() != VT)
5977 // Make sure that operands in input to each add/sub node always
5978 // come from a same pair of vectors.
5979 if (InVec0 != Op0.getOperand(0)) {
5980 if (ExpectedOpcode == ISD::FSUB)
5983 // FADD is commutable. Try to commute the operands
5984 // and then test again.
5985 std::swap(Op0, Op1);
5986 if (InVec0 != Op0.getOperand(0))
5990 if (InVec1 != Op1.getOperand(0))
5993 // Update the pair of expected opcodes.
5994 std::swap(ExpectedOpcode, NextExpectedOpcode);
5997 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5998 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5999 InVec1.getOpcode() != ISD::UNDEF)
6000 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6005 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6006 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6007 const X86Subtarget *Subtarget,
6008 SelectionDAG &DAG) {
6009 EVT VT = BV->getValueType(0);
6010 unsigned NumElts = VT.getVectorNumElements();
6011 unsigned NumUndefsLO = 0;
6012 unsigned NumUndefsHI = 0;
6013 unsigned Half = NumElts/2;
6015 // Count the number of UNDEF operands in the build_vector in input.
6016 for (unsigned i = 0, e = Half; i != e; ++i)
6017 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6020 for (unsigned i = Half, e = NumElts; i != e; ++i)
6021 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6024 // Early exit if this is either a build_vector of all UNDEFs or all the
6025 // operands but one are UNDEF.
6026 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6030 SDValue InVec0, InVec1;
6031 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6032 // Try to match an SSE3 float HADD/HSUB.
6033 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6034 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6036 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6037 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6038 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6039 // Try to match an SSSE3 integer HADD/HSUB.
6040 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6041 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6043 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6044 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6047 if (!Subtarget->hasAVX())
6050 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6051 // Try to match an AVX horizontal add/sub of packed single/double
6052 // precision floating point values from 256-bit vectors.
6053 SDValue InVec2, InVec3;
6054 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6055 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6056 ((InVec0.getOpcode() == ISD::UNDEF ||
6057 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6058 ((InVec1.getOpcode() == ISD::UNDEF ||
6059 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6060 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6062 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6063 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6064 ((InVec0.getOpcode() == ISD::UNDEF ||
6065 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6066 ((InVec1.getOpcode() == ISD::UNDEF ||
6067 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6068 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6069 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6070 // Try to match an AVX2 horizontal add/sub of signed integers.
6071 SDValue InVec2, InVec3;
6073 bool CanFold = true;
6075 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6076 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6077 ((InVec0.getOpcode() == ISD::UNDEF ||
6078 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6079 ((InVec1.getOpcode() == ISD::UNDEF ||
6080 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6081 X86Opcode = X86ISD::HADD;
6082 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6083 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6084 ((InVec0.getOpcode() == ISD::UNDEF ||
6085 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6086 ((InVec1.getOpcode() == ISD::UNDEF ||
6087 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6088 X86Opcode = X86ISD::HSUB;
6093 // Fold this build_vector into a single horizontal add/sub.
6094 // Do this only if the target has AVX2.
6095 if (Subtarget->hasAVX2())
6096 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6098 // Do not try to expand this build_vector into a pair of horizontal
6099 // add/sub if we can emit a pair of scalar add/sub.
6100 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6103 // Convert this build_vector into a pair of horizontal binop followed by
6105 bool isUndefLO = NumUndefsLO == Half;
6106 bool isUndefHI = NumUndefsHI == Half;
6107 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6108 isUndefLO, isUndefHI);
6112 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6113 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6115 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6116 X86Opcode = X86ISD::HADD;
6117 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6118 X86Opcode = X86ISD::HSUB;
6119 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6120 X86Opcode = X86ISD::FHADD;
6121 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6122 X86Opcode = X86ISD::FHSUB;
6126 // Don't try to expand this build_vector into a pair of horizontal add/sub
6127 // if we can simply emit a pair of scalar add/sub.
6128 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6131 // Convert this build_vector into two horizontal add/sub followed by
6133 bool isUndefLO = NumUndefsLO == Half;
6134 bool isUndefHI = NumUndefsHI == Half;
6135 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6136 isUndefLO, isUndefHI);
6143 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6146 MVT VT = Op.getSimpleValueType();
6147 MVT ExtVT = VT.getVectorElementType();
6148 unsigned NumElems = Op.getNumOperands();
6150 // Generate vectors for predicate vectors.
6151 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6152 return LowerBUILD_VECTORvXi1(Op, DAG);
6154 // Vectors containing all zeros can be matched by pxor and xorps later
6155 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6156 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6157 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6158 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6161 return getZeroVector(VT, Subtarget, DAG, dl);
6164 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6165 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6166 // vpcmpeqd on 256-bit vectors.
6167 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6168 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6171 if (!VT.is512BitVector())
6172 return getOnesVector(VT, Subtarget, DAG, dl);
6175 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6176 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6178 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6179 return HorizontalOp;
6180 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6183 unsigned EVTBits = ExtVT.getSizeInBits();
6185 unsigned NumZero = 0;
6186 unsigned NumNonZero = 0;
6187 unsigned NonZeros = 0;
6188 bool IsAllConstants = true;
6189 SmallSet<SDValue, 8> Values;
6190 for (unsigned i = 0; i < NumElems; ++i) {
6191 SDValue Elt = Op.getOperand(i);
6192 if (Elt.getOpcode() == ISD::UNDEF)
6195 if (Elt.getOpcode() != ISD::Constant &&
6196 Elt.getOpcode() != ISD::ConstantFP)
6197 IsAllConstants = false;
6198 if (X86::isZeroNode(Elt))
6201 NonZeros |= (1 << i);
6206 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6207 if (NumNonZero == 0)
6208 return DAG.getUNDEF(VT);
6210 // Special case for single non-zero, non-undef, element.
6211 if (NumNonZero == 1) {
6212 unsigned Idx = countTrailingZeros(NonZeros);
6213 SDValue Item = Op.getOperand(Idx);
6215 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6216 // the value are obviously zero, truncate the value to i32 and do the
6217 // insertion that way. Only do this if the value is non-constant or if the
6218 // value is a constant being inserted into element 0. It is cheaper to do
6219 // a constant pool load than it is to do a movd + shuffle.
6220 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6221 (!IsAllConstants || Idx == 0)) {
6222 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6224 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6225 EVT VecVT = MVT::v4i32;
6227 // Truncate the value (which may itself be a constant) to i32, and
6228 // convert it to a vector with movd (S2V+shuffle to zero extend).
6229 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6230 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6231 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6232 Item, Idx * 2, true, Subtarget, DAG));
6236 // If we have a constant or non-constant insertion into the low element of
6237 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6238 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6239 // depending on what the source datatype is.
6242 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6244 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6245 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6246 if (VT.is512BitVector()) {
6247 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6248 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6249 Item, DAG.getIntPtrConstant(0, dl));
6251 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6252 "Expected an SSE value type!");
6253 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6254 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6255 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6258 // We can't directly insert an i8 or i16 into a vector, so zero extend
6260 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6261 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6262 if (VT.is256BitVector()) {
6263 if (Subtarget->hasAVX()) {
6264 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6265 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6267 // Without AVX, we need to extend to a 128-bit vector and then
6268 // insert into the 256-bit vector.
6269 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6270 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6271 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6274 assert(VT.is128BitVector() && "Expected an SSE value type!");
6275 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6276 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6278 return DAG.getBitcast(VT, Item);
6282 // Is it a vector logical left shift?
6283 if (NumElems == 2 && Idx == 1 &&
6284 X86::isZeroNode(Op.getOperand(0)) &&
6285 !X86::isZeroNode(Op.getOperand(1))) {
6286 unsigned NumBits = VT.getSizeInBits();
6287 return getVShift(true, VT,
6288 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6289 VT, Op.getOperand(1)),
6290 NumBits/2, DAG, *this, dl);
6293 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6296 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6297 // is a non-constant being inserted into an element other than the low one,
6298 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6299 // movd/movss) to move this into the low element, then shuffle it into
6301 if (EVTBits == 32) {
6302 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6303 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6307 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6308 if (Values.size() == 1) {
6309 if (EVTBits == 32) {
6310 // Instead of a shuffle like this:
6311 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6312 // Check if it's possible to issue this instead.
6313 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6314 unsigned Idx = countTrailingZeros(NonZeros);
6315 SDValue Item = Op.getOperand(Idx);
6316 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6317 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6322 // A vector full of immediates; various special cases are already
6323 // handled, so this is best done with a single constant-pool load.
6327 // For AVX-length vectors, see if we can use a vector load to get all of the
6328 // elements, otherwise build the individual 128-bit pieces and use
6329 // shuffles to put them in place.
6330 if (VT.is256BitVector() || VT.is512BitVector()) {
6331 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6333 // Check for a build vector of consecutive loads.
6334 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6337 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6339 // Build both the lower and upper subvector.
6340 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6341 makeArrayRef(&V[0], NumElems/2));
6342 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6343 makeArrayRef(&V[NumElems / 2], NumElems/2));
6345 // Recreate the wider vector with the lower and upper part.
6346 if (VT.is256BitVector())
6347 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6348 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6351 // Let legalizer expand 2-wide build_vectors.
6352 if (EVTBits == 64) {
6353 if (NumNonZero == 1) {
6354 // One half is zero or undef.
6355 unsigned Idx = countTrailingZeros(NonZeros);
6356 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6357 Op.getOperand(Idx));
6358 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6363 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6364 if (EVTBits == 8 && NumElems == 16)
6365 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6369 if (EVTBits == 16 && NumElems == 8)
6370 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6374 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6375 if (EVTBits == 32 && NumElems == 4)
6376 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6379 // If element VT is == 32 bits, turn it into a number of shuffles.
6380 SmallVector<SDValue, 8> V(NumElems);
6381 if (NumElems == 4 && NumZero > 0) {
6382 for (unsigned i = 0; i < 4; ++i) {
6383 bool isZero = !(NonZeros & (1 << i));
6385 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6387 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6390 for (unsigned i = 0; i < 2; ++i) {
6391 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6394 V[i] = V[i*2]; // Must be a zero vector.
6397 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6400 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6403 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6408 bool Reverse1 = (NonZeros & 0x3) == 2;
6409 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6413 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6414 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6416 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6419 if (Values.size() > 1 && VT.is128BitVector()) {
6420 // Check for a build vector of consecutive loads.
6421 for (unsigned i = 0; i < NumElems; ++i)
6422 V[i] = Op.getOperand(i);
6424 // Check for elements which are consecutive loads.
6425 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6428 // Check for a build vector from mostly shuffle plus few inserting.
6429 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6432 // For SSE 4.1, use insertps to put the high elements into the low element.
6433 if (Subtarget->hasSSE41()) {
6435 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6436 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6438 Result = DAG.getUNDEF(VT);
6440 for (unsigned i = 1; i < NumElems; ++i) {
6441 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6442 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6443 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6448 // Otherwise, expand into a number of unpckl*, start by extending each of
6449 // our (non-undef) elements to the full vector width with the element in the
6450 // bottom slot of the vector (which generates no code for SSE).
6451 for (unsigned i = 0; i < NumElems; ++i) {
6452 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6453 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6455 V[i] = DAG.getUNDEF(VT);
6458 // Next, we iteratively mix elements, e.g. for v4f32:
6459 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6460 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6461 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6462 unsigned EltStride = NumElems >> 1;
6463 while (EltStride != 0) {
6464 for (unsigned i = 0; i < EltStride; ++i) {
6465 // If V[i+EltStride] is undef and this is the first round of mixing,
6466 // then it is safe to just drop this shuffle: V[i] is already in the
6467 // right place, the one element (since it's the first round) being
6468 // inserted as undef can be dropped. This isn't safe for successive
6469 // rounds because they will permute elements within both vectors.
6470 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6471 EltStride == NumElems/2)
6474 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6483 // 256-bit AVX can use the vinsertf128 instruction
6484 // to create 256-bit vectors from two other 128-bit ones.
6485 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6487 MVT ResVT = Op.getSimpleValueType();
6489 assert((ResVT.is256BitVector() ||
6490 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6492 SDValue V1 = Op.getOperand(0);
6493 SDValue V2 = Op.getOperand(1);
6494 unsigned NumElems = ResVT.getVectorNumElements();
6495 if (ResVT.is256BitVector())
6496 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6498 if (Op.getNumOperands() == 4) {
6499 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6500 ResVT.getVectorNumElements()/2);
6501 SDValue V3 = Op.getOperand(2);
6502 SDValue V4 = Op.getOperand(3);
6503 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6504 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6506 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6509 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6510 const X86Subtarget *Subtarget,
6511 SelectionDAG & DAG) {
6513 MVT ResVT = Op.getSimpleValueType();
6514 unsigned NumOfOperands = Op.getNumOperands();
6516 assert(isPowerOf2_32(NumOfOperands) &&
6517 "Unexpected number of operands in CONCAT_VECTORS");
6519 if (NumOfOperands > 2) {
6520 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6521 ResVT.getVectorNumElements()/2);
6522 SmallVector<SDValue, 2> Ops;
6523 for (unsigned i = 0; i < NumOfOperands/2; i++)
6524 Ops.push_back(Op.getOperand(i));
6525 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6527 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6528 Ops.push_back(Op.getOperand(i));
6529 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6530 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6533 SDValue V1 = Op.getOperand(0);
6534 SDValue V2 = Op.getOperand(1);
6535 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6536 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6538 if (IsZeroV1 && IsZeroV2)
6539 return getZeroVector(ResVT, Subtarget, DAG, dl);
6541 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6542 SDValue Undef = DAG.getUNDEF(ResVT);
6543 unsigned NumElems = ResVT.getVectorNumElements();
6544 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6546 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6547 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6551 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6552 // Zero the upper bits of V1
6553 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6554 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6557 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6560 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6561 const X86Subtarget *Subtarget,
6562 SelectionDAG &DAG) {
6563 MVT VT = Op.getSimpleValueType();
6564 if (VT.getVectorElementType() == MVT::i1)
6565 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6567 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6568 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6569 Op.getNumOperands() == 4)));
6571 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6572 // from two other 128-bit ones.
6574 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6575 return LowerAVXCONCAT_VECTORS(Op, DAG);
6578 //===----------------------------------------------------------------------===//
6579 // Vector shuffle lowering
6581 // This is an experimental code path for lowering vector shuffles on x86. It is
6582 // designed to handle arbitrary vector shuffles and blends, gracefully
6583 // degrading performance as necessary. It works hard to recognize idiomatic
6584 // shuffles and lower them to optimal instruction patterns without leaving
6585 // a framework that allows reasonably efficient handling of all vector shuffle
6587 //===----------------------------------------------------------------------===//
6589 /// \brief Tiny helper function to identify a no-op mask.
6591 /// This is a somewhat boring predicate function. It checks whether the mask
6592 /// array input, which is assumed to be a single-input shuffle mask of the kind
6593 /// used by the X86 shuffle instructions (not a fully general
6594 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6595 /// in-place shuffle are 'no-op's.
6596 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6597 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6598 if (Mask[i] != -1 && Mask[i] != i)
6603 /// \brief Helper function to classify a mask as a single-input mask.
6605 /// This isn't a generic single-input test because in the vector shuffle
6606 /// lowering we canonicalize single inputs to be the first input operand. This
6607 /// means we can more quickly test for a single input by only checking whether
6608 /// an input from the second operand exists. We also assume that the size of
6609 /// mask corresponds to the size of the input vectors which isn't true in the
6610 /// fully general case.
6611 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6613 if (M >= (int)Mask.size())
6618 /// \brief Test whether there are elements crossing 128-bit lanes in this
6621 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6622 /// and we routinely test for these.
6623 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6624 int LaneSize = 128 / VT.getScalarSizeInBits();
6625 int Size = Mask.size();
6626 for (int i = 0; i < Size; ++i)
6627 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6632 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6634 /// This checks a shuffle mask to see if it is performing the same
6635 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6636 /// that it is also not lane-crossing. It may however involve a blend from the
6637 /// same lane of a second vector.
6639 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6640 /// non-trivial to compute in the face of undef lanes. The representation is
6641 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6642 /// entries from both V1 and V2 inputs to the wider mask.
6644 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6645 SmallVectorImpl<int> &RepeatedMask) {
6646 int LaneSize = 128 / VT.getScalarSizeInBits();
6647 RepeatedMask.resize(LaneSize, -1);
6648 int Size = Mask.size();
6649 for (int i = 0; i < Size; ++i) {
6652 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6653 // This entry crosses lanes, so there is no way to model this shuffle.
6656 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6657 if (RepeatedMask[i % LaneSize] == -1)
6658 // This is the first non-undef entry in this slot of a 128-bit lane.
6659 RepeatedMask[i % LaneSize] =
6660 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6661 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6662 // Found a mismatch with the repeated mask.
6668 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6671 /// This is a fast way to test a shuffle mask against a fixed pattern:
6673 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6675 /// It returns true if the mask is exactly as wide as the argument list, and
6676 /// each element of the mask is either -1 (signifying undef) or the value given
6677 /// in the argument.
6678 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6679 ArrayRef<int> ExpectedMask) {
6680 if (Mask.size() != ExpectedMask.size())
6683 int Size = Mask.size();
6685 // If the values are build vectors, we can look through them to find
6686 // equivalent inputs that make the shuffles equivalent.
6687 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6688 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6690 for (int i = 0; i < Size; ++i)
6691 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6692 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6693 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6694 if (!MaskBV || !ExpectedBV ||
6695 MaskBV->getOperand(Mask[i] % Size) !=
6696 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6703 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6705 /// This helper function produces an 8-bit shuffle immediate corresponding to
6706 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6707 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6710 /// NB: We rely heavily on "undef" masks preserving the input lane.
6711 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6712 SelectionDAG &DAG) {
6713 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6714 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6715 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6716 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6717 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6720 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6721 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6722 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6723 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6724 return DAG.getConstant(Imm, DL, MVT::i8);
6727 /// \brief Compute whether each element of a shuffle is zeroable.
6729 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6730 /// Either it is an undef element in the shuffle mask, the element of the input
6731 /// referenced is undef, or the element of the input referenced is known to be
6732 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6733 /// as many lanes with this technique as possible to simplify the remaining
6735 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6736 SDValue V1, SDValue V2) {
6737 SmallBitVector Zeroable(Mask.size(), false);
6739 while (V1.getOpcode() == ISD::BITCAST)
6740 V1 = V1->getOperand(0);
6741 while (V2.getOpcode() == ISD::BITCAST)
6742 V2 = V2->getOperand(0);
6744 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6745 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6747 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6749 // Handle the easy cases.
6750 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6755 // If this is an index into a build_vector node (which has the same number
6756 // of elements), dig out the input value and use it.
6757 SDValue V = M < Size ? V1 : V2;
6758 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6761 SDValue Input = V.getOperand(M % Size);
6762 // The UNDEF opcode check really should be dead code here, but not quite
6763 // worth asserting on (it isn't invalid, just unexpected).
6764 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6771 // X86 has dedicated unpack instructions that can handle specific blend
6772 // operations: UNPCKH and UNPCKL.
6773 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6774 SDValue V1, SDValue V2,
6775 SelectionDAG &DAG) {
6776 int NumElts = VT.getVectorNumElements();
6779 bool UnpcklSwapped = true;
6780 bool UnpckhSwapped = true;
6781 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6783 for (int i = 0; i < NumElts; ++i) {
6784 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6786 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6787 int HiPos = LoPos + NumEltsInLane / 2;
6788 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6789 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6793 if (Mask[i] != LoPos)
6795 if (Mask[i] != HiPos)
6797 if (Mask[i] != LoPosSwapped)
6798 UnpcklSwapped = false;
6799 if (Mask[i] != HiPosSwapped)
6800 UnpckhSwapped = false;
6801 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6805 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6807 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6809 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6811 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6813 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6817 /// \brief Try to emit a bitmask instruction for a shuffle.
6819 /// This handles cases where we can model a blend exactly as a bitmask due to
6820 /// one of the inputs being zeroable.
6821 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6822 SDValue V2, ArrayRef<int> Mask,
6823 SelectionDAG &DAG) {
6824 MVT EltVT = VT.getScalarType();
6825 int NumEltBits = EltVT.getSizeInBits();
6826 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6827 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6828 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6830 if (EltVT.isFloatingPoint()) {
6831 Zero = DAG.getBitcast(EltVT, Zero);
6832 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6834 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6835 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6837 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6840 if (Mask[i] % Size != i)
6841 return SDValue(); // Not a blend.
6843 V = Mask[i] < Size ? V1 : V2;
6844 else if (V != (Mask[i] < Size ? V1 : V2))
6845 return SDValue(); // Can only let one input through the mask.
6847 VMaskOps[i] = AllOnes;
6850 return SDValue(); // No non-zeroable elements!
6852 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6853 V = DAG.getNode(VT.isFloatingPoint()
6854 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6859 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6861 /// This is used as a fallback approach when first class blend instructions are
6862 /// unavailable. Currently it is only suitable for integer vectors, but could
6863 /// be generalized for floating point vectors if desirable.
6864 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6865 SDValue V2, ArrayRef<int> Mask,
6866 SelectionDAG &DAG) {
6867 assert(VT.isInteger() && "Only supports integer vector types!");
6868 MVT EltVT = VT.getScalarType();
6869 int NumEltBits = EltVT.getSizeInBits();
6870 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6871 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6873 SmallVector<SDValue, 16> MaskOps;
6874 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6875 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6876 return SDValue(); // Shuffled input!
6877 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6880 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6881 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6882 // We have to cast V2 around.
6883 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6884 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6885 DAG.getBitcast(MaskVT, V1Mask),
6886 DAG.getBitcast(MaskVT, V2)));
6887 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6890 /// \brief Try to emit a blend instruction for a shuffle.
6892 /// This doesn't do any checks for the availability of instructions for blending
6893 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6894 /// be matched in the backend with the type given. What it does check for is
6895 /// that the shuffle mask is in fact a blend.
6896 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6897 SDValue V2, ArrayRef<int> Mask,
6898 const X86Subtarget *Subtarget,
6899 SelectionDAG &DAG) {
6900 unsigned BlendMask = 0;
6901 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6902 if (Mask[i] >= Size) {
6903 if (Mask[i] != i + Size)
6904 return SDValue(); // Shuffled V2 input!
6905 BlendMask |= 1u << i;
6908 if (Mask[i] >= 0 && Mask[i] != i)
6909 return SDValue(); // Shuffled V1 input!
6911 switch (VT.SimpleTy) {
6916 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6917 DAG.getConstant(BlendMask, DL, MVT::i8));
6921 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6925 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6926 // that instruction.
6927 if (Subtarget->hasAVX2()) {
6928 // Scale the blend by the number of 32-bit dwords per element.
6929 int Scale = VT.getScalarSizeInBits() / 32;
6931 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6932 if (Mask[i] >= Size)
6933 for (int j = 0; j < Scale; ++j)
6934 BlendMask |= 1u << (i * Scale + j);
6936 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6937 V1 = DAG.getBitcast(BlendVT, V1);
6938 V2 = DAG.getBitcast(BlendVT, V2);
6939 return DAG.getBitcast(
6940 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6941 DAG.getConstant(BlendMask, DL, MVT::i8)));
6945 // For integer shuffles we need to expand the mask and cast the inputs to
6946 // v8i16s prior to blending.
6947 int Scale = 8 / VT.getVectorNumElements();
6949 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6950 if (Mask[i] >= Size)
6951 for (int j = 0; j < Scale; ++j)
6952 BlendMask |= 1u << (i * Scale + j);
6954 V1 = DAG.getBitcast(MVT::v8i16, V1);
6955 V2 = DAG.getBitcast(MVT::v8i16, V2);
6956 return DAG.getBitcast(VT,
6957 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6958 DAG.getConstant(BlendMask, DL, MVT::i8)));
6962 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6963 SmallVector<int, 8> RepeatedMask;
6964 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6965 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6966 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6968 for (int i = 0; i < 8; ++i)
6969 if (RepeatedMask[i] >= 16)
6970 BlendMask |= 1u << i;
6971 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6972 DAG.getConstant(BlendMask, DL, MVT::i8));
6978 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6979 "256-bit byte-blends require AVX2 support!");
6981 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6982 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6985 // Scale the blend by the number of bytes per element.
6986 int Scale = VT.getScalarSizeInBits() / 8;
6988 // This form of blend is always done on bytes. Compute the byte vector
6990 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6992 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6993 // mix of LLVM's code generator and the x86 backend. We tell the code
6994 // generator that boolean values in the elements of an x86 vector register
6995 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6996 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6997 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6998 // of the element (the remaining are ignored) and 0 in that high bit would
6999 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7000 // the LLVM model for boolean values in vector elements gets the relevant
7001 // bit set, it is set backwards and over constrained relative to x86's
7003 SmallVector<SDValue, 32> VSELECTMask;
7004 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7005 for (int j = 0; j < Scale; ++j)
7006 VSELECTMask.push_back(
7007 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7008 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7011 V1 = DAG.getBitcast(BlendVT, V1);
7012 V2 = DAG.getBitcast(BlendVT, V2);
7013 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7014 DAG.getNode(ISD::BUILD_VECTOR, DL,
7015 BlendVT, VSELECTMask),
7020 llvm_unreachable("Not a supported integer vector type!");
7024 /// \brief Try to lower as a blend of elements from two inputs followed by
7025 /// a single-input permutation.
7027 /// This matches the pattern where we can blend elements from two inputs and
7028 /// then reduce the shuffle to a single-input permutation.
7029 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7032 SelectionDAG &DAG) {
7033 // We build up the blend mask while checking whether a blend is a viable way
7034 // to reduce the shuffle.
7035 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7036 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7038 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7042 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7044 if (BlendMask[Mask[i] % Size] == -1)
7045 BlendMask[Mask[i] % Size] = Mask[i];
7046 else if (BlendMask[Mask[i] % Size] != Mask[i])
7047 return SDValue(); // Can't blend in the needed input!
7049 PermuteMask[i] = Mask[i] % Size;
7052 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7053 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7056 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7057 /// blends and permutes.
7059 /// This matches the extremely common pattern for handling combined
7060 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7061 /// operations. It will try to pick the best arrangement of shuffles and
7063 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7067 SelectionDAG &DAG) {
7068 // Shuffle the input elements into the desired positions in V1 and V2 and
7069 // blend them together.
7070 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7071 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7072 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7073 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7074 if (Mask[i] >= 0 && Mask[i] < Size) {
7075 V1Mask[i] = Mask[i];
7077 } else if (Mask[i] >= Size) {
7078 V2Mask[i] = Mask[i] - Size;
7079 BlendMask[i] = i + Size;
7082 // Try to lower with the simpler initial blend strategy unless one of the
7083 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7084 // shuffle may be able to fold with a load or other benefit. However, when
7085 // we'll have to do 2x as many shuffles in order to achieve this, blending
7086 // first is a better strategy.
7087 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7088 if (SDValue BlendPerm =
7089 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7092 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7093 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7094 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7097 /// \brief Try to lower a vector shuffle as a byte rotation.
7099 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7100 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7101 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7102 /// try to generically lower a vector shuffle through such an pattern. It
7103 /// does not check for the profitability of lowering either as PALIGNR or
7104 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7105 /// This matches shuffle vectors that look like:
7107 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7109 /// Essentially it concatenates V1 and V2, shifts right by some number of
7110 /// elements, and takes the low elements as the result. Note that while this is
7111 /// specified as a *right shift* because x86 is little-endian, it is a *left
7112 /// rotate* of the vector lanes.
7113 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7116 const X86Subtarget *Subtarget,
7117 SelectionDAG &DAG) {
7118 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7120 int NumElts = Mask.size();
7121 int NumLanes = VT.getSizeInBits() / 128;
7122 int NumLaneElts = NumElts / NumLanes;
7124 // We need to detect various ways of spelling a rotation:
7125 // [11, 12, 13, 14, 15, 0, 1, 2]
7126 // [-1, 12, 13, 14, -1, -1, 1, -1]
7127 // [-1, -1, -1, -1, -1, -1, 1, 2]
7128 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7129 // [-1, 4, 5, 6, -1, -1, 9, -1]
7130 // [-1, 4, 5, 6, -1, -1, -1, -1]
7133 for (int l = 0; l < NumElts; l += NumLaneElts) {
7134 for (int i = 0; i < NumLaneElts; ++i) {
7135 if (Mask[l + i] == -1)
7137 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7139 // Get the mod-Size index and lane correct it.
7140 int LaneIdx = (Mask[l + i] % NumElts) - l;
7141 // Make sure it was in this lane.
7142 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7145 // Determine where a rotated vector would have started.
7146 int StartIdx = i - LaneIdx;
7148 // The identity rotation isn't interesting, stop.
7151 // If we found the tail of a vector the rotation must be the missing
7152 // front. If we found the head of a vector, it must be how much of the
7154 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7157 Rotation = CandidateRotation;
7158 else if (Rotation != CandidateRotation)
7159 // The rotations don't match, so we can't match this mask.
7162 // Compute which value this mask is pointing at.
7163 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7165 // Compute which of the two target values this index should be assigned
7166 // to. This reflects whether the high elements are remaining or the low
7167 // elements are remaining.
7168 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7170 // Either set up this value if we've not encountered it before, or check
7171 // that it remains consistent.
7174 else if (TargetV != MaskV)
7175 // This may be a rotation, but it pulls from the inputs in some
7176 // unsupported interleaving.
7181 // Check that we successfully analyzed the mask, and normalize the results.
7182 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7183 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7189 // The actual rotate instruction rotates bytes, so we need to scale the
7190 // rotation based on how many bytes are in the vector lane.
7191 int Scale = 16 / NumLaneElts;
7193 // SSSE3 targets can use the palignr instruction.
7194 if (Subtarget->hasSSSE3()) {
7195 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7196 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7197 Lo = DAG.getBitcast(AlignVT, Lo);
7198 Hi = DAG.getBitcast(AlignVT, Hi);
7200 return DAG.getBitcast(
7201 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7202 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7205 assert(VT.getSizeInBits() == 128 &&
7206 "Rotate-based lowering only supports 128-bit lowering!");
7207 assert(Mask.size() <= 16 &&
7208 "Can shuffle at most 16 bytes in a 128-bit vector!");
7210 // Default SSE2 implementation
7211 int LoByteShift = 16 - Rotation * Scale;
7212 int HiByteShift = Rotation * Scale;
7214 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7215 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7216 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7218 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7219 DAG.getConstant(LoByteShift, DL, MVT::i8));
7220 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7221 DAG.getConstant(HiByteShift, DL, MVT::i8));
7222 return DAG.getBitcast(VT,
7223 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7226 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7228 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7229 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7230 /// matches elements from one of the input vectors shuffled to the left or
7231 /// right with zeroable elements 'shifted in'. It handles both the strictly
7232 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7235 /// PSHL : (little-endian) left bit shift.
7236 /// [ zz, 0, zz, 2 ]
7237 /// [ -1, 4, zz, -1 ]
7238 /// PSRL : (little-endian) right bit shift.
7240 /// [ -1, -1, 7, zz]
7241 /// PSLLDQ : (little-endian) left byte shift
7242 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7243 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7244 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7245 /// PSRLDQ : (little-endian) right byte shift
7246 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7247 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7248 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7249 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7250 SDValue V2, ArrayRef<int> Mask,
7251 SelectionDAG &DAG) {
7252 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7254 int Size = Mask.size();
7255 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7257 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7258 for (int i = 0; i < Size; i += Scale)
7259 for (int j = 0; j < Shift; ++j)
7260 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7266 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7267 for (int i = 0; i != Size; i += Scale) {
7268 unsigned Pos = Left ? i + Shift : i;
7269 unsigned Low = Left ? i : i + Shift;
7270 unsigned Len = Scale - Shift;
7271 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7272 Low + (V == V1 ? 0 : Size)))
7276 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7277 bool ByteShift = ShiftEltBits > 64;
7278 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7279 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7280 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7282 // Normalize the scale for byte shifts to still produce an i64 element
7284 Scale = ByteShift ? Scale / 2 : Scale;
7286 // We need to round trip through the appropriate type for the shift.
7287 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7288 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7289 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7290 "Illegal integer vector type");
7291 V = DAG.getBitcast(ShiftVT, V);
7293 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7294 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7295 return DAG.getBitcast(VT, V);
7298 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7299 // keep doubling the size of the integer elements up to that. We can
7300 // then shift the elements of the integer vector by whole multiples of
7301 // their width within the elements of the larger integer vector. Test each
7302 // multiple to see if we can find a match with the moved element indices
7303 // and that the shifted in elements are all zeroable.
7304 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7305 for (int Shift = 1; Shift != Scale; ++Shift)
7306 for (bool Left : {true, false})
7307 if (CheckZeros(Shift, Scale, Left))
7308 for (SDValue V : {V1, V2})
7309 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7316 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7317 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7318 SDValue V2, ArrayRef<int> Mask,
7319 SelectionDAG &DAG) {
7320 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7321 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7323 int Size = Mask.size();
7324 int HalfSize = Size / 2;
7325 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7327 // Upper half must be undefined.
7328 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7331 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7332 // Remainder of lower half result is zero and upper half is all undef.
7333 auto LowerAsEXTRQ = [&]() {
7334 // Determine the extraction length from the part of the
7335 // lower half that isn't zeroable.
7337 for (; Len >= 0; --Len)
7338 if (!Zeroable[Len - 1])
7340 assert(Len > 0 && "Zeroable shuffle mask");
7342 // Attempt to match first Len sequential elements from the lower half.
7345 for (int i = 0; i != Len; ++i) {
7349 SDValue &V = (M < Size ? V1 : V2);
7352 // All mask elements must be in the lower half.
7356 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7367 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7368 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7369 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7370 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7371 DAG.getConstant(BitLen, DL, MVT::i8),
7372 DAG.getConstant(BitIdx, DL, MVT::i8));
7375 if (SDValue ExtrQ = LowerAsEXTRQ())
7378 // INSERTQ: Extract lowest Len elements from lower half of second source and
7379 // insert over first source, starting at Idx.
7380 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7381 auto LowerAsInsertQ = [&]() {
7382 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7385 // Attempt to match first source from mask before insertion point.
7386 if (isUndefInRange(Mask, 0, Idx)) {
7388 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7390 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7396 // Extend the extraction length looking to match both the insertion of
7397 // the second source and the remaining elements of the first.
7398 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7403 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7405 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7411 // Match the remaining elements of the lower half.
7412 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7414 } else if ((!Base || (Base == V1)) &&
7415 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7417 } else if ((!Base || (Base == V2)) &&
7418 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7425 // We may not have a base (first source) - this can safely be undefined.
7427 Base = DAG.getUNDEF(VT);
7429 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7430 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7431 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7432 DAG.getConstant(BitLen, DL, MVT::i8),
7433 DAG.getConstant(BitIdx, DL, MVT::i8));
7440 if (SDValue InsertQ = LowerAsInsertQ())
7446 /// \brief Lower a vector shuffle as a zero or any extension.
7448 /// Given a specific number of elements, element bit width, and extension
7449 /// stride, produce either a zero or any extension based on the available
7450 /// features of the subtarget. The extended elements are consecutive and
7451 /// begin and can start from an offseted element index in the input; to
7452 /// avoid excess shuffling the offset must either being in the bottom lane
7453 /// or at the start of a higher lane. All extended elements must be from
7455 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7456 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7457 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7458 assert(Scale > 1 && "Need a scale to extend.");
7459 int EltBits = VT.getScalarSizeInBits();
7460 int NumElements = VT.getVectorNumElements();
7461 int NumEltsPerLane = 128 / EltBits;
7462 int OffsetLane = Offset / NumEltsPerLane;
7463 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7464 "Only 8, 16, and 32 bit elements can be extended.");
7465 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7466 assert(0 <= Offset && "Extension offset must be positive.");
7467 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7468 "Extension offset must be in the first lane or start an upper lane.");
7470 // Check that an index is in same lane as the base offset.
7471 auto SafeOffset = [&](int Idx) {
7472 return OffsetLane == (Idx / NumEltsPerLane);
7475 // Shift along an input so that the offset base moves to the first element.
7476 auto ShuffleOffset = [&](SDValue V) {
7480 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7481 for (int i = 0; i * Scale < NumElements; ++i) {
7482 int SrcIdx = i + Offset;
7483 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7485 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7488 // Found a valid zext mask! Try various lowering strategies based on the
7489 // input type and available ISA extensions.
7490 if (Subtarget->hasSSE41()) {
7491 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7492 // PUNPCK will catch this in a later shuffle match.
7493 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7495 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7496 NumElements / Scale);
7497 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7498 return DAG.getBitcast(VT, InputV);
7501 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7503 // For any extends we can cheat for larger element sizes and use shuffle
7504 // instructions that can fold with a load and/or copy.
7505 if (AnyExt && EltBits == 32) {
7506 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7508 return DAG.getBitcast(
7509 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7510 DAG.getBitcast(MVT::v4i32, InputV),
7511 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7513 if (AnyExt && EltBits == 16 && Scale > 2) {
7514 int PSHUFDMask[4] = {Offset / 2, -1,
7515 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7516 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7517 DAG.getBitcast(MVT::v4i32, InputV),
7518 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7519 int PSHUFWMask[4] = {1, -1, -1, -1};
7520 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7521 return DAG.getBitcast(
7522 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7523 DAG.getBitcast(MVT::v8i16, InputV),
7524 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7527 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7529 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7530 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7531 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7533 int LoIdx = Offset * EltBits;
7534 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7535 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7536 DAG.getConstant(EltBits, DL, MVT::i8),
7537 DAG.getConstant(LoIdx, DL, MVT::i8)));
7539 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7540 !SafeOffset(Offset + 1))
7541 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7543 int HiIdx = (Offset + 1) * EltBits;
7544 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7545 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7546 DAG.getConstant(EltBits, DL, MVT::i8),
7547 DAG.getConstant(HiIdx, DL, MVT::i8)));
7548 return DAG.getNode(ISD::BITCAST, DL, VT,
7549 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7552 // If this would require more than 2 unpack instructions to expand, use
7553 // pshufb when available. We can only use more than 2 unpack instructions
7554 // when zero extending i8 elements which also makes it easier to use pshufb.
7555 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7556 assert(NumElements == 16 && "Unexpected byte vector width!");
7557 SDValue PSHUFBMask[16];
7558 for (int i = 0; i < 16; ++i) {
7559 int Idx = Offset + (i / Scale);
7560 PSHUFBMask[i] = DAG.getConstant(
7561 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7563 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7564 return DAG.getBitcast(VT,
7565 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7566 DAG.getNode(ISD::BUILD_VECTOR, DL,
7567 MVT::v16i8, PSHUFBMask)));
7570 // If we are extending from an offset, ensure we start on a boundary that
7571 // we can unpack from.
7572 int AlignToUnpack = Offset % (NumElements / Scale);
7573 if (AlignToUnpack) {
7574 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7575 for (int i = AlignToUnpack; i < NumElements; ++i)
7576 ShMask[i - AlignToUnpack] = i;
7577 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7578 Offset -= AlignToUnpack;
7581 // Otherwise emit a sequence of unpacks.
7583 unsigned UnpackLoHi = X86ISD::UNPCKL;
7584 if (Offset >= (NumElements / 2)) {
7585 UnpackLoHi = X86ISD::UNPCKH;
7586 Offset -= (NumElements / 2);
7589 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7590 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7591 : getZeroVector(InputVT, Subtarget, DAG, DL);
7592 InputV = DAG.getBitcast(InputVT, InputV);
7593 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7597 } while (Scale > 1);
7598 return DAG.getBitcast(VT, InputV);
7601 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7603 /// This routine will try to do everything in its power to cleverly lower
7604 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7605 /// check for the profitability of this lowering, it tries to aggressively
7606 /// match this pattern. It will use all of the micro-architectural details it
7607 /// can to emit an efficient lowering. It handles both blends with all-zero
7608 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7609 /// masking out later).
7611 /// The reason we have dedicated lowering for zext-style shuffles is that they
7612 /// are both incredibly common and often quite performance sensitive.
7613 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7614 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7615 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7616 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7618 int Bits = VT.getSizeInBits();
7619 int NumLanes = Bits / 128;
7620 int NumElements = VT.getVectorNumElements();
7621 int NumEltsPerLane = NumElements / NumLanes;
7622 assert(VT.getScalarSizeInBits() <= 32 &&
7623 "Exceeds 32-bit integer zero extension limit");
7624 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7626 // Define a helper function to check a particular ext-scale and lower to it if
7628 auto Lower = [&](int Scale) -> SDValue {
7633 for (int i = 0; i < NumElements; ++i) {
7636 continue; // Valid anywhere but doesn't tell us anything.
7637 if (i % Scale != 0) {
7638 // Each of the extended elements need to be zeroable.
7642 // We no longer are in the anyext case.
7647 // Each of the base elements needs to be consecutive indices into the
7648 // same input vector.
7649 SDValue V = M < NumElements ? V1 : V2;
7650 M = M % NumElements;
7653 Offset = M - (i / Scale);
7654 } else if (InputV != V)
7655 return SDValue(); // Flip-flopping inputs.
7657 // Offset must start in the lowest 128-bit lane or at the start of an
7659 // FIXME: Is it ever worth allowing a negative base offset?
7660 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7661 (Offset % NumEltsPerLane) == 0))
7664 // If we are offsetting, all referenced entries must come from the same
7666 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7669 if ((M % NumElements) != (Offset + (i / Scale)))
7670 return SDValue(); // Non-consecutive strided elements.
7674 // If we fail to find an input, we have a zero-shuffle which should always
7675 // have already been handled.
7676 // FIXME: Maybe handle this here in case during blending we end up with one?
7680 // If we are offsetting, don't extend if we only match a single input, we
7681 // can always do better by using a basic PSHUF or PUNPCK.
7682 if (Offset != 0 && Matches < 2)
7685 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7686 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7689 // The widest scale possible for extending is to a 64-bit integer.
7690 assert(Bits % 64 == 0 &&
7691 "The number of bits in a vector must be divisible by 64 on x86!");
7692 int NumExtElements = Bits / 64;
7694 // Each iteration, try extending the elements half as much, but into twice as
7696 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7697 assert(NumElements % NumExtElements == 0 &&
7698 "The input vector size must be divisible by the extended size.");
7699 if (SDValue V = Lower(NumElements / NumExtElements))
7703 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7707 // Returns one of the source operands if the shuffle can be reduced to a
7708 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7709 auto CanZExtLowHalf = [&]() {
7710 for (int i = NumElements / 2; i != NumElements; ++i)
7713 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7715 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7720 if (SDValue V = CanZExtLowHalf()) {
7721 V = DAG.getBitcast(MVT::v2i64, V);
7722 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7723 return DAG.getBitcast(VT, V);
7726 // No viable ext lowering found.
7730 /// \brief Try to get a scalar value for a specific element of a vector.
7732 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7733 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7734 SelectionDAG &DAG) {
7735 MVT VT = V.getSimpleValueType();
7736 MVT EltVT = VT.getVectorElementType();
7737 while (V.getOpcode() == ISD::BITCAST)
7738 V = V.getOperand(0);
7739 // If the bitcasts shift the element size, we can't extract an equivalent
7741 MVT NewVT = V.getSimpleValueType();
7742 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7745 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7746 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7747 // Ensure the scalar operand is the same size as the destination.
7748 // FIXME: Add support for scalar truncation where possible.
7749 SDValue S = V.getOperand(Idx);
7750 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7751 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7757 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7759 /// This is particularly important because the set of instructions varies
7760 /// significantly based on whether the operand is a load or not.
7761 static bool isShuffleFoldableLoad(SDValue V) {
7762 while (V.getOpcode() == ISD::BITCAST)
7763 V = V.getOperand(0);
7765 return ISD::isNON_EXTLoad(V.getNode());
7768 /// \brief Try to lower insertion of a single element into a zero vector.
7770 /// This is a common pattern that we have especially efficient patterns to lower
7771 /// across all subtarget feature sets.
7772 static SDValue lowerVectorShuffleAsElementInsertion(
7773 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7774 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7775 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7777 MVT EltVT = VT.getVectorElementType();
7779 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7780 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7782 bool IsV1Zeroable = true;
7783 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7784 if (i != V2Index && !Zeroable[i]) {
7785 IsV1Zeroable = false;
7789 // Check for a single input from a SCALAR_TO_VECTOR node.
7790 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7791 // all the smarts here sunk into that routine. However, the current
7792 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7793 // vector shuffle lowering is dead.
7794 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7796 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7797 // We need to zext the scalar if it is smaller than an i32.
7798 V2S = DAG.getBitcast(EltVT, V2S);
7799 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7800 // Using zext to expand a narrow element won't work for non-zero
7805 // Zero-extend directly to i32.
7807 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7809 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7810 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7811 EltVT == MVT::i16) {
7812 // Either not inserting from the low element of the input or the input
7813 // element size is too small to use VZEXT_MOVL to clear the high bits.
7817 if (!IsV1Zeroable) {
7818 // If V1 can't be treated as a zero vector we have fewer options to lower
7819 // this. We can't support integer vectors or non-zero targets cheaply, and
7820 // the V1 elements can't be permuted in any way.
7821 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7822 if (!VT.isFloatingPoint() || V2Index != 0)
7824 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7825 V1Mask[V2Index] = -1;
7826 if (!isNoopShuffleMask(V1Mask))
7828 // This is essentially a special case blend operation, but if we have
7829 // general purpose blend operations, they are always faster. Bail and let
7830 // the rest of the lowering handle these as blends.
7831 if (Subtarget->hasSSE41())
7834 // Otherwise, use MOVSD or MOVSS.
7835 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7836 "Only two types of floating point element types to handle!");
7837 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7841 // This lowering only works for the low element with floating point vectors.
7842 if (VT.isFloatingPoint() && V2Index != 0)
7845 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7847 V2 = DAG.getBitcast(VT, V2);
7850 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7851 // the desired position. Otherwise it is more efficient to do a vector
7852 // shift left. We know that we can do a vector shift left because all
7853 // the inputs are zero.
7854 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7855 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7856 V2Shuffle[V2Index] = 0;
7857 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7859 V2 = DAG.getBitcast(MVT::v2i64, V2);
7861 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7862 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7863 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7864 DAG.getDataLayout(), VT)));
7865 V2 = DAG.getBitcast(VT, V2);
7871 /// \brief Try to lower broadcast of a single element.
7873 /// For convenience, this code also bundles all of the subtarget feature set
7874 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7875 /// a convenient way to factor it out.
7876 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7878 const X86Subtarget *Subtarget,
7879 SelectionDAG &DAG) {
7880 if (!Subtarget->hasAVX())
7882 if (VT.isInteger() && !Subtarget->hasAVX2())
7885 // Check that the mask is a broadcast.
7886 int BroadcastIdx = -1;
7888 if (M >= 0 && BroadcastIdx == -1)
7890 else if (M >= 0 && M != BroadcastIdx)
7893 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7894 "a sorted mask where the broadcast "
7897 // Go up the chain of (vector) values to find a scalar load that we can
7898 // combine with the broadcast.
7900 switch (V.getOpcode()) {
7901 case ISD::CONCAT_VECTORS: {
7902 int OperandSize = Mask.size() / V.getNumOperands();
7903 V = V.getOperand(BroadcastIdx / OperandSize);
7904 BroadcastIdx %= OperandSize;
7908 case ISD::INSERT_SUBVECTOR: {
7909 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7910 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7914 int BeginIdx = (int)ConstantIdx->getZExtValue();
7916 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7917 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7918 BroadcastIdx -= BeginIdx;
7929 // Check if this is a broadcast of a scalar. We special case lowering
7930 // for scalars so that we can more effectively fold with loads.
7931 // First, look through bitcast: if the original value has a larger element
7932 // type than the shuffle, the broadcast element is in essence truncated.
7933 // Make that explicit to ease folding.
7934 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7935 EVT EltVT = VT.getVectorElementType();
7936 SDValue V0 = V.getOperand(0);
7937 EVT V0VT = V0.getValueType();
7939 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7940 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7941 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7942 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7947 // Also check the simpler case, where we can directly reuse the scalar.
7948 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7949 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7950 V = V.getOperand(BroadcastIdx);
7952 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7953 // Only AVX2 has register broadcasts.
7954 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7956 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7957 // We can't broadcast from a vector register without AVX2, and we can only
7958 // broadcast from the zero-element of a vector register.
7962 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7965 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7966 // INSERTPS when the V1 elements are already in the correct locations
7967 // because otherwise we can just always use two SHUFPS instructions which
7968 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7969 // perform INSERTPS if a single V1 element is out of place and all V2
7970 // elements are zeroable.
7971 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7973 SelectionDAG &DAG) {
7974 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7975 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7976 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7977 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7979 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7982 int V1DstIndex = -1;
7983 int V2DstIndex = -1;
7984 bool V1UsedInPlace = false;
7986 for (int i = 0; i < 4; ++i) {
7987 // Synthesize a zero mask from the zeroable elements (includes undefs).
7993 // Flag if we use any V1 inputs in place.
7995 V1UsedInPlace = true;
7999 // We can only insert a single non-zeroable element.
8000 if (V1DstIndex != -1 || V2DstIndex != -1)
8004 // V1 input out of place for insertion.
8007 // V2 input for insertion.
8012 // Don't bother if we have no (non-zeroable) element for insertion.
8013 if (V1DstIndex == -1 && V2DstIndex == -1)
8016 // Determine element insertion src/dst indices. The src index is from the
8017 // start of the inserted vector, not the start of the concatenated vector.
8018 unsigned V2SrcIndex = 0;
8019 if (V1DstIndex != -1) {
8020 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8021 // and don't use the original V2 at all.
8022 V2SrcIndex = Mask[V1DstIndex];
8023 V2DstIndex = V1DstIndex;
8026 V2SrcIndex = Mask[V2DstIndex] - 4;
8029 // If no V1 inputs are used in place, then the result is created only from
8030 // the zero mask and the V2 insertion - so remove V1 dependency.
8032 V1 = DAG.getUNDEF(MVT::v4f32);
8034 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8035 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8037 // Insert the V2 element into the desired position.
8039 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8040 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8043 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8044 /// UNPCK instruction.
8046 /// This specifically targets cases where we end up with alternating between
8047 /// the two inputs, and so can permute them into something that feeds a single
8048 /// UNPCK instruction. Note that this routine only targets integer vectors
8049 /// because for floating point vectors we have a generalized SHUFPS lowering
8050 /// strategy that handles everything that doesn't *exactly* match an unpack,
8051 /// making this clever lowering unnecessary.
8052 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8053 SDValue V1, SDValue V2,
8055 SelectionDAG &DAG) {
8056 assert(!VT.isFloatingPoint() &&
8057 "This routine only supports integer vectors.");
8058 assert(!isSingleInputShuffleMask(Mask) &&
8059 "This routine should only be used when blending two inputs.");
8060 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8062 int Size = Mask.size();
8064 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8065 return M >= 0 && M % Size < Size / 2;
8067 int NumHiInputs = std::count_if(
8068 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8070 bool UnpackLo = NumLoInputs >= NumHiInputs;
8072 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8073 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8074 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8076 for (int i = 0; i < Size; ++i) {
8080 // Each element of the unpack contains Scale elements from this mask.
8081 int UnpackIdx = i / Scale;
8083 // We only handle the case where V1 feeds the first slots of the unpack.
8084 // We rely on canonicalization to ensure this is the case.
8085 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8088 // Setup the mask for this input. The indexing is tricky as we have to
8089 // handle the unpack stride.
8090 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8091 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8095 // If we will have to shuffle both inputs to use the unpack, check whether
8096 // we can just unpack first and shuffle the result. If so, skip this unpack.
8097 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8098 !isNoopShuffleMask(V2Mask))
8101 // Shuffle the inputs into place.
8102 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8103 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8105 // Cast the inputs to the type we will use to unpack them.
8106 V1 = DAG.getBitcast(UnpackVT, V1);
8107 V2 = DAG.getBitcast(UnpackVT, V2);
8109 // Unpack the inputs and cast the result back to the desired type.
8110 return DAG.getBitcast(
8111 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8115 // We try each unpack from the largest to the smallest to try and find one
8116 // that fits this mask.
8117 int OrigNumElements = VT.getVectorNumElements();
8118 int OrigScalarSize = VT.getScalarSizeInBits();
8119 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8120 int Scale = ScalarSize / OrigScalarSize;
8121 int NumElements = OrigNumElements / Scale;
8122 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8123 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8127 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8129 if (NumLoInputs == 0 || NumHiInputs == 0) {
8130 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8131 "We have to have *some* inputs!");
8132 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8134 // FIXME: We could consider the total complexity of the permute of each
8135 // possible unpacking. Or at the least we should consider how many
8136 // half-crossings are created.
8137 // FIXME: We could consider commuting the unpacks.
8139 SmallVector<int, 32> PermMask;
8140 PermMask.assign(Size, -1);
8141 for (int i = 0; i < Size; ++i) {
8145 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8148 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8150 return DAG.getVectorShuffle(
8151 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8153 DAG.getUNDEF(VT), PermMask);
8159 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8161 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8162 /// support for floating point shuffles but not integer shuffles. These
8163 /// instructions will incur a domain crossing penalty on some chips though so
8164 /// it is better to avoid lowering through this for integer vectors where
8166 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8167 const X86Subtarget *Subtarget,
8168 SelectionDAG &DAG) {
8170 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8171 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8172 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8174 ArrayRef<int> Mask = SVOp->getMask();
8175 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8177 if (isSingleInputShuffleMask(Mask)) {
8178 // Use low duplicate instructions for masks that match their pattern.
8179 if (Subtarget->hasSSE3())
8180 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8181 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8183 // Straight shuffle of a single input vector. Simulate this by using the
8184 // single input as both of the "inputs" to this instruction..
8185 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8187 if (Subtarget->hasAVX()) {
8188 // If we have AVX, we can use VPERMILPS which will allow folding a load
8189 // into the shuffle.
8190 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8191 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8194 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8195 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8197 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8198 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8200 // If we have a single input, insert that into V1 if we can do so cheaply.
8201 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8202 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8203 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8205 // Try inverting the insertion since for v2 masks it is easy to do and we
8206 // can't reliably sort the mask one way or the other.
8207 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8208 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8209 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8210 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8214 // Try to use one of the special instruction patterns to handle two common
8215 // blend patterns if a zero-blend above didn't work.
8216 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8217 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8218 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8219 // We can either use a special instruction to load over the low double or
8220 // to move just the low double.
8222 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8224 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8226 if (Subtarget->hasSSE41())
8227 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8231 // Use dedicated unpack instructions for masks that match their pattern.
8232 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8233 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8234 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8235 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8237 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8238 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8239 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8242 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8244 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8245 /// the integer unit to minimize domain crossing penalties. However, for blends
8246 /// it falls back to the floating point shuffle operation with appropriate bit
8248 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8249 const X86Subtarget *Subtarget,
8250 SelectionDAG &DAG) {
8252 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8253 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8254 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8256 ArrayRef<int> Mask = SVOp->getMask();
8257 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8259 if (isSingleInputShuffleMask(Mask)) {
8260 // Check for being able to broadcast a single element.
8261 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8262 Mask, Subtarget, DAG))
8265 // Straight shuffle of a single input vector. For everything from SSE2
8266 // onward this has a single fast instruction with no scary immediates.
8267 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8268 V1 = DAG.getBitcast(MVT::v4i32, V1);
8269 int WidenedMask[4] = {
8270 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8271 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8272 return DAG.getBitcast(
8274 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8275 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8277 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8278 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8279 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8280 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8282 // If we have a blend of two PACKUS operations an the blend aligns with the
8283 // low and half halves, we can just merge the PACKUS operations. This is
8284 // particularly important as it lets us merge shuffles that this routine itself
8286 auto GetPackNode = [](SDValue V) {
8287 while (V.getOpcode() == ISD::BITCAST)
8288 V = V.getOperand(0);
8290 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8292 if (SDValue V1Pack = GetPackNode(V1))
8293 if (SDValue V2Pack = GetPackNode(V2))
8294 return DAG.getBitcast(MVT::v2i64,
8295 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8296 Mask[0] == 0 ? V1Pack.getOperand(0)
8297 : V1Pack.getOperand(1),
8298 Mask[1] == 2 ? V2Pack.getOperand(0)
8299 : V2Pack.getOperand(1)));
8301 // Try to use shift instructions.
8303 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8306 // When loading a scalar and then shuffling it into a vector we can often do
8307 // the insertion cheaply.
8308 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8309 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8311 // Try inverting the insertion since for v2 masks it is easy to do and we
8312 // can't reliably sort the mask one way or the other.
8313 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8314 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8315 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8318 // We have different paths for blend lowering, but they all must use the
8319 // *exact* same predicate.
8320 bool IsBlendSupported = Subtarget->hasSSE41();
8321 if (IsBlendSupported)
8322 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8326 // Use dedicated unpack instructions for masks that match their pattern.
8327 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8328 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8329 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8330 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8332 // Try to use byte rotation instructions.
8333 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8334 if (Subtarget->hasSSSE3())
8335 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8336 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8339 // If we have direct support for blends, we should lower by decomposing into
8340 // a permute. That will be faster than the domain cross.
8341 if (IsBlendSupported)
8342 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8345 // We implement this with SHUFPD which is pretty lame because it will likely
8346 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8347 // However, all the alternatives are still more cycles and newer chips don't
8348 // have this problem. It would be really nice if x86 had better shuffles here.
8349 V1 = DAG.getBitcast(MVT::v2f64, V1);
8350 V2 = DAG.getBitcast(MVT::v2f64, V2);
8351 return DAG.getBitcast(MVT::v2i64,
8352 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8355 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8357 /// This is used to disable more specialized lowerings when the shufps lowering
8358 /// will happen to be efficient.
8359 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8360 // This routine only handles 128-bit shufps.
8361 assert(Mask.size() == 4 && "Unsupported mask size!");
8363 // To lower with a single SHUFPS we need to have the low half and high half
8364 // each requiring a single input.
8365 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8367 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8373 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8375 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8376 /// It makes no assumptions about whether this is the *best* lowering, it simply
8378 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8379 ArrayRef<int> Mask, SDValue V1,
8380 SDValue V2, SelectionDAG &DAG) {
8381 SDValue LowV = V1, HighV = V2;
8382 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8385 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8387 if (NumV2Elements == 1) {
8389 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8392 // Compute the index adjacent to V2Index and in the same half by toggling
8394 int V2AdjIndex = V2Index ^ 1;
8396 if (Mask[V2AdjIndex] == -1) {
8397 // Handles all the cases where we have a single V2 element and an undef.
8398 // This will only ever happen in the high lanes because we commute the
8399 // vector otherwise.
8401 std::swap(LowV, HighV);
8402 NewMask[V2Index] -= 4;
8404 // Handle the case where the V2 element ends up adjacent to a V1 element.
8405 // To make this work, blend them together as the first step.
8406 int V1Index = V2AdjIndex;
8407 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8408 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8409 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8411 // Now proceed to reconstruct the final blend as we have the necessary
8412 // high or low half formed.
8419 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8420 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8422 } else if (NumV2Elements == 2) {
8423 if (Mask[0] < 4 && Mask[1] < 4) {
8424 // Handle the easy case where we have V1 in the low lanes and V2 in the
8428 } else if (Mask[2] < 4 && Mask[3] < 4) {
8429 // We also handle the reversed case because this utility may get called
8430 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8431 // arrange things in the right direction.
8437 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8438 // trying to place elements directly, just blend them and set up the final
8439 // shuffle to place them.
8441 // The first two blend mask elements are for V1, the second two are for
8443 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8444 Mask[2] < 4 ? Mask[2] : Mask[3],
8445 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8446 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8447 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8448 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8450 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8453 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8454 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8455 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8456 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8459 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8460 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8463 /// \brief Lower 4-lane 32-bit floating point shuffles.
8465 /// Uses instructions exclusively from the floating point unit to minimize
8466 /// domain crossing penalties, as these are sufficient to implement all v4f32
8468 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8469 const X86Subtarget *Subtarget,
8470 SelectionDAG &DAG) {
8472 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8473 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8474 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8476 ArrayRef<int> Mask = SVOp->getMask();
8477 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8480 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8482 if (NumV2Elements == 0) {
8483 // Check for being able to broadcast a single element.
8484 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8485 Mask, Subtarget, DAG))
8488 // Use even/odd duplicate instructions for masks that match their pattern.
8489 if (Subtarget->hasSSE3()) {
8490 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8491 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8492 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8493 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8496 if (Subtarget->hasAVX()) {
8497 // If we have AVX, we can use VPERMILPS which will allow folding a load
8498 // into the shuffle.
8499 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8500 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8503 // Otherwise, use a straight shuffle of a single input vector. We pass the
8504 // input vector to both operands to simulate this with a SHUFPS.
8505 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8506 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8509 // There are special ways we can lower some single-element blends. However, we
8510 // have custom ways we can lower more complex single-element blends below that
8511 // we defer to if both this and BLENDPS fail to match, so restrict this to
8512 // when the V2 input is targeting element 0 of the mask -- that is the fast
8514 if (NumV2Elements == 1 && Mask[0] >= 4)
8515 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8516 Mask, Subtarget, DAG))
8519 if (Subtarget->hasSSE41()) {
8520 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8524 // Use INSERTPS if we can complete the shuffle efficiently.
8525 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8528 if (!isSingleSHUFPSMask(Mask))
8529 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8530 DL, MVT::v4f32, V1, V2, Mask, DAG))
8534 // Use dedicated unpack instructions for masks that match their pattern.
8535 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8536 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8537 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8538 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8539 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8540 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8541 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8542 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8544 // Otherwise fall back to a SHUFPS lowering strategy.
8545 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8548 /// \brief Lower 4-lane i32 vector shuffles.
8550 /// We try to handle these with integer-domain shuffles where we can, but for
8551 /// blends we use the floating point domain blend instructions.
8552 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8553 const X86Subtarget *Subtarget,
8554 SelectionDAG &DAG) {
8556 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8557 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8558 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8559 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8560 ArrayRef<int> Mask = SVOp->getMask();
8561 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8563 // Whenever we can lower this as a zext, that instruction is strictly faster
8564 // than any alternative. It also allows us to fold memory operands into the
8565 // shuffle in many cases.
8566 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8567 Mask, Subtarget, DAG))
8571 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8573 if (NumV2Elements == 0) {
8574 // Check for being able to broadcast a single element.
8575 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8576 Mask, Subtarget, DAG))
8579 // Straight shuffle of a single input vector. For everything from SSE2
8580 // onward this has a single fast instruction with no scary immediates.
8581 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8582 // but we aren't actually going to use the UNPCK instruction because doing
8583 // so prevents folding a load into this instruction or making a copy.
8584 const int UnpackLoMask[] = {0, 0, 1, 1};
8585 const int UnpackHiMask[] = {2, 2, 3, 3};
8586 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8587 Mask = UnpackLoMask;
8588 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8589 Mask = UnpackHiMask;
8591 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8592 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8595 // Try to use shift instructions.
8597 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8600 // There are special ways we can lower some single-element blends.
8601 if (NumV2Elements == 1)
8602 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8603 Mask, Subtarget, DAG))
8606 // We have different paths for blend lowering, but they all must use the
8607 // *exact* same predicate.
8608 bool IsBlendSupported = Subtarget->hasSSE41();
8609 if (IsBlendSupported)
8610 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8614 if (SDValue Masked =
8615 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8618 // Use dedicated unpack instructions for masks that match their pattern.
8619 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8620 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8621 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8622 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8623 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8624 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8625 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8626 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8628 // Try to use byte rotation instructions.
8629 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8630 if (Subtarget->hasSSSE3())
8631 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8632 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8635 // If we have direct support for blends, we should lower by decomposing into
8636 // a permute. That will be faster than the domain cross.
8637 if (IsBlendSupported)
8638 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8641 // Try to lower by permuting the inputs into an unpack instruction.
8642 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8646 // We implement this with SHUFPS because it can blend from two vectors.
8647 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8648 // up the inputs, bypassing domain shift penalties that we would encur if we
8649 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8651 return DAG.getBitcast(
8653 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8654 DAG.getBitcast(MVT::v4f32, V2), Mask));
8657 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8658 /// shuffle lowering, and the most complex part.
8660 /// The lowering strategy is to try to form pairs of input lanes which are
8661 /// targeted at the same half of the final vector, and then use a dword shuffle
8662 /// to place them onto the right half, and finally unpack the paired lanes into
8663 /// their final position.
8665 /// The exact breakdown of how to form these dword pairs and align them on the
8666 /// correct sides is really tricky. See the comments within the function for
8667 /// more of the details.
8669 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8670 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8671 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8672 /// vector, form the analogous 128-bit 8-element Mask.
8673 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8674 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8675 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8676 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8677 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8679 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8680 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8681 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8683 SmallVector<int, 4> LoInputs;
8684 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8685 [](int M) { return M >= 0; });
8686 std::sort(LoInputs.begin(), LoInputs.end());
8687 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8688 SmallVector<int, 4> HiInputs;
8689 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8690 [](int M) { return M >= 0; });
8691 std::sort(HiInputs.begin(), HiInputs.end());
8692 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8694 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8695 int NumHToL = LoInputs.size() - NumLToL;
8697 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8698 int NumHToH = HiInputs.size() - NumLToH;
8699 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8700 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8701 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8702 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8704 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8705 // such inputs we can swap two of the dwords across the half mark and end up
8706 // with <=2 inputs to each half in each half. Once there, we can fall through
8707 // to the generic code below. For example:
8709 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8710 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8712 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8713 // and an existing 2-into-2 on the other half. In this case we may have to
8714 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8715 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8716 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8717 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8718 // half than the one we target for fixing) will be fixed when we re-enter this
8719 // path. We will also combine away any sequence of PSHUFD instructions that
8720 // result into a single instruction. Here is an example of the tricky case:
8722 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8723 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8725 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8727 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8728 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8730 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8731 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8733 // The result is fine to be handled by the generic logic.
8734 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8735 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8736 int AOffset, int BOffset) {
8737 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8738 "Must call this with A having 3 or 1 inputs from the A half.");
8739 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8740 "Must call this with B having 1 or 3 inputs from the B half.");
8741 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8742 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8744 bool ThreeAInputs = AToAInputs.size() == 3;
8746 // Compute the index of dword with only one word among the three inputs in
8747 // a half by taking the sum of the half with three inputs and subtracting
8748 // the sum of the actual three inputs. The difference is the remaining
8751 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8752 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8753 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8754 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8755 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8756 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8757 int TripleNonInputIdx =
8758 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8759 TripleDWord = TripleNonInputIdx / 2;
8761 // We use xor with one to compute the adjacent DWord to whichever one the
8763 OneInputDWord = (OneInput / 2) ^ 1;
8765 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8766 // and BToA inputs. If there is also such a problem with the BToB and AToB
8767 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8768 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8769 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8770 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8771 // Compute how many inputs will be flipped by swapping these DWords. We
8773 // to balance this to ensure we don't form a 3-1 shuffle in the other
8775 int NumFlippedAToBInputs =
8776 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8777 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8778 int NumFlippedBToBInputs =
8779 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8780 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8781 if ((NumFlippedAToBInputs == 1 &&
8782 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8783 (NumFlippedBToBInputs == 1 &&
8784 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8785 // We choose whether to fix the A half or B half based on whether that
8786 // half has zero flipped inputs. At zero, we may not be able to fix it
8787 // with that half. We also bias towards fixing the B half because that
8788 // will more commonly be the high half, and we have to bias one way.
8789 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8790 ArrayRef<int> Inputs) {
8791 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8792 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8793 PinnedIdx ^ 1) != Inputs.end();
8794 // Determine whether the free index is in the flipped dword or the
8795 // unflipped dword based on where the pinned index is. We use this bit
8796 // in an xor to conditionally select the adjacent dword.
8797 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8798 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8799 FixFreeIdx) != Inputs.end();
8800 if (IsFixIdxInput == IsFixFreeIdxInput)
8802 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8803 FixFreeIdx) != Inputs.end();
8804 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8805 "We need to be changing the number of flipped inputs!");
8806 int PSHUFHalfMask[] = {0, 1, 2, 3};
8807 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8808 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8810 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8813 if (M != -1 && M == FixIdx)
8815 else if (M != -1 && M == FixFreeIdx)
8818 if (NumFlippedBToBInputs != 0) {
8820 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8821 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8823 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8824 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8825 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8830 int PSHUFDMask[] = {0, 1, 2, 3};
8831 PSHUFDMask[ADWord] = BDWord;
8832 PSHUFDMask[BDWord] = ADWord;
8835 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8836 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8838 // Adjust the mask to match the new locations of A and B.
8840 if (M != -1 && M/2 == ADWord)
8841 M = 2 * BDWord + M % 2;
8842 else if (M != -1 && M/2 == BDWord)
8843 M = 2 * ADWord + M % 2;
8845 // Recurse back into this routine to re-compute state now that this isn't
8846 // a 3 and 1 problem.
8847 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8850 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8851 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8852 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8853 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8855 // At this point there are at most two inputs to the low and high halves from
8856 // each half. That means the inputs can always be grouped into dwords and
8857 // those dwords can then be moved to the correct half with a dword shuffle.
8858 // We use at most one low and one high word shuffle to collect these paired
8859 // inputs into dwords, and finally a dword shuffle to place them.
8860 int PSHUFLMask[4] = {-1, -1, -1, -1};
8861 int PSHUFHMask[4] = {-1, -1, -1, -1};
8862 int PSHUFDMask[4] = {-1, -1, -1, -1};
8864 // First fix the masks for all the inputs that are staying in their
8865 // original halves. This will then dictate the targets of the cross-half
8867 auto fixInPlaceInputs =
8868 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8869 MutableArrayRef<int> SourceHalfMask,
8870 MutableArrayRef<int> HalfMask, int HalfOffset) {
8871 if (InPlaceInputs.empty())
8873 if (InPlaceInputs.size() == 1) {
8874 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8875 InPlaceInputs[0] - HalfOffset;
8876 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8879 if (IncomingInputs.empty()) {
8880 // Just fix all of the in place inputs.
8881 for (int Input : InPlaceInputs) {
8882 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8883 PSHUFDMask[Input / 2] = Input / 2;
8888 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8889 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8890 InPlaceInputs[0] - HalfOffset;
8891 // Put the second input next to the first so that they are packed into
8892 // a dword. We find the adjacent index by toggling the low bit.
8893 int AdjIndex = InPlaceInputs[0] ^ 1;
8894 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8895 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8896 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8898 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8899 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8901 // Now gather the cross-half inputs and place them into a free dword of
8902 // their target half.
8903 // FIXME: This operation could almost certainly be simplified dramatically to
8904 // look more like the 3-1 fixing operation.
8905 auto moveInputsToRightHalf = [&PSHUFDMask](
8906 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8907 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8908 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8910 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8911 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8913 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8915 int LowWord = Word & ~1;
8916 int HighWord = Word | 1;
8917 return isWordClobbered(SourceHalfMask, LowWord) ||
8918 isWordClobbered(SourceHalfMask, HighWord);
8921 if (IncomingInputs.empty())
8924 if (ExistingInputs.empty()) {
8925 // Map any dwords with inputs from them into the right half.
8926 for (int Input : IncomingInputs) {
8927 // If the source half mask maps over the inputs, turn those into
8928 // swaps and use the swapped lane.
8929 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8930 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8931 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8932 Input - SourceOffset;
8933 // We have to swap the uses in our half mask in one sweep.
8934 for (int &M : HalfMask)
8935 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8937 else if (M == Input)
8938 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8940 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8941 Input - SourceOffset &&
8942 "Previous placement doesn't match!");
8944 // Note that this correctly re-maps both when we do a swap and when
8945 // we observe the other side of the swap above. We rely on that to
8946 // avoid swapping the members of the input list directly.
8947 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8950 // Map the input's dword into the correct half.
8951 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8952 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8954 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8956 "Previous placement doesn't match!");
8959 // And just directly shift any other-half mask elements to be same-half
8960 // as we will have mirrored the dword containing the element into the
8961 // same position within that half.
8962 for (int &M : HalfMask)
8963 if (M >= SourceOffset && M < SourceOffset + 4) {
8964 M = M - SourceOffset + DestOffset;
8965 assert(M >= 0 && "This should never wrap below zero!");
8970 // Ensure we have the input in a viable dword of its current half. This
8971 // is particularly tricky because the original position may be clobbered
8972 // by inputs being moved and *staying* in that half.
8973 if (IncomingInputs.size() == 1) {
8974 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8975 int InputFixed = std::find(std::begin(SourceHalfMask),
8976 std::end(SourceHalfMask), -1) -
8977 std::begin(SourceHalfMask) + SourceOffset;
8978 SourceHalfMask[InputFixed - SourceOffset] =
8979 IncomingInputs[0] - SourceOffset;
8980 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8982 IncomingInputs[0] = InputFixed;
8984 } else if (IncomingInputs.size() == 2) {
8985 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8986 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8987 // We have two non-adjacent or clobbered inputs we need to extract from
8988 // the source half. To do this, we need to map them into some adjacent
8989 // dword slot in the source mask.
8990 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8991 IncomingInputs[1] - SourceOffset};
8993 // If there is a free slot in the source half mask adjacent to one of
8994 // the inputs, place the other input in it. We use (Index XOR 1) to
8995 // compute an adjacent index.
8996 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8997 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8998 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8999 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9000 InputsFixed[1] = InputsFixed[0] ^ 1;
9001 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9002 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9003 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9004 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9005 InputsFixed[0] = InputsFixed[1] ^ 1;
9006 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9007 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9008 // The two inputs are in the same DWord but it is clobbered and the
9009 // adjacent DWord isn't used at all. Move both inputs to the free
9011 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9012 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9013 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9014 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9016 // The only way we hit this point is if there is no clobbering
9017 // (because there are no off-half inputs to this half) and there is no
9018 // free slot adjacent to one of the inputs. In this case, we have to
9019 // swap an input with a non-input.
9020 for (int i = 0; i < 4; ++i)
9021 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9022 "We can't handle any clobbers here!");
9023 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9024 "Cannot have adjacent inputs here!");
9026 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9027 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9029 // We also have to update the final source mask in this case because
9030 // it may need to undo the above swap.
9031 for (int &M : FinalSourceHalfMask)
9032 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9033 M = InputsFixed[1] + SourceOffset;
9034 else if (M == InputsFixed[1] + SourceOffset)
9035 M = (InputsFixed[0] ^ 1) + SourceOffset;
9037 InputsFixed[1] = InputsFixed[0] ^ 1;
9040 // Point everything at the fixed inputs.
9041 for (int &M : HalfMask)
9042 if (M == IncomingInputs[0])
9043 M = InputsFixed[0] + SourceOffset;
9044 else if (M == IncomingInputs[1])
9045 M = InputsFixed[1] + SourceOffset;
9047 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9048 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9051 llvm_unreachable("Unhandled input size!");
9054 // Now hoist the DWord down to the right half.
9055 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9056 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9057 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9058 for (int &M : HalfMask)
9059 for (int Input : IncomingInputs)
9061 M = FreeDWord * 2 + Input % 2;
9063 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9064 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9065 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9066 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9068 // Now enact all the shuffles we've computed to move the inputs into their
9070 if (!isNoopShuffleMask(PSHUFLMask))
9071 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9072 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9073 if (!isNoopShuffleMask(PSHUFHMask))
9074 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9075 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9076 if (!isNoopShuffleMask(PSHUFDMask))
9079 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9080 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9082 // At this point, each half should contain all its inputs, and we can then
9083 // just shuffle them into their final position.
9084 assert(std::count_if(LoMask.begin(), LoMask.end(),
9085 [](int M) { return M >= 4; }) == 0 &&
9086 "Failed to lift all the high half inputs to the low mask!");
9087 assert(std::count_if(HiMask.begin(), HiMask.end(),
9088 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9089 "Failed to lift all the low half inputs to the high mask!");
9091 // Do a half shuffle for the low mask.
9092 if (!isNoopShuffleMask(LoMask))
9093 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9094 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9096 // Do a half shuffle with the high mask after shifting its values down.
9097 for (int &M : HiMask)
9100 if (!isNoopShuffleMask(HiMask))
9101 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9102 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9107 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9108 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9109 SDValue V2, ArrayRef<int> Mask,
9110 SelectionDAG &DAG, bool &V1InUse,
9112 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9118 int Size = Mask.size();
9119 int Scale = 16 / Size;
9120 for (int i = 0; i < 16; ++i) {
9121 if (Mask[i / Scale] == -1) {
9122 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9124 const int ZeroMask = 0x80;
9125 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9127 int V2Idx = Mask[i / Scale] < Size
9129 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9130 if (Zeroable[i / Scale])
9131 V1Idx = V2Idx = ZeroMask;
9132 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9133 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9134 V1InUse |= (ZeroMask != V1Idx);
9135 V2InUse |= (ZeroMask != V2Idx);
9140 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9141 DAG.getBitcast(MVT::v16i8, V1),
9142 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9144 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9145 DAG.getBitcast(MVT::v16i8, V2),
9146 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9148 // If we need shuffled inputs from both, blend the two.
9150 if (V1InUse && V2InUse)
9151 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9153 V = V1InUse ? V1 : V2;
9155 // Cast the result back to the correct type.
9156 return DAG.getBitcast(VT, V);
9159 /// \brief Generic lowering of 8-lane i16 shuffles.
9161 /// This handles both single-input shuffles and combined shuffle/blends with
9162 /// two inputs. The single input shuffles are immediately delegated to
9163 /// a dedicated lowering routine.
9165 /// The blends are lowered in one of three fundamental ways. If there are few
9166 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9167 /// of the input is significantly cheaper when lowered as an interleaving of
9168 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9169 /// halves of the inputs separately (making them have relatively few inputs)
9170 /// and then concatenate them.
9171 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9172 const X86Subtarget *Subtarget,
9173 SelectionDAG &DAG) {
9175 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9176 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9177 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9178 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9179 ArrayRef<int> OrigMask = SVOp->getMask();
9180 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9181 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9182 MutableArrayRef<int> Mask(MaskStorage);
9184 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9186 // Whenever we can lower this as a zext, that instruction is strictly faster
9187 // than any alternative.
9188 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9189 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9192 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9194 auto isV2 = [](int M) { return M >= 8; };
9196 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9198 if (NumV2Inputs == 0) {
9199 // Check for being able to broadcast a single element.
9200 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9201 Mask, Subtarget, DAG))
9204 // Try to use shift instructions.
9206 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9209 // Use dedicated unpack instructions for masks that match their pattern.
9210 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9211 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9212 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9213 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9215 // Try to use byte rotation instructions.
9216 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9217 Mask, Subtarget, DAG))
9220 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9224 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9225 "All single-input shuffles should be canonicalized to be V1-input "
9228 // Try to use shift instructions.
9230 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9233 // See if we can use SSE4A Extraction / Insertion.
9234 if (Subtarget->hasSSE4A())
9235 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9238 // There are special ways we can lower some single-element blends.
9239 if (NumV2Inputs == 1)
9240 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9241 Mask, Subtarget, DAG))
9244 // We have different paths for blend lowering, but they all must use the
9245 // *exact* same predicate.
9246 bool IsBlendSupported = Subtarget->hasSSE41();
9247 if (IsBlendSupported)
9248 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9252 if (SDValue Masked =
9253 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9256 // Use dedicated unpack instructions for masks that match their pattern.
9257 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9258 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9259 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9260 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9262 // Try to use byte rotation instructions.
9263 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9264 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9267 if (SDValue BitBlend =
9268 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9271 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9275 // If we can't directly blend but can use PSHUFB, that will be better as it
9276 // can both shuffle and set up the inefficient blend.
9277 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9278 bool V1InUse, V2InUse;
9279 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9283 // We can always bit-blend if we have to so the fallback strategy is to
9284 // decompose into single-input permutes and blends.
9285 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9289 /// \brief Check whether a compaction lowering can be done by dropping even
9290 /// elements and compute how many times even elements must be dropped.
9292 /// This handles shuffles which take every Nth element where N is a power of
9293 /// two. Example shuffle masks:
9295 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9296 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9297 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9298 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9299 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9300 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9302 /// Any of these lanes can of course be undef.
9304 /// This routine only supports N <= 3.
9305 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9308 /// \returns N above, or the number of times even elements must be dropped if
9309 /// there is such a number. Otherwise returns zero.
9310 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9311 // Figure out whether we're looping over two inputs or just one.
9312 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9314 // The modulus for the shuffle vector entries is based on whether this is
9315 // a single input or not.
9316 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9317 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9318 "We should only be called with masks with a power-of-2 size!");
9320 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9322 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9323 // and 2^3 simultaneously. This is because we may have ambiguity with
9324 // partially undef inputs.
9325 bool ViableForN[3] = {true, true, true};
9327 for (int i = 0, e = Mask.size(); i < e; ++i) {
9328 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9333 bool IsAnyViable = false;
9334 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9335 if (ViableForN[j]) {
9338 // The shuffle mask must be equal to (i * 2^N) % M.
9339 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9342 ViableForN[j] = false;
9344 // Early exit if we exhaust the possible powers of two.
9349 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9353 // Return 0 as there is no viable power of two.
9357 /// \brief Generic lowering of v16i8 shuffles.
9359 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9360 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9361 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9362 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9364 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9365 const X86Subtarget *Subtarget,
9366 SelectionDAG &DAG) {
9368 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9369 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9370 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9371 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9372 ArrayRef<int> Mask = SVOp->getMask();
9373 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9375 // Try to use shift instructions.
9377 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9380 // Try to use byte rotation instructions.
9381 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9382 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9385 // Try to use a zext lowering.
9386 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9387 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9390 // See if we can use SSE4A Extraction / Insertion.
9391 if (Subtarget->hasSSE4A())
9392 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9396 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9398 // For single-input shuffles, there are some nicer lowering tricks we can use.
9399 if (NumV2Elements == 0) {
9400 // Check for being able to broadcast a single element.
9401 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9402 Mask, Subtarget, DAG))
9405 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9406 // Notably, this handles splat and partial-splat shuffles more efficiently.
9407 // However, it only makes sense if the pre-duplication shuffle simplifies
9408 // things significantly. Currently, this means we need to be able to
9409 // express the pre-duplication shuffle as an i16 shuffle.
9411 // FIXME: We should check for other patterns which can be widened into an
9412 // i16 shuffle as well.
9413 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9414 for (int i = 0; i < 16; i += 2)
9415 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9420 auto tryToWidenViaDuplication = [&]() -> SDValue {
9421 if (!canWidenViaDuplication(Mask))
9423 SmallVector<int, 4> LoInputs;
9424 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9425 [](int M) { return M >= 0 && M < 8; });
9426 std::sort(LoInputs.begin(), LoInputs.end());
9427 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9429 SmallVector<int, 4> HiInputs;
9430 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9431 [](int M) { return M >= 8; });
9432 std::sort(HiInputs.begin(), HiInputs.end());
9433 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9436 bool TargetLo = LoInputs.size() >= HiInputs.size();
9437 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9438 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9440 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9441 SmallDenseMap<int, int, 8> LaneMap;
9442 for (int I : InPlaceInputs) {
9443 PreDupI16Shuffle[I/2] = I/2;
9446 int j = TargetLo ? 0 : 4, je = j + 4;
9447 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9448 // Check if j is already a shuffle of this input. This happens when
9449 // there are two adjacent bytes after we move the low one.
9450 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9451 // If we haven't yet mapped the input, search for a slot into which
9453 while (j < je && PreDupI16Shuffle[j] != -1)
9457 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9460 // Map this input with the i16 shuffle.
9461 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9464 // Update the lane map based on the mapping we ended up with.
9465 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9467 V1 = DAG.getBitcast(
9469 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9470 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9472 // Unpack the bytes to form the i16s that will be shuffled into place.
9473 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9474 MVT::v16i8, V1, V1);
9476 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9477 for (int i = 0; i < 16; ++i)
9478 if (Mask[i] != -1) {
9479 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9480 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9481 if (PostDupI16Shuffle[i / 2] == -1)
9482 PostDupI16Shuffle[i / 2] = MappedMask;
9484 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9485 "Conflicting entrties in the original shuffle!");
9487 return DAG.getBitcast(
9489 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9490 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9492 if (SDValue V = tryToWidenViaDuplication())
9496 if (SDValue Masked =
9497 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9500 // Use dedicated unpack instructions for masks that match their pattern.
9501 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9502 0, 16, 1, 17, 2, 18, 3, 19,
9504 4, 20, 5, 21, 6, 22, 7, 23}))
9505 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9506 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9507 8, 24, 9, 25, 10, 26, 11, 27,
9509 12, 28, 13, 29, 14, 30, 15, 31}))
9510 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9512 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9513 // with PSHUFB. It is important to do this before we attempt to generate any
9514 // blends but after all of the single-input lowerings. If the single input
9515 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9516 // want to preserve that and we can DAG combine any longer sequences into
9517 // a PSHUFB in the end. But once we start blending from multiple inputs,
9518 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9519 // and there are *very* few patterns that would actually be faster than the
9520 // PSHUFB approach because of its ability to zero lanes.
9522 // FIXME: The only exceptions to the above are blends which are exact
9523 // interleavings with direct instructions supporting them. We currently don't
9524 // handle those well here.
9525 if (Subtarget->hasSSSE3()) {
9526 bool V1InUse = false;
9527 bool V2InUse = false;
9529 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9530 DAG, V1InUse, V2InUse);
9532 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9533 // do so. This avoids using them to handle blends-with-zero which is
9534 // important as a single pshufb is significantly faster for that.
9535 if (V1InUse && V2InUse) {
9536 if (Subtarget->hasSSE41())
9537 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9538 Mask, Subtarget, DAG))
9541 // We can use an unpack to do the blending rather than an or in some
9542 // cases. Even though the or may be (very minorly) more efficient, we
9543 // preference this lowering because there are common cases where part of
9544 // the complexity of the shuffles goes away when we do the final blend as
9546 // FIXME: It might be worth trying to detect if the unpack-feeding
9547 // shuffles will both be pshufb, in which case we shouldn't bother with
9549 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9550 DL, MVT::v16i8, V1, V2, Mask, DAG))
9557 // There are special ways we can lower some single-element blends.
9558 if (NumV2Elements == 1)
9559 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9560 Mask, Subtarget, DAG))
9563 if (SDValue BitBlend =
9564 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9567 // Check whether a compaction lowering can be done. This handles shuffles
9568 // which take every Nth element for some even N. See the helper function for
9571 // We special case these as they can be particularly efficiently handled with
9572 // the PACKUSB instruction on x86 and they show up in common patterns of
9573 // rearranging bytes to truncate wide elements.
9574 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9575 // NumEvenDrops is the power of two stride of the elements. Another way of
9576 // thinking about it is that we need to drop the even elements this many
9577 // times to get the original input.
9578 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9580 // First we need to zero all the dropped bytes.
9581 assert(NumEvenDrops <= 3 &&
9582 "No support for dropping even elements more than 3 times.");
9583 // We use the mask type to pick which bytes are preserved based on how many
9584 // elements are dropped.
9585 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9586 SDValue ByteClearMask = DAG.getBitcast(
9587 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9588 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9590 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9592 // Now pack things back together.
9593 V1 = DAG.getBitcast(MVT::v8i16, V1);
9594 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9595 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9596 for (int i = 1; i < NumEvenDrops; ++i) {
9597 Result = DAG.getBitcast(MVT::v8i16, Result);
9598 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9604 // Handle multi-input cases by blending single-input shuffles.
9605 if (NumV2Elements > 0)
9606 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9609 // The fallback path for single-input shuffles widens this into two v8i16
9610 // vectors with unpacks, shuffles those, and then pulls them back together
9614 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9615 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9616 for (int i = 0; i < 16; ++i)
9618 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9620 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9622 SDValue VLoHalf, VHiHalf;
9623 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9624 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9626 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9627 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9628 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9629 [](int M) { return M >= 0 && M % 2 == 1; })) {
9630 // Use a mask to drop the high bytes.
9631 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9632 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9633 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9635 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9636 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9638 // Squash the masks to point directly into VLoHalf.
9639 for (int &M : LoBlendMask)
9642 for (int &M : HiBlendMask)
9646 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9647 // VHiHalf so that we can blend them as i16s.
9648 VLoHalf = DAG.getBitcast(
9649 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9650 VHiHalf = DAG.getBitcast(
9651 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9654 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9655 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9657 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9660 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9662 /// This routine breaks down the specific type of 128-bit shuffle and
9663 /// dispatches to the lowering routines accordingly.
9664 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9665 MVT VT, const X86Subtarget *Subtarget,
9666 SelectionDAG &DAG) {
9667 switch (VT.SimpleTy) {
9669 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9671 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9673 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9675 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9677 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9679 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9682 llvm_unreachable("Unimplemented!");
9686 /// \brief Helper function to test whether a shuffle mask could be
9687 /// simplified by widening the elements being shuffled.
9689 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9690 /// leaves it in an unspecified state.
9692 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9693 /// shuffle masks. The latter have the special property of a '-2' representing
9694 /// a zero-ed lane of a vector.
9695 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9696 SmallVectorImpl<int> &WidenedMask) {
9697 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9698 // If both elements are undef, its trivial.
9699 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9700 WidenedMask.push_back(SM_SentinelUndef);
9704 // Check for an undef mask and a mask value properly aligned to fit with
9705 // a pair of values. If we find such a case, use the non-undef mask's value.
9706 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9707 WidenedMask.push_back(Mask[i + 1] / 2);
9710 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9711 WidenedMask.push_back(Mask[i] / 2);
9715 // When zeroing, we need to spread the zeroing across both lanes to widen.
9716 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9717 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9718 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9719 WidenedMask.push_back(SM_SentinelZero);
9725 // Finally check if the two mask values are adjacent and aligned with
9727 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9728 WidenedMask.push_back(Mask[i] / 2);
9732 // Otherwise we can't safely widen the elements used in this shuffle.
9735 assert(WidenedMask.size() == Mask.size() / 2 &&
9736 "Incorrect size of mask after widening the elements!");
9741 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9743 /// This routine just extracts two subvectors, shuffles them independently, and
9744 /// then concatenates them back together. This should work effectively with all
9745 /// AVX vector shuffle types.
9746 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9747 SDValue V2, ArrayRef<int> Mask,
9748 SelectionDAG &DAG) {
9749 assert(VT.getSizeInBits() >= 256 &&
9750 "Only for 256-bit or wider vector shuffles!");
9751 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9752 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9754 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9755 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9757 int NumElements = VT.getVectorNumElements();
9758 int SplitNumElements = NumElements / 2;
9759 MVT ScalarVT = VT.getScalarType();
9760 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9762 // Rather than splitting build-vectors, just build two narrower build
9763 // vectors. This helps shuffling with splats and zeros.
9764 auto SplitVector = [&](SDValue V) {
9765 while (V.getOpcode() == ISD::BITCAST)
9766 V = V->getOperand(0);
9768 MVT OrigVT = V.getSimpleValueType();
9769 int OrigNumElements = OrigVT.getVectorNumElements();
9770 int OrigSplitNumElements = OrigNumElements / 2;
9771 MVT OrigScalarVT = OrigVT.getScalarType();
9772 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9776 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9778 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9779 DAG.getIntPtrConstant(0, DL));
9780 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9781 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9784 SmallVector<SDValue, 16> LoOps, HiOps;
9785 for (int i = 0; i < OrigSplitNumElements; ++i) {
9786 LoOps.push_back(BV->getOperand(i));
9787 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9789 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9790 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9792 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9793 DAG.getBitcast(SplitVT, HiV));
9796 SDValue LoV1, HiV1, LoV2, HiV2;
9797 std::tie(LoV1, HiV1) = SplitVector(V1);
9798 std::tie(LoV2, HiV2) = SplitVector(V2);
9800 // Now create two 4-way blends of these half-width vectors.
9801 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9802 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9803 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9804 for (int i = 0; i < SplitNumElements; ++i) {
9805 int M = HalfMask[i];
9806 if (M >= NumElements) {
9807 if (M >= NumElements + SplitNumElements)
9811 V2BlendMask.push_back(M - NumElements);
9812 V1BlendMask.push_back(-1);
9813 BlendMask.push_back(SplitNumElements + i);
9814 } else if (M >= 0) {
9815 if (M >= SplitNumElements)
9819 V2BlendMask.push_back(-1);
9820 V1BlendMask.push_back(M);
9821 BlendMask.push_back(i);
9823 V2BlendMask.push_back(-1);
9824 V1BlendMask.push_back(-1);
9825 BlendMask.push_back(-1);
9829 // Because the lowering happens after all combining takes place, we need to
9830 // manually combine these blend masks as much as possible so that we create
9831 // a minimal number of high-level vector shuffle nodes.
9833 // First try just blending the halves of V1 or V2.
9834 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9835 return DAG.getUNDEF(SplitVT);
9836 if (!UseLoV2 && !UseHiV2)
9837 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9838 if (!UseLoV1 && !UseHiV1)
9839 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9841 SDValue V1Blend, V2Blend;
9842 if (UseLoV1 && UseHiV1) {
9844 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9846 // We only use half of V1 so map the usage down into the final blend mask.
9847 V1Blend = UseLoV1 ? LoV1 : HiV1;
9848 for (int i = 0; i < SplitNumElements; ++i)
9849 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9850 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9852 if (UseLoV2 && UseHiV2) {
9854 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9856 // We only use half of V2 so map the usage down into the final blend mask.
9857 V2Blend = UseLoV2 ? LoV2 : HiV2;
9858 for (int i = 0; i < SplitNumElements; ++i)
9859 if (BlendMask[i] >= SplitNumElements)
9860 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9862 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9864 SDValue Lo = HalfBlend(LoMask);
9865 SDValue Hi = HalfBlend(HiMask);
9866 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9869 /// \brief Either split a vector in halves or decompose the shuffles and the
9872 /// This is provided as a good fallback for many lowerings of non-single-input
9873 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9874 /// between splitting the shuffle into 128-bit components and stitching those
9875 /// back together vs. extracting the single-input shuffles and blending those
9877 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9878 SDValue V2, ArrayRef<int> Mask,
9879 SelectionDAG &DAG) {
9880 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9881 "lower single-input shuffles as it "
9882 "could then recurse on itself.");
9883 int Size = Mask.size();
9885 // If this can be modeled as a broadcast of two elements followed by a blend,
9886 // prefer that lowering. This is especially important because broadcasts can
9887 // often fold with memory operands.
9888 auto DoBothBroadcast = [&] {
9889 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9892 if (V2BroadcastIdx == -1)
9893 V2BroadcastIdx = M - Size;
9894 else if (M - Size != V2BroadcastIdx)
9896 } else if (M >= 0) {
9897 if (V1BroadcastIdx == -1)
9899 else if (M != V1BroadcastIdx)
9904 if (DoBothBroadcast())
9905 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9908 // If the inputs all stem from a single 128-bit lane of each input, then we
9909 // split them rather than blending because the split will decompose to
9910 // unusually few instructions.
9911 int LaneCount = VT.getSizeInBits() / 128;
9912 int LaneSize = Size / LaneCount;
9913 SmallBitVector LaneInputs[2];
9914 LaneInputs[0].resize(LaneCount, false);
9915 LaneInputs[1].resize(LaneCount, false);
9916 for (int i = 0; i < Size; ++i)
9918 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9919 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9920 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9922 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9923 // that the decomposed single-input shuffles don't end up here.
9924 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9927 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9928 /// a permutation and blend of those lanes.
9930 /// This essentially blends the out-of-lane inputs to each lane into the lane
9931 /// from a permuted copy of the vector. This lowering strategy results in four
9932 /// instructions in the worst case for a single-input cross lane shuffle which
9933 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9934 /// of. Special cases for each particular shuffle pattern should be handled
9935 /// prior to trying this lowering.
9936 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9937 SDValue V1, SDValue V2,
9939 SelectionDAG &DAG) {
9940 // FIXME: This should probably be generalized for 512-bit vectors as well.
9941 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9942 int LaneSize = Mask.size() / 2;
9944 // If there are only inputs from one 128-bit lane, splitting will in fact be
9945 // less expensive. The flags track whether the given lane contains an element
9946 // that crosses to another lane.
9947 bool LaneCrossing[2] = {false, false};
9948 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9949 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9950 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9951 if (!LaneCrossing[0] || !LaneCrossing[1])
9952 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9954 if (isSingleInputShuffleMask(Mask)) {
9955 SmallVector<int, 32> FlippedBlendMask;
9956 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9957 FlippedBlendMask.push_back(
9958 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9960 : Mask[i] % LaneSize +
9961 (i / LaneSize) * LaneSize + Size));
9963 // Flip the vector, and blend the results which should now be in-lane. The
9964 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9965 // 5 for the high source. The value 3 selects the high half of source 2 and
9966 // the value 2 selects the low half of source 2. We only use source 2 to
9967 // allow folding it into a memory operand.
9968 unsigned PERMMask = 3 | 2 << 4;
9969 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9970 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9971 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9974 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9975 // will be handled by the above logic and a blend of the results, much like
9976 // other patterns in AVX.
9977 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9980 /// \brief Handle lowering 2-lane 128-bit shuffles.
9981 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9982 SDValue V2, ArrayRef<int> Mask,
9983 const X86Subtarget *Subtarget,
9984 SelectionDAG &DAG) {
9985 // TODO: If minimizing size and one of the inputs is a zero vector and the
9986 // the zero vector has only one use, we could use a VPERM2X128 to save the
9987 // instruction bytes needed to explicitly generate the zero vector.
9989 // Blends are faster and handle all the non-lane-crossing cases.
9990 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9994 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9995 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9997 // If either input operand is a zero vector, use VPERM2X128 because its mask
9998 // allows us to replace the zero input with an implicit zero.
9999 if (!IsV1Zero && !IsV2Zero) {
10000 // Check for patterns which can be matched with a single insert of a 128-bit
10002 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10003 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10004 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10005 VT.getVectorNumElements() / 2);
10006 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10007 DAG.getIntPtrConstant(0, DL));
10008 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10009 OnlyUsesV1 ? V1 : V2,
10010 DAG.getIntPtrConstant(0, DL));
10011 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10015 // Otherwise form a 128-bit permutation. After accounting for undefs,
10016 // convert the 64-bit shuffle mask selection values into 128-bit
10017 // selection bits by dividing the indexes by 2 and shifting into positions
10018 // defined by a vperm2*128 instruction's immediate control byte.
10020 // The immediate permute control byte looks like this:
10021 // [1:0] - select 128 bits from sources for low half of destination
10023 // [3] - zero low half of destination
10024 // [5:4] - select 128 bits from sources for high half of destination
10026 // [7] - zero high half of destination
10028 int MaskLO = Mask[0];
10029 if (MaskLO == SM_SentinelUndef)
10030 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10032 int MaskHI = Mask[2];
10033 if (MaskHI == SM_SentinelUndef)
10034 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10036 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10038 // If either input is a zero vector, replace it with an undef input.
10039 // Shuffle mask values < 4 are selecting elements of V1.
10040 // Shuffle mask values >= 4 are selecting elements of V2.
10041 // Adjust each half of the permute mask by clearing the half that was
10042 // selecting the zero vector and setting the zero mask bit.
10044 V1 = DAG.getUNDEF(VT);
10046 PermMask = (PermMask & 0xf0) | 0x08;
10048 PermMask = (PermMask & 0x0f) | 0x80;
10051 V2 = DAG.getUNDEF(VT);
10053 PermMask = (PermMask & 0xf0) | 0x08;
10055 PermMask = (PermMask & 0x0f) | 0x80;
10058 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10059 DAG.getConstant(PermMask, DL, MVT::i8));
10062 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10063 /// shuffling each lane.
10065 /// This will only succeed when the result of fixing the 128-bit lanes results
10066 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10067 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10068 /// the lane crosses early and then use simpler shuffles within each lane.
10070 /// FIXME: It might be worthwhile at some point to support this without
10071 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10072 /// in x86 only floating point has interesting non-repeating shuffles, and even
10073 /// those are still *marginally* more expensive.
10074 static SDValue lowerVectorShuffleByMerging128BitLanes(
10075 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10076 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10077 assert(!isSingleInputShuffleMask(Mask) &&
10078 "This is only useful with multiple inputs.");
10080 int Size = Mask.size();
10081 int LaneSize = 128 / VT.getScalarSizeInBits();
10082 int NumLanes = Size / LaneSize;
10083 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10085 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10086 // check whether the in-128-bit lane shuffles share a repeating pattern.
10087 SmallVector<int, 4> Lanes;
10088 Lanes.resize(NumLanes, -1);
10089 SmallVector<int, 4> InLaneMask;
10090 InLaneMask.resize(LaneSize, -1);
10091 for (int i = 0; i < Size; ++i) {
10095 int j = i / LaneSize;
10097 if (Lanes[j] < 0) {
10098 // First entry we've seen for this lane.
10099 Lanes[j] = Mask[i] / LaneSize;
10100 } else if (Lanes[j] != Mask[i] / LaneSize) {
10101 // This doesn't match the lane selected previously!
10105 // Check that within each lane we have a consistent shuffle mask.
10106 int k = i % LaneSize;
10107 if (InLaneMask[k] < 0) {
10108 InLaneMask[k] = Mask[i] % LaneSize;
10109 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10110 // This doesn't fit a repeating in-lane mask.
10115 // First shuffle the lanes into place.
10116 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10117 VT.getSizeInBits() / 64);
10118 SmallVector<int, 8> LaneMask;
10119 LaneMask.resize(NumLanes * 2, -1);
10120 for (int i = 0; i < NumLanes; ++i)
10121 if (Lanes[i] >= 0) {
10122 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10123 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10126 V1 = DAG.getBitcast(LaneVT, V1);
10127 V2 = DAG.getBitcast(LaneVT, V2);
10128 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10130 // Cast it back to the type we actually want.
10131 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10133 // Now do a simple shuffle that isn't lane crossing.
10134 SmallVector<int, 8> NewMask;
10135 NewMask.resize(Size, -1);
10136 for (int i = 0; i < Size; ++i)
10138 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10139 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10140 "Must not introduce lane crosses at this point!");
10142 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10145 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10148 /// This returns true if the elements from a particular input are already in the
10149 /// slot required by the given mask and require no permutation.
10150 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10151 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10152 int Size = Mask.size();
10153 for (int i = 0; i < Size; ++i)
10154 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10160 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10161 ArrayRef<int> Mask, SDValue V1,
10162 SDValue V2, SelectionDAG &DAG) {
10164 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10165 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10166 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10167 int NumElts = VT.getVectorNumElements();
10168 bool ShufpdMask = true;
10169 bool CommutableMask = true;
10170 unsigned Immediate = 0;
10171 for (int i = 0; i < NumElts; ++i) {
10174 int Val = (i & 6) + NumElts * (i & 1);
10175 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10176 if (Mask[i] < Val || Mask[i] > Val + 1)
10177 ShufpdMask = false;
10178 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10179 CommutableMask = false;
10180 Immediate |= (Mask[i] % 2) << i;
10183 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10184 DAG.getConstant(Immediate, DL, MVT::i8));
10185 if (CommutableMask)
10186 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10187 DAG.getConstant(Immediate, DL, MVT::i8));
10191 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10193 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10194 /// isn't available.
10195 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10196 const X86Subtarget *Subtarget,
10197 SelectionDAG &DAG) {
10199 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10200 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10202 ArrayRef<int> Mask = SVOp->getMask();
10203 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10205 SmallVector<int, 4> WidenedMask;
10206 if (canWidenShuffleElements(Mask, WidenedMask))
10207 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10210 if (isSingleInputShuffleMask(Mask)) {
10211 // Check for being able to broadcast a single element.
10212 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10213 Mask, Subtarget, DAG))
10216 // Use low duplicate instructions for masks that match their pattern.
10217 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10218 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10220 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10221 // Non-half-crossing single input shuffles can be lowerid with an
10222 // interleaved permutation.
10223 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10224 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10225 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10226 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10229 // With AVX2 we have direct support for this permutation.
10230 if (Subtarget->hasAVX2())
10231 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10232 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10234 // Otherwise, fall back.
10235 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10239 // X86 has dedicated unpack instructions that can handle specific blend
10240 // operations: UNPCKH and UNPCKL.
10241 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10242 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10243 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10244 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10245 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10246 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10247 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10248 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10250 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10254 // Check if the blend happens to exactly fit that of SHUFPD.
10256 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10259 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10260 // shuffle. However, if we have AVX2 and either inputs are already in place,
10261 // we will be able to shuffle even across lanes the other input in a single
10262 // instruction so skip this pattern.
10263 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10264 isShuffleMaskInputInPlace(1, Mask))))
10265 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10266 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10269 // If we have AVX2 then we always want to lower with a blend because an v4 we
10270 // can fully permute the elements.
10271 if (Subtarget->hasAVX2())
10272 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10275 // Otherwise fall back on generic lowering.
10276 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10279 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10281 /// This routine is only called when we have AVX2 and thus a reasonable
10282 /// instruction set for v4i64 shuffling..
10283 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10284 const X86Subtarget *Subtarget,
10285 SelectionDAG &DAG) {
10287 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10288 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10289 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10290 ArrayRef<int> Mask = SVOp->getMask();
10291 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10292 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10294 SmallVector<int, 4> WidenedMask;
10295 if (canWidenShuffleElements(Mask, WidenedMask))
10296 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10299 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10303 // Check for being able to broadcast a single element.
10304 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10305 Mask, Subtarget, DAG))
10308 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10309 // use lower latency instructions that will operate on both 128-bit lanes.
10310 SmallVector<int, 2> RepeatedMask;
10311 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10312 if (isSingleInputShuffleMask(Mask)) {
10313 int PSHUFDMask[] = {-1, -1, -1, -1};
10314 for (int i = 0; i < 2; ++i)
10315 if (RepeatedMask[i] >= 0) {
10316 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10317 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10319 return DAG.getBitcast(
10321 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10322 DAG.getBitcast(MVT::v8i32, V1),
10323 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10327 // AVX2 provides a direct instruction for permuting a single input across
10329 if (isSingleInputShuffleMask(Mask))
10330 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10331 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10333 // Try to use shift instructions.
10334 if (SDValue Shift =
10335 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10338 // Use dedicated unpack instructions for masks that match their pattern.
10339 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10340 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10341 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10342 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10343 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10344 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10345 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10346 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10348 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10349 // shuffle. However, if we have AVX2 and either inputs are already in place,
10350 // we will be able to shuffle even across lanes the other input in a single
10351 // instruction so skip this pattern.
10352 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10353 isShuffleMaskInputInPlace(1, Mask))))
10354 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10355 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10358 // Otherwise fall back on generic blend lowering.
10359 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10363 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10365 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10366 /// isn't available.
10367 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10368 const X86Subtarget *Subtarget,
10369 SelectionDAG &DAG) {
10371 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10372 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10373 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10374 ArrayRef<int> Mask = SVOp->getMask();
10375 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10377 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10381 // Check for being able to broadcast a single element.
10382 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10383 Mask, Subtarget, DAG))
10386 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10387 // options to efficiently lower the shuffle.
10388 SmallVector<int, 4> RepeatedMask;
10389 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10390 assert(RepeatedMask.size() == 4 &&
10391 "Repeated masks must be half the mask width!");
10393 // Use even/odd duplicate instructions for masks that match their pattern.
10394 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10395 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10396 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10397 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10399 if (isSingleInputShuffleMask(Mask))
10400 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10401 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10403 // Use dedicated unpack instructions for masks that match their pattern.
10404 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10405 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10406 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10407 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10408 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10409 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10410 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10411 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10413 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10414 // have already handled any direct blends. We also need to squash the
10415 // repeated mask into a simulated v4f32 mask.
10416 for (int i = 0; i < 4; ++i)
10417 if (RepeatedMask[i] >= 8)
10418 RepeatedMask[i] -= 4;
10419 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10422 // If we have a single input shuffle with different shuffle patterns in the
10423 // two 128-bit lanes use the variable mask to VPERMILPS.
10424 if (isSingleInputShuffleMask(Mask)) {
10425 SDValue VPermMask[8];
10426 for (int i = 0; i < 8; ++i)
10427 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10428 : DAG.getConstant(Mask[i], DL, MVT::i32);
10429 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10430 return DAG.getNode(
10431 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10432 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10434 if (Subtarget->hasAVX2())
10435 return DAG.getNode(
10436 X86ISD::VPERMV, DL, MVT::v8f32,
10437 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10438 MVT::v8i32, VPermMask)),
10441 // Otherwise, fall back.
10442 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10446 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10448 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10449 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10452 // If we have AVX2 then we always want to lower with a blend because at v8 we
10453 // can fully permute the elements.
10454 if (Subtarget->hasAVX2())
10455 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10458 // Otherwise fall back on generic lowering.
10459 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10462 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10464 /// This routine is only called when we have AVX2 and thus a reasonable
10465 /// instruction set for v8i32 shuffling..
10466 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10467 const X86Subtarget *Subtarget,
10468 SelectionDAG &DAG) {
10470 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10471 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10472 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10473 ArrayRef<int> Mask = SVOp->getMask();
10474 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10475 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10477 // Whenever we can lower this as a zext, that instruction is strictly faster
10478 // than any alternative. It also allows us to fold memory operands into the
10479 // shuffle in many cases.
10480 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10481 Mask, Subtarget, DAG))
10484 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10488 // Check for being able to broadcast a single element.
10489 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10490 Mask, Subtarget, DAG))
10493 // If the shuffle mask is repeated in each 128-bit lane we can use more
10494 // efficient instructions that mirror the shuffles across the two 128-bit
10496 SmallVector<int, 4> RepeatedMask;
10497 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10498 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10499 if (isSingleInputShuffleMask(Mask))
10500 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10501 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10503 // Use dedicated unpack instructions for masks that match their pattern.
10504 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10505 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10506 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10507 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10508 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10509 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10510 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10511 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10514 // Try to use shift instructions.
10515 if (SDValue Shift =
10516 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10520 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10523 // If the shuffle patterns aren't repeated but it is a single input, directly
10524 // generate a cross-lane VPERMD instruction.
10525 if (isSingleInputShuffleMask(Mask)) {
10526 SDValue VPermMask[8];
10527 for (int i = 0; i < 8; ++i)
10528 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10529 : DAG.getConstant(Mask[i], DL, MVT::i32);
10530 return DAG.getNode(
10531 X86ISD::VPERMV, DL, MVT::v8i32,
10532 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10535 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10537 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10538 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10541 // Otherwise fall back on generic blend lowering.
10542 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10546 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10548 /// This routine is only called when we have AVX2 and thus a reasonable
10549 /// instruction set for v16i16 shuffling..
10550 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10551 const X86Subtarget *Subtarget,
10552 SelectionDAG &DAG) {
10554 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10555 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10556 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10557 ArrayRef<int> Mask = SVOp->getMask();
10558 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10559 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10561 // Whenever we can lower this as a zext, that instruction is strictly faster
10562 // than any alternative. It also allows us to fold memory operands into the
10563 // shuffle in many cases.
10564 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10565 Mask, Subtarget, DAG))
10568 // Check for being able to broadcast a single element.
10569 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10570 Mask, Subtarget, DAG))
10573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10577 // Use dedicated unpack instructions for masks that match their pattern.
10578 if (isShuffleEquivalent(V1, V2, Mask,
10579 {// First 128-bit lane:
10580 0, 16, 1, 17, 2, 18, 3, 19,
10581 // Second 128-bit lane:
10582 8, 24, 9, 25, 10, 26, 11, 27}))
10583 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10584 if (isShuffleEquivalent(V1, V2, Mask,
10585 {// First 128-bit lane:
10586 4, 20, 5, 21, 6, 22, 7, 23,
10587 // Second 128-bit lane:
10588 12, 28, 13, 29, 14, 30, 15, 31}))
10589 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10591 // Try to use shift instructions.
10592 if (SDValue Shift =
10593 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10596 // Try to use byte rotation instructions.
10597 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10598 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10601 if (isSingleInputShuffleMask(Mask)) {
10602 // There are no generalized cross-lane shuffle operations available on i16
10604 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10605 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10608 SmallVector<int, 8> RepeatedMask;
10609 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10610 // As this is a single-input shuffle, the repeated mask should be
10611 // a strictly valid v8i16 mask that we can pass through to the v8i16
10612 // lowering to handle even the v16 case.
10613 return lowerV8I16GeneralSingleInputVectorShuffle(
10614 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10617 SDValue PSHUFBMask[32];
10618 for (int i = 0; i < 16; ++i) {
10619 if (Mask[i] == -1) {
10620 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10624 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10625 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10626 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10627 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10629 return DAG.getBitcast(MVT::v16i16,
10630 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10631 DAG.getBitcast(MVT::v32i8, V1),
10632 DAG.getNode(ISD::BUILD_VECTOR, DL,
10633 MVT::v32i8, PSHUFBMask)));
10636 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10638 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10639 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10642 // Otherwise fall back on generic lowering.
10643 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10646 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10648 /// This routine is only called when we have AVX2 and thus a reasonable
10649 /// instruction set for v32i8 shuffling..
10650 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10651 const X86Subtarget *Subtarget,
10652 SelectionDAG &DAG) {
10654 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10655 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10657 ArrayRef<int> Mask = SVOp->getMask();
10658 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10659 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10661 // Whenever we can lower this as a zext, that instruction is strictly faster
10662 // than any alternative. It also allows us to fold memory operands into the
10663 // shuffle in many cases.
10664 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10665 Mask, Subtarget, DAG))
10668 // Check for being able to broadcast a single element.
10669 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10670 Mask, Subtarget, DAG))
10673 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10677 // Use dedicated unpack instructions for masks that match their pattern.
10678 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10680 if (isShuffleEquivalent(
10682 {// First 128-bit lane:
10683 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10684 // Second 128-bit lane:
10685 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10686 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10687 if (isShuffleEquivalent(
10689 {// First 128-bit lane:
10690 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10691 // Second 128-bit lane:
10692 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10693 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10695 // Try to use shift instructions.
10696 if (SDValue Shift =
10697 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10700 // Try to use byte rotation instructions.
10701 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10702 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10705 if (isSingleInputShuffleMask(Mask)) {
10706 // There are no generalized cross-lane shuffle operations available on i8
10708 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10709 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10712 SDValue PSHUFBMask[32];
10713 for (int i = 0; i < 32; ++i)
10716 ? DAG.getUNDEF(MVT::i8)
10717 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10720 return DAG.getNode(
10721 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10722 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10725 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10727 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10728 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10731 // Otherwise fall back on generic lowering.
10732 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10735 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10737 /// This routine either breaks down the specific type of a 256-bit x86 vector
10738 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10739 /// together based on the available instructions.
10740 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10741 MVT VT, const X86Subtarget *Subtarget,
10742 SelectionDAG &DAG) {
10744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10745 ArrayRef<int> Mask = SVOp->getMask();
10747 // If we have a single input to the zero element, insert that into V1 if we
10748 // can do so cheaply.
10749 int NumElts = VT.getVectorNumElements();
10750 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10751 return M >= NumElts;
10754 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10755 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10756 DL, VT, V1, V2, Mask, Subtarget, DAG))
10759 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10760 // can check for those subtargets here and avoid much of the subtarget
10761 // querying in the per-vector-type lowering routines. With AVX1 we have
10762 // essentially *zero* ability to manipulate a 256-bit vector with integer
10763 // types. Since we'll use floating point types there eventually, just
10764 // immediately cast everything to a float and operate entirely in that domain.
10765 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10766 int ElementBits = VT.getScalarSizeInBits();
10767 if (ElementBits < 32)
10768 // No floating point type available, decompose into 128-bit vectors.
10769 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10771 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10772 VT.getVectorNumElements());
10773 V1 = DAG.getBitcast(FpVT, V1);
10774 V2 = DAG.getBitcast(FpVT, V2);
10775 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10778 switch (VT.SimpleTy) {
10780 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10782 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10784 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10786 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10788 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10790 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10793 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10797 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10798 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10799 ArrayRef<int> Mask,
10800 SDValue V1, SDValue V2,
10801 SelectionDAG &DAG) {
10802 assert(VT.getScalarSizeInBits() == 64 &&
10803 "Unexpected element type size for 128bit shuffle.");
10805 // To handle 256 bit vector requires VLX and most probably
10806 // function lowerV2X128VectorShuffle() is better solution.
10807 assert(VT.getSizeInBits() == 512 &&
10808 "Unexpected vector size for 128bit shuffle.");
10810 SmallVector<int, 4> WidenedMask;
10811 if (!canWidenShuffleElements(Mask, WidenedMask))
10814 // Form a 128-bit permutation.
10815 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10816 // bits defined by a vshuf64x2 instruction's immediate control byte.
10817 unsigned PermMask = 0, Imm = 0;
10818 unsigned ControlBitsNum = WidenedMask.size() / 2;
10820 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10821 if (WidenedMask[i] == SM_SentinelZero)
10824 // Use first element in place of undef mask.
10825 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10826 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10829 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10830 DAG.getConstant(PermMask, DL, MVT::i8));
10833 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10834 ArrayRef<int> Mask, SDValue V1,
10835 SDValue V2, SelectionDAG &DAG) {
10837 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10839 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10840 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10842 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10843 if (isSingleInputShuffleMask(Mask))
10844 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10846 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10849 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10850 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10851 const X86Subtarget *Subtarget,
10852 SelectionDAG &DAG) {
10854 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10855 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10856 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10857 ArrayRef<int> Mask = SVOp->getMask();
10858 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10860 if (SDValue Shuf128 =
10861 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10864 if (SDValue Unpck =
10865 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10868 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10871 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10872 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10873 const X86Subtarget *Subtarget,
10874 SelectionDAG &DAG) {
10876 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10877 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10878 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10879 ArrayRef<int> Mask = SVOp->getMask();
10880 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10882 if (SDValue Unpck =
10883 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10886 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10889 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10890 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10891 const X86Subtarget *Subtarget,
10892 SelectionDAG &DAG) {
10894 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10895 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10896 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10897 ArrayRef<int> Mask = SVOp->getMask();
10898 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10900 if (SDValue Shuf128 =
10901 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10904 if (SDValue Unpck =
10905 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10908 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10911 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10912 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10913 const X86Subtarget *Subtarget,
10914 SelectionDAG &DAG) {
10916 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10917 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10918 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10919 ArrayRef<int> Mask = SVOp->getMask();
10920 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10922 if (SDValue Unpck =
10923 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10926 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10929 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10930 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10931 const X86Subtarget *Subtarget,
10932 SelectionDAG &DAG) {
10934 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10935 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10936 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10937 ArrayRef<int> Mask = SVOp->getMask();
10938 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10939 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10941 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10944 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10945 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10946 const X86Subtarget *Subtarget,
10947 SelectionDAG &DAG) {
10949 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10950 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10951 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10952 ArrayRef<int> Mask = SVOp->getMask();
10953 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10954 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10956 // FIXME: Implement direct support for this type!
10957 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10960 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10962 /// This routine either breaks down the specific type of a 512-bit x86 vector
10963 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10964 /// together based on the available instructions.
10965 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10966 MVT VT, const X86Subtarget *Subtarget,
10967 SelectionDAG &DAG) {
10969 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10970 ArrayRef<int> Mask = SVOp->getMask();
10971 assert(Subtarget->hasAVX512() &&
10972 "Cannot lower 512-bit vectors w/ basic ISA!");
10974 // Check for being able to broadcast a single element.
10975 if (SDValue Broadcast =
10976 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10979 // Dispatch to each element type for lowering. If we don't have supprot for
10980 // specific element type shuffles at 512 bits, immediately split them and
10981 // lower them. Each lowering routine of a given type is allowed to assume that
10982 // the requisite ISA extensions for that element type are available.
10983 switch (VT.SimpleTy) {
10985 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10987 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10989 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10991 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10993 if (Subtarget->hasBWI())
10994 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10997 if (Subtarget->hasBWI())
10998 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11002 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11005 // Otherwise fall back on splitting.
11006 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11009 // Lower vXi1 vector shuffles.
11010 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11011 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11012 // vector, shuffle and then truncate it back.
11013 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11014 MVT VT, const X86Subtarget *Subtarget,
11015 SelectionDAG &DAG) {
11017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11018 ArrayRef<int> Mask = SVOp->getMask();
11019 assert(Subtarget->hasAVX512() &&
11020 "Cannot lower 512-bit vectors w/o basic ISA!");
11022 switch (VT.SimpleTy) {
11024 assert(false && "Expected a vector of i1 elements");
11027 ExtVT = MVT::v2i64;
11030 ExtVT = MVT::v4i32;
11033 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11036 ExtVT = MVT::v16i32;
11039 ExtVT = MVT::v32i16;
11042 ExtVT = MVT::v64i8;
11046 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11047 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11048 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11049 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11051 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11054 V2 = DAG.getUNDEF(ExtVT);
11055 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11056 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11057 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11058 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11060 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11061 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11062 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11064 /// \brief Top-level lowering for x86 vector shuffles.
11066 /// This handles decomposition, canonicalization, and lowering of all x86
11067 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11068 /// above in helper routines. The canonicalization attempts to widen shuffles
11069 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11070 /// s.t. only one of the two inputs needs to be tested, etc.
11071 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11072 SelectionDAG &DAG) {
11073 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11074 ArrayRef<int> Mask = SVOp->getMask();
11075 SDValue V1 = Op.getOperand(0);
11076 SDValue V2 = Op.getOperand(1);
11077 MVT VT = Op.getSimpleValueType();
11078 int NumElements = VT.getVectorNumElements();
11080 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
11082 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11083 "Can't lower MMX shuffles");
11085 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11086 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11087 if (V1IsUndef && V2IsUndef)
11088 return DAG.getUNDEF(VT);
11090 // When we create a shuffle node we put the UNDEF node to second operand,
11091 // but in some cases the first operand may be transformed to UNDEF.
11092 // In this case we should just commute the node.
11094 return DAG.getCommutedVectorShuffle(*SVOp);
11096 // Check for non-undef masks pointing at an undef vector and make the masks
11097 // undef as well. This makes it easier to match the shuffle based solely on
11101 if (M >= NumElements) {
11102 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11103 for (int &M : NewMask)
11104 if (M >= NumElements)
11106 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11109 // We actually see shuffles that are entirely re-arrangements of a set of
11110 // zero inputs. This mostly happens while decomposing complex shuffles into
11111 // simple ones. Directly lower these as a buildvector of zeros.
11112 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11113 if (Zeroable.all())
11114 return getZeroVector(VT, Subtarget, DAG, dl);
11116 // Try to collapse shuffles into using a vector type with fewer elements but
11117 // wider element types. We cap this to not form integers or floating point
11118 // elements wider than 64 bits, but it might be interesting to form i128
11119 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11120 SmallVector<int, 16> WidenedMask;
11121 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11122 canWidenShuffleElements(Mask, WidenedMask)) {
11123 MVT NewEltVT = VT.isFloatingPoint()
11124 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11125 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11126 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11127 // Make sure that the new vector type is legal. For example, v2f64 isn't
11129 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11130 V1 = DAG.getBitcast(NewVT, V1);
11131 V2 = DAG.getBitcast(NewVT, V2);
11132 return DAG.getBitcast(
11133 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11137 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11138 for (int M : SVOp->getMask())
11140 ++NumUndefElements;
11141 else if (M < NumElements)
11146 // Commute the shuffle as needed such that more elements come from V1 than
11147 // V2. This allows us to match the shuffle pattern strictly on how many
11148 // elements come from V1 without handling the symmetric cases.
11149 if (NumV2Elements > NumV1Elements)
11150 return DAG.getCommutedVectorShuffle(*SVOp);
11152 // When the number of V1 and V2 elements are the same, try to minimize the
11153 // number of uses of V2 in the low half of the vector. When that is tied,
11154 // ensure that the sum of indices for V1 is equal to or lower than the sum
11155 // indices for V2. When those are equal, try to ensure that the number of odd
11156 // indices for V1 is lower than the number of odd indices for V2.
11157 if (NumV1Elements == NumV2Elements) {
11158 int LowV1Elements = 0, LowV2Elements = 0;
11159 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11160 if (M >= NumElements)
11164 if (LowV2Elements > LowV1Elements) {
11165 return DAG.getCommutedVectorShuffle(*SVOp);
11166 } else if (LowV2Elements == LowV1Elements) {
11167 int SumV1Indices = 0, SumV2Indices = 0;
11168 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11169 if (SVOp->getMask()[i] >= NumElements)
11171 else if (SVOp->getMask()[i] >= 0)
11173 if (SumV2Indices < SumV1Indices) {
11174 return DAG.getCommutedVectorShuffle(*SVOp);
11175 } else if (SumV2Indices == SumV1Indices) {
11176 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11177 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11178 if (SVOp->getMask()[i] >= NumElements)
11179 NumV2OddIndices += i % 2;
11180 else if (SVOp->getMask()[i] >= 0)
11181 NumV1OddIndices += i % 2;
11182 if (NumV2OddIndices < NumV1OddIndices)
11183 return DAG.getCommutedVectorShuffle(*SVOp);
11188 // For each vector width, delegate to a specialized lowering routine.
11189 if (VT.getSizeInBits() == 128)
11190 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11192 if (VT.getSizeInBits() == 256)
11193 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11195 if (VT.getSizeInBits() == 512)
11196 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11199 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11200 llvm_unreachable("Unimplemented!");
11203 // This function assumes its argument is a BUILD_VECTOR of constants or
11204 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11206 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11207 unsigned &MaskValue) {
11209 unsigned NumElems = BuildVector->getNumOperands();
11211 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11212 // We don't handle the >2 lanes case right now.
11213 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11217 unsigned NumElemsInLane = NumElems / NumLanes;
11219 // Blend for v16i16 should be symmetric for the both lanes.
11220 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11221 SDValue EltCond = BuildVector->getOperand(i);
11222 SDValue SndLaneEltCond =
11223 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11225 int Lane1Cond = -1, Lane2Cond = -1;
11226 if (isa<ConstantSDNode>(EltCond))
11227 Lane1Cond = !isZero(EltCond);
11228 if (isa<ConstantSDNode>(SndLaneEltCond))
11229 Lane2Cond = !isZero(SndLaneEltCond);
11231 unsigned LaneMask = 0;
11232 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11233 // Lane1Cond != 0, means we want the first argument.
11234 // Lane1Cond == 0, means we want the second argument.
11235 // The encoding of this argument is 0 for the first argument, 1
11236 // for the second. Therefore, invert the condition.
11237 LaneMask = !Lane1Cond << i;
11238 else if (Lane1Cond < 0)
11239 LaneMask = !Lane2Cond << i;
11243 MaskValue |= LaneMask;
11245 MaskValue |= LaneMask << NumElemsInLane;
11250 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11251 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11252 const X86Subtarget *Subtarget,
11253 SelectionDAG &DAG) {
11254 SDValue Cond = Op.getOperand(0);
11255 SDValue LHS = Op.getOperand(1);
11256 SDValue RHS = Op.getOperand(2);
11258 MVT VT = Op.getSimpleValueType();
11260 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11262 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11264 // Only non-legal VSELECTs reach this lowering, convert those into generic
11265 // shuffles and re-use the shuffle lowering path for blends.
11266 SmallVector<int, 32> Mask;
11267 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11268 SDValue CondElt = CondBV->getOperand(i);
11270 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11272 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11275 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11276 // A vselect where all conditions and data are constants can be optimized into
11277 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11278 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11279 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11280 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11283 // Try to lower this to a blend-style vector shuffle. This can handle all
11284 // constant condition cases.
11285 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11288 // Variable blends are only legal from SSE4.1 onward.
11289 if (!Subtarget->hasSSE41())
11292 // Only some types will be legal on some subtargets. If we can emit a legal
11293 // VSELECT-matching blend, return Op, and but if we need to expand, return
11295 switch (Op.getSimpleValueType().SimpleTy) {
11297 // Most of the vector types have blends past SSE4.1.
11301 // The byte blends for AVX vectors were introduced only in AVX2.
11302 if (Subtarget->hasAVX2())
11309 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11310 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11313 // FIXME: We should custom lower this by fixing the condition and using i8
11319 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11320 MVT VT = Op.getSimpleValueType();
11323 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11326 if (VT.getSizeInBits() == 8) {
11327 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11328 Op.getOperand(0), Op.getOperand(1));
11329 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11330 DAG.getValueType(VT));
11331 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11334 if (VT.getSizeInBits() == 16) {
11335 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11336 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11338 return DAG.getNode(
11339 ISD::TRUNCATE, dl, MVT::i16,
11340 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11341 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11342 Op.getOperand(1)));
11343 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11344 Op.getOperand(0), Op.getOperand(1));
11345 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11346 DAG.getValueType(VT));
11347 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11350 if (VT == MVT::f32) {
11351 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11352 // the result back to FR32 register. It's only worth matching if the
11353 // result has a single use which is a store or a bitcast to i32. And in
11354 // the case of a store, it's not worth it if the index is a constant 0,
11355 // because a MOVSSmr can be used instead, which is smaller and faster.
11356 if (!Op.hasOneUse())
11358 SDNode *User = *Op.getNode()->use_begin();
11359 if ((User->getOpcode() != ISD::STORE ||
11360 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11361 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11362 (User->getOpcode() != ISD::BITCAST ||
11363 User->getValueType(0) != MVT::i32))
11365 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11366 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11368 return DAG.getBitcast(MVT::f32, Extract);
11371 if (VT == MVT::i32 || VT == MVT::i64) {
11372 // ExtractPS/pextrq works with constant index.
11373 if (isa<ConstantSDNode>(Op.getOperand(1)))
11379 /// Extract one bit from mask vector, like v16i1 or v8i1.
11380 /// AVX-512 feature.
11382 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11383 SDValue Vec = Op.getOperand(0);
11385 MVT VecVT = Vec.getSimpleValueType();
11386 SDValue Idx = Op.getOperand(1);
11387 MVT EltVT = Op.getSimpleValueType();
11389 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11390 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11391 "Unexpected vector type in ExtractBitFromMaskVector");
11393 // variable index can't be handled in mask registers,
11394 // extend vector to VR512
11395 if (!isa<ConstantSDNode>(Idx)) {
11396 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11397 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11398 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11399 ExtVT.getVectorElementType(), Ext, Idx);
11400 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11403 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11404 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11405 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11406 rc = getRegClassFor(MVT::v16i1);
11407 unsigned MaxSift = rc->getSize()*8 - 1;
11408 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11409 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11410 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11411 DAG.getConstant(MaxSift, dl, MVT::i8));
11412 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11413 DAG.getIntPtrConstant(0, dl));
11417 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11418 SelectionDAG &DAG) const {
11420 SDValue Vec = Op.getOperand(0);
11421 MVT VecVT = Vec.getSimpleValueType();
11422 SDValue Idx = Op.getOperand(1);
11424 if (Op.getSimpleValueType() == MVT::i1)
11425 return ExtractBitFromMaskVector(Op, DAG);
11427 if (!isa<ConstantSDNode>(Idx)) {
11428 if (VecVT.is512BitVector() ||
11429 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11430 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11433 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11434 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11435 MaskEltVT.getSizeInBits());
11437 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11438 auto PtrVT = getPointerTy(DAG.getDataLayout());
11439 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11440 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11441 DAG.getConstant(0, dl, PtrVT));
11442 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11443 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11444 DAG.getConstant(0, dl, PtrVT));
11449 // If this is a 256-bit vector result, first extract the 128-bit vector and
11450 // then extract the element from the 128-bit vector.
11451 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11453 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11454 // Get the 128-bit vector.
11455 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11456 MVT EltVT = VecVT.getVectorElementType();
11458 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11460 //if (IdxVal >= NumElems/2)
11461 // IdxVal -= NumElems/2;
11462 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11463 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11464 DAG.getConstant(IdxVal, dl, MVT::i32));
11467 assert(VecVT.is128BitVector() && "Unexpected vector length");
11469 if (Subtarget->hasSSE41())
11470 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11473 MVT VT = Op.getSimpleValueType();
11474 // TODO: handle v16i8.
11475 if (VT.getSizeInBits() == 16) {
11476 SDValue Vec = Op.getOperand(0);
11477 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11479 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11480 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11481 DAG.getBitcast(MVT::v4i32, Vec),
11482 Op.getOperand(1)));
11483 // Transform it so it match pextrw which produces a 32-bit result.
11484 MVT EltVT = MVT::i32;
11485 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11486 Op.getOperand(0), Op.getOperand(1));
11487 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11488 DAG.getValueType(VT));
11489 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11492 if (VT.getSizeInBits() == 32) {
11493 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11497 // SHUFPS the element to the lowest double word, then movss.
11498 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11499 MVT VVT = Op.getOperand(0).getSimpleValueType();
11500 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11501 DAG.getUNDEF(VVT), Mask);
11502 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11503 DAG.getIntPtrConstant(0, dl));
11506 if (VT.getSizeInBits() == 64) {
11507 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11508 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11509 // to match extract_elt for f64.
11510 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11514 // UNPCKHPD the element to the lowest double word, then movsd.
11515 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11516 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11517 int Mask[2] = { 1, -1 };
11518 MVT VVT = Op.getOperand(0).getSimpleValueType();
11519 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11520 DAG.getUNDEF(VVT), Mask);
11521 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11522 DAG.getIntPtrConstant(0, dl));
11528 /// Insert one bit to mask vector, like v16i1 or v8i1.
11529 /// AVX-512 feature.
11531 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11533 SDValue Vec = Op.getOperand(0);
11534 SDValue Elt = Op.getOperand(1);
11535 SDValue Idx = Op.getOperand(2);
11536 MVT VecVT = Vec.getSimpleValueType();
11538 if (!isa<ConstantSDNode>(Idx)) {
11539 // Non constant index. Extend source and destination,
11540 // insert element and then truncate the result.
11541 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11542 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11543 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11544 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11545 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11546 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11549 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11550 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11552 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11553 DAG.getConstant(IdxVal, dl, MVT::i8));
11554 if (Vec.getOpcode() == ISD::UNDEF)
11556 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11559 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11560 SelectionDAG &DAG) const {
11561 MVT VT = Op.getSimpleValueType();
11562 MVT EltVT = VT.getVectorElementType();
11564 if (EltVT == MVT::i1)
11565 return InsertBitToMaskVector(Op, DAG);
11568 SDValue N0 = Op.getOperand(0);
11569 SDValue N1 = Op.getOperand(1);
11570 SDValue N2 = Op.getOperand(2);
11571 if (!isa<ConstantSDNode>(N2))
11573 auto *N2C = cast<ConstantSDNode>(N2);
11574 unsigned IdxVal = N2C->getZExtValue();
11576 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11577 // into that, and then insert the subvector back into the result.
11578 if (VT.is256BitVector() || VT.is512BitVector()) {
11579 // With a 256-bit vector, we can insert into the zero element efficiently
11580 // using a blend if we have AVX or AVX2 and the right data type.
11581 if (VT.is256BitVector() && IdxVal == 0) {
11582 // TODO: It is worthwhile to cast integer to floating point and back
11583 // and incur a domain crossing penalty if that's what we'll end up
11584 // doing anyway after extracting to a 128-bit vector.
11585 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11586 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11587 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11588 N2 = DAG.getIntPtrConstant(1, dl);
11589 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11593 // Get the desired 128-bit vector chunk.
11594 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11596 // Insert the element into the desired chunk.
11597 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11598 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11600 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11601 DAG.getConstant(IdxIn128, dl, MVT::i32));
11603 // Insert the changed part back into the bigger vector
11604 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11606 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11608 if (Subtarget->hasSSE41()) {
11609 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11611 if (VT == MVT::v8i16) {
11612 Opc = X86ISD::PINSRW;
11614 assert(VT == MVT::v16i8);
11615 Opc = X86ISD::PINSRB;
11618 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11620 if (N1.getValueType() != MVT::i32)
11621 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11622 if (N2.getValueType() != MVT::i32)
11623 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11624 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11627 if (EltVT == MVT::f32) {
11628 // Bits [7:6] of the constant are the source select. This will always be
11629 // zero here. The DAG Combiner may combine an extract_elt index into
11630 // these bits. For example (insert (extract, 3), 2) could be matched by
11631 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11632 // Bits [5:4] of the constant are the destination select. This is the
11633 // value of the incoming immediate.
11634 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11635 // combine either bitwise AND or insert of float 0.0 to set these bits.
11637 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11638 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11639 // If this is an insertion of 32-bits into the low 32-bits of
11640 // a vector, we prefer to generate a blend with immediate rather
11641 // than an insertps. Blends are simpler operations in hardware and so
11642 // will always have equal or better performance than insertps.
11643 // But if optimizing for size and there's a load folding opportunity,
11644 // generate insertps because blendps does not have a 32-bit memory
11646 N2 = DAG.getIntPtrConstant(1, dl);
11647 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11648 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11650 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11651 // Create this as a scalar to vector..
11652 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11653 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11656 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11657 // PINSR* works with constant index.
11662 if (EltVT == MVT::i8)
11665 if (EltVT.getSizeInBits() == 16) {
11666 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11667 // as its second argument.
11668 if (N1.getValueType() != MVT::i32)
11669 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11670 if (N2.getValueType() != MVT::i32)
11671 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11672 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11677 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11679 MVT OpVT = Op.getSimpleValueType();
11681 // If this is a 256-bit vector result, first insert into a 128-bit
11682 // vector and then insert into the 256-bit vector.
11683 if (!OpVT.is128BitVector()) {
11684 // Insert into a 128-bit vector.
11685 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11686 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11687 OpVT.getVectorNumElements() / SizeFactor);
11689 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11691 // Insert the 128-bit vector.
11692 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11695 if (OpVT == MVT::v1i64 &&
11696 Op.getOperand(0).getValueType() == MVT::i64)
11697 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11699 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11700 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11701 return DAG.getBitcast(
11702 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11705 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11706 // a simple subregister reference or explicit instructions to grab
11707 // upper bits of a vector.
11708 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11709 SelectionDAG &DAG) {
11711 SDValue In = Op.getOperand(0);
11712 SDValue Idx = Op.getOperand(1);
11713 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11714 MVT ResVT = Op.getSimpleValueType();
11715 MVT InVT = In.getSimpleValueType();
11717 if (Subtarget->hasFp256()) {
11718 if (ResVT.is128BitVector() &&
11719 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11720 isa<ConstantSDNode>(Idx)) {
11721 return Extract128BitVector(In, IdxVal, DAG, dl);
11723 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11724 isa<ConstantSDNode>(Idx)) {
11725 return Extract256BitVector(In, IdxVal, DAG, dl);
11731 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11732 // simple superregister reference or explicit instructions to insert
11733 // the upper bits of a vector.
11734 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11735 SelectionDAG &DAG) {
11736 if (!Subtarget->hasAVX())
11740 SDValue Vec = Op.getOperand(0);
11741 SDValue SubVec = Op.getOperand(1);
11742 SDValue Idx = Op.getOperand(2);
11744 if (!isa<ConstantSDNode>(Idx))
11747 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11748 MVT OpVT = Op.getSimpleValueType();
11749 MVT SubVecVT = SubVec.getSimpleValueType();
11751 // Fold two 16-byte subvector loads into one 32-byte load:
11752 // (insert_subvector (insert_subvector undef, (load addr), 0),
11753 // (load addr + 16), Elts/2)
11755 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11756 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11757 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11758 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11759 if (Idx2 && Idx2->getZExtValue() == 0) {
11760 SDValue SubVec2 = Vec.getOperand(1);
11761 // If needed, look through a bitcast to get to the load.
11762 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11763 SubVec2 = SubVec2.getOperand(0);
11765 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11767 unsigned Alignment = FirstLd->getAlignment();
11768 unsigned AS = FirstLd->getAddressSpace();
11769 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11770 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11771 OpVT, AS, Alignment, &Fast) && Fast) {
11772 SDValue Ops[] = { SubVec2, SubVec };
11773 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11780 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11781 SubVecVT.is128BitVector())
11782 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11784 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11785 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11787 if (OpVT.getVectorElementType() == MVT::i1) {
11788 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11790 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11791 SDValue Undef = DAG.getUNDEF(OpVT);
11792 unsigned NumElems = OpVT.getVectorNumElements();
11793 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11795 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11796 // Zero upper bits of the Vec
11797 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11798 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11800 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11802 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11803 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11806 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11808 // Zero upper bits of the Vec2
11809 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11810 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11811 // Zero lower bits of the Vec
11812 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11813 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11814 // Merge them together
11815 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11821 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11822 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11823 // one of the above mentioned nodes. It has to be wrapped because otherwise
11824 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11825 // be used to form addressing mode. These wrapped nodes will be selected
11828 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11829 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11831 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11832 // global base reg.
11833 unsigned char OpFlag = 0;
11834 unsigned WrapperKind = X86ISD::Wrapper;
11835 CodeModel::Model M = DAG.getTarget().getCodeModel();
11837 if (Subtarget->isPICStyleRIPRel() &&
11838 (M == CodeModel::Small || M == CodeModel::Kernel))
11839 WrapperKind = X86ISD::WrapperRIP;
11840 else if (Subtarget->isPICStyleGOT())
11841 OpFlag = X86II::MO_GOTOFF;
11842 else if (Subtarget->isPICStyleStubPIC())
11843 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11845 auto PtrVT = getPointerTy(DAG.getDataLayout());
11846 SDValue Result = DAG.getTargetConstantPool(
11847 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11849 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11850 // With PIC, the address is actually $g + Offset.
11853 DAG.getNode(ISD::ADD, DL, PtrVT,
11854 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11860 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11861 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11863 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11864 // global base reg.
11865 unsigned char OpFlag = 0;
11866 unsigned WrapperKind = X86ISD::Wrapper;
11867 CodeModel::Model M = DAG.getTarget().getCodeModel();
11869 if (Subtarget->isPICStyleRIPRel() &&
11870 (M == CodeModel::Small || M == CodeModel::Kernel))
11871 WrapperKind = X86ISD::WrapperRIP;
11872 else if (Subtarget->isPICStyleGOT())
11873 OpFlag = X86II::MO_GOTOFF;
11874 else if (Subtarget->isPICStyleStubPIC())
11875 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11877 auto PtrVT = getPointerTy(DAG.getDataLayout());
11878 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11880 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11882 // With PIC, the address is actually $g + Offset.
11885 DAG.getNode(ISD::ADD, DL, PtrVT,
11886 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11892 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11893 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11895 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11896 // global base reg.
11897 unsigned char OpFlag = 0;
11898 unsigned WrapperKind = X86ISD::Wrapper;
11899 CodeModel::Model M = DAG.getTarget().getCodeModel();
11901 if (Subtarget->isPICStyleRIPRel() &&
11902 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11903 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11904 OpFlag = X86II::MO_GOTPCREL;
11905 WrapperKind = X86ISD::WrapperRIP;
11906 } else if (Subtarget->isPICStyleGOT()) {
11907 OpFlag = X86II::MO_GOT;
11908 } else if (Subtarget->isPICStyleStubPIC()) {
11909 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11910 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11911 OpFlag = X86II::MO_DARWIN_NONLAZY;
11914 auto PtrVT = getPointerTy(DAG.getDataLayout());
11915 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11918 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11920 // With PIC, the address is actually $g + Offset.
11921 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11922 !Subtarget->is64Bit()) {
11924 DAG.getNode(ISD::ADD, DL, PtrVT,
11925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11928 // For symbols that require a load from a stub to get the address, emit the
11930 if (isGlobalStubReference(OpFlag))
11931 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11932 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11933 false, false, false, 0);
11939 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11940 // Create the TargetBlockAddressAddress node.
11941 unsigned char OpFlags =
11942 Subtarget->ClassifyBlockAddressReference();
11943 CodeModel::Model M = DAG.getTarget().getCodeModel();
11944 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11945 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11947 auto PtrVT = getPointerTy(DAG.getDataLayout());
11948 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11950 if (Subtarget->isPICStyleRIPRel() &&
11951 (M == CodeModel::Small || M == CodeModel::Kernel))
11952 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11954 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11956 // With PIC, the address is actually $g + Offset.
11957 if (isGlobalRelativeToPICBase(OpFlags)) {
11958 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11959 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11966 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11967 int64_t Offset, SelectionDAG &DAG) const {
11968 // Create the TargetGlobalAddress node, folding in the constant
11969 // offset if it is legal.
11970 unsigned char OpFlags =
11971 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11972 CodeModel::Model M = DAG.getTarget().getCodeModel();
11973 auto PtrVT = getPointerTy(DAG.getDataLayout());
11975 if (OpFlags == X86II::MO_NO_FLAG &&
11976 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11977 // A direct static reference to a global.
11978 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11981 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11984 if (Subtarget->isPICStyleRIPRel() &&
11985 (M == CodeModel::Small || M == CodeModel::Kernel))
11986 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11988 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11990 // With PIC, the address is actually $g + Offset.
11991 if (isGlobalRelativeToPICBase(OpFlags)) {
11992 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11993 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11996 // For globals that require a load from a stub to get the address, emit the
11998 if (isGlobalStubReference(OpFlags))
11999 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12000 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12001 false, false, false, 0);
12003 // If there was a non-zero offset that we didn't fold, create an explicit
12004 // addition for it.
12006 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12007 DAG.getConstant(Offset, dl, PtrVT));
12013 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12014 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12015 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12016 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12020 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12021 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12022 unsigned char OperandFlags, bool LocalDynamic = false) {
12023 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12024 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12026 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12027 GA->getValueType(0),
12031 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12035 SDValue Ops[] = { Chain, TGA, *InFlag };
12036 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12038 SDValue Ops[] = { Chain, TGA };
12039 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12042 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12043 MFI->setAdjustsStack(true);
12044 MFI->setHasCalls(true);
12046 SDValue Flag = Chain.getValue(1);
12047 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12050 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12052 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12055 SDLoc dl(GA); // ? function entry point might be better
12056 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12057 DAG.getNode(X86ISD::GlobalBaseReg,
12058 SDLoc(), PtrVT), InFlag);
12059 InFlag = Chain.getValue(1);
12061 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12064 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12066 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12068 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12069 X86::RAX, X86II::MO_TLSGD);
12072 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12078 // Get the start address of the TLS block for this module.
12079 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12080 .getInfo<X86MachineFunctionInfo>();
12081 MFI->incNumLocalDynamicTLSAccesses();
12085 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12086 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12089 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12090 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12091 InFlag = Chain.getValue(1);
12092 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12093 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12096 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12100 unsigned char OperandFlags = X86II::MO_DTPOFF;
12101 unsigned WrapperKind = X86ISD::Wrapper;
12102 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12103 GA->getValueType(0),
12104 GA->getOffset(), OperandFlags);
12105 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12107 // Add x@dtpoff with the base.
12108 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12111 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12112 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12113 const EVT PtrVT, TLSModel::Model model,
12114 bool is64Bit, bool isPIC) {
12117 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12118 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12119 is64Bit ? 257 : 256));
12121 SDValue ThreadPointer =
12122 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12123 MachinePointerInfo(Ptr), false, false, false, 0);
12125 unsigned char OperandFlags = 0;
12126 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12128 unsigned WrapperKind = X86ISD::Wrapper;
12129 if (model == TLSModel::LocalExec) {
12130 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12131 } else if (model == TLSModel::InitialExec) {
12133 OperandFlags = X86II::MO_GOTTPOFF;
12134 WrapperKind = X86ISD::WrapperRIP;
12136 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12139 llvm_unreachable("Unexpected model");
12142 // emit "addl x@ntpoff,%eax" (local exec)
12143 // or "addl x@indntpoff,%eax" (initial exec)
12144 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12146 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12147 GA->getOffset(), OperandFlags);
12148 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12150 if (model == TLSModel::InitialExec) {
12151 if (isPIC && !is64Bit) {
12152 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12153 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12157 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12158 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12159 false, false, false, 0);
12162 // The address of the thread local variable is the add of the thread
12163 // pointer with the offset of the variable.
12164 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12168 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12170 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12171 const GlobalValue *GV = GA->getGlobal();
12172 auto PtrVT = getPointerTy(DAG.getDataLayout());
12174 if (Subtarget->isTargetELF()) {
12175 if (DAG.getTarget().Options.EmulatedTLS)
12176 return LowerToTLSEmulatedModel(GA, DAG);
12177 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12179 case TLSModel::GeneralDynamic:
12180 if (Subtarget->is64Bit())
12181 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12182 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12183 case TLSModel::LocalDynamic:
12184 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12185 Subtarget->is64Bit());
12186 case TLSModel::InitialExec:
12187 case TLSModel::LocalExec:
12188 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12189 DAG.getTarget().getRelocationModel() ==
12192 llvm_unreachable("Unknown TLS model.");
12195 if (Subtarget->isTargetDarwin()) {
12196 // Darwin only has one model of TLS. Lower to that.
12197 unsigned char OpFlag = 0;
12198 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12199 X86ISD::WrapperRIP : X86ISD::Wrapper;
12201 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12202 // global base reg.
12203 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12204 !Subtarget->is64Bit();
12206 OpFlag = X86II::MO_TLVP_PIC_BASE;
12208 OpFlag = X86II::MO_TLVP;
12210 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12211 GA->getValueType(0),
12212 GA->getOffset(), OpFlag);
12213 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12215 // With PIC32, the address is actually $g + Offset.
12217 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12218 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12221 // Lowering the machine isd will make sure everything is in the right
12223 SDValue Chain = DAG.getEntryNode();
12224 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12225 SDValue Args[] = { Chain, Offset };
12226 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12228 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12229 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12230 MFI->setAdjustsStack(true);
12232 // And our return value (tls address) is in the standard call return value
12234 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12235 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12238 if (Subtarget->isTargetKnownWindowsMSVC() ||
12239 Subtarget->isTargetWindowsGNU()) {
12240 // Just use the implicit TLS architecture
12241 // Need to generate someting similar to:
12242 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12244 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12245 // mov rcx, qword [rdx+rcx*8]
12246 // mov eax, .tls$:tlsvar
12247 // [rax+rcx] contains the address
12248 // Windows 64bit: gs:0x58
12249 // Windows 32bit: fs:__tls_array
12252 SDValue Chain = DAG.getEntryNode();
12254 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12255 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12256 // use its literal value of 0x2C.
12257 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12258 ? Type::getInt8PtrTy(*DAG.getContext(),
12260 : Type::getInt32PtrTy(*DAG.getContext(),
12263 SDValue TlsArray = Subtarget->is64Bit()
12264 ? DAG.getIntPtrConstant(0x58, dl)
12265 : (Subtarget->isTargetWindowsGNU()
12266 ? DAG.getIntPtrConstant(0x2C, dl)
12267 : DAG.getExternalSymbol("_tls_array", PtrVT));
12269 SDValue ThreadPointer =
12270 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12274 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12275 res = ThreadPointer;
12277 // Load the _tls_index variable
12278 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12279 if (Subtarget->is64Bit())
12280 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12281 MachinePointerInfo(), MVT::i32, false, false,
12284 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12287 auto &DL = DAG.getDataLayout();
12289 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12290 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12292 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12295 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12298 // Get the offset of start of .tls section
12299 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12300 GA->getValueType(0),
12301 GA->getOffset(), X86II::MO_SECREL);
12302 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12304 // The address of the thread local variable is the add of the thread
12305 // pointer with the offset of the variable.
12306 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12309 llvm_unreachable("TLS not implemented for this target.");
12312 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12313 /// and take a 2 x i32 value to shift plus a shift amount.
12314 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12315 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12316 MVT VT = Op.getSimpleValueType();
12317 unsigned VTBits = VT.getSizeInBits();
12319 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12320 SDValue ShOpLo = Op.getOperand(0);
12321 SDValue ShOpHi = Op.getOperand(1);
12322 SDValue ShAmt = Op.getOperand(2);
12323 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12324 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12326 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12327 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12328 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12329 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12330 : DAG.getConstant(0, dl, VT);
12332 SDValue Tmp2, Tmp3;
12333 if (Op.getOpcode() == ISD::SHL_PARTS) {
12334 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12335 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12337 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12338 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12341 // If the shift amount is larger or equal than the width of a part we can't
12342 // rely on the results of shld/shrd. Insert a test and select the appropriate
12343 // values for large shift amounts.
12344 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12345 DAG.getConstant(VTBits, dl, MVT::i8));
12346 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12347 AndNode, DAG.getConstant(0, dl, MVT::i8));
12350 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12351 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12352 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12354 if (Op.getOpcode() == ISD::SHL_PARTS) {
12355 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12356 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12358 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12359 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12362 SDValue Ops[2] = { Lo, Hi };
12363 return DAG.getMergeValues(Ops, dl);
12366 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12367 SelectionDAG &DAG) const {
12368 SDValue Src = Op.getOperand(0);
12369 MVT SrcVT = Src.getSimpleValueType();
12370 MVT VT = Op.getSimpleValueType();
12373 if (SrcVT.isVector()) {
12374 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12375 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12376 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12377 DAG.getUNDEF(SrcVT)));
12379 if (SrcVT.getVectorElementType() == MVT::i1) {
12380 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12381 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12382 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12387 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12388 "Unknown SINT_TO_FP to lower!");
12390 // These are really Legal; return the operand so the caller accepts it as
12392 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12394 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12395 Subtarget->is64Bit()) {
12399 unsigned Size = SrcVT.getSizeInBits()/8;
12400 MachineFunction &MF = DAG.getMachineFunction();
12401 auto PtrVT = getPointerTy(MF.getDataLayout());
12402 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12403 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12404 SDValue Chain = DAG.getStore(
12405 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12406 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12408 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12411 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12413 SelectionDAG &DAG) const {
12417 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12419 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12421 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12423 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12425 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12426 MachineMemOperand *MMO;
12428 int SSFI = FI->getIndex();
12429 MMO = DAG.getMachineFunction().getMachineMemOperand(
12430 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12431 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12433 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12434 StackSlot = StackSlot.getOperand(1);
12436 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12437 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12439 Tys, Ops, SrcVT, MMO);
12442 Chain = Result.getValue(1);
12443 SDValue InFlag = Result.getValue(2);
12445 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12446 // shouldn't be necessary except that RFP cannot be live across
12447 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12448 MachineFunction &MF = DAG.getMachineFunction();
12449 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12450 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12451 auto PtrVT = getPointerTy(MF.getDataLayout());
12452 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12453 Tys = DAG.getVTList(MVT::Other);
12455 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12457 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12458 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12459 MachineMemOperand::MOStore, SSFISize, SSFISize);
12461 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12462 Ops, Op.getValueType(), MMO);
12463 Result = DAG.getLoad(
12464 Op.getValueType(), DL, Chain, StackSlot,
12465 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12466 false, false, false, 0);
12472 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12473 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12474 SelectionDAG &DAG) const {
12475 // This algorithm is not obvious. Here it is what we're trying to output:
12478 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12479 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12481 haddpd %xmm0, %xmm0
12483 pshufd $0x4e, %xmm0, %xmm1
12489 LLVMContext *Context = DAG.getContext();
12491 // Build some magic constants.
12492 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12493 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12494 auto PtrVT = getPointerTy(DAG.getDataLayout());
12495 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12497 SmallVector<Constant*,2> CV1;
12499 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12500 APInt(64, 0x4330000000000000ULL))));
12502 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12503 APInt(64, 0x4530000000000000ULL))));
12504 Constant *C1 = ConstantVector::get(CV1);
12505 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12507 // Load the 64-bit value into an XMM register.
12508 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12511 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12512 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12513 false, false, false, 16);
12515 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12518 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12519 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12520 false, false, false, 16);
12521 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12522 // TODO: Are there any fast-math-flags to propagate here?
12523 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12526 if (Subtarget->hasSSE3()) {
12527 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12528 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12530 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12531 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12533 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12534 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12537 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12538 DAG.getIntPtrConstant(0, dl));
12541 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12542 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12543 SelectionDAG &DAG) const {
12545 // FP constant to bias correct the final result.
12546 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12549 // Load the 32-bit value into an XMM register.
12550 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12553 // Zero out the upper parts of the register.
12554 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12556 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12557 DAG.getBitcast(MVT::v2f64, Load),
12558 DAG.getIntPtrConstant(0, dl));
12560 // Or the load with the bias.
12561 SDValue Or = DAG.getNode(
12562 ISD::OR, dl, MVT::v2i64,
12563 DAG.getBitcast(MVT::v2i64,
12564 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12565 DAG.getBitcast(MVT::v2i64,
12566 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12568 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12569 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12571 // Subtract the bias.
12572 // TODO: Are there any fast-math-flags to propagate here?
12573 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12575 // Handle final rounding.
12576 EVT DestVT = Op.getValueType();
12578 if (DestVT.bitsLT(MVT::f64))
12579 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12580 DAG.getIntPtrConstant(0, dl));
12581 if (DestVT.bitsGT(MVT::f64))
12582 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12584 // Handle final rounding.
12588 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12589 const X86Subtarget &Subtarget) {
12590 // The algorithm is the following:
12591 // #ifdef __SSE4_1__
12592 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12593 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12594 // (uint4) 0x53000000, 0xaa);
12596 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12597 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12599 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12600 // return (float4) lo + fhi;
12602 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12603 // reassociate the two FADDs, and if we do that, the algorithm fails
12604 // spectacularly (PR24512).
12605 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12606 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12607 // there's also the MachineCombiner reassociations happening on Machine IR.
12608 if (DAG.getTarget().Options.UnsafeFPMath)
12612 SDValue V = Op->getOperand(0);
12613 EVT VecIntVT = V.getValueType();
12614 bool Is128 = VecIntVT == MVT::v4i32;
12615 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12616 // If we convert to something else than the supported type, e.g., to v4f64,
12618 if (VecFloatVT != Op->getValueType(0))
12621 unsigned NumElts = VecIntVT.getVectorNumElements();
12622 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12623 "Unsupported custom type");
12624 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12626 // In the #idef/#else code, we have in common:
12627 // - The vector of constants:
12633 // Create the splat vector for 0x4b000000.
12634 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12635 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12636 CstLow, CstLow, CstLow, CstLow};
12637 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12638 makeArrayRef(&CstLowArray[0], NumElts));
12639 // Create the splat vector for 0x53000000.
12640 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12641 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12642 CstHigh, CstHigh, CstHigh, CstHigh};
12643 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12644 makeArrayRef(&CstHighArray[0], NumElts));
12646 // Create the right shift.
12647 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12648 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12649 CstShift, CstShift, CstShift, CstShift};
12650 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12651 makeArrayRef(&CstShiftArray[0], NumElts));
12652 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12655 if (Subtarget.hasSSE41()) {
12656 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12657 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12658 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12659 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12660 // Low will be bitcasted right away, so do not bother bitcasting back to its
12662 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12663 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12664 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12665 // (uint4) 0x53000000, 0xaa);
12666 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12667 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12668 // High will be bitcasted right away, so do not bother bitcasting back to
12669 // its original type.
12670 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12671 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12673 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12674 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12675 CstMask, CstMask, CstMask);
12676 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12677 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12678 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12680 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12681 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12684 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12685 SDValue CstFAdd = DAG.getConstantFP(
12686 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12687 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12688 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12689 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12690 makeArrayRef(&CstFAddArray[0], NumElts));
12692 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12693 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12694 // TODO: Are there any fast-math-flags to propagate here?
12696 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12697 // return (float4) lo + fhi;
12698 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12699 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12702 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12703 SelectionDAG &DAG) const {
12704 SDValue N0 = Op.getOperand(0);
12705 MVT SVT = N0.getSimpleValueType();
12708 switch (SVT.SimpleTy) {
12710 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12715 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12716 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12717 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12721 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12724 if (Subtarget->hasAVX512())
12725 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12726 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12728 llvm_unreachable(nullptr);
12731 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12732 SelectionDAG &DAG) const {
12733 SDValue N0 = Op.getOperand(0);
12735 auto PtrVT = getPointerTy(DAG.getDataLayout());
12737 if (Op.getValueType().isVector())
12738 return lowerUINT_TO_FP_vec(Op, DAG);
12740 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12741 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12742 // the optimization here.
12743 if (DAG.SignBitIsZero(N0))
12744 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12746 MVT SrcVT = N0.getSimpleValueType();
12747 MVT DstVT = Op.getSimpleValueType();
12749 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12750 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12751 // Conversions from unsigned i32 to f32/f64 are legal,
12752 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12756 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12757 return LowerUINT_TO_FP_i64(Op, DAG);
12758 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12759 return LowerUINT_TO_FP_i32(Op, DAG);
12760 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12763 // Make a 64-bit buffer, and use it to build an FILD.
12764 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12765 if (SrcVT == MVT::i32) {
12766 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12767 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12768 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12769 StackSlot, MachinePointerInfo(),
12771 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12772 OffsetSlot, MachinePointerInfo(),
12774 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12778 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12779 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12780 StackSlot, MachinePointerInfo(),
12782 // For i64 source, we need to add the appropriate power of 2 if the input
12783 // was negative. This is the same as the optimization in
12784 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12785 // we must be careful to do the computation in x87 extended precision, not
12786 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12787 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12788 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12789 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12790 MachineMemOperand::MOLoad, 8, 8);
12792 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12793 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12794 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12797 APInt FF(32, 0x5F800000ULL);
12799 // Check whether the sign bit is set.
12800 SDValue SignSet = DAG.getSetCC(
12801 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12802 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12804 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12805 SDValue FudgePtr = DAG.getConstantPool(
12806 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12808 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12809 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12810 SDValue Four = DAG.getIntPtrConstant(4, dl);
12811 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12813 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12815 // Load the value out, extending it from f32 to f80.
12816 // FIXME: Avoid the extend by constructing the right constant pool?
12817 SDValue Fudge = DAG.getExtLoad(
12818 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12819 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12820 false, false, false, 4);
12821 // Extend everything to 80 bits to force it to be done on x87.
12822 // TODO: Are there any fast-math-flags to propagate here?
12823 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12824 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12825 DAG.getIntPtrConstant(0, dl));
12828 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12829 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12830 // just return an <SDValue(), SDValue()> pair.
12831 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12832 // to i16, i32 or i64, and we lower it to a legal sequence.
12833 // If lowered to the final integer result we return a <result, SDValue()> pair.
12834 // Otherwise we lower it to a sequence ending with a FIST, return a
12835 // <FIST, StackSlot> pair, and the caller is responsible for loading
12836 // the final integer result from StackSlot.
12837 std::pair<SDValue,SDValue>
12838 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12839 bool IsSigned, bool IsReplace) const {
12842 EVT DstTy = Op.getValueType();
12843 EVT TheVT = Op.getOperand(0).getValueType();
12844 auto PtrVT = getPointerTy(DAG.getDataLayout());
12846 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12847 // f16 must be promoted before using the lowering in this routine.
12848 // fp128 does not use this lowering.
12849 return std::make_pair(SDValue(), SDValue());
12852 // If using FIST to compute an unsigned i64, we'll need some fixup
12853 // to handle values above the maximum signed i64. A FIST is always
12854 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12855 bool UnsignedFixup = !IsSigned &&
12856 DstTy == MVT::i64 &&
12857 (!Subtarget->is64Bit() ||
12858 !isScalarFPTypeInSSEReg(TheVT));
12860 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12861 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12862 // The low 32 bits of the fist result will have the correct uint32 result.
12863 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12867 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12868 DstTy.getSimpleVT() >= MVT::i16 &&
12869 "Unknown FP_TO_INT to lower!");
12871 // These are really Legal.
12872 if (DstTy == MVT::i32 &&
12873 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12874 return std::make_pair(SDValue(), SDValue());
12875 if (Subtarget->is64Bit() &&
12876 DstTy == MVT::i64 &&
12877 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12878 return std::make_pair(SDValue(), SDValue());
12880 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12882 MachineFunction &MF = DAG.getMachineFunction();
12883 unsigned MemSize = DstTy.getSizeInBits()/8;
12884 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12885 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12888 switch (DstTy.getSimpleVT().SimpleTy) {
12889 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12890 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12891 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12892 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12895 SDValue Chain = DAG.getEntryNode();
12896 SDValue Value = Op.getOperand(0);
12897 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12899 if (UnsignedFixup) {
12901 // Conversion to unsigned i64 is implemented with a select,
12902 // depending on whether the source value fits in the range
12903 // of a signed i64. Let Thresh be the FP equivalent of
12904 // 0x8000000000000000ULL.
12906 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12907 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12908 // Fist-to-mem64 FistSrc
12909 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12910 // to XOR'ing the high 32 bits with Adjust.
12912 // Being a power of 2, Thresh is exactly representable in all FP formats.
12913 // For X87 we'd like to use the smallest FP type for this constant, but
12914 // for DAG type consistency we have to match the FP operand type.
12916 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12917 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12918 bool LosesInfo = false;
12919 if (TheVT == MVT::f64)
12920 // The rounding mode is irrelevant as the conversion should be exact.
12921 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12923 else if (TheVT == MVT::f80)
12924 Status = Thresh.convert(APFloat::x87DoubleExtended,
12925 APFloat::rmNearestTiesToEven, &LosesInfo);
12927 assert(Status == APFloat::opOK && !LosesInfo &&
12928 "FP conversion should have been exact");
12930 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12932 SDValue Cmp = DAG.getSetCC(DL,
12933 getSetCCResultType(DAG.getDataLayout(),
12934 *DAG.getContext(), TheVT),
12935 Value, ThreshVal, ISD::SETLT);
12936 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12937 DAG.getConstant(0, DL, MVT::i32),
12938 DAG.getConstant(0x80000000, DL, MVT::i32));
12939 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12940 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12941 *DAG.getContext(), TheVT),
12942 Value, ThreshVal, ISD::SETLT);
12943 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12946 // FIXME This causes a redundant load/store if the SSE-class value is already
12947 // in memory, such as if it is on the callstack.
12948 if (isScalarFPTypeInSSEReg(TheVT)) {
12949 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12950 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12951 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12953 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12955 Chain, StackSlot, DAG.getValueType(TheVT)
12958 MachineMemOperand *MMO =
12959 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12960 MachineMemOperand::MOLoad, MemSize, MemSize);
12961 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12962 Chain = Value.getValue(1);
12963 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12964 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12967 MachineMemOperand *MMO =
12968 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12969 MachineMemOperand::MOStore, MemSize, MemSize);
12971 if (UnsignedFixup) {
12973 // Insert the FIST, load its result as two i32's,
12974 // and XOR the high i32 with Adjust.
12976 SDValue FistOps[] = { Chain, Value, StackSlot };
12977 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12978 FistOps, DstTy, MMO);
12980 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12981 MachinePointerInfo(),
12982 false, false, false, 0);
12983 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12984 DAG.getConstant(4, DL, PtrVT));
12986 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12987 MachinePointerInfo(),
12988 false, false, false, 0);
12989 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12991 if (Subtarget->is64Bit()) {
12992 // Join High32 and Low32 into a 64-bit result.
12993 // (High32 << 32) | Low32
12994 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12995 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12996 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12997 DAG.getConstant(32, DL, MVT::i8));
12998 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12999 return std::make_pair(Result, SDValue());
13002 SDValue ResultOps[] = { Low32, High32 };
13004 SDValue pair = IsReplace
13005 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13006 : DAG.getMergeValues(ResultOps, DL);
13007 return std::make_pair(pair, SDValue());
13009 // Build the FP_TO_INT*_IN_MEM
13010 SDValue Ops[] = { Chain, Value, StackSlot };
13011 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13013 return std::make_pair(FIST, StackSlot);
13017 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13018 const X86Subtarget *Subtarget) {
13019 MVT VT = Op->getSimpleValueType(0);
13020 SDValue In = Op->getOperand(0);
13021 MVT InVT = In.getSimpleValueType();
13024 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
13025 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13027 // Optimize vectors in AVX mode:
13030 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13031 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13032 // Concat upper and lower parts.
13035 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13036 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13037 // Concat upper and lower parts.
13040 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13041 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13042 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13045 if (Subtarget->hasInt256())
13046 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13048 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13049 SDValue Undef = DAG.getUNDEF(InVT);
13050 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13051 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13052 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13054 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13055 VT.getVectorNumElements()/2);
13057 OpLo = DAG.getBitcast(HVT, OpLo);
13058 OpHi = DAG.getBitcast(HVT, OpHi);
13060 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13063 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13064 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13065 MVT VT = Op->getSimpleValueType(0);
13066 SDValue In = Op->getOperand(0);
13067 MVT InVT = In.getSimpleValueType();
13069 unsigned int NumElts = VT.getVectorNumElements();
13070 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13073 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13074 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13076 assert(InVT.getVectorElementType() == MVT::i1);
13077 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13079 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13081 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13083 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13084 if (VT.is512BitVector())
13086 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13089 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13090 SelectionDAG &DAG) {
13091 if (Subtarget->hasFp256())
13092 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13098 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13099 SelectionDAG &DAG) {
13101 MVT VT = Op.getSimpleValueType();
13102 SDValue In = Op.getOperand(0);
13103 MVT SVT = In.getSimpleValueType();
13105 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13106 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13108 if (Subtarget->hasFp256())
13109 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13112 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13113 VT.getVectorNumElements() != SVT.getVectorNumElements());
13117 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13119 MVT VT = Op.getSimpleValueType();
13120 SDValue In = Op.getOperand(0);
13121 MVT InVT = In.getSimpleValueType();
13123 if (VT == MVT::i1) {
13124 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13125 "Invalid scalar TRUNCATE operation");
13126 if (InVT.getSizeInBits() >= 32)
13128 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13129 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13131 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13132 "Invalid TRUNCATE operation");
13134 // move vector to mask - truncate solution for SKX
13135 if (VT.getVectorElementType() == MVT::i1) {
13136 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13137 Subtarget->hasBWI())
13138 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13139 if ((InVT.is256BitVector() || InVT.is128BitVector())
13140 && InVT.getScalarSizeInBits() <= 16 &&
13141 Subtarget->hasBWI() && Subtarget->hasVLX())
13142 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13143 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13144 Subtarget->hasDQI())
13145 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13146 if ((InVT.is256BitVector() || InVT.is128BitVector())
13147 && InVT.getScalarSizeInBits() >= 32 &&
13148 Subtarget->hasDQI() && Subtarget->hasVLX())
13149 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13152 if (VT.getVectorElementType() == MVT::i1) {
13153 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13154 unsigned NumElts = InVT.getVectorNumElements();
13155 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13156 if (InVT.getSizeInBits() < 512) {
13157 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13158 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13163 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13164 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13165 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13168 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13169 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13170 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13171 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13173 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13174 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13175 if (Subtarget->hasInt256()) {
13176 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13177 In = DAG.getBitcast(MVT::v8i32, In);
13178 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13180 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13181 DAG.getIntPtrConstant(0, DL));
13184 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13185 DAG.getIntPtrConstant(0, DL));
13186 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13187 DAG.getIntPtrConstant(2, DL));
13188 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13189 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13190 static const int ShufMask[] = {0, 2, 4, 6};
13191 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13194 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13195 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13196 if (Subtarget->hasInt256()) {
13197 In = DAG.getBitcast(MVT::v32i8, In);
13199 SmallVector<SDValue,32> pshufbMask;
13200 for (unsigned i = 0; i < 2; ++i) {
13201 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13202 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13203 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13204 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13205 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13206 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13207 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13208 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13209 for (unsigned j = 0; j < 8; ++j)
13210 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13212 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13213 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13214 In = DAG.getBitcast(MVT::v4i64, In);
13216 static const int ShufMask[] = {0, 2, -1, -1};
13217 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13219 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13220 DAG.getIntPtrConstant(0, DL));
13221 return DAG.getBitcast(VT, In);
13224 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13225 DAG.getIntPtrConstant(0, DL));
13227 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13228 DAG.getIntPtrConstant(4, DL));
13230 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13231 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13233 // The PSHUFB mask:
13234 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13235 -1, -1, -1, -1, -1, -1, -1, -1};
13237 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13238 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13239 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13241 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13242 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13244 // The MOVLHPS Mask:
13245 static const int ShufMask2[] = {0, 1, 4, 5};
13246 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13247 return DAG.getBitcast(MVT::v8i16, res);
13250 // Handle truncation of V256 to V128 using shuffles.
13251 if (!VT.is128BitVector() || !InVT.is256BitVector())
13254 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13256 unsigned NumElems = VT.getVectorNumElements();
13257 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13259 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13260 // Prepare truncation shuffle mask
13261 for (unsigned i = 0; i != NumElems; ++i)
13262 MaskVec[i] = i * 2;
13263 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13264 DAG.getUNDEF(NVT), &MaskVec[0]);
13265 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13266 DAG.getIntPtrConstant(0, DL));
13269 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13270 SelectionDAG &DAG) const {
13271 assert(!Op.getSimpleValueType().isVector());
13273 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13274 /*IsSigned=*/ true, /*IsReplace=*/ false);
13275 SDValue FIST = Vals.first, StackSlot = Vals.second;
13276 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13277 if (!FIST.getNode())
13280 if (StackSlot.getNode())
13281 // Load the result.
13282 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13283 FIST, StackSlot, MachinePointerInfo(),
13284 false, false, false, 0);
13286 // The node is the result.
13290 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13291 SelectionDAG &DAG) const {
13292 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13293 /*IsSigned=*/ false, /*IsReplace=*/ false);
13294 SDValue FIST = Vals.first, StackSlot = Vals.second;
13295 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13296 if (!FIST.getNode())
13299 if (StackSlot.getNode())
13300 // Load the result.
13301 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13302 FIST, StackSlot, MachinePointerInfo(),
13303 false, false, false, 0);
13305 // The node is the result.
13309 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13311 MVT VT = Op.getSimpleValueType();
13312 SDValue In = Op.getOperand(0);
13313 MVT SVT = In.getSimpleValueType();
13315 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13317 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13318 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13319 In, DAG.getUNDEF(SVT)));
13322 /// The only differences between FABS and FNEG are the mask and the logic op.
13323 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13324 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13325 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13326 "Wrong opcode for lowering FABS or FNEG.");
13328 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13330 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13331 // into an FNABS. We'll lower the FABS after that if it is still in use.
13333 for (SDNode *User : Op->uses())
13334 if (User->getOpcode() == ISD::FNEG)
13338 MVT VT = Op.getSimpleValueType();
13340 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13341 // decide if we should generate a 16-byte constant mask when we only need 4 or
13342 // 8 bytes for the scalar case.
13348 if (VT.isVector()) {
13350 EltVT = VT.getVectorElementType();
13351 NumElts = VT.getVectorNumElements();
13353 // There are no scalar bitwise logical SSE/AVX instructions, so we
13354 // generate a 16-byte vector constant and logic op even for the scalar case.
13355 // Using a 16-byte mask allows folding the load of the mask with
13356 // the logic op, so it can save (~4 bytes) on code size.
13357 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13359 NumElts = (VT == MVT::f64) ? 2 : 4;
13362 unsigned EltBits = EltVT.getSizeInBits();
13363 LLVMContext *Context = DAG.getContext();
13364 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13366 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13367 Constant *C = ConstantInt::get(*Context, MaskElt);
13368 C = ConstantVector::getSplat(NumElts, C);
13369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13370 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13371 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13373 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13374 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13375 false, false, false, Alignment);
13377 SDValue Op0 = Op.getOperand(0);
13378 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13380 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13381 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13384 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13386 // For the scalar case extend to a 128-bit vector, perform the logic op,
13387 // and extract the scalar result back out.
13388 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13389 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13390 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13391 DAG.getIntPtrConstant(0, dl));
13394 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13396 LLVMContext *Context = DAG.getContext();
13397 SDValue Op0 = Op.getOperand(0);
13398 SDValue Op1 = Op.getOperand(1);
13400 MVT VT = Op.getSimpleValueType();
13401 MVT SrcVT = Op1.getSimpleValueType();
13403 // If second operand is smaller, extend it first.
13404 if (SrcVT.bitsLT(VT)) {
13405 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13408 // And if it is bigger, shrink it first.
13409 if (SrcVT.bitsGT(VT)) {
13410 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13414 // At this point the operands and the result should have the same
13415 // type, and that won't be f80 since that is not custom lowered.
13417 const fltSemantics &Sem =
13418 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13419 const unsigned SizeInBits = VT.getSizeInBits();
13421 SmallVector<Constant *, 4> CV(
13422 VT == MVT::f64 ? 2 : 4,
13423 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13425 // First, clear all bits but the sign bit from the second operand (sign).
13426 CV[0] = ConstantFP::get(*Context,
13427 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13428 Constant *C = ConstantVector::get(CV);
13429 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13430 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13432 // Perform all logic operations as 16-byte vectors because there are no
13433 // scalar FP logic instructions in SSE. This allows load folding of the
13434 // constants into the logic instructions.
13435 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13437 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13438 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13439 false, false, false, 16);
13440 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13441 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13443 // Next, clear the sign bit from the first operand (magnitude).
13444 // If it's a constant, we can clear it here.
13445 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13446 APFloat APF = Op0CN->getValueAPF();
13447 // If the magnitude is a positive zero, the sign bit alone is enough.
13448 if (APF.isPosZero())
13449 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13450 DAG.getIntPtrConstant(0, dl));
13452 CV[0] = ConstantFP::get(*Context, APF);
13454 CV[0] = ConstantFP::get(
13456 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13458 C = ConstantVector::get(CV);
13459 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13461 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13462 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13463 false, false, false, 16);
13464 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13465 if (!isa<ConstantFPSDNode>(Op0)) {
13466 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13467 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13469 // OR the magnitude value with the sign bit.
13470 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13472 DAG.getIntPtrConstant(0, dl));
13475 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13476 SDValue N0 = Op.getOperand(0);
13478 MVT VT = Op.getSimpleValueType();
13480 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13481 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13482 DAG.getConstant(1, dl, VT));
13483 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13486 // Check whether an OR'd tree is PTEST-able.
13487 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13488 SelectionDAG &DAG) {
13489 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13491 if (!Subtarget->hasSSE41())
13494 if (!Op->hasOneUse())
13497 SDNode *N = Op.getNode();
13500 SmallVector<SDValue, 8> Opnds;
13501 DenseMap<SDValue, unsigned> VecInMap;
13502 SmallVector<SDValue, 8> VecIns;
13503 EVT VT = MVT::Other;
13505 // Recognize a special case where a vector is casted into wide integer to
13507 Opnds.push_back(N->getOperand(0));
13508 Opnds.push_back(N->getOperand(1));
13510 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13511 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13512 // BFS traverse all OR'd operands.
13513 if (I->getOpcode() == ISD::OR) {
13514 Opnds.push_back(I->getOperand(0));
13515 Opnds.push_back(I->getOperand(1));
13516 // Re-evaluate the number of nodes to be traversed.
13517 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13521 // Quit if a non-EXTRACT_VECTOR_ELT
13522 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13525 // Quit if without a constant index.
13526 SDValue Idx = I->getOperand(1);
13527 if (!isa<ConstantSDNode>(Idx))
13530 SDValue ExtractedFromVec = I->getOperand(0);
13531 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13532 if (M == VecInMap.end()) {
13533 VT = ExtractedFromVec.getValueType();
13534 // Quit if not 128/256-bit vector.
13535 if (!VT.is128BitVector() && !VT.is256BitVector())
13537 // Quit if not the same type.
13538 if (VecInMap.begin() != VecInMap.end() &&
13539 VT != VecInMap.begin()->first.getValueType())
13541 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13542 VecIns.push_back(ExtractedFromVec);
13544 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13547 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13548 "Not extracted from 128-/256-bit vector.");
13550 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13552 for (DenseMap<SDValue, unsigned>::const_iterator
13553 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13554 // Quit if not all elements are used.
13555 if (I->second != FullMask)
13559 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13561 // Cast all vectors into TestVT for PTEST.
13562 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13563 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13565 // If more than one full vectors are evaluated, OR them first before PTEST.
13566 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13567 // Each iteration will OR 2 nodes and append the result until there is only
13568 // 1 node left, i.e. the final OR'd value of all vectors.
13569 SDValue LHS = VecIns[Slot];
13570 SDValue RHS = VecIns[Slot + 1];
13571 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13574 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13575 VecIns.back(), VecIns.back());
13578 /// \brief return true if \c Op has a use that doesn't just read flags.
13579 static bool hasNonFlagsUse(SDValue Op) {
13580 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13582 SDNode *User = *UI;
13583 unsigned UOpNo = UI.getOperandNo();
13584 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13585 // Look pass truncate.
13586 UOpNo = User->use_begin().getOperandNo();
13587 User = *User->use_begin();
13590 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13591 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13597 /// Emit nodes that will be selected as "test Op0,Op0", or something
13599 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13600 SelectionDAG &DAG) const {
13601 if (Op.getValueType() == MVT::i1) {
13602 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13603 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13604 DAG.getConstant(0, dl, MVT::i8));
13606 // CF and OF aren't always set the way we want. Determine which
13607 // of these we need.
13608 bool NeedCF = false;
13609 bool NeedOF = false;
13612 case X86::COND_A: case X86::COND_AE:
13613 case X86::COND_B: case X86::COND_BE:
13616 case X86::COND_G: case X86::COND_GE:
13617 case X86::COND_L: case X86::COND_LE:
13618 case X86::COND_O: case X86::COND_NO: {
13619 // Check if we really need to set the
13620 // Overflow flag. If NoSignedWrap is present
13621 // that is not actually needed.
13622 switch (Op->getOpcode()) {
13627 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13628 if (BinNode->Flags.hasNoSignedWrap())
13638 // See if we can use the EFLAGS value from the operand instead of
13639 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13640 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13641 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13642 // Emit a CMP with 0, which is the TEST pattern.
13643 //if (Op.getValueType() == MVT::i1)
13644 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13645 // DAG.getConstant(0, MVT::i1));
13646 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13647 DAG.getConstant(0, dl, Op.getValueType()));
13649 unsigned Opcode = 0;
13650 unsigned NumOperands = 0;
13652 // Truncate operations may prevent the merge of the SETCC instruction
13653 // and the arithmetic instruction before it. Attempt to truncate the operands
13654 // of the arithmetic instruction and use a reduced bit-width instruction.
13655 bool NeedTruncation = false;
13656 SDValue ArithOp = Op;
13657 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13658 SDValue Arith = Op->getOperand(0);
13659 // Both the trunc and the arithmetic op need to have one user each.
13660 if (Arith->hasOneUse())
13661 switch (Arith.getOpcode()) {
13668 NeedTruncation = true;
13674 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13675 // which may be the result of a CAST. We use the variable 'Op', which is the
13676 // non-casted variable when we check for possible users.
13677 switch (ArithOp.getOpcode()) {
13679 // Due to an isel shortcoming, be conservative if this add is likely to be
13680 // selected as part of a load-modify-store instruction. When the root node
13681 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13682 // uses of other nodes in the match, such as the ADD in this case. This
13683 // leads to the ADD being left around and reselected, with the result being
13684 // two adds in the output. Alas, even if none our users are stores, that
13685 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13686 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13687 // climbing the DAG back to the root, and it doesn't seem to be worth the
13689 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13690 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13691 if (UI->getOpcode() != ISD::CopyToReg &&
13692 UI->getOpcode() != ISD::SETCC &&
13693 UI->getOpcode() != ISD::STORE)
13696 if (ConstantSDNode *C =
13697 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13698 // An add of one will be selected as an INC.
13699 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13700 Opcode = X86ISD::INC;
13705 // An add of negative one (subtract of one) will be selected as a DEC.
13706 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13707 Opcode = X86ISD::DEC;
13713 // Otherwise use a regular EFLAGS-setting add.
13714 Opcode = X86ISD::ADD;
13719 // If we have a constant logical shift that's only used in a comparison
13720 // against zero turn it into an equivalent AND. This allows turning it into
13721 // a TEST instruction later.
13722 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13723 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13724 EVT VT = Op.getValueType();
13725 unsigned BitWidth = VT.getSizeInBits();
13726 unsigned ShAmt = Op->getConstantOperandVal(1);
13727 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13729 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13730 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13731 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13732 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13734 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13735 DAG.getConstant(Mask, dl, VT));
13736 DAG.ReplaceAllUsesWith(Op, New);
13742 // If the primary and result isn't used, don't bother using X86ISD::AND,
13743 // because a TEST instruction will be better.
13744 if (!hasNonFlagsUse(Op))
13750 // Due to the ISEL shortcoming noted above, be conservative if this op is
13751 // likely to be selected as part of a load-modify-store instruction.
13752 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13753 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13754 if (UI->getOpcode() == ISD::STORE)
13757 // Otherwise use a regular EFLAGS-setting instruction.
13758 switch (ArithOp.getOpcode()) {
13759 default: llvm_unreachable("unexpected operator!");
13760 case ISD::SUB: Opcode = X86ISD::SUB; break;
13761 case ISD::XOR: Opcode = X86ISD::XOR; break;
13762 case ISD::AND: Opcode = X86ISD::AND; break;
13764 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13765 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13766 if (EFLAGS.getNode())
13769 Opcode = X86ISD::OR;
13783 return SDValue(Op.getNode(), 1);
13789 // If we found that truncation is beneficial, perform the truncation and
13791 if (NeedTruncation) {
13792 EVT VT = Op.getValueType();
13793 SDValue WideVal = Op->getOperand(0);
13794 EVT WideVT = WideVal.getValueType();
13795 unsigned ConvertedOp = 0;
13796 // Use a target machine opcode to prevent further DAGCombine
13797 // optimizations that may separate the arithmetic operations
13798 // from the setcc node.
13799 switch (WideVal.getOpcode()) {
13801 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13802 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13803 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13804 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13805 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13809 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13810 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13811 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13812 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13813 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13819 // Emit a CMP with 0, which is the TEST pattern.
13820 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13821 DAG.getConstant(0, dl, Op.getValueType()));
13823 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13824 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13826 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13827 DAG.ReplaceAllUsesWith(Op, New);
13828 return SDValue(New.getNode(), 1);
13831 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13833 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13834 SDLoc dl, SelectionDAG &DAG) const {
13835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13836 if (C->getAPIntValue() == 0)
13837 return EmitTest(Op0, X86CC, dl, DAG);
13839 if (Op0.getValueType() == MVT::i1)
13840 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13843 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13844 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13845 // Do the comparison at i32 if it's smaller, besides the Atom case.
13846 // This avoids subregister aliasing issues. Keep the smaller reference
13847 // if we're optimizing for size, however, as that'll allow better folding
13848 // of memory operations.
13849 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13850 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13851 !Subtarget->isAtom()) {
13852 unsigned ExtendOp =
13853 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13854 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13855 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13857 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13858 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13859 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13861 return SDValue(Sub.getNode(), 1);
13863 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13866 /// Convert a comparison if required by the subtarget.
13867 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13868 SelectionDAG &DAG) const {
13869 // If the subtarget does not support the FUCOMI instruction, floating-point
13870 // comparisons have to be converted.
13871 if (Subtarget->hasCMov() ||
13872 Cmp.getOpcode() != X86ISD::CMP ||
13873 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13874 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13877 // The instruction selector will select an FUCOM instruction instead of
13878 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13879 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13880 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13882 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13883 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13884 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13885 DAG.getConstant(8, dl, MVT::i8));
13886 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13887 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13890 /// The minimum architected relative accuracy is 2^-12. We need one
13891 /// Newton-Raphson step to have a good float result (24 bits of precision).
13892 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13893 DAGCombinerInfo &DCI,
13894 unsigned &RefinementSteps,
13895 bool &UseOneConstNR) const {
13896 EVT VT = Op.getValueType();
13897 const char *RecipOp;
13899 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13900 // TODO: Add support for AVX512 (v16f32).
13901 // It is likely not profitable to do this for f64 because a double-precision
13902 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13903 // instructions: convert to single, rsqrtss, convert back to double, refine
13904 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13905 // along with FMA, this could be a throughput win.
13906 if (VT == MVT::f32 && Subtarget->hasSSE1())
13908 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13909 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13910 RecipOp = "vec-sqrtf";
13914 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13915 if (!Recips.isEnabled(RecipOp))
13918 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13919 UseOneConstNR = false;
13920 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13923 /// The minimum architected relative accuracy is 2^-12. We need one
13924 /// Newton-Raphson step to have a good float result (24 bits of precision).
13925 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13926 DAGCombinerInfo &DCI,
13927 unsigned &RefinementSteps) const {
13928 EVT VT = Op.getValueType();
13929 const char *RecipOp;
13931 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13932 // TODO: Add support for AVX512 (v16f32).
13933 // It is likely not profitable to do this for f64 because a double-precision
13934 // reciprocal estimate with refinement on x86 prior to FMA requires
13935 // 15 instructions: convert to single, rcpss, convert back to double, refine
13936 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13937 // along with FMA, this could be a throughput win.
13938 if (VT == MVT::f32 && Subtarget->hasSSE1())
13940 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13941 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13942 RecipOp = "vec-divf";
13946 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13947 if (!Recips.isEnabled(RecipOp))
13950 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13951 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13954 /// If we have at least two divisions that use the same divisor, convert to
13955 /// multplication by a reciprocal. This may need to be adjusted for a given
13956 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13957 /// This is because we still need one division to calculate the reciprocal and
13958 /// then we need two multiplies by that reciprocal as replacements for the
13959 /// original divisions.
13960 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13964 static bool isAllOnes(SDValue V) {
13965 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13966 return C && C->isAllOnesValue();
13969 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13970 /// if it's possible.
13971 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13972 SDLoc dl, SelectionDAG &DAG) const {
13973 SDValue Op0 = And.getOperand(0);
13974 SDValue Op1 = And.getOperand(1);
13975 if (Op0.getOpcode() == ISD::TRUNCATE)
13976 Op0 = Op0.getOperand(0);
13977 if (Op1.getOpcode() == ISD::TRUNCATE)
13978 Op1 = Op1.getOperand(0);
13981 if (Op1.getOpcode() == ISD::SHL)
13982 std::swap(Op0, Op1);
13983 if (Op0.getOpcode() == ISD::SHL) {
13984 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13985 if (And00C->getZExtValue() == 1) {
13986 // If we looked past a truncate, check that it's only truncating away
13988 unsigned BitWidth = Op0.getValueSizeInBits();
13989 unsigned AndBitWidth = And.getValueSizeInBits();
13990 if (BitWidth > AndBitWidth) {
13992 DAG.computeKnownBits(Op0, Zeros, Ones);
13993 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13997 RHS = Op0.getOperand(1);
13999 } else if (Op1.getOpcode() == ISD::Constant) {
14000 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14001 uint64_t AndRHSVal = AndRHS->getZExtValue();
14002 SDValue AndLHS = Op0;
14004 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14005 LHS = AndLHS.getOperand(0);
14006 RHS = AndLHS.getOperand(1);
14009 // Use BT if the immediate can't be encoded in a TEST instruction.
14010 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14012 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14016 if (LHS.getNode()) {
14017 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14018 // instruction. Since the shift amount is in-range-or-undefined, we know
14019 // that doing a bittest on the i32 value is ok. We extend to i32 because
14020 // the encoding for the i16 version is larger than the i32 version.
14021 // Also promote i16 to i32 for performance / code size reason.
14022 if (LHS.getValueType() == MVT::i8 ||
14023 LHS.getValueType() == MVT::i16)
14024 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14026 // If the operand types disagree, extend the shift amount to match. Since
14027 // BT ignores high bits (like shifts) we can use anyextend.
14028 if (LHS.getValueType() != RHS.getValueType())
14029 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14031 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14032 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14033 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14034 DAG.getConstant(Cond, dl, MVT::i8), BT);
14040 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14042 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14047 // SSE Condition code mapping:
14056 switch (SetCCOpcode) {
14057 default: llvm_unreachable("Unexpected SETCC condition");
14059 case ISD::SETEQ: SSECC = 0; break;
14061 case ISD::SETGT: Swap = true; // Fallthrough
14063 case ISD::SETOLT: SSECC = 1; break;
14065 case ISD::SETGE: Swap = true; // Fallthrough
14067 case ISD::SETOLE: SSECC = 2; break;
14068 case ISD::SETUO: SSECC = 3; break;
14070 case ISD::SETNE: SSECC = 4; break;
14071 case ISD::SETULE: Swap = true; // Fallthrough
14072 case ISD::SETUGE: SSECC = 5; break;
14073 case ISD::SETULT: Swap = true; // Fallthrough
14074 case ISD::SETUGT: SSECC = 6; break;
14075 case ISD::SETO: SSECC = 7; break;
14077 case ISD::SETONE: SSECC = 8; break;
14080 std::swap(Op0, Op1);
14085 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14086 // ones, and then concatenate the result back.
14087 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14088 MVT VT = Op.getSimpleValueType();
14090 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14091 "Unsupported value type for operation");
14093 unsigned NumElems = VT.getVectorNumElements();
14095 SDValue CC = Op.getOperand(2);
14097 // Extract the LHS vectors
14098 SDValue LHS = Op.getOperand(0);
14099 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14100 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14102 // Extract the RHS vectors
14103 SDValue RHS = Op.getOperand(1);
14104 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14105 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14107 // Issue the operation on the smaller types and concatenate the result back
14108 MVT EltVT = VT.getVectorElementType();
14109 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14110 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14111 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14112 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14115 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14116 SDValue Op0 = Op.getOperand(0);
14117 SDValue Op1 = Op.getOperand(1);
14118 SDValue CC = Op.getOperand(2);
14119 MVT VT = Op.getSimpleValueType();
14122 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14123 "Unexpected type for boolean compare operation");
14124 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14125 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14126 DAG.getConstant(-1, dl, VT));
14127 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14128 DAG.getConstant(-1, dl, VT));
14129 switch (SetCCOpcode) {
14130 default: llvm_unreachable("Unexpected SETCC condition");
14132 // (x == y) -> ~(x ^ y)
14133 return DAG.getNode(ISD::XOR, dl, VT,
14134 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14135 DAG.getConstant(-1, dl, VT));
14137 // (x != y) -> (x ^ y)
14138 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14141 // (x > y) -> (x & ~y)
14142 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14145 // (x < y) -> (~x & y)
14146 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14149 // (x <= y) -> (~x | y)
14150 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14153 // (x >=y) -> (x | ~y)
14154 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14158 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14159 const X86Subtarget *Subtarget) {
14160 SDValue Op0 = Op.getOperand(0);
14161 SDValue Op1 = Op.getOperand(1);
14162 SDValue CC = Op.getOperand(2);
14163 MVT VT = Op.getSimpleValueType();
14166 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14167 Op.getValueType().getScalarType() == MVT::i1 &&
14168 "Cannot set masked compare for this operation");
14170 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14172 bool Unsigned = false;
14175 switch (SetCCOpcode) {
14176 default: llvm_unreachable("Unexpected SETCC condition");
14177 case ISD::SETNE: SSECC = 4; break;
14178 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14179 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14180 case ISD::SETLT: Swap = true; //fall-through
14181 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14182 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14183 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14184 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14185 case ISD::SETULE: Unsigned = true; //fall-through
14186 case ISD::SETLE: SSECC = 2; break;
14190 std::swap(Op0, Op1);
14192 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14193 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14194 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14195 DAG.getConstant(SSECC, dl, MVT::i8));
14198 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14199 /// operand \p Op1. If non-trivial (for example because it's not constant)
14200 /// return an empty value.
14201 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14203 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14207 MVT VT = Op1.getSimpleValueType();
14208 MVT EVT = VT.getVectorElementType();
14209 unsigned n = VT.getVectorNumElements();
14210 SmallVector<SDValue, 8> ULTOp1;
14212 for (unsigned i = 0; i < n; ++i) {
14213 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14214 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14217 // Avoid underflow.
14218 APInt Val = Elt->getAPIntValue();
14222 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14225 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14228 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14229 SelectionDAG &DAG) {
14230 SDValue Op0 = Op.getOperand(0);
14231 SDValue Op1 = Op.getOperand(1);
14232 SDValue CC = Op.getOperand(2);
14233 MVT VT = Op.getSimpleValueType();
14234 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14235 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14240 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14241 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14244 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14245 unsigned Opc = X86ISD::CMPP;
14246 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14247 assert(VT.getVectorNumElements() <= 16);
14248 Opc = X86ISD::CMPM;
14250 // In the two special cases we can't handle, emit two comparisons.
14253 unsigned CombineOpc;
14254 if (SetCCOpcode == ISD::SETUEQ) {
14255 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14257 assert(SetCCOpcode == ISD::SETONE);
14258 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14261 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14262 DAG.getConstant(CC0, dl, MVT::i8));
14263 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14264 DAG.getConstant(CC1, dl, MVT::i8));
14265 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14267 // Handle all other FP comparisons here.
14268 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14269 DAG.getConstant(SSECC, dl, MVT::i8));
14272 MVT VTOp0 = Op0.getSimpleValueType();
14273 assert(VTOp0 == Op1.getSimpleValueType() &&
14274 "Expected operands with same type!");
14275 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14276 "Invalid number of packed elements for source and destination!");
14278 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14279 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14280 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14281 // legalizer firstly checks if the first operand in input to the setcc has
14282 // a legal type. If so, then it promotes the return type to that same type.
14283 // Otherwise, the return type is promoted to the 'next legal type' which,
14284 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14286 // We reach this code only if the following two conditions are met:
14287 // 1. Both return type and operand type have been promoted to wider types
14288 // by the type legalizer.
14289 // 2. The original operand type has been promoted to a 256-bit vector.
14291 // Note that condition 2. only applies for AVX targets.
14292 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14293 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14296 // The non-AVX512 code below works under the assumption that source and
14297 // destination types are the same.
14298 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14299 "Value types for source and destination must be the same!");
14301 // Break 256-bit integer vector compare into smaller ones.
14302 if (VT.is256BitVector() && !Subtarget->hasInt256())
14303 return Lower256IntVSETCC(Op, DAG);
14305 EVT OpVT = Op1.getValueType();
14306 if (OpVT.getVectorElementType() == MVT::i1)
14307 return LowerBoolVSETCC_AVX512(Op, DAG);
14309 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14310 if (Subtarget->hasAVX512()) {
14311 if (Op1.getValueType().is512BitVector() ||
14312 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14313 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14314 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14316 // In AVX-512 architecture setcc returns mask with i1 elements,
14317 // But there is no compare instruction for i8 and i16 elements in KNL.
14318 // We are not talking about 512-bit operands in this case, these
14319 // types are illegal.
14321 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14322 OpVT.getVectorElementType().getSizeInBits() >= 8))
14323 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14324 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14327 // Lower using XOP integer comparisons.
14328 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14329 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14330 // Translate compare code to XOP PCOM compare mode.
14331 unsigned CmpMode = 0;
14332 switch (SetCCOpcode) {
14333 default: llvm_unreachable("Unexpected SETCC condition");
14335 case ISD::SETLT: CmpMode = 0x00; break;
14337 case ISD::SETLE: CmpMode = 0x01; break;
14339 case ISD::SETGT: CmpMode = 0x02; break;
14341 case ISD::SETGE: CmpMode = 0x03; break;
14342 case ISD::SETEQ: CmpMode = 0x04; break;
14343 case ISD::SETNE: CmpMode = 0x05; break;
14346 // Are we comparing unsigned or signed integers?
14347 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14348 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14350 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14351 DAG.getConstant(CmpMode, dl, MVT::i8));
14354 // We are handling one of the integer comparisons here. Since SSE only has
14355 // GT and EQ comparisons for integer, swapping operands and multiple
14356 // operations may be required for some comparisons.
14358 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14359 bool Subus = false;
14361 switch (SetCCOpcode) {
14362 default: llvm_unreachable("Unexpected SETCC condition");
14363 case ISD::SETNE: Invert = true;
14364 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14365 case ISD::SETLT: Swap = true;
14366 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14367 case ISD::SETGE: Swap = true;
14368 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14369 Invert = true; break;
14370 case ISD::SETULT: Swap = true;
14371 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14372 FlipSigns = true; break;
14373 case ISD::SETUGE: Swap = true;
14374 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14375 FlipSigns = true; Invert = true; break;
14378 // Special case: Use min/max operations for SETULE/SETUGE
14379 MVT VET = VT.getVectorElementType();
14381 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14382 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14385 switch (SetCCOpcode) {
14387 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14388 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14391 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14394 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14395 if (!MinMax && hasSubus) {
14396 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14398 // t = psubus Op0, Op1
14399 // pcmpeq t, <0..0>
14400 switch (SetCCOpcode) {
14402 case ISD::SETULT: {
14403 // If the comparison is against a constant we can turn this into a
14404 // setule. With psubus, setule does not require a swap. This is
14405 // beneficial because the constant in the register is no longer
14406 // destructed as the destination so it can be hoisted out of a loop.
14407 // Only do this pre-AVX since vpcmp* is no longer destructive.
14408 if (Subtarget->hasAVX())
14410 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14411 if (ULEOp1.getNode()) {
14413 Subus = true; Invert = false; Swap = false;
14417 // Psubus is better than flip-sign because it requires no inversion.
14418 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14419 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14423 Opc = X86ISD::SUBUS;
14429 std::swap(Op0, Op1);
14431 // Check that the operation in question is available (most are plain SSE2,
14432 // but PCMPGTQ and PCMPEQQ have different requirements).
14433 if (VT == MVT::v2i64) {
14434 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14435 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14437 // First cast everything to the right type.
14438 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14439 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14441 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14442 // bits of the inputs before performing those operations. The lower
14443 // compare is always unsigned.
14446 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14448 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14449 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14450 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14451 Sign, Zero, Sign, Zero);
14453 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14454 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14456 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14457 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14458 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14460 // Create masks for only the low parts/high parts of the 64 bit integers.
14461 static const int MaskHi[] = { 1, 1, 3, 3 };
14462 static const int MaskLo[] = { 0, 0, 2, 2 };
14463 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14464 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14465 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14467 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14468 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14471 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14473 return DAG.getBitcast(VT, Result);
14476 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14477 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14478 // pcmpeqd + pshufd + pand.
14479 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14481 // First cast everything to the right type.
14482 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14483 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14486 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14488 // Make sure the lower and upper halves are both all-ones.
14489 static const int Mask[] = { 1, 0, 3, 2 };
14490 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14491 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14494 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14496 return DAG.getBitcast(VT, Result);
14500 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14501 // bits of the inputs before performing those operations.
14503 EVT EltVT = VT.getVectorElementType();
14504 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14506 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14507 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14510 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14512 // If the logical-not of the result is required, perform that now.
14514 Result = DAG.getNOT(dl, Result, VT);
14517 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14520 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14521 getZeroVector(VT, Subtarget, DAG, dl));
14526 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14528 MVT VT = Op.getSimpleValueType();
14530 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14532 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14533 && "SetCC type must be 8-bit or 1-bit integer");
14534 SDValue Op0 = Op.getOperand(0);
14535 SDValue Op1 = Op.getOperand(1);
14537 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14539 // Optimize to BT if possible.
14540 // Lower (X & (1 << N)) == 0 to BT(X, N).
14541 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14542 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14543 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14544 Op1.getOpcode() == ISD::Constant &&
14545 cast<ConstantSDNode>(Op1)->isNullValue() &&
14546 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14547 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14548 if (NewSetCC.getNode()) {
14550 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14555 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14557 if (Op1.getOpcode() == ISD::Constant &&
14558 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14559 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14560 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14562 // If the input is a setcc, then reuse the input setcc or use a new one with
14563 // the inverted condition.
14564 if (Op0.getOpcode() == X86ISD::SETCC) {
14565 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14566 bool Invert = (CC == ISD::SETNE) ^
14567 cast<ConstantSDNode>(Op1)->isNullValue();
14571 CCode = X86::GetOppositeBranchCondition(CCode);
14572 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14573 DAG.getConstant(CCode, dl, MVT::i8),
14574 Op0.getOperand(1));
14576 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14580 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14581 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14582 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14584 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14585 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14588 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14589 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14590 if (X86CC == X86::COND_INVALID)
14593 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14594 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14595 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14596 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14598 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14602 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14603 static bool isX86LogicalCmp(SDValue Op) {
14604 unsigned Opc = Op.getNode()->getOpcode();
14605 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14606 Opc == X86ISD::SAHF)
14608 if (Op.getResNo() == 1 &&
14609 (Opc == X86ISD::ADD ||
14610 Opc == X86ISD::SUB ||
14611 Opc == X86ISD::ADC ||
14612 Opc == X86ISD::SBB ||
14613 Opc == X86ISD::SMUL ||
14614 Opc == X86ISD::UMUL ||
14615 Opc == X86ISD::INC ||
14616 Opc == X86ISD::DEC ||
14617 Opc == X86ISD::OR ||
14618 Opc == X86ISD::XOR ||
14619 Opc == X86ISD::AND))
14622 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14628 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14629 if (V.getOpcode() != ISD::TRUNCATE)
14632 SDValue VOp0 = V.getOperand(0);
14633 unsigned InBits = VOp0.getValueSizeInBits();
14634 unsigned Bits = V.getValueSizeInBits();
14635 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14638 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14639 bool addTest = true;
14640 SDValue Cond = Op.getOperand(0);
14641 SDValue Op1 = Op.getOperand(1);
14642 SDValue Op2 = Op.getOperand(2);
14644 EVT VT = Op1.getValueType();
14647 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14648 // are available or VBLENDV if AVX is available.
14649 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14650 if (Cond.getOpcode() == ISD::SETCC &&
14651 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14652 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14653 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14654 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14655 int SSECC = translateX86FSETCC(
14656 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14659 if (Subtarget->hasAVX512()) {
14660 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14661 DAG.getConstant(SSECC, DL, MVT::i8));
14662 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14665 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14666 DAG.getConstant(SSECC, DL, MVT::i8));
14668 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14669 // of 3 logic instructions for size savings and potentially speed.
14670 // Unfortunately, there is no scalar form of VBLENDV.
14672 // If either operand is a constant, don't try this. We can expect to
14673 // optimize away at least one of the logic instructions later in that
14674 // case, so that sequence would be faster than a variable blend.
14676 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14677 // uses XMM0 as the selection register. That may need just as many
14678 // instructions as the AND/ANDN/OR sequence due to register moves, so
14681 if (Subtarget->hasAVX() &&
14682 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14684 // Convert to vectors, do a VSELECT, and convert back to scalar.
14685 // All of the conversions should be optimized away.
14687 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14688 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14689 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14690 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14692 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14693 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14695 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14697 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14698 VSel, DAG.getIntPtrConstant(0, DL));
14700 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14701 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14702 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14706 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14708 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14709 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14710 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14711 Op1Scalar = Op1.getOperand(0);
14713 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14714 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14715 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14716 Op2Scalar = Op2.getOperand(0);
14717 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14718 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14719 Op1Scalar.getValueType(),
14720 Cond, Op1Scalar, Op2Scalar);
14721 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14722 return DAG.getBitcast(VT, newSelect);
14723 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14724 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14725 DAG.getIntPtrConstant(0, DL));
14729 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14730 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14731 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14732 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14733 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14734 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14735 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14737 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14740 if (Cond.getOpcode() == ISD::SETCC) {
14741 SDValue NewCond = LowerSETCC(Cond, DAG);
14742 if (NewCond.getNode())
14746 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14747 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14748 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14749 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14750 if (Cond.getOpcode() == X86ISD::SETCC &&
14751 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14752 isZero(Cond.getOperand(1).getOperand(1))) {
14753 SDValue Cmp = Cond.getOperand(1);
14755 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14757 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14758 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14759 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14761 SDValue CmpOp0 = Cmp.getOperand(0);
14762 // Apply further optimizations for special cases
14763 // (select (x != 0), -1, 0) -> neg & sbb
14764 // (select (x == 0), 0, -1) -> neg & sbb
14765 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14766 if (YC->isNullValue() &&
14767 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14768 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14769 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14770 DAG.getConstant(0, DL,
14771 CmpOp0.getValueType()),
14773 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14774 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14775 SDValue(Neg.getNode(), 1));
14779 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14780 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14781 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14783 SDValue Res = // Res = 0 or -1.
14784 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14785 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14787 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14788 Res = DAG.getNOT(DL, Res, Res.getValueType());
14790 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14791 if (!N2C || !N2C->isNullValue())
14792 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14797 // Look past (and (setcc_carry (cmp ...)), 1).
14798 if (Cond.getOpcode() == ISD::AND &&
14799 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14800 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14801 if (C && C->getAPIntValue() == 1)
14802 Cond = Cond.getOperand(0);
14805 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14806 // setting operand in place of the X86ISD::SETCC.
14807 unsigned CondOpcode = Cond.getOpcode();
14808 if (CondOpcode == X86ISD::SETCC ||
14809 CondOpcode == X86ISD::SETCC_CARRY) {
14810 CC = Cond.getOperand(0);
14812 SDValue Cmp = Cond.getOperand(1);
14813 unsigned Opc = Cmp.getOpcode();
14814 MVT VT = Op.getSimpleValueType();
14816 bool IllegalFPCMov = false;
14817 if (VT.isFloatingPoint() && !VT.isVector() &&
14818 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14819 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14821 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14822 Opc == X86ISD::BT) { // FIXME
14826 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14827 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14828 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14829 Cond.getOperand(0).getValueType() != MVT::i8)) {
14830 SDValue LHS = Cond.getOperand(0);
14831 SDValue RHS = Cond.getOperand(1);
14832 unsigned X86Opcode;
14835 switch (CondOpcode) {
14836 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14837 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14838 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14839 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14840 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14841 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14842 default: llvm_unreachable("unexpected overflowing operator");
14844 if (CondOpcode == ISD::UMULO)
14845 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14848 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14850 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14852 if (CondOpcode == ISD::UMULO)
14853 Cond = X86Op.getValue(2);
14855 Cond = X86Op.getValue(1);
14857 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14862 // Look past the truncate if the high bits are known zero.
14863 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14864 Cond = Cond.getOperand(0);
14866 // We know the result of AND is compared against zero. Try to match
14868 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14869 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14870 if (NewSetCC.getNode()) {
14871 CC = NewSetCC.getOperand(0);
14872 Cond = NewSetCC.getOperand(1);
14879 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14880 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14883 // a < b ? -1 : 0 -> RES = ~setcc_carry
14884 // a < b ? 0 : -1 -> RES = setcc_carry
14885 // a >= b ? -1 : 0 -> RES = setcc_carry
14886 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14887 if (Cond.getOpcode() == X86ISD::SUB) {
14888 Cond = ConvertCmpIfNecessary(Cond, DAG);
14889 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14891 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14892 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14893 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14894 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14896 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14897 return DAG.getNOT(DL, Res, Res.getValueType());
14902 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14903 // widen the cmov and push the truncate through. This avoids introducing a new
14904 // branch during isel and doesn't add any extensions.
14905 if (Op.getValueType() == MVT::i8 &&
14906 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14907 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14908 if (T1.getValueType() == T2.getValueType() &&
14909 // Blacklist CopyFromReg to avoid partial register stalls.
14910 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14911 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14912 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14913 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14917 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14918 // condition is true.
14919 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14920 SDValue Ops[] = { Op2, Op1, CC, Cond };
14921 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14924 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14925 const X86Subtarget *Subtarget,
14926 SelectionDAG &DAG) {
14927 MVT VT = Op->getSimpleValueType(0);
14928 SDValue In = Op->getOperand(0);
14929 MVT InVT = In.getSimpleValueType();
14930 MVT VTElt = VT.getVectorElementType();
14931 MVT InVTElt = InVT.getVectorElementType();
14935 if ((InVTElt == MVT::i1) &&
14936 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14937 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14939 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14940 VTElt.getSizeInBits() <= 16)) ||
14942 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14943 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14945 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14946 VTElt.getSizeInBits() >= 32))))
14947 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14949 unsigned int NumElts = VT.getVectorNumElements();
14951 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14954 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14955 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14956 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14957 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14960 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14961 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14963 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14966 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14968 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14969 if (VT.is512BitVector())
14971 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14974 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14975 const X86Subtarget *Subtarget,
14976 SelectionDAG &DAG) {
14977 SDValue In = Op->getOperand(0);
14978 MVT VT = Op->getSimpleValueType(0);
14979 MVT InVT = In.getSimpleValueType();
14980 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14982 MVT InSVT = InVT.getScalarType();
14983 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14985 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14987 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14992 // SSE41 targets can use the pmovsx* instructions directly.
14993 if (Subtarget->hasSSE41())
14994 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14996 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15000 // As SRAI is only available on i16/i32 types, we expand only up to i32
15001 // and handle i64 separately.
15002 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
15003 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15004 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15005 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15006 Curr = DAG.getBitcast(CurrVT, Curr);
15009 SDValue SignExt = Curr;
15010 if (CurrVT != InVT) {
15011 unsigned SignExtShift =
15012 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
15013 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15014 DAG.getConstant(SignExtShift, dl, MVT::i8));
15020 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15021 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15022 DAG.getConstant(31, dl, MVT::i8));
15023 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15024 return DAG.getBitcast(VT, Ext);
15030 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15031 SelectionDAG &DAG) {
15032 MVT VT = Op->getSimpleValueType(0);
15033 SDValue In = Op->getOperand(0);
15034 MVT InVT = In.getSimpleValueType();
15037 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15038 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15040 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15041 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15042 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15045 if (Subtarget->hasInt256())
15046 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15048 // Optimize vectors in AVX mode
15049 // Sign extend v8i16 to v8i32 and
15052 // Divide input vector into two parts
15053 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15054 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15055 // concat the vectors to original VT
15057 unsigned NumElems = InVT.getVectorNumElements();
15058 SDValue Undef = DAG.getUNDEF(InVT);
15060 SmallVector<int,8> ShufMask1(NumElems, -1);
15061 for (unsigned i = 0; i != NumElems/2; ++i)
15064 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15066 SmallVector<int,8> ShufMask2(NumElems, -1);
15067 for (unsigned i = 0; i != NumElems/2; ++i)
15068 ShufMask2[i] = i + NumElems/2;
15070 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15072 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15073 VT.getVectorNumElements()/2);
15075 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15076 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15078 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15081 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15082 // may emit an illegal shuffle but the expansion is still better than scalar
15083 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15084 // we'll emit a shuffle and a arithmetic shift.
15085 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15086 // TODO: It is possible to support ZExt by zeroing the undef values during
15087 // the shuffle phase or after the shuffle.
15088 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15089 SelectionDAG &DAG) {
15090 MVT RegVT = Op.getSimpleValueType();
15091 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15092 assert(RegVT.isInteger() &&
15093 "We only custom lower integer vector sext loads.");
15095 // Nothing useful we can do without SSE2 shuffles.
15096 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15098 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15100 EVT MemVT = Ld->getMemoryVT();
15101 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15102 unsigned RegSz = RegVT.getSizeInBits();
15104 ISD::LoadExtType Ext = Ld->getExtensionType();
15106 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15107 && "Only anyext and sext are currently implemented.");
15108 assert(MemVT != RegVT && "Cannot extend to the same type");
15109 assert(MemVT.isVector() && "Must load a vector from memory");
15111 unsigned NumElems = RegVT.getVectorNumElements();
15112 unsigned MemSz = MemVT.getSizeInBits();
15113 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15115 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15116 // The only way in which we have a legal 256-bit vector result but not the
15117 // integer 256-bit operations needed to directly lower a sextload is if we
15118 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15119 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15120 // correctly legalized. We do this late to allow the canonical form of
15121 // sextload to persist throughout the rest of the DAG combiner -- it wants
15122 // to fold together any extensions it can, and so will fuse a sign_extend
15123 // of an sextload into a sextload targeting a wider value.
15125 if (MemSz == 128) {
15126 // Just switch this to a normal load.
15127 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15128 "it must be a legal 128-bit vector "
15130 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15131 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15132 Ld->isInvariant(), Ld->getAlignment());
15134 assert(MemSz < 128 &&
15135 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15136 // Do an sext load to a 128-bit vector type. We want to use the same
15137 // number of elements, but elements half as wide. This will end up being
15138 // recursively lowered by this routine, but will succeed as we definitely
15139 // have all the necessary features if we're using AVX1.
15141 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15142 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15144 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15145 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15146 Ld->isNonTemporal(), Ld->isInvariant(),
15147 Ld->getAlignment());
15150 // Replace chain users with the new chain.
15151 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15152 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15154 // Finally, do a normal sign-extend to the desired register.
15155 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15158 // All sizes must be a power of two.
15159 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15160 "Non-power-of-two elements are not custom lowered!");
15162 // Attempt to load the original value using scalar loads.
15163 // Find the largest scalar type that divides the total loaded size.
15164 MVT SclrLoadTy = MVT::i8;
15165 for (MVT Tp : MVT::integer_valuetypes()) {
15166 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15171 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15172 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15174 SclrLoadTy = MVT::f64;
15176 // Calculate the number of scalar loads that we need to perform
15177 // in order to load our vector from memory.
15178 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15180 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15181 "Can only lower sext loads with a single scalar load!");
15183 unsigned loadRegZize = RegSz;
15184 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15187 // Represent our vector as a sequence of elements which are the
15188 // largest scalar that we can load.
15189 EVT LoadUnitVecVT = EVT::getVectorVT(
15190 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15192 // Represent the data using the same element type that is stored in
15193 // memory. In practice, we ''widen'' MemVT.
15195 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15196 loadRegZize / MemVT.getScalarType().getSizeInBits());
15198 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15199 "Invalid vector type");
15201 // We can't shuffle using an illegal type.
15202 assert(TLI.isTypeLegal(WideVecVT) &&
15203 "We only lower types that form legal widened vector types");
15205 SmallVector<SDValue, 8> Chains;
15206 SDValue Ptr = Ld->getBasePtr();
15207 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15208 TLI.getPointerTy(DAG.getDataLayout()));
15209 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15211 for (unsigned i = 0; i < NumLoads; ++i) {
15212 // Perform a single load.
15213 SDValue ScalarLoad =
15214 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15215 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15216 Ld->getAlignment());
15217 Chains.push_back(ScalarLoad.getValue(1));
15218 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15219 // another round of DAGCombining.
15221 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15223 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15224 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15226 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15229 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15231 // Bitcast the loaded value to a vector of the original element type, in
15232 // the size of the target vector type.
15233 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15234 unsigned SizeRatio = RegSz / MemSz;
15236 if (Ext == ISD::SEXTLOAD) {
15237 // If we have SSE4.1, we can directly emit a VSEXT node.
15238 if (Subtarget->hasSSE41()) {
15239 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15240 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15244 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15246 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15247 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15249 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15250 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15254 // Redistribute the loaded elements into the different locations.
15255 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15256 for (unsigned i = 0; i != NumElems; ++i)
15257 ShuffleVec[i * SizeRatio] = i;
15259 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15260 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15262 // Bitcast to the requested type.
15263 Shuff = DAG.getBitcast(RegVT, Shuff);
15264 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15268 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15269 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15270 // from the AND / OR.
15271 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15272 Opc = Op.getOpcode();
15273 if (Opc != ISD::OR && Opc != ISD::AND)
15275 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15276 Op.getOperand(0).hasOneUse() &&
15277 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15278 Op.getOperand(1).hasOneUse());
15281 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15282 // 1 and that the SETCC node has a single use.
15283 static bool isXor1OfSetCC(SDValue Op) {
15284 if (Op.getOpcode() != ISD::XOR)
15286 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15287 if (N1C && N1C->getAPIntValue() == 1) {
15288 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15289 Op.getOperand(0).hasOneUse();
15294 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15295 bool addTest = true;
15296 SDValue Chain = Op.getOperand(0);
15297 SDValue Cond = Op.getOperand(1);
15298 SDValue Dest = Op.getOperand(2);
15301 bool Inverted = false;
15303 if (Cond.getOpcode() == ISD::SETCC) {
15304 // Check for setcc([su]{add,sub,mul}o == 0).
15305 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15306 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15307 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15308 Cond.getOperand(0).getResNo() == 1 &&
15309 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15310 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15311 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15312 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15313 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15314 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15316 Cond = Cond.getOperand(0);
15318 SDValue NewCond = LowerSETCC(Cond, DAG);
15319 if (NewCond.getNode())
15324 // FIXME: LowerXALUO doesn't handle these!!
15325 else if (Cond.getOpcode() == X86ISD::ADD ||
15326 Cond.getOpcode() == X86ISD::SUB ||
15327 Cond.getOpcode() == X86ISD::SMUL ||
15328 Cond.getOpcode() == X86ISD::UMUL)
15329 Cond = LowerXALUO(Cond, DAG);
15332 // Look pass (and (setcc_carry (cmp ...)), 1).
15333 if (Cond.getOpcode() == ISD::AND &&
15334 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15335 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15336 if (C && C->getAPIntValue() == 1)
15337 Cond = Cond.getOperand(0);
15340 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15341 // setting operand in place of the X86ISD::SETCC.
15342 unsigned CondOpcode = Cond.getOpcode();
15343 if (CondOpcode == X86ISD::SETCC ||
15344 CondOpcode == X86ISD::SETCC_CARRY) {
15345 CC = Cond.getOperand(0);
15347 SDValue Cmp = Cond.getOperand(1);
15348 unsigned Opc = Cmp.getOpcode();
15349 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15350 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15354 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15358 // These can only come from an arithmetic instruction with overflow,
15359 // e.g. SADDO, UADDO.
15360 Cond = Cond.getNode()->getOperand(1);
15366 CondOpcode = Cond.getOpcode();
15367 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15368 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15369 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15370 Cond.getOperand(0).getValueType() != MVT::i8)) {
15371 SDValue LHS = Cond.getOperand(0);
15372 SDValue RHS = Cond.getOperand(1);
15373 unsigned X86Opcode;
15376 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15377 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15379 switch (CondOpcode) {
15380 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15382 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15384 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15387 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15388 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15392 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15395 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15396 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15397 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15398 default: llvm_unreachable("unexpected overflowing operator");
15401 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15402 if (CondOpcode == ISD::UMULO)
15403 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15406 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15408 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15410 if (CondOpcode == ISD::UMULO)
15411 Cond = X86Op.getValue(2);
15413 Cond = X86Op.getValue(1);
15415 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15419 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15420 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15421 if (CondOpc == ISD::OR) {
15422 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15423 // two branches instead of an explicit OR instruction with a
15425 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15426 isX86LogicalCmp(Cmp)) {
15427 CC = Cond.getOperand(0).getOperand(0);
15428 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15429 Chain, Dest, CC, Cmp);
15430 CC = Cond.getOperand(1).getOperand(0);
15434 } else { // ISD::AND
15435 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15436 // two branches instead of an explicit AND instruction with a
15437 // separate test. However, we only do this if this block doesn't
15438 // have a fall-through edge, because this requires an explicit
15439 // jmp when the condition is false.
15440 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15441 isX86LogicalCmp(Cmp) &&
15442 Op.getNode()->hasOneUse()) {
15443 X86::CondCode CCode =
15444 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15445 CCode = X86::GetOppositeBranchCondition(CCode);
15446 CC = DAG.getConstant(CCode, dl, MVT::i8);
15447 SDNode *User = *Op.getNode()->use_begin();
15448 // Look for an unconditional branch following this conditional branch.
15449 // We need this because we need to reverse the successors in order
15450 // to implement FCMP_OEQ.
15451 if (User->getOpcode() == ISD::BR) {
15452 SDValue FalseBB = User->getOperand(1);
15454 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15455 assert(NewBR == User);
15459 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15460 Chain, Dest, CC, Cmp);
15461 X86::CondCode CCode =
15462 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15463 CCode = X86::GetOppositeBranchCondition(CCode);
15464 CC = DAG.getConstant(CCode, dl, MVT::i8);
15470 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15471 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15472 // It should be transformed during dag combiner except when the condition
15473 // is set by a arithmetics with overflow node.
15474 X86::CondCode CCode =
15475 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15476 CCode = X86::GetOppositeBranchCondition(CCode);
15477 CC = DAG.getConstant(CCode, dl, MVT::i8);
15478 Cond = Cond.getOperand(0).getOperand(1);
15480 } else if (Cond.getOpcode() == ISD::SETCC &&
15481 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15482 // For FCMP_OEQ, we can emit
15483 // two branches instead of an explicit AND instruction with a
15484 // separate test. However, we only do this if this block doesn't
15485 // have a fall-through edge, because this requires an explicit
15486 // jmp when the condition is false.
15487 if (Op.getNode()->hasOneUse()) {
15488 SDNode *User = *Op.getNode()->use_begin();
15489 // Look for an unconditional branch following this conditional branch.
15490 // We need this because we need to reverse the successors in order
15491 // to implement FCMP_OEQ.
15492 if (User->getOpcode() == ISD::BR) {
15493 SDValue FalseBB = User->getOperand(1);
15495 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15496 assert(NewBR == User);
15500 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15501 Cond.getOperand(0), Cond.getOperand(1));
15502 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15503 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15504 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15505 Chain, Dest, CC, Cmp);
15506 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15511 } else if (Cond.getOpcode() == ISD::SETCC &&
15512 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15513 // For FCMP_UNE, we can emit
15514 // two branches instead of an explicit AND instruction with a
15515 // separate test. However, we only do this if this block doesn't
15516 // have a fall-through edge, because this requires an explicit
15517 // jmp when the condition is false.
15518 if (Op.getNode()->hasOneUse()) {
15519 SDNode *User = *Op.getNode()->use_begin();
15520 // Look for an unconditional branch following this conditional branch.
15521 // We need this because we need to reverse the successors in order
15522 // to implement FCMP_UNE.
15523 if (User->getOpcode() == ISD::BR) {
15524 SDValue FalseBB = User->getOperand(1);
15526 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15527 assert(NewBR == User);
15530 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15531 Cond.getOperand(0), Cond.getOperand(1));
15532 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15533 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15534 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15535 Chain, Dest, CC, Cmp);
15536 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15546 // Look pass the truncate if the high bits are known zero.
15547 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15548 Cond = Cond.getOperand(0);
15550 // We know the result of AND is compared against zero. Try to match
15552 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15553 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15554 if (NewSetCC.getNode()) {
15555 CC = NewSetCC.getOperand(0);
15556 Cond = NewSetCC.getOperand(1);
15563 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15564 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15565 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15567 Cond = ConvertCmpIfNecessary(Cond, DAG);
15568 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15569 Chain, Dest, CC, Cond);
15572 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15573 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15574 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15575 // that the guard pages used by the OS virtual memory manager are allocated in
15576 // correct sequence.
15578 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15579 SelectionDAG &DAG) const {
15580 MachineFunction &MF = DAG.getMachineFunction();
15581 bool SplitStack = MF.shouldSplitStack();
15582 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15588 SDNode* Node = Op.getNode();
15590 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15591 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15592 " not tell us which reg is the stack pointer!");
15593 EVT VT = Node->getValueType(0);
15594 SDValue Tmp1 = SDValue(Node, 0);
15595 SDValue Tmp2 = SDValue(Node, 1);
15596 SDValue Tmp3 = Node->getOperand(2);
15597 SDValue Chain = Tmp1.getOperand(0);
15599 // Chain the dynamic stack allocation so that it doesn't modify the stack
15600 // pointer when other instructions are using the stack.
15601 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15604 SDValue Size = Tmp2.getOperand(1);
15605 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15606 Chain = SP.getValue(1);
15607 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15608 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15609 unsigned StackAlign = TFI.getStackAlignment();
15610 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15611 if (Align > StackAlign)
15612 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15613 DAG.getConstant(-(uint64_t)Align, dl, VT));
15614 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15616 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15617 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15620 SDValue Ops[2] = { Tmp1, Tmp2 };
15621 return DAG.getMergeValues(Ops, dl);
15625 SDValue Chain = Op.getOperand(0);
15626 SDValue Size = Op.getOperand(1);
15627 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15628 EVT VT = Op.getNode()->getValueType(0);
15630 bool Is64Bit = Subtarget->is64Bit();
15631 MVT SPTy = getPointerTy(DAG.getDataLayout());
15634 MachineRegisterInfo &MRI = MF.getRegInfo();
15637 // The 64 bit implementation of segmented stacks needs to clobber both r10
15638 // r11. This makes it impossible to use it along with nested parameters.
15639 const Function *F = MF.getFunction();
15641 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15643 if (I->hasNestAttr())
15644 report_fatal_error("Cannot use segmented stacks with functions that "
15645 "have nested arguments.");
15648 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15649 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15650 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15651 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15652 DAG.getRegister(Vreg, SPTy));
15653 SDValue Ops1[2] = { Value, Chain };
15654 return DAG.getMergeValues(Ops1, dl);
15657 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15659 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15660 Flag = Chain.getValue(1);
15661 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15663 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15665 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15666 unsigned SPReg = RegInfo->getStackRegister();
15667 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15668 Chain = SP.getValue(1);
15671 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15672 DAG.getConstant(-(uint64_t)Align, dl, VT));
15673 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15676 SDValue Ops1[2] = { SP, Chain };
15677 return DAG.getMergeValues(Ops1, dl);
15681 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15682 MachineFunction &MF = DAG.getMachineFunction();
15683 auto PtrVT = getPointerTy(MF.getDataLayout());
15684 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15686 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15689 if (!Subtarget->is64Bit() ||
15690 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15691 // vastart just stores the address of the VarArgsFrameIndex slot into the
15692 // memory location argument.
15693 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15694 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15695 MachinePointerInfo(SV), false, false, 0);
15699 // gp_offset (0 - 6 * 8)
15700 // fp_offset (48 - 48 + 8 * 16)
15701 // overflow_arg_area (point to parameters coming in memory).
15703 SmallVector<SDValue, 8> MemOps;
15704 SDValue FIN = Op.getOperand(1);
15706 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15707 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15709 FIN, MachinePointerInfo(SV), false, false, 0);
15710 MemOps.push_back(Store);
15713 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15714 Store = DAG.getStore(Op.getOperand(0), DL,
15715 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15717 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15718 MemOps.push_back(Store);
15720 // Store ptr to overflow_arg_area
15721 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15722 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15723 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15724 MachinePointerInfo(SV, 8),
15726 MemOps.push_back(Store);
15728 // Store ptr to reg_save_area.
15729 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15730 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15731 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15732 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15733 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15734 MemOps.push_back(Store);
15735 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15738 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15739 assert(Subtarget->is64Bit() &&
15740 "LowerVAARG only handles 64-bit va_arg!");
15741 assert(Op.getNode()->getNumOperands() == 4);
15743 MachineFunction &MF = DAG.getMachineFunction();
15744 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15745 // The Win64 ABI uses char* instead of a structure.
15746 return DAG.expandVAArg(Op.getNode());
15748 SDValue Chain = Op.getOperand(0);
15749 SDValue SrcPtr = Op.getOperand(1);
15750 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15751 unsigned Align = Op.getConstantOperandVal(3);
15754 EVT ArgVT = Op.getNode()->getValueType(0);
15755 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15756 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15759 // Decide which area this value should be read from.
15760 // TODO: Implement the AMD64 ABI in its entirety. This simple
15761 // selection mechanism works only for the basic types.
15762 if (ArgVT == MVT::f80) {
15763 llvm_unreachable("va_arg for f80 not yet implemented");
15764 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15765 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15766 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15767 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15769 llvm_unreachable("Unhandled argument type in LowerVAARG");
15772 if (ArgMode == 2) {
15773 // Sanity Check: Make sure using fp_offset makes sense.
15774 assert(!Subtarget->useSoftFloat() &&
15775 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15776 Subtarget->hasSSE1());
15779 // Insert VAARG_64 node into the DAG
15780 // VAARG_64 returns two values: Variable Argument Address, Chain
15781 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15782 DAG.getConstant(ArgMode, dl, MVT::i8),
15783 DAG.getConstant(Align, dl, MVT::i32)};
15784 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15785 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15786 VTs, InstOps, MVT::i64,
15787 MachinePointerInfo(SV),
15789 /*Volatile=*/false,
15791 /*WriteMem=*/true);
15792 Chain = VAARG.getValue(1);
15794 // Load the next argument and return it
15795 return DAG.getLoad(ArgVT, dl,
15798 MachinePointerInfo(),
15799 false, false, false, 0);
15802 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15803 SelectionDAG &DAG) {
15804 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15805 // where a va_list is still an i8*.
15806 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15807 if (Subtarget->isCallingConvWin64(
15808 DAG.getMachineFunction().getFunction()->getCallingConv()))
15809 // Probably a Win64 va_copy.
15810 return DAG.expandVACopy(Op.getNode());
15812 SDValue Chain = Op.getOperand(0);
15813 SDValue DstPtr = Op.getOperand(1);
15814 SDValue SrcPtr = Op.getOperand(2);
15815 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15816 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15819 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15820 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15822 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15825 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15826 // amount is a constant. Takes immediate version of shift as input.
15827 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15828 SDValue SrcOp, uint64_t ShiftAmt,
15829 SelectionDAG &DAG) {
15830 MVT ElementType = VT.getVectorElementType();
15832 // Fold this packed shift into its first operand if ShiftAmt is 0.
15836 // Check for ShiftAmt >= element width
15837 if (ShiftAmt >= ElementType.getSizeInBits()) {
15838 if (Opc == X86ISD::VSRAI)
15839 ShiftAmt = ElementType.getSizeInBits() - 1;
15841 return DAG.getConstant(0, dl, VT);
15844 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15845 && "Unknown target vector shift-by-constant node");
15847 // Fold this packed vector shift into a build vector if SrcOp is a
15848 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15849 if (VT == SrcOp.getSimpleValueType() &&
15850 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15851 SmallVector<SDValue, 8> Elts;
15852 unsigned NumElts = SrcOp->getNumOperands();
15853 ConstantSDNode *ND;
15856 default: llvm_unreachable(nullptr);
15857 case X86ISD::VSHLI:
15858 for (unsigned i=0; i!=NumElts; ++i) {
15859 SDValue CurrentOp = SrcOp->getOperand(i);
15860 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15861 Elts.push_back(CurrentOp);
15864 ND = cast<ConstantSDNode>(CurrentOp);
15865 const APInt &C = ND->getAPIntValue();
15866 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15869 case X86ISD::VSRLI:
15870 for (unsigned i=0; i!=NumElts; ++i) {
15871 SDValue CurrentOp = SrcOp->getOperand(i);
15872 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15873 Elts.push_back(CurrentOp);
15876 ND = cast<ConstantSDNode>(CurrentOp);
15877 const APInt &C = ND->getAPIntValue();
15878 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15881 case X86ISD::VSRAI:
15882 for (unsigned i=0; i!=NumElts; ++i) {
15883 SDValue CurrentOp = SrcOp->getOperand(i);
15884 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15885 Elts.push_back(CurrentOp);
15888 ND = cast<ConstantSDNode>(CurrentOp);
15889 const APInt &C = ND->getAPIntValue();
15890 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15895 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15898 return DAG.getNode(Opc, dl, VT, SrcOp,
15899 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15902 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15903 // may or may not be a constant. Takes immediate version of shift as input.
15904 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15905 SDValue SrcOp, SDValue ShAmt,
15906 SelectionDAG &DAG) {
15907 MVT SVT = ShAmt.getSimpleValueType();
15908 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15910 // Catch shift-by-constant.
15911 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15912 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15913 CShAmt->getZExtValue(), DAG);
15915 // Change opcode to non-immediate version
15917 default: llvm_unreachable("Unknown target vector shift node");
15918 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15919 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15920 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15923 const X86Subtarget &Subtarget =
15924 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15925 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15926 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15927 // Let the shuffle legalizer expand this shift amount node.
15928 SDValue Op0 = ShAmt.getOperand(0);
15929 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15930 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15932 // Need to build a vector containing shift amount.
15933 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15934 SmallVector<SDValue, 4> ShOps;
15935 ShOps.push_back(ShAmt);
15936 if (SVT == MVT::i32) {
15937 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15938 ShOps.push_back(DAG.getUNDEF(SVT));
15940 ShOps.push_back(DAG.getUNDEF(SVT));
15942 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15943 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15946 // The return type has to be a 128-bit type with the same element
15947 // type as the input type.
15948 MVT EltVT = VT.getVectorElementType();
15949 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15951 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15952 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15955 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15956 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15957 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15958 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15959 SDValue PreservedSrc,
15960 const X86Subtarget *Subtarget,
15961 SelectionDAG &DAG) {
15962 EVT VT = Op.getValueType();
15963 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15964 MVT::i1, VT.getVectorNumElements());
15965 SDValue VMask = SDValue();
15966 unsigned OpcodeSelect = ISD::VSELECT;
15969 assert(MaskVT.isSimple() && "invalid mask type");
15971 if (isAllOnes(Mask))
15974 if (MaskVT.bitsGT(Mask.getValueType())) {
15975 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15976 MaskVT.getSizeInBits());
15977 VMask = DAG.getBitcast(MaskVT,
15978 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15980 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15981 Mask.getValueType().getSizeInBits());
15982 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15983 // are extracted by EXTRACT_SUBVECTOR.
15984 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15985 DAG.getBitcast(BitcastVT, Mask),
15986 DAG.getIntPtrConstant(0, dl));
15989 switch (Op.getOpcode()) {
15991 case X86ISD::PCMPEQM:
15992 case X86ISD::PCMPGTM:
15994 case X86ISD::CMPMU:
15995 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15996 case X86ISD::VFPCLASS:
15997 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15998 case X86ISD::VTRUNC:
15999 case X86ISD::VTRUNCS:
16000 case X86ISD::VTRUNCUS:
16001 // We can't use ISD::VSELECT here because it is not always "Legal"
16002 // for the destination type. For example vpmovqb require only AVX512
16003 // and vselect that can operate on byte element type require BWI
16004 OpcodeSelect = X86ISD::SELECT;
16007 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16008 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16009 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16012 /// \brief Creates an SDNode for a predicated scalar operation.
16013 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16014 /// The mask is coming as MVT::i8 and it should be truncated
16015 /// to MVT::i1 while lowering masking intrinsics.
16016 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16017 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16018 /// for a scalar instruction.
16019 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16020 SDValue PreservedSrc,
16021 const X86Subtarget *Subtarget,
16022 SelectionDAG &DAG) {
16023 if (isAllOnes(Mask))
16026 EVT VT = Op.getValueType();
16028 // The mask should be of type MVT::i1
16029 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16031 if (Op.getOpcode() == X86ISD::FSETCC)
16032 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16033 if (Op.getOpcode() == X86ISD::VFPCLASS)
16034 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16036 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16037 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16038 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16041 static int getSEHRegistrationNodeSize(const Function *Fn) {
16042 if (!Fn->hasPersonalityFn())
16043 report_fatal_error(
16044 "querying registration node size for function without personality");
16045 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16046 // WinEHStatePass for the full struct definition.
16047 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16048 case EHPersonality::MSVC_X86SEH: return 24;
16049 case EHPersonality::MSVC_CXX: return 16;
16052 report_fatal_error("can only recover FP for MSVC EH personality functions");
16055 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16056 /// function or when returning to a parent frame after catching an exception, we
16057 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16058 /// Here's the math:
16059 /// RegNodeBase = EntryEBP - RegNodeSize
16060 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16061 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16062 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16063 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16064 SDValue EntryEBP) {
16065 MachineFunction &MF = DAG.getMachineFunction();
16068 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16069 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16071 // It's possible that the parent function no longer has a personality function
16072 // if the exceptional code was optimized away, in which case we just return
16073 // the incoming EBP.
16074 if (!Fn->hasPersonalityFn())
16077 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16079 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16081 MCSymbol *OffsetSym =
16082 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16083 GlobalValue::getRealLinkageName(Fn->getName()));
16084 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16085 SDValue RegNodeFrameOffset =
16086 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16088 // RegNodeBase = EntryEBP - RegNodeSize
16089 // ParentFP = RegNodeBase - RegNodeFrameOffset
16090 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16091 DAG.getConstant(RegNodeSize, dl, PtrVT));
16092 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16095 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16096 SelectionDAG &DAG) {
16098 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16099 EVT VT = Op.getValueType();
16100 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16102 switch(IntrData->Type) {
16103 case INTR_TYPE_1OP:
16104 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16105 case INTR_TYPE_2OP:
16106 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16108 case INTR_TYPE_2OP_IMM8:
16109 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16110 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16111 case INTR_TYPE_3OP:
16112 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16113 Op.getOperand(2), Op.getOperand(3));
16114 case INTR_TYPE_4OP:
16115 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16116 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16117 case INTR_TYPE_1OP_MASK_RM: {
16118 SDValue Src = Op.getOperand(1);
16119 SDValue PassThru = Op.getOperand(2);
16120 SDValue Mask = Op.getOperand(3);
16121 SDValue RoundingMode;
16122 // We allways add rounding mode to the Node.
16123 // If the rounding mode is not specified, we add the
16124 // "current direction" mode.
16125 if (Op.getNumOperands() == 4)
16127 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16129 RoundingMode = Op.getOperand(4);
16130 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16131 if (IntrWithRoundingModeOpcode != 0)
16132 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16133 X86::STATIC_ROUNDING::CUR_DIRECTION)
16134 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16135 dl, Op.getValueType(), Src, RoundingMode),
16136 Mask, PassThru, Subtarget, DAG);
16137 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16139 Mask, PassThru, Subtarget, DAG);
16141 case INTR_TYPE_1OP_MASK: {
16142 SDValue Src = Op.getOperand(1);
16143 SDValue PassThru = Op.getOperand(2);
16144 SDValue Mask = Op.getOperand(3);
16145 // We add rounding mode to the Node when
16146 // - RM Opcode is specified and
16147 // - RM is not "current direction".
16148 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16149 if (IntrWithRoundingModeOpcode != 0) {
16150 SDValue Rnd = Op.getOperand(4);
16151 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16152 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16153 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16154 dl, Op.getValueType(),
16156 Mask, PassThru, Subtarget, DAG);
16159 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16160 Mask, PassThru, Subtarget, DAG);
16162 case INTR_TYPE_SCALAR_MASK: {
16163 SDValue Src1 = Op.getOperand(1);
16164 SDValue Src2 = Op.getOperand(2);
16165 SDValue passThru = Op.getOperand(3);
16166 SDValue Mask = Op.getOperand(4);
16167 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16168 Mask, passThru, Subtarget, DAG);
16170 case INTR_TYPE_SCALAR_MASK_RM: {
16171 SDValue Src1 = Op.getOperand(1);
16172 SDValue Src2 = Op.getOperand(2);
16173 SDValue Src0 = Op.getOperand(3);
16174 SDValue Mask = Op.getOperand(4);
16175 // There are 2 kinds of intrinsics in this group:
16176 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16177 // (2) With rounding mode and sae - 7 operands.
16178 if (Op.getNumOperands() == 6) {
16179 SDValue Sae = Op.getOperand(5);
16180 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16181 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16183 Mask, Src0, Subtarget, DAG);
16185 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16186 SDValue RoundingMode = Op.getOperand(5);
16187 SDValue Sae = Op.getOperand(6);
16188 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16189 RoundingMode, Sae),
16190 Mask, Src0, Subtarget, DAG);
16192 case INTR_TYPE_2OP_MASK:
16193 case INTR_TYPE_2OP_IMM8_MASK: {
16194 SDValue Src1 = Op.getOperand(1);
16195 SDValue Src2 = Op.getOperand(2);
16196 SDValue PassThru = Op.getOperand(3);
16197 SDValue Mask = Op.getOperand(4);
16199 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16200 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16202 // We specify 2 possible opcodes for intrinsics with rounding modes.
16203 // First, we check if the intrinsic may have non-default rounding mode,
16204 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16205 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16206 if (IntrWithRoundingModeOpcode != 0) {
16207 SDValue Rnd = Op.getOperand(5);
16208 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16209 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16210 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16211 dl, Op.getValueType(),
16213 Mask, PassThru, Subtarget, DAG);
16216 // TODO: Intrinsics should have fast-math-flags to propagate.
16217 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16218 Mask, PassThru, Subtarget, DAG);
16220 case INTR_TYPE_2OP_MASK_RM: {
16221 SDValue Src1 = Op.getOperand(1);
16222 SDValue Src2 = Op.getOperand(2);
16223 SDValue PassThru = Op.getOperand(3);
16224 SDValue Mask = Op.getOperand(4);
16225 // We specify 2 possible modes for intrinsics, with/without rounding
16227 // First, we check if the intrinsic have rounding mode (6 operands),
16228 // if not, we set rounding mode to "current".
16230 if (Op.getNumOperands() == 6)
16231 Rnd = Op.getOperand(5);
16233 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16234 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16236 Mask, PassThru, Subtarget, DAG);
16238 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16239 SDValue Src1 = Op.getOperand(1);
16240 SDValue Src2 = Op.getOperand(2);
16241 SDValue Src3 = Op.getOperand(3);
16242 SDValue PassThru = Op.getOperand(4);
16243 SDValue Mask = Op.getOperand(5);
16244 SDValue Sae = Op.getOperand(6);
16246 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16248 Mask, PassThru, Subtarget, DAG);
16250 case INTR_TYPE_3OP_MASK_RM: {
16251 SDValue Src1 = Op.getOperand(1);
16252 SDValue Src2 = Op.getOperand(2);
16253 SDValue Imm = Op.getOperand(3);
16254 SDValue PassThru = Op.getOperand(4);
16255 SDValue Mask = Op.getOperand(5);
16256 // We specify 2 possible modes for intrinsics, with/without rounding
16258 // First, we check if the intrinsic have rounding mode (7 operands),
16259 // if not, we set rounding mode to "current".
16261 if (Op.getNumOperands() == 7)
16262 Rnd = Op.getOperand(6);
16264 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16265 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16266 Src1, Src2, Imm, Rnd),
16267 Mask, PassThru, Subtarget, DAG);
16269 case INTR_TYPE_3OP_IMM8_MASK:
16270 case INTR_TYPE_3OP_MASK:
16271 case INSERT_SUBVEC: {
16272 SDValue Src1 = Op.getOperand(1);
16273 SDValue Src2 = Op.getOperand(2);
16274 SDValue Src3 = Op.getOperand(3);
16275 SDValue PassThru = Op.getOperand(4);
16276 SDValue Mask = Op.getOperand(5);
16278 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16279 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16280 else if (IntrData->Type == INSERT_SUBVEC) {
16281 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16282 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16283 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16284 Imm *= Src2.getValueType().getVectorNumElements();
16285 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16288 // We specify 2 possible opcodes for intrinsics with rounding modes.
16289 // First, we check if the intrinsic may have non-default rounding mode,
16290 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16291 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16292 if (IntrWithRoundingModeOpcode != 0) {
16293 SDValue Rnd = Op.getOperand(6);
16294 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16295 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16296 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16297 dl, Op.getValueType(),
16298 Src1, Src2, Src3, Rnd),
16299 Mask, PassThru, Subtarget, DAG);
16302 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16304 Mask, PassThru, Subtarget, DAG);
16306 case VPERM_3OP_MASKZ:
16307 case VPERM_3OP_MASK:
16310 case FMA_OP_MASK: {
16311 SDValue Src1 = Op.getOperand(1);
16312 SDValue Src2 = Op.getOperand(2);
16313 SDValue Src3 = Op.getOperand(3);
16314 SDValue Mask = Op.getOperand(4);
16315 EVT VT = Op.getValueType();
16316 SDValue PassThru = SDValue();
16318 // set PassThru element
16319 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16320 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16321 else if (IntrData->Type == FMA_OP_MASK3)
16326 // We specify 2 possible opcodes for intrinsics with rounding modes.
16327 // First, we check if the intrinsic may have non-default rounding mode,
16328 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16329 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16330 if (IntrWithRoundingModeOpcode != 0) {
16331 SDValue Rnd = Op.getOperand(5);
16332 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16333 X86::STATIC_ROUNDING::CUR_DIRECTION)
16334 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16335 dl, Op.getValueType(),
16336 Src1, Src2, Src3, Rnd),
16337 Mask, PassThru, Subtarget, DAG);
16339 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16340 dl, Op.getValueType(),
16342 Mask, PassThru, Subtarget, DAG);
16344 case TERLOG_OP_MASK:
16345 case TERLOG_OP_MASKZ: {
16346 SDValue Src1 = Op.getOperand(1);
16347 SDValue Src2 = Op.getOperand(2);
16348 SDValue Src3 = Op.getOperand(3);
16349 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16350 SDValue Mask = Op.getOperand(5);
16351 EVT VT = Op.getValueType();
16352 SDValue PassThru = Src1;
16353 // Set PassThru element.
16354 if (IntrData->Type == TERLOG_OP_MASKZ)
16355 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16357 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16358 Src1, Src2, Src3, Src4),
16359 Mask, PassThru, Subtarget, DAG);
16362 // FPclass intrinsics with mask
16363 SDValue Src1 = Op.getOperand(1);
16364 EVT VT = Src1.getValueType();
16365 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16366 VT.getVectorNumElements());
16367 SDValue Imm = Op.getOperand(2);
16368 SDValue Mask = Op.getOperand(3);
16369 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16370 Mask.getValueType().getSizeInBits());
16371 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16372 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16373 DAG.getTargetConstant(0, dl, MaskVT),
16375 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16376 DAG.getUNDEF(BitcastVT), FPclassMask,
16377 DAG.getIntPtrConstant(0, dl));
16378 return DAG.getBitcast(Op.getValueType(), Res);
16381 SDValue Src1 = Op.getOperand(1);
16382 SDValue Imm = Op.getOperand(2);
16383 SDValue Mask = Op.getOperand(3);
16384 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16385 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16386 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16387 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16390 case CMP_MASK_CC: {
16391 // Comparison intrinsics with masks.
16392 // Example of transformation:
16393 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16394 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16396 // (v8i1 (insert_subvector undef,
16397 // (v2i1 (and (PCMPEQM %a, %b),
16398 // (extract_subvector
16399 // (v8i1 (bitcast %mask)), 0))), 0))))
16400 EVT VT = Op.getOperand(1).getValueType();
16401 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16402 VT.getVectorNumElements());
16403 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16404 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16405 Mask.getValueType().getSizeInBits());
16407 if (IntrData->Type == CMP_MASK_CC) {
16408 SDValue CC = Op.getOperand(3);
16409 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16410 // We specify 2 possible opcodes for intrinsics with rounding modes.
16411 // First, we check if the intrinsic may have non-default rounding mode,
16412 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16413 if (IntrData->Opc1 != 0) {
16414 SDValue Rnd = Op.getOperand(5);
16415 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16416 X86::STATIC_ROUNDING::CUR_DIRECTION)
16417 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16418 Op.getOperand(2), CC, Rnd);
16420 //default rounding mode
16422 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16423 Op.getOperand(2), CC);
16426 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16427 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16430 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16431 DAG.getTargetConstant(0, dl,
16434 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16435 DAG.getUNDEF(BitcastVT), CmpMask,
16436 DAG.getIntPtrConstant(0, dl));
16437 return DAG.getBitcast(Op.getValueType(), Res);
16439 case CMP_MASK_SCALAR_CC: {
16440 SDValue Src1 = Op.getOperand(1);
16441 SDValue Src2 = Op.getOperand(2);
16442 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16443 SDValue Mask = Op.getOperand(4);
16446 if (IntrData->Opc1 != 0) {
16447 SDValue Rnd = Op.getOperand(5);
16448 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16449 X86::STATIC_ROUNDING::CUR_DIRECTION)
16450 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16452 //default rounding mode
16454 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16456 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16457 DAG.getTargetConstant(0, dl,
16461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16462 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16463 DAG.getValueType(MVT::i1));
16465 case COMI: { // Comparison intrinsics
16466 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16467 SDValue LHS = Op.getOperand(1);
16468 SDValue RHS = Op.getOperand(2);
16469 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16470 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16471 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16472 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16473 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16474 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16477 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16478 Op.getOperand(1), Op.getOperand(2), DAG);
16480 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16481 Op.getSimpleValueType(),
16483 Op.getOperand(2), DAG),
16484 Op.getOperand(4), Op.getOperand(3), Subtarget,
16486 case COMPRESS_EXPAND_IN_REG: {
16487 SDValue Mask = Op.getOperand(3);
16488 SDValue DataToCompress = Op.getOperand(1);
16489 SDValue PassThru = Op.getOperand(2);
16490 if (isAllOnes(Mask)) // return data as is
16491 return Op.getOperand(1);
16493 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16495 Mask, PassThru, Subtarget, DAG);
16498 SDValue Mask = Op.getOperand(3);
16499 EVT VT = Op.getValueType();
16500 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16501 VT.getVectorNumElements());
16502 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16503 Mask.getValueType().getSizeInBits());
16505 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16506 DAG.getBitcast(BitcastVT, Mask),
16507 DAG.getIntPtrConstant(0, dl));
16508 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16517 default: return SDValue(); // Don't custom lower most intrinsics.
16519 case Intrinsic::x86_avx2_permd:
16520 case Intrinsic::x86_avx2_permps:
16521 // Operands intentionally swapped. Mask is last operand to intrinsic,
16522 // but second operand for node/instruction.
16523 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16524 Op.getOperand(2), Op.getOperand(1));
16526 // ptest and testp intrinsics. The intrinsic these come from are designed to
16527 // return an integer value, not just an instruction so lower it to the ptest
16528 // or testp pattern and a setcc for the result.
16529 case Intrinsic::x86_sse41_ptestz:
16530 case Intrinsic::x86_sse41_ptestc:
16531 case Intrinsic::x86_sse41_ptestnzc:
16532 case Intrinsic::x86_avx_ptestz_256:
16533 case Intrinsic::x86_avx_ptestc_256:
16534 case Intrinsic::x86_avx_ptestnzc_256:
16535 case Intrinsic::x86_avx_vtestz_ps:
16536 case Intrinsic::x86_avx_vtestc_ps:
16537 case Intrinsic::x86_avx_vtestnzc_ps:
16538 case Intrinsic::x86_avx_vtestz_pd:
16539 case Intrinsic::x86_avx_vtestc_pd:
16540 case Intrinsic::x86_avx_vtestnzc_pd:
16541 case Intrinsic::x86_avx_vtestz_ps_256:
16542 case Intrinsic::x86_avx_vtestc_ps_256:
16543 case Intrinsic::x86_avx_vtestnzc_ps_256:
16544 case Intrinsic::x86_avx_vtestz_pd_256:
16545 case Intrinsic::x86_avx_vtestc_pd_256:
16546 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16547 bool IsTestPacked = false;
16550 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16551 case Intrinsic::x86_avx_vtestz_ps:
16552 case Intrinsic::x86_avx_vtestz_pd:
16553 case Intrinsic::x86_avx_vtestz_ps_256:
16554 case Intrinsic::x86_avx_vtestz_pd_256:
16555 IsTestPacked = true; // Fallthrough
16556 case Intrinsic::x86_sse41_ptestz:
16557 case Intrinsic::x86_avx_ptestz_256:
16559 X86CC = X86::COND_E;
16561 case Intrinsic::x86_avx_vtestc_ps:
16562 case Intrinsic::x86_avx_vtestc_pd:
16563 case Intrinsic::x86_avx_vtestc_ps_256:
16564 case Intrinsic::x86_avx_vtestc_pd_256:
16565 IsTestPacked = true; // Fallthrough
16566 case Intrinsic::x86_sse41_ptestc:
16567 case Intrinsic::x86_avx_ptestc_256:
16569 X86CC = X86::COND_B;
16571 case Intrinsic::x86_avx_vtestnzc_ps:
16572 case Intrinsic::x86_avx_vtestnzc_pd:
16573 case Intrinsic::x86_avx_vtestnzc_ps_256:
16574 case Intrinsic::x86_avx_vtestnzc_pd_256:
16575 IsTestPacked = true; // Fallthrough
16576 case Intrinsic::x86_sse41_ptestnzc:
16577 case Intrinsic::x86_avx_ptestnzc_256:
16579 X86CC = X86::COND_A;
16583 SDValue LHS = Op.getOperand(1);
16584 SDValue RHS = Op.getOperand(2);
16585 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16586 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16587 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16588 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16589 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16591 case Intrinsic::x86_avx512_kortestz_w:
16592 case Intrinsic::x86_avx512_kortestc_w: {
16593 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16594 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16595 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16596 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16597 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16598 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16599 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16602 case Intrinsic::x86_sse42_pcmpistria128:
16603 case Intrinsic::x86_sse42_pcmpestria128:
16604 case Intrinsic::x86_sse42_pcmpistric128:
16605 case Intrinsic::x86_sse42_pcmpestric128:
16606 case Intrinsic::x86_sse42_pcmpistrio128:
16607 case Intrinsic::x86_sse42_pcmpestrio128:
16608 case Intrinsic::x86_sse42_pcmpistris128:
16609 case Intrinsic::x86_sse42_pcmpestris128:
16610 case Intrinsic::x86_sse42_pcmpistriz128:
16611 case Intrinsic::x86_sse42_pcmpestriz128: {
16615 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16616 case Intrinsic::x86_sse42_pcmpistria128:
16617 Opcode = X86ISD::PCMPISTRI;
16618 X86CC = X86::COND_A;
16620 case Intrinsic::x86_sse42_pcmpestria128:
16621 Opcode = X86ISD::PCMPESTRI;
16622 X86CC = X86::COND_A;
16624 case Intrinsic::x86_sse42_pcmpistric128:
16625 Opcode = X86ISD::PCMPISTRI;
16626 X86CC = X86::COND_B;
16628 case Intrinsic::x86_sse42_pcmpestric128:
16629 Opcode = X86ISD::PCMPESTRI;
16630 X86CC = X86::COND_B;
16632 case Intrinsic::x86_sse42_pcmpistrio128:
16633 Opcode = X86ISD::PCMPISTRI;
16634 X86CC = X86::COND_O;
16636 case Intrinsic::x86_sse42_pcmpestrio128:
16637 Opcode = X86ISD::PCMPESTRI;
16638 X86CC = X86::COND_O;
16640 case Intrinsic::x86_sse42_pcmpistris128:
16641 Opcode = X86ISD::PCMPISTRI;
16642 X86CC = X86::COND_S;
16644 case Intrinsic::x86_sse42_pcmpestris128:
16645 Opcode = X86ISD::PCMPESTRI;
16646 X86CC = X86::COND_S;
16648 case Intrinsic::x86_sse42_pcmpistriz128:
16649 Opcode = X86ISD::PCMPISTRI;
16650 X86CC = X86::COND_E;
16652 case Intrinsic::x86_sse42_pcmpestriz128:
16653 Opcode = X86ISD::PCMPESTRI;
16654 X86CC = X86::COND_E;
16657 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16658 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16659 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16660 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16661 DAG.getConstant(X86CC, dl, MVT::i8),
16662 SDValue(PCMP.getNode(), 1));
16663 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16666 case Intrinsic::x86_sse42_pcmpistri128:
16667 case Intrinsic::x86_sse42_pcmpestri128: {
16669 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16670 Opcode = X86ISD::PCMPISTRI;
16672 Opcode = X86ISD::PCMPESTRI;
16674 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16675 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16676 return DAG.getNode(Opcode, dl, VTs, NewOps);
16679 case Intrinsic::x86_seh_lsda: {
16680 // Compute the symbol for the LSDA. We know it'll get emitted later.
16681 MachineFunction &MF = DAG.getMachineFunction();
16682 SDValue Op1 = Op.getOperand(1);
16683 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16684 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16685 GlobalValue::getRealLinkageName(Fn->getName()));
16687 // Generate a simple absolute symbol reference. This intrinsic is only
16688 // supported on 32-bit Windows, which isn't PIC.
16689 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16690 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16693 case Intrinsic::x86_seh_recoverfp: {
16694 SDValue FnOp = Op.getOperand(1);
16695 SDValue IncomingFPOp = Op.getOperand(2);
16696 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16697 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16699 report_fatal_error(
16700 "llvm.x86.seh.recoverfp must take a function as the first argument");
16701 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16704 case Intrinsic::localaddress: {
16705 // Returns one of the stack, base, or frame pointer registers, depending on
16706 // which is used to reference local variables.
16707 MachineFunction &MF = DAG.getMachineFunction();
16708 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16710 if (RegInfo->hasBasePointer(MF))
16711 Reg = RegInfo->getBaseRegister();
16712 else // This function handles the SP or FP case.
16713 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16714 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16719 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16720 SDValue Src, SDValue Mask, SDValue Base,
16721 SDValue Index, SDValue ScaleOp, SDValue Chain,
16722 const X86Subtarget * Subtarget) {
16724 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16726 llvm_unreachable("Invalid scale type");
16727 unsigned ScaleVal = C->getZExtValue();
16728 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16729 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16731 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16732 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16733 Index.getSimpleValueType().getVectorNumElements());
16735 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16737 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16739 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16740 Mask.getValueType().getSizeInBits());
16742 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16743 // are extracted by EXTRACT_SUBVECTOR.
16744 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16745 DAG.getBitcast(BitcastVT, Mask),
16746 DAG.getIntPtrConstant(0, dl));
16748 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16749 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16750 SDValue Segment = DAG.getRegister(0, MVT::i32);
16751 if (Src.getOpcode() == ISD::UNDEF)
16752 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16753 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16754 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16755 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16756 return DAG.getMergeValues(RetOps, dl);
16759 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16760 SDValue Src, SDValue Mask, SDValue Base,
16761 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16763 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16765 llvm_unreachable("Invalid scale type");
16766 unsigned ScaleVal = C->getZExtValue();
16767 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16768 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16770 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16771 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16772 SDValue Segment = DAG.getRegister(0, MVT::i32);
16773 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16774 Index.getSimpleValueType().getVectorNumElements());
16776 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16778 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16780 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16781 Mask.getValueType().getSizeInBits());
16783 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16784 // are extracted by EXTRACT_SUBVECTOR.
16785 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16786 DAG.getBitcast(BitcastVT, Mask),
16787 DAG.getIntPtrConstant(0, dl));
16789 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16790 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16791 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16792 return SDValue(Res, 1);
16795 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16796 SDValue Mask, SDValue Base, SDValue Index,
16797 SDValue ScaleOp, SDValue Chain) {
16799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16800 assert(C && "Invalid scale type");
16801 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16802 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16803 SDValue Segment = DAG.getRegister(0, MVT::i32);
16805 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16807 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16809 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16811 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16812 //SDVTList VTs = DAG.getVTList(MVT::Other);
16813 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16814 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16815 return SDValue(Res, 0);
16818 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16819 // read performance monitor counters (x86_rdpmc).
16820 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16821 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16822 SmallVectorImpl<SDValue> &Results) {
16823 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16824 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16827 // The ECX register is used to select the index of the performance counter
16829 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16831 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16833 // Reads the content of a 64-bit performance counter and returns it in the
16834 // registers EDX:EAX.
16835 if (Subtarget->is64Bit()) {
16836 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16837 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16840 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16841 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16844 Chain = HI.getValue(1);
16846 if (Subtarget->is64Bit()) {
16847 // The EAX register is loaded with the low-order 32 bits. The EDX register
16848 // is loaded with the supported high-order bits of the counter.
16849 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16850 DAG.getConstant(32, DL, MVT::i8));
16851 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16852 Results.push_back(Chain);
16856 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16857 SDValue Ops[] = { LO, HI };
16858 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16859 Results.push_back(Pair);
16860 Results.push_back(Chain);
16863 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16864 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16865 // also used to custom lower READCYCLECOUNTER nodes.
16866 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16867 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16868 SmallVectorImpl<SDValue> &Results) {
16869 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16870 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16873 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16874 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16875 // and the EAX register is loaded with the low-order 32 bits.
16876 if (Subtarget->is64Bit()) {
16877 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16878 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16881 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16882 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16885 SDValue Chain = HI.getValue(1);
16887 if (Opcode == X86ISD::RDTSCP_DAG) {
16888 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16890 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16891 // the ECX register. Add 'ecx' explicitly to the chain.
16892 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16894 // Explicitly store the content of ECX at the location passed in input
16895 // to the 'rdtscp' intrinsic.
16896 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16897 MachinePointerInfo(), false, false, 0);
16900 if (Subtarget->is64Bit()) {
16901 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16902 // the EAX register is loaded with the low-order 32 bits.
16903 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16904 DAG.getConstant(32, DL, MVT::i8));
16905 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16906 Results.push_back(Chain);
16910 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16911 SDValue Ops[] = { LO, HI };
16912 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16913 Results.push_back(Pair);
16914 Results.push_back(Chain);
16917 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16918 SelectionDAG &DAG) {
16919 SmallVector<SDValue, 2> Results;
16921 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16923 return DAG.getMergeValues(Results, DL);
16926 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16927 SelectionDAG &DAG) {
16928 MachineFunction &MF = DAG.getMachineFunction();
16929 const Function *Fn = MF.getFunction();
16931 SDValue Chain = Op.getOperand(0);
16933 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16934 "using llvm.x86.seh.restoreframe requires a frame pointer");
16936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16937 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16939 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16940 unsigned FrameReg =
16941 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16942 unsigned SPReg = RegInfo->getStackRegister();
16943 unsigned SlotSize = RegInfo->getSlotSize();
16945 // Get incoming EBP.
16946 SDValue IncomingEBP =
16947 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16949 // SP is saved in the first field of every registration node, so load
16950 // [EBP-RegNodeSize] into SP.
16951 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16952 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16953 DAG.getConstant(-RegNodeSize, dl, VT));
16955 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16956 false, VT.getScalarSizeInBits() / 8);
16957 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16959 if (!RegInfo->needsStackRealignment(MF)) {
16960 // Adjust EBP to point back to the original frame position.
16961 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16962 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16964 assert(RegInfo->hasBasePointer(MF) &&
16965 "functions with Win32 EH must use frame or base pointer register");
16967 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16968 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16969 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16971 // Reload the spilled EBP value, now that the stack and base pointers are
16973 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16974 X86FI->setHasSEHFramePtrSave(true);
16975 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16976 X86FI->setSEHFramePtrSaveIndex(FI);
16977 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16978 MachinePointerInfo(), false, false, false,
16979 VT.getScalarSizeInBits() / 8);
16980 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16986 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16987 /// return truncate Store/MaskedStore Node
16988 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16992 SDValue Mask = Op.getOperand(4);
16993 SDValue DataToTruncate = Op.getOperand(3);
16994 SDValue Addr = Op.getOperand(2);
16995 SDValue Chain = Op.getOperand(0);
16997 EVT VT = DataToTruncate.getValueType();
16998 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16999 ElementType, VT.getVectorNumElements());
17001 if (isAllOnes(Mask)) // return just a truncate store
17002 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17003 MachinePointerInfo(), SVT, false, false,
17004 SVT.getScalarSizeInBits()/8);
17006 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
17007 MVT::i1, VT.getVectorNumElements());
17008 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17009 Mask.getValueType().getSizeInBits());
17010 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17011 // are extracted by EXTRACT_SUBVECTOR.
17012 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17013 DAG.getBitcast(BitcastVT, Mask),
17014 DAG.getIntPtrConstant(0, dl));
17016 MachineMemOperand *MMO = DAG.getMachineFunction().
17017 getMachineMemOperand(MachinePointerInfo(),
17018 MachineMemOperand::MOStore, SVT.getStoreSize(),
17019 SVT.getScalarSizeInBits()/8);
17021 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17022 VMask, SVT, MMO, true);
17025 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17026 SelectionDAG &DAG) {
17027 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17029 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17031 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17032 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17037 switch(IntrData->Type) {
17039 llvm_unreachable("Unknown Intrinsic Type");
17043 // Emit the node with the right value type.
17044 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17045 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17047 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17048 // Otherwise return the value from Rand, which is always 0, casted to i32.
17049 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17050 DAG.getConstant(1, dl, Op->getValueType(1)),
17051 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17052 SDValue(Result.getNode(), 1) };
17053 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17054 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17057 // Return { result, isValid, chain }.
17058 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17059 SDValue(Result.getNode(), 2));
17062 //gather(v1, mask, index, base, scale);
17063 SDValue Chain = Op.getOperand(0);
17064 SDValue Src = Op.getOperand(2);
17065 SDValue Base = Op.getOperand(3);
17066 SDValue Index = Op.getOperand(4);
17067 SDValue Mask = Op.getOperand(5);
17068 SDValue Scale = Op.getOperand(6);
17069 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17073 //scatter(base, mask, index, v1, scale);
17074 SDValue Chain = Op.getOperand(0);
17075 SDValue Base = Op.getOperand(2);
17076 SDValue Mask = Op.getOperand(3);
17077 SDValue Index = Op.getOperand(4);
17078 SDValue Src = Op.getOperand(5);
17079 SDValue Scale = Op.getOperand(6);
17080 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17084 SDValue Hint = Op.getOperand(6);
17085 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17086 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17087 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17088 SDValue Chain = Op.getOperand(0);
17089 SDValue Mask = Op.getOperand(2);
17090 SDValue Index = Op.getOperand(3);
17091 SDValue Base = Op.getOperand(4);
17092 SDValue Scale = Op.getOperand(5);
17093 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17095 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17097 SmallVector<SDValue, 2> Results;
17098 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17100 return DAG.getMergeValues(Results, dl);
17102 // Read Performance Monitoring Counters.
17104 SmallVector<SDValue, 2> Results;
17105 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17106 return DAG.getMergeValues(Results, dl);
17108 // XTEST intrinsics.
17110 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17111 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17112 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17113 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17115 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17116 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17117 Ret, SDValue(InTrans.getNode(), 1));
17121 SmallVector<SDValue, 2> Results;
17122 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17123 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17124 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17125 DAG.getConstant(-1, dl, MVT::i8));
17126 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17127 Op.getOperand(4), GenCF.getValue(1));
17128 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17129 Op.getOperand(5), MachinePointerInfo(),
17131 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17132 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17134 Results.push_back(SetCC);
17135 Results.push_back(Store);
17136 return DAG.getMergeValues(Results, dl);
17138 case COMPRESS_TO_MEM: {
17140 SDValue Mask = Op.getOperand(4);
17141 SDValue DataToCompress = Op.getOperand(3);
17142 SDValue Addr = Op.getOperand(2);
17143 SDValue Chain = Op.getOperand(0);
17145 EVT VT = DataToCompress.getValueType();
17146 if (isAllOnes(Mask)) // return just a store
17147 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17148 MachinePointerInfo(), false, false,
17149 VT.getScalarSizeInBits()/8);
17151 SDValue Compressed =
17152 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17153 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17154 return DAG.getStore(Chain, dl, Compressed, Addr,
17155 MachinePointerInfo(), false, false,
17156 VT.getScalarSizeInBits()/8);
17158 case TRUNCATE_TO_MEM_VI8:
17159 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17160 case TRUNCATE_TO_MEM_VI16:
17161 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17162 case TRUNCATE_TO_MEM_VI32:
17163 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17164 case EXPAND_FROM_MEM: {
17166 SDValue Mask = Op.getOperand(4);
17167 SDValue PassThru = Op.getOperand(3);
17168 SDValue Addr = Op.getOperand(2);
17169 SDValue Chain = Op.getOperand(0);
17170 EVT VT = Op.getValueType();
17172 if (isAllOnes(Mask)) // return just a load
17173 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17174 false, VT.getScalarSizeInBits()/8);
17176 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17177 false, false, false,
17178 VT.getScalarSizeInBits()/8);
17180 SDValue Results[] = {
17181 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17182 Mask, PassThru, Subtarget, DAG), Chain};
17183 return DAG.getMergeValues(Results, dl);
17188 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17189 SelectionDAG &DAG) const {
17190 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17191 MFI->setReturnAddressIsTaken(true);
17193 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17196 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17198 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17201 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17202 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17203 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17204 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17205 DAG.getNode(ISD::ADD, dl, PtrVT,
17206 FrameAddr, Offset),
17207 MachinePointerInfo(), false, false, false, 0);
17210 // Just load the return address.
17211 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17212 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17213 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17216 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17217 MachineFunction &MF = DAG.getMachineFunction();
17218 MachineFrameInfo *MFI = MF.getFrameInfo();
17219 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17220 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17221 EVT VT = Op.getValueType();
17223 MFI->setFrameAddressIsTaken(true);
17225 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17226 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17227 // is not possible to crawl up the stack without looking at the unwind codes
17229 int FrameAddrIndex = FuncInfo->getFAIndex();
17230 if (!FrameAddrIndex) {
17231 // Set up a frame object for the return address.
17232 unsigned SlotSize = RegInfo->getSlotSize();
17233 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17234 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17235 FuncInfo->setFAIndex(FrameAddrIndex);
17237 return DAG.getFrameIndex(FrameAddrIndex, VT);
17240 unsigned FrameReg =
17241 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17242 SDLoc dl(Op); // FIXME probably not meaningful
17243 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17244 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17245 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17246 "Invalid Frame Register!");
17247 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17249 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17250 MachinePointerInfo(),
17251 false, false, false, 0);
17255 // FIXME? Maybe this could be a TableGen attribute on some registers and
17256 // this table could be generated automatically from RegInfo.
17257 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17258 SelectionDAG &DAG) const {
17259 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17260 const MachineFunction &MF = DAG.getMachineFunction();
17262 unsigned Reg = StringSwitch<unsigned>(RegName)
17263 .Case("esp", X86::ESP)
17264 .Case("rsp", X86::RSP)
17265 .Case("ebp", X86::EBP)
17266 .Case("rbp", X86::RBP)
17269 if (Reg == X86::EBP || Reg == X86::RBP) {
17270 if (!TFI.hasFP(MF))
17271 report_fatal_error("register " + StringRef(RegName) +
17272 " is allocatable: function has no frame pointer");
17275 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17276 unsigned FrameReg =
17277 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17278 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17279 "Invalid Frame Register!");
17287 report_fatal_error("Invalid register name global variable");
17290 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17291 SelectionDAG &DAG) const {
17292 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17293 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17296 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17297 SDValue Chain = Op.getOperand(0);
17298 SDValue Offset = Op.getOperand(1);
17299 SDValue Handler = Op.getOperand(2);
17302 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17303 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17304 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17305 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17306 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17307 "Invalid Frame Register!");
17308 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17309 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17311 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17312 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17314 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17315 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17317 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17319 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17320 DAG.getRegister(StoreAddrReg, PtrVT));
17323 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17324 SelectionDAG &DAG) const {
17326 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17327 DAG.getVTList(MVT::i32, MVT::Other),
17328 Op.getOperand(0), Op.getOperand(1));
17331 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17332 SelectionDAG &DAG) const {
17334 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17335 Op.getOperand(0), Op.getOperand(1));
17338 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17339 return Op.getOperand(0);
17342 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17343 SelectionDAG &DAG) const {
17344 SDValue Root = Op.getOperand(0);
17345 SDValue Trmp = Op.getOperand(1); // trampoline
17346 SDValue FPtr = Op.getOperand(2); // nested function
17347 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17350 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17351 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17353 if (Subtarget->is64Bit()) {
17354 SDValue OutChains[6];
17356 // Large code-model.
17357 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17358 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17360 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17361 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17363 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17365 // Load the pointer to the nested function into R11.
17366 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17367 SDValue Addr = Trmp;
17368 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17369 Addr, MachinePointerInfo(TrmpAddr),
17372 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17373 DAG.getConstant(2, dl, MVT::i64));
17374 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17375 MachinePointerInfo(TrmpAddr, 2),
17378 // Load the 'nest' parameter value into R10.
17379 // R10 is specified in X86CallingConv.td
17380 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17382 DAG.getConstant(10, dl, MVT::i64));
17383 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17384 Addr, MachinePointerInfo(TrmpAddr, 10),
17387 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17388 DAG.getConstant(12, dl, MVT::i64));
17389 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17390 MachinePointerInfo(TrmpAddr, 12),
17393 // Jump to the nested function.
17394 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17395 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17396 DAG.getConstant(20, dl, MVT::i64));
17397 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17398 Addr, MachinePointerInfo(TrmpAddr, 20),
17401 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17402 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17403 DAG.getConstant(22, dl, MVT::i64));
17404 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17405 Addr, MachinePointerInfo(TrmpAddr, 22),
17408 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17410 const Function *Func =
17411 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17412 CallingConv::ID CC = Func->getCallingConv();
17417 llvm_unreachable("Unsupported calling convention");
17418 case CallingConv::C:
17419 case CallingConv::X86_StdCall: {
17420 // Pass 'nest' parameter in ECX.
17421 // Must be kept in sync with X86CallingConv.td
17422 NestReg = X86::ECX;
17424 // Check that ECX wasn't needed by an 'inreg' parameter.
17425 FunctionType *FTy = Func->getFunctionType();
17426 const AttributeSet &Attrs = Func->getAttributes();
17428 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17429 unsigned InRegCount = 0;
17432 for (FunctionType::param_iterator I = FTy->param_begin(),
17433 E = FTy->param_end(); I != E; ++I, ++Idx)
17434 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17435 auto &DL = DAG.getDataLayout();
17436 // FIXME: should only count parameters that are lowered to integers.
17437 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17440 if (InRegCount > 2) {
17441 report_fatal_error("Nest register in use - reduce number of inreg"
17447 case CallingConv::X86_FastCall:
17448 case CallingConv::X86_ThisCall:
17449 case CallingConv::Fast:
17450 // Pass 'nest' parameter in EAX.
17451 // Must be kept in sync with X86CallingConv.td
17452 NestReg = X86::EAX;
17456 SDValue OutChains[4];
17457 SDValue Addr, Disp;
17459 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17460 DAG.getConstant(10, dl, MVT::i32));
17461 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17463 // This is storing the opcode for MOV32ri.
17464 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17465 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17466 OutChains[0] = DAG.getStore(Root, dl,
17467 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17468 Trmp, MachinePointerInfo(TrmpAddr),
17471 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17472 DAG.getConstant(1, dl, MVT::i32));
17473 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17474 MachinePointerInfo(TrmpAddr, 1),
17477 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17478 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17479 DAG.getConstant(5, dl, MVT::i32));
17480 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17481 Addr, MachinePointerInfo(TrmpAddr, 5),
17484 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17485 DAG.getConstant(6, dl, MVT::i32));
17486 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17487 MachinePointerInfo(TrmpAddr, 6),
17490 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17494 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17495 SelectionDAG &DAG) const {
17497 The rounding mode is in bits 11:10 of FPSR, and has the following
17499 00 Round to nearest
17504 FLT_ROUNDS, on the other hand, expects the following:
17511 To perform the conversion, we do:
17512 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17515 MachineFunction &MF = DAG.getMachineFunction();
17516 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17517 unsigned StackAlignment = TFI.getStackAlignment();
17518 MVT VT = Op.getSimpleValueType();
17521 // Save FP Control Word to stack slot
17522 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17523 SDValue StackSlot =
17524 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17526 MachineMemOperand *MMO =
17527 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17528 MachineMemOperand::MOStore, 2, 2);
17530 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17531 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17532 DAG.getVTList(MVT::Other),
17533 Ops, MVT::i16, MMO);
17535 // Load FP Control Word from stack slot
17536 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17537 MachinePointerInfo(), false, false, false, 0);
17539 // Transform as necessary
17541 DAG.getNode(ISD::SRL, DL, MVT::i16,
17542 DAG.getNode(ISD::AND, DL, MVT::i16,
17543 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17544 DAG.getConstant(11, DL, MVT::i8));
17546 DAG.getNode(ISD::SRL, DL, MVT::i16,
17547 DAG.getNode(ISD::AND, DL, MVT::i16,
17548 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17549 DAG.getConstant(9, DL, MVT::i8));
17552 DAG.getNode(ISD::AND, DL, MVT::i16,
17553 DAG.getNode(ISD::ADD, DL, MVT::i16,
17554 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17555 DAG.getConstant(1, DL, MVT::i16)),
17556 DAG.getConstant(3, DL, MVT::i16));
17558 return DAG.getNode((VT.getSizeInBits() < 16 ?
17559 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17562 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17564 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17565 // to 512-bit vector.
17566 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17567 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17568 // split the vector, perform operation on it's Lo a Hi part and
17569 // concatenate the results.
17570 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17572 MVT VT = Op.getSimpleValueType();
17573 MVT EltVT = VT.getVectorElementType();
17574 unsigned NumElems = VT.getVectorNumElements();
17576 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17577 // Extend to 512 bit vector.
17578 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17579 "Unsupported value type for operation");
17581 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17582 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17583 DAG.getUNDEF(NewVT),
17585 DAG.getIntPtrConstant(0, dl));
17586 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17588 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17589 DAG.getIntPtrConstant(0, dl));
17592 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17593 "Unsupported element type");
17595 if (16 < NumElems) {
17596 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17598 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17599 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17601 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17602 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17604 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17607 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17609 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17610 "Unsupported value type for operation");
17612 // Use native supported vector instruction vplzcntd.
17613 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17614 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17615 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17616 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17618 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17621 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17622 SelectionDAG &DAG) {
17623 MVT VT = Op.getSimpleValueType();
17625 unsigned NumBits = VT.getSizeInBits();
17628 if (VT.isVector() && Subtarget->hasAVX512())
17629 return LowerVectorCTLZ_AVX512(Op, DAG);
17631 Op = Op.getOperand(0);
17632 if (VT == MVT::i8) {
17633 // Zero extend to i32 since there is not an i8 bsr.
17635 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17638 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17639 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17640 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17642 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17645 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17646 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17649 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17651 // Finally xor with NumBits-1.
17652 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17653 DAG.getConstant(NumBits - 1, dl, OpVT));
17656 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17660 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17661 SelectionDAG &DAG) {
17662 MVT VT = Op.getSimpleValueType();
17664 unsigned NumBits = VT.getSizeInBits();
17667 if (VT.isVector() && Subtarget->hasAVX512())
17668 return LowerVectorCTLZ_AVX512(Op, DAG);
17670 Op = Op.getOperand(0);
17671 if (VT == MVT::i8) {
17672 // Zero extend to i32 since there is not an i8 bsr.
17674 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17677 // Issue a bsr (scan bits in reverse).
17678 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17679 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17681 // And xor with NumBits-1.
17682 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17683 DAG.getConstant(NumBits - 1, dl, OpVT));
17686 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17690 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17691 MVT VT = Op.getSimpleValueType();
17692 unsigned NumBits = VT.getScalarSizeInBits();
17695 if (VT.isVector()) {
17696 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17698 SDValue N0 = Op.getOperand(0);
17699 SDValue Zero = DAG.getConstant(0, dl, VT);
17701 // lsb(x) = (x & -x)
17702 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17703 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17705 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17706 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17707 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17708 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17709 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17710 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17713 // cttz(x) = ctpop(lsb - 1)
17714 SDValue One = DAG.getConstant(1, dl, VT);
17715 return DAG.getNode(ISD::CTPOP, dl, VT,
17716 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17719 assert(Op.getOpcode() == ISD::CTTZ &&
17720 "Only scalar CTTZ requires custom lowering");
17722 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17723 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17724 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17726 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17729 DAG.getConstant(NumBits, dl, VT),
17730 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17733 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17736 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17737 // ones, and then concatenate the result back.
17738 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17739 MVT VT = Op.getSimpleValueType();
17741 assert(VT.is256BitVector() && VT.isInteger() &&
17742 "Unsupported value type for operation");
17744 unsigned NumElems = VT.getVectorNumElements();
17747 // Extract the LHS vectors
17748 SDValue LHS = Op.getOperand(0);
17749 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17750 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17752 // Extract the RHS vectors
17753 SDValue RHS = Op.getOperand(1);
17754 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17755 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17757 MVT EltVT = VT.getVectorElementType();
17758 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17760 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17761 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17762 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17765 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17766 if (Op.getValueType() == MVT::i1)
17767 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17768 Op.getOperand(0), Op.getOperand(1));
17769 assert(Op.getSimpleValueType().is256BitVector() &&
17770 Op.getSimpleValueType().isInteger() &&
17771 "Only handle AVX 256-bit vector integer operation");
17772 return Lower256IntArith(Op, DAG);
17775 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17776 if (Op.getValueType() == MVT::i1)
17777 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17778 Op.getOperand(0), Op.getOperand(1));
17779 assert(Op.getSimpleValueType().is256BitVector() &&
17780 Op.getSimpleValueType().isInteger() &&
17781 "Only handle AVX 256-bit vector integer operation");
17782 return Lower256IntArith(Op, DAG);
17785 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17786 assert(Op.getSimpleValueType().is256BitVector() &&
17787 Op.getSimpleValueType().isInteger() &&
17788 "Only handle AVX 256-bit vector integer operation");
17789 return Lower256IntArith(Op, DAG);
17792 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17793 SelectionDAG &DAG) {
17795 MVT VT = Op.getSimpleValueType();
17798 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17800 // Decompose 256-bit ops into smaller 128-bit ops.
17801 if (VT.is256BitVector() && !Subtarget->hasInt256())
17802 return Lower256IntArith(Op, DAG);
17804 SDValue A = Op.getOperand(0);
17805 SDValue B = Op.getOperand(1);
17807 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17808 // pairs, multiply and truncate.
17809 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17810 if (Subtarget->hasInt256()) {
17811 if (VT == MVT::v32i8) {
17812 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17813 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17814 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17815 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17816 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17817 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17818 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17819 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17820 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17821 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17824 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17825 return DAG.getNode(
17826 ISD::TRUNCATE, dl, VT,
17827 DAG.getNode(ISD::MUL, dl, ExVT,
17828 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17829 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17832 assert(VT == MVT::v16i8 &&
17833 "Pre-AVX2 support only supports v16i8 multiplication");
17834 MVT ExVT = MVT::v8i16;
17836 // Extract the lo parts and sign extend to i16
17838 if (Subtarget->hasSSE41()) {
17839 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17840 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17842 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17843 -1, 4, -1, 5, -1, 6, -1, 7};
17844 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17845 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17846 ALo = DAG.getBitcast(ExVT, ALo);
17847 BLo = DAG.getBitcast(ExVT, BLo);
17848 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17849 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17852 // Extract the hi parts and sign extend to i16
17854 if (Subtarget->hasSSE41()) {
17855 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17856 -1, -1, -1, -1, -1, -1, -1, -1};
17857 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17858 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17859 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17860 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17862 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17863 -1, 12, -1, 13, -1, 14, -1, 15};
17864 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17865 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17866 AHi = DAG.getBitcast(ExVT, AHi);
17867 BHi = DAG.getBitcast(ExVT, BHi);
17868 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17869 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17872 // Multiply, mask the lower 8bits of the lo/hi results and pack
17873 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17874 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17875 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17876 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17877 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17880 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17881 if (VT == MVT::v4i32) {
17882 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17883 "Should not custom lower when pmuldq is available!");
17885 // Extract the odd parts.
17886 static const int UnpackMask[] = { 1, -1, 3, -1 };
17887 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17888 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17890 // Multiply the even parts.
17891 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17892 // Now multiply odd parts.
17893 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17895 Evens = DAG.getBitcast(VT, Evens);
17896 Odds = DAG.getBitcast(VT, Odds);
17898 // Merge the two vectors back together with a shuffle. This expands into 2
17900 static const int ShufMask[] = { 0, 4, 2, 6 };
17901 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17904 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17905 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17907 // Ahi = psrlqi(a, 32);
17908 // Bhi = psrlqi(b, 32);
17910 // AloBlo = pmuludq(a, b);
17911 // AloBhi = pmuludq(a, Bhi);
17912 // AhiBlo = pmuludq(Ahi, b);
17914 // AloBhi = psllqi(AloBhi, 32);
17915 // AhiBlo = psllqi(AhiBlo, 32);
17916 // return AloBlo + AloBhi + AhiBlo;
17918 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17919 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17921 SDValue AhiBlo = Ahi;
17922 SDValue AloBhi = Bhi;
17923 // Bit cast to 32-bit vectors for MULUDQ
17924 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17925 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17926 A = DAG.getBitcast(MulVT, A);
17927 B = DAG.getBitcast(MulVT, B);
17928 Ahi = DAG.getBitcast(MulVT, Ahi);
17929 Bhi = DAG.getBitcast(MulVT, Bhi);
17931 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17932 // After shifting right const values the result may be all-zero.
17933 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17934 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17935 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17937 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17938 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17939 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17942 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17943 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17946 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17947 assert(Subtarget->isTargetWin64() && "Unexpected target");
17948 EVT VT = Op.getValueType();
17949 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17950 "Unexpected return type for lowering");
17954 switch (Op->getOpcode()) {
17955 default: llvm_unreachable("Unexpected request for libcall!");
17956 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17957 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17958 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17959 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17960 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17961 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17965 SDValue InChain = DAG.getEntryNode();
17967 TargetLowering::ArgListTy Args;
17968 TargetLowering::ArgListEntry Entry;
17969 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17970 EVT ArgVT = Op->getOperand(i).getValueType();
17971 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17972 "Unexpected argument type for lowering");
17973 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17974 Entry.Node = StackPtr;
17975 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17977 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17978 Entry.Ty = PointerType::get(ArgTy,0);
17979 Entry.isSExt = false;
17980 Entry.isZExt = false;
17981 Args.push_back(Entry);
17984 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17985 getPointerTy(DAG.getDataLayout()));
17987 TargetLowering::CallLoweringInfo CLI(DAG);
17988 CLI.setDebugLoc(dl).setChain(InChain)
17989 .setCallee(getLibcallCallingConv(LC),
17990 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17991 Callee, std::move(Args), 0)
17992 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17994 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17995 return DAG.getBitcast(VT, CallInfo.first);
17998 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17999 SelectionDAG &DAG) {
18000 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18001 EVT VT = Op0.getValueType();
18004 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18005 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18007 // PMULxD operations multiply each even value (starting at 0) of LHS with
18008 // the related value of RHS and produce a widen result.
18009 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18010 // => <2 x i64> <ae|cg>
18012 // In other word, to have all the results, we need to perform two PMULxD:
18013 // 1. one with the even values.
18014 // 2. one with the odd values.
18015 // To achieve #2, with need to place the odd values at an even position.
18017 // Place the odd value at an even position (basically, shift all values 1
18018 // step to the left):
18019 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18020 // <a|b|c|d> => <b|undef|d|undef>
18021 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18022 // <e|f|g|h> => <f|undef|h|undef>
18023 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18025 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18027 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18028 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18030 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18031 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18032 // => <2 x i64> <ae|cg>
18033 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18034 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18035 // => <2 x i64> <bf|dh>
18036 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18038 // Shuffle it back into the right order.
18039 SDValue Highs, Lows;
18040 if (VT == MVT::v8i32) {
18041 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18042 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18043 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18044 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18046 const int HighMask[] = {1, 5, 3, 7};
18047 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18048 const int LowMask[] = {0, 4, 2, 6};
18049 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18052 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18053 // unsigned multiply.
18054 if (IsSigned && !Subtarget->hasSSE41()) {
18055 SDValue ShAmt = DAG.getConstant(
18057 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18058 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18059 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18060 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18061 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18063 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18064 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18067 // The first result of MUL_LOHI is actually the low value, followed by the
18069 SDValue Ops[] = {Lows, Highs};
18070 return DAG.getMergeValues(Ops, dl);
18073 // Return true if the required (according to Opcode) shift-imm form is natively
18074 // supported by the Subtarget
18075 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18077 if (VT.getScalarSizeInBits() < 16)
18080 if (VT.is512BitVector() &&
18081 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18084 bool LShift = VT.is128BitVector() ||
18085 (VT.is256BitVector() && Subtarget->hasInt256());
18087 bool AShift = LShift && (Subtarget->hasVLX() ||
18088 (VT != MVT::v2i64 && VT != MVT::v4i64));
18089 return (Opcode == ISD::SRA) ? AShift : LShift;
18092 // The shift amount is a variable, but it is the same for all vector lanes.
18093 // These instructions are defined together with shift-immediate.
18095 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18097 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18100 // Return true if the required (according to Opcode) variable-shift form is
18101 // natively supported by the Subtarget
18102 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18105 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18108 // vXi16 supported only on AVX-512, BWI
18109 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18112 if (VT.is512BitVector() || Subtarget->hasVLX())
18115 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18116 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18117 return (Opcode == ISD::SRA) ? AShift : LShift;
18120 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18121 const X86Subtarget *Subtarget) {
18122 MVT VT = Op.getSimpleValueType();
18124 SDValue R = Op.getOperand(0);
18125 SDValue Amt = Op.getOperand(1);
18127 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18128 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18130 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18131 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18132 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18133 SDValue Ex = DAG.getBitcast(ExVT, R);
18135 if (ShiftAmt >= 32) {
18136 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18138 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18139 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18140 ShiftAmt - 32, DAG);
18141 if (VT == MVT::v2i64)
18142 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18143 if (VT == MVT::v4i64)
18144 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18145 {9, 1, 11, 3, 13, 5, 15, 7});
18147 // SRA upper i32, SHL whole i64 and select lower i32.
18148 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18151 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18152 Lower = DAG.getBitcast(ExVT, Lower);
18153 if (VT == MVT::v2i64)
18154 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18155 if (VT == MVT::v4i64)
18156 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18157 {8, 1, 10, 3, 12, 5, 14, 7});
18159 return DAG.getBitcast(VT, Ex);
18162 // Optimize shl/srl/sra with constant shift amount.
18163 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18164 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18165 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18167 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18168 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18170 // i64 SRA needs to be performed as partial shifts.
18171 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18172 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18173 return ArithmeticShiftRight64(ShiftAmt);
18175 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18176 unsigned NumElts = VT.getVectorNumElements();
18177 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18179 // Simple i8 add case
18180 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18181 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18183 // ashr(R, 7) === cmp_slt(R, 0)
18184 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18185 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18186 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18189 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18190 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18193 if (Op.getOpcode() == ISD::SHL) {
18194 // Make a large shift.
18195 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18197 SHL = DAG.getBitcast(VT, SHL);
18198 // Zero out the rightmost bits.
18199 SmallVector<SDValue, 32> V(
18200 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18201 return DAG.getNode(ISD::AND, dl, VT, SHL,
18202 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18204 if (Op.getOpcode() == ISD::SRL) {
18205 // Make a large shift.
18206 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18208 SRL = DAG.getBitcast(VT, SRL);
18209 // Zero out the leftmost bits.
18210 SmallVector<SDValue, 32> V(
18211 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18212 return DAG.getNode(ISD::AND, dl, VT, SRL,
18213 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18215 if (Op.getOpcode() == ISD::SRA) {
18216 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18217 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18218 SmallVector<SDValue, 32> V(NumElts,
18219 DAG.getConstant(128 >> ShiftAmt, dl,
18221 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18222 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18223 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18226 llvm_unreachable("Unknown shift opcode.");
18231 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18232 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18233 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18235 // Peek through any splat that was introduced for i64 shift vectorization.
18236 int SplatIndex = -1;
18237 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18238 if (SVN->isSplat()) {
18239 SplatIndex = SVN->getSplatIndex();
18240 Amt = Amt.getOperand(0);
18241 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18242 "Splat shuffle referencing second operand");
18245 if (Amt.getOpcode() != ISD::BITCAST ||
18246 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18249 Amt = Amt.getOperand(0);
18250 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18251 VT.getVectorNumElements();
18252 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18253 uint64_t ShiftAmt = 0;
18254 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18255 for (unsigned i = 0; i != Ratio; ++i) {
18256 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18260 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18263 // Check remaining shift amounts (if not a splat).
18264 if (SplatIndex < 0) {
18265 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18266 uint64_t ShAmt = 0;
18267 for (unsigned j = 0; j != Ratio; ++j) {
18268 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18272 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18274 if (ShAmt != ShiftAmt)
18279 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18280 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18282 if (Op.getOpcode() == ISD::SRA)
18283 return ArithmeticShiftRight64(ShiftAmt);
18289 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18290 const X86Subtarget* Subtarget) {
18291 MVT VT = Op.getSimpleValueType();
18293 SDValue R = Op.getOperand(0);
18294 SDValue Amt = Op.getOperand(1);
18296 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18297 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18299 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18300 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18302 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18304 EVT EltVT = VT.getVectorElementType();
18306 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18307 // Check if this build_vector node is doing a splat.
18308 // If so, then set BaseShAmt equal to the splat value.
18309 BaseShAmt = BV->getSplatValue();
18310 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18311 BaseShAmt = SDValue();
18313 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18314 Amt = Amt.getOperand(0);
18316 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18317 if (SVN && SVN->isSplat()) {
18318 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18319 SDValue InVec = Amt.getOperand(0);
18320 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18321 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18322 "Unexpected shuffle index found!");
18323 BaseShAmt = InVec.getOperand(SplatIdx);
18324 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18325 if (ConstantSDNode *C =
18326 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18327 if (C->getZExtValue() == SplatIdx)
18328 BaseShAmt = InVec.getOperand(1);
18333 // Avoid introducing an extract element from a shuffle.
18334 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18335 DAG.getIntPtrConstant(SplatIdx, dl));
18339 if (BaseShAmt.getNode()) {
18340 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18341 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18342 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18343 else if (EltVT.bitsLT(MVT::i32))
18344 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18346 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18350 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18351 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18352 Amt.getOpcode() == ISD::BITCAST &&
18353 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18354 Amt = Amt.getOperand(0);
18355 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18356 VT.getVectorNumElements();
18357 std::vector<SDValue> Vals(Ratio);
18358 for (unsigned i = 0; i != Ratio; ++i)
18359 Vals[i] = Amt.getOperand(i);
18360 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18361 for (unsigned j = 0; j != Ratio; ++j)
18362 if (Vals[j] != Amt.getOperand(i + j))
18366 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18367 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18372 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18373 SelectionDAG &DAG) {
18374 MVT VT = Op.getSimpleValueType();
18376 SDValue R = Op.getOperand(0);
18377 SDValue Amt = Op.getOperand(1);
18379 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18380 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18382 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18385 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18388 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18391 // XOP has 128-bit variable logical/arithmetic shifts.
18392 // +ve/-ve Amt = shift left/right.
18393 if (Subtarget->hasXOP() &&
18394 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18395 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18396 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18397 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18398 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18400 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18401 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18402 if (Op.getOpcode() == ISD::SRA)
18403 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18406 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18407 // shifts per-lane and then shuffle the partial results back together.
18408 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18409 // Splat the shift amounts so the scalar shifts above will catch it.
18410 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18411 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18412 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18413 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18414 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18417 // i64 vector arithmetic shift can be emulated with the transform:
18418 // M = lshr(SIGN_BIT, Amt)
18419 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18420 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18421 Op.getOpcode() == ISD::SRA) {
18422 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18423 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18424 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18425 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18426 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18430 // If possible, lower this packed shift into a vector multiply instead of
18431 // expanding it into a sequence of scalar shifts.
18432 // Do this only if the vector shift count is a constant build_vector.
18433 if (Op.getOpcode() == ISD::SHL &&
18434 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18435 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18436 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18437 SmallVector<SDValue, 8> Elts;
18438 EVT SVT = VT.getScalarType();
18439 unsigned SVTBits = SVT.getSizeInBits();
18440 const APInt &One = APInt(SVTBits, 1);
18441 unsigned NumElems = VT.getVectorNumElements();
18443 for (unsigned i=0; i !=NumElems; ++i) {
18444 SDValue Op = Amt->getOperand(i);
18445 if (Op->getOpcode() == ISD::UNDEF) {
18446 Elts.push_back(Op);
18450 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18451 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18452 uint64_t ShAmt = C.getZExtValue();
18453 if (ShAmt >= SVTBits) {
18454 Elts.push_back(DAG.getUNDEF(SVT));
18457 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18459 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18460 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18463 // Lower SHL with variable shift amount.
18464 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18465 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18467 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18468 DAG.getConstant(0x3f800000U, dl, VT));
18469 Op = DAG.getBitcast(MVT::v4f32, Op);
18470 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18471 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18474 // If possible, lower this shift as a sequence of two shifts by
18475 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18477 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18479 // Could be rewritten as:
18480 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18482 // The advantage is that the two shifts from the example would be
18483 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18484 // the vector shift into four scalar shifts plus four pairs of vector
18486 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18487 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18488 unsigned TargetOpcode = X86ISD::MOVSS;
18489 bool CanBeSimplified;
18490 // The splat value for the first packed shift (the 'X' from the example).
18491 SDValue Amt1 = Amt->getOperand(0);
18492 // The splat value for the second packed shift (the 'Y' from the example).
18493 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18494 Amt->getOperand(2);
18496 // See if it is possible to replace this node with a sequence of
18497 // two shifts followed by a MOVSS/MOVSD
18498 if (VT == MVT::v4i32) {
18499 // Check if it is legal to use a MOVSS.
18500 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18501 Amt2 == Amt->getOperand(3);
18502 if (!CanBeSimplified) {
18503 // Otherwise, check if we can still simplify this node using a MOVSD.
18504 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18505 Amt->getOperand(2) == Amt->getOperand(3);
18506 TargetOpcode = X86ISD::MOVSD;
18507 Amt2 = Amt->getOperand(2);
18510 // Do similar checks for the case where the machine value type
18512 CanBeSimplified = Amt1 == Amt->getOperand(1);
18513 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18514 CanBeSimplified = Amt2 == Amt->getOperand(i);
18516 if (!CanBeSimplified) {
18517 TargetOpcode = X86ISD::MOVSD;
18518 CanBeSimplified = true;
18519 Amt2 = Amt->getOperand(4);
18520 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18521 CanBeSimplified = Amt1 == Amt->getOperand(i);
18522 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18523 CanBeSimplified = Amt2 == Amt->getOperand(j);
18527 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18528 isa<ConstantSDNode>(Amt2)) {
18529 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18530 EVT CastVT = MVT::v4i32;
18532 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18533 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18535 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18536 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18537 if (TargetOpcode == X86ISD::MOVSD)
18538 CastVT = MVT::v2i64;
18539 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18540 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18541 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18543 return DAG.getBitcast(VT, Result);
18547 // v4i32 Non Uniform Shifts.
18548 // If the shift amount is constant we can shift each lane using the SSE2
18549 // immediate shifts, else we need to zero-extend each lane to the lower i64
18550 // and shift using the SSE2 variable shifts.
18551 // The separate results can then be blended together.
18552 if (VT == MVT::v4i32) {
18553 unsigned Opc = Op.getOpcode();
18554 SDValue Amt0, Amt1, Amt2, Amt3;
18555 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18556 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18557 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18558 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18559 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18561 // ISD::SHL is handled above but we include it here for completeness.
18564 llvm_unreachable("Unknown target vector shift node");
18566 Opc = X86ISD::VSHL;
18569 Opc = X86ISD::VSRL;
18572 Opc = X86ISD::VSRA;
18575 // The SSE2 shifts use the lower i64 as the same shift amount for
18576 // all lanes and the upper i64 is ignored. These shuffle masks
18577 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18578 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18579 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18580 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18581 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18582 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18585 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18586 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18587 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18588 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18589 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18590 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18591 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18594 if (VT == MVT::v16i8 ||
18595 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18596 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18597 unsigned ShiftOpcode = Op->getOpcode();
18599 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18600 // On SSE41 targets we make use of the fact that VSELECT lowers
18601 // to PBLENDVB which selects bytes based just on the sign bit.
18602 if (Subtarget->hasSSE41()) {
18603 V0 = DAG.getBitcast(VT, V0);
18604 V1 = DAG.getBitcast(VT, V1);
18605 Sel = DAG.getBitcast(VT, Sel);
18606 return DAG.getBitcast(SelVT,
18607 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18609 // On pre-SSE41 targets we test for the sign bit by comparing to
18610 // zero - a negative value will set all bits of the lanes to true
18611 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18612 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18613 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18614 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18617 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18618 // We can safely do this using i16 shifts as we're only interested in
18619 // the 3 lower bits of each byte.
18620 Amt = DAG.getBitcast(ExtVT, Amt);
18621 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18622 Amt = DAG.getBitcast(VT, Amt);
18624 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18625 // r = VSELECT(r, shift(r, 4), a);
18627 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18628 R = SignBitSelect(VT, Amt, M, R);
18631 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18633 // r = VSELECT(r, shift(r, 2), a);
18634 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18635 R = SignBitSelect(VT, Amt, M, R);
18638 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18640 // return VSELECT(r, shift(r, 1), a);
18641 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18642 R = SignBitSelect(VT, Amt, M, R);
18646 if (Op->getOpcode() == ISD::SRA) {
18647 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18648 // so we can correctly sign extend. We don't care what happens to the
18650 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18651 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18652 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18653 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18654 ALo = DAG.getBitcast(ExtVT, ALo);
18655 AHi = DAG.getBitcast(ExtVT, AHi);
18656 RLo = DAG.getBitcast(ExtVT, RLo);
18657 RHi = DAG.getBitcast(ExtVT, RHi);
18659 // r = VSELECT(r, shift(r, 4), a);
18660 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18661 DAG.getConstant(4, dl, ExtVT));
18662 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18663 DAG.getConstant(4, dl, ExtVT));
18664 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18665 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18668 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18669 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18671 // r = VSELECT(r, shift(r, 2), a);
18672 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18673 DAG.getConstant(2, dl, ExtVT));
18674 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18675 DAG.getConstant(2, dl, ExtVT));
18676 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18677 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18680 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18681 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18683 // r = VSELECT(r, shift(r, 1), a);
18684 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18685 DAG.getConstant(1, dl, ExtVT));
18686 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18687 DAG.getConstant(1, dl, ExtVT));
18688 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18689 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18691 // Logical shift the result back to the lower byte, leaving a zero upper
18693 // meaning that we can safely pack with PACKUSWB.
18695 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18697 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18698 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18702 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18703 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18704 // solution better.
18705 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18706 MVT ExtVT = MVT::v8i32;
18708 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18709 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18710 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18711 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18712 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18715 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18716 MVT ExtVT = MVT::v8i32;
18717 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18718 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18719 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18720 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18721 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18722 ALo = DAG.getBitcast(ExtVT, ALo);
18723 AHi = DAG.getBitcast(ExtVT, AHi);
18724 RLo = DAG.getBitcast(ExtVT, RLo);
18725 RHi = DAG.getBitcast(ExtVT, RHi);
18726 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18727 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18728 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18729 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18730 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18733 if (VT == MVT::v8i16) {
18734 unsigned ShiftOpcode = Op->getOpcode();
18736 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18737 // On SSE41 targets we make use of the fact that VSELECT lowers
18738 // to PBLENDVB which selects bytes based just on the sign bit.
18739 if (Subtarget->hasSSE41()) {
18740 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18741 V0 = DAG.getBitcast(ExtVT, V0);
18742 V1 = DAG.getBitcast(ExtVT, V1);
18743 Sel = DAG.getBitcast(ExtVT, Sel);
18744 return DAG.getBitcast(
18745 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18747 // On pre-SSE41 targets we splat the sign bit - a negative value will
18748 // set all bits of the lanes to true and VSELECT uses that in
18749 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18751 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18752 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18755 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18756 if (Subtarget->hasSSE41()) {
18757 // On SSE41 targets we need to replicate the shift mask in both
18758 // bytes for PBLENDVB.
18761 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18762 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18764 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18767 // r = VSELECT(r, shift(r, 8), a);
18768 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18769 R = SignBitSelect(Amt, M, R);
18772 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18774 // r = VSELECT(r, shift(r, 4), a);
18775 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18776 R = SignBitSelect(Amt, M, R);
18779 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18781 // r = VSELECT(r, shift(r, 2), a);
18782 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18783 R = SignBitSelect(Amt, M, R);
18786 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18788 // return VSELECT(r, shift(r, 1), a);
18789 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18790 R = SignBitSelect(Amt, M, R);
18794 // Decompose 256-bit shifts into smaller 128-bit shifts.
18795 if (VT.is256BitVector()) {
18796 unsigned NumElems = VT.getVectorNumElements();
18797 MVT EltVT = VT.getVectorElementType();
18798 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18800 // Extract the two vectors
18801 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18802 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18804 // Recreate the shift amount vectors
18805 SDValue Amt1, Amt2;
18806 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18807 // Constant shift amount
18808 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18809 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18810 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18812 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18813 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18815 // Variable shift amount
18816 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18817 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18820 // Issue new vector shifts for the smaller types
18821 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18822 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18824 // Concatenate the result back
18825 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18831 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18832 SelectionDAG &DAG) {
18833 MVT VT = Op.getSimpleValueType();
18835 SDValue R = Op.getOperand(0);
18836 SDValue Amt = Op.getOperand(1);
18837 unsigned Opc = Op.getOpcode();
18839 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18840 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18841 assert((Opc == ISD::ROTL) && "Only ROTL supported");
18843 // XOP has 128-bit vector variable + immediate rotates.
18844 // +ve/-ve Amt = rotate left/right.
18846 // Split 256-bit integers.
18847 if (VT.getSizeInBits() == 256)
18848 return Lower256IntArith(Op, DAG);
18850 assert(VT.getSizeInBits() == 128 && "Only rotate 128-bit vectors!");
18852 // Attempt to rotate by immediate.
18853 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18854 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18855 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18856 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18857 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18858 DAG.getConstant(RotateAmt, DL, MVT::i8));
18862 // Use general rotate by variable (per-element).
18863 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18866 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18867 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18868 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18869 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18870 // has only one use.
18871 SDNode *N = Op.getNode();
18872 SDValue LHS = N->getOperand(0);
18873 SDValue RHS = N->getOperand(1);
18874 unsigned BaseOp = 0;
18877 switch (Op.getOpcode()) {
18878 default: llvm_unreachable("Unknown ovf instruction!");
18880 // A subtract of one will be selected as a INC. Note that INC doesn't
18881 // set CF, so we can't do this for UADDO.
18882 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18884 BaseOp = X86ISD::INC;
18885 Cond = X86::COND_O;
18888 BaseOp = X86ISD::ADD;
18889 Cond = X86::COND_O;
18892 BaseOp = X86ISD::ADD;
18893 Cond = X86::COND_B;
18896 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18897 // set CF, so we can't do this for USUBO.
18898 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18900 BaseOp = X86ISD::DEC;
18901 Cond = X86::COND_O;
18904 BaseOp = X86ISD::SUB;
18905 Cond = X86::COND_O;
18908 BaseOp = X86ISD::SUB;
18909 Cond = X86::COND_B;
18912 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18913 Cond = X86::COND_O;
18915 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18916 if (N->getValueType(0) == MVT::i8) {
18917 BaseOp = X86ISD::UMUL8;
18918 Cond = X86::COND_O;
18921 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18923 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18926 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18927 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18928 SDValue(Sum.getNode(), 2));
18930 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18934 // Also sets EFLAGS.
18935 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18936 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18939 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18940 DAG.getConstant(Cond, DL, MVT::i32),
18941 SDValue(Sum.getNode(), 1));
18943 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18946 /// Returns true if the operand type is exactly twice the native width, and
18947 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18948 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18949 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18950 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18951 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18954 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18955 else if (OpWidth == 128)
18956 return Subtarget->hasCmpxchg16b();
18961 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18962 return needsCmpXchgNb(SI->getValueOperand()->getType());
18965 // Note: this turns large loads into lock cmpxchg8b/16b.
18966 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18967 TargetLowering::AtomicExpansionKind
18968 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18969 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18970 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18971 : AtomicExpansionKind::None;
18974 TargetLowering::AtomicExpansionKind
18975 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18976 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18977 Type *MemType = AI->getType();
18979 // If the operand is too big, we must see if cmpxchg8/16b is available
18980 // and default to library calls otherwise.
18981 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18982 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18983 : AtomicExpansionKind::None;
18986 AtomicRMWInst::BinOp Op = AI->getOperation();
18989 llvm_unreachable("Unknown atomic operation");
18990 case AtomicRMWInst::Xchg:
18991 case AtomicRMWInst::Add:
18992 case AtomicRMWInst::Sub:
18993 // It's better to use xadd, xsub or xchg for these in all cases.
18994 return AtomicExpansionKind::None;
18995 case AtomicRMWInst::Or:
18996 case AtomicRMWInst::And:
18997 case AtomicRMWInst::Xor:
18998 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18999 // prefix to a normal instruction for these operations.
19000 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19001 : AtomicExpansionKind::None;
19002 case AtomicRMWInst::Nand:
19003 case AtomicRMWInst::Max:
19004 case AtomicRMWInst::Min:
19005 case AtomicRMWInst::UMax:
19006 case AtomicRMWInst::UMin:
19007 // These always require a non-trivial set of data operations on x86. We must
19008 // use a cmpxchg loop.
19009 return AtomicExpansionKind::CmpXChg;
19013 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19014 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19015 // no-sse2). There isn't any reason to disable it if the target processor
19017 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19021 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19022 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19023 Type *MemType = AI->getType();
19024 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19025 // there is no benefit in turning such RMWs into loads, and it is actually
19026 // harmful as it introduces a mfence.
19027 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19030 auto Builder = IRBuilder<>(AI);
19031 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19032 auto SynchScope = AI->getSynchScope();
19033 // We must restrict the ordering to avoid generating loads with Release or
19034 // ReleaseAcquire orderings.
19035 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19036 auto Ptr = AI->getPointerOperand();
19038 // Before the load we need a fence. Here is an example lifted from
19039 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19042 // x.store(1, relaxed);
19043 // r1 = y.fetch_add(0, release);
19045 // y.fetch_add(42, acquire);
19046 // r2 = x.load(relaxed);
19047 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19048 // lowered to just a load without a fence. A mfence flushes the store buffer,
19049 // making the optimization clearly correct.
19050 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19051 // otherwise, we might be able to be more aggressive on relaxed idempotent
19052 // rmw. In practice, they do not look useful, so we don't try to be
19053 // especially clever.
19054 if (SynchScope == SingleThread)
19055 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19056 // the IR level, so we must wrap it in an intrinsic.
19059 if (!hasMFENCE(*Subtarget))
19060 // FIXME: it might make sense to use a locked operation here but on a
19061 // different cache-line to prevent cache-line bouncing. In practice it
19062 // is probably a small win, and x86 processors without mfence are rare
19063 // enough that we do not bother.
19067 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19068 Builder.CreateCall(MFence, {});
19070 // Finally we can emit the atomic load.
19071 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19072 AI->getType()->getPrimitiveSizeInBits());
19073 Loaded->setAtomic(Order, SynchScope);
19074 AI->replaceAllUsesWith(Loaded);
19075 AI->eraseFromParent();
19079 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19080 SelectionDAG &DAG) {
19082 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19083 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19084 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19085 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19087 // The only fence that needs an instruction is a sequentially-consistent
19088 // cross-thread fence.
19089 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19090 if (hasMFENCE(*Subtarget))
19091 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19093 SDValue Chain = Op.getOperand(0);
19094 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19096 DAG.getRegister(X86::ESP, MVT::i32), // Base
19097 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19098 DAG.getRegister(0, MVT::i32), // Index
19099 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19100 DAG.getRegister(0, MVT::i32), // Segment.
19104 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19105 return SDValue(Res, 0);
19108 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19109 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19112 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19113 SelectionDAG &DAG) {
19114 MVT T = Op.getSimpleValueType();
19118 switch(T.SimpleTy) {
19119 default: llvm_unreachable("Invalid value type!");
19120 case MVT::i8: Reg = X86::AL; size = 1; break;
19121 case MVT::i16: Reg = X86::AX; size = 2; break;
19122 case MVT::i32: Reg = X86::EAX; size = 4; break;
19124 assert(Subtarget->is64Bit() && "Node not type legal!");
19125 Reg = X86::RAX; size = 8;
19128 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19129 Op.getOperand(2), SDValue());
19130 SDValue Ops[] = { cpIn.getValue(0),
19133 DAG.getTargetConstant(size, DL, MVT::i8),
19134 cpIn.getValue(1) };
19135 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19136 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19137 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19141 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19142 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19143 MVT::i32, cpOut.getValue(2));
19144 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19145 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19148 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19149 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19150 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19154 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19155 SelectionDAG &DAG) {
19156 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19157 MVT DstVT = Op.getSimpleValueType();
19159 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19160 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19161 if (DstVT != MVT::f64)
19162 // This conversion needs to be expanded.
19165 SDValue InVec = Op->getOperand(0);
19167 unsigned NumElts = SrcVT.getVectorNumElements();
19168 EVT SVT = SrcVT.getVectorElementType();
19170 // Widen the vector in input in the case of MVT::v2i32.
19171 // Example: from MVT::v2i32 to MVT::v4i32.
19172 SmallVector<SDValue, 16> Elts;
19173 for (unsigned i = 0, e = NumElts; i != e; ++i)
19174 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19175 DAG.getIntPtrConstant(i, dl)));
19177 // Explicitly mark the extra elements as Undef.
19178 Elts.append(NumElts, DAG.getUNDEF(SVT));
19180 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19181 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19182 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19183 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19184 DAG.getIntPtrConstant(0, dl));
19187 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19188 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19189 assert((DstVT == MVT::i64 ||
19190 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19191 "Unexpected custom BITCAST");
19192 // i64 <=> MMX conversions are Legal.
19193 if (SrcVT==MVT::i64 && DstVT.isVector())
19195 if (DstVT==MVT::i64 && SrcVT.isVector())
19197 // MMX <=> MMX conversions are Legal.
19198 if (SrcVT.isVector() && DstVT.isVector())
19200 // All other conversions need to be expanded.
19204 /// Compute the horizontal sum of bytes in V for the elements of VT.
19206 /// Requires V to be a byte vector and VT to be an integer vector type with
19207 /// wider elements than V's type. The width of the elements of VT determines
19208 /// how many bytes of V are summed horizontally to produce each element of the
19210 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19211 const X86Subtarget *Subtarget,
19212 SelectionDAG &DAG) {
19214 MVT ByteVecVT = V.getSimpleValueType();
19215 MVT EltVT = VT.getVectorElementType();
19216 int NumElts = VT.getVectorNumElements();
19217 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19218 "Expected value to have byte element type.");
19219 assert(EltVT != MVT::i8 &&
19220 "Horizontal byte sum only makes sense for wider elements!");
19221 unsigned VecSize = VT.getSizeInBits();
19222 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19224 // PSADBW instruction horizontally add all bytes and leave the result in i64
19225 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19226 if (EltVT == MVT::i64) {
19227 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19228 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19229 return DAG.getBitcast(VT, V);
19232 if (EltVT == MVT::i32) {
19233 // We unpack the low half and high half into i32s interleaved with zeros so
19234 // that we can use PSADBW to horizontally sum them. The most useful part of
19235 // this is that it lines up the results of two PSADBW instructions to be
19236 // two v2i64 vectors which concatenated are the 4 population counts. We can
19237 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19238 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19239 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19240 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19242 // Do the horizontal sums into two v2i64s.
19243 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19244 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19245 DAG.getBitcast(ByteVecVT, Low), Zeros);
19246 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19247 DAG.getBitcast(ByteVecVT, High), Zeros);
19249 // Merge them together.
19250 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19251 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19252 DAG.getBitcast(ShortVecVT, Low),
19253 DAG.getBitcast(ShortVecVT, High));
19255 return DAG.getBitcast(VT, V);
19258 // The only element type left is i16.
19259 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19261 // To obtain pop count for each i16 element starting from the pop count for
19262 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19263 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19264 // directly supported.
19265 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19266 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19267 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19268 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19269 DAG.getBitcast(ByteVecVT, V));
19270 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19273 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19274 const X86Subtarget *Subtarget,
19275 SelectionDAG &DAG) {
19276 MVT VT = Op.getSimpleValueType();
19277 MVT EltVT = VT.getVectorElementType();
19278 unsigned VecSize = VT.getSizeInBits();
19280 // Implement a lookup table in register by using an algorithm based on:
19281 // http://wm.ite.pl/articles/sse-popcount.html
19283 // The general idea is that every lower byte nibble in the input vector is an
19284 // index into a in-register pre-computed pop count table. We then split up the
19285 // input vector in two new ones: (1) a vector with only the shifted-right
19286 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19287 // masked out higher ones) for each byte. PSHUB is used separately with both
19288 // to index the in-register table. Next, both are added and the result is a
19289 // i8 vector where each element contains the pop count for input byte.
19291 // To obtain the pop count for elements != i8, we follow up with the same
19292 // approach and use additional tricks as described below.
19294 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19295 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19296 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19297 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19299 int NumByteElts = VecSize / 8;
19300 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19301 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19302 SmallVector<SDValue, 16> LUTVec;
19303 for (int i = 0; i < NumByteElts; ++i)
19304 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19305 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19306 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19307 DAG.getConstant(0x0F, DL, MVT::i8));
19308 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19311 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19312 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19313 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19316 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19318 // The input vector is used as the shuffle mask that index elements into the
19319 // LUT. After counting low and high nibbles, add the vector to obtain the
19320 // final pop count per i8 element.
19321 SDValue HighPopCnt =
19322 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19323 SDValue LowPopCnt =
19324 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19325 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19327 if (EltVT == MVT::i8)
19330 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19333 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19334 const X86Subtarget *Subtarget,
19335 SelectionDAG &DAG) {
19336 MVT VT = Op.getSimpleValueType();
19337 assert(VT.is128BitVector() &&
19338 "Only 128-bit vector bitmath lowering supported.");
19340 int VecSize = VT.getSizeInBits();
19341 MVT EltVT = VT.getVectorElementType();
19342 int Len = EltVT.getSizeInBits();
19344 // This is the vectorized version of the "best" algorithm from
19345 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19346 // with a minor tweak to use a series of adds + shifts instead of vector
19347 // multiplications. Implemented for all integer vector types. We only use
19348 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19349 // much faster, even faster than using native popcnt instructions.
19351 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19352 MVT VT = V.getSimpleValueType();
19353 SmallVector<SDValue, 32> Shifters(
19354 VT.getVectorNumElements(),
19355 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19356 return DAG.getNode(OpCode, DL, VT, V,
19357 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19359 auto GetMask = [&](SDValue V, APInt Mask) {
19360 MVT VT = V.getSimpleValueType();
19361 SmallVector<SDValue, 32> Masks(
19362 VT.getVectorNumElements(),
19363 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19364 return DAG.getNode(ISD::AND, DL, VT, V,
19365 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19368 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19369 // x86, so set the SRL type to have elements at least i16 wide. This is
19370 // correct because all of our SRLs are followed immediately by a mask anyways
19371 // that handles any bits that sneak into the high bits of the byte elements.
19372 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19376 // v = v - ((v >> 1) & 0x55555555...)
19378 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19379 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19380 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19382 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19383 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19384 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19385 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19386 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19388 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19389 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19390 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19391 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19393 // At this point, V contains the byte-wise population count, and we are
19394 // merely doing a horizontal sum if necessary to get the wider element
19396 if (EltVT == MVT::i8)
19399 return LowerHorizontalByteSum(
19400 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19404 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19405 SelectionDAG &DAG) {
19406 MVT VT = Op.getSimpleValueType();
19407 // FIXME: Need to add AVX-512 support here!
19408 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19409 "Unknown CTPOP type to handle");
19410 SDLoc DL(Op.getNode());
19411 SDValue Op0 = Op.getOperand(0);
19413 if (!Subtarget->hasSSSE3()) {
19414 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19415 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19416 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19419 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19420 unsigned NumElems = VT.getVectorNumElements();
19422 // Extract each 128-bit vector, compute pop count and concat the result.
19423 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19424 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19426 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19427 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19428 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19431 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19434 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19435 SelectionDAG &DAG) {
19436 assert(Op.getValueType().isVector() &&
19437 "We only do custom lowering for vector population count.");
19438 return LowerVectorCTPOP(Op, Subtarget, DAG);
19441 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19442 SDNode *Node = Op.getNode();
19444 EVT T = Node->getValueType(0);
19445 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19446 DAG.getConstant(0, dl, T), Node->getOperand(2));
19447 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19448 cast<AtomicSDNode>(Node)->getMemoryVT(),
19449 Node->getOperand(0),
19450 Node->getOperand(1), negOp,
19451 cast<AtomicSDNode>(Node)->getMemOperand(),
19452 cast<AtomicSDNode>(Node)->getOrdering(),
19453 cast<AtomicSDNode>(Node)->getSynchScope());
19456 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19457 SDNode *Node = Op.getNode();
19459 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19461 // Convert seq_cst store -> xchg
19462 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19463 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19464 // (The only way to get a 16-byte store is cmpxchg16b)
19465 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19466 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19467 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19468 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19469 cast<AtomicSDNode>(Node)->getMemoryVT(),
19470 Node->getOperand(0),
19471 Node->getOperand(1), Node->getOperand(2),
19472 cast<AtomicSDNode>(Node)->getMemOperand(),
19473 cast<AtomicSDNode>(Node)->getOrdering(),
19474 cast<AtomicSDNode>(Node)->getSynchScope());
19475 return Swap.getValue(1);
19477 // Other atomic stores have a simple pattern.
19481 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19482 EVT VT = Op.getNode()->getSimpleValueType(0);
19484 // Let legalize expand this if it isn't a legal type yet.
19485 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19488 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19491 bool ExtraOp = false;
19492 switch (Op.getOpcode()) {
19493 default: llvm_unreachable("Invalid code");
19494 case ISD::ADDC: Opc = X86ISD::ADD; break;
19495 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19496 case ISD::SUBC: Opc = X86ISD::SUB; break;
19497 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19501 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19503 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19504 Op.getOperand(1), Op.getOperand(2));
19507 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19508 SelectionDAG &DAG) {
19509 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19511 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19512 // which returns the values as { float, float } (in XMM0) or
19513 // { double, double } (which is returned in XMM0, XMM1).
19515 SDValue Arg = Op.getOperand(0);
19516 EVT ArgVT = Arg.getValueType();
19517 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19519 TargetLowering::ArgListTy Args;
19520 TargetLowering::ArgListEntry Entry;
19524 Entry.isSExt = false;
19525 Entry.isZExt = false;
19526 Args.push_back(Entry);
19528 bool isF64 = ArgVT == MVT::f64;
19529 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19530 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19531 // the results are returned via SRet in memory.
19532 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19533 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19535 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19537 Type *RetTy = isF64
19538 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19539 : (Type*)VectorType::get(ArgTy, 4);
19541 TargetLowering::CallLoweringInfo CLI(DAG);
19542 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19543 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19545 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19548 // Returned in xmm0 and xmm1.
19549 return CallResult.first;
19551 // Returned in bits 0:31 and 32:64 xmm0.
19552 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19553 CallResult.first, DAG.getIntPtrConstant(0, dl));
19554 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19555 CallResult.first, DAG.getIntPtrConstant(1, dl));
19556 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19557 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19560 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19561 SelectionDAG &DAG) {
19562 assert(Subtarget->hasAVX512() &&
19563 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19565 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19566 EVT VT = N->getValue().getValueType();
19567 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19570 // X86 scatter kills mask register, so its type should be added to
19571 // the list of return values
19572 if (N->getNumValues() == 1) {
19573 SDValue Index = N->getIndex();
19574 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19575 !Index.getValueType().is512BitVector())
19576 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19578 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19579 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19580 N->getOperand(3), Index };
19582 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19583 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19584 return SDValue(NewScatter.getNode(), 0);
19589 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19590 SelectionDAG &DAG) {
19591 assert(Subtarget->hasAVX512() &&
19592 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19594 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19595 EVT VT = Op.getValueType();
19596 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19599 SDValue Index = N->getIndex();
19600 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19601 !Index.getValueType().is512BitVector()) {
19602 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19603 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19604 N->getOperand(3), Index };
19605 DAG.UpdateNodeOperands(N, Ops);
19610 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19611 SelectionDAG &DAG) const {
19612 // TODO: Eventually, the lowering of these nodes should be informed by or
19613 // deferred to the GC strategy for the function in which they appear. For
19614 // now, however, they must be lowered to something. Since they are logically
19615 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19616 // require special handling for these nodes), lower them as literal NOOPs for
19618 SmallVector<SDValue, 2> Ops;
19620 Ops.push_back(Op.getOperand(0));
19621 if (Op->getGluedNode())
19622 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19625 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19626 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19631 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19632 SelectionDAG &DAG) const {
19633 // TODO: Eventually, the lowering of these nodes should be informed by or
19634 // deferred to the GC strategy for the function in which they appear. For
19635 // now, however, they must be lowered to something. Since they are logically
19636 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19637 // require special handling for these nodes), lower them as literal NOOPs for
19639 SmallVector<SDValue, 2> Ops;
19641 Ops.push_back(Op.getOperand(0));
19642 if (Op->getGluedNode())
19643 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19646 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19647 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19652 /// LowerOperation - Provide custom lowering hooks for some operations.
19654 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19655 switch (Op.getOpcode()) {
19656 default: llvm_unreachable("Should not custom lower this!");
19657 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19658 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19659 return LowerCMP_SWAP(Op, Subtarget, DAG);
19660 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19661 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19662 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19663 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19664 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19665 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19666 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19667 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19668 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19669 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19670 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19671 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19672 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19673 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19674 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19675 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19676 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19677 case ISD::SHL_PARTS:
19678 case ISD::SRA_PARTS:
19679 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19680 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19681 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19682 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19683 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19684 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19685 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19686 case ISD::SIGN_EXTEND_VECTOR_INREG:
19687 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19688 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19689 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19690 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19691 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19693 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19694 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19695 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19696 case ISD::SETCC: return LowerSETCC(Op, DAG);
19697 case ISD::SELECT: return LowerSELECT(Op, DAG);
19698 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19699 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19700 case ISD::VASTART: return LowerVASTART(Op, DAG);
19701 case ISD::VAARG: return LowerVAARG(Op, DAG);
19702 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19703 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19704 case ISD::INTRINSIC_VOID:
19705 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19706 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19707 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19708 case ISD::FRAME_TO_ARGS_OFFSET:
19709 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19710 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19711 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19712 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19713 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19714 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19715 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19716 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19717 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19718 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19720 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19721 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19722 case ISD::UMUL_LOHI:
19723 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19724 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19727 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19733 case ISD::UMULO: return LowerXALUO(Op, DAG);
19734 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19735 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19739 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19740 case ISD::ADD: return LowerADD(Op, DAG);
19741 case ISD::SUB: return LowerSUB(Op, DAG);
19745 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19746 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19747 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19748 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19749 case ISD::GC_TRANSITION_START:
19750 return LowerGC_TRANSITION_START(Op, DAG);
19751 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19755 /// ReplaceNodeResults - Replace a node with an illegal result type
19756 /// with a new node built out of custom code.
19757 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19758 SmallVectorImpl<SDValue>&Results,
19759 SelectionDAG &DAG) const {
19761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19762 switch (N->getOpcode()) {
19764 llvm_unreachable("Do not know how to custom type legalize this operation!");
19765 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19766 case X86ISD::FMINC:
19768 case X86ISD::FMAXC:
19769 case X86ISD::FMAX: {
19770 EVT VT = N->getValueType(0);
19771 if (VT != MVT::v2f32)
19772 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19773 SDValue UNDEF = DAG.getUNDEF(VT);
19774 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19775 N->getOperand(0), UNDEF);
19776 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19777 N->getOperand(1), UNDEF);
19778 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19781 case ISD::SIGN_EXTEND_INREG:
19786 // We don't want to expand or promote these.
19793 case ISD::UDIVREM: {
19794 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19795 Results.push_back(V);
19798 case ISD::FP_TO_SINT:
19799 case ISD::FP_TO_UINT: {
19800 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19802 std::pair<SDValue,SDValue> Vals =
19803 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19804 SDValue FIST = Vals.first, StackSlot = Vals.second;
19805 if (FIST.getNode()) {
19806 EVT VT = N->getValueType(0);
19807 // Return a load from the stack slot.
19808 if (StackSlot.getNode())
19809 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19810 MachinePointerInfo(),
19811 false, false, false, 0));
19813 Results.push_back(FIST);
19817 case ISD::UINT_TO_FP: {
19818 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19819 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19820 N->getValueType(0) != MVT::v2f32)
19822 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19824 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19826 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19827 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19828 DAG.getBitcast(MVT::v2i64, VBias));
19829 Or = DAG.getBitcast(MVT::v2f64, Or);
19830 // TODO: Are there any fast-math-flags to propagate here?
19831 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19832 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19835 case ISD::FP_ROUND: {
19836 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19838 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19839 Results.push_back(V);
19842 case ISD::FP_EXTEND: {
19843 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19844 // No other ValueType for FP_EXTEND should reach this point.
19845 assert(N->getValueType(0) == MVT::v2f32 &&
19846 "Do not know how to legalize this Node");
19849 case ISD::INTRINSIC_W_CHAIN: {
19850 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19852 default : llvm_unreachable("Do not know how to custom type "
19853 "legalize this intrinsic operation!");
19854 case Intrinsic::x86_rdtsc:
19855 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19857 case Intrinsic::x86_rdtscp:
19858 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19860 case Intrinsic::x86_rdpmc:
19861 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19864 case ISD::READCYCLECOUNTER: {
19865 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19868 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19869 EVT T = N->getValueType(0);
19870 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19871 bool Regs64bit = T == MVT::i128;
19872 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19873 SDValue cpInL, cpInH;
19874 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19875 DAG.getConstant(0, dl, HalfT));
19876 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19877 DAG.getConstant(1, dl, HalfT));
19878 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19879 Regs64bit ? X86::RAX : X86::EAX,
19881 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19882 Regs64bit ? X86::RDX : X86::EDX,
19883 cpInH, cpInL.getValue(1));
19884 SDValue swapInL, swapInH;
19885 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19886 DAG.getConstant(0, dl, HalfT));
19887 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19888 DAG.getConstant(1, dl, HalfT));
19889 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19890 Regs64bit ? X86::RBX : X86::EBX,
19891 swapInL, cpInH.getValue(1));
19892 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19893 Regs64bit ? X86::RCX : X86::ECX,
19894 swapInH, swapInL.getValue(1));
19895 SDValue Ops[] = { swapInH.getValue(0),
19897 swapInH.getValue(1) };
19898 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19899 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19900 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19901 X86ISD::LCMPXCHG8_DAG;
19902 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19903 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19904 Regs64bit ? X86::RAX : X86::EAX,
19905 HalfT, Result.getValue(1));
19906 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19907 Regs64bit ? X86::RDX : X86::EDX,
19908 HalfT, cpOutL.getValue(2));
19909 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19911 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19912 MVT::i32, cpOutH.getValue(2));
19914 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19915 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19916 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19918 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19919 Results.push_back(Success);
19920 Results.push_back(EFLAGS.getValue(1));
19923 case ISD::ATOMIC_SWAP:
19924 case ISD::ATOMIC_LOAD_ADD:
19925 case ISD::ATOMIC_LOAD_SUB:
19926 case ISD::ATOMIC_LOAD_AND:
19927 case ISD::ATOMIC_LOAD_OR:
19928 case ISD::ATOMIC_LOAD_XOR:
19929 case ISD::ATOMIC_LOAD_NAND:
19930 case ISD::ATOMIC_LOAD_MIN:
19931 case ISD::ATOMIC_LOAD_MAX:
19932 case ISD::ATOMIC_LOAD_UMIN:
19933 case ISD::ATOMIC_LOAD_UMAX:
19934 case ISD::ATOMIC_LOAD: {
19935 // Delegate to generic TypeLegalization. Situations we can really handle
19936 // should have already been dealt with by AtomicExpandPass.cpp.
19939 case ISD::BITCAST: {
19940 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19941 EVT DstVT = N->getValueType(0);
19942 EVT SrcVT = N->getOperand(0)->getValueType(0);
19944 if (SrcVT != MVT::f64 ||
19945 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19948 unsigned NumElts = DstVT.getVectorNumElements();
19949 EVT SVT = DstVT.getVectorElementType();
19950 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19951 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19952 MVT::v2f64, N->getOperand(0));
19953 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19955 if (ExperimentalVectorWideningLegalization) {
19956 // If we are legalizing vectors by widening, we already have the desired
19957 // legal vector type, just return it.
19958 Results.push_back(ToVecInt);
19962 SmallVector<SDValue, 8> Elts;
19963 for (unsigned i = 0, e = NumElts; i != e; ++i)
19964 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19965 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19967 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19972 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19973 switch ((X86ISD::NodeType)Opcode) {
19974 case X86ISD::FIRST_NUMBER: break;
19975 case X86ISD::BSF: return "X86ISD::BSF";
19976 case X86ISD::BSR: return "X86ISD::BSR";
19977 case X86ISD::SHLD: return "X86ISD::SHLD";
19978 case X86ISD::SHRD: return "X86ISD::SHRD";
19979 case X86ISD::FAND: return "X86ISD::FAND";
19980 case X86ISD::FANDN: return "X86ISD::FANDN";
19981 case X86ISD::FOR: return "X86ISD::FOR";
19982 case X86ISD::FXOR: return "X86ISD::FXOR";
19983 case X86ISD::FILD: return "X86ISD::FILD";
19984 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19985 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19986 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19987 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19988 case X86ISD::FLD: return "X86ISD::FLD";
19989 case X86ISD::FST: return "X86ISD::FST";
19990 case X86ISD::CALL: return "X86ISD::CALL";
19991 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19992 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19993 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19994 case X86ISD::BT: return "X86ISD::BT";
19995 case X86ISD::CMP: return "X86ISD::CMP";
19996 case X86ISD::COMI: return "X86ISD::COMI";
19997 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19998 case X86ISD::CMPM: return "X86ISD::CMPM";
19999 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20000 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20001 case X86ISD::SETCC: return "X86ISD::SETCC";
20002 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20003 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20004 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20005 case X86ISD::CMOV: return "X86ISD::CMOV";
20006 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20007 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20008 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20009 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20010 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20011 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20012 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20013 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20014 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20015 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20016 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20017 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20018 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20019 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20020 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20021 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20022 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20023 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20024 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20025 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20026 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20027 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20028 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20029 case X86ISD::HADD: return "X86ISD::HADD";
20030 case X86ISD::HSUB: return "X86ISD::HSUB";
20031 case X86ISD::FHADD: return "X86ISD::FHADD";
20032 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20033 case X86ISD::ABS: return "X86ISD::ABS";
20034 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20035 case X86ISD::FMAX: return "X86ISD::FMAX";
20036 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20037 case X86ISD::FMIN: return "X86ISD::FMIN";
20038 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20039 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20040 case X86ISD::FMINC: return "X86ISD::FMINC";
20041 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20042 case X86ISD::FRCP: return "X86ISD::FRCP";
20043 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20044 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20045 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20046 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20047 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20048 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20049 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20050 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20051 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20052 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20053 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20054 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20055 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20056 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20057 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20058 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20059 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20060 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20061 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20062 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20063 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20064 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20065 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20066 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20067 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20068 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20069 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20070 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20071 case X86ISD::VSHL: return "X86ISD::VSHL";
20072 case X86ISD::VSRL: return "X86ISD::VSRL";
20073 case X86ISD::VSRA: return "X86ISD::VSRA";
20074 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20075 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20076 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20077 case X86ISD::CMPP: return "X86ISD::CMPP";
20078 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20079 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20080 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20081 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20082 case X86ISD::ADD: return "X86ISD::ADD";
20083 case X86ISD::SUB: return "X86ISD::SUB";
20084 case X86ISD::ADC: return "X86ISD::ADC";
20085 case X86ISD::SBB: return "X86ISD::SBB";
20086 case X86ISD::SMUL: return "X86ISD::SMUL";
20087 case X86ISD::UMUL: return "X86ISD::UMUL";
20088 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20089 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20090 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20091 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20092 case X86ISD::INC: return "X86ISD::INC";
20093 case X86ISD::DEC: return "X86ISD::DEC";
20094 case X86ISD::OR: return "X86ISD::OR";
20095 case X86ISD::XOR: return "X86ISD::XOR";
20096 case X86ISD::AND: return "X86ISD::AND";
20097 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20098 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20099 case X86ISD::PTEST: return "X86ISD::PTEST";
20100 case X86ISD::TESTP: return "X86ISD::TESTP";
20101 case X86ISD::TESTM: return "X86ISD::TESTM";
20102 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20103 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20104 case X86ISD::KTEST: return "X86ISD::KTEST";
20105 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20106 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20107 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20108 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20109 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20110 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20111 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20112 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20113 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20114 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20115 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20116 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20117 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20118 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20119 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20120 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20121 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20122 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20123 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20124 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20125 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20126 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20127 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20128 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20129 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20130 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20131 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20132 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20133 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20134 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20135 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20136 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20137 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20138 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20139 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20140 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20141 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20142 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20143 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20144 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20145 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20146 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20147 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20148 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20149 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20150 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20151 case X86ISD::SAHF: return "X86ISD::SAHF";
20152 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20153 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20154 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20155 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20156 case X86ISD::VPROT: return "X86ISD::VPROT";
20157 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20158 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20159 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20160 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20161 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20162 case X86ISD::FMADD: return "X86ISD::FMADD";
20163 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20164 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20165 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20166 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20167 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20168 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20169 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20170 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20171 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20172 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20173 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20174 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20175 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20176 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20177 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20178 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20179 case X86ISD::XTEST: return "X86ISD::XTEST";
20180 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20181 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20182 case X86ISD::SELECT: return "X86ISD::SELECT";
20183 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20184 case X86ISD::RCP28: return "X86ISD::RCP28";
20185 case X86ISD::EXP2: return "X86ISD::EXP2";
20186 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20187 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20188 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20189 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20190 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20191 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20192 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20193 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20194 case X86ISD::ADDS: return "X86ISD::ADDS";
20195 case X86ISD::SUBS: return "X86ISD::SUBS";
20196 case X86ISD::AVG: return "X86ISD::AVG";
20197 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20198 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20199 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20200 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20201 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20202 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20207 // isLegalAddressingMode - Return true if the addressing mode represented
20208 // by AM is legal for this target, for a load/store of the specified type.
20209 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20210 const AddrMode &AM, Type *Ty,
20211 unsigned AS) const {
20212 // X86 supports extremely general addressing modes.
20213 CodeModel::Model M = getTargetMachine().getCodeModel();
20214 Reloc::Model R = getTargetMachine().getRelocationModel();
20216 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20217 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20222 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20224 // If a reference to this global requires an extra load, we can't fold it.
20225 if (isGlobalStubReference(GVFlags))
20228 // If BaseGV requires a register for the PIC base, we cannot also have a
20229 // BaseReg specified.
20230 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20233 // If lower 4G is not available, then we must use rip-relative addressing.
20234 if ((M != CodeModel::Small || R != Reloc::Static) &&
20235 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20239 switch (AM.Scale) {
20245 // These scales always work.
20250 // These scales are formed with basereg+scalereg. Only accept if there is
20255 default: // Other stuff never works.
20262 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20263 unsigned Bits = Ty->getScalarSizeInBits();
20265 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20266 // particularly cheaper than those without.
20270 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20271 // variable shifts just as cheap as scalar ones.
20272 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20275 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20276 // fully general vector.
20280 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20281 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20283 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20284 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20285 return NumBits1 > NumBits2;
20288 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20289 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20292 if (!isTypeLegal(EVT::getEVT(Ty1)))
20295 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20297 // Assuming the caller doesn't have a zeroext or signext return parameter,
20298 // truncation all the way down to i1 is valid.
20302 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20303 return isInt<32>(Imm);
20306 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20307 // Can also use sub to handle negated immediates.
20308 return isInt<32>(Imm);
20311 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20312 if (!VT1.isInteger() || !VT2.isInteger())
20314 unsigned NumBits1 = VT1.getSizeInBits();
20315 unsigned NumBits2 = VT2.getSizeInBits();
20316 return NumBits1 > NumBits2;
20319 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20320 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20321 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20324 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20325 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20326 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20329 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20330 EVT VT1 = Val.getValueType();
20331 if (isZExtFree(VT1, VT2))
20334 if (Val.getOpcode() != ISD::LOAD)
20337 if (!VT1.isSimple() || !VT1.isInteger() ||
20338 !VT2.isSimple() || !VT2.isInteger())
20341 switch (VT1.getSimpleVT().SimpleTy) {
20346 // X86 has 8, 16, and 32-bit zero-extending loads.
20353 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20356 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20357 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20360 VT = VT.getScalarType();
20362 if (!VT.isSimple())
20365 switch (VT.getSimpleVT().SimpleTy) {
20376 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20377 // i16 instructions are longer (0x66 prefix) and potentially slower.
20378 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20381 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20382 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20383 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20384 /// are assumed to be legal.
20386 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20388 if (!VT.isSimple())
20391 // Not for i1 vectors
20392 if (VT.getScalarType() == MVT::i1)
20395 // Very little shuffling can be done for 64-bit vectors right now.
20396 if (VT.getSizeInBits() == 64)
20399 // We only care that the types being shuffled are legal. The lowering can
20400 // handle any possible shuffle mask that results.
20401 return isTypeLegal(VT.getSimpleVT());
20405 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20407 // Just delegate to the generic legality, clear masks aren't special.
20408 return isShuffleMaskLegal(Mask, VT);
20411 //===----------------------------------------------------------------------===//
20412 // X86 Scheduler Hooks
20413 //===----------------------------------------------------------------------===//
20415 /// Utility function to emit xbegin specifying the start of an RTM region.
20416 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20417 const TargetInstrInfo *TII) {
20418 DebugLoc DL = MI->getDebugLoc();
20420 const BasicBlock *BB = MBB->getBasicBlock();
20421 MachineFunction::iterator I = ++MBB->getIterator();
20423 // For the v = xbegin(), we generate
20434 MachineBasicBlock *thisMBB = MBB;
20435 MachineFunction *MF = MBB->getParent();
20436 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20437 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20438 MF->insert(I, mainMBB);
20439 MF->insert(I, sinkMBB);
20441 // Transfer the remainder of BB and its successor edges to sinkMBB.
20442 sinkMBB->splice(sinkMBB->begin(), MBB,
20443 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20444 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20448 // # fallthrough to mainMBB
20449 // # abortion to sinkMBB
20450 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20451 thisMBB->addSuccessor(mainMBB);
20452 thisMBB->addSuccessor(sinkMBB);
20456 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20457 mainMBB->addSuccessor(sinkMBB);
20460 // EAX is live into the sinkMBB
20461 sinkMBB->addLiveIn(X86::EAX);
20462 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20463 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20466 MI->eraseFromParent();
20470 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20471 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20472 // in the .td file.
20473 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20474 const TargetInstrInfo *TII) {
20476 switch (MI->getOpcode()) {
20477 default: llvm_unreachable("illegal opcode!");
20478 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20479 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20480 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20481 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20482 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20483 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20484 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20485 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20488 DebugLoc dl = MI->getDebugLoc();
20489 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20491 unsigned NumArgs = MI->getNumOperands();
20492 for (unsigned i = 1; i < NumArgs; ++i) {
20493 MachineOperand &Op = MI->getOperand(i);
20494 if (!(Op.isReg() && Op.isImplicit()))
20495 MIB.addOperand(Op);
20497 if (MI->hasOneMemOperand())
20498 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20500 BuildMI(*BB, MI, dl,
20501 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20502 .addReg(X86::XMM0);
20504 MI->eraseFromParent();
20508 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20509 // defs in an instruction pattern
20510 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20511 const TargetInstrInfo *TII) {
20513 switch (MI->getOpcode()) {
20514 default: llvm_unreachable("illegal opcode!");
20515 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20516 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20517 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20518 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20519 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20520 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20521 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20522 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20525 DebugLoc dl = MI->getDebugLoc();
20526 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20528 unsigned NumArgs = MI->getNumOperands(); // remove the results
20529 for (unsigned i = 1; i < NumArgs; ++i) {
20530 MachineOperand &Op = MI->getOperand(i);
20531 if (!(Op.isReg() && Op.isImplicit()))
20532 MIB.addOperand(Op);
20534 if (MI->hasOneMemOperand())
20535 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20537 BuildMI(*BB, MI, dl,
20538 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20541 MI->eraseFromParent();
20545 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20546 const X86Subtarget *Subtarget) {
20547 DebugLoc dl = MI->getDebugLoc();
20548 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20549 // Address into RAX/EAX, other two args into ECX, EDX.
20550 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20551 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20552 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20553 for (int i = 0; i < X86::AddrNumOperands; ++i)
20554 MIB.addOperand(MI->getOperand(i));
20556 unsigned ValOps = X86::AddrNumOperands;
20557 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20558 .addReg(MI->getOperand(ValOps).getReg());
20559 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20560 .addReg(MI->getOperand(ValOps+1).getReg());
20562 // The instruction doesn't actually take any operands though.
20563 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20565 MI->eraseFromParent(); // The pseudo is gone now.
20569 MachineBasicBlock *
20570 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20571 MachineBasicBlock *MBB) const {
20572 // Emit va_arg instruction on X86-64.
20574 // Operands to this pseudo-instruction:
20575 // 0 ) Output : destination address (reg)
20576 // 1-5) Input : va_list address (addr, i64mem)
20577 // 6 ) ArgSize : Size (in bytes) of vararg type
20578 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20579 // 8 ) Align : Alignment of type
20580 // 9 ) EFLAGS (implicit-def)
20582 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20583 static_assert(X86::AddrNumOperands == 5,
20584 "VAARG_64 assumes 5 address operands");
20586 unsigned DestReg = MI->getOperand(0).getReg();
20587 MachineOperand &Base = MI->getOperand(1);
20588 MachineOperand &Scale = MI->getOperand(2);
20589 MachineOperand &Index = MI->getOperand(3);
20590 MachineOperand &Disp = MI->getOperand(4);
20591 MachineOperand &Segment = MI->getOperand(5);
20592 unsigned ArgSize = MI->getOperand(6).getImm();
20593 unsigned ArgMode = MI->getOperand(7).getImm();
20594 unsigned Align = MI->getOperand(8).getImm();
20596 // Memory Reference
20597 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20598 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20599 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20601 // Machine Information
20602 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20603 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20604 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20605 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20606 DebugLoc DL = MI->getDebugLoc();
20608 // struct va_list {
20611 // i64 overflow_area (address)
20612 // i64 reg_save_area (address)
20614 // sizeof(va_list) = 24
20615 // alignment(va_list) = 8
20617 unsigned TotalNumIntRegs = 6;
20618 unsigned TotalNumXMMRegs = 8;
20619 bool UseGPOffset = (ArgMode == 1);
20620 bool UseFPOffset = (ArgMode == 2);
20621 unsigned MaxOffset = TotalNumIntRegs * 8 +
20622 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20624 /* Align ArgSize to a multiple of 8 */
20625 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20626 bool NeedsAlign = (Align > 8);
20628 MachineBasicBlock *thisMBB = MBB;
20629 MachineBasicBlock *overflowMBB;
20630 MachineBasicBlock *offsetMBB;
20631 MachineBasicBlock *endMBB;
20633 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20634 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20635 unsigned OffsetReg = 0;
20637 if (!UseGPOffset && !UseFPOffset) {
20638 // If we only pull from the overflow region, we don't create a branch.
20639 // We don't need to alter control flow.
20640 OffsetDestReg = 0; // unused
20641 OverflowDestReg = DestReg;
20643 offsetMBB = nullptr;
20644 overflowMBB = thisMBB;
20647 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20648 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20649 // If not, pull from overflow_area. (branch to overflowMBB)
20654 // offsetMBB overflowMBB
20659 // Registers for the PHI in endMBB
20660 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20661 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20663 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20664 MachineFunction *MF = MBB->getParent();
20665 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20666 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20667 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20669 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20671 // Insert the new basic blocks
20672 MF->insert(MBBIter, offsetMBB);
20673 MF->insert(MBBIter, overflowMBB);
20674 MF->insert(MBBIter, endMBB);
20676 // Transfer the remainder of MBB and its successor edges to endMBB.
20677 endMBB->splice(endMBB->begin(), thisMBB,
20678 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20679 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20681 // Make offsetMBB and overflowMBB successors of thisMBB
20682 thisMBB->addSuccessor(offsetMBB);
20683 thisMBB->addSuccessor(overflowMBB);
20685 // endMBB is a successor of both offsetMBB and overflowMBB
20686 offsetMBB->addSuccessor(endMBB);
20687 overflowMBB->addSuccessor(endMBB);
20689 // Load the offset value into a register
20690 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20691 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20695 .addDisp(Disp, UseFPOffset ? 4 : 0)
20696 .addOperand(Segment)
20697 .setMemRefs(MMOBegin, MMOEnd);
20699 // Check if there is enough room left to pull this argument.
20700 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20702 .addImm(MaxOffset + 8 - ArgSizeA8);
20704 // Branch to "overflowMBB" if offset >= max
20705 // Fall through to "offsetMBB" otherwise
20706 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20707 .addMBB(overflowMBB);
20710 // In offsetMBB, emit code to use the reg_save_area.
20712 assert(OffsetReg != 0);
20714 // Read the reg_save_area address.
20715 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20716 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20721 .addOperand(Segment)
20722 .setMemRefs(MMOBegin, MMOEnd);
20724 // Zero-extend the offset
20725 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20726 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20729 .addImm(X86::sub_32bit);
20731 // Add the offset to the reg_save_area to get the final address.
20732 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20733 .addReg(OffsetReg64)
20734 .addReg(RegSaveReg);
20736 // Compute the offset for the next argument
20737 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20738 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20740 .addImm(UseFPOffset ? 16 : 8);
20742 // Store it back into the va_list.
20743 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20747 .addDisp(Disp, UseFPOffset ? 4 : 0)
20748 .addOperand(Segment)
20749 .addReg(NextOffsetReg)
20750 .setMemRefs(MMOBegin, MMOEnd);
20753 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20758 // Emit code to use overflow area
20761 // Load the overflow_area address into a register.
20762 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20763 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20768 .addOperand(Segment)
20769 .setMemRefs(MMOBegin, MMOEnd);
20771 // If we need to align it, do so. Otherwise, just copy the address
20772 // to OverflowDestReg.
20774 // Align the overflow address
20775 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20776 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20778 // aligned_addr = (addr + (align-1)) & ~(align-1)
20779 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20780 .addReg(OverflowAddrReg)
20783 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20785 .addImm(~(uint64_t)(Align-1));
20787 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20788 .addReg(OverflowAddrReg);
20791 // Compute the next overflow address after this argument.
20792 // (the overflow address should be kept 8-byte aligned)
20793 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20794 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20795 .addReg(OverflowDestReg)
20796 .addImm(ArgSizeA8);
20798 // Store the new overflow address.
20799 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20804 .addOperand(Segment)
20805 .addReg(NextAddrReg)
20806 .setMemRefs(MMOBegin, MMOEnd);
20808 // If we branched, emit the PHI to the front of endMBB.
20810 BuildMI(*endMBB, endMBB->begin(), DL,
20811 TII->get(X86::PHI), DestReg)
20812 .addReg(OffsetDestReg).addMBB(offsetMBB)
20813 .addReg(OverflowDestReg).addMBB(overflowMBB);
20816 // Erase the pseudo instruction
20817 MI->eraseFromParent();
20822 MachineBasicBlock *
20823 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20825 MachineBasicBlock *MBB) const {
20826 // Emit code to save XMM registers to the stack. The ABI says that the
20827 // number of registers to save is given in %al, so it's theoretically
20828 // possible to do an indirect jump trick to avoid saving all of them,
20829 // however this code takes a simpler approach and just executes all
20830 // of the stores if %al is non-zero. It's less code, and it's probably
20831 // easier on the hardware branch predictor, and stores aren't all that
20832 // expensive anyway.
20834 // Create the new basic blocks. One block contains all the XMM stores,
20835 // and one block is the final destination regardless of whether any
20836 // stores were performed.
20837 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20838 MachineFunction *F = MBB->getParent();
20839 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20840 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20841 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20842 F->insert(MBBIter, XMMSaveMBB);
20843 F->insert(MBBIter, EndMBB);
20845 // Transfer the remainder of MBB and its successor edges to EndMBB.
20846 EndMBB->splice(EndMBB->begin(), MBB,
20847 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20848 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20850 // The original block will now fall through to the XMM save block.
20851 MBB->addSuccessor(XMMSaveMBB);
20852 // The XMMSaveMBB will fall through to the end block.
20853 XMMSaveMBB->addSuccessor(EndMBB);
20855 // Now add the instructions.
20856 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20857 DebugLoc DL = MI->getDebugLoc();
20859 unsigned CountReg = MI->getOperand(0).getReg();
20860 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20861 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20863 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20864 // If %al is 0, branch around the XMM save block.
20865 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20866 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20867 MBB->addSuccessor(EndMBB);
20870 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20871 // that was just emitted, but clearly shouldn't be "saved".
20872 assert((MI->getNumOperands() <= 3 ||
20873 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20874 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20875 && "Expected last argument to be EFLAGS");
20876 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20877 // In the XMM save block, save all the XMM argument registers.
20878 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20879 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20880 MachineMemOperand *MMO = F->getMachineMemOperand(
20881 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20882 MachineMemOperand::MOStore,
20883 /*Size=*/16, /*Align=*/16);
20884 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20885 .addFrameIndex(RegSaveFrameIndex)
20886 .addImm(/*Scale=*/1)
20887 .addReg(/*IndexReg=*/0)
20888 .addImm(/*Disp=*/Offset)
20889 .addReg(/*Segment=*/0)
20890 .addReg(MI->getOperand(i).getReg())
20891 .addMemOperand(MMO);
20894 MI->eraseFromParent(); // The pseudo instruction is gone now.
20899 // The EFLAGS operand of SelectItr might be missing a kill marker
20900 // because there were multiple uses of EFLAGS, and ISel didn't know
20901 // which to mark. Figure out whether SelectItr should have had a
20902 // kill marker, and set it if it should. Returns the correct kill
20904 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20905 MachineBasicBlock* BB,
20906 const TargetRegisterInfo* TRI) {
20907 // Scan forward through BB for a use/def of EFLAGS.
20908 MachineBasicBlock::iterator miI(std::next(SelectItr));
20909 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20910 const MachineInstr& mi = *miI;
20911 if (mi.readsRegister(X86::EFLAGS))
20913 if (mi.definesRegister(X86::EFLAGS))
20914 break; // Should have kill-flag - update below.
20917 // If we hit the end of the block, check whether EFLAGS is live into a
20919 if (miI == BB->end()) {
20920 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20921 sEnd = BB->succ_end();
20922 sItr != sEnd; ++sItr) {
20923 MachineBasicBlock* succ = *sItr;
20924 if (succ->isLiveIn(X86::EFLAGS))
20929 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20930 // out. SelectMI should have a kill flag on EFLAGS.
20931 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20935 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20936 // together with other CMOV pseudo-opcodes into a single basic-block with
20937 // conditional jump around it.
20938 static bool isCMOVPseudo(MachineInstr *MI) {
20939 switch (MI->getOpcode()) {
20940 case X86::CMOV_FR32:
20941 case X86::CMOV_FR64:
20942 case X86::CMOV_GR8:
20943 case X86::CMOV_GR16:
20944 case X86::CMOV_GR32:
20945 case X86::CMOV_RFP32:
20946 case X86::CMOV_RFP64:
20947 case X86::CMOV_RFP80:
20948 case X86::CMOV_V2F64:
20949 case X86::CMOV_V2I64:
20950 case X86::CMOV_V4F32:
20951 case X86::CMOV_V4F64:
20952 case X86::CMOV_V4I64:
20953 case X86::CMOV_V16F32:
20954 case X86::CMOV_V8F32:
20955 case X86::CMOV_V8F64:
20956 case X86::CMOV_V8I64:
20957 case X86::CMOV_V8I1:
20958 case X86::CMOV_V16I1:
20959 case X86::CMOV_V32I1:
20960 case X86::CMOV_V64I1:
20968 MachineBasicBlock *
20969 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20970 MachineBasicBlock *BB) const {
20971 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20972 DebugLoc DL = MI->getDebugLoc();
20974 // To "insert" a SELECT_CC instruction, we actually have to insert the
20975 // diamond control-flow pattern. The incoming instruction knows the
20976 // destination vreg to set, the condition code register to branch on, the
20977 // true/false values to select between, and a branch opcode to use.
20978 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20979 MachineFunction::iterator It = ++BB->getIterator();
20984 // cmpTY ccX, r1, r2
20986 // fallthrough --> copy0MBB
20987 MachineBasicBlock *thisMBB = BB;
20988 MachineFunction *F = BB->getParent();
20990 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20991 // as described above, by inserting a BB, and then making a PHI at the join
20992 // point to select the true and false operands of the CMOV in the PHI.
20994 // The code also handles two different cases of multiple CMOV opcodes
20998 // In this case, there are multiple CMOVs in a row, all which are based on
20999 // the same condition setting (or the exact opposite condition setting).
21000 // In this case we can lower all the CMOVs using a single inserted BB, and
21001 // then make a number of PHIs at the join point to model the CMOVs. The only
21002 // trickiness here, is that in a case like:
21004 // t2 = CMOV cond1 t1, f1
21005 // t3 = CMOV cond1 t2, f2
21007 // when rewriting this into PHIs, we have to perform some renaming on the
21008 // temps since you cannot have a PHI operand refer to a PHI result earlier
21009 // in the same block. The "simple" but wrong lowering would be:
21011 // t2 = PHI t1(BB1), f1(BB2)
21012 // t3 = PHI t2(BB1), f2(BB2)
21014 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21015 // renaming is to note that on the path through BB1, t2 is really just a
21016 // copy of t1, and do that renaming, properly generating:
21018 // t2 = PHI t1(BB1), f1(BB2)
21019 // t3 = PHI t1(BB1), f2(BB2)
21021 // Case 2, we lower cascaded CMOVs such as
21023 // (CMOV (CMOV F, T, cc1), T, cc2)
21025 // to two successives branches. For that, we look for another CMOV as the
21026 // following instruction.
21028 // Without this, we would add a PHI between the two jumps, which ends up
21029 // creating a few copies all around. For instance, for
21031 // (sitofp (zext (fcmp une)))
21033 // we would generate:
21035 // ucomiss %xmm1, %xmm0
21036 // movss <1.0f>, %xmm0
21037 // movaps %xmm0, %xmm1
21039 // xorps %xmm1, %xmm1
21042 // movaps %xmm1, %xmm0
21046 // because this custom-inserter would have generated:
21058 // A: X = ...; Y = ...
21060 // C: Z = PHI [X, A], [Y, B]
21062 // E: PHI [X, C], [Z, D]
21064 // If we lower both CMOVs in a single step, we can instead generate:
21076 // A: X = ...; Y = ...
21078 // E: PHI [X, A], [X, C], [Y, D]
21080 // Which, in our sitofp/fcmp example, gives us something like:
21082 // ucomiss %xmm1, %xmm0
21083 // movss <1.0f>, %xmm0
21086 // xorps %xmm0, %xmm0
21090 MachineInstr *CascadedCMOV = nullptr;
21091 MachineInstr *LastCMOV = MI;
21092 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21093 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21094 MachineBasicBlock::iterator NextMIIt =
21095 std::next(MachineBasicBlock::iterator(MI));
21097 // Check for case 1, where there are multiple CMOVs with the same condition
21098 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21099 // number of jumps the most.
21101 if (isCMOVPseudo(MI)) {
21102 // See if we have a string of CMOVS with the same condition.
21103 while (NextMIIt != BB->end() &&
21104 isCMOVPseudo(NextMIIt) &&
21105 (NextMIIt->getOperand(3).getImm() == CC ||
21106 NextMIIt->getOperand(3).getImm() == OppCC)) {
21107 LastCMOV = &*NextMIIt;
21112 // This checks for case 2, but only do this if we didn't already find
21113 // case 1, as indicated by LastCMOV == MI.
21114 if (LastCMOV == MI &&
21115 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21116 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21117 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21118 CascadedCMOV = &*NextMIIt;
21121 MachineBasicBlock *jcc1MBB = nullptr;
21123 // If we have a cascaded CMOV, we lower it to two successive branches to
21124 // the same block. EFLAGS is used by both, so mark it as live in the second.
21125 if (CascadedCMOV) {
21126 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21127 F->insert(It, jcc1MBB);
21128 jcc1MBB->addLiveIn(X86::EFLAGS);
21131 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21132 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21133 F->insert(It, copy0MBB);
21134 F->insert(It, sinkMBB);
21136 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21137 // live into the sink and copy blocks.
21138 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21140 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21141 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21142 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21143 copy0MBB->addLiveIn(X86::EFLAGS);
21144 sinkMBB->addLiveIn(X86::EFLAGS);
21147 // Transfer the remainder of BB and its successor edges to sinkMBB.
21148 sinkMBB->splice(sinkMBB->begin(), BB,
21149 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21150 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21152 // Add the true and fallthrough blocks as its successors.
21153 if (CascadedCMOV) {
21154 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21155 BB->addSuccessor(jcc1MBB);
21157 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21158 // jump to the sinkMBB.
21159 jcc1MBB->addSuccessor(copy0MBB);
21160 jcc1MBB->addSuccessor(sinkMBB);
21162 BB->addSuccessor(copy0MBB);
21165 // The true block target of the first (or only) branch is always sinkMBB.
21166 BB->addSuccessor(sinkMBB);
21168 // Create the conditional branch instruction.
21169 unsigned Opc = X86::GetCondBranchFromCond(CC);
21170 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21172 if (CascadedCMOV) {
21173 unsigned Opc2 = X86::GetCondBranchFromCond(
21174 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21175 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21179 // %FalseValue = ...
21180 // # fallthrough to sinkMBB
21181 copy0MBB->addSuccessor(sinkMBB);
21184 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21186 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21187 MachineBasicBlock::iterator MIItEnd =
21188 std::next(MachineBasicBlock::iterator(LastCMOV));
21189 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21190 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21191 MachineInstrBuilder MIB;
21193 // As we are creating the PHIs, we have to be careful if there is more than
21194 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21195 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21196 // That also means that PHI construction must work forward from earlier to
21197 // later, and that the code must maintain a mapping from earlier PHI's
21198 // destination registers, and the registers that went into the PHI.
21200 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21201 unsigned DestReg = MIIt->getOperand(0).getReg();
21202 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21203 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21205 // If this CMOV we are generating is the opposite condition from
21206 // the jump we generated, then we have to swap the operands for the
21207 // PHI that is going to be generated.
21208 if (MIIt->getOperand(3).getImm() == OppCC)
21209 std::swap(Op1Reg, Op2Reg);
21211 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21212 Op1Reg = RegRewriteTable[Op1Reg].first;
21214 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21215 Op2Reg = RegRewriteTable[Op2Reg].second;
21217 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21218 TII->get(X86::PHI), DestReg)
21219 .addReg(Op1Reg).addMBB(copy0MBB)
21220 .addReg(Op2Reg).addMBB(thisMBB);
21222 // Add this PHI to the rewrite table.
21223 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21226 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21227 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21228 if (CascadedCMOV) {
21229 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21230 // Copy the PHI result to the register defined by the second CMOV.
21231 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21232 DL, TII->get(TargetOpcode::COPY),
21233 CascadedCMOV->getOperand(0).getReg())
21234 .addReg(MI->getOperand(0).getReg());
21235 CascadedCMOV->eraseFromParent();
21238 // Now remove the CMOV(s).
21239 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21240 (MIIt++)->eraseFromParent();
21245 MachineBasicBlock *
21246 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21247 MachineBasicBlock *BB) const {
21248 // Combine the following atomic floating-point modification pattern:
21249 // a.store(reg OP a.load(acquire), release)
21250 // Transform them into:
21251 // OPss (%gpr), %xmm
21252 // movss %xmm, (%gpr)
21253 // Or sd equivalent for 64-bit operations.
21255 switch (MI->getOpcode()) {
21256 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21257 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21258 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21260 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21261 DebugLoc DL = MI->getDebugLoc();
21262 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21263 MachineOperand MSrc = MI->getOperand(0);
21264 unsigned VSrc = MI->getOperand(5).getReg();
21265 const MachineOperand &Disp = MI->getOperand(3);
21266 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21267 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21268 if (hasDisp && MSrc.isReg())
21269 MSrc.setIsKill(false);
21270 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21271 .addOperand(/*Base=*/MSrc)
21272 .addImm(/*Scale=*/1)
21273 .addReg(/*Index=*/0)
21274 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21276 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21277 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21279 .addOperand(/*Base=*/MSrc)
21280 .addImm(/*Scale=*/1)
21281 .addReg(/*Index=*/0)
21282 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21283 .addReg(/*Segment=*/0);
21284 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21285 MI->eraseFromParent(); // The pseudo instruction is gone now.
21289 MachineBasicBlock *
21290 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21291 MachineBasicBlock *BB) const {
21292 MachineFunction *MF = BB->getParent();
21293 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21294 DebugLoc DL = MI->getDebugLoc();
21295 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21297 assert(MF->shouldSplitStack());
21299 const bool Is64Bit = Subtarget->is64Bit();
21300 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21302 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21303 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21306 // ... [Till the alloca]
21307 // If stacklet is not large enough, jump to mallocMBB
21310 // Allocate by subtracting from RSP
21311 // Jump to continueMBB
21314 // Allocate by call to runtime
21318 // [rest of original BB]
21321 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21322 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21323 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21325 MachineRegisterInfo &MRI = MF->getRegInfo();
21326 const TargetRegisterClass *AddrRegClass =
21327 getRegClassFor(getPointerTy(MF->getDataLayout()));
21329 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21330 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21331 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21332 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21333 sizeVReg = MI->getOperand(1).getReg(),
21334 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21336 MachineFunction::iterator MBBIter = ++BB->getIterator();
21338 MF->insert(MBBIter, bumpMBB);
21339 MF->insert(MBBIter, mallocMBB);
21340 MF->insert(MBBIter, continueMBB);
21342 continueMBB->splice(continueMBB->begin(), BB,
21343 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21344 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21346 // Add code to the main basic block to check if the stack limit has been hit,
21347 // and if so, jump to mallocMBB otherwise to bumpMBB.
21348 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21349 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21350 .addReg(tmpSPVReg).addReg(sizeVReg);
21351 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21352 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21353 .addReg(SPLimitVReg);
21354 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21356 // bumpMBB simply decreases the stack pointer, since we know the current
21357 // stacklet has enough space.
21358 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21359 .addReg(SPLimitVReg);
21360 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21361 .addReg(SPLimitVReg);
21362 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21364 // Calls into a routine in libgcc to allocate more space from the heap.
21365 const uint32_t *RegMask =
21366 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21368 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21370 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21371 .addExternalSymbol("__morestack_allocate_stack_space")
21372 .addRegMask(RegMask)
21373 .addReg(X86::RDI, RegState::Implicit)
21374 .addReg(X86::RAX, RegState::ImplicitDefine);
21375 } else if (Is64Bit) {
21376 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21378 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21379 .addExternalSymbol("__morestack_allocate_stack_space")
21380 .addRegMask(RegMask)
21381 .addReg(X86::EDI, RegState::Implicit)
21382 .addReg(X86::EAX, RegState::ImplicitDefine);
21384 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21386 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21387 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21388 .addExternalSymbol("__morestack_allocate_stack_space")
21389 .addRegMask(RegMask)
21390 .addReg(X86::EAX, RegState::ImplicitDefine);
21394 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21397 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21398 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21399 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21401 // Set up the CFG correctly.
21402 BB->addSuccessor(bumpMBB);
21403 BB->addSuccessor(mallocMBB);
21404 mallocMBB->addSuccessor(continueMBB);
21405 bumpMBB->addSuccessor(continueMBB);
21407 // Take care of the PHI nodes.
21408 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21409 MI->getOperand(0).getReg())
21410 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21411 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21413 // Delete the original pseudo instruction.
21414 MI->eraseFromParent();
21417 return continueMBB;
21420 MachineBasicBlock *
21421 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21422 MachineBasicBlock *BB) const {
21423 DebugLoc DL = MI->getDebugLoc();
21425 assert(!Subtarget->isTargetMachO());
21427 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21430 MI->eraseFromParent(); // The pseudo instruction is gone now.
21434 MachineBasicBlock *
21435 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21436 MachineBasicBlock *BB) const {
21437 // This is pretty easy. We're taking the value that we received from
21438 // our load from the relocation, sticking it in either RDI (x86-64)
21439 // or EAX and doing an indirect call. The return value will then
21440 // be in the normal return register.
21441 MachineFunction *F = BB->getParent();
21442 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21443 DebugLoc DL = MI->getDebugLoc();
21445 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21446 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21448 // Get a register mask for the lowered call.
21449 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21450 // proper register mask.
21451 const uint32_t *RegMask =
21452 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21453 if (Subtarget->is64Bit()) {
21454 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21455 TII->get(X86::MOV64rm), X86::RDI)
21457 .addImm(0).addReg(0)
21458 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21459 MI->getOperand(3).getTargetFlags())
21461 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21462 addDirectMem(MIB, X86::RDI);
21463 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21464 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21465 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21466 TII->get(X86::MOV32rm), X86::EAX)
21468 .addImm(0).addReg(0)
21469 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21470 MI->getOperand(3).getTargetFlags())
21472 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21473 addDirectMem(MIB, X86::EAX);
21474 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21476 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21477 TII->get(X86::MOV32rm), X86::EAX)
21478 .addReg(TII->getGlobalBaseReg(F))
21479 .addImm(0).addReg(0)
21480 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21481 MI->getOperand(3).getTargetFlags())
21483 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21484 addDirectMem(MIB, X86::EAX);
21485 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21488 MI->eraseFromParent(); // The pseudo instruction is gone now.
21492 MachineBasicBlock *
21493 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21494 MachineBasicBlock *MBB) const {
21495 DebugLoc DL = MI->getDebugLoc();
21496 MachineFunction *MF = MBB->getParent();
21497 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21498 MachineRegisterInfo &MRI = MF->getRegInfo();
21500 const BasicBlock *BB = MBB->getBasicBlock();
21501 MachineFunction::iterator I = ++MBB->getIterator();
21503 // Memory Reference
21504 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21505 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21508 unsigned MemOpndSlot = 0;
21510 unsigned CurOp = 0;
21512 DstReg = MI->getOperand(CurOp++).getReg();
21513 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21514 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21515 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21516 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21518 MemOpndSlot = CurOp;
21520 MVT PVT = getPointerTy(MF->getDataLayout());
21521 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21522 "Invalid Pointer Size!");
21524 // For v = setjmp(buf), we generate
21527 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21528 // SjLjSetup restoreMBB
21534 // v = phi(main, restore)
21537 // if base pointer being used, load it from frame
21540 MachineBasicBlock *thisMBB = MBB;
21541 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21542 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21543 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21544 MF->insert(I, mainMBB);
21545 MF->insert(I, sinkMBB);
21546 MF->push_back(restoreMBB);
21547 restoreMBB->setHasAddressTaken();
21549 MachineInstrBuilder MIB;
21551 // Transfer the remainder of BB and its successor edges to sinkMBB.
21552 sinkMBB->splice(sinkMBB->begin(), MBB,
21553 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21554 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21557 unsigned PtrStoreOpc = 0;
21558 unsigned LabelReg = 0;
21559 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21560 Reloc::Model RM = MF->getTarget().getRelocationModel();
21561 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21562 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21564 // Prepare IP either in reg or imm.
21565 if (!UseImmLabel) {
21566 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21567 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21568 LabelReg = MRI.createVirtualRegister(PtrRC);
21569 if (Subtarget->is64Bit()) {
21570 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21574 .addMBB(restoreMBB)
21577 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21578 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21579 .addReg(XII->getGlobalBaseReg(MF))
21582 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21586 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21588 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21589 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21590 if (i == X86::AddrDisp)
21591 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21593 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21596 MIB.addReg(LabelReg);
21598 MIB.addMBB(restoreMBB);
21599 MIB.setMemRefs(MMOBegin, MMOEnd);
21601 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21602 .addMBB(restoreMBB);
21604 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21605 MIB.addRegMask(RegInfo->getNoPreservedMask());
21606 thisMBB->addSuccessor(mainMBB);
21607 thisMBB->addSuccessor(restoreMBB);
21611 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21612 mainMBB->addSuccessor(sinkMBB);
21615 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21616 TII->get(X86::PHI), DstReg)
21617 .addReg(mainDstReg).addMBB(mainMBB)
21618 .addReg(restoreDstReg).addMBB(restoreMBB);
21621 if (RegInfo->hasBasePointer(*MF)) {
21622 const bool Uses64BitFramePtr =
21623 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21624 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21625 X86FI->setRestoreBasePointer(MF);
21626 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21627 unsigned BasePtr = RegInfo->getBaseRegister();
21628 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21629 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21630 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21631 .setMIFlag(MachineInstr::FrameSetup);
21633 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21634 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21635 restoreMBB->addSuccessor(sinkMBB);
21637 MI->eraseFromParent();
21641 MachineBasicBlock *
21642 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21643 MachineBasicBlock *MBB) const {
21644 DebugLoc DL = MI->getDebugLoc();
21645 MachineFunction *MF = MBB->getParent();
21646 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21647 MachineRegisterInfo &MRI = MF->getRegInfo();
21649 // Memory Reference
21650 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21651 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21653 MVT PVT = getPointerTy(MF->getDataLayout());
21654 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21655 "Invalid Pointer Size!");
21657 const TargetRegisterClass *RC =
21658 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21659 unsigned Tmp = MRI.createVirtualRegister(RC);
21660 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21661 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21662 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21663 unsigned SP = RegInfo->getStackRegister();
21665 MachineInstrBuilder MIB;
21667 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21668 const int64_t SPOffset = 2 * PVT.getStoreSize();
21670 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21671 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21674 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21675 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21676 MIB.addOperand(MI->getOperand(i));
21677 MIB.setMemRefs(MMOBegin, MMOEnd);
21679 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21680 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21681 if (i == X86::AddrDisp)
21682 MIB.addDisp(MI->getOperand(i), LabelOffset);
21684 MIB.addOperand(MI->getOperand(i));
21686 MIB.setMemRefs(MMOBegin, MMOEnd);
21688 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21689 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21690 if (i == X86::AddrDisp)
21691 MIB.addDisp(MI->getOperand(i), SPOffset);
21693 MIB.addOperand(MI->getOperand(i));
21695 MIB.setMemRefs(MMOBegin, MMOEnd);
21697 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21699 MI->eraseFromParent();
21703 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21704 // accumulator loops. Writing back to the accumulator allows the coalescer
21705 // to remove extra copies in the loop.
21706 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21707 MachineBasicBlock *
21708 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21709 MachineBasicBlock *MBB) const {
21710 MachineOperand &AddendOp = MI->getOperand(3);
21712 // Bail out early if the addend isn't a register - we can't switch these.
21713 if (!AddendOp.isReg())
21716 MachineFunction &MF = *MBB->getParent();
21717 MachineRegisterInfo &MRI = MF.getRegInfo();
21719 // Check whether the addend is defined by a PHI:
21720 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21721 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21722 if (!AddendDef.isPHI())
21725 // Look for the following pattern:
21727 // %addend = phi [%entry, 0], [%loop, %result]
21729 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21733 // %addend = phi [%entry, 0], [%loop, %result]
21735 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21737 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21738 assert(AddendDef.getOperand(i).isReg());
21739 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21740 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21741 if (&PHISrcInst == MI) {
21742 // Found a matching instruction.
21743 unsigned NewFMAOpc = 0;
21744 switch (MI->getOpcode()) {
21745 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21746 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21747 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21748 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21749 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21750 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21751 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21752 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21753 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21754 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21755 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21756 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21757 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21758 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21759 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21760 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21761 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21762 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21763 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21764 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21766 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21767 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21768 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21769 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21770 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21771 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21772 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21773 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21774 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21775 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21776 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21777 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21778 default: llvm_unreachable("Unrecognized FMA variant.");
21781 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21782 MachineInstrBuilder MIB =
21783 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21784 .addOperand(MI->getOperand(0))
21785 .addOperand(MI->getOperand(3))
21786 .addOperand(MI->getOperand(2))
21787 .addOperand(MI->getOperand(1));
21788 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21789 MI->eraseFromParent();
21796 MachineBasicBlock *
21797 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21798 MachineBasicBlock *BB) const {
21799 switch (MI->getOpcode()) {
21800 default: llvm_unreachable("Unexpected instr type to insert");
21801 case X86::TAILJMPd64:
21802 case X86::TAILJMPr64:
21803 case X86::TAILJMPm64:
21804 case X86::TAILJMPd64_REX:
21805 case X86::TAILJMPr64_REX:
21806 case X86::TAILJMPm64_REX:
21807 llvm_unreachable("TAILJMP64 would not be touched here.");
21808 case X86::TCRETURNdi64:
21809 case X86::TCRETURNri64:
21810 case X86::TCRETURNmi64:
21812 case X86::WIN_ALLOCA:
21813 return EmitLoweredWinAlloca(MI, BB);
21814 case X86::SEG_ALLOCA_32:
21815 case X86::SEG_ALLOCA_64:
21816 return EmitLoweredSegAlloca(MI, BB);
21817 case X86::TLSCall_32:
21818 case X86::TLSCall_64:
21819 return EmitLoweredTLSCall(MI, BB);
21820 case X86::CMOV_FR32:
21821 case X86::CMOV_FR64:
21822 case X86::CMOV_GR8:
21823 case X86::CMOV_GR16:
21824 case X86::CMOV_GR32:
21825 case X86::CMOV_RFP32:
21826 case X86::CMOV_RFP64:
21827 case X86::CMOV_RFP80:
21828 case X86::CMOV_V2F64:
21829 case X86::CMOV_V2I64:
21830 case X86::CMOV_V4F32:
21831 case X86::CMOV_V4F64:
21832 case X86::CMOV_V4I64:
21833 case X86::CMOV_V16F32:
21834 case X86::CMOV_V8F32:
21835 case X86::CMOV_V8F64:
21836 case X86::CMOV_V8I64:
21837 case X86::CMOV_V8I1:
21838 case X86::CMOV_V16I1:
21839 case X86::CMOV_V32I1:
21840 case X86::CMOV_V64I1:
21841 return EmitLoweredSelect(MI, BB);
21843 case X86::RELEASE_FADD32mr:
21844 case X86::RELEASE_FADD64mr:
21845 return EmitLoweredAtomicFP(MI, BB);
21847 case X86::FP32_TO_INT16_IN_MEM:
21848 case X86::FP32_TO_INT32_IN_MEM:
21849 case X86::FP32_TO_INT64_IN_MEM:
21850 case X86::FP64_TO_INT16_IN_MEM:
21851 case X86::FP64_TO_INT32_IN_MEM:
21852 case X86::FP64_TO_INT64_IN_MEM:
21853 case X86::FP80_TO_INT16_IN_MEM:
21854 case X86::FP80_TO_INT32_IN_MEM:
21855 case X86::FP80_TO_INT64_IN_MEM: {
21856 MachineFunction *F = BB->getParent();
21857 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21858 DebugLoc DL = MI->getDebugLoc();
21860 // Change the floating point control register to use "round towards zero"
21861 // mode when truncating to an integer value.
21862 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21863 addFrameReference(BuildMI(*BB, MI, DL,
21864 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21866 // Load the old value of the high byte of the control word...
21868 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21869 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21872 // Set the high part to be round to zero...
21873 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21876 // Reload the modified control word now...
21877 addFrameReference(BuildMI(*BB, MI, DL,
21878 TII->get(X86::FLDCW16m)), CWFrameIdx);
21880 // Restore the memory image of control word to original value
21881 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21884 // Get the X86 opcode to use.
21886 switch (MI->getOpcode()) {
21887 default: llvm_unreachable("illegal opcode!");
21888 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21889 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21890 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21891 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21892 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21893 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21894 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21895 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21896 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21900 MachineOperand &Op = MI->getOperand(0);
21902 AM.BaseType = X86AddressMode::RegBase;
21903 AM.Base.Reg = Op.getReg();
21905 AM.BaseType = X86AddressMode::FrameIndexBase;
21906 AM.Base.FrameIndex = Op.getIndex();
21908 Op = MI->getOperand(1);
21910 AM.Scale = Op.getImm();
21911 Op = MI->getOperand(2);
21913 AM.IndexReg = Op.getImm();
21914 Op = MI->getOperand(3);
21915 if (Op.isGlobal()) {
21916 AM.GV = Op.getGlobal();
21918 AM.Disp = Op.getImm();
21920 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21921 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21923 // Reload the original control word now.
21924 addFrameReference(BuildMI(*BB, MI, DL,
21925 TII->get(X86::FLDCW16m)), CWFrameIdx);
21927 MI->eraseFromParent(); // The pseudo instruction is gone now.
21930 // String/text processing lowering.
21931 case X86::PCMPISTRM128REG:
21932 case X86::VPCMPISTRM128REG:
21933 case X86::PCMPISTRM128MEM:
21934 case X86::VPCMPISTRM128MEM:
21935 case X86::PCMPESTRM128REG:
21936 case X86::VPCMPESTRM128REG:
21937 case X86::PCMPESTRM128MEM:
21938 case X86::VPCMPESTRM128MEM:
21939 assert(Subtarget->hasSSE42() &&
21940 "Target must have SSE4.2 or AVX features enabled");
21941 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21943 // String/text processing lowering.
21944 case X86::PCMPISTRIREG:
21945 case X86::VPCMPISTRIREG:
21946 case X86::PCMPISTRIMEM:
21947 case X86::VPCMPISTRIMEM:
21948 case X86::PCMPESTRIREG:
21949 case X86::VPCMPESTRIREG:
21950 case X86::PCMPESTRIMEM:
21951 case X86::VPCMPESTRIMEM:
21952 assert(Subtarget->hasSSE42() &&
21953 "Target must have SSE4.2 or AVX features enabled");
21954 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21956 // Thread synchronization.
21958 return EmitMonitor(MI, BB, Subtarget);
21962 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21964 case X86::VASTART_SAVE_XMM_REGS:
21965 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21967 case X86::VAARG_64:
21968 return EmitVAARG64WithCustomInserter(MI, BB);
21970 case X86::EH_SjLj_SetJmp32:
21971 case X86::EH_SjLj_SetJmp64:
21972 return emitEHSjLjSetJmp(MI, BB);
21974 case X86::EH_SjLj_LongJmp32:
21975 case X86::EH_SjLj_LongJmp64:
21976 return emitEHSjLjLongJmp(MI, BB);
21978 case TargetOpcode::STATEPOINT:
21979 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21980 // this point in the process. We diverge later.
21981 return emitPatchPoint(MI, BB);
21983 case TargetOpcode::STACKMAP:
21984 case TargetOpcode::PATCHPOINT:
21985 return emitPatchPoint(MI, BB);
21987 case X86::VFMADDPDr213r:
21988 case X86::VFMADDPSr213r:
21989 case X86::VFMADDSDr213r:
21990 case X86::VFMADDSSr213r:
21991 case X86::VFMSUBPDr213r:
21992 case X86::VFMSUBPSr213r:
21993 case X86::VFMSUBSDr213r:
21994 case X86::VFMSUBSSr213r:
21995 case X86::VFNMADDPDr213r:
21996 case X86::VFNMADDPSr213r:
21997 case X86::VFNMADDSDr213r:
21998 case X86::VFNMADDSSr213r:
21999 case X86::VFNMSUBPDr213r:
22000 case X86::VFNMSUBPSr213r:
22001 case X86::VFNMSUBSDr213r:
22002 case X86::VFNMSUBSSr213r:
22003 case X86::VFMADDSUBPDr213r:
22004 case X86::VFMADDSUBPSr213r:
22005 case X86::VFMSUBADDPDr213r:
22006 case X86::VFMSUBADDPSr213r:
22007 case X86::VFMADDPDr213rY:
22008 case X86::VFMADDPSr213rY:
22009 case X86::VFMSUBPDr213rY:
22010 case X86::VFMSUBPSr213rY:
22011 case X86::VFNMADDPDr213rY:
22012 case X86::VFNMADDPSr213rY:
22013 case X86::VFNMSUBPDr213rY:
22014 case X86::VFNMSUBPSr213rY:
22015 case X86::VFMADDSUBPDr213rY:
22016 case X86::VFMADDSUBPSr213rY:
22017 case X86::VFMSUBADDPDr213rY:
22018 case X86::VFMSUBADDPSr213rY:
22019 return emitFMA3Instr(MI, BB);
22023 //===----------------------------------------------------------------------===//
22024 // X86 Optimization Hooks
22025 //===----------------------------------------------------------------------===//
22027 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22030 const SelectionDAG &DAG,
22031 unsigned Depth) const {
22032 unsigned BitWidth = KnownZero.getBitWidth();
22033 unsigned Opc = Op.getOpcode();
22034 assert((Opc >= ISD::BUILTIN_OP_END ||
22035 Opc == ISD::INTRINSIC_WO_CHAIN ||
22036 Opc == ISD::INTRINSIC_W_CHAIN ||
22037 Opc == ISD::INTRINSIC_VOID) &&
22038 "Should use MaskedValueIsZero if you don't know whether Op"
22039 " is a target node!");
22041 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22055 // These nodes' second result is a boolean.
22056 if (Op.getResNo() == 0)
22059 case X86ISD::SETCC:
22060 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22062 case ISD::INTRINSIC_WO_CHAIN: {
22063 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22064 unsigned NumLoBits = 0;
22067 case Intrinsic::x86_sse_movmsk_ps:
22068 case Intrinsic::x86_avx_movmsk_ps_256:
22069 case Intrinsic::x86_sse2_movmsk_pd:
22070 case Intrinsic::x86_avx_movmsk_pd_256:
22071 case Intrinsic::x86_mmx_pmovmskb:
22072 case Intrinsic::x86_sse2_pmovmskb_128:
22073 case Intrinsic::x86_avx2_pmovmskb: {
22074 // High bits of movmskp{s|d}, pmovmskb are known zero.
22076 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22077 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22078 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22079 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22080 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22081 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22082 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22083 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22085 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22094 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22096 const SelectionDAG &,
22097 unsigned Depth) const {
22098 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22099 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22100 return Op.getValueType().getScalarType().getSizeInBits();
22106 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22107 /// node is a GlobalAddress + offset.
22108 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22109 const GlobalValue* &GA,
22110 int64_t &Offset) const {
22111 if (N->getOpcode() == X86ISD::Wrapper) {
22112 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22113 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22114 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22118 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22121 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22122 /// same as extracting the high 128-bit part of 256-bit vector and then
22123 /// inserting the result into the low part of a new 256-bit vector
22124 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22125 EVT VT = SVOp->getValueType(0);
22126 unsigned NumElems = VT.getVectorNumElements();
22128 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22129 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22130 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22131 SVOp->getMaskElt(j) >= 0)
22137 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22138 /// same as extracting the low 128-bit part of 256-bit vector and then
22139 /// inserting the result into the high part of a new 256-bit vector
22140 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22141 EVT VT = SVOp->getValueType(0);
22142 unsigned NumElems = VT.getVectorNumElements();
22144 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22145 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22146 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22147 SVOp->getMaskElt(j) >= 0)
22153 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22154 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22155 TargetLowering::DAGCombinerInfo &DCI,
22156 const X86Subtarget* Subtarget) {
22158 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22159 SDValue V1 = SVOp->getOperand(0);
22160 SDValue V2 = SVOp->getOperand(1);
22161 EVT VT = SVOp->getValueType(0);
22162 unsigned NumElems = VT.getVectorNumElements();
22164 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22165 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22169 // V UNDEF BUILD_VECTOR UNDEF
22171 // CONCAT_VECTOR CONCAT_VECTOR
22174 // RESULT: V + zero extended
22176 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22177 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22178 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22181 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22184 // To match the shuffle mask, the first half of the mask should
22185 // be exactly the first vector, and all the rest a splat with the
22186 // first element of the second one.
22187 for (unsigned i = 0; i != NumElems/2; ++i)
22188 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22189 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22192 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22193 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22194 if (Ld->hasNUsesOfValue(1, 0)) {
22195 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22196 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22198 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22200 Ld->getPointerInfo(),
22201 Ld->getAlignment(),
22202 false/*isVolatile*/, true/*ReadMem*/,
22203 false/*WriteMem*/);
22205 // Make sure the newly-created LOAD is in the same position as Ld in
22206 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22207 // and update uses of Ld's output chain to use the TokenFactor.
22208 if (Ld->hasAnyUseOfValue(1)) {
22209 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22210 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22211 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22212 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22213 SDValue(ResNode.getNode(), 1));
22216 return DAG.getBitcast(VT, ResNode);
22220 // Emit a zeroed vector and insert the desired subvector on its
22222 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22223 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22224 return DCI.CombineTo(N, InsV);
22227 //===--------------------------------------------------------------------===//
22228 // Combine some shuffles into subvector extracts and inserts:
22231 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22232 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22233 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22234 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22235 return DCI.CombineTo(N, InsV);
22238 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22239 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22240 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22241 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22242 return DCI.CombineTo(N, InsV);
22248 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22251 /// This is the leaf of the recursive combinine below. When we have found some
22252 /// chain of single-use x86 shuffle instructions and accumulated the combined
22253 /// shuffle mask represented by them, this will try to pattern match that mask
22254 /// into either a single instruction if there is a special purpose instruction
22255 /// for this operation, or into a PSHUFB instruction which is a fully general
22256 /// instruction but should only be used to replace chains over a certain depth.
22257 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22258 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22259 TargetLowering::DAGCombinerInfo &DCI,
22260 const X86Subtarget *Subtarget) {
22261 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22263 // Find the operand that enters the chain. Note that multiple uses are OK
22264 // here, we're not going to remove the operand we find.
22265 SDValue Input = Op.getOperand(0);
22266 while (Input.getOpcode() == ISD::BITCAST)
22267 Input = Input.getOperand(0);
22269 MVT VT = Input.getSimpleValueType();
22270 MVT RootVT = Root.getSimpleValueType();
22273 if (Mask.size() == 1) {
22274 int Index = Mask[0];
22275 assert((Index >= 0 || Index == SM_SentinelUndef ||
22276 Index == SM_SentinelZero) &&
22277 "Invalid shuffle index found!");
22279 // We may end up with an accumulated mask of size 1 as a result of
22280 // widening of shuffle operands (see function canWidenShuffleElements).
22281 // If the only shuffle index is equal to SM_SentinelZero then propagate
22282 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22283 // mask, and therefore the entire chain of shuffles can be folded away.
22284 if (Index == SM_SentinelZero)
22285 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22287 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22292 // Use the float domain if the operand type is a floating point type.
22293 bool FloatDomain = VT.isFloatingPoint();
22295 // For floating point shuffles, we don't have free copies in the shuffle
22296 // instructions or the ability to load as part of the instruction, so
22297 // canonicalize their shuffles to UNPCK or MOV variants.
22299 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22300 // vectors because it can have a load folded into it that UNPCK cannot. This
22301 // doesn't preclude something switching to the shorter encoding post-RA.
22303 // FIXME: Should teach these routines about AVX vector widths.
22304 if (FloatDomain && VT.getSizeInBits() == 128) {
22305 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22306 bool Lo = Mask.equals({0, 0});
22309 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22310 // is no slower than UNPCKLPD but has the option to fold the input operand
22311 // into even an unaligned memory load.
22312 if (Lo && Subtarget->hasSSE3()) {
22313 Shuffle = X86ISD::MOVDDUP;
22314 ShuffleVT = MVT::v2f64;
22316 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22317 // than the UNPCK variants.
22318 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22319 ShuffleVT = MVT::v4f32;
22321 if (Depth == 1 && Root->getOpcode() == Shuffle)
22322 return false; // Nothing to do!
22323 Op = DAG.getBitcast(ShuffleVT, Input);
22324 DCI.AddToWorklist(Op.getNode());
22325 if (Shuffle == X86ISD::MOVDDUP)
22326 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22328 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22329 DCI.AddToWorklist(Op.getNode());
22330 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22334 if (Subtarget->hasSSE3() &&
22335 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22336 bool Lo = Mask.equals({0, 0, 2, 2});
22337 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22338 MVT ShuffleVT = MVT::v4f32;
22339 if (Depth == 1 && Root->getOpcode() == Shuffle)
22340 return false; // Nothing to do!
22341 Op = DAG.getBitcast(ShuffleVT, Input);
22342 DCI.AddToWorklist(Op.getNode());
22343 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22344 DCI.AddToWorklist(Op.getNode());
22345 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22349 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22350 bool Lo = Mask.equals({0, 0, 1, 1});
22351 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22352 MVT ShuffleVT = MVT::v4f32;
22353 if (Depth == 1 && Root->getOpcode() == Shuffle)
22354 return false; // Nothing to do!
22355 Op = DAG.getBitcast(ShuffleVT, Input);
22356 DCI.AddToWorklist(Op.getNode());
22357 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22358 DCI.AddToWorklist(Op.getNode());
22359 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22365 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22366 // variants as none of these have single-instruction variants that are
22367 // superior to the UNPCK formulation.
22368 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22369 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22370 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22371 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22373 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22374 bool Lo = Mask[0] == 0;
22375 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22376 if (Depth == 1 && Root->getOpcode() == Shuffle)
22377 return false; // Nothing to do!
22379 switch (Mask.size()) {
22381 ShuffleVT = MVT::v8i16;
22384 ShuffleVT = MVT::v16i8;
22387 llvm_unreachable("Impossible mask size!");
22389 Op = DAG.getBitcast(ShuffleVT, Input);
22390 DCI.AddToWorklist(Op.getNode());
22391 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22392 DCI.AddToWorklist(Op.getNode());
22393 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22398 // Don't try to re-form single instruction chains under any circumstances now
22399 // that we've done encoding canonicalization for them.
22403 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22404 // can replace them with a single PSHUFB instruction profitably. Intel's
22405 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22406 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22407 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22408 SmallVector<SDValue, 16> PSHUFBMask;
22409 int NumBytes = VT.getSizeInBits() / 8;
22410 int Ratio = NumBytes / Mask.size();
22411 for (int i = 0; i < NumBytes; ++i) {
22412 if (Mask[i / Ratio] == SM_SentinelUndef) {
22413 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22416 int M = Mask[i / Ratio] != SM_SentinelZero
22417 ? Ratio * Mask[i / Ratio] + i % Ratio
22419 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22421 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22422 Op = DAG.getBitcast(ByteVT, Input);
22423 DCI.AddToWorklist(Op.getNode());
22424 SDValue PSHUFBMaskOp =
22425 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22426 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22427 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22428 DCI.AddToWorklist(Op.getNode());
22429 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22434 // Failed to find any combines.
22438 /// \brief Fully generic combining of x86 shuffle instructions.
22440 /// This should be the last combine run over the x86 shuffle instructions. Once
22441 /// they have been fully optimized, this will recursively consider all chains
22442 /// of single-use shuffle instructions, build a generic model of the cumulative
22443 /// shuffle operation, and check for simpler instructions which implement this
22444 /// operation. We use this primarily for two purposes:
22446 /// 1) Collapse generic shuffles to specialized single instructions when
22447 /// equivalent. In most cases, this is just an encoding size win, but
22448 /// sometimes we will collapse multiple generic shuffles into a single
22449 /// special-purpose shuffle.
22450 /// 2) Look for sequences of shuffle instructions with 3 or more total
22451 /// instructions, and replace them with the slightly more expensive SSSE3
22452 /// PSHUFB instruction if available. We do this as the last combining step
22453 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22454 /// a suitable short sequence of other instructions. The PHUFB will either
22455 /// use a register or have to read from memory and so is slightly (but only
22456 /// slightly) more expensive than the other shuffle instructions.
22458 /// Because this is inherently a quadratic operation (for each shuffle in
22459 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22460 /// This should never be an issue in practice as the shuffle lowering doesn't
22461 /// produce sequences of more than 8 instructions.
22463 /// FIXME: We will currently miss some cases where the redundant shuffling
22464 /// would simplify under the threshold for PSHUFB formation because of
22465 /// combine-ordering. To fix this, we should do the redundant instruction
22466 /// combining in this recursive walk.
22467 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22468 ArrayRef<int> RootMask,
22469 int Depth, bool HasPSHUFB,
22471 TargetLowering::DAGCombinerInfo &DCI,
22472 const X86Subtarget *Subtarget) {
22473 // Bound the depth of our recursive combine because this is ultimately
22474 // quadratic in nature.
22478 // Directly rip through bitcasts to find the underlying operand.
22479 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22480 Op = Op.getOperand(0);
22482 MVT VT = Op.getSimpleValueType();
22483 if (!VT.isVector())
22484 return false; // Bail if we hit a non-vector.
22486 assert(Root.getSimpleValueType().isVector() &&
22487 "Shuffles operate on vector types!");
22488 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22489 "Can only combine shuffles of the same vector register size.");
22491 if (!isTargetShuffle(Op.getOpcode()))
22493 SmallVector<int, 16> OpMask;
22495 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22496 // We only can combine unary shuffles which we can decode the mask for.
22497 if (!HaveMask || !IsUnary)
22500 assert(VT.getVectorNumElements() == OpMask.size() &&
22501 "Different mask size from vector size!");
22502 assert(((RootMask.size() > OpMask.size() &&
22503 RootMask.size() % OpMask.size() == 0) ||
22504 (OpMask.size() > RootMask.size() &&
22505 OpMask.size() % RootMask.size() == 0) ||
22506 OpMask.size() == RootMask.size()) &&
22507 "The smaller number of elements must divide the larger.");
22508 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22509 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22510 assert(((RootRatio == 1 && OpRatio == 1) ||
22511 (RootRatio == 1) != (OpRatio == 1)) &&
22512 "Must not have a ratio for both incoming and op masks!");
22514 SmallVector<int, 16> Mask;
22515 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22517 // Merge this shuffle operation's mask into our accumulated mask. Note that
22518 // this shuffle's mask will be the first applied to the input, followed by the
22519 // root mask to get us all the way to the root value arrangement. The reason
22520 // for this order is that we are recursing up the operation chain.
22521 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22522 int RootIdx = i / RootRatio;
22523 if (RootMask[RootIdx] < 0) {
22524 // This is a zero or undef lane, we're done.
22525 Mask.push_back(RootMask[RootIdx]);
22529 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22530 int OpIdx = RootMaskedIdx / OpRatio;
22531 if (OpMask[OpIdx] < 0) {
22532 // The incoming lanes are zero or undef, it doesn't matter which ones we
22534 Mask.push_back(OpMask[OpIdx]);
22538 // Ok, we have non-zero lanes, map them through.
22539 Mask.push_back(OpMask[OpIdx] * OpRatio +
22540 RootMaskedIdx % OpRatio);
22543 // See if we can recurse into the operand to combine more things.
22544 switch (Op.getOpcode()) {
22545 case X86ISD::PSHUFB:
22547 case X86ISD::PSHUFD:
22548 case X86ISD::PSHUFHW:
22549 case X86ISD::PSHUFLW:
22550 if (Op.getOperand(0).hasOneUse() &&
22551 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22552 HasPSHUFB, DAG, DCI, Subtarget))
22556 case X86ISD::UNPCKL:
22557 case X86ISD::UNPCKH:
22558 assert(Op.getOperand(0) == Op.getOperand(1) &&
22559 "We only combine unary shuffles!");
22560 // We can't check for single use, we have to check that this shuffle is the
22562 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22563 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22564 HasPSHUFB, DAG, DCI, Subtarget))
22569 // Minor canonicalization of the accumulated shuffle mask to make it easier
22570 // to match below. All this does is detect masks with squential pairs of
22571 // elements, and shrink them to the half-width mask. It does this in a loop
22572 // so it will reduce the size of the mask to the minimal width mask which
22573 // performs an equivalent shuffle.
22574 SmallVector<int, 16> WidenedMask;
22575 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22576 Mask = std::move(WidenedMask);
22577 WidenedMask.clear();
22580 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22584 /// \brief Get the PSHUF-style mask from PSHUF node.
22586 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22587 /// PSHUF-style masks that can be reused with such instructions.
22588 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22589 MVT VT = N.getSimpleValueType();
22590 SmallVector<int, 4> Mask;
22592 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22596 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22597 // matter. Check that the upper masks are repeats and remove them.
22598 if (VT.getSizeInBits() > 128) {
22599 int LaneElts = 128 / VT.getScalarSizeInBits();
22601 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22602 for (int j = 0; j < LaneElts; ++j)
22603 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22604 "Mask doesn't repeat in high 128-bit lanes!");
22606 Mask.resize(LaneElts);
22609 switch (N.getOpcode()) {
22610 case X86ISD::PSHUFD:
22612 case X86ISD::PSHUFLW:
22615 case X86ISD::PSHUFHW:
22616 Mask.erase(Mask.begin(), Mask.begin() + 4);
22617 for (int &M : Mask)
22621 llvm_unreachable("No valid shuffle instruction found!");
22625 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22627 /// We walk up the chain and look for a combinable shuffle, skipping over
22628 /// shuffles that we could hoist this shuffle's transformation past without
22629 /// altering anything.
22631 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22633 TargetLowering::DAGCombinerInfo &DCI) {
22634 assert(N.getOpcode() == X86ISD::PSHUFD &&
22635 "Called with something other than an x86 128-bit half shuffle!");
22638 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22639 // of the shuffles in the chain so that we can form a fresh chain to replace
22641 SmallVector<SDValue, 8> Chain;
22642 SDValue V = N.getOperand(0);
22643 for (; V.hasOneUse(); V = V.getOperand(0)) {
22644 switch (V.getOpcode()) {
22646 return SDValue(); // Nothing combined!
22649 // Skip bitcasts as we always know the type for the target specific
22653 case X86ISD::PSHUFD:
22654 // Found another dword shuffle.
22657 case X86ISD::PSHUFLW:
22658 // Check that the low words (being shuffled) are the identity in the
22659 // dword shuffle, and the high words are self-contained.
22660 if (Mask[0] != 0 || Mask[1] != 1 ||
22661 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22664 Chain.push_back(V);
22667 case X86ISD::PSHUFHW:
22668 // Check that the high words (being shuffled) are the identity in the
22669 // dword shuffle, and the low words are self-contained.
22670 if (Mask[2] != 2 || Mask[3] != 3 ||
22671 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22674 Chain.push_back(V);
22677 case X86ISD::UNPCKL:
22678 case X86ISD::UNPCKH:
22679 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22680 // shuffle into a preceding word shuffle.
22681 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22682 V.getSimpleValueType().getScalarType() != MVT::i16)
22685 // Search for a half-shuffle which we can combine with.
22686 unsigned CombineOp =
22687 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22688 if (V.getOperand(0) != V.getOperand(1) ||
22689 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22691 Chain.push_back(V);
22692 V = V.getOperand(0);
22694 switch (V.getOpcode()) {
22696 return SDValue(); // Nothing to combine.
22698 case X86ISD::PSHUFLW:
22699 case X86ISD::PSHUFHW:
22700 if (V.getOpcode() == CombineOp)
22703 Chain.push_back(V);
22707 V = V.getOperand(0);
22711 } while (V.hasOneUse());
22714 // Break out of the loop if we break out of the switch.
22718 if (!V.hasOneUse())
22719 // We fell out of the loop without finding a viable combining instruction.
22722 // Merge this node's mask and our incoming mask.
22723 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22724 for (int &M : Mask)
22726 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22727 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22729 // Rebuild the chain around this new shuffle.
22730 while (!Chain.empty()) {
22731 SDValue W = Chain.pop_back_val();
22733 if (V.getValueType() != W.getOperand(0).getValueType())
22734 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22736 switch (W.getOpcode()) {
22738 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22740 case X86ISD::UNPCKL:
22741 case X86ISD::UNPCKH:
22742 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22745 case X86ISD::PSHUFD:
22746 case X86ISD::PSHUFLW:
22747 case X86ISD::PSHUFHW:
22748 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22752 if (V.getValueType() != N.getValueType())
22753 V = DAG.getBitcast(N.getValueType(), V);
22755 // Return the new chain to replace N.
22759 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22762 /// We walk up the chain, skipping shuffles of the other half and looking
22763 /// through shuffles which switch halves trying to find a shuffle of the same
22764 /// pair of dwords.
22765 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22767 TargetLowering::DAGCombinerInfo &DCI) {
22769 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22770 "Called with something other than an x86 128-bit half shuffle!");
22772 unsigned CombineOpcode = N.getOpcode();
22774 // Walk up a single-use chain looking for a combinable shuffle.
22775 SDValue V = N.getOperand(0);
22776 for (; V.hasOneUse(); V = V.getOperand(0)) {
22777 switch (V.getOpcode()) {
22779 return false; // Nothing combined!
22782 // Skip bitcasts as we always know the type for the target specific
22786 case X86ISD::PSHUFLW:
22787 case X86ISD::PSHUFHW:
22788 if (V.getOpcode() == CombineOpcode)
22791 // Other-half shuffles are no-ops.
22794 // Break out of the loop if we break out of the switch.
22798 if (!V.hasOneUse())
22799 // We fell out of the loop without finding a viable combining instruction.
22802 // Combine away the bottom node as its shuffle will be accumulated into
22803 // a preceding shuffle.
22804 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22806 // Record the old value.
22809 // Merge this node's mask and our incoming mask (adjusted to account for all
22810 // the pshufd instructions encountered).
22811 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22812 for (int &M : Mask)
22814 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22815 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22817 // Check that the shuffles didn't cancel each other out. If not, we need to
22818 // combine to the new one.
22820 // Replace the combinable shuffle with the combined one, updating all users
22821 // so that we re-evaluate the chain here.
22822 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22827 /// \brief Try to combine x86 target specific shuffles.
22828 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22829 TargetLowering::DAGCombinerInfo &DCI,
22830 const X86Subtarget *Subtarget) {
22832 MVT VT = N.getSimpleValueType();
22833 SmallVector<int, 4> Mask;
22835 switch (N.getOpcode()) {
22836 case X86ISD::PSHUFD:
22837 case X86ISD::PSHUFLW:
22838 case X86ISD::PSHUFHW:
22839 Mask = getPSHUFShuffleMask(N);
22840 assert(Mask.size() == 4);
22846 // Nuke no-op shuffles that show up after combining.
22847 if (isNoopShuffleMask(Mask))
22848 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22850 // Look for simplifications involving one or two shuffle instructions.
22851 SDValue V = N.getOperand(0);
22852 switch (N.getOpcode()) {
22855 case X86ISD::PSHUFLW:
22856 case X86ISD::PSHUFHW:
22857 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22859 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22860 return SDValue(); // We combined away this shuffle, so we're done.
22862 // See if this reduces to a PSHUFD which is no more expensive and can
22863 // combine with more operations. Note that it has to at least flip the
22864 // dwords as otherwise it would have been removed as a no-op.
22865 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22866 int DMask[] = {0, 1, 2, 3};
22867 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22868 DMask[DOffset + 0] = DOffset + 1;
22869 DMask[DOffset + 1] = DOffset + 0;
22870 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22871 V = DAG.getBitcast(DVT, V);
22872 DCI.AddToWorklist(V.getNode());
22873 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22874 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22875 DCI.AddToWorklist(V.getNode());
22876 return DAG.getBitcast(VT, V);
22879 // Look for shuffle patterns which can be implemented as a single unpack.
22880 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22881 // only works when we have a PSHUFD followed by two half-shuffles.
22882 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22883 (V.getOpcode() == X86ISD::PSHUFLW ||
22884 V.getOpcode() == X86ISD::PSHUFHW) &&
22885 V.getOpcode() != N.getOpcode() &&
22887 SDValue D = V.getOperand(0);
22888 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22889 D = D.getOperand(0);
22890 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22891 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22892 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22893 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22894 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22896 for (int i = 0; i < 4; ++i) {
22897 WordMask[i + NOffset] = Mask[i] + NOffset;
22898 WordMask[i + VOffset] = VMask[i] + VOffset;
22900 // Map the word mask through the DWord mask.
22902 for (int i = 0; i < 8; ++i)
22903 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22904 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22905 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22906 // We can replace all three shuffles with an unpack.
22907 V = DAG.getBitcast(VT, D.getOperand(0));
22908 DCI.AddToWorklist(V.getNode());
22909 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22918 case X86ISD::PSHUFD:
22919 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22928 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22930 /// We combine this directly on the abstract vector shuffle nodes so it is
22931 /// easier to generically match. We also insert dummy vector shuffle nodes for
22932 /// the operands which explicitly discard the lanes which are unused by this
22933 /// operation to try to flow through the rest of the combiner the fact that
22934 /// they're unused.
22935 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22937 EVT VT = N->getValueType(0);
22939 // We only handle target-independent shuffles.
22940 // FIXME: It would be easy and harmless to use the target shuffle mask
22941 // extraction tool to support more.
22942 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22945 auto *SVN = cast<ShuffleVectorSDNode>(N);
22946 ArrayRef<int> Mask = SVN->getMask();
22947 SDValue V1 = N->getOperand(0);
22948 SDValue V2 = N->getOperand(1);
22950 // We require the first shuffle operand to be the SUB node, and the second to
22951 // be the ADD node.
22952 // FIXME: We should support the commuted patterns.
22953 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22956 // If there are other uses of these operations we can't fold them.
22957 if (!V1->hasOneUse() || !V2->hasOneUse())
22960 // Ensure that both operations have the same operands. Note that we can
22961 // commute the FADD operands.
22962 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22963 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22964 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22967 // We're looking for blends between FADD and FSUB nodes. We insist on these
22968 // nodes being lined up in a specific expected pattern.
22969 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22970 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22971 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22974 // Only specific types are legal at this point, assert so we notice if and
22975 // when these change.
22976 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22977 VT == MVT::v4f64) &&
22978 "Unknown vector type encountered!");
22980 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22983 /// PerformShuffleCombine - Performs several different shuffle combines.
22984 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22985 TargetLowering::DAGCombinerInfo &DCI,
22986 const X86Subtarget *Subtarget) {
22988 SDValue N0 = N->getOperand(0);
22989 SDValue N1 = N->getOperand(1);
22990 EVT VT = N->getValueType(0);
22992 // Don't create instructions with illegal types after legalize types has run.
22993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22994 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22997 // If we have legalized the vector types, look for blends of FADD and FSUB
22998 // nodes that we can fuse into an ADDSUB node.
22999 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23000 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23003 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23004 if (Subtarget->hasFp256() && VT.is256BitVector() &&
23005 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23006 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23008 // During Type Legalization, when promoting illegal vector types,
23009 // the backend might introduce new shuffle dag nodes and bitcasts.
23011 // This code performs the following transformation:
23012 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23013 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23015 // We do this only if both the bitcast and the BINOP dag nodes have
23016 // one use. Also, perform this transformation only if the new binary
23017 // operation is legal. This is to avoid introducing dag nodes that
23018 // potentially need to be further expanded (or custom lowered) into a
23019 // less optimal sequence of dag nodes.
23020 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23021 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23022 N0.getOpcode() == ISD::BITCAST) {
23023 SDValue BC0 = N0.getOperand(0);
23024 EVT SVT = BC0.getValueType();
23025 unsigned Opcode = BC0.getOpcode();
23026 unsigned NumElts = VT.getVectorNumElements();
23028 if (BC0.hasOneUse() && SVT.isVector() &&
23029 SVT.getVectorNumElements() * 2 == NumElts &&
23030 TLI.isOperationLegal(Opcode, VT)) {
23031 bool CanFold = false;
23043 unsigned SVTNumElts = SVT.getVectorNumElements();
23044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23045 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23046 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23047 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23048 CanFold = SVOp->getMaskElt(i) < 0;
23051 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23052 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23053 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23054 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23059 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23060 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23061 // consecutive, non-overlapping, and in the right order.
23062 SmallVector<SDValue, 16> Elts;
23063 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23064 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23066 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23069 if (isTargetShuffle(N->getOpcode())) {
23071 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23072 if (Shuffle.getNode())
23075 // Try recursively combining arbitrary sequences of x86 shuffle
23076 // instructions into higher-order shuffles. We do this after combining
23077 // specific PSHUF instruction sequences into their minimal form so that we
23078 // can evaluate how many specialized shuffle instructions are involved in
23079 // a particular chain.
23080 SmallVector<int, 1> NonceMask; // Just a placeholder.
23081 NonceMask.push_back(0);
23082 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23083 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23085 return SDValue(); // This routine will use CombineTo to replace N.
23091 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23092 /// specific shuffle of a load can be folded into a single element load.
23093 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23094 /// shuffles have been custom lowered so we need to handle those here.
23095 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23096 TargetLowering::DAGCombinerInfo &DCI) {
23097 if (DCI.isBeforeLegalizeOps())
23100 SDValue InVec = N->getOperand(0);
23101 SDValue EltNo = N->getOperand(1);
23103 if (!isa<ConstantSDNode>(EltNo))
23106 EVT OriginalVT = InVec.getValueType();
23108 if (InVec.getOpcode() == ISD::BITCAST) {
23109 // Don't duplicate a load with other uses.
23110 if (!InVec.hasOneUse())
23112 EVT BCVT = InVec.getOperand(0).getValueType();
23113 if (!BCVT.isVector() ||
23114 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23116 InVec = InVec.getOperand(0);
23119 EVT CurrentVT = InVec.getValueType();
23121 if (!isTargetShuffle(InVec.getOpcode()))
23124 // Don't duplicate a load with other uses.
23125 if (!InVec.hasOneUse())
23128 SmallVector<int, 16> ShuffleMask;
23130 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23131 ShuffleMask, UnaryShuffle))
23134 // Select the input vector, guarding against out of range extract vector.
23135 unsigned NumElems = CurrentVT.getVectorNumElements();
23136 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23137 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23138 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23139 : InVec.getOperand(1);
23141 // If inputs to shuffle are the same for both ops, then allow 2 uses
23142 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23143 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23145 if (LdNode.getOpcode() == ISD::BITCAST) {
23146 // Don't duplicate a load with other uses.
23147 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23150 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23151 LdNode = LdNode.getOperand(0);
23154 if (!ISD::isNormalLoad(LdNode.getNode()))
23157 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23159 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23162 EVT EltVT = N->getValueType(0);
23163 // If there's a bitcast before the shuffle, check if the load type and
23164 // alignment is valid.
23165 unsigned Align = LN0->getAlignment();
23166 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23167 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23168 EltVT.getTypeForEVT(*DAG.getContext()));
23170 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23173 // All checks match so transform back to vector_shuffle so that DAG combiner
23174 // can finish the job
23177 // Create shuffle node taking into account the case that its a unary shuffle
23178 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23179 : InVec.getOperand(1);
23180 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23181 InVec.getOperand(0), Shuffle,
23183 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23184 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23188 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23189 /// special and don't usually play with other vector types, it's better to
23190 /// handle them early to be sure we emit efficient code by avoiding
23191 /// store-load conversions.
23192 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
23193 if (N->getValueType(0) != MVT::x86mmx ||
23194 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
23195 N->getOperand(0)->getValueType(0) != MVT::v2i32)
23198 SDValue V = N->getOperand(0);
23199 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
23200 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
23201 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
23202 N->getValueType(0), V.getOperand(0));
23207 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23208 /// generation and convert it from being a bunch of shuffles and extracts
23209 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23210 /// storing the value and loading scalars back, while for x64 we should
23211 /// use 64-bit extracts and shifts.
23212 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23213 TargetLowering::DAGCombinerInfo &DCI) {
23214 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23217 SDValue InputVector = N->getOperand(0);
23218 SDLoc dl(InputVector);
23219 // Detect mmx to i32 conversion through a v2i32 elt extract.
23220 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23221 N->getValueType(0) == MVT::i32 &&
23222 InputVector.getValueType() == MVT::v2i32) {
23224 // The bitcast source is a direct mmx result.
23225 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23226 if (MMXSrc.getValueType() == MVT::x86mmx)
23227 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23228 N->getValueType(0),
23229 InputVector.getNode()->getOperand(0));
23231 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23232 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23233 MMXSrc.getValueType() == MVT::i64) {
23234 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23235 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23236 MMXSrcOp.getValueType() == MVT::v1i64 &&
23237 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23238 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23239 N->getValueType(0), MMXSrcOp.getOperand(0));
23243 EVT VT = N->getValueType(0);
23245 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
23246 InputVector.getOpcode() == ISD::BITCAST &&
23247 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
23248 uint64_t ExtractedElt =
23249 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23250 uint64_t InputValue =
23251 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23252 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23253 return DAG.getConstant(Res, dl, MVT::i1);
23255 // Only operate on vectors of 4 elements, where the alternative shuffling
23256 // gets to be more expensive.
23257 if (InputVector.getValueType() != MVT::v4i32)
23260 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23261 // single use which is a sign-extend or zero-extend, and all elements are
23263 SmallVector<SDNode *, 4> Uses;
23264 unsigned ExtractedElements = 0;
23265 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23266 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23267 if (UI.getUse().getResNo() != InputVector.getResNo())
23270 SDNode *Extract = *UI;
23271 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23274 if (Extract->getValueType(0) != MVT::i32)
23276 if (!Extract->hasOneUse())
23278 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23279 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23281 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23284 // Record which element was extracted.
23285 ExtractedElements |=
23286 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23288 Uses.push_back(Extract);
23291 // If not all the elements were used, this may not be worthwhile.
23292 if (ExtractedElements != 15)
23295 // Ok, we've now decided to do the transformation.
23296 // If 64-bit shifts are legal, use the extract-shift sequence,
23297 // otherwise bounce the vector off the cache.
23298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23301 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23302 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23303 auto &DL = DAG.getDataLayout();
23304 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23305 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23306 DAG.getConstant(0, dl, VecIdxTy));
23307 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23308 DAG.getConstant(1, dl, VecIdxTy));
23310 SDValue ShAmt = DAG.getConstant(
23311 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23312 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23313 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23314 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23315 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23316 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23317 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23319 // Store the value to a temporary stack slot.
23320 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23321 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23322 MachinePointerInfo(), false, false, 0);
23324 EVT ElementType = InputVector.getValueType().getVectorElementType();
23325 unsigned EltSize = ElementType.getSizeInBits() / 8;
23327 // Replace each use (extract) with a load of the appropriate element.
23328 for (unsigned i = 0; i < 4; ++i) {
23329 uint64_t Offset = EltSize * i;
23330 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23331 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23333 SDValue ScalarAddr =
23334 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23336 // Load the scalar.
23337 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23338 ScalarAddr, MachinePointerInfo(),
23339 false, false, false, 0);
23344 // Replace the extracts
23345 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23346 UE = Uses.end(); UI != UE; ++UI) {
23347 SDNode *Extract = *UI;
23349 SDValue Idx = Extract->getOperand(1);
23350 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23351 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23354 // The replacement was made in place; don't return anything.
23359 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23360 const X86Subtarget *Subtarget) {
23362 SDValue Cond = N->getOperand(0);
23363 SDValue LHS = N->getOperand(1);
23364 SDValue RHS = N->getOperand(2);
23366 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23367 SDValue CondSrc = Cond->getOperand(0);
23368 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23369 Cond = CondSrc->getOperand(0);
23372 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23375 // A vselect where all conditions and data are constants can be optimized into
23376 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23377 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23378 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23381 unsigned MaskValue = 0;
23382 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23385 MVT VT = N->getSimpleValueType(0);
23386 unsigned NumElems = VT.getVectorNumElements();
23387 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23388 for (unsigned i = 0; i < NumElems; ++i) {
23389 // Be sure we emit undef where we can.
23390 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23391 ShuffleMask[i] = -1;
23393 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23396 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23397 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23399 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23402 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23404 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23405 TargetLowering::DAGCombinerInfo &DCI,
23406 const X86Subtarget *Subtarget) {
23408 SDValue Cond = N->getOperand(0);
23409 // Get the LHS/RHS of the select.
23410 SDValue LHS = N->getOperand(1);
23411 SDValue RHS = N->getOperand(2);
23412 EVT VT = LHS.getValueType();
23413 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23415 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23416 // instructions match the semantics of the common C idiom x<y?x:y but not
23417 // x<=y?x:y, because of how they handle negative zero (which can be
23418 // ignored in unsafe-math mode).
23419 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23420 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23421 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23422 (Subtarget->hasSSE2() ||
23423 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23424 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23426 unsigned Opcode = 0;
23427 // Check for x CC y ? x : y.
23428 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23429 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23433 // Converting this to a min would handle NaNs incorrectly, and swapping
23434 // the operands would cause it to handle comparisons between positive
23435 // and negative zero incorrectly.
23436 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23437 if (!DAG.getTarget().Options.UnsafeFPMath &&
23438 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23440 std::swap(LHS, RHS);
23442 Opcode = X86ISD::FMIN;
23445 // Converting this to a min would handle comparisons between positive
23446 // and negative zero incorrectly.
23447 if (!DAG.getTarget().Options.UnsafeFPMath &&
23448 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23450 Opcode = X86ISD::FMIN;
23453 // Converting this to a min would handle both negative zeros and NaNs
23454 // incorrectly, but we can swap the operands to fix both.
23455 std::swap(LHS, RHS);
23459 Opcode = X86ISD::FMIN;
23463 // Converting this to a max would handle comparisons between positive
23464 // and negative zero incorrectly.
23465 if (!DAG.getTarget().Options.UnsafeFPMath &&
23466 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23468 Opcode = X86ISD::FMAX;
23471 // Converting this to a max would handle NaNs incorrectly, and swapping
23472 // the operands would cause it to handle comparisons between positive
23473 // and negative zero incorrectly.
23474 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23475 if (!DAG.getTarget().Options.UnsafeFPMath &&
23476 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23478 std::swap(LHS, RHS);
23480 Opcode = X86ISD::FMAX;
23483 // Converting this to a max would handle both negative zeros and NaNs
23484 // incorrectly, but we can swap the operands to fix both.
23485 std::swap(LHS, RHS);
23489 Opcode = X86ISD::FMAX;
23492 // Check for x CC y ? y : x -- a min/max with reversed arms.
23493 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23494 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23498 // Converting this to a min would handle comparisons between positive
23499 // and negative zero incorrectly, and swapping the operands would
23500 // cause it to handle NaNs incorrectly.
23501 if (!DAG.getTarget().Options.UnsafeFPMath &&
23502 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23503 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23505 std::swap(LHS, RHS);
23507 Opcode = X86ISD::FMIN;
23510 // Converting this to a min would handle NaNs incorrectly.
23511 if (!DAG.getTarget().Options.UnsafeFPMath &&
23512 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23514 Opcode = X86ISD::FMIN;
23517 // Converting this to a min would handle both negative zeros and NaNs
23518 // incorrectly, but we can swap the operands to fix both.
23519 std::swap(LHS, RHS);
23523 Opcode = X86ISD::FMIN;
23527 // Converting this to a max would handle NaNs incorrectly.
23528 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23530 Opcode = X86ISD::FMAX;
23533 // Converting this to a max would handle comparisons between positive
23534 // and negative zero incorrectly, and swapping the operands would
23535 // cause it to handle NaNs incorrectly.
23536 if (!DAG.getTarget().Options.UnsafeFPMath &&
23537 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23538 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23540 std::swap(LHS, RHS);
23542 Opcode = X86ISD::FMAX;
23545 // Converting this to a max would handle both negative zeros and NaNs
23546 // incorrectly, but we can swap the operands to fix both.
23547 std::swap(LHS, RHS);
23551 Opcode = X86ISD::FMAX;
23557 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23560 EVT CondVT = Cond.getValueType();
23561 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23562 CondVT.getVectorElementType() == MVT::i1) {
23563 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23564 // lowering on KNL. In this case we convert it to
23565 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23566 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23567 // Since SKX these selects have a proper lowering.
23568 EVT OpVT = LHS.getValueType();
23569 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23570 (OpVT.getVectorElementType() == MVT::i8 ||
23571 OpVT.getVectorElementType() == MVT::i16) &&
23572 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23573 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23574 DCI.AddToWorklist(Cond.getNode());
23575 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23578 // If this is a select between two integer constants, try to do some
23580 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23581 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23582 // Don't do this for crazy integer types.
23583 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23584 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23585 // so that TrueC (the true value) is larger than FalseC.
23586 bool NeedsCondInvert = false;
23588 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23589 // Efficiently invertible.
23590 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23591 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23592 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23593 NeedsCondInvert = true;
23594 std::swap(TrueC, FalseC);
23597 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23598 if (FalseC->getAPIntValue() == 0 &&
23599 TrueC->getAPIntValue().isPowerOf2()) {
23600 if (NeedsCondInvert) // Invert the condition if needed.
23601 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23602 DAG.getConstant(1, DL, Cond.getValueType()));
23604 // Zero extend the condition if needed.
23605 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23607 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23608 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23609 DAG.getConstant(ShAmt, DL, MVT::i8));
23612 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23613 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23614 if (NeedsCondInvert) // Invert the condition if needed.
23615 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23616 DAG.getConstant(1, DL, Cond.getValueType()));
23618 // Zero extend the condition if needed.
23619 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23620 FalseC->getValueType(0), Cond);
23621 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23622 SDValue(FalseC, 0));
23625 // Optimize cases that will turn into an LEA instruction. This requires
23626 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23627 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23628 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23629 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23631 bool isFastMultiplier = false;
23633 switch ((unsigned char)Diff) {
23635 case 1: // result = add base, cond
23636 case 2: // result = lea base( , cond*2)
23637 case 3: // result = lea base(cond, cond*2)
23638 case 4: // result = lea base( , cond*4)
23639 case 5: // result = lea base(cond, cond*4)
23640 case 8: // result = lea base( , cond*8)
23641 case 9: // result = lea base(cond, cond*8)
23642 isFastMultiplier = true;
23647 if (isFastMultiplier) {
23648 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23649 if (NeedsCondInvert) // Invert the condition if needed.
23650 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23651 DAG.getConstant(1, DL, Cond.getValueType()));
23653 // Zero extend the condition if needed.
23654 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23656 // Scale the condition by the difference.
23658 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23659 DAG.getConstant(Diff, DL,
23660 Cond.getValueType()));
23662 // Add the base if non-zero.
23663 if (FalseC->getAPIntValue() != 0)
23664 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23665 SDValue(FalseC, 0));
23672 // Canonicalize max and min:
23673 // (x > y) ? x : y -> (x >= y) ? x : y
23674 // (x < y) ? x : y -> (x <= y) ? x : y
23675 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23676 // the need for an extra compare
23677 // against zero. e.g.
23678 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23680 // testl %edi, %edi
23682 // cmovgl %edi, %eax
23686 // cmovsl %eax, %edi
23687 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23688 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23689 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23690 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23695 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23696 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23697 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23698 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23703 // Early exit check
23704 if (!TLI.isTypeLegal(VT))
23707 // Match VSELECTs into subs with unsigned saturation.
23708 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23709 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23710 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23711 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23712 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23714 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23715 // left side invert the predicate to simplify logic below.
23717 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23719 CC = ISD::getSetCCInverse(CC, true);
23720 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23724 if (Other.getNode() && Other->getNumOperands() == 2 &&
23725 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23726 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23727 SDValue CondRHS = Cond->getOperand(1);
23729 // Look for a general sub with unsigned saturation first.
23730 // x >= y ? x-y : 0 --> subus x, y
23731 // x > y ? x-y : 0 --> subus x, y
23732 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23733 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23734 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23736 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23737 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23738 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23739 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23740 // If the RHS is a constant we have to reverse the const
23741 // canonicalization.
23742 // x > C-1 ? x+-C : 0 --> subus x, C
23743 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23744 CondRHSConst->getAPIntValue() ==
23745 (-OpRHSConst->getAPIntValue() - 1))
23746 return DAG.getNode(
23747 X86ISD::SUBUS, DL, VT, OpLHS,
23748 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23750 // Another special case: If C was a sign bit, the sub has been
23751 // canonicalized into a xor.
23752 // FIXME: Would it be better to use computeKnownBits to determine
23753 // whether it's safe to decanonicalize the xor?
23754 // x s< 0 ? x^C : 0 --> subus x, C
23755 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23756 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23757 OpRHSConst->getAPIntValue().isSignBit())
23758 // Note that we have to rebuild the RHS constant here to ensure we
23759 // don't rely on particular values of undef lanes.
23760 return DAG.getNode(
23761 X86ISD::SUBUS, DL, VT, OpLHS,
23762 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23767 // Simplify vector selection if condition value type matches vselect
23769 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23770 assert(Cond.getValueType().isVector() &&
23771 "vector select expects a vector selector!");
23773 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23774 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23776 // Try invert the condition if true value is not all 1s and false value
23778 if (!TValIsAllOnes && !FValIsAllZeros &&
23779 // Check if the selector will be produced by CMPP*/PCMP*
23780 Cond.getOpcode() == ISD::SETCC &&
23781 // Check if SETCC has already been promoted
23782 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23784 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23785 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23787 if (TValIsAllZeros || FValIsAllOnes) {
23788 SDValue CC = Cond.getOperand(2);
23789 ISD::CondCode NewCC =
23790 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23791 Cond.getOperand(0).getValueType().isInteger());
23792 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23793 std::swap(LHS, RHS);
23794 TValIsAllOnes = FValIsAllOnes;
23795 FValIsAllZeros = TValIsAllZeros;
23799 if (TValIsAllOnes || FValIsAllZeros) {
23802 if (TValIsAllOnes && FValIsAllZeros)
23804 else if (TValIsAllOnes)
23806 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23807 else if (FValIsAllZeros)
23808 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23809 DAG.getBitcast(CondVT, LHS));
23811 return DAG.getBitcast(VT, Ret);
23815 // We should generate an X86ISD::BLENDI from a vselect if its argument
23816 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23817 // constants. This specific pattern gets generated when we split a
23818 // selector for a 512 bit vector in a machine without AVX512 (but with
23819 // 256-bit vectors), during legalization:
23821 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23823 // Iff we find this pattern and the build_vectors are built from
23824 // constants, we translate the vselect into a shuffle_vector that we
23825 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23826 if ((N->getOpcode() == ISD::VSELECT ||
23827 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23828 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23829 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23830 if (Shuffle.getNode())
23834 // If this is a *dynamic* select (non-constant condition) and we can match
23835 // this node with one of the variable blend instructions, restructure the
23836 // condition so that the blends can use the high bit of each element and use
23837 // SimplifyDemandedBits to simplify the condition operand.
23838 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23839 !DCI.isBeforeLegalize() &&
23840 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23841 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23843 // Don't optimize vector selects that map to mask-registers.
23847 // We can only handle the cases where VSELECT is directly legal on the
23848 // subtarget. We custom lower VSELECT nodes with constant conditions and
23849 // this makes it hard to see whether a dynamic VSELECT will correctly
23850 // lower, so we both check the operation's status and explicitly handle the
23851 // cases where a *dynamic* blend will fail even though a constant-condition
23852 // blend could be custom lowered.
23853 // FIXME: We should find a better way to handle this class of problems.
23854 // Potentially, we should combine constant-condition vselect nodes
23855 // pre-legalization into shuffles and not mark as many types as custom
23857 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23859 // FIXME: We don't support i16-element blends currently. We could and
23860 // should support them by making *all* the bits in the condition be set
23861 // rather than just the high bit and using an i8-element blend.
23862 if (VT.getScalarType() == MVT::i16)
23864 // Dynamic blending was only available from SSE4.1 onward.
23865 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23867 // Byte blends are only available in AVX2
23868 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23869 !Subtarget->hasAVX2())
23872 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23873 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23875 APInt KnownZero, KnownOne;
23876 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23877 DCI.isBeforeLegalizeOps());
23878 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23879 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23881 // If we changed the computation somewhere in the DAG, this change
23882 // will affect all users of Cond.
23883 // Make sure it is fine and update all the nodes so that we do not
23884 // use the generic VSELECT anymore. Otherwise, we may perform
23885 // wrong optimizations as we messed up with the actual expectation
23886 // for the vector boolean values.
23887 if (Cond != TLO.Old) {
23888 // Check all uses of that condition operand to check whether it will be
23889 // consumed by non-BLEND instructions, which may depend on all bits are
23891 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23893 if (I->getOpcode() != ISD::VSELECT)
23894 // TODO: Add other opcodes eventually lowered into BLEND.
23897 // Update all the users of the condition, before committing the change,
23898 // so that the VSELECT optimizations that expect the correct vector
23899 // boolean value will not be triggered.
23900 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23902 DAG.ReplaceAllUsesOfValueWith(
23904 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23905 Cond, I->getOperand(1), I->getOperand(2)));
23906 DCI.CommitTargetLoweringOpt(TLO);
23909 // At this point, only Cond is changed. Change the condition
23910 // just for N to keep the opportunity to optimize all other
23911 // users their own way.
23912 DAG.ReplaceAllUsesOfValueWith(
23914 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23915 TLO.New, N->getOperand(1), N->getOperand(2)));
23923 // Check whether a boolean test is testing a boolean value generated by
23924 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23927 // Simplify the following patterns:
23928 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23929 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23930 // to (Op EFLAGS Cond)
23932 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23933 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23934 // to (Op EFLAGS !Cond)
23936 // where Op could be BRCOND or CMOV.
23938 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23939 // Quit if not CMP and SUB with its value result used.
23940 if (Cmp.getOpcode() != X86ISD::CMP &&
23941 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23944 // Quit if not used as a boolean value.
23945 if (CC != X86::COND_E && CC != X86::COND_NE)
23948 // Check CMP operands. One of them should be 0 or 1 and the other should be
23949 // an SetCC or extended from it.
23950 SDValue Op1 = Cmp.getOperand(0);
23951 SDValue Op2 = Cmp.getOperand(1);
23954 const ConstantSDNode* C = nullptr;
23955 bool needOppositeCond = (CC == X86::COND_E);
23956 bool checkAgainstTrue = false; // Is it a comparison against 1?
23958 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23960 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23962 else // Quit if all operands are not constants.
23965 if (C->getZExtValue() == 1) {
23966 needOppositeCond = !needOppositeCond;
23967 checkAgainstTrue = true;
23968 } else if (C->getZExtValue() != 0)
23969 // Quit if the constant is neither 0 or 1.
23972 bool truncatedToBoolWithAnd = false;
23973 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23974 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23975 SetCC.getOpcode() == ISD::TRUNCATE ||
23976 SetCC.getOpcode() == ISD::AND) {
23977 if (SetCC.getOpcode() == ISD::AND) {
23979 ConstantSDNode *CS;
23980 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23981 CS->getZExtValue() == 1)
23983 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23984 CS->getZExtValue() == 1)
23988 SetCC = SetCC.getOperand(OpIdx);
23989 truncatedToBoolWithAnd = true;
23991 SetCC = SetCC.getOperand(0);
23994 switch (SetCC.getOpcode()) {
23995 case X86ISD::SETCC_CARRY:
23996 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23997 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23998 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23999 // truncated to i1 using 'and'.
24000 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24002 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24003 "Invalid use of SETCC_CARRY!");
24005 case X86ISD::SETCC:
24006 // Set the condition code or opposite one if necessary.
24007 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24008 if (needOppositeCond)
24009 CC = X86::GetOppositeBranchCondition(CC);
24010 return SetCC.getOperand(1);
24011 case X86ISD::CMOV: {
24012 // Check whether false/true value has canonical one, i.e. 0 or 1.
24013 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24014 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24015 // Quit if true value is not a constant.
24018 // Quit if false value is not a constant.
24020 SDValue Op = SetCC.getOperand(0);
24021 // Skip 'zext' or 'trunc' node.
24022 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24023 Op.getOpcode() == ISD::TRUNCATE)
24024 Op = Op.getOperand(0);
24025 // A special case for rdrand/rdseed, where 0 is set if false cond is
24027 if ((Op.getOpcode() != X86ISD::RDRAND &&
24028 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24031 // Quit if false value is not the constant 0 or 1.
24032 bool FValIsFalse = true;
24033 if (FVal && FVal->getZExtValue() != 0) {
24034 if (FVal->getZExtValue() != 1)
24036 // If FVal is 1, opposite cond is needed.
24037 needOppositeCond = !needOppositeCond;
24038 FValIsFalse = false;
24040 // Quit if TVal is not the constant opposite of FVal.
24041 if (FValIsFalse && TVal->getZExtValue() != 1)
24043 if (!FValIsFalse && TVal->getZExtValue() != 0)
24045 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24046 if (needOppositeCond)
24047 CC = X86::GetOppositeBranchCondition(CC);
24048 return SetCC.getOperand(3);
24055 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24057 /// (X86or (X86setcc) (X86setcc))
24058 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24059 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24060 X86::CondCode &CC1, SDValue &Flags,
24062 if (Cond->getOpcode() == X86ISD::CMP) {
24063 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24064 if (!CondOp1C || !CondOp1C->isNullValue())
24067 Cond = Cond->getOperand(0);
24072 SDValue SetCC0, SetCC1;
24073 switch (Cond->getOpcode()) {
24074 default: return false;
24081 SetCC0 = Cond->getOperand(0);
24082 SetCC1 = Cond->getOperand(1);
24086 // Make sure we have SETCC nodes, using the same flags value.
24087 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24088 SetCC1.getOpcode() != X86ISD::SETCC ||
24089 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24092 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24093 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24094 Flags = SetCC0->getOperand(1);
24098 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24099 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24100 TargetLowering::DAGCombinerInfo &DCI,
24101 const X86Subtarget *Subtarget) {
24104 // If the flag operand isn't dead, don't touch this CMOV.
24105 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24108 SDValue FalseOp = N->getOperand(0);
24109 SDValue TrueOp = N->getOperand(1);
24110 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24111 SDValue Cond = N->getOperand(3);
24113 if (CC == X86::COND_E || CC == X86::COND_NE) {
24114 switch (Cond.getOpcode()) {
24118 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24119 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24120 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24126 Flags = checkBoolTestSetCCCombine(Cond, CC);
24127 if (Flags.getNode() &&
24128 // Extra check as FCMOV only supports a subset of X86 cond.
24129 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24130 SDValue Ops[] = { FalseOp, TrueOp,
24131 DAG.getConstant(CC, DL, MVT::i8), Flags };
24132 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24135 // If this is a select between two integer constants, try to do some
24136 // optimizations. Note that the operands are ordered the opposite of SELECT
24138 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24139 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24140 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24141 // larger than FalseC (the false value).
24142 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24143 CC = X86::GetOppositeBranchCondition(CC);
24144 std::swap(TrueC, FalseC);
24145 std::swap(TrueOp, FalseOp);
24148 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24149 // This is efficient for any integer data type (including i8/i16) and
24151 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24152 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24153 DAG.getConstant(CC, DL, MVT::i8), Cond);
24155 // Zero extend the condition if needed.
24156 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24158 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24159 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24160 DAG.getConstant(ShAmt, DL, MVT::i8));
24161 if (N->getNumValues() == 2) // Dead flag value?
24162 return DCI.CombineTo(N, Cond, SDValue());
24166 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24167 // for any integer data type, including i8/i16.
24168 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24169 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24170 DAG.getConstant(CC, DL, MVT::i8), Cond);
24172 // Zero extend the condition if needed.
24173 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24174 FalseC->getValueType(0), Cond);
24175 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24176 SDValue(FalseC, 0));
24178 if (N->getNumValues() == 2) // Dead flag value?
24179 return DCI.CombineTo(N, Cond, SDValue());
24183 // Optimize cases that will turn into an LEA instruction. This requires
24184 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24185 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24186 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24187 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24189 bool isFastMultiplier = false;
24191 switch ((unsigned char)Diff) {
24193 case 1: // result = add base, cond
24194 case 2: // result = lea base( , cond*2)
24195 case 3: // result = lea base(cond, cond*2)
24196 case 4: // result = lea base( , cond*4)
24197 case 5: // result = lea base(cond, cond*4)
24198 case 8: // result = lea base( , cond*8)
24199 case 9: // result = lea base(cond, cond*8)
24200 isFastMultiplier = true;
24205 if (isFastMultiplier) {
24206 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24207 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24208 DAG.getConstant(CC, DL, MVT::i8), Cond);
24209 // Zero extend the condition if needed.
24210 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24212 // Scale the condition by the difference.
24214 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24215 DAG.getConstant(Diff, DL, Cond.getValueType()));
24217 // Add the base if non-zero.
24218 if (FalseC->getAPIntValue() != 0)
24219 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24220 SDValue(FalseC, 0));
24221 if (N->getNumValues() == 2) // Dead flag value?
24222 return DCI.CombineTo(N, Cond, SDValue());
24229 // Handle these cases:
24230 // (select (x != c), e, c) -> select (x != c), e, x),
24231 // (select (x == c), c, e) -> select (x == c), x, e)
24232 // where the c is an integer constant, and the "select" is the combination
24233 // of CMOV and CMP.
24235 // The rationale for this change is that the conditional-move from a constant
24236 // needs two instructions, however, conditional-move from a register needs
24237 // only one instruction.
24239 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24240 // some instruction-combining opportunities. This opt needs to be
24241 // postponed as late as possible.
24243 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24244 // the DCI.xxxx conditions are provided to postpone the optimization as
24245 // late as possible.
24247 ConstantSDNode *CmpAgainst = nullptr;
24248 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24249 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24250 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24252 if (CC == X86::COND_NE &&
24253 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24254 CC = X86::GetOppositeBranchCondition(CC);
24255 std::swap(TrueOp, FalseOp);
24258 if (CC == X86::COND_E &&
24259 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24260 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24261 DAG.getConstant(CC, DL, MVT::i8), Cond };
24262 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24267 // Fold and/or of setcc's to double CMOV:
24268 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24269 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24271 // This combine lets us generate:
24272 // cmovcc1 (jcc1 if we don't have CMOV)
24278 // cmovne (jne if we don't have CMOV)
24279 // When we can't use the CMOV instruction, it might increase branch
24281 // When we can use CMOV, or when there is no mispredict, this improves
24282 // throughput and reduces register pressure.
24284 if (CC == X86::COND_NE) {
24286 X86::CondCode CC0, CC1;
24288 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24290 std::swap(FalseOp, TrueOp);
24291 CC0 = X86::GetOppositeBranchCondition(CC0);
24292 CC1 = X86::GetOppositeBranchCondition(CC1);
24295 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24297 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24298 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24299 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24308 /// PerformMulCombine - Optimize a single multiply with constant into two
24309 /// in order to implement it with two cheaper instructions, e.g.
24310 /// LEA + SHL, LEA + LEA.
24311 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24312 TargetLowering::DAGCombinerInfo &DCI) {
24313 // An imul is usually smaller than the alternative sequence.
24314 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24317 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24320 EVT VT = N->getValueType(0);
24321 if (VT != MVT::i64 && VT != MVT::i32)
24324 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24327 uint64_t MulAmt = C->getZExtValue();
24328 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24331 uint64_t MulAmt1 = 0;
24332 uint64_t MulAmt2 = 0;
24333 if ((MulAmt % 9) == 0) {
24335 MulAmt2 = MulAmt / 9;
24336 } else if ((MulAmt % 5) == 0) {
24338 MulAmt2 = MulAmt / 5;
24339 } else if ((MulAmt % 3) == 0) {
24341 MulAmt2 = MulAmt / 3;
24344 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24347 if (isPowerOf2_64(MulAmt2) &&
24348 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24349 // If second multiplifer is pow2, issue it first. We want the multiply by
24350 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24352 std::swap(MulAmt1, MulAmt2);
24355 if (isPowerOf2_64(MulAmt1))
24356 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24357 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24359 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24360 DAG.getConstant(MulAmt1, DL, VT));
24362 if (isPowerOf2_64(MulAmt2))
24363 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24364 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24366 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24367 DAG.getConstant(MulAmt2, DL, VT));
24369 // Do not add new nodes to DAG combiner worklist.
24370 DCI.CombineTo(N, NewMul, false);
24375 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24376 SDValue N0 = N->getOperand(0);
24377 SDValue N1 = N->getOperand(1);
24378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24379 EVT VT = N0.getValueType();
24381 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24382 // since the result of setcc_c is all zero's or all ones.
24383 if (VT.isInteger() && !VT.isVector() &&
24384 N1C && N0.getOpcode() == ISD::AND &&
24385 N0.getOperand(1).getOpcode() == ISD::Constant) {
24386 SDValue N00 = N0.getOperand(0);
24387 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24388 APInt ShAmt = N1C->getAPIntValue();
24389 Mask = Mask.shl(ShAmt);
24390 bool MaskOK = false;
24391 // We can handle cases concerning bit-widening nodes containing setcc_c if
24392 // we carefully interrogate the mask to make sure we are semantics
24394 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24395 // of the underlying setcc_c operation if the setcc_c was zero extended.
24396 // Consider the following example:
24397 // zext(setcc_c) -> i32 0x0000FFFF
24398 // c1 -> i32 0x0000FFFF
24399 // c2 -> i32 0x00000001
24400 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24401 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24402 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24404 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24405 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24407 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24408 N00.getOpcode() == ISD::ANY_EXTEND) &&
24409 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24410 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24412 if (MaskOK && Mask != 0) {
24414 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24418 // Hardware support for vector shifts is sparse which makes us scalarize the
24419 // vector operations in many cases. Also, on sandybridge ADD is faster than
24421 // (shl V, 1) -> add V,V
24422 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24423 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24424 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24425 // We shift all of the values by one. In many cases we do not have
24426 // hardware support for this operation. This is better expressed as an ADD
24428 if (N1SplatC->getAPIntValue() == 1)
24429 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24435 /// \brief Returns a vector of 0s if the node in input is a vector logical
24436 /// shift by a constant amount which is known to be bigger than or equal
24437 /// to the vector element size in bits.
24438 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24439 const X86Subtarget *Subtarget) {
24440 EVT VT = N->getValueType(0);
24442 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24443 (!Subtarget->hasInt256() ||
24444 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24447 SDValue Amt = N->getOperand(1);
24449 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24450 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24451 APInt ShiftAmt = AmtSplat->getAPIntValue();
24452 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24454 // SSE2/AVX2 logical shifts always return a vector of 0s
24455 // if the shift amount is bigger than or equal to
24456 // the element size. The constant shift amount will be
24457 // encoded as a 8-bit immediate.
24458 if (ShiftAmt.trunc(8).uge(MaxAmount))
24459 return getZeroVector(VT, Subtarget, DAG, DL);
24465 /// PerformShiftCombine - Combine shifts.
24466 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24467 TargetLowering::DAGCombinerInfo &DCI,
24468 const X86Subtarget *Subtarget) {
24469 if (N->getOpcode() == ISD::SHL)
24470 if (SDValue V = PerformSHLCombine(N, DAG))
24473 // Try to fold this logical shift into a zero vector.
24474 if (N->getOpcode() != ISD::SRA)
24475 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24481 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24482 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24483 // and friends. Likewise for OR -> CMPNEQSS.
24484 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24485 TargetLowering::DAGCombinerInfo &DCI,
24486 const X86Subtarget *Subtarget) {
24489 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24490 // we're requiring SSE2 for both.
24491 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24492 SDValue N0 = N->getOperand(0);
24493 SDValue N1 = N->getOperand(1);
24494 SDValue CMP0 = N0->getOperand(1);
24495 SDValue CMP1 = N1->getOperand(1);
24498 // The SETCCs should both refer to the same CMP.
24499 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24502 SDValue CMP00 = CMP0->getOperand(0);
24503 SDValue CMP01 = CMP0->getOperand(1);
24504 EVT VT = CMP00.getValueType();
24506 if (VT == MVT::f32 || VT == MVT::f64) {
24507 bool ExpectingFlags = false;
24508 // Check for any users that want flags:
24509 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24510 !ExpectingFlags && UI != UE; ++UI)
24511 switch (UI->getOpcode()) {
24516 ExpectingFlags = true;
24518 case ISD::CopyToReg:
24519 case ISD::SIGN_EXTEND:
24520 case ISD::ZERO_EXTEND:
24521 case ISD::ANY_EXTEND:
24525 if (!ExpectingFlags) {
24526 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24527 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24529 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24530 X86::CondCode tmp = cc0;
24535 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24536 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24537 // FIXME: need symbolic constants for these magic numbers.
24538 // See X86ATTInstPrinter.cpp:printSSECC().
24539 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24540 if (Subtarget->hasAVX512()) {
24541 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24543 DAG.getConstant(x86cc, DL, MVT::i8));
24544 if (N->getValueType(0) != MVT::i1)
24545 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24549 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24550 CMP00.getValueType(), CMP00, CMP01,
24551 DAG.getConstant(x86cc, DL,
24554 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24555 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24557 if (is64BitFP && !Subtarget->is64Bit()) {
24558 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24559 // 64-bit integer, since that's not a legal type. Since
24560 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24561 // bits, but can do this little dance to extract the lowest 32 bits
24562 // and work with those going forward.
24563 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24565 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24566 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24567 Vector32, DAG.getIntPtrConstant(0, DL));
24571 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24572 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24573 DAG.getConstant(1, DL, IntVT));
24574 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24576 return OneBitOfTruth;
24584 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24585 /// so it can be folded inside ANDNP.
24586 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24587 EVT VT = N->getValueType(0);
24589 // Match direct AllOnes for 128 and 256-bit vectors
24590 if (ISD::isBuildVectorAllOnes(N))
24593 // Look through a bit convert.
24594 if (N->getOpcode() == ISD::BITCAST)
24595 N = N->getOperand(0).getNode();
24597 // Sometimes the operand may come from a insert_subvector building a 256-bit
24599 if (VT.is256BitVector() &&
24600 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24601 SDValue V1 = N->getOperand(0);
24602 SDValue V2 = N->getOperand(1);
24604 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24605 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24606 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24607 ISD::isBuildVectorAllOnes(V2.getNode()))
24614 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24615 // register. In most cases we actually compare or select YMM-sized registers
24616 // and mixing the two types creates horrible code. This method optimizes
24617 // some of the transition sequences.
24618 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24619 TargetLowering::DAGCombinerInfo &DCI,
24620 const X86Subtarget *Subtarget) {
24621 EVT VT = N->getValueType(0);
24622 if (!VT.is256BitVector())
24625 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24626 N->getOpcode() == ISD::ZERO_EXTEND ||
24627 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24629 SDValue Narrow = N->getOperand(0);
24630 EVT NarrowVT = Narrow->getValueType(0);
24631 if (!NarrowVT.is128BitVector())
24634 if (Narrow->getOpcode() != ISD::XOR &&
24635 Narrow->getOpcode() != ISD::AND &&
24636 Narrow->getOpcode() != ISD::OR)
24639 SDValue N0 = Narrow->getOperand(0);
24640 SDValue N1 = Narrow->getOperand(1);
24643 // The Left side has to be a trunc.
24644 if (N0.getOpcode() != ISD::TRUNCATE)
24647 // The type of the truncated inputs.
24648 EVT WideVT = N0->getOperand(0)->getValueType(0);
24652 // The right side has to be a 'trunc' or a constant vector.
24653 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24654 ConstantSDNode *RHSConstSplat = nullptr;
24655 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24656 RHSConstSplat = RHSBV->getConstantSplatNode();
24657 if (!RHSTrunc && !RHSConstSplat)
24660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24662 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24665 // Set N0 and N1 to hold the inputs to the new wide operation.
24666 N0 = N0->getOperand(0);
24667 if (RHSConstSplat) {
24668 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24669 SDValue(RHSConstSplat, 0));
24670 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24671 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24672 } else if (RHSTrunc) {
24673 N1 = N1->getOperand(0);
24676 // Generate the wide operation.
24677 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24678 unsigned Opcode = N->getOpcode();
24680 case ISD::ANY_EXTEND:
24682 case ISD::ZERO_EXTEND: {
24683 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24684 APInt Mask = APInt::getAllOnesValue(InBits);
24685 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24686 return DAG.getNode(ISD::AND, DL, VT,
24687 Op, DAG.getConstant(Mask, DL, VT));
24689 case ISD::SIGN_EXTEND:
24690 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24691 Op, DAG.getValueType(NarrowVT));
24693 llvm_unreachable("Unexpected opcode");
24697 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24698 TargetLowering::DAGCombinerInfo &DCI,
24699 const X86Subtarget *Subtarget) {
24700 SDValue N0 = N->getOperand(0);
24701 SDValue N1 = N->getOperand(1);
24704 // A vector zext_in_reg may be represented as a shuffle,
24705 // feeding into a bitcast (this represents anyext) feeding into
24706 // an and with a mask.
24707 // We'd like to try to combine that into a shuffle with zero
24708 // plus a bitcast, removing the and.
24709 if (N0.getOpcode() != ISD::BITCAST ||
24710 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24713 // The other side of the AND should be a splat of 2^C, where C
24714 // is the number of bits in the source type.
24715 if (N1.getOpcode() == ISD::BITCAST)
24716 N1 = N1.getOperand(0);
24717 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24719 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24721 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24722 EVT SrcType = Shuffle->getValueType(0);
24724 // We expect a single-source shuffle
24725 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24728 unsigned SrcSize = SrcType.getScalarSizeInBits();
24730 APInt SplatValue, SplatUndef;
24731 unsigned SplatBitSize;
24733 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24734 SplatBitSize, HasAnyUndefs))
24737 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24738 // Make sure the splat matches the mask we expect
24739 if (SplatBitSize > ResSize ||
24740 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24743 // Make sure the input and output size make sense
24744 if (SrcSize >= ResSize || ResSize % SrcSize)
24747 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24748 // The number of u's between each two values depends on the ratio between
24749 // the source and dest type.
24750 unsigned ZextRatio = ResSize / SrcSize;
24751 bool IsZext = true;
24752 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24753 if (i % ZextRatio) {
24754 if (Shuffle->getMaskElt(i) > 0) {
24760 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24761 // Expected element number
24771 // Ok, perform the transformation - replace the shuffle with
24772 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24773 // (instead of undef) where the k elements come from the zero vector.
24774 SmallVector<int, 8> Mask;
24775 unsigned NumElems = SrcType.getVectorNumElements();
24776 for (unsigned i = 0; i < NumElems; ++i)
24778 Mask.push_back(NumElems);
24780 Mask.push_back(i / ZextRatio);
24782 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24783 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24784 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24787 /// If both input operands of a logic op are being cast from floating point
24788 /// types, try to convert this into a floating point logic node to avoid
24789 /// unnecessary moves from SSE to integer registers.
24790 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24791 const X86Subtarget *Subtarget) {
24792 unsigned FPOpcode = ISD::DELETED_NODE;
24793 if (N->getOpcode() == ISD::AND)
24794 FPOpcode = X86ISD::FAND;
24795 else if (N->getOpcode() == ISD::OR)
24796 FPOpcode = X86ISD::FOR;
24797 else if (N->getOpcode() == ISD::XOR)
24798 FPOpcode = X86ISD::FXOR;
24800 assert(FPOpcode != ISD::DELETED_NODE &&
24801 "Unexpected input node for FP logic conversion");
24803 EVT VT = N->getValueType(0);
24804 SDValue N0 = N->getOperand(0);
24805 SDValue N1 = N->getOperand(1);
24807 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24808 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24809 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24810 SDValue N00 = N0.getOperand(0);
24811 SDValue N10 = N1.getOperand(0);
24812 EVT N00Type = N00.getValueType();
24813 EVT N10Type = N10.getValueType();
24814 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24815 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24816 return DAG.getBitcast(VT, FPLogic);
24822 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24823 TargetLowering::DAGCombinerInfo &DCI,
24824 const X86Subtarget *Subtarget) {
24825 if (DCI.isBeforeLegalizeOps())
24828 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24831 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24834 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24837 EVT VT = N->getValueType(0);
24838 SDValue N0 = N->getOperand(0);
24839 SDValue N1 = N->getOperand(1);
24842 // Create BEXTR instructions
24843 // BEXTR is ((X >> imm) & (2**size-1))
24844 if (VT == MVT::i32 || VT == MVT::i64) {
24845 // Check for BEXTR.
24846 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24847 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24848 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24849 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24850 if (MaskNode && ShiftNode) {
24851 uint64_t Mask = MaskNode->getZExtValue();
24852 uint64_t Shift = ShiftNode->getZExtValue();
24853 if (isMask_64(Mask)) {
24854 uint64_t MaskSize = countPopulation(Mask);
24855 if (Shift + MaskSize <= VT.getSizeInBits())
24856 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24857 DAG.getConstant(Shift | (MaskSize << 8), DL,
24866 // Want to form ANDNP nodes:
24867 // 1) In the hopes of then easily combining them with OR and AND nodes
24868 // to form PBLEND/PSIGN.
24869 // 2) To match ANDN packed intrinsics
24870 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24873 // Check LHS for vnot
24874 if (N0.getOpcode() == ISD::XOR &&
24875 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24876 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24877 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24879 // Check RHS for vnot
24880 if (N1.getOpcode() == ISD::XOR &&
24881 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24882 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24883 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24888 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24889 TargetLowering::DAGCombinerInfo &DCI,
24890 const X86Subtarget *Subtarget) {
24891 if (DCI.isBeforeLegalizeOps())
24894 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24897 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24900 SDValue N0 = N->getOperand(0);
24901 SDValue N1 = N->getOperand(1);
24902 EVT VT = N->getValueType(0);
24904 // look for psign/blend
24905 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24906 if (!Subtarget->hasSSSE3() ||
24907 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24910 // Canonicalize pandn to RHS
24911 if (N0.getOpcode() == X86ISD::ANDNP)
24913 // or (and (m, y), (pandn m, x))
24914 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24915 SDValue Mask = N1.getOperand(0);
24916 SDValue X = N1.getOperand(1);
24918 if (N0.getOperand(0) == Mask)
24919 Y = N0.getOperand(1);
24920 if (N0.getOperand(1) == Mask)
24921 Y = N0.getOperand(0);
24923 // Check to see if the mask appeared in both the AND and ANDNP and
24927 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24928 // Look through mask bitcast.
24929 if (Mask.getOpcode() == ISD::BITCAST)
24930 Mask = Mask.getOperand(0);
24931 if (X.getOpcode() == ISD::BITCAST)
24932 X = X.getOperand(0);
24933 if (Y.getOpcode() == ISD::BITCAST)
24934 Y = Y.getOperand(0);
24936 EVT MaskVT = Mask.getValueType();
24938 // Validate that the Mask operand is a vector sra node.
24939 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24940 // there is no psrai.b
24941 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24942 unsigned SraAmt = ~0;
24943 if (Mask.getOpcode() == ISD::SRA) {
24944 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24945 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24946 SraAmt = AmtConst->getZExtValue();
24947 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24948 SDValue SraC = Mask.getOperand(1);
24949 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24951 if ((SraAmt + 1) != EltBits)
24956 // Now we know we at least have a plendvb with the mask val. See if
24957 // we can form a psignb/w/d.
24958 // psign = x.type == y.type == mask.type && y = sub(0, x);
24959 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24960 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24961 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24962 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24963 "Unsupported VT for PSIGN");
24964 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24965 return DAG.getBitcast(VT, Mask);
24967 // PBLENDVB only available on SSE 4.1
24968 if (!Subtarget->hasSSE41())
24971 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24973 X = DAG.getBitcast(BlendVT, X);
24974 Y = DAG.getBitcast(BlendVT, Y);
24975 Mask = DAG.getBitcast(BlendVT, Mask);
24976 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24977 return DAG.getBitcast(VT, Mask);
24981 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24984 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24985 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24987 // SHLD/SHRD instructions have lower register pressure, but on some
24988 // platforms they have higher latency than the equivalent
24989 // series of shifts/or that would otherwise be generated.
24990 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24991 // have higher latencies and we are not optimizing for size.
24992 if (!OptForSize && Subtarget->isSHLDSlow())
24995 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24997 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24999 if (!N0.hasOneUse() || !N1.hasOneUse())
25002 SDValue ShAmt0 = N0.getOperand(1);
25003 if (ShAmt0.getValueType() != MVT::i8)
25005 SDValue ShAmt1 = N1.getOperand(1);
25006 if (ShAmt1.getValueType() != MVT::i8)
25008 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25009 ShAmt0 = ShAmt0.getOperand(0);
25010 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25011 ShAmt1 = ShAmt1.getOperand(0);
25014 unsigned Opc = X86ISD::SHLD;
25015 SDValue Op0 = N0.getOperand(0);
25016 SDValue Op1 = N1.getOperand(0);
25017 if (ShAmt0.getOpcode() == ISD::SUB) {
25018 Opc = X86ISD::SHRD;
25019 std::swap(Op0, Op1);
25020 std::swap(ShAmt0, ShAmt1);
25023 unsigned Bits = VT.getSizeInBits();
25024 if (ShAmt1.getOpcode() == ISD::SUB) {
25025 SDValue Sum = ShAmt1.getOperand(0);
25026 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25027 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25028 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25029 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25030 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25031 return DAG.getNode(Opc, DL, VT,
25033 DAG.getNode(ISD::TRUNCATE, DL,
25036 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25037 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25039 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25040 return DAG.getNode(Opc, DL, VT,
25041 N0.getOperand(0), N1.getOperand(0),
25042 DAG.getNode(ISD::TRUNCATE, DL,
25049 // Generate NEG and CMOV for integer abs.
25050 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25051 EVT VT = N->getValueType(0);
25053 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25054 // 8-bit integer abs to NEG and CMOV.
25055 if (VT.isInteger() && VT.getSizeInBits() == 8)
25058 SDValue N0 = N->getOperand(0);
25059 SDValue N1 = N->getOperand(1);
25062 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25063 // and change it to SUB and CMOV.
25064 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25065 N0.getOpcode() == ISD::ADD &&
25066 N0.getOperand(1) == N1 &&
25067 N1.getOpcode() == ISD::SRA &&
25068 N1.getOperand(0) == N0.getOperand(0))
25069 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25070 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25071 // Generate SUB & CMOV.
25072 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25073 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25075 SDValue Ops[] = { N0.getOperand(0), Neg,
25076 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25077 SDValue(Neg.getNode(), 1) };
25078 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25083 // Try to turn tests against the signbit in the form of:
25084 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25087 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25088 // This is only worth doing if the output type is i8.
25089 if (N->getValueType(0) != MVT::i8)
25092 SDValue N0 = N->getOperand(0);
25093 SDValue N1 = N->getOperand(1);
25095 // We should be performing an xor against a truncated shift.
25096 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25099 // Make sure we are performing an xor against one.
25100 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25103 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25104 SDValue Shift = N0.getOperand(0);
25105 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25108 // Make sure we are truncating from one of i16, i32 or i64.
25109 EVT ShiftTy = Shift.getValueType();
25110 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25113 // Make sure the shift amount extracts the sign bit.
25114 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25115 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25118 // Create a greater-than comparison against -1.
25119 // N.B. Using SETGE against 0 works but we want a canonical looking
25120 // comparison, using SETGT matches up with what TranslateX86CC.
25122 SDValue ShiftOp = Shift.getOperand(0);
25123 EVT ShiftOpTy = ShiftOp.getValueType();
25124 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25125 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25129 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25130 TargetLowering::DAGCombinerInfo &DCI,
25131 const X86Subtarget *Subtarget) {
25132 if (DCI.isBeforeLegalizeOps())
25135 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25138 if (Subtarget->hasCMov())
25139 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25142 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25148 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25149 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25150 TargetLowering::DAGCombinerInfo &DCI,
25151 const X86Subtarget *Subtarget) {
25152 LoadSDNode *Ld = cast<LoadSDNode>(N);
25153 EVT RegVT = Ld->getValueType(0);
25154 EVT MemVT = Ld->getMemoryVT();
25156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25158 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25159 // into two 16-byte operations.
25160 ISD::LoadExtType Ext = Ld->getExtensionType();
25162 unsigned AddressSpace = Ld->getAddressSpace();
25163 unsigned Alignment = Ld->getAlignment();
25164 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25165 Ext == ISD::NON_EXTLOAD &&
25166 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25167 AddressSpace, Alignment, &Fast) && !Fast) {
25168 unsigned NumElems = RegVT.getVectorNumElements();
25172 SDValue Ptr = Ld->getBasePtr();
25173 SDValue Increment =
25174 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25176 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25178 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25179 Ld->getPointerInfo(), Ld->isVolatile(),
25180 Ld->isNonTemporal(), Ld->isInvariant(),
25182 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25183 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25184 Ld->getPointerInfo(), Ld->isVolatile(),
25185 Ld->isNonTemporal(), Ld->isInvariant(),
25186 std::min(16U, Alignment));
25187 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25189 Load2.getValue(1));
25191 SDValue NewVec = DAG.getUNDEF(RegVT);
25192 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25193 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25194 return DCI.CombineTo(N, NewVec, TF, true);
25200 /// PerformMLOADCombine - Resolve extending loads
25201 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25202 TargetLowering::DAGCombinerInfo &DCI,
25203 const X86Subtarget *Subtarget) {
25204 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25205 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25208 EVT VT = Mld->getValueType(0);
25209 unsigned NumElems = VT.getVectorNumElements();
25210 EVT LdVT = Mld->getMemoryVT();
25213 assert(LdVT != VT && "Cannot extend to the same type");
25214 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25215 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25216 // From, To sizes and ElemCount must be pow of two
25217 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25218 "Unexpected size for extending masked load");
25220 unsigned SizeRatio = ToSz / FromSz;
25221 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25223 // Create a type on which we perform the shuffle
25224 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25225 LdVT.getScalarType(), NumElems*SizeRatio);
25226 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25228 // Convert Src0 value
25229 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25230 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25231 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25232 for (unsigned i = 0; i != NumElems; ++i)
25233 ShuffleVec[i] = i * SizeRatio;
25235 // Can't shuffle using an illegal type.
25236 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25237 "WideVecVT should be legal");
25238 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25239 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25241 // Prepare the new mask
25243 SDValue Mask = Mld->getMask();
25244 if (Mask.getValueType() == VT) {
25245 // Mask and original value have the same type
25246 NewMask = DAG.getBitcast(WideVecVT, Mask);
25247 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25248 for (unsigned i = 0; i != NumElems; ++i)
25249 ShuffleVec[i] = i * SizeRatio;
25250 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25251 ShuffleVec[i] = NumElems*SizeRatio;
25252 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25253 DAG.getConstant(0, dl, WideVecVT),
25257 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25258 unsigned WidenNumElts = NumElems*SizeRatio;
25259 unsigned MaskNumElts = VT.getVectorNumElements();
25260 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25263 unsigned NumConcat = WidenNumElts / MaskNumElts;
25264 SmallVector<SDValue, 16> Ops(NumConcat);
25265 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25267 for (unsigned i = 1; i != NumConcat; ++i)
25270 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25273 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25274 Mld->getBasePtr(), NewMask, WideSrc0,
25275 Mld->getMemoryVT(), Mld->getMemOperand(),
25277 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25278 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25280 /// PerformMSTORECombine - Resolve truncating stores
25281 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25282 const X86Subtarget *Subtarget) {
25283 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25284 if (!Mst->isTruncatingStore())
25287 EVT VT = Mst->getValue().getValueType();
25288 unsigned NumElems = VT.getVectorNumElements();
25289 EVT StVT = Mst->getMemoryVT();
25292 assert(StVT != VT && "Cannot truncate to the same type");
25293 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25294 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25298 // The truncating store is legal in some cases. For example
25299 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25300 // are designated for truncate store.
25301 // In this case we don't need any further transformations.
25302 if (TLI.isTruncStoreLegal(VT, StVT))
25305 // From, To sizes and ElemCount must be pow of two
25306 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25307 "Unexpected size for truncating masked store");
25308 // We are going to use the original vector elt for storing.
25309 // Accumulated smaller vector elements must be a multiple of the store size.
25310 assert (((NumElems * FromSz) % ToSz) == 0 &&
25311 "Unexpected ratio for truncating masked store");
25313 unsigned SizeRatio = FromSz / ToSz;
25314 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25316 // Create a type on which we perform the shuffle
25317 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25318 StVT.getScalarType(), NumElems*SizeRatio);
25320 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25322 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25323 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25324 for (unsigned i = 0; i != NumElems; ++i)
25325 ShuffleVec[i] = i * SizeRatio;
25327 // Can't shuffle using an illegal type.
25328 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25329 "WideVecVT should be legal");
25331 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25332 DAG.getUNDEF(WideVecVT),
25336 SDValue Mask = Mst->getMask();
25337 if (Mask.getValueType() == VT) {
25338 // Mask and original value have the same type
25339 NewMask = DAG.getBitcast(WideVecVT, Mask);
25340 for (unsigned i = 0; i != NumElems; ++i)
25341 ShuffleVec[i] = i * SizeRatio;
25342 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25343 ShuffleVec[i] = NumElems*SizeRatio;
25344 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25345 DAG.getConstant(0, dl, WideVecVT),
25349 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25350 unsigned WidenNumElts = NumElems*SizeRatio;
25351 unsigned MaskNumElts = VT.getVectorNumElements();
25352 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25355 unsigned NumConcat = WidenNumElts / MaskNumElts;
25356 SmallVector<SDValue, 16> Ops(NumConcat);
25357 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25359 for (unsigned i = 1; i != NumConcat; ++i)
25362 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25365 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25366 NewMask, StVT, Mst->getMemOperand(), false);
25368 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25369 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25370 const X86Subtarget *Subtarget) {
25371 StoreSDNode *St = cast<StoreSDNode>(N);
25372 EVT VT = St->getValue().getValueType();
25373 EVT StVT = St->getMemoryVT();
25375 SDValue StoredVal = St->getOperand(1);
25376 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25378 // If we are saving a concatenation of two XMM registers and 32-byte stores
25379 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25381 unsigned AddressSpace = St->getAddressSpace();
25382 unsigned Alignment = St->getAlignment();
25383 if (VT.is256BitVector() && StVT == VT &&
25384 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25385 AddressSpace, Alignment, &Fast) && !Fast) {
25386 unsigned NumElems = VT.getVectorNumElements();
25390 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25391 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25394 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25395 SDValue Ptr0 = St->getBasePtr();
25396 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25398 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25399 St->getPointerInfo(), St->isVolatile(),
25400 St->isNonTemporal(), Alignment);
25401 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25402 St->getPointerInfo(), St->isVolatile(),
25403 St->isNonTemporal(),
25404 std::min(16U, Alignment));
25405 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25408 // Optimize trunc store (of multiple scalars) to shuffle and store.
25409 // First, pack all of the elements in one place. Next, store to memory
25410 // in fewer chunks.
25411 if (St->isTruncatingStore() && VT.isVector()) {
25412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25413 unsigned NumElems = VT.getVectorNumElements();
25414 assert(StVT != VT && "Cannot truncate to the same type");
25415 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25416 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25418 // The truncating store is legal in some cases. For example
25419 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25420 // are designated for truncate store.
25421 // In this case we don't need any further transformations.
25422 if (TLI.isTruncStoreLegal(VT, StVT))
25425 // From, To sizes and ElemCount must be pow of two
25426 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25427 // We are going to use the original vector elt for storing.
25428 // Accumulated smaller vector elements must be a multiple of the store size.
25429 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25431 unsigned SizeRatio = FromSz / ToSz;
25433 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25435 // Create a type on which we perform the shuffle
25436 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25437 StVT.getScalarType(), NumElems*SizeRatio);
25439 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25441 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25442 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25443 for (unsigned i = 0; i != NumElems; ++i)
25444 ShuffleVec[i] = i * SizeRatio;
25446 // Can't shuffle using an illegal type.
25447 if (!TLI.isTypeLegal(WideVecVT))
25450 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25451 DAG.getUNDEF(WideVecVT),
25453 // At this point all of the data is stored at the bottom of the
25454 // register. We now need to save it to mem.
25456 // Find the largest store unit
25457 MVT StoreType = MVT::i8;
25458 for (MVT Tp : MVT::integer_valuetypes()) {
25459 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25463 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25464 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25465 (64 <= NumElems * ToSz))
25466 StoreType = MVT::f64;
25468 // Bitcast the original vector into a vector of store-size units
25469 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25470 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25471 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25472 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25473 SmallVector<SDValue, 8> Chains;
25474 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25475 TLI.getPointerTy(DAG.getDataLayout()));
25476 SDValue Ptr = St->getBasePtr();
25478 // Perform one or more big stores into memory.
25479 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25480 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25481 StoreType, ShuffWide,
25482 DAG.getIntPtrConstant(i, dl));
25483 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25484 St->getPointerInfo(), St->isVolatile(),
25485 St->isNonTemporal(), St->getAlignment());
25486 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25487 Chains.push_back(Ch);
25490 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25493 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25494 // the FP state in cases where an emms may be missing.
25495 // A preferable solution to the general problem is to figure out the right
25496 // places to insert EMMS. This qualifies as a quick hack.
25498 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25499 if (VT.getSizeInBits() != 64)
25502 const Function *F = DAG.getMachineFunction().getFunction();
25503 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25505 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25506 if ((VT.isVector() ||
25507 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25508 isa<LoadSDNode>(St->getValue()) &&
25509 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25510 St->getChain().hasOneUse() && !St->isVolatile()) {
25511 SDNode* LdVal = St->getValue().getNode();
25512 LoadSDNode *Ld = nullptr;
25513 int TokenFactorIndex = -1;
25514 SmallVector<SDValue, 8> Ops;
25515 SDNode* ChainVal = St->getChain().getNode();
25516 // Must be a store of a load. We currently handle two cases: the load
25517 // is a direct child, and it's under an intervening TokenFactor. It is
25518 // possible to dig deeper under nested TokenFactors.
25519 if (ChainVal == LdVal)
25520 Ld = cast<LoadSDNode>(St->getChain());
25521 else if (St->getValue().hasOneUse() &&
25522 ChainVal->getOpcode() == ISD::TokenFactor) {
25523 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25524 if (ChainVal->getOperand(i).getNode() == LdVal) {
25525 TokenFactorIndex = i;
25526 Ld = cast<LoadSDNode>(St->getValue());
25528 Ops.push_back(ChainVal->getOperand(i));
25532 if (!Ld || !ISD::isNormalLoad(Ld))
25535 // If this is not the MMX case, i.e. we are just turning i64 load/store
25536 // into f64 load/store, avoid the transformation if there are multiple
25537 // uses of the loaded value.
25538 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25543 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25544 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25546 if (Subtarget->is64Bit() || F64IsLegal) {
25547 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25548 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25549 Ld->getPointerInfo(), Ld->isVolatile(),
25550 Ld->isNonTemporal(), Ld->isInvariant(),
25551 Ld->getAlignment());
25552 SDValue NewChain = NewLd.getValue(1);
25553 if (TokenFactorIndex != -1) {
25554 Ops.push_back(NewChain);
25555 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25557 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25558 St->getPointerInfo(),
25559 St->isVolatile(), St->isNonTemporal(),
25560 St->getAlignment());
25563 // Otherwise, lower to two pairs of 32-bit loads / stores.
25564 SDValue LoAddr = Ld->getBasePtr();
25565 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25566 DAG.getConstant(4, LdDL, MVT::i32));
25568 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25569 Ld->getPointerInfo(),
25570 Ld->isVolatile(), Ld->isNonTemporal(),
25571 Ld->isInvariant(), Ld->getAlignment());
25572 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25573 Ld->getPointerInfo().getWithOffset(4),
25574 Ld->isVolatile(), Ld->isNonTemporal(),
25576 MinAlign(Ld->getAlignment(), 4));
25578 SDValue NewChain = LoLd.getValue(1);
25579 if (TokenFactorIndex != -1) {
25580 Ops.push_back(LoLd);
25581 Ops.push_back(HiLd);
25582 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25585 LoAddr = St->getBasePtr();
25586 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25587 DAG.getConstant(4, StDL, MVT::i32));
25589 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25590 St->getPointerInfo(),
25591 St->isVolatile(), St->isNonTemporal(),
25592 St->getAlignment());
25593 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25594 St->getPointerInfo().getWithOffset(4),
25596 St->isNonTemporal(),
25597 MinAlign(St->getAlignment(), 4));
25598 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25601 // This is similar to the above case, but here we handle a scalar 64-bit
25602 // integer store that is extracted from a vector on a 32-bit target.
25603 // If we have SSE2, then we can treat it like a floating-point double
25604 // to get past legalization. The execution dependencies fixup pass will
25605 // choose the optimal machine instruction for the store if this really is
25606 // an integer or v2f32 rather than an f64.
25607 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25608 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25609 SDValue OldExtract = St->getOperand(1);
25610 SDValue ExtOp0 = OldExtract.getOperand(0);
25611 unsigned VecSize = ExtOp0.getValueSizeInBits();
25612 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25613 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25614 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25615 BitCast, OldExtract.getOperand(1));
25616 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25617 St->getPointerInfo(), St->isVolatile(),
25618 St->isNonTemporal(), St->getAlignment());
25624 /// Return 'true' if this vector operation is "horizontal"
25625 /// and return the operands for the horizontal operation in LHS and RHS. A
25626 /// horizontal operation performs the binary operation on successive elements
25627 /// of its first operand, then on successive elements of its second operand,
25628 /// returning the resulting values in a vector. For example, if
25629 /// A = < float a0, float a1, float a2, float a3 >
25631 /// B = < float b0, float b1, float b2, float b3 >
25632 /// then the result of doing a horizontal operation on A and B is
25633 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25634 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25635 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25636 /// set to A, RHS to B, and the routine returns 'true'.
25637 /// Note that the binary operation should have the property that if one of the
25638 /// operands is UNDEF then the result is UNDEF.
25639 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25640 // Look for the following pattern: if
25641 // A = < float a0, float a1, float a2, float a3 >
25642 // B = < float b0, float b1, float b2, float b3 >
25644 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25645 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25646 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25647 // which is A horizontal-op B.
25649 // At least one of the operands should be a vector shuffle.
25650 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25651 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25654 MVT VT = LHS.getSimpleValueType();
25656 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25657 "Unsupported vector type for horizontal add/sub");
25659 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25660 // operate independently on 128-bit lanes.
25661 unsigned NumElts = VT.getVectorNumElements();
25662 unsigned NumLanes = VT.getSizeInBits()/128;
25663 unsigned NumLaneElts = NumElts / NumLanes;
25664 assert((NumLaneElts % 2 == 0) &&
25665 "Vector type should have an even number of elements in each lane");
25666 unsigned HalfLaneElts = NumLaneElts/2;
25668 // View LHS in the form
25669 // LHS = VECTOR_SHUFFLE A, B, LMask
25670 // If LHS is not a shuffle then pretend it is the shuffle
25671 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25672 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25675 SmallVector<int, 16> LMask(NumElts);
25676 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25677 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25678 A = LHS.getOperand(0);
25679 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25680 B = LHS.getOperand(1);
25681 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25682 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25684 if (LHS.getOpcode() != ISD::UNDEF)
25686 for (unsigned i = 0; i != NumElts; ++i)
25690 // Likewise, view RHS in the form
25691 // RHS = VECTOR_SHUFFLE C, D, RMask
25693 SmallVector<int, 16> RMask(NumElts);
25694 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25695 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25696 C = RHS.getOperand(0);
25697 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25698 D = RHS.getOperand(1);
25699 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25700 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25702 if (RHS.getOpcode() != ISD::UNDEF)
25704 for (unsigned i = 0; i != NumElts; ++i)
25708 // Check that the shuffles are both shuffling the same vectors.
25709 if (!(A == C && B == D) && !(A == D && B == C))
25712 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25713 if (!A.getNode() && !B.getNode())
25716 // If A and B occur in reverse order in RHS, then "swap" them (which means
25717 // rewriting the mask).
25719 ShuffleVectorSDNode::commuteMask(RMask);
25721 // At this point LHS and RHS are equivalent to
25722 // LHS = VECTOR_SHUFFLE A, B, LMask
25723 // RHS = VECTOR_SHUFFLE A, B, RMask
25724 // Check that the masks correspond to performing a horizontal operation.
25725 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25726 for (unsigned i = 0; i != NumLaneElts; ++i) {
25727 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25729 // Ignore any UNDEF components.
25730 if (LIdx < 0 || RIdx < 0 ||
25731 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25732 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25735 // Check that successive elements are being operated on. If not, this is
25736 // not a horizontal operation.
25737 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25738 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25739 if (!(LIdx == Index && RIdx == Index + 1) &&
25740 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25745 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25746 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25750 /// Do target-specific dag combines on floating point adds.
25751 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25752 const X86Subtarget *Subtarget) {
25753 EVT VT = N->getValueType(0);
25754 SDValue LHS = N->getOperand(0);
25755 SDValue RHS = N->getOperand(1);
25757 // Try to synthesize horizontal adds from adds of shuffles.
25758 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25759 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25760 isHorizontalBinOp(LHS, RHS, true))
25761 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25765 /// Do target-specific dag combines on floating point subs.
25766 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25767 const X86Subtarget *Subtarget) {
25768 EVT VT = N->getValueType(0);
25769 SDValue LHS = N->getOperand(0);
25770 SDValue RHS = N->getOperand(1);
25772 // Try to synthesize horizontal subs from subs of shuffles.
25773 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25774 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25775 isHorizontalBinOp(LHS, RHS, false))
25776 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25780 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25781 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25782 const X86Subtarget *Subtarget) {
25783 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25785 // F[X]OR(0.0, x) -> x
25786 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25787 if (C->getValueAPF().isPosZero())
25788 return N->getOperand(1);
25790 // F[X]OR(x, 0.0) -> x
25791 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25792 if (C->getValueAPF().isPosZero())
25793 return N->getOperand(0);
25795 EVT VT = N->getValueType(0);
25796 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25798 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25799 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25801 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25802 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25803 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25804 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25805 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25810 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25811 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25812 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25814 // Only perform optimizations if UnsafeMath is used.
25815 if (!DAG.getTarget().Options.UnsafeFPMath)
25818 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25819 // into FMINC and FMAXC, which are Commutative operations.
25820 unsigned NewOp = 0;
25821 switch (N->getOpcode()) {
25822 default: llvm_unreachable("unknown opcode");
25823 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25824 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25827 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25828 N->getOperand(0), N->getOperand(1));
25831 /// Do target-specific dag combines on X86ISD::FAND nodes.
25832 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25833 // FAND(0.0, x) -> 0.0
25834 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25835 if (C->getValueAPF().isPosZero())
25836 return N->getOperand(0);
25838 // FAND(x, 0.0) -> 0.0
25839 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25840 if (C->getValueAPF().isPosZero())
25841 return N->getOperand(1);
25846 /// Do target-specific dag combines on X86ISD::FANDN nodes
25847 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25848 // FANDN(0.0, x) -> x
25849 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25850 if (C->getValueAPF().isPosZero())
25851 return N->getOperand(1);
25853 // FANDN(x, 0.0) -> 0.0
25854 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25855 if (C->getValueAPF().isPosZero())
25856 return N->getOperand(1);
25861 static SDValue PerformBTCombine(SDNode *N,
25863 TargetLowering::DAGCombinerInfo &DCI) {
25864 // BT ignores high bits in the bit index operand.
25865 SDValue Op1 = N->getOperand(1);
25866 if (Op1.hasOneUse()) {
25867 unsigned BitWidth = Op1.getValueSizeInBits();
25868 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25869 APInt KnownZero, KnownOne;
25870 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25871 !DCI.isBeforeLegalizeOps());
25872 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25873 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25874 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25875 DCI.CommitTargetLoweringOpt(TLO);
25880 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25881 SDValue Op = N->getOperand(0);
25882 if (Op.getOpcode() == ISD::BITCAST)
25883 Op = Op.getOperand(0);
25884 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25885 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25886 VT.getVectorElementType().getSizeInBits() ==
25887 OpVT.getVectorElementType().getSizeInBits()) {
25888 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25893 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25894 const X86Subtarget *Subtarget) {
25895 EVT VT = N->getValueType(0);
25896 if (!VT.isVector())
25899 SDValue N0 = N->getOperand(0);
25900 SDValue N1 = N->getOperand(1);
25901 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25904 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25905 // both SSE and AVX2 since there is no sign-extended shift right
25906 // operation on a vector with 64-bit elements.
25907 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25908 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25909 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25910 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25911 SDValue N00 = N0.getOperand(0);
25913 // EXTLOAD has a better solution on AVX2,
25914 // it may be replaced with X86ISD::VSEXT node.
25915 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25916 if (!ISD::isNormalLoad(N00.getNode()))
25919 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25920 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25922 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25928 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25929 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25930 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25931 /// eliminate extend, add, and shift instructions.
25932 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25933 const X86Subtarget *Subtarget) {
25934 // TODO: This should be valid for other integer types.
25935 EVT VT = Sext->getValueType(0);
25936 if (VT != MVT::i64)
25939 // We need an 'add nsw' feeding into the 'sext'.
25940 SDValue Add = Sext->getOperand(0);
25941 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25944 // Having a constant operand to the 'add' ensures that we are not increasing
25945 // the instruction count because the constant is extended for free below.
25946 // A constant operand can also become the displacement field of an LEA.
25947 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25951 // Don't make the 'add' bigger if there's no hope of combining it with some
25952 // other 'add' or 'shl' instruction.
25953 // TODO: It may be profitable to generate simpler LEA instructions in place
25954 // of single 'add' instructions, but the cost model for selecting an LEA
25955 // currently has a high threshold.
25956 bool HasLEAPotential = false;
25957 for (auto *User : Sext->uses()) {
25958 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
25959 HasLEAPotential = true;
25963 if (!HasLEAPotential)
25966 // Everything looks good, so pull the 'sext' ahead of the 'add'.
25967 int64_t AddConstant = AddOp1->getSExtValue();
25968 SDValue AddOp0 = Add.getOperand(0);
25969 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
25970 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
25972 // The wider add is guaranteed to not wrap because both operands are
25975 Flags.setNoSignedWrap(true);
25976 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
25979 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25980 TargetLowering::DAGCombinerInfo &DCI,
25981 const X86Subtarget *Subtarget) {
25982 SDValue N0 = N->getOperand(0);
25983 EVT VT = N->getValueType(0);
25984 EVT SVT = VT.getScalarType();
25985 EVT InVT = N0.getValueType();
25986 EVT InSVT = InVT.getScalarType();
25989 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25990 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25991 // This exposes the sext to the sdivrem lowering, so that it directly extends
25992 // from AH (which we otherwise need to do contortions to access).
25993 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25994 InVT == MVT::i8 && VT == MVT::i32) {
25995 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25996 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25997 N0.getOperand(0), N0.getOperand(1));
25998 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25999 return R.getValue(1);
26002 if (!DCI.isBeforeLegalizeOps()) {
26003 if (InVT == MVT::i1) {
26004 SDValue Zero = DAG.getConstant(0, DL, VT);
26006 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26007 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26012 if (VT.isVector() && Subtarget->hasSSE2()) {
26013 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26014 EVT InVT = N.getValueType();
26015 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26016 Size / InVT.getScalarSizeInBits());
26017 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26018 DAG.getUNDEF(InVT));
26020 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26023 // If target-size is less than 128-bits, extend to a type that would extend
26024 // to 128 bits, extend that and extract the original target vector.
26025 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26026 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26027 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26028 unsigned Scale = 128 / VT.getSizeInBits();
26030 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26031 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26032 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26033 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26034 DAG.getIntPtrConstant(0, DL));
26037 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26038 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26039 if (VT.getSizeInBits() == 128 &&
26040 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26041 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26042 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26043 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26046 // On pre-AVX2 targets, split into 128-bit nodes of
26047 // ISD::SIGN_EXTEND_VECTOR_INREG.
26048 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26049 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26050 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26051 unsigned NumVecs = VT.getSizeInBits() / 128;
26052 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26053 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26054 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26056 SmallVector<SDValue, 8> Opnds;
26057 for (unsigned i = 0, Offset = 0; i != NumVecs;
26058 ++i, Offset += NumSubElts) {
26059 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26060 DAG.getIntPtrConstant(Offset, DL));
26061 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26062 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26063 Opnds.push_back(SrcVec);
26065 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26069 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
26070 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26073 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26079 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26080 const X86Subtarget* Subtarget) {
26082 EVT VT = N->getValueType(0);
26084 // Let legalize expand this if it isn't a legal type yet.
26085 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26088 EVT ScalarVT = VT.getScalarType();
26089 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26090 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26091 !Subtarget->hasAVX512()))
26094 SDValue A = N->getOperand(0);
26095 SDValue B = N->getOperand(1);
26096 SDValue C = N->getOperand(2);
26098 bool NegA = (A.getOpcode() == ISD::FNEG);
26099 bool NegB = (B.getOpcode() == ISD::FNEG);
26100 bool NegC = (C.getOpcode() == ISD::FNEG);
26102 // Negative multiplication when NegA xor NegB
26103 bool NegMul = (NegA != NegB);
26105 A = A.getOperand(0);
26107 B = B.getOperand(0);
26109 C = C.getOperand(0);
26113 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26115 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26117 return DAG.getNode(Opcode, dl, VT, A, B, C);
26120 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26121 TargetLowering::DAGCombinerInfo &DCI,
26122 const X86Subtarget *Subtarget) {
26123 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26124 // (and (i32 x86isd::setcc_carry), 1)
26125 // This eliminates the zext. This transformation is necessary because
26126 // ISD::SETCC is always legalized to i8.
26128 SDValue N0 = N->getOperand(0);
26129 EVT VT = N->getValueType(0);
26131 if (N0.getOpcode() == ISD::AND &&
26133 N0.getOperand(0).hasOneUse()) {
26134 SDValue N00 = N0.getOperand(0);
26135 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26137 if (!C || C->getZExtValue() != 1)
26139 return DAG.getNode(ISD::AND, dl, VT,
26140 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26141 N00.getOperand(0), N00.getOperand(1)),
26142 DAG.getConstant(1, dl, VT));
26146 if (N0.getOpcode() == ISD::TRUNCATE &&
26148 N0.getOperand(0).hasOneUse()) {
26149 SDValue N00 = N0.getOperand(0);
26150 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26151 return DAG.getNode(ISD::AND, dl, VT,
26152 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26153 N00.getOperand(0), N00.getOperand(1)),
26154 DAG.getConstant(1, dl, VT));
26158 if (VT.is256BitVector())
26159 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26162 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26163 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26164 // This exposes the zext to the udivrem lowering, so that it directly extends
26165 // from AH (which we otherwise need to do contortions to access).
26166 if (N0.getOpcode() == ISD::UDIVREM &&
26167 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26168 (VT == MVT::i32 || VT == MVT::i64)) {
26169 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26170 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26171 N0.getOperand(0), N0.getOperand(1));
26172 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26173 return R.getValue(1);
26179 // Optimize x == -y --> x+y == 0
26180 // x != -y --> x+y != 0
26181 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26182 const X86Subtarget* Subtarget) {
26183 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26184 SDValue LHS = N->getOperand(0);
26185 SDValue RHS = N->getOperand(1);
26186 EVT VT = N->getValueType(0);
26189 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26190 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26191 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26192 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26193 LHS.getOperand(1));
26194 return DAG.getSetCC(DL, N->getValueType(0), addV,
26195 DAG.getConstant(0, DL, addV.getValueType()), CC);
26197 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26199 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26200 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26201 RHS.getOperand(1));
26202 return DAG.getSetCC(DL, N->getValueType(0), addV,
26203 DAG.getConstant(0, DL, addV.getValueType()), CC);
26206 if (VT.getScalarType() == MVT::i1 &&
26207 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26209 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26210 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26211 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26213 if (!IsSEXT0 || !IsVZero1) {
26214 // Swap the operands and update the condition code.
26215 std::swap(LHS, RHS);
26216 CC = ISD::getSetCCSwappedOperands(CC);
26218 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26219 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26220 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26223 if (IsSEXT0 && IsVZero1) {
26224 assert(VT == LHS.getOperand(0).getValueType() &&
26225 "Uexpected operand type");
26226 if (CC == ISD::SETGT)
26227 return DAG.getConstant(0, DL, VT);
26228 if (CC == ISD::SETLE)
26229 return DAG.getConstant(1, DL, VT);
26230 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26231 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26233 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26234 "Unexpected condition code!");
26235 return LHS.getOperand(0);
26242 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
26243 SelectionDAG &DAG) {
26245 MVT VT = Load->getSimpleValueType(0);
26246 MVT EVT = VT.getVectorElementType();
26247 SDValue Addr = Load->getOperand(1);
26248 SDValue NewAddr = DAG.getNode(
26249 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
26250 DAG.getConstant(Index * EVT.getStoreSize(), dl,
26251 Addr.getSimpleValueType()));
26254 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
26255 DAG.getMachineFunction().getMachineMemOperand(
26256 Load->getMemOperand(), 0, EVT.getStoreSize()));
26260 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26261 const X86Subtarget *Subtarget) {
26263 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26264 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26265 "X86insertps is only defined for v4x32");
26267 SDValue Ld = N->getOperand(1);
26268 if (MayFoldLoad(Ld)) {
26269 // Extract the countS bits from the immediate so we can get the proper
26270 // address when narrowing the vector load to a specific element.
26271 // When the second source op is a memory address, insertps doesn't use
26272 // countS and just gets an f32 from that address.
26273 unsigned DestIndex =
26274 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26276 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26278 // Create this as a scalar to vector to match the instruction pattern.
26279 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26280 // countS bits are ignored when loading from memory on insertps, which
26281 // means we don't need to explicitly set them to 0.
26282 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26283 LoadScalarToVector, N->getOperand(2));
26288 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26289 SDValue V0 = N->getOperand(0);
26290 SDValue V1 = N->getOperand(1);
26292 EVT VT = N->getValueType(0);
26294 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26295 // operands and changing the mask to 1. This saves us a bunch of
26296 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26297 // x86InstrInfo knows how to commute this back after instruction selection
26298 // if it would help register allocation.
26300 // TODO: If optimizing for size or a processor that doesn't suffer from
26301 // partial register update stalls, this should be transformed into a MOVSD
26302 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26304 if (VT == MVT::v2f64)
26305 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26306 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26307 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26308 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26314 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26315 // as "sbb reg,reg", since it can be extended without zext and produces
26316 // an all-ones bit which is more useful than 0/1 in some cases.
26317 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26320 return DAG.getNode(ISD::AND, DL, VT,
26321 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26322 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26324 DAG.getConstant(1, DL, VT));
26325 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26326 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26327 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26328 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26332 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26333 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26334 TargetLowering::DAGCombinerInfo &DCI,
26335 const X86Subtarget *Subtarget) {
26337 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26338 SDValue EFLAGS = N->getOperand(1);
26340 if (CC == X86::COND_A) {
26341 // Try to convert COND_A into COND_B in an attempt to facilitate
26342 // materializing "setb reg".
26344 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26345 // cannot take an immediate as its first operand.
26347 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26348 EFLAGS.getValueType().isInteger() &&
26349 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26350 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26351 EFLAGS.getNode()->getVTList(),
26352 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26353 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26354 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26358 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26359 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26361 if (CC == X86::COND_B)
26362 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26364 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26365 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26366 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26372 // Optimize branch condition evaluation.
26374 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26375 TargetLowering::DAGCombinerInfo &DCI,
26376 const X86Subtarget *Subtarget) {
26378 SDValue Chain = N->getOperand(0);
26379 SDValue Dest = N->getOperand(1);
26380 SDValue EFLAGS = N->getOperand(3);
26381 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26383 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26384 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26385 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26392 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26393 SelectionDAG &DAG) {
26394 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26395 // optimize away operation when it's from a constant.
26397 // The general transformation is:
26398 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26399 // AND(VECTOR_CMP(x,y), constant2)
26400 // constant2 = UNARYOP(constant)
26402 // Early exit if this isn't a vector operation, the operand of the
26403 // unary operation isn't a bitwise AND, or if the sizes of the operations
26404 // aren't the same.
26405 EVT VT = N->getValueType(0);
26406 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26407 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26408 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26411 // Now check that the other operand of the AND is a constant. We could
26412 // make the transformation for non-constant splats as well, but it's unclear
26413 // that would be a benefit as it would not eliminate any operations, just
26414 // perform one more step in scalar code before moving to the vector unit.
26415 if (BuildVectorSDNode *BV =
26416 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26417 // Bail out if the vector isn't a constant.
26418 if (!BV->isConstant())
26421 // Everything checks out. Build up the new and improved node.
26423 EVT IntVT = BV->getValueType(0);
26424 // Create a new constant of the appropriate type for the transformed
26426 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26427 // The AND node needs bitcasts to/from an integer vector type around it.
26428 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26429 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26430 N->getOperand(0)->getOperand(0), MaskConst);
26431 SDValue Res = DAG.getBitcast(VT, NewAnd);
26438 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26439 const X86Subtarget *Subtarget) {
26440 SDValue Op0 = N->getOperand(0);
26441 EVT VT = N->getValueType(0);
26442 EVT InVT = Op0.getValueType();
26443 EVT InSVT = InVT.getScalarType();
26444 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26446 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26447 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26448 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26450 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26451 InVT.getVectorNumElements());
26452 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26454 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26455 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26457 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26463 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26464 const X86Subtarget *Subtarget) {
26465 // First try to optimize away the conversion entirely when it's
26466 // conditionally from a constant. Vectors only.
26467 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26470 // Now move on to more general possibilities.
26471 SDValue Op0 = N->getOperand(0);
26472 EVT VT = N->getValueType(0);
26473 EVT InVT = Op0.getValueType();
26474 EVT InSVT = InVT.getScalarType();
26476 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26477 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26478 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26480 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26481 InVT.getVectorNumElements());
26482 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26483 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26486 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26487 // a 32-bit target where SSE doesn't support i64->FP operations.
26488 if (Op0.getOpcode() == ISD::LOAD) {
26489 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26490 EVT LdVT = Ld->getValueType(0);
26492 // This transformation is not supported if the result type is f16
26493 if (VT == MVT::f16)
26496 if (!Ld->isVolatile() && !VT.isVector() &&
26497 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26498 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26499 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26500 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26501 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26508 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26509 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26510 X86TargetLowering::DAGCombinerInfo &DCI) {
26511 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26512 // the result is either zero or one (depending on the input carry bit).
26513 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26514 if (X86::isZeroNode(N->getOperand(0)) &&
26515 X86::isZeroNode(N->getOperand(1)) &&
26516 // We don't have a good way to replace an EFLAGS use, so only do this when
26518 SDValue(N, 1).use_empty()) {
26520 EVT VT = N->getValueType(0);
26521 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26522 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26523 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26524 DAG.getConstant(X86::COND_B, DL,
26527 DAG.getConstant(1, DL, VT));
26528 return DCI.CombineTo(N, Res1, CarryOut);
26534 // fold (add Y, (sete X, 0)) -> adc 0, Y
26535 // (add Y, (setne X, 0)) -> sbb -1, Y
26536 // (sub (sete X, 0), Y) -> sbb 0, Y
26537 // (sub (setne X, 0), Y) -> adc -1, Y
26538 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26541 // Look through ZExts.
26542 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26543 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26546 SDValue SetCC = Ext.getOperand(0);
26547 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26550 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26551 if (CC != X86::COND_E && CC != X86::COND_NE)
26554 SDValue Cmp = SetCC.getOperand(1);
26555 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26556 !X86::isZeroNode(Cmp.getOperand(1)) ||
26557 !Cmp.getOperand(0).getValueType().isInteger())
26560 SDValue CmpOp0 = Cmp.getOperand(0);
26561 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26562 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26564 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26565 if (CC == X86::COND_NE)
26566 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26567 DL, OtherVal.getValueType(), OtherVal,
26568 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26570 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26571 DL, OtherVal.getValueType(), OtherVal,
26572 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26575 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26576 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26577 const X86Subtarget *Subtarget) {
26578 EVT VT = N->getValueType(0);
26579 SDValue Op0 = N->getOperand(0);
26580 SDValue Op1 = N->getOperand(1);
26582 // Try to synthesize horizontal adds from adds of shuffles.
26583 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26584 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26585 isHorizontalBinOp(Op0, Op1, true))
26586 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26588 return OptimizeConditionalInDecrement(N, DAG);
26591 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26592 const X86Subtarget *Subtarget) {
26593 SDValue Op0 = N->getOperand(0);
26594 SDValue Op1 = N->getOperand(1);
26596 // X86 can't encode an immediate LHS of a sub. See if we can push the
26597 // negation into a preceding instruction.
26598 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26599 // If the RHS of the sub is a XOR with one use and a constant, invert the
26600 // immediate. Then add one to the LHS of the sub so we can turn
26601 // X-Y -> X+~Y+1, saving one register.
26602 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26603 isa<ConstantSDNode>(Op1.getOperand(1))) {
26604 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26605 EVT VT = Op0.getValueType();
26606 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26608 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26609 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26610 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26614 // Try to synthesize horizontal adds from adds of shuffles.
26615 EVT VT = N->getValueType(0);
26616 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26617 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26618 isHorizontalBinOp(Op0, Op1, true))
26619 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26621 return OptimizeConditionalInDecrement(N, DAG);
26624 /// performVZEXTCombine - Performs build vector combines
26625 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26626 TargetLowering::DAGCombinerInfo &DCI,
26627 const X86Subtarget *Subtarget) {
26629 MVT VT = N->getSimpleValueType(0);
26630 SDValue Op = N->getOperand(0);
26631 MVT OpVT = Op.getSimpleValueType();
26632 MVT OpEltVT = OpVT.getVectorElementType();
26633 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26635 // (vzext (bitcast (vzext (x)) -> (vzext x)
26637 while (V.getOpcode() == ISD::BITCAST)
26638 V = V.getOperand(0);
26640 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26641 MVT InnerVT = V.getSimpleValueType();
26642 MVT InnerEltVT = InnerVT.getVectorElementType();
26644 // If the element sizes match exactly, we can just do one larger vzext. This
26645 // is always an exact type match as vzext operates on integer types.
26646 if (OpEltVT == InnerEltVT) {
26647 assert(OpVT == InnerVT && "Types must match for vzext!");
26648 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26651 // The only other way we can combine them is if only a single element of the
26652 // inner vzext is used in the input to the outer vzext.
26653 if (InnerEltVT.getSizeInBits() < InputBits)
26656 // In this case, the inner vzext is completely dead because we're going to
26657 // only look at bits inside of the low element. Just do the outer vzext on
26658 // a bitcast of the input to the inner.
26659 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26662 // Check if we can bypass extracting and re-inserting an element of an input
26663 // vector. Essentially:
26664 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26665 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26666 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26667 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26668 SDValue ExtractedV = V.getOperand(0);
26669 SDValue OrigV = ExtractedV.getOperand(0);
26670 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26671 if (ExtractIdx->getZExtValue() == 0) {
26672 MVT OrigVT = OrigV.getSimpleValueType();
26673 // Extract a subvector if necessary...
26674 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26675 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26676 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26677 OrigVT.getVectorNumElements() / Ratio);
26678 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26679 DAG.getIntPtrConstant(0, DL));
26681 Op = DAG.getBitcast(OpVT, OrigV);
26682 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26689 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26690 DAGCombinerInfo &DCI) const {
26691 SelectionDAG &DAG = DCI.DAG;
26692 switch (N->getOpcode()) {
26694 case ISD::EXTRACT_VECTOR_ELT:
26695 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26698 case X86ISD::SHRUNKBLEND:
26699 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26700 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26701 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26702 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26703 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26704 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26705 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26708 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26709 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26710 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26711 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26712 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26713 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26714 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26715 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26716 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26717 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26718 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26719 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26721 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26723 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26724 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26725 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26726 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26727 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26728 case ISD::ANY_EXTEND:
26729 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26730 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26731 case ISD::SIGN_EXTEND_INREG:
26732 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26733 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26734 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26735 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26736 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26737 case X86ISD::SHUFP: // Handle all target specific shuffles
26738 case X86ISD::PALIGNR:
26739 case X86ISD::UNPCKH:
26740 case X86ISD::UNPCKL:
26741 case X86ISD::MOVHLPS:
26742 case X86ISD::MOVLHPS:
26743 case X86ISD::PSHUFB:
26744 case X86ISD::PSHUFD:
26745 case X86ISD::PSHUFHW:
26746 case X86ISD::PSHUFLW:
26747 case X86ISD::MOVSS:
26748 case X86ISD::MOVSD:
26749 case X86ISD::VPERMILPI:
26750 case X86ISD::VPERM2X128:
26751 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26752 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26753 case X86ISD::INSERTPS: {
26754 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26755 return PerformINSERTPSCombine(N, DAG, Subtarget);
26758 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26764 /// isTypeDesirableForOp - Return true if the target has native support for
26765 /// the specified value type and it is 'desirable' to use the type for the
26766 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26767 /// instruction encodings are longer and some i16 instructions are slow.
26768 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26769 if (!isTypeLegal(VT))
26771 if (VT != MVT::i16)
26778 case ISD::SIGN_EXTEND:
26779 case ISD::ZERO_EXTEND:
26780 case ISD::ANY_EXTEND:
26793 /// IsDesirableToPromoteOp - This method query the target whether it is
26794 /// beneficial for dag combiner to promote the specified node. If true, it
26795 /// should return the desired promotion type by reference.
26796 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26797 EVT VT = Op.getValueType();
26798 if (VT != MVT::i16)
26801 bool Promote = false;
26802 bool Commute = false;
26803 switch (Op.getOpcode()) {
26806 LoadSDNode *LD = cast<LoadSDNode>(Op);
26807 // If the non-extending load has a single use and it's not live out, then it
26808 // might be folded.
26809 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26810 Op.hasOneUse()*/) {
26811 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26812 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26813 // The only case where we'd want to promote LOAD (rather then it being
26814 // promoted as an operand is when it's only use is liveout.
26815 if (UI->getOpcode() != ISD::CopyToReg)
26822 case ISD::SIGN_EXTEND:
26823 case ISD::ZERO_EXTEND:
26824 case ISD::ANY_EXTEND:
26829 SDValue N0 = Op.getOperand(0);
26830 // Look out for (store (shl (load), x)).
26831 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26844 SDValue N0 = Op.getOperand(0);
26845 SDValue N1 = Op.getOperand(1);
26846 if (!Commute && MayFoldLoad(N1))
26848 // Avoid disabling potential load folding opportunities.
26849 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26851 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26861 //===----------------------------------------------------------------------===//
26862 // X86 Inline Assembly Support
26863 //===----------------------------------------------------------------------===//
26865 // Helper to match a string separated by whitespace.
26866 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26867 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26869 for (StringRef Piece : Pieces) {
26870 if (!S.startswith(Piece)) // Check if the piece matches.
26873 S = S.substr(Piece.size());
26874 StringRef::size_type Pos = S.find_first_not_of(" \t");
26875 if (Pos == 0) // We matched a prefix.
26884 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26886 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26887 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26888 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26889 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26891 if (AsmPieces.size() == 3)
26893 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26900 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26901 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26903 std::string AsmStr = IA->getAsmString();
26905 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26906 if (!Ty || Ty->getBitWidth() % 16 != 0)
26909 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26910 SmallVector<StringRef, 4> AsmPieces;
26911 SplitString(AsmStr, AsmPieces, ";\n");
26913 switch (AsmPieces.size()) {
26914 default: return false;
26916 // FIXME: this should verify that we are targeting a 486 or better. If not,
26917 // we will turn this bswap into something that will be lowered to logical
26918 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26919 // lower so don't worry about this.
26921 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26922 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26923 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26924 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26925 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26926 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26927 // No need to check constraints, nothing other than the equivalent of
26928 // "=r,0" would be valid here.
26929 return IntrinsicLowering::LowerToByteSwap(CI);
26932 // rorw $$8, ${0:w} --> llvm.bswap.i16
26933 if (CI->getType()->isIntegerTy(16) &&
26934 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26935 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26936 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26938 StringRef ConstraintsStr = IA->getConstraintString();
26939 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26940 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26941 if (clobbersFlagRegisters(AsmPieces))
26942 return IntrinsicLowering::LowerToByteSwap(CI);
26946 if (CI->getType()->isIntegerTy(32) &&
26947 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26948 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26949 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26950 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26952 StringRef ConstraintsStr = IA->getConstraintString();
26953 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26954 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26955 if (clobbersFlagRegisters(AsmPieces))
26956 return IntrinsicLowering::LowerToByteSwap(CI);
26959 if (CI->getType()->isIntegerTy(64)) {
26960 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26961 if (Constraints.size() >= 2 &&
26962 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26963 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26964 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26965 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26966 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26967 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26968 return IntrinsicLowering::LowerToByteSwap(CI);
26976 /// getConstraintType - Given a constraint letter, return the type of
26977 /// constraint it is for this target.
26978 X86TargetLowering::ConstraintType
26979 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26980 if (Constraint.size() == 1) {
26981 switch (Constraint[0]) {
26992 return C_RegisterClass;
27016 return TargetLowering::getConstraintType(Constraint);
27019 /// Examine constraint type and operand type and determine a weight value.
27020 /// This object must already have been set up with the operand type
27021 /// and the current alternative constraint selected.
27022 TargetLowering::ConstraintWeight
27023 X86TargetLowering::getSingleConstraintMatchWeight(
27024 AsmOperandInfo &info, const char *constraint) const {
27025 ConstraintWeight weight = CW_Invalid;
27026 Value *CallOperandVal = info.CallOperandVal;
27027 // If we don't have a value, we can't do a match,
27028 // but allow it at the lowest weight.
27029 if (!CallOperandVal)
27031 Type *type = CallOperandVal->getType();
27032 // Look at the constraint type.
27033 switch (*constraint) {
27035 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27046 if (CallOperandVal->getType()->isIntegerTy())
27047 weight = CW_SpecificReg;
27052 if (type->isFloatingPointTy())
27053 weight = CW_SpecificReg;
27056 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27057 weight = CW_SpecificReg;
27061 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27062 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27063 weight = CW_Register;
27066 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27067 if (C->getZExtValue() <= 31)
27068 weight = CW_Constant;
27072 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27073 if (C->getZExtValue() <= 63)
27074 weight = CW_Constant;
27078 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27079 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27080 weight = CW_Constant;
27084 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27085 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27086 weight = CW_Constant;
27090 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27091 if (C->getZExtValue() <= 3)
27092 weight = CW_Constant;
27096 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27097 if (C->getZExtValue() <= 0xff)
27098 weight = CW_Constant;
27103 if (isa<ConstantFP>(CallOperandVal)) {
27104 weight = CW_Constant;
27108 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27109 if ((C->getSExtValue() >= -0x80000000LL) &&
27110 (C->getSExtValue() <= 0x7fffffffLL))
27111 weight = CW_Constant;
27115 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27116 if (C->getZExtValue() <= 0xffffffff)
27117 weight = CW_Constant;
27124 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27125 /// with another that has more specific requirements based on the type of the
27126 /// corresponding operand.
27127 const char *X86TargetLowering::
27128 LowerXConstraint(EVT ConstraintVT) const {
27129 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27130 // 'f' like normal targets.
27131 if (ConstraintVT.isFloatingPoint()) {
27132 if (Subtarget->hasSSE2())
27134 if (Subtarget->hasSSE1())
27138 return TargetLowering::LowerXConstraint(ConstraintVT);
27141 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27142 /// vector. If it is invalid, don't add anything to Ops.
27143 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27144 std::string &Constraint,
27145 std::vector<SDValue>&Ops,
27146 SelectionDAG &DAG) const {
27149 // Only support length 1 constraints for now.
27150 if (Constraint.length() > 1) return;
27152 char ConstraintLetter = Constraint[0];
27153 switch (ConstraintLetter) {
27156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27157 if (C->getZExtValue() <= 31) {
27158 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27159 Op.getValueType());
27165 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27166 if (C->getZExtValue() <= 63) {
27167 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27168 Op.getValueType());
27174 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27175 if (isInt<8>(C->getSExtValue())) {
27176 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27177 Op.getValueType());
27183 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27184 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27185 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27186 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27187 Op.getValueType());
27193 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27194 if (C->getZExtValue() <= 3) {
27195 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27196 Op.getValueType());
27202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27203 if (C->getZExtValue() <= 255) {
27204 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27205 Op.getValueType());
27211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27212 if (C->getZExtValue() <= 127) {
27213 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27214 Op.getValueType());
27220 // 32-bit signed value
27221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27222 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27223 C->getSExtValue())) {
27224 // Widen to 64 bits here to get it sign extended.
27225 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27228 // FIXME gcc accepts some relocatable values here too, but only in certain
27229 // memory models; it's complicated.
27234 // 32-bit unsigned value
27235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27236 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27237 C->getZExtValue())) {
27238 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27239 Op.getValueType());
27243 // FIXME gcc accepts some relocatable values here too, but only in certain
27244 // memory models; it's complicated.
27248 // Literal immediates are always ok.
27249 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27250 // Widen to 64 bits here to get it sign extended.
27251 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27255 // In any sort of PIC mode addresses need to be computed at runtime by
27256 // adding in a register or some sort of table lookup. These can't
27257 // be used as immediates.
27258 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27261 // If we are in non-pic codegen mode, we allow the address of a global (with
27262 // an optional displacement) to be used with 'i'.
27263 GlobalAddressSDNode *GA = nullptr;
27264 int64_t Offset = 0;
27266 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27268 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27269 Offset += GA->getOffset();
27271 } else if (Op.getOpcode() == ISD::ADD) {
27272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27273 Offset += C->getZExtValue();
27274 Op = Op.getOperand(0);
27277 } else if (Op.getOpcode() == ISD::SUB) {
27278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27279 Offset += -C->getZExtValue();
27280 Op = Op.getOperand(0);
27285 // Otherwise, this isn't something we can handle, reject it.
27289 const GlobalValue *GV = GA->getGlobal();
27290 // If we require an extra load to get this address, as in PIC mode, we
27291 // can't accept it.
27292 if (isGlobalStubReference(
27293 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27296 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27297 GA->getValueType(0), Offset);
27302 if (Result.getNode()) {
27303 Ops.push_back(Result);
27306 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27309 std::pair<unsigned, const TargetRegisterClass *>
27310 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27311 StringRef Constraint,
27313 // First, see if this is a constraint that directly corresponds to an LLVM
27315 if (Constraint.size() == 1) {
27316 // GCC Constraint Letters
27317 switch (Constraint[0]) {
27319 // TODO: Slight differences here in allocation order and leaving
27320 // RIP in the class. Do they matter any more here than they do
27321 // in the normal allocation?
27322 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27323 if (Subtarget->is64Bit()) {
27324 if (VT == MVT::i32 || VT == MVT::f32)
27325 return std::make_pair(0U, &X86::GR32RegClass);
27326 if (VT == MVT::i16)
27327 return std::make_pair(0U, &X86::GR16RegClass);
27328 if (VT == MVT::i8 || VT == MVT::i1)
27329 return std::make_pair(0U, &X86::GR8RegClass);
27330 if (VT == MVT::i64 || VT == MVT::f64)
27331 return std::make_pair(0U, &X86::GR64RegClass);
27334 // 32-bit fallthrough
27335 case 'Q': // Q_REGS
27336 if (VT == MVT::i32 || VT == MVT::f32)
27337 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27338 if (VT == MVT::i16)
27339 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27340 if (VT == MVT::i8 || VT == MVT::i1)
27341 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27342 if (VT == MVT::i64)
27343 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27345 case 'r': // GENERAL_REGS
27346 case 'l': // INDEX_REGS
27347 if (VT == MVT::i8 || VT == MVT::i1)
27348 return std::make_pair(0U, &X86::GR8RegClass);
27349 if (VT == MVT::i16)
27350 return std::make_pair(0U, &X86::GR16RegClass);
27351 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27352 return std::make_pair(0U, &X86::GR32RegClass);
27353 return std::make_pair(0U, &X86::GR64RegClass);
27354 case 'R': // LEGACY_REGS
27355 if (VT == MVT::i8 || VT == MVT::i1)
27356 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27357 if (VT == MVT::i16)
27358 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27359 if (VT == MVT::i32 || !Subtarget->is64Bit())
27360 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27361 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27362 case 'f': // FP Stack registers.
27363 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27364 // value to the correct fpstack register class.
27365 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27366 return std::make_pair(0U, &X86::RFP32RegClass);
27367 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27368 return std::make_pair(0U, &X86::RFP64RegClass);
27369 return std::make_pair(0U, &X86::RFP80RegClass);
27370 case 'y': // MMX_REGS if MMX allowed.
27371 if (!Subtarget->hasMMX()) break;
27372 return std::make_pair(0U, &X86::VR64RegClass);
27373 case 'Y': // SSE_REGS if SSE2 allowed
27374 if (!Subtarget->hasSSE2()) break;
27376 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27377 if (!Subtarget->hasSSE1()) break;
27379 switch (VT.SimpleTy) {
27381 // Scalar SSE types.
27384 return std::make_pair(0U, &X86::FR32RegClass);
27387 return std::make_pair(0U, &X86::FR64RegClass);
27395 return std::make_pair(0U, &X86::VR128RegClass);
27403 return std::make_pair(0U, &X86::VR256RegClass);
27408 return std::make_pair(0U, &X86::VR512RegClass);
27414 // Use the default implementation in TargetLowering to convert the register
27415 // constraint into a member of a register class.
27416 std::pair<unsigned, const TargetRegisterClass*> Res;
27417 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27419 // Not found as a standard register?
27421 // Map st(0) -> st(7) -> ST0
27422 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27423 tolower(Constraint[1]) == 's' &&
27424 tolower(Constraint[2]) == 't' &&
27425 Constraint[3] == '(' &&
27426 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27427 Constraint[5] == ')' &&
27428 Constraint[6] == '}') {
27430 Res.first = X86::FP0+Constraint[4]-'0';
27431 Res.second = &X86::RFP80RegClass;
27435 // GCC allows "st(0)" to be called just plain "st".
27436 if (StringRef("{st}").equals_lower(Constraint)) {
27437 Res.first = X86::FP0;
27438 Res.second = &X86::RFP80RegClass;
27443 if (StringRef("{flags}").equals_lower(Constraint)) {
27444 Res.first = X86::EFLAGS;
27445 Res.second = &X86::CCRRegClass;
27449 // 'A' means EAX + EDX.
27450 if (Constraint == "A") {
27451 Res.first = X86::EAX;
27452 Res.second = &X86::GR32_ADRegClass;
27458 // Otherwise, check to see if this is a register class of the wrong value
27459 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27460 // turn into {ax},{dx}.
27461 // MVT::Other is used to specify clobber names.
27462 if (Res.second->hasType(VT) || VT == MVT::Other)
27463 return Res; // Correct type already, nothing to do.
27465 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27466 // return "eax". This should even work for things like getting 64bit integer
27467 // registers when given an f64 type.
27468 const TargetRegisterClass *Class = Res.second;
27469 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27470 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27471 unsigned Size = VT.getSizeInBits();
27472 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27473 : Size == 16 ? MVT::i16
27474 : Size == 32 ? MVT::i32
27475 : Size == 64 ? MVT::i64
27477 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27479 Res.first = DestReg;
27480 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27481 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27482 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27483 : &X86::GR64RegClass;
27484 assert(Res.second->contains(Res.first) && "Register in register class");
27486 // No register found/type mismatch.
27488 Res.second = nullptr;
27490 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27491 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27492 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27493 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27494 Class == &X86::VR512RegClass) {
27495 // Handle references to XMM physical registers that got mapped into the
27496 // wrong class. This can happen with constraints like {xmm0} where the
27497 // target independent register mapper will just pick the first match it can
27498 // find, ignoring the required type.
27500 if (VT == MVT::f32 || VT == MVT::i32)
27501 Res.second = &X86::FR32RegClass;
27502 else if (VT == MVT::f64 || VT == MVT::i64)
27503 Res.second = &X86::FR64RegClass;
27504 else if (X86::VR128RegClass.hasType(VT))
27505 Res.second = &X86::VR128RegClass;
27506 else if (X86::VR256RegClass.hasType(VT))
27507 Res.second = &X86::VR256RegClass;
27508 else if (X86::VR512RegClass.hasType(VT))
27509 Res.second = &X86::VR512RegClass;
27511 // Type mismatch and not a clobber: Return an error;
27513 Res.second = nullptr;
27520 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27521 const AddrMode &AM, Type *Ty,
27522 unsigned AS) const {
27523 // Scaling factors are not free at all.
27524 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27525 // will take 2 allocations in the out of order engine instead of 1
27526 // for plain addressing mode, i.e. inst (reg1).
27528 // vaddps (%rsi,%drx), %ymm0, %ymm1
27529 // Requires two allocations (one for the load, one for the computation)
27531 // vaddps (%rsi), %ymm0, %ymm1
27532 // Requires just 1 allocation, i.e., freeing allocations for other operations
27533 // and having less micro operations to execute.
27535 // For some X86 architectures, this is even worse because for instance for
27536 // stores, the complex addressing mode forces the instruction to use the
27537 // "load" ports instead of the dedicated "store" port.
27538 // E.g., on Haswell:
27539 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27540 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27541 if (isLegalAddressingMode(DL, AM, Ty, AS))
27542 // Scale represents reg2 * scale, thus account for 1
27543 // as soon as we use a second register.
27544 return AM.Scale != 0;
27548 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27549 // Integer division on x86 is expensive. However, when aggressively optimizing
27550 // for code size, we prefer to use a div instruction, as it is usually smaller
27551 // than the alternative sequence.
27552 // The exception to this is vector division. Since x86 doesn't have vector
27553 // integer division, leaving the division as-is is a loss even in terms of
27554 // size, because it will have to be scalarized, while the alternative code
27555 // sequence can be performed in vector form.
27556 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27557 Attribute::MinSize);
27558 return OptSize && !VT.isVector();